1 /* SuperH Ethernet device driver
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/clk.h>
44 #include <linux/sh_eth.h>
45 #include <linux/of_mdio.h>
49 #define SH_ETH_DEF_MSG_ENABLE \
55 #define SH_ETH_OFFSET_INVALID ((u16)~0)
57 #define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
61 SH_ETH_OFFSET_DEFAULTS,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
158 SH_ETH_OFFSET_DEFAULTS,
203 [TSU_CTRST] = 0x0004,
204 [TSU_FWSLC] = 0x0038,
205 [TSU_VTAG0] = 0x0058,
206 [TSU_ADSBSY] = 0x0060,
208 [TSU_POST1] = 0x0070,
209 [TSU_POST2] = 0x0074,
210 [TSU_POST3] = 0x0078,
211 [TSU_POST4] = 0x007c,
212 [TSU_ADRH0] = 0x0100,
220 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
221 SH_ETH_OFFSET_DEFAULTS,
268 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
269 SH_ETH_OFFSET_DEFAULTS,
322 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
323 SH_ETH_OFFSET_DEFAULTS,
371 [TSU_CTRST] = 0x0004,
372 [TSU_FWEN0] = 0x0010,
373 [TSU_FWEN1] = 0x0014,
375 [TSU_BSYSL0] = 0x0020,
376 [TSU_BSYSL1] = 0x0024,
377 [TSU_PRISL0] = 0x0028,
378 [TSU_PRISL1] = 0x002c,
379 [TSU_FWSL0] = 0x0030,
380 [TSU_FWSL1] = 0x0034,
381 [TSU_FWSLC] = 0x0038,
382 [TSU_QTAGM0] = 0x0040,
383 [TSU_QTAGM1] = 0x0044,
384 [TSU_ADQT0] = 0x0048,
385 [TSU_ADQT1] = 0x004c,
387 [TSU_FWINMK] = 0x0054,
388 [TSU_ADSBSY] = 0x0060,
390 [TSU_POST1] = 0x0070,
391 [TSU_POST2] = 0x0074,
392 [TSU_POST3] = 0x0078,
393 [TSU_POST4] = 0x007c,
408 [TSU_ADRH0] = 0x0100,
411 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
412 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
414 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
416 struct sh_eth_private *mdp = netdev_priv(ndev);
417 u16 offset = mdp->reg_offset[enum_index];
419 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
422 iowrite32(data, mdp->addr + offset);
425 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
427 struct sh_eth_private *mdp = netdev_priv(ndev);
428 u16 offset = mdp->reg_offset[enum_index];
430 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
433 return ioread32(mdp->addr + offset);
436 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
439 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
443 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
445 return mdp->reg_offset == sh_eth_offset_gigabit;
448 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
450 return mdp->reg_offset == sh_eth_offset_fast_rz;
453 static void sh_eth_select_mii(struct net_device *ndev)
455 struct sh_eth_private *mdp = netdev_priv(ndev);
458 switch (mdp->phy_interface) {
459 case PHY_INTERFACE_MODE_GMII:
462 case PHY_INTERFACE_MODE_MII:
465 case PHY_INTERFACE_MODE_RMII:
470 "PHY interface mode was not setup. Set to MII.\n");
475 sh_eth_write(ndev, value, RMII_MII);
478 static void sh_eth_set_duplex(struct net_device *ndev)
480 struct sh_eth_private *mdp = netdev_priv(ndev);
482 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
485 static void sh_eth_chip_reset(struct net_device *ndev)
487 struct sh_eth_private *mdp = netdev_priv(ndev);
490 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
494 static void sh_eth_set_rate_gether(struct net_device *ndev)
496 struct sh_eth_private *mdp = netdev_priv(ndev);
498 switch (mdp->speed) {
499 case 10: /* 10BASE */
500 sh_eth_write(ndev, GECMR_10, GECMR);
502 case 100:/* 100BASE */
503 sh_eth_write(ndev, GECMR_100, GECMR);
505 case 1000: /* 1000BASE */
506 sh_eth_write(ndev, GECMR_1000, GECMR);
513 static struct sh_eth_cpu_data r7s72100_data = {
514 .chip_reset = sh_eth_chip_reset,
515 .set_duplex = sh_eth_set_duplex,
517 .register_type = SH_ETH_REG_FAST_RZ,
519 .ecsr_value = ECSR_ICD,
520 .ecsipr_value = ECSIPR_ICDIP,
521 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
522 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
524 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
525 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
526 EESIPR_RMAFIP | EESIPR_RRFIP |
527 EESIPR_RTLFIP | EESIPR_RTSFIP |
528 EESIPR_PREIP | EESIPR_CERFIP,
530 .tx_check = EESR_TC1 | EESR_FTC,
531 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
532 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
534 .fdr_value = 0x0000070f,
536 .trscer_err_mask = DESC_I_RINT8 | DESC_I_RINT5,
544 .rpadir_value = 2 << 16,
551 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
553 sh_eth_chip_reset(ndev);
555 sh_eth_select_mii(ndev);
559 static struct sh_eth_cpu_data r8a7740_data = {
560 .chip_reset = sh_eth_chip_reset_r8a7740,
561 .set_duplex = sh_eth_set_duplex,
562 .set_rate = sh_eth_set_rate_gether,
564 .register_type = SH_ETH_REG_GIGABIT,
566 .ecsr_value = ECSR_ICD | ECSR_MPD,
567 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
568 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
569 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
570 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
571 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
572 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
573 EESIPR_CEEFIP | EESIPR_CELFIP |
574 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
575 EESIPR_PREIP | EESIPR_CERFIP,
577 .tx_check = EESR_TC1 | EESR_FTC,
578 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
579 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
581 .fdr_value = 0x0000070f,
589 .rpadir_value = 2 << 16,
598 /* There is CPU dependent code */
599 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
601 struct sh_eth_private *mdp = netdev_priv(ndev);
603 switch (mdp->speed) {
604 case 10: /* 10BASE */
605 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
607 case 100:/* 100BASE */
608 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
614 static struct sh_eth_cpu_data r8a777x_data = {
615 .set_duplex = sh_eth_set_duplex,
616 .set_rate = sh_eth_set_rate_r8a777x,
618 .register_type = SH_ETH_REG_FAST_RCAR,
620 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
621 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
622 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
623 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
624 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
625 EESIPR_RMAFIP | EESIPR_RRFIP |
626 EESIPR_RTLFIP | EESIPR_RTSFIP |
627 EESIPR_PREIP | EESIPR_CERFIP,
629 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
630 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
631 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
632 .fdr_value = 0x00000f0f,
641 static struct sh_eth_cpu_data r8a779x_data = {
642 .set_duplex = sh_eth_set_duplex,
643 .set_rate = sh_eth_set_rate_r8a777x,
645 .register_type = SH_ETH_REG_FAST_RCAR,
647 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
648 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
650 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
651 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
652 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
653 EESIPR_RMAFIP | EESIPR_RRFIP |
654 EESIPR_RTLFIP | EESIPR_RTSFIP |
655 EESIPR_PREIP | EESIPR_CERFIP,
657 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
658 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
659 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
660 .fdr_value = 0x00000f0f,
662 .trscer_err_mask = DESC_I_RINT8,
671 #endif /* CONFIG_OF */
673 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
675 struct sh_eth_private *mdp = netdev_priv(ndev);
677 switch (mdp->speed) {
678 case 10: /* 10BASE */
679 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
681 case 100:/* 100BASE */
682 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
688 static struct sh_eth_cpu_data sh7724_data = {
689 .set_duplex = sh_eth_set_duplex,
690 .set_rate = sh_eth_set_rate_sh7724,
692 .register_type = SH_ETH_REG_FAST_SH4,
694 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
695 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
696 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
697 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
698 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
699 EESIPR_RMAFIP | EESIPR_RRFIP |
700 EESIPR_RTLFIP | EESIPR_RTSFIP |
701 EESIPR_PREIP | EESIPR_CERFIP,
703 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
704 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
705 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
712 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
715 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
717 struct sh_eth_private *mdp = netdev_priv(ndev);
719 switch (mdp->speed) {
720 case 10: /* 10BASE */
721 sh_eth_write(ndev, 0, RTRATE);
723 case 100:/* 100BASE */
724 sh_eth_write(ndev, 1, RTRATE);
730 static struct sh_eth_cpu_data sh7757_data = {
731 .set_duplex = sh_eth_set_duplex,
732 .set_rate = sh_eth_set_rate_sh7757,
734 .register_type = SH_ETH_REG_FAST_SH4,
736 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
737 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
738 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
739 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
740 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
741 EESIPR_CEEFIP | EESIPR_CELFIP |
742 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
743 EESIPR_PREIP | EESIPR_CERFIP,
745 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
746 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
747 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
749 .irq_flags = IRQF_SHARED,
756 .rpadir_value = 2 << 16,
761 #define SH_GIGA_ETH_BASE 0xfee00000UL
762 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
763 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
764 static void sh_eth_chip_reset_giga(struct net_device *ndev)
766 u32 mahr[2], malr[2];
769 /* save MAHR and MALR */
770 for (i = 0; i < 2; i++) {
771 malr[i] = ioread32((void *)GIGA_MALR(i));
772 mahr[i] = ioread32((void *)GIGA_MAHR(i));
775 sh_eth_chip_reset(ndev);
777 /* restore MAHR and MALR */
778 for (i = 0; i < 2; i++) {
779 iowrite32(malr[i], (void *)GIGA_MALR(i));
780 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
784 static void sh_eth_set_rate_giga(struct net_device *ndev)
786 struct sh_eth_private *mdp = netdev_priv(ndev);
788 switch (mdp->speed) {
789 case 10: /* 10BASE */
790 sh_eth_write(ndev, 0x00000000, GECMR);
792 case 100:/* 100BASE */
793 sh_eth_write(ndev, 0x00000010, GECMR);
795 case 1000: /* 1000BASE */
796 sh_eth_write(ndev, 0x00000020, GECMR);
801 /* SH7757(GETHERC) */
802 static struct sh_eth_cpu_data sh7757_data_giga = {
803 .chip_reset = sh_eth_chip_reset_giga,
804 .set_duplex = sh_eth_set_duplex,
805 .set_rate = sh_eth_set_rate_giga,
807 .register_type = SH_ETH_REG_GIGABIT,
809 .ecsr_value = ECSR_ICD | ECSR_MPD,
810 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
811 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
812 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
813 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
814 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
815 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
816 EESIPR_CEEFIP | EESIPR_CELFIP |
817 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
818 EESIPR_PREIP | EESIPR_CERFIP,
820 .tx_check = EESR_TC1 | EESR_FTC,
821 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
822 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
824 .fdr_value = 0x0000072f,
826 .irq_flags = IRQF_SHARED,
833 .rpadir_value = 2 << 16,
841 static struct sh_eth_cpu_data sh7734_data = {
842 .chip_reset = sh_eth_chip_reset,
843 .set_duplex = sh_eth_set_duplex,
844 .set_rate = sh_eth_set_rate_gether,
846 .register_type = SH_ETH_REG_GIGABIT,
848 .ecsr_value = ECSR_ICD | ECSR_MPD,
849 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
850 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
851 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
852 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
853 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
854 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
855 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
856 EESIPR_PREIP | EESIPR_CERFIP,
858 .tx_check = EESR_TC1 | EESR_FTC,
859 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
860 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
877 static struct sh_eth_cpu_data sh7763_data = {
878 .chip_reset = sh_eth_chip_reset,
879 .set_duplex = sh_eth_set_duplex,
880 .set_rate = sh_eth_set_rate_gether,
882 .register_type = SH_ETH_REG_GIGABIT,
884 .ecsr_value = ECSR_ICD | ECSR_MPD,
885 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
886 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
887 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
888 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
889 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
890 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
891 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
892 EESIPR_PREIP | EESIPR_CERFIP,
894 .tx_check = EESR_TC1 | EESR_FTC,
895 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
896 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
906 .irq_flags = IRQF_SHARED,
911 static struct sh_eth_cpu_data sh7619_data = {
912 .register_type = SH_ETH_REG_FAST_SH3_SH2,
914 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
915 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
916 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
917 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
918 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
919 EESIPR_CEEFIP | EESIPR_CELFIP |
920 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
921 EESIPR_PREIP | EESIPR_CERFIP,
929 static struct sh_eth_cpu_data sh771x_data = {
930 .register_type = SH_ETH_REG_FAST_SH3_SH2,
932 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
933 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
934 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
935 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
936 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
937 EESIPR_CEEFIP | EESIPR_CELFIP |
938 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
939 EESIPR_PREIP | EESIPR_CERFIP,
941 .trscer_err_mask = DESC_I_RINT8,
947 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
950 cd->ecsr_value = DEFAULT_ECSR_INIT;
952 if (!cd->ecsipr_value)
953 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
955 if (!cd->fcftr_value)
956 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
957 DEFAULT_FIFO_F_D_RFD;
960 cd->fdr_value = DEFAULT_FDR_INIT;
963 cd->tx_check = DEFAULT_TX_CHECK;
965 if (!cd->eesr_err_check)
966 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
968 if (!cd->trscer_err_mask)
969 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
972 static int sh_eth_check_reset(struct net_device *ndev)
978 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
984 netdev_err(ndev, "Device reset failed\n");
990 static int sh_eth_reset(struct net_device *ndev)
992 struct sh_eth_private *mdp = netdev_priv(ndev);
995 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
996 sh_eth_write(ndev, EDSR_ENALL, EDSR);
997 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
999 ret = sh_eth_check_reset(ndev);
1004 sh_eth_write(ndev, 0x0, TDLAR);
1005 sh_eth_write(ndev, 0x0, TDFAR);
1006 sh_eth_write(ndev, 0x0, TDFXR);
1007 sh_eth_write(ndev, 0x0, TDFFR);
1008 sh_eth_write(ndev, 0x0, RDLAR);
1009 sh_eth_write(ndev, 0x0, RDFAR);
1010 sh_eth_write(ndev, 0x0, RDFXR);
1011 sh_eth_write(ndev, 0x0, RDFFR);
1013 /* Reset HW CRC register */
1014 if (mdp->cd->hw_checksum)
1015 sh_eth_write(ndev, 0x0, CSMR);
1017 /* Select MII mode */
1018 if (mdp->cd->select_mii)
1019 sh_eth_select_mii(ndev);
1021 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
1023 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
1029 static void sh_eth_set_receive_align(struct sk_buff *skb)
1031 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1034 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1037 /* Program the hardware MAC address from dev->dev_addr. */
1038 static void update_mac_address(struct net_device *ndev)
1041 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1042 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1044 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1047 /* Get MAC address from SuperH MAC address register
1049 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1050 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1051 * When you want use this device, you must set MAC address in bootloader.
1054 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1056 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1057 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1059 u32 mahr = sh_eth_read(ndev, MAHR);
1060 u32 malr = sh_eth_read(ndev, MALR);
1062 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1063 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1064 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1065 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1066 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1067 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
1071 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
1073 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
1074 return EDTRR_TRNS_GETHER;
1076 return EDTRR_TRNS_ETHER;
1080 void (*set_gate)(void *addr);
1081 struct mdiobb_ctrl ctrl;
1085 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1087 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1090 if (bitbang->set_gate)
1091 bitbang->set_gate(bitbang->addr);
1093 pir = ioread32(bitbang->addr);
1098 iowrite32(pir, bitbang->addr);
1101 /* Data I/O pin control */
1102 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1104 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1108 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1110 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1114 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1116 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1118 if (bitbang->set_gate)
1119 bitbang->set_gate(bitbang->addr);
1121 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1124 /* MDC pin control */
1125 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1127 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1130 /* mdio bus control struct */
1131 static struct mdiobb_ops bb_ops = {
1132 .owner = THIS_MODULE,
1133 .set_mdc = sh_mdc_ctrl,
1134 .set_mdio_dir = sh_mmd_ctrl,
1135 .set_mdio_data = sh_set_mdio,
1136 .get_mdio_data = sh_get_mdio,
1139 /* free Tx skb function */
1140 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1142 struct sh_eth_private *mdp = netdev_priv(ndev);
1143 struct sh_eth_txdesc *txdesc;
1148 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1149 entry = mdp->dirty_tx % mdp->num_tx_ring;
1150 txdesc = &mdp->tx_ring[entry];
1151 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1152 if (sent_only && !sent)
1154 /* TACT bit must be checked before all the following reads */
1156 netif_info(mdp, tx_done, ndev,
1157 "tx entry %d status 0x%08x\n",
1158 entry, le32_to_cpu(txdesc->status));
1159 /* Free the original skb. */
1160 if (mdp->tx_skbuff[entry]) {
1161 dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1162 le32_to_cpu(txdesc->len) >> 16,
1164 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1165 mdp->tx_skbuff[entry] = NULL;
1168 txdesc->status = cpu_to_le32(TD_TFP);
1169 if (entry >= mdp->num_tx_ring - 1)
1170 txdesc->status |= cpu_to_le32(TD_TDLE);
1173 ndev->stats.tx_packets++;
1174 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1180 /* free skb and descriptor buffer */
1181 static void sh_eth_ring_free(struct net_device *ndev)
1183 struct sh_eth_private *mdp = netdev_priv(ndev);
1187 for (i = 0; i < mdp->num_rx_ring; i++) {
1188 if (mdp->rx_skbuff[i]) {
1189 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1191 dma_unmap_single(&ndev->dev,
1192 le32_to_cpu(rxdesc->addr),
1193 ALIGN(mdp->rx_buf_sz, 32),
1197 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1198 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1200 mdp->rx_ring = NULL;
1203 /* Free Rx skb ringbuffer */
1204 if (mdp->rx_skbuff) {
1205 for (i = 0; i < mdp->num_rx_ring; i++)
1206 dev_kfree_skb(mdp->rx_skbuff[i]);
1208 kfree(mdp->rx_skbuff);
1209 mdp->rx_skbuff = NULL;
1212 sh_eth_tx_free(ndev, false);
1214 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1215 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1217 mdp->tx_ring = NULL;
1220 /* Free Tx skb ringbuffer */
1221 kfree(mdp->tx_skbuff);
1222 mdp->tx_skbuff = NULL;
1225 /* format skb and descriptor buffer */
1226 static void sh_eth_ring_format(struct net_device *ndev)
1228 struct sh_eth_private *mdp = netdev_priv(ndev);
1230 struct sk_buff *skb;
1231 struct sh_eth_rxdesc *rxdesc = NULL;
1232 struct sh_eth_txdesc *txdesc = NULL;
1233 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1234 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1235 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1236 dma_addr_t dma_addr;
1244 memset(mdp->rx_ring, 0, rx_ringsize);
1246 /* build Rx ring buffer */
1247 for (i = 0; i < mdp->num_rx_ring; i++) {
1249 mdp->rx_skbuff[i] = NULL;
1250 skb = netdev_alloc_skb(ndev, skbuff_size);
1253 sh_eth_set_receive_align(skb);
1255 /* The size of the buffer is a multiple of 32 bytes. */
1256 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1257 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1259 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1263 mdp->rx_skbuff[i] = skb;
1266 rxdesc = &mdp->rx_ring[i];
1267 rxdesc->len = cpu_to_le32(buf_len << 16);
1268 rxdesc->addr = cpu_to_le32(dma_addr);
1269 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1271 /* Rx descriptor address set */
1273 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1274 if (sh_eth_is_gether(mdp) ||
1275 sh_eth_is_rz_fast_ether(mdp))
1276 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1280 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1282 /* Mark the last entry as wrapping the ring. */
1284 rxdesc->status |= cpu_to_le32(RD_RDLE);
1286 memset(mdp->tx_ring, 0, tx_ringsize);
1288 /* build Tx ring buffer */
1289 for (i = 0; i < mdp->num_tx_ring; i++) {
1290 mdp->tx_skbuff[i] = NULL;
1291 txdesc = &mdp->tx_ring[i];
1292 txdesc->status = cpu_to_le32(TD_TFP);
1293 txdesc->len = cpu_to_le32(0);
1295 /* Tx descriptor address set */
1296 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1297 if (sh_eth_is_gether(mdp) ||
1298 sh_eth_is_rz_fast_ether(mdp))
1299 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1303 txdesc->status |= cpu_to_le32(TD_TDLE);
1306 /* Get skb and descriptor buffer */
1307 static int sh_eth_ring_init(struct net_device *ndev)
1309 struct sh_eth_private *mdp = netdev_priv(ndev);
1310 int rx_ringsize, tx_ringsize;
1312 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1313 * card needs room to do 8 byte alignment, +2 so we can reserve
1314 * the first 2 bytes, and +16 gets room for the status word from the
1317 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1318 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1319 if (mdp->cd->rpadir)
1320 mdp->rx_buf_sz += NET_IP_ALIGN;
1322 /* Allocate RX and TX skb rings */
1323 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1325 if (!mdp->rx_skbuff)
1328 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1330 if (!mdp->tx_skbuff)
1333 /* Allocate all Rx descriptors. */
1334 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1335 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1342 /* Allocate all Tx descriptors. */
1343 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1344 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1351 /* Free Rx and Tx skb ring buffer and DMA buffer */
1352 sh_eth_ring_free(ndev);
1357 static int sh_eth_dev_init(struct net_device *ndev)
1359 struct sh_eth_private *mdp = netdev_priv(ndev);
1363 ret = sh_eth_reset(ndev);
1367 if (mdp->cd->rmiimode)
1368 sh_eth_write(ndev, 0x1, RMIIMODE);
1370 /* Descriptor format */
1371 sh_eth_ring_format(ndev);
1372 if (mdp->cd->rpadir)
1373 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1375 /* all sh_eth int mask */
1376 sh_eth_write(ndev, 0, EESIPR);
1378 #if defined(__LITTLE_ENDIAN)
1379 if (mdp->cd->hw_swap)
1380 sh_eth_write(ndev, EDMR_EL, EDMR);
1383 sh_eth_write(ndev, 0, EDMR);
1386 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1387 sh_eth_write(ndev, 0, TFTR);
1389 /* Frame recv control (enable multiple-packets per rx irq) */
1390 sh_eth_write(ndev, RMCR_RNC, RMCR);
1392 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1395 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1397 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1399 if (!mdp->cd->no_trimd)
1400 sh_eth_write(ndev, 0, TRIMD);
1402 /* Recv frame limit set register */
1403 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1406 sh_eth_modify(ndev, EESR, 0, 0);
1407 mdp->irq_enabled = true;
1408 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1410 /* PAUSE Prohibition */
1411 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1412 ECMR_TE | ECMR_RE, ECMR);
1414 if (mdp->cd->set_rate)
1415 mdp->cd->set_rate(ndev);
1417 /* E-MAC Status Register clear */
1418 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1420 /* E-MAC Interrupt Enable register */
1421 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1423 /* Set MAC address */
1424 update_mac_address(ndev);
1428 sh_eth_write(ndev, APR_AP, APR);
1430 sh_eth_write(ndev, MPR_MP, MPR);
1431 if (mdp->cd->tpauser)
1432 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1434 /* Setting the Rx mode will start the Rx process. */
1435 sh_eth_write(ndev, EDRRR_R, EDRRR);
1440 static void sh_eth_dev_exit(struct net_device *ndev)
1442 struct sh_eth_private *mdp = netdev_priv(ndev);
1445 /* Deactivate all TX descriptors, so DMA should stop at next
1446 * packet boundary if it's currently running
1448 for (i = 0; i < mdp->num_tx_ring; i++)
1449 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1451 /* Disable TX FIFO egress to MAC */
1452 sh_eth_rcv_snd_disable(ndev);
1454 /* Stop RX DMA at next packet boundary */
1455 sh_eth_write(ndev, 0, EDRRR);
1457 /* Aside from TX DMA, we can't tell when the hardware is
1458 * really stopped, so we need to reset to make sure.
1459 * Before doing that, wait for long enough to *probably*
1460 * finish transmitting the last packet and poll stats.
1462 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1463 sh_eth_get_stats(ndev);
1466 /* Set the RMII mode again if required */
1467 if (mdp->cd->rmiimode)
1468 sh_eth_write(ndev, 0x1, RMIIMODE);
1470 /* Set MAC address again */
1471 update_mac_address(ndev);
1474 /* Packet receive function */
1475 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1477 struct sh_eth_private *mdp = netdev_priv(ndev);
1478 struct sh_eth_rxdesc *rxdesc;
1480 int entry = mdp->cur_rx % mdp->num_rx_ring;
1481 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1483 struct sk_buff *skb;
1485 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1486 dma_addr_t dma_addr;
1490 boguscnt = min(boguscnt, *quota);
1492 rxdesc = &mdp->rx_ring[entry];
1493 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1494 /* RACT bit must be checked before all the following reads */
1496 desc_status = le32_to_cpu(rxdesc->status);
1497 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1502 netif_info(mdp, rx_status, ndev,
1503 "rx entry %d status 0x%08x len %d\n",
1504 entry, desc_status, pkt_len);
1506 if (!(desc_status & RDFEND))
1507 ndev->stats.rx_length_errors++;
1509 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1510 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1511 * bit 0. However, in case of the R8A7740 and R7S72100
1512 * the RFS bits are from bit 25 to bit 16. So, the
1513 * driver needs right shifting by 16.
1515 if (mdp->cd->hw_checksum)
1518 skb = mdp->rx_skbuff[entry];
1519 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1520 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1521 ndev->stats.rx_errors++;
1522 if (desc_status & RD_RFS1)
1523 ndev->stats.rx_crc_errors++;
1524 if (desc_status & RD_RFS2)
1525 ndev->stats.rx_frame_errors++;
1526 if (desc_status & RD_RFS3)
1527 ndev->stats.rx_length_errors++;
1528 if (desc_status & RD_RFS4)
1529 ndev->stats.rx_length_errors++;
1530 if (desc_status & RD_RFS6)
1531 ndev->stats.rx_missed_errors++;
1532 if (desc_status & RD_RFS10)
1533 ndev->stats.rx_over_errors++;
1535 dma_addr = le32_to_cpu(rxdesc->addr);
1536 if (!mdp->cd->hw_swap)
1538 phys_to_virt(ALIGN(dma_addr, 4)),
1540 mdp->rx_skbuff[entry] = NULL;
1541 if (mdp->cd->rpadir)
1542 skb_reserve(skb, NET_IP_ALIGN);
1543 dma_unmap_single(&ndev->dev, dma_addr,
1544 ALIGN(mdp->rx_buf_sz, 32),
1546 skb_put(skb, pkt_len);
1547 skb->protocol = eth_type_trans(skb, ndev);
1548 netif_receive_skb(skb);
1549 ndev->stats.rx_packets++;
1550 ndev->stats.rx_bytes += pkt_len;
1551 if (desc_status & RD_RFS8)
1552 ndev->stats.multicast++;
1554 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1555 rxdesc = &mdp->rx_ring[entry];
1558 /* Refill the Rx ring buffers. */
1559 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1560 entry = mdp->dirty_rx % mdp->num_rx_ring;
1561 rxdesc = &mdp->rx_ring[entry];
1562 /* The size of the buffer is 32 byte boundary. */
1563 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1564 rxdesc->len = cpu_to_le32(buf_len << 16);
1566 if (mdp->rx_skbuff[entry] == NULL) {
1567 skb = netdev_alloc_skb(ndev, skbuff_size);
1569 break; /* Better luck next round. */
1570 sh_eth_set_receive_align(skb);
1571 dma_addr = dma_map_single(&ndev->dev, skb->data,
1572 buf_len, DMA_FROM_DEVICE);
1573 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1577 mdp->rx_skbuff[entry] = skb;
1579 skb_checksum_none_assert(skb);
1580 rxdesc->addr = cpu_to_le32(dma_addr);
1582 dma_wmb(); /* RACT bit must be set after all the above writes */
1583 if (entry >= mdp->num_rx_ring - 1)
1585 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1587 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1590 /* Restart Rx engine if stopped. */
1591 /* If we don't need to check status, don't. -KDU */
1592 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1593 /* fix the values for the next receiving if RDE is set */
1594 if (intr_status & EESR_RDE &&
1595 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1596 u32 count = (sh_eth_read(ndev, RDFAR) -
1597 sh_eth_read(ndev, RDLAR)) >> 4;
1599 mdp->cur_rx = count;
1600 mdp->dirty_rx = count;
1602 sh_eth_write(ndev, EDRRR_R, EDRRR);
1605 *quota -= limit - boguscnt - 1;
1610 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1612 /* disable tx and rx */
1613 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1616 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1618 /* enable tx and rx */
1619 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1622 /* E-MAC interrupt handler */
1623 static void sh_eth_emac_interrupt(struct net_device *ndev)
1625 struct sh_eth_private *mdp = netdev_priv(ndev);
1629 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1630 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1631 if (felic_stat & ECSR_ICD)
1632 ndev->stats.tx_carrier_errors++;
1633 if (felic_stat & ECSR_MPD)
1634 pm_wakeup_event(&mdp->pdev->dev, 0);
1635 if (felic_stat & ECSR_LCHNG) {
1637 if (mdp->cd->no_psr || mdp->no_ether_link)
1639 link_stat = sh_eth_read(ndev, PSR);
1640 if (mdp->ether_link_active_low)
1641 link_stat = ~link_stat;
1642 if (!(link_stat & PHY_ST_LINK)) {
1643 sh_eth_rcv_snd_disable(ndev);
1646 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1648 sh_eth_modify(ndev, ECSR, 0, 0);
1649 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1650 /* enable tx and rx */
1651 sh_eth_rcv_snd_enable(ndev);
1656 /* error control function */
1657 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1659 struct sh_eth_private *mdp = netdev_priv(ndev);
1662 if (intr_status & EESR_TWB) {
1663 /* Unused write back interrupt */
1664 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1665 ndev->stats.tx_aborted_errors++;
1666 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1670 if (intr_status & EESR_RABT) {
1671 /* Receive Abort int */
1672 if (intr_status & EESR_RFRMER) {
1673 /* Receive Frame Overflow int */
1674 ndev->stats.rx_frame_errors++;
1678 if (intr_status & EESR_TDE) {
1679 /* Transmit Descriptor Empty int */
1680 ndev->stats.tx_fifo_errors++;
1681 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1684 if (intr_status & EESR_TFE) {
1685 /* FIFO under flow */
1686 ndev->stats.tx_fifo_errors++;
1687 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1690 if (intr_status & EESR_RDE) {
1691 /* Receive Descriptor Empty int */
1692 ndev->stats.rx_over_errors++;
1695 if (intr_status & EESR_RFE) {
1696 /* Receive FIFO Overflow int */
1697 ndev->stats.rx_fifo_errors++;
1700 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1702 ndev->stats.tx_fifo_errors++;
1703 netif_err(mdp, tx_err, ndev, "Address Error\n");
1706 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1707 if (mdp->cd->no_ade)
1709 if (intr_status & mask) {
1711 u32 edtrr = sh_eth_read(ndev, EDTRR);
1714 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1715 intr_status, mdp->cur_tx, mdp->dirty_tx,
1716 (u32)ndev->state, edtrr);
1717 /* dirty buffer free */
1718 sh_eth_tx_free(ndev, true);
1721 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1723 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1726 netif_wake_queue(ndev);
1730 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1732 struct net_device *ndev = netdev;
1733 struct sh_eth_private *mdp = netdev_priv(ndev);
1734 struct sh_eth_cpu_data *cd = mdp->cd;
1735 irqreturn_t ret = IRQ_NONE;
1736 u32 intr_status, intr_enable;
1738 spin_lock(&mdp->lock);
1740 /* Get interrupt status */
1741 intr_status = sh_eth_read(ndev, EESR);
1742 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1743 * enabled since it's the one that comes thru regardless of the mask,
1744 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1745 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1748 intr_enable = sh_eth_read(ndev, EESIPR);
1749 intr_status &= intr_enable | EESIPR_ECIIP;
1750 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1751 cd->eesr_err_check))
1756 if (unlikely(!mdp->irq_enabled)) {
1757 sh_eth_write(ndev, 0, EESIPR);
1761 if (intr_status & EESR_RX_CHECK) {
1762 if (napi_schedule_prep(&mdp->napi)) {
1763 /* Mask Rx interrupts */
1764 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1766 __napi_schedule(&mdp->napi);
1769 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1770 intr_status, intr_enable);
1775 if (intr_status & cd->tx_check) {
1776 /* Clear Tx interrupts */
1777 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1779 sh_eth_tx_free(ndev, true);
1780 netif_wake_queue(ndev);
1783 /* E-MAC interrupt */
1784 if (intr_status & EESR_ECI)
1785 sh_eth_emac_interrupt(ndev);
1787 if (intr_status & cd->eesr_err_check) {
1788 /* Clear error interrupts */
1789 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1791 sh_eth_error(ndev, intr_status);
1795 spin_unlock(&mdp->lock);
1800 static int sh_eth_poll(struct napi_struct *napi, int budget)
1802 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1804 struct net_device *ndev = napi->dev;
1809 intr_status = sh_eth_read(ndev, EESR);
1810 if (!(intr_status & EESR_RX_CHECK))
1812 /* Clear Rx interrupts */
1813 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1815 if (sh_eth_rx(ndev, intr_status, "a))
1819 napi_complete(napi);
1821 /* Reenable Rx interrupts */
1822 if (mdp->irq_enabled)
1823 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1825 return budget - quota;
1828 /* PHY state control function */
1829 static void sh_eth_adjust_link(struct net_device *ndev)
1831 struct sh_eth_private *mdp = netdev_priv(ndev);
1832 struct phy_device *phydev = ndev->phydev;
1833 unsigned long flags;
1836 spin_lock_irqsave(&mdp->lock, flags);
1838 /* Disable TX and RX right over here, if E-MAC change is ignored */
1839 if (mdp->cd->no_psr || mdp->no_ether_link)
1840 sh_eth_rcv_snd_disable(ndev);
1843 if (phydev->duplex != mdp->duplex) {
1845 mdp->duplex = phydev->duplex;
1846 if (mdp->cd->set_duplex)
1847 mdp->cd->set_duplex(ndev);
1850 if (phydev->speed != mdp->speed) {
1852 mdp->speed = phydev->speed;
1853 if (mdp->cd->set_rate)
1854 mdp->cd->set_rate(ndev);
1857 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1859 mdp->link = phydev->link;
1861 } else if (mdp->link) {
1868 /* Enable TX and RX right over here, if E-MAC change is ignored */
1869 if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link)
1870 sh_eth_rcv_snd_enable(ndev);
1873 spin_unlock_irqrestore(&mdp->lock, flags);
1875 if (new_state && netif_msg_link(mdp))
1876 phy_print_status(phydev);
1879 /* PHY init function */
1880 static int sh_eth_phy_init(struct net_device *ndev)
1882 struct device_node *np = ndev->dev.parent->of_node;
1883 struct sh_eth_private *mdp = netdev_priv(ndev);
1884 struct phy_device *phydev;
1890 /* Try connect to PHY */
1892 struct device_node *pn;
1894 pn = of_parse_phandle(np, "phy-handle", 0);
1895 phydev = of_phy_connect(ndev, pn,
1896 sh_eth_adjust_link, 0,
1897 mdp->phy_interface);
1901 phydev = ERR_PTR(-ENOENT);
1903 char phy_id[MII_BUS_ID_SIZE + 3];
1905 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1906 mdp->mii_bus->id, mdp->phy_id);
1908 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1909 mdp->phy_interface);
1912 if (IS_ERR(phydev)) {
1913 netdev_err(ndev, "failed to connect PHY\n");
1914 return PTR_ERR(phydev);
1917 phy_attached_info(phydev);
1922 /* PHY control start function */
1923 static int sh_eth_phy_start(struct net_device *ndev)
1927 ret = sh_eth_phy_init(ndev);
1931 phy_start(ndev->phydev);
1936 static int sh_eth_get_link_ksettings(struct net_device *ndev,
1937 struct ethtool_link_ksettings *cmd)
1939 struct sh_eth_private *mdp = netdev_priv(ndev);
1940 unsigned long flags;
1945 spin_lock_irqsave(&mdp->lock, flags);
1946 phy_ethtool_ksettings_get(ndev->phydev, cmd);
1947 spin_unlock_irqrestore(&mdp->lock, flags);
1952 static int sh_eth_set_link_ksettings(struct net_device *ndev,
1953 const struct ethtool_link_ksettings *cmd)
1958 return phy_ethtool_ksettings_set(ndev->phydev, cmd);
1961 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1962 * version must be bumped as well. Just adding registers up to that
1963 * limit is fine, as long as the existing register indices don't
1966 #define SH_ETH_REG_DUMP_VERSION 1
1967 #define SH_ETH_REG_DUMP_MAX_REGS 256
1969 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1971 struct sh_eth_private *mdp = netdev_priv(ndev);
1972 struct sh_eth_cpu_data *cd = mdp->cd;
1976 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1978 /* Dump starts with a bitmap that tells ethtool which
1979 * registers are defined for this chip.
1981 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1989 /* Add a register to the dump, if it has a defined offset.
1990 * This automatically skips most undefined registers, but for
1991 * some it is also necessary to check a capability flag in
1992 * struct sh_eth_cpu_data.
1994 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1995 #define add_reg_from(reg, read_expr) do { \
1996 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1998 mark_reg_valid(reg); \
1999 *buf++ = read_expr; \
2004 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2005 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2071 if (cd->hw_checksum)
2077 add_tsu_reg(TSU_CTRST);
2078 add_tsu_reg(TSU_FWEN0);
2079 add_tsu_reg(TSU_FWEN1);
2080 add_tsu_reg(TSU_FCM);
2081 add_tsu_reg(TSU_BSYSL0);
2082 add_tsu_reg(TSU_BSYSL1);
2083 add_tsu_reg(TSU_PRISL0);
2084 add_tsu_reg(TSU_PRISL1);
2085 add_tsu_reg(TSU_FWSL0);
2086 add_tsu_reg(TSU_FWSL1);
2087 add_tsu_reg(TSU_FWSLC);
2088 add_tsu_reg(TSU_QTAG0);
2089 add_tsu_reg(TSU_QTAG1);
2090 add_tsu_reg(TSU_QTAGM0);
2091 add_tsu_reg(TSU_QTAGM1);
2092 add_tsu_reg(TSU_FWSR);
2093 add_tsu_reg(TSU_FWINMK);
2094 add_tsu_reg(TSU_ADQT0);
2095 add_tsu_reg(TSU_ADQT1);
2096 add_tsu_reg(TSU_VTAG0);
2097 add_tsu_reg(TSU_VTAG1);
2098 add_tsu_reg(TSU_ADSBSY);
2099 add_tsu_reg(TSU_TEN);
2100 add_tsu_reg(TSU_POST1);
2101 add_tsu_reg(TSU_POST2);
2102 add_tsu_reg(TSU_POST3);
2103 add_tsu_reg(TSU_POST4);
2104 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2105 /* This is the start of a table, not just a single
2111 mark_reg_valid(TSU_ADRH0);
2112 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2115 mdp->reg_offset[TSU_ADRH0] +
2118 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2122 #undef mark_reg_valid
2130 static int sh_eth_get_regs_len(struct net_device *ndev)
2132 return __sh_eth_get_regs(ndev, NULL);
2135 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2138 struct sh_eth_private *mdp = netdev_priv(ndev);
2140 regs->version = SH_ETH_REG_DUMP_VERSION;
2142 pm_runtime_get_sync(&mdp->pdev->dev);
2143 __sh_eth_get_regs(ndev, buf);
2144 pm_runtime_put_sync(&mdp->pdev->dev);
2147 static int sh_eth_nway_reset(struct net_device *ndev)
2152 return phy_start_aneg(ndev->phydev);
2155 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2157 struct sh_eth_private *mdp = netdev_priv(ndev);
2158 return mdp->msg_enable;
2161 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2163 struct sh_eth_private *mdp = netdev_priv(ndev);
2164 mdp->msg_enable = value;
2167 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2168 "rx_current", "tx_current",
2169 "rx_dirty", "tx_dirty",
2171 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2173 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2177 return SH_ETH_STATS_LEN;
2183 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2184 struct ethtool_stats *stats, u64 *data)
2186 struct sh_eth_private *mdp = netdev_priv(ndev);
2189 /* device-specific stats */
2190 data[i++] = mdp->cur_rx;
2191 data[i++] = mdp->cur_tx;
2192 data[i++] = mdp->dirty_rx;
2193 data[i++] = mdp->dirty_tx;
2196 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2198 switch (stringset) {
2200 memcpy(data, sh_eth_gstrings_stats,
2201 sizeof(sh_eth_gstrings_stats));
2206 static void sh_eth_get_ringparam(struct net_device *ndev,
2207 struct ethtool_ringparam *ring)
2209 struct sh_eth_private *mdp = netdev_priv(ndev);
2211 ring->rx_max_pending = RX_RING_MAX;
2212 ring->tx_max_pending = TX_RING_MAX;
2213 ring->rx_pending = mdp->num_rx_ring;
2214 ring->tx_pending = mdp->num_tx_ring;
2217 static int sh_eth_set_ringparam(struct net_device *ndev,
2218 struct ethtool_ringparam *ring)
2220 struct sh_eth_private *mdp = netdev_priv(ndev);
2223 if (ring->tx_pending > TX_RING_MAX ||
2224 ring->rx_pending > RX_RING_MAX ||
2225 ring->tx_pending < TX_RING_MIN ||
2226 ring->rx_pending < RX_RING_MIN)
2228 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2231 if (netif_running(ndev)) {
2232 netif_device_detach(ndev);
2233 netif_tx_disable(ndev);
2235 /* Serialise with the interrupt handler and NAPI, then
2236 * disable interrupts. We have to clear the
2237 * irq_enabled flag first to ensure that interrupts
2238 * won't be re-enabled.
2240 mdp->irq_enabled = false;
2241 synchronize_irq(ndev->irq);
2242 napi_synchronize(&mdp->napi);
2243 sh_eth_write(ndev, 0x0000, EESIPR);
2245 sh_eth_dev_exit(ndev);
2247 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2248 sh_eth_ring_free(ndev);
2251 /* Set new parameters */
2252 mdp->num_rx_ring = ring->rx_pending;
2253 mdp->num_tx_ring = ring->tx_pending;
2255 if (netif_running(ndev)) {
2256 ret = sh_eth_ring_init(ndev);
2258 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2262 ret = sh_eth_dev_init(ndev);
2264 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2269 netif_device_attach(ndev);
2275 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2277 struct sh_eth_private *mdp = netdev_priv(ndev);
2282 if (mdp->cd->magic && mdp->clk) {
2283 wol->supported = WAKE_MAGIC;
2284 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2288 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2290 struct sh_eth_private *mdp = netdev_priv(ndev);
2292 if (!mdp->cd->magic || !mdp->clk || wol->wolopts & ~WAKE_MAGIC)
2295 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2297 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2302 static const struct ethtool_ops sh_eth_ethtool_ops = {
2303 .get_regs_len = sh_eth_get_regs_len,
2304 .get_regs = sh_eth_get_regs,
2305 .nway_reset = sh_eth_nway_reset,
2306 .get_msglevel = sh_eth_get_msglevel,
2307 .set_msglevel = sh_eth_set_msglevel,
2308 .get_link = ethtool_op_get_link,
2309 .get_strings = sh_eth_get_strings,
2310 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2311 .get_sset_count = sh_eth_get_sset_count,
2312 .get_ringparam = sh_eth_get_ringparam,
2313 .set_ringparam = sh_eth_set_ringparam,
2314 .get_link_ksettings = sh_eth_get_link_ksettings,
2315 .set_link_ksettings = sh_eth_set_link_ksettings,
2316 .get_wol = sh_eth_get_wol,
2317 .set_wol = sh_eth_set_wol,
2320 /* network device open function */
2321 static int sh_eth_open(struct net_device *ndev)
2323 struct sh_eth_private *mdp = netdev_priv(ndev);
2326 pm_runtime_get_sync(&mdp->pdev->dev);
2328 napi_enable(&mdp->napi);
2330 ret = request_irq(ndev->irq, sh_eth_interrupt,
2331 mdp->cd->irq_flags, ndev->name, ndev);
2333 netdev_err(ndev, "Can not assign IRQ number\n");
2337 /* Descriptor set */
2338 ret = sh_eth_ring_init(ndev);
2343 ret = sh_eth_dev_init(ndev);
2347 /* PHY control start*/
2348 ret = sh_eth_phy_start(ndev);
2352 netif_start_queue(ndev);
2359 free_irq(ndev->irq, ndev);
2361 napi_disable(&mdp->napi);
2362 pm_runtime_put_sync(&mdp->pdev->dev);
2366 /* Timeout function */
2367 static void sh_eth_tx_timeout(struct net_device *ndev)
2369 struct sh_eth_private *mdp = netdev_priv(ndev);
2370 struct sh_eth_rxdesc *rxdesc;
2373 netif_stop_queue(ndev);
2375 netif_err(mdp, timer, ndev,
2376 "transmit timed out, status %8.8x, resetting...\n",
2377 sh_eth_read(ndev, EESR));
2379 /* tx_errors count up */
2380 ndev->stats.tx_errors++;
2382 /* Free all the skbuffs in the Rx queue. */
2383 for (i = 0; i < mdp->num_rx_ring; i++) {
2384 rxdesc = &mdp->rx_ring[i];
2385 rxdesc->status = cpu_to_le32(0);
2386 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2387 dev_kfree_skb(mdp->rx_skbuff[i]);
2388 mdp->rx_skbuff[i] = NULL;
2390 for (i = 0; i < mdp->num_tx_ring; i++) {
2391 dev_kfree_skb(mdp->tx_skbuff[i]);
2392 mdp->tx_skbuff[i] = NULL;
2396 sh_eth_dev_init(ndev);
2398 netif_start_queue(ndev);
2401 /* Packet transmit function */
2402 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2404 struct sh_eth_private *mdp = netdev_priv(ndev);
2405 struct sh_eth_txdesc *txdesc;
2406 dma_addr_t dma_addr;
2408 unsigned long flags;
2410 spin_lock_irqsave(&mdp->lock, flags);
2411 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2412 if (!sh_eth_tx_free(ndev, true)) {
2413 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2414 netif_stop_queue(ndev);
2415 spin_unlock_irqrestore(&mdp->lock, flags);
2416 return NETDEV_TX_BUSY;
2419 spin_unlock_irqrestore(&mdp->lock, flags);
2421 if (skb_put_padto(skb, ETH_ZLEN))
2422 return NETDEV_TX_OK;
2424 entry = mdp->cur_tx % mdp->num_tx_ring;
2425 mdp->tx_skbuff[entry] = skb;
2426 txdesc = &mdp->tx_ring[entry];
2428 if (!mdp->cd->hw_swap)
2429 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2430 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2432 if (dma_mapping_error(&ndev->dev, dma_addr)) {
2434 return NETDEV_TX_OK;
2436 txdesc->addr = cpu_to_le32(dma_addr);
2437 txdesc->len = cpu_to_le32(skb->len << 16);
2439 dma_wmb(); /* TACT bit must be set after all the above writes */
2440 if (entry >= mdp->num_tx_ring - 1)
2441 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2443 txdesc->status |= cpu_to_le32(TD_TACT);
2445 wmb(); /* cur_tx must be incremented after TACT bit was set */
2448 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2449 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2451 return NETDEV_TX_OK;
2454 /* The statistics registers have write-clear behaviour, which means we
2455 * will lose any increment between the read and write. We mitigate
2456 * this by only clearing when we read a non-zero value, so we will
2457 * never falsely report a total of zero.
2460 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2462 u32 delta = sh_eth_read(ndev, reg);
2466 sh_eth_write(ndev, 0, reg);
2470 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2472 struct sh_eth_private *mdp = netdev_priv(ndev);
2474 if (sh_eth_is_rz_fast_ether(mdp))
2475 return &ndev->stats;
2477 if (!mdp->is_opened)
2478 return &ndev->stats;
2480 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2481 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2482 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2484 if (sh_eth_is_gether(mdp)) {
2485 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2487 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2490 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2494 return &ndev->stats;
2497 /* device close function */
2498 static int sh_eth_close(struct net_device *ndev)
2500 struct sh_eth_private *mdp = netdev_priv(ndev);
2502 netif_stop_queue(ndev);
2504 /* Serialise with the interrupt handler and NAPI, then disable
2505 * interrupts. We have to clear the irq_enabled flag first to
2506 * ensure that interrupts won't be re-enabled.
2508 mdp->irq_enabled = false;
2509 synchronize_irq(ndev->irq);
2510 napi_disable(&mdp->napi);
2511 sh_eth_write(ndev, 0x0000, EESIPR);
2513 sh_eth_dev_exit(ndev);
2515 /* PHY Disconnect */
2517 phy_stop(ndev->phydev);
2518 phy_disconnect(ndev->phydev);
2521 free_irq(ndev->irq, ndev);
2523 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2524 sh_eth_ring_free(ndev);
2528 pm_runtime_put(&mdp->pdev->dev);
2533 /* ioctl to device function */
2534 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2536 struct phy_device *phydev = ndev->phydev;
2538 if (!netif_running(ndev))
2544 return phy_mii_ioctl(phydev, rq, cmd);
2547 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2549 if (netif_running(ndev))
2552 ndev->mtu = new_mtu;
2553 netdev_update_features(ndev);
2558 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2559 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2562 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2565 static u32 sh_eth_tsu_get_post_mask(int entry)
2567 return 0x0f << (28 - ((entry % 8) * 4));
2570 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2572 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2575 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2578 struct sh_eth_private *mdp = netdev_priv(ndev);
2582 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2583 tmp = ioread32(reg_offset);
2584 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2587 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2590 struct sh_eth_private *mdp = netdev_priv(ndev);
2591 u32 post_mask, ref_mask, tmp;
2594 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2595 post_mask = sh_eth_tsu_get_post_mask(entry);
2596 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2598 tmp = ioread32(reg_offset);
2599 iowrite32(tmp & ~post_mask, reg_offset);
2601 /* If other port enables, the function returns "true" */
2602 return tmp & ref_mask;
2605 static int sh_eth_tsu_busy(struct net_device *ndev)
2607 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2608 struct sh_eth_private *mdp = netdev_priv(ndev);
2610 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2614 netdev_err(ndev, "%s: timeout\n", __func__);
2622 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2627 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2628 iowrite32(val, reg);
2629 if (sh_eth_tsu_busy(ndev) < 0)
2632 val = addr[4] << 8 | addr[5];
2633 iowrite32(val, reg + 4);
2634 if (sh_eth_tsu_busy(ndev) < 0)
2640 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2644 val = ioread32(reg);
2645 addr[0] = (val >> 24) & 0xff;
2646 addr[1] = (val >> 16) & 0xff;
2647 addr[2] = (val >> 8) & 0xff;
2648 addr[3] = val & 0xff;
2649 val = ioread32(reg + 4);
2650 addr[4] = (val >> 8) & 0xff;
2651 addr[5] = val & 0xff;
2655 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2657 struct sh_eth_private *mdp = netdev_priv(ndev);
2658 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2660 u8 c_addr[ETH_ALEN];
2662 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2663 sh_eth_tsu_read_entry(reg_offset, c_addr);
2664 if (ether_addr_equal(addr, c_addr))
2671 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2676 memset(blank, 0, sizeof(blank));
2677 entry = sh_eth_tsu_find_entry(ndev, blank);
2678 return (entry < 0) ? -ENOMEM : entry;
2681 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2684 struct sh_eth_private *mdp = netdev_priv(ndev);
2685 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2689 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2690 ~(1 << (31 - entry)), TSU_TEN);
2692 memset(blank, 0, sizeof(blank));
2693 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2699 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2701 struct sh_eth_private *mdp = netdev_priv(ndev);
2702 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2708 i = sh_eth_tsu_find_entry(ndev, addr);
2710 /* No entry found, create one */
2711 i = sh_eth_tsu_find_empty(ndev);
2714 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2718 /* Enable the entry */
2719 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2720 (1 << (31 - i)), TSU_TEN);
2723 /* Entry found or created, enable POST */
2724 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2729 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2731 struct sh_eth_private *mdp = netdev_priv(ndev);
2737 i = sh_eth_tsu_find_entry(ndev, addr);
2740 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2743 /* Disable the entry if both ports was disabled */
2744 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2752 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2754 struct sh_eth_private *mdp = netdev_priv(ndev);
2760 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2761 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2764 /* Disable the entry if both ports was disabled */
2765 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2773 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2775 struct sh_eth_private *mdp = netdev_priv(ndev);
2777 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2783 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2784 sh_eth_tsu_read_entry(reg_offset, addr);
2785 if (is_multicast_ether_addr(addr))
2786 sh_eth_tsu_del_entry(ndev, addr);
2790 /* Update promiscuous flag and multicast filter */
2791 static void sh_eth_set_rx_mode(struct net_device *ndev)
2793 struct sh_eth_private *mdp = netdev_priv(ndev);
2796 unsigned long flags;
2798 spin_lock_irqsave(&mdp->lock, flags);
2799 /* Initial condition is MCT = 1, PRM = 0.
2800 * Depending on ndev->flags, set PRM or clear MCT
2802 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2804 ecmr_bits |= ECMR_MCT;
2806 if (!(ndev->flags & IFF_MULTICAST)) {
2807 sh_eth_tsu_purge_mcast(ndev);
2810 if (ndev->flags & IFF_ALLMULTI) {
2811 sh_eth_tsu_purge_mcast(ndev);
2812 ecmr_bits &= ~ECMR_MCT;
2816 if (ndev->flags & IFF_PROMISC) {
2817 sh_eth_tsu_purge_all(ndev);
2818 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2819 } else if (mdp->cd->tsu) {
2820 struct netdev_hw_addr *ha;
2821 netdev_for_each_mc_addr(ha, ndev) {
2822 if (mcast_all && is_multicast_ether_addr(ha->addr))
2825 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2827 sh_eth_tsu_purge_mcast(ndev);
2828 ecmr_bits &= ~ECMR_MCT;
2835 /* update the ethernet mode */
2836 sh_eth_write(ndev, ecmr_bits, ECMR);
2838 spin_unlock_irqrestore(&mdp->lock, flags);
2841 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2849 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2850 __be16 proto, u16 vid)
2852 struct sh_eth_private *mdp = netdev_priv(ndev);
2853 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2855 if (unlikely(!mdp->cd->tsu))
2858 /* No filtering if vid = 0 */
2862 mdp->vlan_num_ids++;
2864 /* The controller has one VLAN tag HW filter. So, if the filter is
2865 * already enabled, the driver disables it and the filte
2867 if (mdp->vlan_num_ids > 1) {
2868 /* disable VLAN filter */
2869 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2873 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2879 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2880 __be16 proto, u16 vid)
2882 struct sh_eth_private *mdp = netdev_priv(ndev);
2883 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2885 if (unlikely(!mdp->cd->tsu))
2888 /* No filtering if vid = 0 */
2892 mdp->vlan_num_ids--;
2893 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2898 /* SuperH's TSU register init function */
2899 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2901 if (!mdp->cd->dual_port) {
2902 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2903 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2904 TSU_FWSLC); /* Enable POST registers */
2908 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2909 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2910 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2911 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2912 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2913 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2914 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2915 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2916 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2917 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2918 if (sh_eth_is_gether(mdp)) {
2919 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2920 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2922 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2923 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2925 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2926 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2927 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2928 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2929 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2930 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2931 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2934 /* MDIO bus release function */
2935 static int sh_mdio_release(struct sh_eth_private *mdp)
2937 /* unregister mdio bus */
2938 mdiobus_unregister(mdp->mii_bus);
2940 /* free bitbang info */
2941 free_mdio_bitbang(mdp->mii_bus);
2946 /* MDIO bus init function */
2947 static int sh_mdio_init(struct sh_eth_private *mdp,
2948 struct sh_eth_plat_data *pd)
2951 struct bb_info *bitbang;
2952 struct platform_device *pdev = mdp->pdev;
2953 struct device *dev = &mdp->pdev->dev;
2955 /* create bit control struct for PHY */
2956 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2961 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2962 bitbang->set_gate = pd->set_mdio_gate;
2963 bitbang->ctrl.ops = &bb_ops;
2965 /* MII controller setting */
2966 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2970 /* Hook up MII support for ethtool */
2971 mdp->mii_bus->name = "sh_mii";
2972 mdp->mii_bus->parent = dev;
2973 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2974 pdev->name, pdev->id);
2976 /* register MDIO bus */
2978 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2980 if (pd->phy_irq > 0)
2981 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2983 ret = mdiobus_register(mdp->mii_bus);
2992 free_mdio_bitbang(mdp->mii_bus);
2996 static const u16 *sh_eth_get_register_offset(int register_type)
2998 const u16 *reg_offset = NULL;
3000 switch (register_type) {
3001 case SH_ETH_REG_GIGABIT:
3002 reg_offset = sh_eth_offset_gigabit;
3004 case SH_ETH_REG_FAST_RZ:
3005 reg_offset = sh_eth_offset_fast_rz;
3007 case SH_ETH_REG_FAST_RCAR:
3008 reg_offset = sh_eth_offset_fast_rcar;
3010 case SH_ETH_REG_FAST_SH4:
3011 reg_offset = sh_eth_offset_fast_sh4;
3013 case SH_ETH_REG_FAST_SH3_SH2:
3014 reg_offset = sh_eth_offset_fast_sh3_sh2;
3021 static const struct net_device_ops sh_eth_netdev_ops = {
3022 .ndo_open = sh_eth_open,
3023 .ndo_stop = sh_eth_close,
3024 .ndo_start_xmit = sh_eth_start_xmit,
3025 .ndo_get_stats = sh_eth_get_stats,
3026 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3027 .ndo_tx_timeout = sh_eth_tx_timeout,
3028 .ndo_do_ioctl = sh_eth_do_ioctl,
3029 .ndo_change_mtu = sh_eth_change_mtu,
3030 .ndo_validate_addr = eth_validate_addr,
3031 .ndo_set_mac_address = eth_mac_addr,
3034 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3035 .ndo_open = sh_eth_open,
3036 .ndo_stop = sh_eth_close,
3037 .ndo_start_xmit = sh_eth_start_xmit,
3038 .ndo_get_stats = sh_eth_get_stats,
3039 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3040 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3041 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3042 .ndo_tx_timeout = sh_eth_tx_timeout,
3043 .ndo_do_ioctl = sh_eth_do_ioctl,
3044 .ndo_change_mtu = sh_eth_change_mtu,
3045 .ndo_validate_addr = eth_validate_addr,
3046 .ndo_set_mac_address = eth_mac_addr,
3050 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3052 struct device_node *np = dev->of_node;
3053 struct sh_eth_plat_data *pdata;
3054 const char *mac_addr;
3057 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3061 ret = of_get_phy_mode(np);
3064 pdata->phy_interface = ret;
3066 mac_addr = of_get_mac_address(np);
3068 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3070 pdata->no_ether_link =
3071 of_property_read_bool(np, "renesas,no-ether-link");
3072 pdata->ether_link_active_low =
3073 of_property_read_bool(np, "renesas,ether-link-active-low");
3078 static const struct of_device_id sh_eth_match_table[] = {
3079 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3080 { .compatible = "renesas,ether-r8a7743", .data = &r8a779x_data },
3081 { .compatible = "renesas,ether-r8a7745", .data = &r8a779x_data },
3082 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3083 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3084 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3085 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
3086 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
3087 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
3088 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3091 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3093 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3099 static int sh_eth_drv_probe(struct platform_device *pdev)
3101 struct resource *res;
3102 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3103 const struct platform_device_id *id = platform_get_device_id(pdev);
3104 struct sh_eth_private *mdp;
3105 struct net_device *ndev;
3109 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3111 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3115 pm_runtime_enable(&pdev->dev);
3116 pm_runtime_get_sync(&pdev->dev);
3122 ret = platform_get_irq(pdev, 0);
3127 SET_NETDEV_DEV(ndev, &pdev->dev);
3129 mdp = netdev_priv(ndev);
3130 mdp->num_tx_ring = TX_RING_SIZE;
3131 mdp->num_rx_ring = RX_RING_SIZE;
3132 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3133 if (IS_ERR(mdp->addr)) {
3134 ret = PTR_ERR(mdp->addr);
3138 /* Get clock, if not found that's OK but Wake-On-Lan is unavailable */
3139 mdp->clk = devm_clk_get(&pdev->dev, NULL);
3140 if (IS_ERR(mdp->clk))
3143 ndev->base_addr = res->start;
3145 spin_lock_init(&mdp->lock);
3148 if (pdev->dev.of_node)
3149 pd = sh_eth_parse_dt(&pdev->dev);
3151 dev_err(&pdev->dev, "no platform data\n");
3157 mdp->phy_id = pd->phy;
3158 mdp->phy_interface = pd->phy_interface;
3159 mdp->no_ether_link = pd->no_ether_link;
3160 mdp->ether_link_active_low = pd->ether_link_active_low;
3164 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3166 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3168 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3169 if (!mdp->reg_offset) {
3170 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3171 mdp->cd->register_type);
3175 sh_eth_set_default_cpu_data(mdp->cd);
3177 /* User's manual states max MTU should be 2048 but due to the
3178 * alignment calculations in sh_eth_ring_init() the practical
3179 * MTU is a bit less. Maybe this can be optimized some more.
3181 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3182 ndev->min_mtu = ETH_MIN_MTU;
3186 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3188 ndev->netdev_ops = &sh_eth_netdev_ops;
3189 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3190 ndev->watchdog_timeo = TX_TIMEOUT;
3192 /* debug message level */
3193 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3195 /* read and set MAC address */
3196 read_mac_address(ndev, pd->mac_addr);
3197 if (!is_valid_ether_addr(ndev->dev_addr)) {
3198 dev_warn(&pdev->dev,
3199 "no valid MAC address supplied, using a random one.\n");
3200 eth_hw_addr_random(ndev);
3203 /* ioremap the TSU registers */
3205 struct resource *rtsu;
3207 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3209 dev_err(&pdev->dev, "no TSU resource\n");
3213 /* We can only request the TSU region for the first port
3214 * of the two sharing this TSU for the probe to succeed...
3216 if (devno % 2 == 0 &&
3217 !devm_request_mem_region(&pdev->dev, rtsu->start,
3218 resource_size(rtsu),
3219 dev_name(&pdev->dev))) {
3220 dev_err(&pdev->dev, "can't request TSU resource.\n");
3224 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3225 resource_size(rtsu));
3226 if (!mdp->tsu_addr) {
3227 dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3231 mdp->port = devno % 2;
3232 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3235 /* Need to init only the first port of the two sharing a TSU */
3236 if (devno % 2 == 0) {
3237 if (mdp->cd->chip_reset)
3238 mdp->cd->chip_reset(ndev);
3241 /* TSU init (Init only)*/
3242 sh_eth_tsu_init(mdp);
3246 if (mdp->cd->rmiimode)
3247 sh_eth_write(ndev, 0x1, RMIIMODE);
3250 ret = sh_mdio_init(mdp, pd);
3252 if (ret != -EPROBE_DEFER)
3253 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3257 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3259 /* network device register */
3260 ret = register_netdev(ndev);
3264 if (mdp->cd->magic && mdp->clk)
3265 device_set_wakeup_capable(&pdev->dev, 1);
3267 /* print device information */
3268 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3269 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3271 pm_runtime_put(&pdev->dev);
3272 platform_set_drvdata(pdev, ndev);
3277 netif_napi_del(&mdp->napi);
3278 sh_mdio_release(mdp);
3285 pm_runtime_put(&pdev->dev);
3286 pm_runtime_disable(&pdev->dev);
3290 static int sh_eth_drv_remove(struct platform_device *pdev)
3292 struct net_device *ndev = platform_get_drvdata(pdev);
3293 struct sh_eth_private *mdp = netdev_priv(ndev);
3295 unregister_netdev(ndev);
3296 netif_napi_del(&mdp->napi);
3297 sh_mdio_release(mdp);
3298 pm_runtime_disable(&pdev->dev);
3305 #ifdef CONFIG_PM_SLEEP
3306 static int sh_eth_wol_setup(struct net_device *ndev)
3308 struct sh_eth_private *mdp = netdev_priv(ndev);
3310 /* Only allow ECI interrupts */
3311 synchronize_irq(ndev->irq);
3312 napi_disable(&mdp->napi);
3313 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3315 /* Enable MagicPacket */
3316 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3318 /* Increased clock usage so device won't be suspended */
3319 clk_enable(mdp->clk);
3321 return enable_irq_wake(ndev->irq);
3324 static int sh_eth_wol_restore(struct net_device *ndev)
3326 struct sh_eth_private *mdp = netdev_priv(ndev);
3329 napi_enable(&mdp->napi);
3331 /* Disable MagicPacket */
3332 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3334 /* The device needs to be reset to restore MagicPacket logic
3335 * for next wakeup. If we close and open the device it will
3336 * both be reset and all registers restored. This is what
3337 * happens during suspend and resume without WoL enabled.
3339 ret = sh_eth_close(ndev);
3342 ret = sh_eth_open(ndev);
3346 /* Restore clock usage count */
3347 clk_disable(mdp->clk);
3349 return disable_irq_wake(ndev->irq);
3352 static int sh_eth_suspend(struct device *dev)
3354 struct net_device *ndev = dev_get_drvdata(dev);
3355 struct sh_eth_private *mdp = netdev_priv(ndev);
3358 if (!netif_running(ndev))
3361 netif_device_detach(ndev);
3363 if (mdp->wol_enabled)
3364 ret = sh_eth_wol_setup(ndev);
3366 ret = sh_eth_close(ndev);
3371 static int sh_eth_resume(struct device *dev)
3373 struct net_device *ndev = dev_get_drvdata(dev);
3374 struct sh_eth_private *mdp = netdev_priv(ndev);
3377 if (!netif_running(ndev))
3380 if (mdp->wol_enabled)
3381 ret = sh_eth_wol_restore(ndev);
3383 ret = sh_eth_open(ndev);
3388 netif_device_attach(ndev);
3394 static int sh_eth_runtime_nop(struct device *dev)
3396 /* Runtime PM callback shared between ->runtime_suspend()
3397 * and ->runtime_resume(). Simply returns success.
3399 * This driver re-initializes all registers after
3400 * pm_runtime_get_sync() anyway so there is no need
3401 * to save and restore registers here.
3406 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3407 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3408 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3410 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3412 #define SH_ETH_PM_OPS NULL
3415 static const struct platform_device_id sh_eth_id_table[] = {
3416 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3417 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3418 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3419 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3420 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3421 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3422 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3425 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3427 static struct platform_driver sh_eth_driver = {
3428 .probe = sh_eth_drv_probe,
3429 .remove = sh_eth_drv_remove,
3430 .id_table = sh_eth_id_table,
3433 .pm = SH_ETH_PM_OPS,
3434 .of_match_table = of_match_ptr(sh_eth_match_table),
3438 module_platform_driver(sh_eth_driver);
3440 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3441 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3442 MODULE_LICENSE("GPL v2");