1 /* Renesas Ethernet AVB device driver
3 * Copyright (C) 2014-2019 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
5 * Copyright (C) 2015 Cogent Embedded, Inc. <source@cogentembedded.com>
7 * Based on the SuperH Ethernet driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
14 #include <linux/cache.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/net_tstamp.h>
27 #include <linux/of_device.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_mdio.h>
30 #include <linux/of_net.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
33 #include <linux/spinlock.h>
37 #define RAVB_DEF_MSG_ENABLE \
43 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
47 for (i = 0; i < 10000; i++) {
48 if ((ravb_read(ndev, reg) & mask) == value)
55 static int ravb_config(struct net_device *ndev)
60 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG,
62 /* Check if the operating mode is changed to the config mode */
63 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
65 netdev_err(ndev, "failed to switch device to config mode\n");
70 static void ravb_set_duplex(struct net_device *ndev)
72 struct ravb_private *priv = netdev_priv(ndev);
73 u32 ecmr = ravb_read(ndev, ECMR);
75 if (priv->duplex) /* Full */
79 ravb_write(ndev, ecmr, ECMR);
82 static void ravb_set_rate(struct net_device *ndev)
84 struct ravb_private *priv = netdev_priv(ndev);
86 switch (priv->speed) {
87 case 100: /* 100BASE */
88 ravb_write(ndev, GECMR_SPEED_100, GECMR);
90 case 1000: /* 1000BASE */
91 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
98 static void ravb_set_buffer_align(struct sk_buff *skb)
100 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
103 skb_reserve(skb, RAVB_ALIGN - reserve);
106 /* Get MAC address from the MAC address registers
108 * Ethernet AVB device doesn't have ROM for MAC address.
109 * This function gets the MAC address that was used by a bootloader.
111 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
114 ether_addr_copy(ndev->dev_addr, mac);
116 ndev->dev_addr[0] = (ravb_read(ndev, MAHR) >> 24);
117 ndev->dev_addr[1] = (ravb_read(ndev, MAHR) >> 16) & 0xFF;
118 ndev->dev_addr[2] = (ravb_read(ndev, MAHR) >> 8) & 0xFF;
119 ndev->dev_addr[3] = (ravb_read(ndev, MAHR) >> 0) & 0xFF;
120 ndev->dev_addr[4] = (ravb_read(ndev, MALR) >> 8) & 0xFF;
121 ndev->dev_addr[5] = (ravb_read(ndev, MALR) >> 0) & 0xFF;
125 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
127 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
129 u32 pir = ravb_read(priv->ndev, PIR);
135 ravb_write(priv->ndev, pir, PIR);
138 /* MDC pin control */
139 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
141 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
144 /* Data I/O pin control */
145 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
147 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
151 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
153 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
157 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
159 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
162 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
165 /* MDIO bus control struct */
166 static struct mdiobb_ops bb_ops = {
167 .owner = THIS_MODULE,
168 .set_mdc = ravb_set_mdc,
169 .set_mdio_dir = ravb_set_mdio_dir,
170 .set_mdio_data = ravb_set_mdio_data,
171 .get_mdio_data = ravb_get_mdio_data,
174 /* Free TX skb function for AVB-IP */
175 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
177 struct ravb_private *priv = netdev_priv(ndev);
178 struct net_device_stats *stats = &priv->stats[q];
179 struct ravb_tx_desc *desc;
184 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
187 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
189 desc = &priv->tx_ring[q][entry];
190 txed = desc->die_dt == DT_FEMPTY;
191 if (free_txed_only && !txed)
193 /* Descriptor type must be checked before all other reads */
195 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
196 /* Free the original skb. */
197 if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
198 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
199 size, DMA_TO_DEVICE);
200 /* Last packet descriptor? */
201 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
202 entry /= NUM_TX_DESC;
203 dev_kfree_skb_any(priv->tx_skb[q][entry]);
204 priv->tx_skb[q][entry] = NULL;
211 stats->tx_bytes += size;
212 desc->die_dt = DT_EEMPTY;
217 /* Free skb's and DMA buffers for Ethernet AVB */
218 static void ravb_ring_free(struct net_device *ndev, int q)
220 struct ravb_private *priv = netdev_priv(ndev);
224 if (priv->rx_ring[q]) {
225 for (i = 0; i < priv->num_rx_ring[q]; i++) {
226 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
228 if (!dma_mapping_error(ndev->dev.parent,
229 le32_to_cpu(desc->dptr)))
230 dma_unmap_single(ndev->dev.parent,
231 le32_to_cpu(desc->dptr),
235 ring_size = sizeof(struct ravb_ex_rx_desc) *
236 (priv->num_rx_ring[q] + 1);
237 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
238 priv->rx_desc_dma[q]);
239 priv->rx_ring[q] = NULL;
242 if (priv->tx_ring[q]) {
243 ravb_tx_free(ndev, q, false);
245 ring_size = sizeof(struct ravb_tx_desc) *
246 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
247 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
248 priv->tx_desc_dma[q]);
249 priv->tx_ring[q] = NULL;
252 /* Free RX skb ringbuffer */
253 if (priv->rx_skb[q]) {
254 for (i = 0; i < priv->num_rx_ring[q]; i++)
255 dev_kfree_skb(priv->rx_skb[q][i]);
257 kfree(priv->rx_skb[q]);
258 priv->rx_skb[q] = NULL;
260 /* Free aligned TX buffers */
261 kfree(priv->tx_align[q]);
262 priv->tx_align[q] = NULL;
264 /* Free TX skb ringbuffer.
265 * SKBs are freed by ravb_tx_free() call above.
267 kfree(priv->tx_skb[q]);
268 priv->tx_skb[q] = NULL;
271 /* Format skb and descriptor buffer for Ethernet AVB */
272 static void ravb_ring_format(struct net_device *ndev, int q)
274 struct ravb_private *priv = netdev_priv(ndev);
275 struct ravb_ex_rx_desc *rx_desc;
276 struct ravb_tx_desc *tx_desc;
277 struct ravb_desc *desc;
278 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
279 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
286 priv->dirty_rx[q] = 0;
287 priv->dirty_tx[q] = 0;
289 memset(priv->rx_ring[q], 0, rx_ring_size);
290 /* Build RX ring buffer */
291 for (i = 0; i < priv->num_rx_ring[q]; i++) {
293 rx_desc = &priv->rx_ring[q][i];
294 /* The size of the buffer should be on 16-byte boundary. */
295 rx_desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16));
296 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
297 ALIGN(PKT_BUF_SZ, 16),
299 /* We just set the data size to 0 for a failed mapping which
300 * should prevent DMA from happening...
302 if (dma_mapping_error(ndev->dev.parent, dma_addr))
303 rx_desc->ds_cc = cpu_to_le16(0);
304 rx_desc->dptr = cpu_to_le32(dma_addr);
305 rx_desc->die_dt = DT_FEMPTY;
307 rx_desc = &priv->rx_ring[q][i];
308 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
309 rx_desc->die_dt = DT_LINKFIX; /* type */
311 memset(priv->tx_ring[q], 0, tx_ring_size);
312 /* Build TX ring buffer */
313 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
315 tx_desc->die_dt = DT_EEMPTY;
317 tx_desc->die_dt = DT_EEMPTY;
319 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
320 tx_desc->die_dt = DT_LINKFIX; /* type */
322 /* RX descriptor base address for best effort */
323 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
324 desc->die_dt = DT_LINKFIX; /* type */
325 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
327 /* TX descriptor base address for best effort */
328 desc = &priv->desc_bat[q];
329 desc->die_dt = DT_LINKFIX; /* type */
330 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
333 /* Init skb and descriptor buffer for Ethernet AVB */
334 static int ravb_ring_init(struct net_device *ndev, int q)
336 struct ravb_private *priv = netdev_priv(ndev);
341 /* Allocate RX and TX skb rings */
342 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
343 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
344 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
345 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
346 if (!priv->rx_skb[q] || !priv->tx_skb[q])
349 for (i = 0; i < priv->num_rx_ring[q]; i++) {
350 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
353 ravb_set_buffer_align(skb);
354 priv->rx_skb[q][i] = skb;
357 /* Allocate rings for the aligned buffers */
358 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
359 DPTR_ALIGN - 1, GFP_KERNEL);
360 if (!priv->tx_align[q])
363 /* Allocate all RX descriptors. */
364 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
365 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
366 &priv->rx_desc_dma[q],
368 if (!priv->rx_ring[q])
371 priv->dirty_rx[q] = 0;
373 /* Allocate all TX descriptors. */
374 ring_size = sizeof(struct ravb_tx_desc) *
375 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
376 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
377 &priv->tx_desc_dma[q],
379 if (!priv->tx_ring[q])
385 ravb_ring_free(ndev, q);
390 /* E-MAC init function */
391 static void ravb_emac_init(struct net_device *ndev)
393 struct ravb_private *priv = netdev_priv(ndev);
396 /* Receive frame limit set register */
397 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
399 /* PAUSE prohibition */
400 ecmr = ravb_read(ndev, ECMR);
402 ecmr |= ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
403 ravb_write(ndev, ecmr, ECMR);
407 /* Set MAC address */
409 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
410 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
412 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
414 ravb_write(ndev, 1, MPR);
416 /* E-MAC status register clear */
417 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
419 /* E-MAC interrupt enable register */
420 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
423 /* Device init function for Ethernet AVB */
424 static int ravb_dmac_init(struct net_device *ndev)
428 /* Set CONFIG mode */
429 error = ravb_config(ndev);
433 error = ravb_ring_init(ndev, RAVB_BE);
436 error = ravb_ring_init(ndev, RAVB_NC);
438 ravb_ring_free(ndev, RAVB_BE);
442 /* Descriptor format */
443 ravb_ring_format(ndev, RAVB_BE);
444 ravb_ring_format(ndev, RAVB_NC);
446 #if defined(__LITTLE_ENDIAN)
447 ravb_write(ndev, ravb_read(ndev, CCC) & ~CCC_BOC, CCC);
449 ravb_write(ndev, ravb_read(ndev, CCC) | CCC_BOC, CCC);
453 ravb_write(ndev, RCR_EFFS | RCR_ENCF | RCR_ETS0 | 0x18000000, RCR);
456 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
458 /* Timestamp enable */
459 ravb_write(ndev, TCCR_TFEN, TCCR);
461 /* Interrupt enable: */
463 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
464 /* Receive FIFO full error, descriptor empty */
465 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
466 /* Frame transmitted, timestamp FIFO updated */
467 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
469 /* Setting the control will start the AVB-DMAC process. */
470 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_OPERATION,
476 static void ravb_get_tx_tstamp(struct net_device *ndev)
478 struct ravb_private *priv = netdev_priv(ndev);
479 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
480 struct skb_shared_hwtstamps shhwtstamps;
482 struct timespec64 ts;
487 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
489 tfa2 = ravb_read(ndev, TFA2);
490 tfa_tag = (tfa2 & TFA2_TST) >> 16;
491 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
492 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
493 ravb_read(ndev, TFA1);
494 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
495 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
496 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
500 list_del(&ts_skb->list);
502 if (tag == tfa_tag) {
503 skb_tstamp_tx(skb, &shhwtstamps);
504 dev_consume_skb_any(skb);
507 dev_kfree_skb_any(skb);
510 ravb_write(ndev, ravb_read(ndev, TCCR) | TCCR_TFR, TCCR);
514 /* Packet receive function for Ethernet AVB */
515 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
517 struct ravb_private *priv = netdev_priv(ndev);
518 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
519 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
521 struct net_device_stats *stats = &priv->stats[q];
522 struct ravb_ex_rx_desc *desc;
525 struct timespec64 ts;
530 boguscnt = min(boguscnt, *quota);
532 desc = &priv->rx_ring[q][entry];
533 while (desc->die_dt != DT_FEMPTY) {
534 /* Descriptor type must be checked before all other reads */
536 desc_status = desc->msc;
537 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
542 /* We use 0-byte descriptors to mark the DMA mapping errors */
546 if (desc_status & MSC_MC)
549 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
552 if (desc_status & MSC_CRC)
553 stats->rx_crc_errors++;
554 if (desc_status & MSC_RFE)
555 stats->rx_frame_errors++;
556 if (desc_status & (MSC_RTLF | MSC_RTSF))
557 stats->rx_length_errors++;
558 if (desc_status & MSC_CEEF)
559 stats->rx_missed_errors++;
561 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
563 skb = priv->rx_skb[q][entry];
564 priv->rx_skb[q][entry] = NULL;
565 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
566 ALIGN(PKT_BUF_SZ, 16),
568 get_ts &= (q == RAVB_NC) ?
569 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
570 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
572 struct skb_shared_hwtstamps *shhwtstamps;
574 shhwtstamps = skb_hwtstamps(skb);
575 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
576 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
577 32) | le32_to_cpu(desc->ts_sl);
578 ts.tv_nsec = le32_to_cpu(desc->ts_n);
579 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
581 skb_put(skb, pkt_len);
582 skb->protocol = eth_type_trans(skb, ndev);
583 napi_gro_receive(&priv->napi[q], skb);
585 stats->rx_bytes += pkt_len;
588 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
589 desc = &priv->rx_ring[q][entry];
592 /* Refill the RX ring buffers. */
593 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
594 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
595 desc = &priv->rx_ring[q][entry];
596 /* The size of the buffer should be on 16-byte boundary. */
597 desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16));
599 if (!priv->rx_skb[q][entry]) {
600 skb = netdev_alloc_skb(ndev,
601 PKT_BUF_SZ + RAVB_ALIGN - 1);
603 break; /* Better luck next round. */
604 ravb_set_buffer_align(skb);
605 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
606 le16_to_cpu(desc->ds_cc),
608 skb_checksum_none_assert(skb);
609 /* We just set the data size to 0 for a failed mapping
610 * which should prevent DMA from happening...
612 if (dma_mapping_error(ndev->dev.parent, dma_addr))
613 desc->ds_cc = cpu_to_le16(0);
614 desc->dptr = cpu_to_le32(dma_addr);
615 priv->rx_skb[q][entry] = skb;
617 /* Descriptor type must be set after all the above writes */
619 desc->die_dt = DT_FEMPTY;
622 *quota -= limit - (++boguscnt);
624 return boguscnt <= 0;
627 static void ravb_rcv_snd_disable(struct net_device *ndev)
629 /* Disable TX and RX */
630 ravb_write(ndev, ravb_read(ndev, ECMR) & ~(ECMR_RE | ECMR_TE), ECMR);
633 static void ravb_rcv_snd_enable(struct net_device *ndev)
635 /* Enable TX and RX */
636 ravb_write(ndev, ravb_read(ndev, ECMR) | ECMR_RE | ECMR_TE, ECMR);
639 /* function for waiting dma process finished */
640 static int ravb_stop_dma(struct net_device *ndev)
644 /* Wait for stopping the hardware TX process */
645 error = ravb_wait(ndev, TCCR,
646 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
650 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
655 /* Stop the E-MAC's RX/TX processes. */
656 ravb_rcv_snd_disable(ndev);
658 /* Wait for stopping the RX DMA process */
659 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
663 /* Stop AVB-DMAC process */
664 return ravb_config(ndev);
667 /* E-MAC interrupt handler */
668 static void ravb_emac_interrupt(struct net_device *ndev)
670 struct ravb_private *priv = netdev_priv(ndev);
673 ecsr = ravb_read(ndev, ECSR);
674 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
676 ndev->stats.tx_carrier_errors++;
677 if (ecsr & ECSR_LCHNG) {
679 if (priv->no_avb_link)
681 psr = ravb_read(ndev, PSR);
682 if (priv->avb_link_active_low)
684 if (!(psr & PSR_LMON)) {
685 /* DIsable RX and TX */
686 ravb_rcv_snd_disable(ndev);
688 /* Enable RX and TX */
689 ravb_rcv_snd_enable(ndev);
694 /* Error interrupt handler */
695 static void ravb_error_interrupt(struct net_device *ndev)
697 struct ravb_private *priv = netdev_priv(ndev);
700 eis = ravb_read(ndev, EIS);
701 ravb_write(ndev, ~EIS_QFS, EIS);
703 ris2 = ravb_read(ndev, RIS2);
704 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);
706 /* Receive Descriptor Empty int */
707 if (ris2 & RIS2_QFF0)
708 priv->stats[RAVB_BE].rx_over_errors++;
710 /* Receive Descriptor Empty int */
711 if (ris2 & RIS2_QFF1)
712 priv->stats[RAVB_NC].rx_over_errors++;
714 /* Receive FIFO Overflow int */
715 if (ris2 & RIS2_RFFF)
716 priv->rx_fifo_errors++;
720 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
722 struct net_device *ndev = dev_id;
723 struct ravb_private *priv = netdev_priv(ndev);
724 irqreturn_t result = IRQ_NONE;
727 spin_lock(&priv->lock);
728 /* Get interrupt status */
729 iss = ravb_read(ndev, ISS);
731 /* Received and transmitted interrupts */
732 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
733 u32 ris0 = ravb_read(ndev, RIS0);
734 u32 ric0 = ravb_read(ndev, RIC0);
735 u32 tis = ravb_read(ndev, TIS);
736 u32 tic = ravb_read(ndev, TIC);
739 /* Timestamp updated */
740 if (tis & TIS_TFUF) {
741 ravb_write(ndev, ~TIS_TFUF, TIS);
742 ravb_get_tx_tstamp(ndev);
743 result = IRQ_HANDLED;
746 /* Network control and best effort queue RX/TX */
747 for (q = RAVB_NC; q >= RAVB_BE; q--) {
748 if (((ris0 & ric0) & BIT(q)) ||
749 ((tis & tic) & BIT(q))) {
750 if (napi_schedule_prep(&priv->napi[q])) {
751 /* Mask RX and TX interrupts */
754 ravb_write(ndev, ric0, RIC0);
755 ravb_write(ndev, tic, TIC);
756 __napi_schedule(&priv->napi[q]);
759 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
762 " tx status 0x%08x, tx mask 0x%08x.\n",
765 result = IRQ_HANDLED;
770 /* E-MAC status summary */
772 ravb_emac_interrupt(ndev);
773 result = IRQ_HANDLED;
776 /* Error status summary */
778 ravb_error_interrupt(ndev);
779 result = IRQ_HANDLED;
783 result = ravb_ptp_interrupt(ndev);
786 spin_unlock(&priv->lock);
790 static int ravb_poll(struct napi_struct *napi, int budget)
792 struct net_device *ndev = napi->dev;
793 struct ravb_private *priv = netdev_priv(ndev);
795 int q = napi - priv->napi;
801 tis = ravb_read(ndev, TIS);
802 ris0 = ravb_read(ndev, RIS0);
803 if (!((ris0 & mask) || (tis & mask)))
806 /* Processing RX Descriptor Ring */
808 /* Clear RX interrupt */
809 ravb_write(ndev, ~mask, RIS0);
810 if (ravb_rx(ndev, "a, q))
813 /* Processing TX Descriptor Ring */
815 spin_lock_irqsave(&priv->lock, flags);
816 /* Clear TX interrupt */
817 ravb_write(ndev, ~mask, TIS);
818 ravb_tx_free(ndev, q, true);
819 netif_wake_subqueue(ndev, q);
821 spin_unlock_irqrestore(&priv->lock, flags);
827 /* Re-enable RX/TX interrupts */
828 spin_lock_irqsave(&priv->lock, flags);
829 ravb_write(ndev, ravb_read(ndev, RIC0) | mask, RIC0);
830 ravb_write(ndev, ravb_read(ndev, TIC) | mask, TIC);
832 spin_unlock_irqrestore(&priv->lock, flags);
834 /* Receive error message handling */
835 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
836 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
837 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
838 ndev->stats.rx_over_errors = priv->rx_over_errors;
839 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
840 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
842 return budget - quota;
845 /* PHY state control function */
846 static void ravb_adjust_link(struct net_device *ndev)
848 struct ravb_private *priv = netdev_priv(ndev);
849 struct phy_device *phydev = priv->phydev;
850 bool new_state = false;
853 if (phydev->duplex != priv->duplex) {
855 priv->duplex = phydev->duplex;
856 ravb_set_duplex(ndev);
859 if (phydev->speed != priv->speed) {
861 priv->speed = phydev->speed;
865 ravb_write(ndev, ravb_read(ndev, ECMR) & ~ECMR_TXF,
868 priv->link = phydev->link;
869 if (priv->no_avb_link)
870 ravb_rcv_snd_enable(ndev);
872 } else if (priv->link) {
877 if (priv->no_avb_link)
878 ravb_rcv_snd_disable(ndev);
881 if (new_state && netif_msg_link(priv))
882 phy_print_status(phydev);
885 /* PHY init function */
886 static int ravb_phy_init(struct net_device *ndev)
888 struct device_node *np = ndev->dev.parent->of_node;
889 struct ravb_private *priv = netdev_priv(ndev);
890 struct phy_device *phydev;
891 struct device_node *pn;
897 /* Try connecting to PHY */
898 pn = of_parse_phandle(np, "phy-handle", 0);
899 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
900 priv->phy_interface);
902 netdev_err(ndev, "failed to connect PHY\n");
906 /* This driver only support 10/100Mbit speeds on Gen3
909 if (priv->chip_id == RCAR_GEN3) {
912 err = phy_set_max_speed(phydev, SPEED_100);
914 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
915 phy_disconnect(phydev);
919 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
922 /* 10BASE is not supported */
923 phydev->supported &= ~PHY_10BT_FEATURES;
925 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
926 phydev->addr, phydev->irq, phydev->drv->name);
928 priv->phydev = phydev;
933 /* PHY control start function */
934 static int ravb_phy_start(struct net_device *ndev)
936 struct ravb_private *priv = netdev_priv(ndev);
939 error = ravb_phy_init(ndev);
943 phy_start(priv->phydev);
948 static int ravb_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
950 struct ravb_private *priv = netdev_priv(ndev);
955 spin_lock_irqsave(&priv->lock, flags);
956 error = phy_ethtool_gset(priv->phydev, ecmd);
957 spin_unlock_irqrestore(&priv->lock, flags);
963 static int ravb_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
965 struct ravb_private *priv = netdev_priv(ndev);
972 spin_lock_irqsave(&priv->lock, flags);
974 /* Disable TX and RX */
975 ravb_rcv_snd_disable(ndev);
977 error = phy_ethtool_sset(priv->phydev, ecmd);
981 if (ecmd->duplex == DUPLEX_FULL)
986 ravb_set_duplex(ndev);
991 /* Enable TX and RX */
992 ravb_rcv_snd_enable(ndev);
995 spin_unlock_irqrestore(&priv->lock, flags);
1000 static int ravb_nway_reset(struct net_device *ndev)
1002 struct ravb_private *priv = netdev_priv(ndev);
1003 int error = -ENODEV;
1004 unsigned long flags;
1007 spin_lock_irqsave(&priv->lock, flags);
1008 error = phy_start_aneg(priv->phydev);
1009 spin_unlock_irqrestore(&priv->lock, flags);
1015 static u32 ravb_get_msglevel(struct net_device *ndev)
1017 struct ravb_private *priv = netdev_priv(ndev);
1019 return priv->msg_enable;
1022 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1024 struct ravb_private *priv = netdev_priv(ndev);
1026 priv->msg_enable = value;
1029 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1030 "rx_queue_0_current",
1031 "tx_queue_0_current",
1034 "rx_queue_0_packets",
1035 "tx_queue_0_packets",
1038 "rx_queue_0_mcast_packets",
1039 "rx_queue_0_errors",
1040 "rx_queue_0_crc_errors",
1041 "rx_queue_0_frame_errors",
1042 "rx_queue_0_length_errors",
1043 "rx_queue_0_missed_errors",
1044 "rx_queue_0_over_errors",
1046 "rx_queue_1_current",
1047 "tx_queue_1_current",
1050 "rx_queue_1_packets",
1051 "tx_queue_1_packets",
1054 "rx_queue_1_mcast_packets",
1055 "rx_queue_1_errors",
1056 "rx_queue_1_crc_errors",
1057 "rx_queue_1_frame_errors",
1058 "rx_queue_1_length_errors",
1059 "rx_queue_1_missed_errors",
1060 "rx_queue_1_over_errors",
1063 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1065 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1069 return RAVB_STATS_LEN;
1075 static void ravb_get_ethtool_stats(struct net_device *ndev,
1076 struct ethtool_stats *stats, u64 *data)
1078 struct ravb_private *priv = netdev_priv(ndev);
1082 /* Device-specific stats */
1083 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1084 struct net_device_stats *stats = &priv->stats[q];
1086 data[i++] = priv->cur_rx[q];
1087 data[i++] = priv->cur_tx[q];
1088 data[i++] = priv->dirty_rx[q];
1089 data[i++] = priv->dirty_tx[q];
1090 data[i++] = stats->rx_packets;
1091 data[i++] = stats->tx_packets;
1092 data[i++] = stats->rx_bytes;
1093 data[i++] = stats->tx_bytes;
1094 data[i++] = stats->multicast;
1095 data[i++] = stats->rx_errors;
1096 data[i++] = stats->rx_crc_errors;
1097 data[i++] = stats->rx_frame_errors;
1098 data[i++] = stats->rx_length_errors;
1099 data[i++] = stats->rx_missed_errors;
1100 data[i++] = stats->rx_over_errors;
1104 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1106 switch (stringset) {
1108 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1113 static void ravb_get_ringparam(struct net_device *ndev,
1114 struct ethtool_ringparam *ring)
1116 struct ravb_private *priv = netdev_priv(ndev);
1118 ring->rx_max_pending = BE_RX_RING_MAX;
1119 ring->tx_max_pending = BE_TX_RING_MAX;
1120 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1121 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1124 static int ravb_set_ringparam(struct net_device *ndev,
1125 struct ethtool_ringparam *ring)
1127 struct ravb_private *priv = netdev_priv(ndev);
1130 if (ring->tx_pending > BE_TX_RING_MAX ||
1131 ring->rx_pending > BE_RX_RING_MAX ||
1132 ring->tx_pending < BE_TX_RING_MIN ||
1133 ring->rx_pending < BE_RX_RING_MIN)
1135 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1138 if (netif_running(ndev)) {
1139 netif_device_detach(ndev);
1140 /* Stop PTP Clock driver */
1141 ravb_ptp_stop(ndev);
1142 /* Wait for DMA stopping */
1143 error = ravb_stop_dma(ndev);
1146 "cannot set ringparam! Any AVB processes are still running?\n");
1149 synchronize_irq(ndev->irq);
1151 /* Free all the skb's in the RX queue and the DMA buffers. */
1152 ravb_ring_free(ndev, RAVB_BE);
1153 ravb_ring_free(ndev, RAVB_NC);
1156 /* Set new parameters */
1157 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1158 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1160 if (netif_running(ndev)) {
1161 error = ravb_dmac_init(ndev);
1164 "%s: ravb_dmac_init() failed, error %d\n",
1169 ravb_emac_init(ndev);
1171 /* Initialise PTP Clock driver */
1172 ravb_ptp_init(ndev, priv->pdev);
1174 netif_device_attach(ndev);
1180 static int ravb_get_ts_info(struct net_device *ndev,
1181 struct ethtool_ts_info *info)
1183 struct ravb_private *priv = netdev_priv(ndev);
1185 info->so_timestamping =
1186 SOF_TIMESTAMPING_TX_SOFTWARE |
1187 SOF_TIMESTAMPING_RX_SOFTWARE |
1188 SOF_TIMESTAMPING_SOFTWARE |
1189 SOF_TIMESTAMPING_TX_HARDWARE |
1190 SOF_TIMESTAMPING_RX_HARDWARE |
1191 SOF_TIMESTAMPING_RAW_HARDWARE;
1192 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1194 (1 << HWTSTAMP_FILTER_NONE) |
1195 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1196 (1 << HWTSTAMP_FILTER_ALL);
1197 info->phc_index = ptp_clock_index(priv->ptp.clock);
1202 static const struct ethtool_ops ravb_ethtool_ops = {
1203 .get_settings = ravb_get_settings,
1204 .set_settings = ravb_set_settings,
1205 .nway_reset = ravb_nway_reset,
1206 .get_msglevel = ravb_get_msglevel,
1207 .set_msglevel = ravb_set_msglevel,
1208 .get_link = ethtool_op_get_link,
1209 .get_strings = ravb_get_strings,
1210 .get_ethtool_stats = ravb_get_ethtool_stats,
1211 .get_sset_count = ravb_get_sset_count,
1212 .get_ringparam = ravb_get_ringparam,
1213 .set_ringparam = ravb_set_ringparam,
1214 .get_ts_info = ravb_get_ts_info,
1217 /* Network device open function for Ethernet AVB */
1218 static int ravb_open(struct net_device *ndev)
1220 struct ravb_private *priv = netdev_priv(ndev);
1223 napi_enable(&priv->napi[RAVB_BE]);
1224 napi_enable(&priv->napi[RAVB_NC]);
1226 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, ndev->name,
1229 netdev_err(ndev, "cannot request IRQ\n");
1233 if (priv->chip_id == RCAR_GEN3) {
1234 error = request_irq(priv->emac_irq, ravb_interrupt,
1235 IRQF_SHARED, ndev->name, ndev);
1237 netdev_err(ndev, "cannot request IRQ\n");
1243 error = ravb_dmac_init(ndev);
1246 ravb_emac_init(ndev);
1248 /* Initialise PTP Clock driver */
1249 ravb_ptp_init(ndev, priv->pdev);
1251 netif_tx_start_all_queues(ndev);
1253 /* PHY control start */
1254 error = ravb_phy_start(ndev);
1261 /* Stop PTP Clock driver */
1262 ravb_ptp_stop(ndev);
1264 if (priv->chip_id == RCAR_GEN3)
1265 free_irq(priv->emac_irq, ndev);
1267 free_irq(ndev->irq, ndev);
1269 napi_disable(&priv->napi[RAVB_NC]);
1270 napi_disable(&priv->napi[RAVB_BE]);
1274 /* Timeout function for Ethernet AVB */
1275 static void ravb_tx_timeout(struct net_device *ndev)
1277 struct ravb_private *priv = netdev_priv(ndev);
1279 netif_err(priv, tx_err, ndev,
1280 "transmit timed out, status %08x, resetting...\n",
1281 ravb_read(ndev, ISS));
1283 /* tx_errors count up */
1284 ndev->stats.tx_errors++;
1286 schedule_work(&priv->work);
1289 static void ravb_tx_timeout_work(struct work_struct *work)
1291 struct ravb_private *priv = container_of(work, struct ravb_private,
1293 struct net_device *ndev = priv->ndev;
1296 netif_tx_stop_all_queues(ndev);
1298 /* Stop PTP Clock driver */
1299 ravb_ptp_stop(ndev);
1301 /* Wait for DMA stopping */
1302 if (ravb_stop_dma(ndev)) {
1303 /* If ravb_stop_dma() fails, the hardware is still operating
1304 * for TX and/or RX. So, this should not call the following
1305 * functions because ravb_dmac_init() is possible to fail too.
1306 * Also, this should not retry ravb_stop_dma() again and again
1307 * here because it's possible to wait forever. So, this just
1308 * re-enables the TX and RX and skip the following
1309 * re-initialization procedure.
1311 ravb_rcv_snd_enable(ndev);
1315 ravb_ring_free(ndev, RAVB_BE);
1316 ravb_ring_free(ndev, RAVB_NC);
1319 error = ravb_dmac_init(ndev);
1321 /* If ravb_dmac_init() fails, descriptors are freed. So, this
1322 * should return here to avoid re-enabling the TX and RX in
1325 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n",
1329 ravb_emac_init(ndev);
1332 /* Initialise PTP Clock driver */
1333 ravb_ptp_init(ndev, priv->pdev);
1335 netif_tx_start_all_queues(ndev);
1338 /* Packet transmit function for Ethernet AVB */
1339 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1341 struct ravb_private *priv = netdev_priv(ndev);
1342 u16 q = skb_get_queue_mapping(skb);
1343 struct ravb_tstamp_skb *ts_skb;
1344 struct ravb_tx_desc *desc;
1345 unsigned long flags;
1351 spin_lock_irqsave(&priv->lock, flags);
1352 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1354 netif_err(priv, tx_queued, ndev,
1355 "still transmitting with the full ring!\n");
1356 netif_stop_subqueue(ndev, q);
1357 spin_unlock_irqrestore(&priv->lock, flags);
1358 return NETDEV_TX_BUSY;
1360 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1361 priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
1363 if (skb_put_padto(skb, ETH_ZLEN))
1366 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1367 entry / NUM_TX_DESC * DPTR_ALIGN;
1368 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1369 /* Zero length DMA descriptors are problematic as they seem to
1370 * terminate DMA transfers. Avoid them by simply using a length of
1371 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN.
1373 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of
1374 * data by the call to skb_put_padto() above this is safe with
1375 * respect to both the length of the first DMA descriptor (len)
1376 * overflowing the available data and the length of the second DMA
1377 * descriptor (skb->len - len) being negative.
1382 memcpy(buffer, skb->data, len);
1383 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1384 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1387 desc = &priv->tx_ring[q][entry];
1388 desc->ds_tagl = cpu_to_le16(len);
1389 desc->dptr = cpu_to_le32(dma_addr);
1391 buffer = skb->data + len;
1392 len = skb->len - len;
1393 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1394 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1398 desc->ds_tagl = cpu_to_le16(len);
1399 desc->dptr = cpu_to_le32(dma_addr);
1401 /* TX timestamp required */
1403 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1406 dma_unmap_single(ndev->dev.parent, dma_addr, len,
1410 ts_skb->skb = skb_get(skb);
1411 ts_skb->tag = priv->ts_skb_tag++;
1412 priv->ts_skb_tag &= 0x3ff;
1413 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1415 /* TAG and timestamp required flag */
1416 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1417 skb_tx_timestamp(skb);
1418 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1419 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1422 /* Descriptor type must be set after all the above writes */
1424 desc->die_dt = DT_FEND;
1426 desc->die_dt = DT_FSTART;
1428 ravb_write(ndev, ravb_read(ndev, TCCR) | (TCCR_TSRQ0 << q), TCCR);
1430 priv->cur_tx[q] += NUM_TX_DESC;
1431 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1432 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC &&
1433 !ravb_tx_free(ndev, q, true))
1434 netif_stop_subqueue(ndev, q);
1438 spin_unlock_irqrestore(&priv->lock, flags);
1439 return NETDEV_TX_OK;
1442 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1443 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1445 dev_kfree_skb_any(skb);
1446 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
1450 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1451 void *accel_priv, select_queue_fallback_t fallback)
1453 /* If skb needs TX timestamp, it is handled in network control queue */
1454 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1459 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1461 struct ravb_private *priv = netdev_priv(ndev);
1462 struct net_device_stats *nstats, *stats0, *stats1;
1464 nstats = &ndev->stats;
1465 stats0 = &priv->stats[RAVB_BE];
1466 stats1 = &priv->stats[RAVB_NC];
1468 nstats->tx_dropped += ravb_read(ndev, TROCR);
1469 ravb_write(ndev, 0, TROCR); /* (write clear) */
1470 nstats->collisions += ravb_read(ndev, CDCR);
1471 ravb_write(ndev, 0, CDCR); /* (write clear) */
1472 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1473 ravb_write(ndev, 0, LCCR); /* (write clear) */
1475 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1476 ravb_write(ndev, 0, CERCR); /* (write clear) */
1477 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1478 ravb_write(ndev, 0, CEECR); /* (write clear) */
1480 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1481 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1482 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1483 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1484 nstats->multicast = stats0->multicast + stats1->multicast;
1485 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1486 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1487 nstats->rx_frame_errors =
1488 stats0->rx_frame_errors + stats1->rx_frame_errors;
1489 nstats->rx_length_errors =
1490 stats0->rx_length_errors + stats1->rx_length_errors;
1491 nstats->rx_missed_errors =
1492 stats0->rx_missed_errors + stats1->rx_missed_errors;
1493 nstats->rx_over_errors =
1494 stats0->rx_over_errors + stats1->rx_over_errors;
1499 /* Update promiscuous bit */
1500 static void ravb_set_rx_mode(struct net_device *ndev)
1502 struct ravb_private *priv = netdev_priv(ndev);
1503 unsigned long flags;
1506 spin_lock_irqsave(&priv->lock, flags);
1507 ecmr = ravb_read(ndev, ECMR);
1508 if (ndev->flags & IFF_PROMISC)
1512 ravb_write(ndev, ecmr, ECMR);
1514 spin_unlock_irqrestore(&priv->lock, flags);
1517 /* Device close function for Ethernet AVB */
1518 static int ravb_close(struct net_device *ndev)
1520 struct ravb_private *priv = netdev_priv(ndev);
1521 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1523 netif_tx_stop_all_queues(ndev);
1525 /* Disable interrupts by clearing the interrupt masks. */
1526 ravb_write(ndev, 0, RIC0);
1527 ravb_write(ndev, 0, RIC1);
1528 ravb_write(ndev, 0, RIC2);
1529 ravb_write(ndev, 0, TIC);
1531 /* Stop PTP Clock driver */
1532 ravb_ptp_stop(ndev);
1534 /* Set the config mode to stop the AVB-DMAC's processes */
1535 if (ravb_stop_dma(ndev) < 0)
1537 "device will be stopped after h/w processes are done.\n");
1539 /* Clear the timestamp list */
1540 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1541 list_del(&ts_skb->list);
1542 kfree_skb(ts_skb->skb);
1546 /* PHY disconnect */
1548 phy_stop(priv->phydev);
1549 phy_disconnect(priv->phydev);
1550 priv->phydev = NULL;
1553 if (priv->chip_id == RCAR_GEN3)
1554 free_irq(priv->emac_irq, ndev);
1555 free_irq(ndev->irq, ndev);
1557 napi_disable(&priv->napi[RAVB_NC]);
1558 napi_disable(&priv->napi[RAVB_BE]);
1560 /* Free all the skb's in the RX queue and the DMA buffers. */
1561 ravb_ring_free(ndev, RAVB_BE);
1562 ravb_ring_free(ndev, RAVB_NC);
1567 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1569 struct ravb_private *priv = netdev_priv(ndev);
1570 struct hwtstamp_config config;
1573 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1575 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) {
1576 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT:
1577 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1579 case RAVB_RXTSTAMP_TYPE_ALL:
1580 config.rx_filter = HWTSTAMP_FILTER_ALL;
1583 config.rx_filter = HWTSTAMP_FILTER_NONE;
1586 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1590 /* Control hardware time stamping */
1591 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1593 struct ravb_private *priv = netdev_priv(ndev);
1594 struct hwtstamp_config config;
1595 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1598 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1601 /* Reserved for future extensions */
1605 switch (config.tx_type) {
1606 case HWTSTAMP_TX_OFF:
1609 case HWTSTAMP_TX_ON:
1610 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1616 switch (config.rx_filter) {
1617 case HWTSTAMP_FILTER_NONE:
1620 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1621 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1624 config.rx_filter = HWTSTAMP_FILTER_ALL;
1625 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1628 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1629 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1631 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1635 /* ioctl to device function */
1636 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1638 struct ravb_private *priv = netdev_priv(ndev);
1639 struct phy_device *phydev = priv->phydev;
1641 if (!netif_running(ndev))
1649 return ravb_hwtstamp_get(ndev, req);
1651 return ravb_hwtstamp_set(ndev, req);
1654 return phy_mii_ioctl(phydev, req, cmd);
1657 static const struct net_device_ops ravb_netdev_ops = {
1658 .ndo_open = ravb_open,
1659 .ndo_stop = ravb_close,
1660 .ndo_start_xmit = ravb_start_xmit,
1661 .ndo_select_queue = ravb_select_queue,
1662 .ndo_get_stats = ravb_get_stats,
1663 .ndo_set_rx_mode = ravb_set_rx_mode,
1664 .ndo_tx_timeout = ravb_tx_timeout,
1665 .ndo_do_ioctl = ravb_do_ioctl,
1666 .ndo_validate_addr = eth_validate_addr,
1667 .ndo_set_mac_address = eth_mac_addr,
1668 .ndo_change_mtu = eth_change_mtu,
1671 /* MDIO bus init function */
1672 static int ravb_mdio_init(struct ravb_private *priv)
1674 struct platform_device *pdev = priv->pdev;
1675 struct device *dev = &pdev->dev;
1679 priv->mdiobb.ops = &bb_ops;
1681 /* MII controller setting */
1682 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1686 /* Hook up MII support for ethtool */
1687 priv->mii_bus->name = "ravb_mii";
1688 priv->mii_bus->parent = dev;
1689 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1690 pdev->name, pdev->id);
1692 /* Register MDIO bus */
1693 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1700 free_mdio_bitbang(priv->mii_bus);
1704 /* MDIO bus release function */
1705 static int ravb_mdio_release(struct ravb_private *priv)
1707 /* Unregister mdio bus */
1708 mdiobus_unregister(priv->mii_bus);
1710 /* Free bitbang info */
1711 free_mdio_bitbang(priv->mii_bus);
1716 static const struct of_device_id ravb_match_table[] = {
1717 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1718 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1719 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1722 MODULE_DEVICE_TABLE(of, ravb_match_table);
1724 static int ravb_probe(struct platform_device *pdev)
1726 struct device_node *np = pdev->dev.of_node;
1727 const struct of_device_id *match;
1728 struct ravb_private *priv;
1729 enum ravb_chip_id chip_id;
1730 struct net_device *ndev;
1732 struct resource *res;
1736 "this driver is required to be instantiated from device tree\n");
1740 /* Get base address */
1741 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1743 dev_err(&pdev->dev, "invalid resource\n");
1747 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
1748 NUM_TX_QUEUE, NUM_RX_QUEUE);
1752 pm_runtime_enable(&pdev->dev);
1753 pm_runtime_get_sync(&pdev->dev);
1755 /* The Ether-specific entries in the device structure. */
1756 ndev->base_addr = res->start;
1759 match = of_match_device(of_match_ptr(ravb_match_table), &pdev->dev);
1760 chip_id = (enum ravb_chip_id)match->data;
1762 if (chip_id == RCAR_GEN3)
1763 irq = platform_get_irq_byname(pdev, "ch22");
1765 irq = platform_get_irq(pdev, 0);
1772 SET_NETDEV_DEV(ndev, &pdev->dev);
1774 priv = netdev_priv(ndev);
1777 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
1778 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
1779 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
1780 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
1781 priv->addr = devm_ioremap_resource(&pdev->dev, res);
1782 if (IS_ERR(priv->addr)) {
1783 error = PTR_ERR(priv->addr);
1787 spin_lock_init(&priv->lock);
1788 INIT_WORK(&priv->work, ravb_tx_timeout_work);
1790 priv->phy_interface = of_get_phy_mode(np);
1792 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
1793 priv->avb_link_active_low =
1794 of_property_read_bool(np, "renesas,ether-link-active-low");
1796 if (chip_id == RCAR_GEN3) {
1797 irq = platform_get_irq_byname(pdev, "ch24");
1802 priv->emac_irq = irq;
1805 priv->chip_id = chip_id;
1808 ndev->netdev_ops = &ravb_netdev_ops;
1809 ndev->ethtool_ops = &ravb_ethtool_ops;
1811 /* Set AVB config mode */
1812 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG,
1815 /* Set CSEL value */
1816 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) | CCC_CSEL_HPB,
1820 ravb_write(ndev, ((1000 << 20) / 130) & GTI_TIV, GTI);
1822 /* Request GTI loading */
1823 ravb_write(ndev, ravb_read(ndev, GCCR) | GCCR_LTI, GCCR);
1825 /* Allocate descriptor base address table */
1826 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
1827 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
1828 &priv->desc_bat_dma, GFP_KERNEL);
1829 if (!priv->desc_bat) {
1831 "Cannot allocate desc base address table (size %d bytes)\n",
1832 priv->desc_bat_size);
1836 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
1837 priv->desc_bat[q].die_dt = DT_EOS;
1838 ravb_write(ndev, priv->desc_bat_dma, DBAT);
1840 /* Initialise HW timestamp list */
1841 INIT_LIST_HEAD(&priv->ts_skb_list);
1843 /* Debug message level */
1844 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
1846 /* Read and set MAC address */
1847 ravb_read_mac_address(ndev, of_get_mac_address(np));
1848 if (!is_valid_ether_addr(ndev->dev_addr)) {
1849 dev_warn(&pdev->dev,
1850 "no valid MAC address supplied, using a random one\n");
1851 eth_hw_addr_random(ndev);
1855 error = ravb_mdio_init(priv);
1857 dev_err(&pdev->dev, "failed to initialize MDIO\n");
1861 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
1862 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
1864 /* Network device register */
1865 error = register_netdev(ndev);
1869 /* Print device information */
1870 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
1871 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
1873 platform_set_drvdata(pdev, ndev);
1878 netif_napi_del(&priv->napi[RAVB_NC]);
1879 netif_napi_del(&priv->napi[RAVB_BE]);
1880 ravb_mdio_release(priv);
1882 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
1883 priv->desc_bat_dma);
1888 pm_runtime_put(&pdev->dev);
1889 pm_runtime_disable(&pdev->dev);
1893 static int ravb_remove(struct platform_device *pdev)
1895 struct net_device *ndev = platform_get_drvdata(pdev);
1896 struct ravb_private *priv = netdev_priv(ndev);
1898 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
1899 priv->desc_bat_dma);
1900 /* Set reset mode */
1901 ravb_write(ndev, CCC_OPC_RESET, CCC);
1902 pm_runtime_put_sync(&pdev->dev);
1903 unregister_netdev(ndev);
1904 netif_napi_del(&priv->napi[RAVB_NC]);
1905 netif_napi_del(&priv->napi[RAVB_BE]);
1906 ravb_mdio_release(priv);
1907 pm_runtime_disable(&pdev->dev);
1909 platform_set_drvdata(pdev, NULL);
1915 static int ravb_runtime_nop(struct device *dev)
1917 /* Runtime PM callback shared between ->runtime_suspend()
1918 * and ->runtime_resume(). Simply returns success.
1920 * This driver re-initializes all registers after
1921 * pm_runtime_get_sync() anyway so there is no need
1922 * to save and restore registers here.
1927 static const struct dev_pm_ops ravb_dev_pm_ops = {
1928 .runtime_suspend = ravb_runtime_nop,
1929 .runtime_resume = ravb_runtime_nop,
1932 #define RAVB_PM_OPS (&ravb_dev_pm_ops)
1934 #define RAVB_PM_OPS NULL
1937 static struct platform_driver ravb_driver = {
1938 .probe = ravb_probe,
1939 .remove = ravb_remove,
1943 .of_match_table = ravb_match_table,
1947 module_platform_driver(ravb_driver);
1949 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
1950 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
1951 MODULE_LICENSE("GPL v2");