1 // SPDX-License-Identifier: GPL-2.0
2 /* Renesas Ethernet AVB device driver
4 * Copyright (C) 2014-2019 Renesas Electronics Corporation
5 * Copyright (C) 2015 Renesas Solutions Corp.
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
8 * Based on the SuperH Ethernet driver
11 #include <linux/cache.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_vlan.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/net_tstamp.h>
24 #include <linux/of_device.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_mdio.h>
27 #include <linux/of_net.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/sys_soc.h>
33 #include <asm/div64.h>
37 #define RAVB_DEF_MSG_ENABLE \
43 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
48 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
53 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
59 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
63 for (i = 0; i < 10000; i++) {
64 if ((ravb_read(ndev, reg) & mask) == value)
71 static int ravb_config(struct net_device *ndev)
76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
77 /* Check if the operating mode is changed to the config mode */
78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
80 netdev_err(ndev, "failed to switch device to config mode\n");
85 static void ravb_set_rate(struct net_device *ndev)
87 struct ravb_private *priv = netdev_priv(ndev);
89 switch (priv->speed) {
90 case 100: /* 100BASE */
91 ravb_write(ndev, GECMR_SPEED_100, GECMR);
93 case 1000: /* 1000BASE */
94 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
99 static void ravb_set_buffer_align(struct sk_buff *skb)
101 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
104 skb_reserve(skb, RAVB_ALIGN - reserve);
107 /* Get MAC address from the MAC address registers
109 * Ethernet AVB device doesn't have ROM for MAC address.
110 * This function gets the MAC address that was used by a bootloader.
112 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
115 ether_addr_copy(ndev->dev_addr, mac);
117 u32 mahr = ravb_read(ndev, MAHR);
118 u32 malr = ravb_read(ndev, MALR);
120 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
121 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
122 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
123 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
124 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
125 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
129 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
131 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
134 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
137 /* MDC pin control */
138 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
140 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
143 /* Data I/O pin control */
144 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
146 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
150 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
152 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
156 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
158 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
161 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
164 /* MDIO bus control struct */
165 static const struct mdiobb_ops bb_ops = {
166 .owner = THIS_MODULE,
167 .set_mdc = ravb_set_mdc,
168 .set_mdio_dir = ravb_set_mdio_dir,
169 .set_mdio_data = ravb_set_mdio_data,
170 .get_mdio_data = ravb_get_mdio_data,
173 /* Free TX skb function for AVB-IP */
174 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
176 struct ravb_private *priv = netdev_priv(ndev);
177 struct net_device_stats *stats = &priv->stats[q];
178 int num_tx_desc = priv->num_tx_desc;
179 struct ravb_tx_desc *desc;
184 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
187 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
189 desc = &priv->tx_ring[q][entry];
190 txed = desc->die_dt == DT_FEMPTY;
191 if (free_txed_only && !txed)
193 /* Descriptor type must be checked before all other reads */
195 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
196 /* Free the original skb. */
197 if (priv->tx_skb[q][entry / num_tx_desc]) {
198 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
199 size, DMA_TO_DEVICE);
200 /* Last packet descriptor? */
201 if (entry % num_tx_desc == num_tx_desc - 1) {
202 entry /= num_tx_desc;
203 dev_kfree_skb_any(priv->tx_skb[q][entry]);
204 priv->tx_skb[q][entry] = NULL;
211 stats->tx_bytes += size;
212 desc->die_dt = DT_EEMPTY;
217 /* Free skb's and DMA buffers for Ethernet AVB */
218 static void ravb_ring_free(struct net_device *ndev, int q)
220 struct ravb_private *priv = netdev_priv(ndev);
221 int num_tx_desc = priv->num_tx_desc;
225 if (priv->rx_ring[q]) {
226 for (i = 0; i < priv->num_rx_ring[q]; i++) {
227 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
229 if (!dma_mapping_error(ndev->dev.parent,
230 le32_to_cpu(desc->dptr)))
231 dma_unmap_single(ndev->dev.parent,
232 le32_to_cpu(desc->dptr),
236 ring_size = sizeof(struct ravb_ex_rx_desc) *
237 (priv->num_rx_ring[q] + 1);
238 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
239 priv->rx_desc_dma[q]);
240 priv->rx_ring[q] = NULL;
243 if (priv->tx_ring[q]) {
244 ravb_tx_free(ndev, q, false);
246 ring_size = sizeof(struct ravb_tx_desc) *
247 (priv->num_tx_ring[q] * num_tx_desc + 1);
248 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
249 priv->tx_desc_dma[q]);
250 priv->tx_ring[q] = NULL;
253 /* Free RX skb ringbuffer */
254 if (priv->rx_skb[q]) {
255 for (i = 0; i < priv->num_rx_ring[q]; i++)
256 dev_kfree_skb(priv->rx_skb[q][i]);
258 kfree(priv->rx_skb[q]);
259 priv->rx_skb[q] = NULL;
261 /* Free aligned TX buffers */
262 kfree(priv->tx_align[q]);
263 priv->tx_align[q] = NULL;
265 /* Free TX skb ringbuffer.
266 * SKBs are freed by ravb_tx_free() call above.
268 kfree(priv->tx_skb[q]);
269 priv->tx_skb[q] = NULL;
272 /* Format skb and descriptor buffer for Ethernet AVB */
273 static void ravb_ring_format(struct net_device *ndev, int q)
275 struct ravb_private *priv = netdev_priv(ndev);
276 int num_tx_desc = priv->num_tx_desc;
277 struct ravb_ex_rx_desc *rx_desc;
278 struct ravb_tx_desc *tx_desc;
279 struct ravb_desc *desc;
280 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
281 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
288 priv->dirty_rx[q] = 0;
289 priv->dirty_tx[q] = 0;
291 memset(priv->rx_ring[q], 0, rx_ring_size);
292 /* Build RX ring buffer */
293 for (i = 0; i < priv->num_rx_ring[q]; i++) {
295 rx_desc = &priv->rx_ring[q][i];
296 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
297 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
300 /* We just set the data size to 0 for a failed mapping which
301 * should prevent DMA from happening...
303 if (dma_mapping_error(ndev->dev.parent, dma_addr))
304 rx_desc->ds_cc = cpu_to_le16(0);
305 rx_desc->dptr = cpu_to_le32(dma_addr);
306 rx_desc->die_dt = DT_FEMPTY;
308 rx_desc = &priv->rx_ring[q][i];
309 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
310 rx_desc->die_dt = DT_LINKFIX; /* type */
312 memset(priv->tx_ring[q], 0, tx_ring_size);
313 /* Build TX ring buffer */
314 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
316 tx_desc->die_dt = DT_EEMPTY;
317 if (num_tx_desc > 1) {
319 tx_desc->die_dt = DT_EEMPTY;
322 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
323 tx_desc->die_dt = DT_LINKFIX; /* type */
325 /* RX descriptor base address for best effort */
326 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
327 desc->die_dt = DT_LINKFIX; /* type */
328 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
330 /* TX descriptor base address for best effort */
331 desc = &priv->desc_bat[q];
332 desc->die_dt = DT_LINKFIX; /* type */
333 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
336 /* Init skb and descriptor buffer for Ethernet AVB */
337 static int ravb_ring_init(struct net_device *ndev, int q)
339 struct ravb_private *priv = netdev_priv(ndev);
340 int num_tx_desc = priv->num_tx_desc;
345 /* Allocate RX and TX skb rings */
346 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
347 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
348 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
349 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
350 if (!priv->rx_skb[q] || !priv->tx_skb[q])
353 for (i = 0; i < priv->num_rx_ring[q]; i++) {
354 skb = netdev_alloc_skb(ndev, RX_BUF_SZ + RAVB_ALIGN - 1);
357 ravb_set_buffer_align(skb);
358 priv->rx_skb[q][i] = skb;
361 if (num_tx_desc > 1) {
362 /* Allocate rings for the aligned buffers */
363 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
364 DPTR_ALIGN - 1, GFP_KERNEL);
365 if (!priv->tx_align[q])
369 /* Allocate all RX descriptors. */
370 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
371 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
372 &priv->rx_desc_dma[q],
374 if (!priv->rx_ring[q])
377 priv->dirty_rx[q] = 0;
379 /* Allocate all TX descriptors. */
380 ring_size = sizeof(struct ravb_tx_desc) *
381 (priv->num_tx_ring[q] * num_tx_desc + 1);
382 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
383 &priv->tx_desc_dma[q],
385 if (!priv->tx_ring[q])
391 ravb_ring_free(ndev, q);
396 /* E-MAC init function */
397 static void ravb_emac_init(struct net_device *ndev)
399 /* Receive frame limit set register */
400 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
402 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
403 ravb_write(ndev, ECMR_ZPF | ECMR_DM |
404 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
405 ECMR_TE | ECMR_RE, ECMR);
409 /* Set MAC address */
411 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
412 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
414 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
416 /* E-MAC status register clear */
417 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
419 /* E-MAC interrupt enable register */
420 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
423 /* Device init function for Ethernet AVB */
424 static int ravb_dmac_init(struct net_device *ndev)
426 struct ravb_private *priv = netdev_priv(ndev);
429 /* Set CONFIG mode */
430 error = ravb_config(ndev);
434 error = ravb_ring_init(ndev, RAVB_BE);
437 error = ravb_ring_init(ndev, RAVB_NC);
439 ravb_ring_free(ndev, RAVB_BE);
443 /* Descriptor format */
444 ravb_ring_format(ndev, RAVB_BE);
445 ravb_ring_format(ndev, RAVB_NC);
449 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
452 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
454 /* Timestamp enable */
455 ravb_write(ndev, TCCR_TFEN, TCCR);
457 /* Interrupt init: */
458 if (priv->chip_id == RCAR_GEN3) {
460 ravb_write(ndev, 0, DIL);
461 /* Set queue specific interrupt */
462 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
465 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
466 /* Disable FIFO full warning */
467 ravb_write(ndev, 0, RIC1);
468 /* Receive FIFO full error, descriptor empty */
469 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
470 /* Frame transmitted, timestamp FIFO updated */
471 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
473 /* Setting the control will start the AVB-DMAC process. */
474 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
479 static void ravb_get_tx_tstamp(struct net_device *ndev)
481 struct ravb_private *priv = netdev_priv(ndev);
482 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
483 struct skb_shared_hwtstamps shhwtstamps;
485 struct timespec64 ts;
490 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
492 tfa2 = ravb_read(ndev, TFA2);
493 tfa_tag = (tfa2 & TFA2_TST) >> 16;
494 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
495 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
496 ravb_read(ndev, TFA1);
497 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
498 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
499 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
503 list_del(&ts_skb->list);
505 if (tag == tfa_tag) {
506 skb_tstamp_tx(skb, &shhwtstamps);
507 dev_consume_skb_any(skb);
510 dev_kfree_skb_any(skb);
513 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
517 static void ravb_rx_csum(struct sk_buff *skb)
521 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes
522 * appended to packet data
524 if (unlikely(skb->len < sizeof(__sum16)))
526 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
527 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
528 skb->ip_summed = CHECKSUM_COMPLETE;
529 skb_trim(skb, skb->len - sizeof(__sum16));
532 /* Packet receive function for Ethernet AVB */
533 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
535 struct ravb_private *priv = netdev_priv(ndev);
536 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
537 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
539 struct net_device_stats *stats = &priv->stats[q];
540 struct ravb_ex_rx_desc *desc;
543 struct timespec64 ts;
548 boguscnt = min(boguscnt, *quota);
550 desc = &priv->rx_ring[q][entry];
551 while (desc->die_dt != DT_FEMPTY) {
552 /* Descriptor type must be checked before all other reads */
554 desc_status = desc->msc;
555 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
560 /* We use 0-byte descriptors to mark the DMA mapping errors */
564 if (desc_status & MSC_MC)
567 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
570 if (desc_status & MSC_CRC)
571 stats->rx_crc_errors++;
572 if (desc_status & MSC_RFE)
573 stats->rx_frame_errors++;
574 if (desc_status & (MSC_RTLF | MSC_RTSF))
575 stats->rx_length_errors++;
576 if (desc_status & MSC_CEEF)
577 stats->rx_missed_errors++;
579 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
581 skb = priv->rx_skb[q][entry];
582 priv->rx_skb[q][entry] = NULL;
583 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
586 get_ts &= (q == RAVB_NC) ?
587 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
588 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
590 struct skb_shared_hwtstamps *shhwtstamps;
592 shhwtstamps = skb_hwtstamps(skb);
593 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
594 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
595 32) | le32_to_cpu(desc->ts_sl);
596 ts.tv_nsec = le32_to_cpu(desc->ts_n);
597 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
600 skb_put(skb, pkt_len);
601 skb->protocol = eth_type_trans(skb, ndev);
602 if (ndev->features & NETIF_F_RXCSUM)
604 napi_gro_receive(&priv->napi[q], skb);
606 stats->rx_bytes += pkt_len;
609 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
610 desc = &priv->rx_ring[q][entry];
613 /* Refill the RX ring buffers. */
614 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
615 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
616 desc = &priv->rx_ring[q][entry];
617 desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
619 if (!priv->rx_skb[q][entry]) {
620 skb = netdev_alloc_skb(ndev,
624 break; /* Better luck next round. */
625 ravb_set_buffer_align(skb);
626 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
627 le16_to_cpu(desc->ds_cc),
629 skb_checksum_none_assert(skb);
630 /* We just set the data size to 0 for a failed mapping
631 * which should prevent DMA from happening...
633 if (dma_mapping_error(ndev->dev.parent, dma_addr))
634 desc->ds_cc = cpu_to_le16(0);
635 desc->dptr = cpu_to_le32(dma_addr);
636 priv->rx_skb[q][entry] = skb;
638 /* Descriptor type must be set after all the above writes */
640 desc->die_dt = DT_FEMPTY;
643 *quota -= limit - (++boguscnt);
645 return boguscnt <= 0;
648 static void ravb_rcv_snd_disable(struct net_device *ndev)
650 /* Disable TX and RX */
651 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
654 static void ravb_rcv_snd_enable(struct net_device *ndev)
656 /* Enable TX and RX */
657 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
660 /* function for waiting dma process finished */
661 static int ravb_stop_dma(struct net_device *ndev)
665 /* Wait for stopping the hardware TX process */
666 error = ravb_wait(ndev, TCCR,
667 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
671 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
676 /* Stop the E-MAC's RX/TX processes. */
677 ravb_rcv_snd_disable(ndev);
679 /* Wait for stopping the RX DMA process */
680 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
684 /* Stop AVB-DMAC process */
685 return ravb_config(ndev);
688 /* E-MAC interrupt handler */
689 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
691 struct ravb_private *priv = netdev_priv(ndev);
694 ecsr = ravb_read(ndev, ECSR);
695 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
698 pm_wakeup_event(&priv->pdev->dev, 0);
700 ndev->stats.tx_carrier_errors++;
701 if (ecsr & ECSR_LCHNG) {
703 if (priv->no_avb_link)
705 psr = ravb_read(ndev, PSR);
706 if (priv->avb_link_active_low)
708 if (!(psr & PSR_LMON)) {
709 /* DIsable RX and TX */
710 ravb_rcv_snd_disable(ndev);
712 /* Enable RX and TX */
713 ravb_rcv_snd_enable(ndev);
718 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
720 struct net_device *ndev = dev_id;
721 struct ravb_private *priv = netdev_priv(ndev);
723 spin_lock(&priv->lock);
724 ravb_emac_interrupt_unlocked(ndev);
725 spin_unlock(&priv->lock);
729 /* Error interrupt handler */
730 static void ravb_error_interrupt(struct net_device *ndev)
732 struct ravb_private *priv = netdev_priv(ndev);
735 eis = ravb_read(ndev, EIS);
736 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);
738 ris2 = ravb_read(ndev, RIS2);
739 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED),
742 /* Receive Descriptor Empty int */
743 if (ris2 & RIS2_QFF0)
744 priv->stats[RAVB_BE].rx_over_errors++;
746 /* Receive Descriptor Empty int */
747 if (ris2 & RIS2_QFF1)
748 priv->stats[RAVB_NC].rx_over_errors++;
750 /* Receive FIFO Overflow int */
751 if (ris2 & RIS2_RFFF)
752 priv->rx_fifo_errors++;
756 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
758 struct ravb_private *priv = netdev_priv(ndev);
759 u32 ris0 = ravb_read(ndev, RIS0);
760 u32 ric0 = ravb_read(ndev, RIC0);
761 u32 tis = ravb_read(ndev, TIS);
762 u32 tic = ravb_read(ndev, TIC);
764 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
765 if (napi_schedule_prep(&priv->napi[q])) {
766 /* Mask RX and TX interrupts */
767 if (priv->chip_id == RCAR_GEN2) {
768 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
769 ravb_write(ndev, tic & ~BIT(q), TIC);
771 ravb_write(ndev, BIT(q), RID0);
772 ravb_write(ndev, BIT(q), TID);
774 __napi_schedule(&priv->napi[q]);
777 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
780 " tx status 0x%08x, tx mask 0x%08x.\n",
788 static bool ravb_timestamp_interrupt(struct net_device *ndev)
790 u32 tis = ravb_read(ndev, TIS);
792 if (tis & TIS_TFUF) {
793 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);
794 ravb_get_tx_tstamp(ndev);
800 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
802 struct net_device *ndev = dev_id;
803 struct ravb_private *priv = netdev_priv(ndev);
804 irqreturn_t result = IRQ_NONE;
807 spin_lock(&priv->lock);
808 /* Get interrupt status */
809 iss = ravb_read(ndev, ISS);
811 /* Received and transmitted interrupts */
812 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
815 /* Timestamp updated */
816 if (ravb_timestamp_interrupt(ndev))
817 result = IRQ_HANDLED;
819 /* Network control and best effort queue RX/TX */
820 for (q = RAVB_NC; q >= RAVB_BE; q--) {
821 if (ravb_queue_interrupt(ndev, q))
822 result = IRQ_HANDLED;
826 /* E-MAC status summary */
828 ravb_emac_interrupt_unlocked(ndev);
829 result = IRQ_HANDLED;
832 /* Error status summary */
834 ravb_error_interrupt(ndev);
835 result = IRQ_HANDLED;
838 /* gPTP interrupt status summary */
839 if (iss & ISS_CGIS) {
840 ravb_ptp_interrupt(ndev);
841 result = IRQ_HANDLED;
844 spin_unlock(&priv->lock);
848 /* Timestamp/Error/gPTP interrupt handler */
849 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
851 struct net_device *ndev = dev_id;
852 struct ravb_private *priv = netdev_priv(ndev);
853 irqreturn_t result = IRQ_NONE;
856 spin_lock(&priv->lock);
857 /* Get interrupt status */
858 iss = ravb_read(ndev, ISS);
860 /* Timestamp updated */
861 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
862 result = IRQ_HANDLED;
864 /* Error status summary */
866 ravb_error_interrupt(ndev);
867 result = IRQ_HANDLED;
870 /* gPTP interrupt status summary */
871 if (iss & ISS_CGIS) {
872 ravb_ptp_interrupt(ndev);
873 result = IRQ_HANDLED;
876 spin_unlock(&priv->lock);
880 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
882 struct net_device *ndev = dev_id;
883 struct ravb_private *priv = netdev_priv(ndev);
884 irqreturn_t result = IRQ_NONE;
886 spin_lock(&priv->lock);
888 /* Network control/Best effort queue RX/TX */
889 if (ravb_queue_interrupt(ndev, q))
890 result = IRQ_HANDLED;
892 spin_unlock(&priv->lock);
896 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
898 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
901 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
903 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
906 static int ravb_poll(struct napi_struct *napi, int budget)
908 struct net_device *ndev = napi->dev;
909 struct ravb_private *priv = netdev_priv(ndev);
911 int q = napi - priv->napi;
916 /* Processing RX Descriptor Ring */
917 /* Clear RX interrupt */
918 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);
919 unmask = !ravb_rx(ndev, "a, q);
921 /* Processing RX Descriptor Ring */
922 spin_lock_irqsave(&priv->lock, flags);
923 /* Clear TX interrupt */
924 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);
925 ravb_tx_free(ndev, q, true);
926 netif_wake_subqueue(ndev, q);
927 spin_unlock_irqrestore(&priv->lock, flags);
934 /* Re-enable RX/TX interrupts */
935 spin_lock_irqsave(&priv->lock, flags);
936 if (priv->chip_id == RCAR_GEN2) {
937 ravb_modify(ndev, RIC0, mask, mask);
938 ravb_modify(ndev, TIC, mask, mask);
940 ravb_write(ndev, mask, RIE0);
941 ravb_write(ndev, mask, TIE);
943 spin_unlock_irqrestore(&priv->lock, flags);
945 /* Receive error message handling */
946 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
947 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
948 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
949 ndev->stats.rx_over_errors = priv->rx_over_errors;
950 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
951 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
953 return budget - quota;
956 /* PHY state control function */
957 static void ravb_adjust_link(struct net_device *ndev)
959 struct ravb_private *priv = netdev_priv(ndev);
960 struct phy_device *phydev = ndev->phydev;
961 bool new_state = false;
964 spin_lock_irqsave(&priv->lock, flags);
966 /* Disable TX and RX right over here, if E-MAC change is ignored */
967 if (priv->no_avb_link)
968 ravb_rcv_snd_disable(ndev);
971 if (phydev->speed != priv->speed) {
973 priv->speed = phydev->speed;
977 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
979 priv->link = phydev->link;
981 } else if (priv->link) {
987 /* Enable TX and RX right over here, if E-MAC change is ignored */
988 if (priv->no_avb_link && phydev->link)
989 ravb_rcv_snd_enable(ndev);
991 spin_unlock_irqrestore(&priv->lock, flags);
993 if (new_state && netif_msg_link(priv))
994 phy_print_status(phydev);
997 static const struct soc_device_attribute r8a7795es10[] = {
998 { .soc_id = "r8a7795", .revision = "ES1.0", },
1002 /* PHY init function */
1003 static int ravb_phy_init(struct net_device *ndev)
1005 struct device_node *np = ndev->dev.parent->of_node;
1006 struct ravb_private *priv = netdev_priv(ndev);
1007 struct phy_device *phydev;
1008 struct device_node *pn;
1009 phy_interface_t iface;
1015 /* Try connecting to PHY */
1016 pn = of_parse_phandle(np, "phy-handle", 0);
1018 /* In the case of a fixed PHY, the DT node associated
1019 * to the PHY is the Ethernet MAC DT node.
1021 if (of_phy_is_fixed_link(np)) {
1022 err = of_phy_register_fixed_link(np);
1026 pn = of_node_get(np);
1029 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII
1030 : priv->phy_interface;
1031 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface);
1034 netdev_err(ndev, "failed to connect PHY\n");
1036 goto err_deregister_fixed_link;
1039 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0
1042 if (soc_device_match(r8a7795es10)) {
1043 err = phy_set_max_speed(phydev, SPEED_100);
1045 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
1046 goto err_phy_disconnect;
1049 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1052 /* 10BASE, Pause and Asym Pause is not supported */
1053 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1054 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
1055 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT);
1056 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT);
1058 /* Half Duplex is not supported */
1059 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1060 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1062 phy_attached_info(phydev);
1067 phy_disconnect(phydev);
1068 err_deregister_fixed_link:
1069 if (of_phy_is_fixed_link(np))
1070 of_phy_deregister_fixed_link(np);
1075 /* PHY control start function */
1076 static int ravb_phy_start(struct net_device *ndev)
1080 error = ravb_phy_init(ndev);
1084 phy_start(ndev->phydev);
1089 static u32 ravb_get_msglevel(struct net_device *ndev)
1091 struct ravb_private *priv = netdev_priv(ndev);
1093 return priv->msg_enable;
1096 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1098 struct ravb_private *priv = netdev_priv(ndev);
1100 priv->msg_enable = value;
1103 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1104 "rx_queue_0_current",
1105 "tx_queue_0_current",
1108 "rx_queue_0_packets",
1109 "tx_queue_0_packets",
1112 "rx_queue_0_mcast_packets",
1113 "rx_queue_0_errors",
1114 "rx_queue_0_crc_errors",
1115 "rx_queue_0_frame_errors",
1116 "rx_queue_0_length_errors",
1117 "rx_queue_0_missed_errors",
1118 "rx_queue_0_over_errors",
1120 "rx_queue_1_current",
1121 "tx_queue_1_current",
1124 "rx_queue_1_packets",
1125 "tx_queue_1_packets",
1128 "rx_queue_1_mcast_packets",
1129 "rx_queue_1_errors",
1130 "rx_queue_1_crc_errors",
1131 "rx_queue_1_frame_errors",
1132 "rx_queue_1_length_errors",
1133 "rx_queue_1_missed_errors",
1134 "rx_queue_1_over_errors",
1137 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1139 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1143 return RAVB_STATS_LEN;
1149 static void ravb_get_ethtool_stats(struct net_device *ndev,
1150 struct ethtool_stats *estats, u64 *data)
1152 struct ravb_private *priv = netdev_priv(ndev);
1156 /* Device-specific stats */
1157 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1158 struct net_device_stats *stats = &priv->stats[q];
1160 data[i++] = priv->cur_rx[q];
1161 data[i++] = priv->cur_tx[q];
1162 data[i++] = priv->dirty_rx[q];
1163 data[i++] = priv->dirty_tx[q];
1164 data[i++] = stats->rx_packets;
1165 data[i++] = stats->tx_packets;
1166 data[i++] = stats->rx_bytes;
1167 data[i++] = stats->tx_bytes;
1168 data[i++] = stats->multicast;
1169 data[i++] = stats->rx_errors;
1170 data[i++] = stats->rx_crc_errors;
1171 data[i++] = stats->rx_frame_errors;
1172 data[i++] = stats->rx_length_errors;
1173 data[i++] = stats->rx_missed_errors;
1174 data[i++] = stats->rx_over_errors;
1178 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1180 switch (stringset) {
1182 memcpy(data, ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1187 static void ravb_get_ringparam(struct net_device *ndev,
1188 struct ethtool_ringparam *ring)
1190 struct ravb_private *priv = netdev_priv(ndev);
1192 ring->rx_max_pending = BE_RX_RING_MAX;
1193 ring->tx_max_pending = BE_TX_RING_MAX;
1194 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1195 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1198 static int ravb_set_ringparam(struct net_device *ndev,
1199 struct ethtool_ringparam *ring)
1201 struct ravb_private *priv = netdev_priv(ndev);
1204 if (ring->tx_pending > BE_TX_RING_MAX ||
1205 ring->rx_pending > BE_RX_RING_MAX ||
1206 ring->tx_pending < BE_TX_RING_MIN ||
1207 ring->rx_pending < BE_RX_RING_MIN)
1209 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1212 if (netif_running(ndev)) {
1213 netif_device_detach(ndev);
1214 /* Stop PTP Clock driver */
1215 if (priv->chip_id == RCAR_GEN2)
1216 ravb_ptp_stop(ndev);
1217 /* Wait for DMA stopping */
1218 error = ravb_stop_dma(ndev);
1221 "cannot set ringparam! Any AVB processes are still running?\n");
1224 synchronize_irq(ndev->irq);
1226 /* Free all the skb's in the RX queue and the DMA buffers. */
1227 ravb_ring_free(ndev, RAVB_BE);
1228 ravb_ring_free(ndev, RAVB_NC);
1231 /* Set new parameters */
1232 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1233 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1235 if (netif_running(ndev)) {
1236 error = ravb_dmac_init(ndev);
1239 "%s: ravb_dmac_init() failed, error %d\n",
1244 ravb_emac_init(ndev);
1246 /* Initialise PTP Clock driver */
1247 if (priv->chip_id == RCAR_GEN2)
1248 ravb_ptp_init(ndev, priv->pdev);
1250 netif_device_attach(ndev);
1256 static int ravb_get_ts_info(struct net_device *ndev,
1257 struct ethtool_ts_info *info)
1259 struct ravb_private *priv = netdev_priv(ndev);
1261 info->so_timestamping =
1262 SOF_TIMESTAMPING_TX_SOFTWARE |
1263 SOF_TIMESTAMPING_RX_SOFTWARE |
1264 SOF_TIMESTAMPING_SOFTWARE |
1265 SOF_TIMESTAMPING_TX_HARDWARE |
1266 SOF_TIMESTAMPING_RX_HARDWARE |
1267 SOF_TIMESTAMPING_RAW_HARDWARE;
1268 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1270 (1 << HWTSTAMP_FILTER_NONE) |
1271 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1272 (1 << HWTSTAMP_FILTER_ALL);
1273 info->phc_index = ptp_clock_index(priv->ptp.clock);
1278 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1280 struct ravb_private *priv = netdev_priv(ndev);
1282 wol->supported = WAKE_MAGIC;
1283 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
1286 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1288 struct ravb_private *priv = netdev_priv(ndev);
1290 if (wol->wolopts & ~WAKE_MAGIC)
1293 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
1295 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled);
1300 static const struct ethtool_ops ravb_ethtool_ops = {
1301 .nway_reset = phy_ethtool_nway_reset,
1302 .get_msglevel = ravb_get_msglevel,
1303 .set_msglevel = ravb_set_msglevel,
1304 .get_link = ethtool_op_get_link,
1305 .get_strings = ravb_get_strings,
1306 .get_ethtool_stats = ravb_get_ethtool_stats,
1307 .get_sset_count = ravb_get_sset_count,
1308 .get_ringparam = ravb_get_ringparam,
1309 .set_ringparam = ravb_set_ringparam,
1310 .get_ts_info = ravb_get_ts_info,
1311 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1312 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1313 .get_wol = ravb_get_wol,
1314 .set_wol = ravb_set_wol,
1317 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1318 struct net_device *ndev, struct device *dev,
1324 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1327 error = request_irq(irq, handler, 0, name, ndev);
1329 netdev_err(ndev, "cannot request IRQ %s\n", name);
1334 /* Network device open function for Ethernet AVB */
1335 static int ravb_open(struct net_device *ndev)
1337 struct ravb_private *priv = netdev_priv(ndev);
1338 struct platform_device *pdev = priv->pdev;
1339 struct device *dev = &pdev->dev;
1342 napi_enable(&priv->napi[RAVB_BE]);
1343 napi_enable(&priv->napi[RAVB_NC]);
1345 if (priv->chip_id == RCAR_GEN2) {
1346 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1349 netdev_err(ndev, "cannot request IRQ\n");
1353 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1357 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1361 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1362 ndev, dev, "ch0:rx_be");
1364 goto out_free_irq_emac;
1365 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1366 ndev, dev, "ch18:tx_be");
1368 goto out_free_irq_be_rx;
1369 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1370 ndev, dev, "ch1:rx_nc");
1372 goto out_free_irq_be_tx;
1373 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1374 ndev, dev, "ch19:tx_nc");
1376 goto out_free_irq_nc_rx;
1380 error = ravb_dmac_init(ndev);
1382 goto out_free_irq_nc_tx;
1383 ravb_emac_init(ndev);
1385 /* Initialise PTP Clock driver */
1386 if (priv->chip_id == RCAR_GEN2)
1387 ravb_ptp_init(ndev, priv->pdev);
1389 /* PHY control start */
1390 error = ravb_phy_start(ndev);
1394 netif_tx_start_all_queues(ndev);
1399 /* Stop PTP Clock driver */
1400 if (priv->chip_id == RCAR_GEN2)
1401 ravb_ptp_stop(ndev);
1403 if (priv->chip_id == RCAR_GEN2)
1405 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1407 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1409 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1411 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1413 free_irq(priv->emac_irq, ndev);
1415 free_irq(ndev->irq, ndev);
1417 napi_disable(&priv->napi[RAVB_NC]);
1418 napi_disable(&priv->napi[RAVB_BE]);
1422 /* Timeout function for Ethernet AVB */
1423 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1425 struct ravb_private *priv = netdev_priv(ndev);
1427 netif_err(priv, tx_err, ndev,
1428 "transmit timed out, status %08x, resetting...\n",
1429 ravb_read(ndev, ISS));
1431 /* tx_errors count up */
1432 ndev->stats.tx_errors++;
1434 schedule_work(&priv->work);
1437 static void ravb_tx_timeout_work(struct work_struct *work)
1439 struct ravb_private *priv = container_of(work, struct ravb_private,
1441 struct net_device *ndev = priv->ndev;
1444 if (!rtnl_trylock()) {
1445 usleep_range(1000, 2000);
1446 schedule_work(&priv->work);
1450 netif_tx_stop_all_queues(ndev);
1452 /* Stop PTP Clock driver */
1453 if (priv->chip_id == RCAR_GEN2)
1454 ravb_ptp_stop(ndev);
1456 /* Wait for DMA stopping */
1457 if (ravb_stop_dma(ndev)) {
1458 /* If ravb_stop_dma() fails, the hardware is still operating
1459 * for TX and/or RX. So, this should not call the following
1460 * functions because ravb_dmac_init() is possible to fail too.
1461 * Also, this should not retry ravb_stop_dma() again and again
1462 * here because it's possible to wait forever. So, this just
1463 * re-enables the TX and RX and skip the following
1464 * re-initialization procedure.
1466 ravb_rcv_snd_enable(ndev);
1470 ravb_ring_free(ndev, RAVB_BE);
1471 ravb_ring_free(ndev, RAVB_NC);
1474 error = ravb_dmac_init(ndev);
1476 /* If ravb_dmac_init() fails, descriptors are freed. So, this
1477 * should return here to avoid re-enabling the TX and RX in
1480 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n",
1484 ravb_emac_init(ndev);
1487 /* Initialise PTP Clock driver */
1488 if (priv->chip_id == RCAR_GEN2)
1489 ravb_ptp_init(ndev, priv->pdev);
1491 netif_tx_start_all_queues(ndev);
1497 /* Packet transmit function for Ethernet AVB */
1498 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1500 struct ravb_private *priv = netdev_priv(ndev);
1501 int num_tx_desc = priv->num_tx_desc;
1502 u16 q = skb_get_queue_mapping(skb);
1503 struct ravb_tstamp_skb *ts_skb;
1504 struct ravb_tx_desc *desc;
1505 unsigned long flags;
1506 dma_addr_t dma_addr;
1511 spin_lock_irqsave(&priv->lock, flags);
1512 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1514 netif_err(priv, tx_queued, ndev,
1515 "still transmitting with the full ring!\n");
1516 netif_stop_subqueue(ndev, q);
1517 spin_unlock_irqrestore(&priv->lock, flags);
1518 return NETDEV_TX_BUSY;
1521 if (skb_put_padto(skb, ETH_ZLEN))
1524 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc);
1525 priv->tx_skb[q][entry / num_tx_desc] = skb;
1527 if (num_tx_desc > 1) {
1528 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1529 entry / num_tx_desc * DPTR_ALIGN;
1530 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1532 /* Zero length DMA descriptors are problematic as they seem
1533 * to terminate DMA transfers. Avoid them by simply using a
1534 * length of DPTR_ALIGN (4) when skb data is aligned to
1537 * As skb is guaranteed to have at least ETH_ZLEN (60)
1538 * bytes of data by the call to skb_put_padto() above this
1539 * is safe with respect to both the length of the first DMA
1540 * descriptor (len) overflowing the available data and the
1541 * length of the second DMA descriptor (skb->len - len)
1547 memcpy(buffer, skb->data, len);
1548 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1550 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1553 desc = &priv->tx_ring[q][entry];
1554 desc->ds_tagl = cpu_to_le16(len);
1555 desc->dptr = cpu_to_le32(dma_addr);
1557 buffer = skb->data + len;
1558 len = skb->len - len;
1559 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1561 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1566 desc = &priv->tx_ring[q][entry];
1568 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len,
1570 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1573 desc->ds_tagl = cpu_to_le16(len);
1574 desc->dptr = cpu_to_le32(dma_addr);
1576 /* TX timestamp required */
1578 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1580 if (num_tx_desc > 1) {
1582 dma_unmap_single(ndev->dev.parent, dma_addr,
1583 len, DMA_TO_DEVICE);
1587 ts_skb->skb = skb_get(skb);
1588 ts_skb->tag = priv->ts_skb_tag++;
1589 priv->ts_skb_tag &= 0x3ff;
1590 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1592 /* TAG and timestamp required flag */
1593 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1594 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1595 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12);
1598 skb_tx_timestamp(skb);
1599 /* Descriptor type must be set after all the above writes */
1601 if (num_tx_desc > 1) {
1602 desc->die_dt = DT_FEND;
1604 desc->die_dt = DT_FSTART;
1606 desc->die_dt = DT_FSINGLE;
1608 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
1610 priv->cur_tx[q] += num_tx_desc;
1611 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1612 (priv->num_tx_ring[q] - 1) * num_tx_desc &&
1613 !ravb_tx_free(ndev, q, true))
1614 netif_stop_subqueue(ndev, q);
1617 spin_unlock_irqrestore(&priv->lock, flags);
1618 return NETDEV_TX_OK;
1621 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1622 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1624 dev_kfree_skb_any(skb);
1625 priv->tx_skb[q][entry / num_tx_desc] = NULL;
1629 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1630 struct net_device *sb_dev)
1632 /* If skb needs TX timestamp, it is handled in network control queue */
1633 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1638 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1640 struct ravb_private *priv = netdev_priv(ndev);
1641 struct net_device_stats *nstats, *stats0, *stats1;
1643 nstats = &ndev->stats;
1644 stats0 = &priv->stats[RAVB_BE];
1645 stats1 = &priv->stats[RAVB_NC];
1647 if (priv->chip_id == RCAR_GEN3) {
1648 nstats->tx_dropped += ravb_read(ndev, TROCR);
1649 ravb_write(ndev, 0, TROCR); /* (write clear) */
1652 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1653 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1654 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1655 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1656 nstats->multicast = stats0->multicast + stats1->multicast;
1657 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1658 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1659 nstats->rx_frame_errors =
1660 stats0->rx_frame_errors + stats1->rx_frame_errors;
1661 nstats->rx_length_errors =
1662 stats0->rx_length_errors + stats1->rx_length_errors;
1663 nstats->rx_missed_errors =
1664 stats0->rx_missed_errors + stats1->rx_missed_errors;
1665 nstats->rx_over_errors =
1666 stats0->rx_over_errors + stats1->rx_over_errors;
1671 /* Update promiscuous bit */
1672 static void ravb_set_rx_mode(struct net_device *ndev)
1674 struct ravb_private *priv = netdev_priv(ndev);
1675 unsigned long flags;
1677 spin_lock_irqsave(&priv->lock, flags);
1678 ravb_modify(ndev, ECMR, ECMR_PRM,
1679 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
1680 spin_unlock_irqrestore(&priv->lock, flags);
1683 /* Device close function for Ethernet AVB */
1684 static int ravb_close(struct net_device *ndev)
1686 struct device_node *np = ndev->dev.parent->of_node;
1687 struct ravb_private *priv = netdev_priv(ndev);
1688 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1690 netif_tx_stop_all_queues(ndev);
1692 /* Disable interrupts by clearing the interrupt masks. */
1693 ravb_write(ndev, 0, RIC0);
1694 ravb_write(ndev, 0, RIC2);
1695 ravb_write(ndev, 0, TIC);
1697 /* Stop PTP Clock driver */
1698 if (priv->chip_id == RCAR_GEN2)
1699 ravb_ptp_stop(ndev);
1701 /* Set the config mode to stop the AVB-DMAC's processes */
1702 if (ravb_stop_dma(ndev) < 0)
1704 "device will be stopped after h/w processes are done.\n");
1706 /* Clear the timestamp list */
1707 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1708 list_del(&ts_skb->list);
1709 kfree_skb(ts_skb->skb);
1713 /* PHY disconnect */
1715 phy_stop(ndev->phydev);
1716 phy_disconnect(ndev->phydev);
1717 if (of_phy_is_fixed_link(np))
1718 of_phy_deregister_fixed_link(np);
1721 cancel_work_sync(&priv->work);
1723 if (priv->chip_id != RCAR_GEN2) {
1724 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1725 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1726 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1727 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1728 free_irq(priv->emac_irq, ndev);
1730 free_irq(ndev->irq, ndev);
1732 napi_disable(&priv->napi[RAVB_NC]);
1733 napi_disable(&priv->napi[RAVB_BE]);
1735 /* Free all the skb's in the RX queue and the DMA buffers. */
1736 ravb_ring_free(ndev, RAVB_BE);
1737 ravb_ring_free(ndev, RAVB_NC);
1742 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1744 struct ravb_private *priv = netdev_priv(ndev);
1745 struct hwtstamp_config config;
1748 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1750 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) {
1751 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT:
1752 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1754 case RAVB_RXTSTAMP_TYPE_ALL:
1755 config.rx_filter = HWTSTAMP_FILTER_ALL;
1758 config.rx_filter = HWTSTAMP_FILTER_NONE;
1761 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1765 /* Control hardware time stamping */
1766 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1768 struct ravb_private *priv = netdev_priv(ndev);
1769 struct hwtstamp_config config;
1770 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1773 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1776 /* Reserved for future extensions */
1780 switch (config.tx_type) {
1781 case HWTSTAMP_TX_OFF:
1784 case HWTSTAMP_TX_ON:
1785 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1791 switch (config.rx_filter) {
1792 case HWTSTAMP_FILTER_NONE:
1795 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1796 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1799 config.rx_filter = HWTSTAMP_FILTER_ALL;
1800 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1803 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1804 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1806 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1810 /* ioctl to device function */
1811 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1813 struct phy_device *phydev = ndev->phydev;
1815 if (!netif_running(ndev))
1823 return ravb_hwtstamp_get(ndev, req);
1825 return ravb_hwtstamp_set(ndev, req);
1828 return phy_mii_ioctl(phydev, req, cmd);
1831 static int ravb_change_mtu(struct net_device *ndev, int new_mtu)
1833 struct ravb_private *priv = netdev_priv(ndev);
1835 ndev->mtu = new_mtu;
1837 if (netif_running(ndev)) {
1838 synchronize_irq(priv->emac_irq);
1839 ravb_emac_init(ndev);
1842 netdev_update_features(ndev);
1847 static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
1849 struct ravb_private *priv = netdev_priv(ndev);
1850 unsigned long flags;
1852 spin_lock_irqsave(&priv->lock, flags);
1854 /* Disable TX and RX */
1855 ravb_rcv_snd_disable(ndev);
1857 /* Modify RX Checksum setting */
1858 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
1860 /* Enable TX and RX */
1861 ravb_rcv_snd_enable(ndev);
1863 spin_unlock_irqrestore(&priv->lock, flags);
1866 static int ravb_set_features(struct net_device *ndev,
1867 netdev_features_t features)
1869 netdev_features_t changed = ndev->features ^ features;
1871 if (changed & NETIF_F_RXCSUM)
1872 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
1874 ndev->features = features;
1879 static const struct net_device_ops ravb_netdev_ops = {
1880 .ndo_open = ravb_open,
1881 .ndo_stop = ravb_close,
1882 .ndo_start_xmit = ravb_start_xmit,
1883 .ndo_select_queue = ravb_select_queue,
1884 .ndo_get_stats = ravb_get_stats,
1885 .ndo_set_rx_mode = ravb_set_rx_mode,
1886 .ndo_tx_timeout = ravb_tx_timeout,
1887 .ndo_do_ioctl = ravb_do_ioctl,
1888 .ndo_change_mtu = ravb_change_mtu,
1889 .ndo_validate_addr = eth_validate_addr,
1890 .ndo_set_mac_address = eth_mac_addr,
1891 .ndo_set_features = ravb_set_features,
1894 /* MDIO bus init function */
1895 static int ravb_mdio_init(struct ravb_private *priv)
1897 struct platform_device *pdev = priv->pdev;
1898 struct device *dev = &pdev->dev;
1902 priv->mdiobb.ops = &bb_ops;
1904 /* MII controller setting */
1905 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1909 /* Hook up MII support for ethtool */
1910 priv->mii_bus->name = "ravb_mii";
1911 priv->mii_bus->parent = dev;
1912 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1913 pdev->name, pdev->id);
1915 /* Register MDIO bus */
1916 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1923 free_mdio_bitbang(priv->mii_bus);
1927 /* MDIO bus release function */
1928 static int ravb_mdio_release(struct ravb_private *priv)
1930 /* Unregister mdio bus */
1931 mdiobus_unregister(priv->mii_bus);
1933 /* Free bitbang info */
1934 free_mdio_bitbang(priv->mii_bus);
1939 static const struct of_device_id ravb_match_table[] = {
1940 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1941 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1942 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
1943 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1944 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
1947 MODULE_DEVICE_TABLE(of, ravb_match_table);
1949 static int ravb_set_gti(struct net_device *ndev)
1951 struct ravb_private *priv = netdev_priv(ndev);
1952 struct device *dev = ndev->dev.parent;
1956 rate = clk_get_rate(priv->clk);
1960 inc = 1000000000ULL << 20;
1963 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1964 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1965 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1969 ravb_write(ndev, inc, GTI);
1974 static void ravb_set_config_mode(struct net_device *ndev)
1976 struct ravb_private *priv = netdev_priv(ndev);
1978 if (priv->chip_id == RCAR_GEN2) {
1979 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
1980 /* Set CSEL value */
1981 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1983 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
1984 CCC_GAC | CCC_CSEL_HPB);
1988 static const struct soc_device_attribute ravb_delay_mode_quirk_match[] = {
1989 { .soc_id = "r8a774c0" },
1990 { .soc_id = "r8a77990" },
1991 { .soc_id = "r8a77995" },
1995 /* Set tx and rx clock internal delay modes */
1996 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev)
1998 struct ravb_private *priv = netdev_priv(ndev);
1999 bool explicit_delay = false;
2002 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) {
2003 /* Valid values are 0 and 1800, according to DT bindings */
2004 priv->rxcidm = !!delay;
2005 explicit_delay = true;
2007 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) {
2008 /* Valid values are 0 and 2000, according to DT bindings */
2009 priv->txcidm = !!delay;
2010 explicit_delay = true;
2016 /* Fall back to legacy rgmii-*id behavior */
2017 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2018 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) {
2020 priv->rgmii_override = 1;
2023 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2024 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
2025 if (!WARN(soc_device_match(ravb_delay_mode_quirk_match),
2026 "phy-mode %s requires TX clock internal delay mode which is not supported by this hardware revision. Please update device tree",
2027 phy_modes(priv->phy_interface))) {
2029 priv->rgmii_override = 1;
2034 static void ravb_set_delay_mode(struct net_device *ndev)
2036 struct ravb_private *priv = netdev_priv(ndev);
2043 ravb_modify(ndev, APSR, APSR_DM, set);
2046 static int ravb_probe(struct platform_device *pdev)
2048 struct device_node *np = pdev->dev.of_node;
2049 struct ravb_private *priv;
2050 enum ravb_chip_id chip_id;
2051 struct net_device *ndev;
2053 struct resource *res;
2058 "this driver is required to be instantiated from device tree\n");
2062 /* Get base address */
2063 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2065 dev_err(&pdev->dev, "invalid resource\n");
2069 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
2070 NUM_TX_QUEUE, NUM_RX_QUEUE);
2074 ndev->features = NETIF_F_RXCSUM;
2075 ndev->hw_features = NETIF_F_RXCSUM;
2077 pm_runtime_enable(&pdev->dev);
2078 error = pm_runtime_resume_and_get(&pdev->dev);
2080 goto out_rpm_disable;
2082 /* The Ether-specific entries in the device structure. */
2083 ndev->base_addr = res->start;
2085 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
2087 if (chip_id == RCAR_GEN3)
2088 irq = platform_get_irq_byname(pdev, "ch22");
2090 irq = platform_get_irq(pdev, 0);
2097 SET_NETDEV_DEV(ndev, &pdev->dev);
2099 priv = netdev_priv(ndev);
2102 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
2103 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2104 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2105 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2106 priv->addr = devm_ioremap_resource(&pdev->dev, res);
2107 if (IS_ERR(priv->addr)) {
2108 error = PTR_ERR(priv->addr);
2112 spin_lock_init(&priv->lock);
2113 INIT_WORK(&priv->work, ravb_tx_timeout_work);
2115 error = of_get_phy_mode(np, &priv->phy_interface);
2116 if (error && error != -ENODEV)
2119 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2120 priv->avb_link_active_low =
2121 of_property_read_bool(np, "renesas,ether-link-active-low");
2123 if (chip_id == RCAR_GEN3) {
2124 irq = platform_get_irq_byname(pdev, "ch24");
2129 priv->emac_irq = irq;
2130 for (i = 0; i < NUM_RX_QUEUE; i++) {
2131 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2136 priv->rx_irqs[i] = irq;
2138 for (i = 0; i < NUM_TX_QUEUE; i++) {
2139 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2144 priv->tx_irqs[i] = irq;
2148 priv->chip_id = chip_id;
2150 priv->clk = devm_clk_get(&pdev->dev, NULL);
2151 if (IS_ERR(priv->clk)) {
2152 error = PTR_ERR(priv->clk);
2156 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
2157 ndev->min_mtu = ETH_MIN_MTU;
2159 priv->num_tx_desc = chip_id == RCAR_GEN2 ?
2160 NUM_TX_DESC_GEN2 : NUM_TX_DESC_GEN3;
2163 ndev->netdev_ops = &ravb_netdev_ops;
2164 ndev->ethtool_ops = &ravb_ethtool_ops;
2166 /* Set AVB config mode */
2167 ravb_set_config_mode(ndev);
2170 error = ravb_set_gti(ndev);
2174 /* Request GTI loading */
2175 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2177 if (priv->chip_id != RCAR_GEN2) {
2178 ravb_parse_delay_mode(np, ndev);
2179 ravb_set_delay_mode(ndev);
2182 /* Allocate descriptor base address table */
2183 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2184 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2185 &priv->desc_bat_dma, GFP_KERNEL);
2186 if (!priv->desc_bat) {
2188 "Cannot allocate desc base address table (size %d bytes)\n",
2189 priv->desc_bat_size);
2193 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2194 priv->desc_bat[q].die_dt = DT_EOS;
2195 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2197 /* Initialise HW timestamp list */
2198 INIT_LIST_HEAD(&priv->ts_skb_list);
2200 /* Initialise PTP Clock driver */
2201 if (chip_id != RCAR_GEN2)
2202 ravb_ptp_init(ndev, pdev);
2204 /* Debug message level */
2205 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2207 /* Read and set MAC address */
2208 ravb_read_mac_address(ndev, of_get_mac_address(np));
2209 if (!is_valid_ether_addr(ndev->dev_addr)) {
2210 dev_warn(&pdev->dev,
2211 "no valid MAC address supplied, using a random one\n");
2212 eth_hw_addr_random(ndev);
2216 error = ravb_mdio_init(priv);
2218 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2222 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2223 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2225 /* Network device register */
2226 error = register_netdev(ndev);
2230 device_set_wakeup_capable(&pdev->dev, 1);
2232 /* Print device information */
2233 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2234 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2236 platform_set_drvdata(pdev, ndev);
2241 netif_napi_del(&priv->napi[RAVB_NC]);
2242 netif_napi_del(&priv->napi[RAVB_BE]);
2243 ravb_mdio_release(priv);
2245 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2246 priv->desc_bat_dma);
2248 /* Stop PTP Clock driver */
2249 if (chip_id != RCAR_GEN2)
2250 ravb_ptp_stop(ndev);
2254 pm_runtime_put(&pdev->dev);
2256 pm_runtime_disable(&pdev->dev);
2260 static int ravb_remove(struct platform_device *pdev)
2262 struct net_device *ndev = platform_get_drvdata(pdev);
2263 struct ravb_private *priv = netdev_priv(ndev);
2265 /* Stop PTP Clock driver */
2266 if (priv->chip_id != RCAR_GEN2)
2267 ravb_ptp_stop(ndev);
2269 /* Set reset mode */
2270 ravb_write(ndev, CCC_OPC_RESET, CCC);
2271 unregister_netdev(ndev);
2272 netif_napi_del(&priv->napi[RAVB_NC]);
2273 netif_napi_del(&priv->napi[RAVB_BE]);
2274 ravb_mdio_release(priv);
2275 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2276 priv->desc_bat_dma);
2277 pm_runtime_put_sync(&pdev->dev);
2278 pm_runtime_disable(&pdev->dev);
2280 platform_set_drvdata(pdev, NULL);
2285 static int ravb_wol_setup(struct net_device *ndev)
2287 struct ravb_private *priv = netdev_priv(ndev);
2289 /* Disable interrupts by clearing the interrupt masks. */
2290 ravb_write(ndev, 0, RIC0);
2291 ravb_write(ndev, 0, RIC2);
2292 ravb_write(ndev, 0, TIC);
2294 /* Only allow ECI interrupts */
2295 synchronize_irq(priv->emac_irq);
2296 napi_disable(&priv->napi[RAVB_NC]);
2297 napi_disable(&priv->napi[RAVB_BE]);
2298 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
2300 /* Enable MagicPacket */
2301 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
2303 return enable_irq_wake(priv->emac_irq);
2306 static int ravb_wol_restore(struct net_device *ndev)
2308 struct ravb_private *priv = netdev_priv(ndev);
2311 napi_enable(&priv->napi[RAVB_NC]);
2312 napi_enable(&priv->napi[RAVB_BE]);
2314 /* Disable MagicPacket */
2315 ravb_modify(ndev, ECMR, ECMR_MPDE, 0);
2317 ret = ravb_close(ndev);
2321 return disable_irq_wake(priv->emac_irq);
2324 static int __maybe_unused ravb_suspend(struct device *dev)
2326 struct net_device *ndev = dev_get_drvdata(dev);
2327 struct ravb_private *priv = netdev_priv(ndev);
2330 if (!netif_running(ndev))
2333 netif_device_detach(ndev);
2335 if (priv->wol_enabled)
2336 ret = ravb_wol_setup(ndev);
2338 ret = ravb_close(ndev);
2343 static int __maybe_unused ravb_resume(struct device *dev)
2345 struct net_device *ndev = dev_get_drvdata(dev);
2346 struct ravb_private *priv = netdev_priv(ndev);
2349 /* If WoL is enabled set reset mode to rearm the WoL logic */
2350 if (priv->wol_enabled)
2351 ravb_write(ndev, CCC_OPC_RESET, CCC);
2353 /* All register have been reset to default values.
2354 * Restore all registers which where setup at probe time and
2355 * reopen device if it was running before system suspended.
2358 /* Set AVB config mode */
2359 ravb_set_config_mode(ndev);
2362 ret = ravb_set_gti(ndev);
2366 /* Request GTI loading */
2367 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2369 if (priv->chip_id != RCAR_GEN2)
2370 ravb_set_delay_mode(ndev);
2372 /* Restore descriptor base address table */
2373 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2375 if (netif_running(ndev)) {
2376 if (priv->wol_enabled) {
2377 ret = ravb_wol_restore(ndev);
2381 ret = ravb_open(ndev);
2384 ravb_set_rx_mode(ndev);
2385 netif_device_attach(ndev);
2391 static int __maybe_unused ravb_runtime_nop(struct device *dev)
2393 /* Runtime PM callback shared between ->runtime_suspend()
2394 * and ->runtime_resume(). Simply returns success.
2396 * This driver re-initializes all registers after
2397 * pm_runtime_get_sync() anyway so there is no need
2398 * to save and restore registers here.
2403 static const struct dev_pm_ops ravb_dev_pm_ops = {
2404 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
2405 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
2408 static struct platform_driver ravb_driver = {
2409 .probe = ravb_probe,
2410 .remove = ravb_remove,
2413 .pm = &ravb_dev_pm_ops,
2414 .of_match_table = ravb_match_table,
2418 module_platform_driver(ravb_driver);
2420 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2421 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2422 MODULE_LICENSE("GPL v2");