1 /* Renesas Ethernet AVB device driver
3 * Copyright (C) 2014-2019 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7 * Based on the SuperH Ethernet driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
14 #include <linux/cache.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/net_tstamp.h>
27 #include <linux/of_device.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_mdio.h>
30 #include <linux/of_net.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
33 #include <linux/spinlock.h>
35 #include <asm/div64.h>
39 #define RAVB_DEF_MSG_ENABLE \
45 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
50 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
55 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
58 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
61 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
65 for (i = 0; i < 10000; i++) {
66 if ((ravb_read(ndev, reg) & mask) == value)
73 static int ravb_config(struct net_device *ndev)
78 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
79 /* Check if the operating mode is changed to the config mode */
80 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
82 netdev_err(ndev, "failed to switch device to config mode\n");
87 static void ravb_set_duplex(struct net_device *ndev)
89 struct ravb_private *priv = netdev_priv(ndev);
91 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0);
94 static void ravb_set_rate(struct net_device *ndev)
96 struct ravb_private *priv = netdev_priv(ndev);
98 switch (priv->speed) {
99 case 100: /* 100BASE */
100 ravb_write(ndev, GECMR_SPEED_100, GECMR);
102 case 1000: /* 1000BASE */
103 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
108 static void ravb_set_buffer_align(struct sk_buff *skb)
110 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
113 skb_reserve(skb, RAVB_ALIGN - reserve);
116 /* Get MAC address from the MAC address registers
118 * Ethernet AVB device doesn't have ROM for MAC address.
119 * This function gets the MAC address that was used by a bootloader.
121 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
124 ether_addr_copy(ndev->dev_addr, mac);
126 u32 mahr = ravb_read(ndev, MAHR);
127 u32 malr = ravb_read(ndev, MALR);
129 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
130 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
131 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
132 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
133 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
134 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
138 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
140 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
143 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
146 /* MDC pin control */
147 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
149 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
152 /* Data I/O pin control */
153 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
155 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
159 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
161 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
165 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
167 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
170 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
173 /* MDIO bus control struct */
174 static struct mdiobb_ops bb_ops = {
175 .owner = THIS_MODULE,
176 .set_mdc = ravb_set_mdc,
177 .set_mdio_dir = ravb_set_mdio_dir,
178 .set_mdio_data = ravb_set_mdio_data,
179 .get_mdio_data = ravb_get_mdio_data,
182 /* Free TX skb function for AVB-IP */
183 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
185 struct ravb_private *priv = netdev_priv(ndev);
186 struct net_device_stats *stats = &priv->stats[q];
187 struct ravb_tx_desc *desc;
192 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
195 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
197 desc = &priv->tx_ring[q][entry];
198 txed = desc->die_dt == DT_FEMPTY;
199 if (free_txed_only && !txed)
201 /* Descriptor type must be checked before all other reads */
203 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
204 /* Free the original skb. */
205 if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
206 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
207 size, DMA_TO_DEVICE);
208 /* Last packet descriptor? */
209 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
210 entry /= NUM_TX_DESC;
211 dev_kfree_skb_any(priv->tx_skb[q][entry]);
212 priv->tx_skb[q][entry] = NULL;
219 stats->tx_bytes += size;
220 desc->die_dt = DT_EEMPTY;
225 /* Free skb's and DMA buffers for Ethernet AVB */
226 static void ravb_ring_free(struct net_device *ndev, int q)
228 struct ravb_private *priv = netdev_priv(ndev);
232 if (priv->rx_ring[q]) {
233 for (i = 0; i < priv->num_rx_ring[q]; i++) {
234 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
236 if (!dma_mapping_error(ndev->dev.parent,
237 le32_to_cpu(desc->dptr)))
238 dma_unmap_single(ndev->dev.parent,
239 le32_to_cpu(desc->dptr),
243 ring_size = sizeof(struct ravb_ex_rx_desc) *
244 (priv->num_rx_ring[q] + 1);
245 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
246 priv->rx_desc_dma[q]);
247 priv->rx_ring[q] = NULL;
250 if (priv->tx_ring[q]) {
251 ravb_tx_free(ndev, q, false);
253 ring_size = sizeof(struct ravb_tx_desc) *
254 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
255 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
256 priv->tx_desc_dma[q]);
257 priv->tx_ring[q] = NULL;
260 /* Free RX skb ringbuffer */
261 if (priv->rx_skb[q]) {
262 for (i = 0; i < priv->num_rx_ring[q]; i++)
263 dev_kfree_skb(priv->rx_skb[q][i]);
265 kfree(priv->rx_skb[q]);
266 priv->rx_skb[q] = NULL;
268 /* Free aligned TX buffers */
269 kfree(priv->tx_align[q]);
270 priv->tx_align[q] = NULL;
272 /* Free TX skb ringbuffer.
273 * SKBs are freed by ravb_tx_free() call above.
275 kfree(priv->tx_skb[q]);
276 priv->tx_skb[q] = NULL;
279 /* Format skb and descriptor buffer for Ethernet AVB */
280 static void ravb_ring_format(struct net_device *ndev, int q)
282 struct ravb_private *priv = netdev_priv(ndev);
283 struct ravb_ex_rx_desc *rx_desc;
284 struct ravb_tx_desc *tx_desc;
285 struct ravb_desc *desc;
286 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
287 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
294 priv->dirty_rx[q] = 0;
295 priv->dirty_tx[q] = 0;
297 memset(priv->rx_ring[q], 0, rx_ring_size);
298 /* Build RX ring buffer */
299 for (i = 0; i < priv->num_rx_ring[q]; i++) {
301 rx_desc = &priv->rx_ring[q][i];
302 rx_desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
303 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
306 /* We just set the data size to 0 for a failed mapping which
307 * should prevent DMA from happening...
309 if (dma_mapping_error(ndev->dev.parent, dma_addr))
310 rx_desc->ds_cc = cpu_to_le16(0);
311 rx_desc->dptr = cpu_to_le32(dma_addr);
312 rx_desc->die_dt = DT_FEMPTY;
314 rx_desc = &priv->rx_ring[q][i];
315 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
316 rx_desc->die_dt = DT_LINKFIX; /* type */
318 memset(priv->tx_ring[q], 0, tx_ring_size);
319 /* Build TX ring buffer */
320 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
322 tx_desc->die_dt = DT_EEMPTY;
324 tx_desc->die_dt = DT_EEMPTY;
326 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
327 tx_desc->die_dt = DT_LINKFIX; /* type */
329 /* RX descriptor base address for best effort */
330 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
331 desc->die_dt = DT_LINKFIX; /* type */
332 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
334 /* TX descriptor base address for best effort */
335 desc = &priv->desc_bat[q];
336 desc->die_dt = DT_LINKFIX; /* type */
337 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
340 /* Init skb and descriptor buffer for Ethernet AVB */
341 static int ravb_ring_init(struct net_device *ndev, int q)
343 struct ravb_private *priv = netdev_priv(ndev);
348 /* Allocate RX and TX skb rings */
349 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
350 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
351 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
352 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
353 if (!priv->rx_skb[q] || !priv->tx_skb[q])
356 for (i = 0; i < priv->num_rx_ring[q]; i++) {
357 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
360 ravb_set_buffer_align(skb);
361 priv->rx_skb[q][i] = skb;
364 /* Allocate rings for the aligned buffers */
365 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
366 DPTR_ALIGN - 1, GFP_KERNEL);
367 if (!priv->tx_align[q])
370 /* Allocate all RX descriptors. */
371 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
372 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
373 &priv->rx_desc_dma[q],
375 if (!priv->rx_ring[q])
378 priv->dirty_rx[q] = 0;
380 /* Allocate all TX descriptors. */
381 ring_size = sizeof(struct ravb_tx_desc) *
382 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
383 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
384 &priv->tx_desc_dma[q],
386 if (!priv->tx_ring[q])
392 ravb_ring_free(ndev, q);
397 /* E-MAC init function */
398 static void ravb_emac_init(struct net_device *ndev)
400 struct ravb_private *priv = netdev_priv(ndev);
402 /* Receive frame limit set register */
403 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
405 /* PAUSE prohibition */
406 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) |
407 ECMR_TE | ECMR_RE, ECMR);
411 /* Set MAC address */
413 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
414 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
416 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
418 /* E-MAC status register clear */
419 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
421 /* E-MAC interrupt enable register */
422 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
425 /* Device init function for Ethernet AVB */
426 static int ravb_dmac_init(struct net_device *ndev)
428 struct ravb_private *priv = netdev_priv(ndev);
431 /* Set CONFIG mode */
432 error = ravb_config(ndev);
436 error = ravb_ring_init(ndev, RAVB_BE);
439 error = ravb_ring_init(ndev, RAVB_NC);
441 ravb_ring_free(ndev, RAVB_BE);
445 /* Descriptor format */
446 ravb_ring_format(ndev, RAVB_BE);
447 ravb_ring_format(ndev, RAVB_NC);
449 #if defined(__LITTLE_ENDIAN)
450 ravb_modify(ndev, CCC, CCC_BOC, 0);
452 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC);
457 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
460 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
462 /* Timestamp enable */
463 ravb_write(ndev, TCCR_TFEN, TCCR);
465 /* Interrupt init: */
466 if (priv->chip_id == RCAR_GEN3) {
468 ravb_write(ndev, 0, DIL);
469 /* Set queue specific interrupt */
470 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
473 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
474 /* Disable FIFO full warning */
475 ravb_write(ndev, 0, RIC1);
476 /* Receive FIFO full error, descriptor empty */
477 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
478 /* Frame transmitted, timestamp FIFO updated */
479 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
481 /* Setting the control will start the AVB-DMAC process. */
482 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
487 static void ravb_get_tx_tstamp(struct net_device *ndev)
489 struct ravb_private *priv = netdev_priv(ndev);
490 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
491 struct skb_shared_hwtstamps shhwtstamps;
493 struct timespec64 ts;
498 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
500 tfa2 = ravb_read(ndev, TFA2);
501 tfa_tag = (tfa2 & TFA2_TST) >> 16;
502 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
503 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
504 ravb_read(ndev, TFA1);
505 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
506 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
507 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
511 list_del(&ts_skb->list);
513 if (tag == tfa_tag) {
514 skb_tstamp_tx(skb, &shhwtstamps);
515 dev_consume_skb_any(skb);
518 dev_kfree_skb_any(skb);
521 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
525 /* Packet receive function for Ethernet AVB */
526 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
528 struct ravb_private *priv = netdev_priv(ndev);
529 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
530 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
532 struct net_device_stats *stats = &priv->stats[q];
533 struct ravb_ex_rx_desc *desc;
536 struct timespec64 ts;
541 boguscnt = min(boguscnt, *quota);
543 desc = &priv->rx_ring[q][entry];
544 while (desc->die_dt != DT_FEMPTY) {
545 /* Descriptor type must be checked before all other reads */
547 desc_status = desc->msc;
548 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
553 /* We use 0-byte descriptors to mark the DMA mapping errors */
557 if (desc_status & MSC_MC)
560 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
563 if (desc_status & MSC_CRC)
564 stats->rx_crc_errors++;
565 if (desc_status & MSC_RFE)
566 stats->rx_frame_errors++;
567 if (desc_status & (MSC_RTLF | MSC_RTSF))
568 stats->rx_length_errors++;
569 if (desc_status & MSC_CEEF)
570 stats->rx_missed_errors++;
572 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
574 skb = priv->rx_skb[q][entry];
575 priv->rx_skb[q][entry] = NULL;
576 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
579 get_ts &= (q == RAVB_NC) ?
580 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
581 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
583 struct skb_shared_hwtstamps *shhwtstamps;
585 shhwtstamps = skb_hwtstamps(skb);
586 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
587 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
588 32) | le32_to_cpu(desc->ts_sl);
589 ts.tv_nsec = le32_to_cpu(desc->ts_n);
590 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
592 skb_put(skb, pkt_len);
593 skb->protocol = eth_type_trans(skb, ndev);
594 napi_gro_receive(&priv->napi[q], skb);
596 stats->rx_bytes += pkt_len;
599 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
600 desc = &priv->rx_ring[q][entry];
603 /* Refill the RX ring buffers. */
604 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
605 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
606 desc = &priv->rx_ring[q][entry];
607 desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
609 if (!priv->rx_skb[q][entry]) {
610 skb = netdev_alloc_skb(ndev,
611 PKT_BUF_SZ + RAVB_ALIGN - 1);
613 break; /* Better luck next round. */
614 ravb_set_buffer_align(skb);
615 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
616 le16_to_cpu(desc->ds_cc),
618 skb_checksum_none_assert(skb);
619 /* We just set the data size to 0 for a failed mapping
620 * which should prevent DMA from happening...
622 if (dma_mapping_error(ndev->dev.parent, dma_addr))
623 desc->ds_cc = cpu_to_le16(0);
624 desc->dptr = cpu_to_le32(dma_addr);
625 priv->rx_skb[q][entry] = skb;
627 /* Descriptor type must be set after all the above writes */
629 desc->die_dt = DT_FEMPTY;
632 *quota -= limit - (++boguscnt);
634 return boguscnt <= 0;
637 static void ravb_rcv_snd_disable(struct net_device *ndev)
639 /* Disable TX and RX */
640 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
643 static void ravb_rcv_snd_enable(struct net_device *ndev)
645 /* Enable TX and RX */
646 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
649 /* function for waiting dma process finished */
650 static int ravb_stop_dma(struct net_device *ndev)
654 /* Wait for stopping the hardware TX process */
655 error = ravb_wait(ndev, TCCR,
656 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
660 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
665 /* Stop the E-MAC's RX/TX processes. */
666 ravb_rcv_snd_disable(ndev);
668 /* Wait for stopping the RX DMA process */
669 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
673 /* Stop AVB-DMAC process */
674 return ravb_config(ndev);
677 /* E-MAC interrupt handler */
678 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
680 struct ravb_private *priv = netdev_priv(ndev);
683 ecsr = ravb_read(ndev, ECSR);
684 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
686 ndev->stats.tx_carrier_errors++;
687 if (ecsr & ECSR_LCHNG) {
689 if (priv->no_avb_link)
691 psr = ravb_read(ndev, PSR);
692 if (priv->avb_link_active_low)
694 if (!(psr & PSR_LMON)) {
695 /* DIsable RX and TX */
696 ravb_rcv_snd_disable(ndev);
698 /* Enable RX and TX */
699 ravb_rcv_snd_enable(ndev);
704 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
706 struct net_device *ndev = dev_id;
707 struct ravb_private *priv = netdev_priv(ndev);
709 spin_lock(&priv->lock);
710 ravb_emac_interrupt_unlocked(ndev);
712 spin_unlock(&priv->lock);
716 /* Error interrupt handler */
717 static void ravb_error_interrupt(struct net_device *ndev)
719 struct ravb_private *priv = netdev_priv(ndev);
722 eis = ravb_read(ndev, EIS);
723 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);
725 ris2 = ravb_read(ndev, RIS2);
726 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED),
729 /* Receive Descriptor Empty int */
730 if (ris2 & RIS2_QFF0)
731 priv->stats[RAVB_BE].rx_over_errors++;
733 /* Receive Descriptor Empty int */
734 if (ris2 & RIS2_QFF1)
735 priv->stats[RAVB_NC].rx_over_errors++;
737 /* Receive FIFO Overflow int */
738 if (ris2 & RIS2_RFFF)
739 priv->rx_fifo_errors++;
743 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
745 struct ravb_private *priv = netdev_priv(ndev);
746 u32 ris0 = ravb_read(ndev, RIS0);
747 u32 ric0 = ravb_read(ndev, RIC0);
748 u32 tis = ravb_read(ndev, TIS);
749 u32 tic = ravb_read(ndev, TIC);
751 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
752 if (napi_schedule_prep(&priv->napi[q])) {
753 /* Mask RX and TX interrupts */
754 if (priv->chip_id == RCAR_GEN2) {
755 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
756 ravb_write(ndev, tic & ~BIT(q), TIC);
758 ravb_write(ndev, BIT(q), RID0);
759 ravb_write(ndev, BIT(q), TID);
761 __napi_schedule(&priv->napi[q]);
764 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
767 " tx status 0x%08x, tx mask 0x%08x.\n",
775 static bool ravb_timestamp_interrupt(struct net_device *ndev)
777 u32 tis = ravb_read(ndev, TIS);
779 if (tis & TIS_TFUF) {
780 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);
781 ravb_get_tx_tstamp(ndev);
787 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
789 struct net_device *ndev = dev_id;
790 struct ravb_private *priv = netdev_priv(ndev);
791 irqreturn_t result = IRQ_NONE;
794 spin_lock(&priv->lock);
795 /* Get interrupt status */
796 iss = ravb_read(ndev, ISS);
798 /* Received and transmitted interrupts */
799 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
802 /* Timestamp updated */
803 if (ravb_timestamp_interrupt(ndev))
804 result = IRQ_HANDLED;
806 /* Network control and best effort queue RX/TX */
807 for (q = RAVB_NC; q >= RAVB_BE; q--) {
808 if (ravb_queue_interrupt(ndev, q))
809 result = IRQ_HANDLED;
813 /* E-MAC status summary */
815 ravb_emac_interrupt_unlocked(ndev);
816 result = IRQ_HANDLED;
819 /* Error status summary */
821 ravb_error_interrupt(ndev);
822 result = IRQ_HANDLED;
825 /* gPTP interrupt status summary */
826 if (iss & ISS_CGIS) {
827 ravb_ptp_interrupt(ndev);
828 result = IRQ_HANDLED;
832 spin_unlock(&priv->lock);
836 /* Timestamp/Error/gPTP interrupt handler */
837 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
839 struct net_device *ndev = dev_id;
840 struct ravb_private *priv = netdev_priv(ndev);
841 irqreturn_t result = IRQ_NONE;
844 spin_lock(&priv->lock);
845 /* Get interrupt status */
846 iss = ravb_read(ndev, ISS);
848 /* Timestamp updated */
849 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
850 result = IRQ_HANDLED;
852 /* Error status summary */
854 ravb_error_interrupt(ndev);
855 result = IRQ_HANDLED;
858 /* gPTP interrupt status summary */
859 if (iss & ISS_CGIS) {
860 ravb_ptp_interrupt(ndev);
861 result = IRQ_HANDLED;
865 spin_unlock(&priv->lock);
869 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
871 struct net_device *ndev = dev_id;
872 struct ravb_private *priv = netdev_priv(ndev);
873 irqreturn_t result = IRQ_NONE;
875 spin_lock(&priv->lock);
877 /* Network control/Best effort queue RX/TX */
878 if (ravb_queue_interrupt(ndev, q))
879 result = IRQ_HANDLED;
882 spin_unlock(&priv->lock);
886 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
888 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
891 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
893 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
896 static int ravb_poll(struct napi_struct *napi, int budget)
898 struct net_device *ndev = napi->dev;
899 struct ravb_private *priv = netdev_priv(ndev);
901 int q = napi - priv->napi;
907 tis = ravb_read(ndev, TIS);
908 ris0 = ravb_read(ndev, RIS0);
909 if (!((ris0 & mask) || (tis & mask)))
912 /* Processing RX Descriptor Ring */
914 /* Clear RX interrupt */
915 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);
916 if (ravb_rx(ndev, "a, q))
919 /* Processing TX Descriptor Ring */
921 spin_lock_irqsave(&priv->lock, flags);
922 /* Clear TX interrupt */
923 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);
924 ravb_tx_free(ndev, q, true);
925 netif_wake_subqueue(ndev, q);
927 spin_unlock_irqrestore(&priv->lock, flags);
933 /* Re-enable RX/TX interrupts */
934 spin_lock_irqsave(&priv->lock, flags);
935 if (priv->chip_id == RCAR_GEN2) {
936 ravb_modify(ndev, RIC0, mask, mask);
937 ravb_modify(ndev, TIC, mask, mask);
939 ravb_write(ndev, mask, RIE0);
940 ravb_write(ndev, mask, TIE);
943 spin_unlock_irqrestore(&priv->lock, flags);
945 /* Receive error message handling */
946 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
947 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
948 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
949 ndev->stats.rx_over_errors = priv->rx_over_errors;
950 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
951 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
953 return budget - quota;
956 /* PHY state control function */
957 static void ravb_adjust_link(struct net_device *ndev)
959 struct ravb_private *priv = netdev_priv(ndev);
960 struct phy_device *phydev = ndev->phydev;
961 bool new_state = false;
964 spin_lock_irqsave(&priv->lock, flags);
966 /* Disable TX and RX right over here, if E-MAC change is ignored */
967 if (priv->no_avb_link)
968 ravb_rcv_snd_disable(ndev);
971 if (phydev->duplex != priv->duplex) {
973 priv->duplex = phydev->duplex;
974 ravb_set_duplex(ndev);
977 if (phydev->speed != priv->speed) {
979 priv->speed = phydev->speed;
983 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
985 priv->link = phydev->link;
987 } else if (priv->link) {
994 /* Enable TX and RX right over here, if E-MAC change is ignored */
995 if (priv->no_avb_link && phydev->link)
996 ravb_rcv_snd_enable(ndev);
999 spin_unlock_irqrestore(&priv->lock, flags);
1001 if (new_state && netif_msg_link(priv))
1002 phy_print_status(phydev);
1005 /* PHY init function */
1006 static int ravb_phy_init(struct net_device *ndev)
1008 struct device_node *np = ndev->dev.parent->of_node;
1009 struct ravb_private *priv = netdev_priv(ndev);
1010 struct phy_device *phydev;
1011 struct device_node *pn;
1018 /* Try connecting to PHY */
1019 pn = of_parse_phandle(np, "phy-handle", 0);
1021 /* In the case of a fixed PHY, the DT node associated
1022 * to the PHY is the Ethernet MAC DT node.
1024 if (of_phy_is_fixed_link(np)) {
1025 err = of_phy_register_fixed_link(np);
1029 pn = of_node_get(np);
1031 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
1032 priv->phy_interface);
1035 netdev_err(ndev, "failed to connect PHY\n");
1037 goto err_deregister_fixed_link;
1040 /* This driver only support 10/100Mbit speeds on Gen3
1043 if (priv->chip_id == RCAR_GEN3) {
1044 err = phy_set_max_speed(phydev, SPEED_100);
1046 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
1047 goto err_phy_disconnect;
1050 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1053 /* 10BASE is not supported */
1054 phydev->supported &= ~PHY_10BT_FEATURES;
1056 phy_attached_info(phydev);
1061 phy_disconnect(phydev);
1062 err_deregister_fixed_link:
1063 if (of_phy_is_fixed_link(np))
1064 of_phy_deregister_fixed_link(np);
1069 /* PHY control start function */
1070 static int ravb_phy_start(struct net_device *ndev)
1074 error = ravb_phy_init(ndev);
1078 phy_start(ndev->phydev);
1083 static int ravb_get_link_ksettings(struct net_device *ndev,
1084 struct ethtool_link_ksettings *cmd)
1086 struct ravb_private *priv = netdev_priv(ndev);
1087 int error = -ENODEV;
1088 unsigned long flags;
1091 spin_lock_irqsave(&priv->lock, flags);
1092 error = phy_ethtool_ksettings_get(ndev->phydev, cmd);
1093 spin_unlock_irqrestore(&priv->lock, flags);
1099 static int ravb_set_link_ksettings(struct net_device *ndev,
1100 const struct ethtool_link_ksettings *cmd)
1105 return phy_ethtool_ksettings_set(ndev->phydev, cmd);
1108 static int ravb_nway_reset(struct net_device *ndev)
1110 int error = -ENODEV;
1113 error = phy_start_aneg(ndev->phydev);
1118 static u32 ravb_get_msglevel(struct net_device *ndev)
1120 struct ravb_private *priv = netdev_priv(ndev);
1122 return priv->msg_enable;
1125 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1127 struct ravb_private *priv = netdev_priv(ndev);
1129 priv->msg_enable = value;
1132 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1133 "rx_queue_0_current",
1134 "tx_queue_0_current",
1137 "rx_queue_0_packets",
1138 "tx_queue_0_packets",
1141 "rx_queue_0_mcast_packets",
1142 "rx_queue_0_errors",
1143 "rx_queue_0_crc_errors",
1144 "rx_queue_0_frame_errors",
1145 "rx_queue_0_length_errors",
1146 "rx_queue_0_missed_errors",
1147 "rx_queue_0_over_errors",
1149 "rx_queue_1_current",
1150 "tx_queue_1_current",
1153 "rx_queue_1_packets",
1154 "tx_queue_1_packets",
1157 "rx_queue_1_mcast_packets",
1158 "rx_queue_1_errors",
1159 "rx_queue_1_crc_errors",
1160 "rx_queue_1_frame_errors",
1161 "rx_queue_1_length_errors",
1162 "rx_queue_1_missed_errors",
1163 "rx_queue_1_over_errors",
1166 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1168 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1172 return RAVB_STATS_LEN;
1178 static void ravb_get_ethtool_stats(struct net_device *ndev,
1179 struct ethtool_stats *stats, u64 *data)
1181 struct ravb_private *priv = netdev_priv(ndev);
1185 /* Device-specific stats */
1186 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1187 struct net_device_stats *stats = &priv->stats[q];
1189 data[i++] = priv->cur_rx[q];
1190 data[i++] = priv->cur_tx[q];
1191 data[i++] = priv->dirty_rx[q];
1192 data[i++] = priv->dirty_tx[q];
1193 data[i++] = stats->rx_packets;
1194 data[i++] = stats->tx_packets;
1195 data[i++] = stats->rx_bytes;
1196 data[i++] = stats->tx_bytes;
1197 data[i++] = stats->multicast;
1198 data[i++] = stats->rx_errors;
1199 data[i++] = stats->rx_crc_errors;
1200 data[i++] = stats->rx_frame_errors;
1201 data[i++] = stats->rx_length_errors;
1202 data[i++] = stats->rx_missed_errors;
1203 data[i++] = stats->rx_over_errors;
1207 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1209 switch (stringset) {
1211 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1216 static void ravb_get_ringparam(struct net_device *ndev,
1217 struct ethtool_ringparam *ring)
1219 struct ravb_private *priv = netdev_priv(ndev);
1221 ring->rx_max_pending = BE_RX_RING_MAX;
1222 ring->tx_max_pending = BE_TX_RING_MAX;
1223 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1224 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1227 static int ravb_set_ringparam(struct net_device *ndev,
1228 struct ethtool_ringparam *ring)
1230 struct ravb_private *priv = netdev_priv(ndev);
1233 if (ring->tx_pending > BE_TX_RING_MAX ||
1234 ring->rx_pending > BE_RX_RING_MAX ||
1235 ring->tx_pending < BE_TX_RING_MIN ||
1236 ring->rx_pending < BE_RX_RING_MIN)
1238 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1241 if (netif_running(ndev)) {
1242 netif_device_detach(ndev);
1243 /* Stop PTP Clock driver */
1244 if (priv->chip_id == RCAR_GEN2)
1245 ravb_ptp_stop(ndev);
1246 /* Wait for DMA stopping */
1247 error = ravb_stop_dma(ndev);
1250 "cannot set ringparam! Any AVB processes are still running?\n");
1253 synchronize_irq(ndev->irq);
1255 /* Free all the skb's in the RX queue and the DMA buffers. */
1256 ravb_ring_free(ndev, RAVB_BE);
1257 ravb_ring_free(ndev, RAVB_NC);
1260 /* Set new parameters */
1261 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1262 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1264 if (netif_running(ndev)) {
1265 error = ravb_dmac_init(ndev);
1268 "%s: ravb_dmac_init() failed, error %d\n",
1273 ravb_emac_init(ndev);
1275 /* Initialise PTP Clock driver */
1276 if (priv->chip_id == RCAR_GEN2)
1277 ravb_ptp_init(ndev, priv->pdev);
1279 netif_device_attach(ndev);
1285 static int ravb_get_ts_info(struct net_device *ndev,
1286 struct ethtool_ts_info *info)
1288 struct ravb_private *priv = netdev_priv(ndev);
1290 info->so_timestamping =
1291 SOF_TIMESTAMPING_TX_SOFTWARE |
1292 SOF_TIMESTAMPING_RX_SOFTWARE |
1293 SOF_TIMESTAMPING_SOFTWARE |
1294 SOF_TIMESTAMPING_TX_HARDWARE |
1295 SOF_TIMESTAMPING_RX_HARDWARE |
1296 SOF_TIMESTAMPING_RAW_HARDWARE;
1297 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1299 (1 << HWTSTAMP_FILTER_NONE) |
1300 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1301 (1 << HWTSTAMP_FILTER_ALL);
1302 info->phc_index = ptp_clock_index(priv->ptp.clock);
1307 static const struct ethtool_ops ravb_ethtool_ops = {
1308 .nway_reset = ravb_nway_reset,
1309 .get_msglevel = ravb_get_msglevel,
1310 .set_msglevel = ravb_set_msglevel,
1311 .get_link = ethtool_op_get_link,
1312 .get_strings = ravb_get_strings,
1313 .get_ethtool_stats = ravb_get_ethtool_stats,
1314 .get_sset_count = ravb_get_sset_count,
1315 .get_ringparam = ravb_get_ringparam,
1316 .set_ringparam = ravb_set_ringparam,
1317 .get_ts_info = ravb_get_ts_info,
1318 .get_link_ksettings = ravb_get_link_ksettings,
1319 .set_link_ksettings = ravb_set_link_ksettings,
1322 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1323 struct net_device *ndev, struct device *dev,
1329 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1332 error = request_irq(irq, handler, 0, name, ndev);
1334 netdev_err(ndev, "cannot request IRQ %s\n", name);
1339 /* Network device open function for Ethernet AVB */
1340 static int ravb_open(struct net_device *ndev)
1342 struct ravb_private *priv = netdev_priv(ndev);
1343 struct platform_device *pdev = priv->pdev;
1344 struct device *dev = &pdev->dev;
1347 napi_enable(&priv->napi[RAVB_BE]);
1348 napi_enable(&priv->napi[RAVB_NC]);
1350 if (priv->chip_id == RCAR_GEN2) {
1351 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1354 netdev_err(ndev, "cannot request IRQ\n");
1358 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1362 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1366 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1367 ndev, dev, "ch0:rx_be");
1369 goto out_free_irq_emac;
1370 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1371 ndev, dev, "ch18:tx_be");
1373 goto out_free_irq_be_rx;
1374 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1375 ndev, dev, "ch1:rx_nc");
1377 goto out_free_irq_be_tx;
1378 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1379 ndev, dev, "ch19:tx_nc");
1381 goto out_free_irq_nc_rx;
1385 error = ravb_dmac_init(ndev);
1387 goto out_free_irq_nc_tx;
1388 ravb_emac_init(ndev);
1390 /* Initialise PTP Clock driver */
1391 if (priv->chip_id == RCAR_GEN2)
1392 ravb_ptp_init(ndev, priv->pdev);
1394 netif_tx_start_all_queues(ndev);
1396 /* PHY control start */
1397 error = ravb_phy_start(ndev);
1404 /* Stop PTP Clock driver */
1405 if (priv->chip_id == RCAR_GEN2)
1406 ravb_ptp_stop(ndev);
1408 if (priv->chip_id == RCAR_GEN2)
1410 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1412 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1414 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1416 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1418 free_irq(priv->emac_irq, ndev);
1420 free_irq(ndev->irq, ndev);
1422 napi_disable(&priv->napi[RAVB_NC]);
1423 napi_disable(&priv->napi[RAVB_BE]);
1427 /* Timeout function for Ethernet AVB */
1428 static void ravb_tx_timeout(struct net_device *ndev)
1430 struct ravb_private *priv = netdev_priv(ndev);
1432 netif_err(priv, tx_err, ndev,
1433 "transmit timed out, status %08x, resetting...\n",
1434 ravb_read(ndev, ISS));
1436 /* tx_errors count up */
1437 ndev->stats.tx_errors++;
1439 schedule_work(&priv->work);
1442 static void ravb_tx_timeout_work(struct work_struct *work)
1444 struct ravb_private *priv = container_of(work, struct ravb_private,
1446 struct net_device *ndev = priv->ndev;
1449 netif_tx_stop_all_queues(ndev);
1451 /* Stop PTP Clock driver */
1452 if (priv->chip_id == RCAR_GEN2)
1453 ravb_ptp_stop(ndev);
1455 /* Wait for DMA stopping */
1456 if (ravb_stop_dma(ndev)) {
1457 /* If ravb_stop_dma() fails, the hardware is still operating
1458 * for TX and/or RX. So, this should not call the following
1459 * functions because ravb_dmac_init() is possible to fail too.
1460 * Also, this should not retry ravb_stop_dma() again and again
1461 * here because it's possible to wait forever. So, this just
1462 * re-enables the TX and RX and skip the following
1463 * re-initialization procedure.
1465 ravb_rcv_snd_enable(ndev);
1469 ravb_ring_free(ndev, RAVB_BE);
1470 ravb_ring_free(ndev, RAVB_NC);
1473 error = ravb_dmac_init(ndev);
1475 /* If ravb_dmac_init() fails, descriptors are freed. So, this
1476 * should return here to avoid re-enabling the TX and RX in
1479 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n",
1483 ravb_emac_init(ndev);
1486 /* Initialise PTP Clock driver */
1487 if (priv->chip_id == RCAR_GEN2)
1488 ravb_ptp_init(ndev, priv->pdev);
1490 netif_tx_start_all_queues(ndev);
1493 /* Packet transmit function for Ethernet AVB */
1494 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1496 struct ravb_private *priv = netdev_priv(ndev);
1497 u16 q = skb_get_queue_mapping(skb);
1498 struct ravb_tstamp_skb *ts_skb;
1499 struct ravb_tx_desc *desc;
1500 unsigned long flags;
1506 spin_lock_irqsave(&priv->lock, flags);
1507 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1509 netif_err(priv, tx_queued, ndev,
1510 "still transmitting with the full ring!\n");
1511 netif_stop_subqueue(ndev, q);
1512 spin_unlock_irqrestore(&priv->lock, flags);
1513 return NETDEV_TX_BUSY;
1515 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1516 priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
1518 if (skb_put_padto(skb, ETH_ZLEN))
1521 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1522 entry / NUM_TX_DESC * DPTR_ALIGN;
1523 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1524 /* Zero length DMA descriptors are problematic as they seem to
1525 * terminate DMA transfers. Avoid them by simply using a length of
1526 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN.
1528 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of
1529 * data by the call to skb_put_padto() above this is safe with
1530 * respect to both the length of the first DMA descriptor (len)
1531 * overflowing the available data and the length of the second DMA
1532 * descriptor (skb->len - len) being negative.
1537 memcpy(buffer, skb->data, len);
1538 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1539 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1542 desc = &priv->tx_ring[q][entry];
1543 desc->ds_tagl = cpu_to_le16(len);
1544 desc->dptr = cpu_to_le32(dma_addr);
1546 buffer = skb->data + len;
1547 len = skb->len - len;
1548 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1549 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1553 desc->ds_tagl = cpu_to_le16(len);
1554 desc->dptr = cpu_to_le32(dma_addr);
1556 /* TX timestamp required */
1558 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1561 dma_unmap_single(ndev->dev.parent, dma_addr, len,
1565 ts_skb->skb = skb_get(skb);
1566 ts_skb->tag = priv->ts_skb_tag++;
1567 priv->ts_skb_tag &= 0x3ff;
1568 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1570 /* TAG and timestamp required flag */
1571 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1572 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1573 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1576 skb_tx_timestamp(skb);
1577 /* Descriptor type must be set after all the above writes */
1579 desc->die_dt = DT_FEND;
1581 desc->die_dt = DT_FSTART;
1583 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
1585 priv->cur_tx[q] += NUM_TX_DESC;
1586 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1587 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC &&
1588 !ravb_tx_free(ndev, q, true))
1589 netif_stop_subqueue(ndev, q);
1593 spin_unlock_irqrestore(&priv->lock, flags);
1594 return NETDEV_TX_OK;
1597 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1598 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1600 dev_kfree_skb_any(skb);
1601 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
1605 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1606 void *accel_priv, select_queue_fallback_t fallback)
1608 /* If skb needs TX timestamp, it is handled in network control queue */
1609 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1614 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1616 struct ravb_private *priv = netdev_priv(ndev);
1617 struct net_device_stats *nstats, *stats0, *stats1;
1619 nstats = &ndev->stats;
1620 stats0 = &priv->stats[RAVB_BE];
1621 stats1 = &priv->stats[RAVB_NC];
1623 nstats->tx_dropped += ravb_read(ndev, TROCR);
1624 ravb_write(ndev, 0, TROCR); /* (write clear) */
1625 nstats->collisions += ravb_read(ndev, CDCR);
1626 ravb_write(ndev, 0, CDCR); /* (write clear) */
1627 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1628 ravb_write(ndev, 0, LCCR); /* (write clear) */
1630 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1631 ravb_write(ndev, 0, CERCR); /* (write clear) */
1632 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1633 ravb_write(ndev, 0, CEECR); /* (write clear) */
1635 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1636 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1637 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1638 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1639 nstats->multicast = stats0->multicast + stats1->multicast;
1640 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1641 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1642 nstats->rx_frame_errors =
1643 stats0->rx_frame_errors + stats1->rx_frame_errors;
1644 nstats->rx_length_errors =
1645 stats0->rx_length_errors + stats1->rx_length_errors;
1646 nstats->rx_missed_errors =
1647 stats0->rx_missed_errors + stats1->rx_missed_errors;
1648 nstats->rx_over_errors =
1649 stats0->rx_over_errors + stats1->rx_over_errors;
1654 /* Update promiscuous bit */
1655 static void ravb_set_rx_mode(struct net_device *ndev)
1657 struct ravb_private *priv = netdev_priv(ndev);
1658 unsigned long flags;
1660 spin_lock_irqsave(&priv->lock, flags);
1661 ravb_modify(ndev, ECMR, ECMR_PRM,
1662 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
1664 spin_unlock_irqrestore(&priv->lock, flags);
1667 /* Device close function for Ethernet AVB */
1668 static int ravb_close(struct net_device *ndev)
1670 struct device_node *np = ndev->dev.parent->of_node;
1671 struct ravb_private *priv = netdev_priv(ndev);
1672 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1674 netif_tx_stop_all_queues(ndev);
1676 /* Disable interrupts by clearing the interrupt masks. */
1677 ravb_write(ndev, 0, RIC0);
1678 ravb_write(ndev, 0, RIC2);
1679 ravb_write(ndev, 0, TIC);
1681 /* Stop PTP Clock driver */
1682 if (priv->chip_id == RCAR_GEN2)
1683 ravb_ptp_stop(ndev);
1685 /* Set the config mode to stop the AVB-DMAC's processes */
1686 if (ravb_stop_dma(ndev) < 0)
1688 "device will be stopped after h/w processes are done.\n");
1690 /* Clear the timestamp list */
1691 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1692 list_del(&ts_skb->list);
1693 kfree_skb(ts_skb->skb);
1697 /* PHY disconnect */
1699 phy_stop(ndev->phydev);
1700 phy_disconnect(ndev->phydev);
1701 if (of_phy_is_fixed_link(np))
1702 of_phy_deregister_fixed_link(np);
1705 if (priv->chip_id != RCAR_GEN2) {
1706 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1707 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1708 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1709 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1710 free_irq(priv->emac_irq, ndev);
1712 free_irq(ndev->irq, ndev);
1714 napi_disable(&priv->napi[RAVB_NC]);
1715 napi_disable(&priv->napi[RAVB_BE]);
1717 /* Free all the skb's in the RX queue and the DMA buffers. */
1718 ravb_ring_free(ndev, RAVB_BE);
1719 ravb_ring_free(ndev, RAVB_NC);
1724 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1726 struct ravb_private *priv = netdev_priv(ndev);
1727 struct hwtstamp_config config;
1730 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1732 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) {
1733 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT:
1734 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1736 case RAVB_RXTSTAMP_TYPE_ALL:
1737 config.rx_filter = HWTSTAMP_FILTER_ALL;
1740 config.rx_filter = HWTSTAMP_FILTER_NONE;
1743 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1747 /* Control hardware time stamping */
1748 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1750 struct ravb_private *priv = netdev_priv(ndev);
1751 struct hwtstamp_config config;
1752 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1755 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1758 /* Reserved for future extensions */
1762 switch (config.tx_type) {
1763 case HWTSTAMP_TX_OFF:
1766 case HWTSTAMP_TX_ON:
1767 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1773 switch (config.rx_filter) {
1774 case HWTSTAMP_FILTER_NONE:
1777 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1778 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1781 config.rx_filter = HWTSTAMP_FILTER_ALL;
1782 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1785 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1786 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1788 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1792 /* ioctl to device function */
1793 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1795 struct phy_device *phydev = ndev->phydev;
1797 if (!netif_running(ndev))
1805 return ravb_hwtstamp_get(ndev, req);
1807 return ravb_hwtstamp_set(ndev, req);
1810 return phy_mii_ioctl(phydev, req, cmd);
1813 static const struct net_device_ops ravb_netdev_ops = {
1814 .ndo_open = ravb_open,
1815 .ndo_stop = ravb_close,
1816 .ndo_start_xmit = ravb_start_xmit,
1817 .ndo_select_queue = ravb_select_queue,
1818 .ndo_get_stats = ravb_get_stats,
1819 .ndo_set_rx_mode = ravb_set_rx_mode,
1820 .ndo_tx_timeout = ravb_tx_timeout,
1821 .ndo_do_ioctl = ravb_do_ioctl,
1822 .ndo_validate_addr = eth_validate_addr,
1823 .ndo_set_mac_address = eth_mac_addr,
1824 .ndo_change_mtu = eth_change_mtu,
1827 /* MDIO bus init function */
1828 static int ravb_mdio_init(struct ravb_private *priv)
1830 struct platform_device *pdev = priv->pdev;
1831 struct device *dev = &pdev->dev;
1835 priv->mdiobb.ops = &bb_ops;
1837 /* MII controller setting */
1838 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1842 /* Hook up MII support for ethtool */
1843 priv->mii_bus->name = "ravb_mii";
1844 priv->mii_bus->parent = dev;
1845 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1846 pdev->name, pdev->id);
1848 /* Register MDIO bus */
1849 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1856 free_mdio_bitbang(priv->mii_bus);
1860 /* MDIO bus release function */
1861 static int ravb_mdio_release(struct ravb_private *priv)
1863 /* Unregister mdio bus */
1864 mdiobus_unregister(priv->mii_bus);
1866 /* Free bitbang info */
1867 free_mdio_bitbang(priv->mii_bus);
1872 static const struct of_device_id ravb_match_table[] = {
1873 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1874 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1875 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
1876 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1877 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
1880 MODULE_DEVICE_TABLE(of, ravb_match_table);
1882 static int ravb_set_gti(struct net_device *ndev)
1885 struct device *dev = ndev->dev.parent;
1886 struct device_node *np = dev->of_node;
1891 clk = of_clk_get(np, 0);
1893 dev_err(dev, "could not get clock\n");
1894 return PTR_ERR(clk);
1897 rate = clk_get_rate(clk);
1903 inc = 1000000000ULL << 20;
1906 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1907 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1908 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1912 ravb_write(ndev, inc, GTI);
1917 static void ravb_set_config_mode(struct net_device *ndev)
1919 struct ravb_private *priv = netdev_priv(ndev);
1921 if (priv->chip_id == RCAR_GEN2) {
1922 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
1923 /* Set CSEL value */
1924 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1926 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
1927 CCC_GAC | CCC_CSEL_HPB);
1931 static int ravb_probe(struct platform_device *pdev)
1933 struct device_node *np = pdev->dev.of_node;
1934 struct ravb_private *priv;
1935 enum ravb_chip_id chip_id;
1936 struct net_device *ndev;
1938 struct resource *res;
1943 "this driver is required to be instantiated from device tree\n");
1947 /* Get base address */
1948 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1950 dev_err(&pdev->dev, "invalid resource\n");
1954 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
1955 NUM_TX_QUEUE, NUM_RX_QUEUE);
1959 pm_runtime_enable(&pdev->dev);
1960 pm_runtime_get_sync(&pdev->dev);
1962 /* The Ether-specific entries in the device structure. */
1963 ndev->base_addr = res->start;
1965 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
1967 if (chip_id == RCAR_GEN3)
1968 irq = platform_get_irq_byname(pdev, "ch22");
1970 irq = platform_get_irq(pdev, 0);
1977 SET_NETDEV_DEV(ndev, &pdev->dev);
1979 priv = netdev_priv(ndev);
1982 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
1983 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
1984 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
1985 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
1986 priv->addr = devm_ioremap_resource(&pdev->dev, res);
1987 if (IS_ERR(priv->addr)) {
1988 error = PTR_ERR(priv->addr);
1992 spin_lock_init(&priv->lock);
1993 INIT_WORK(&priv->work, ravb_tx_timeout_work);
1995 priv->phy_interface = of_get_phy_mode(np);
1997 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
1998 priv->avb_link_active_low =
1999 of_property_read_bool(np, "renesas,ether-link-active-low");
2001 if (chip_id == RCAR_GEN3) {
2002 irq = platform_get_irq_byname(pdev, "ch24");
2007 priv->emac_irq = irq;
2008 for (i = 0; i < NUM_RX_QUEUE; i++) {
2009 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2014 priv->rx_irqs[i] = irq;
2016 for (i = 0; i < NUM_TX_QUEUE; i++) {
2017 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2022 priv->tx_irqs[i] = irq;
2026 priv->chip_id = chip_id;
2029 ndev->netdev_ops = &ravb_netdev_ops;
2030 ndev->ethtool_ops = &ravb_ethtool_ops;
2032 /* Set AVB config mode */
2033 ravb_set_config_mode(ndev);
2036 error = ravb_set_gti(ndev);
2040 /* Request GTI loading */
2041 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2043 /* Allocate descriptor base address table */
2044 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2045 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2046 &priv->desc_bat_dma, GFP_KERNEL);
2047 if (!priv->desc_bat) {
2049 "Cannot allocate desc base address table (size %d bytes)\n",
2050 priv->desc_bat_size);
2054 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2055 priv->desc_bat[q].die_dt = DT_EOS;
2056 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2058 /* Initialise HW timestamp list */
2059 INIT_LIST_HEAD(&priv->ts_skb_list);
2061 /* Initialise PTP Clock driver */
2062 if (chip_id != RCAR_GEN2)
2063 ravb_ptp_init(ndev, pdev);
2065 /* Debug message level */
2066 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2068 /* Read and set MAC address */
2069 ravb_read_mac_address(ndev, of_get_mac_address(np));
2070 if (!is_valid_ether_addr(ndev->dev_addr)) {
2071 dev_warn(&pdev->dev,
2072 "no valid MAC address supplied, using a random one\n");
2073 eth_hw_addr_random(ndev);
2077 error = ravb_mdio_init(priv);
2079 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2083 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2084 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2086 /* Network device register */
2087 error = register_netdev(ndev);
2091 /* Print device information */
2092 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2093 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2095 platform_set_drvdata(pdev, ndev);
2100 netif_napi_del(&priv->napi[RAVB_NC]);
2101 netif_napi_del(&priv->napi[RAVB_BE]);
2102 ravb_mdio_release(priv);
2104 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2105 priv->desc_bat_dma);
2107 /* Stop PTP Clock driver */
2108 if (chip_id != RCAR_GEN2)
2109 ravb_ptp_stop(ndev);
2114 pm_runtime_put(&pdev->dev);
2115 pm_runtime_disable(&pdev->dev);
2119 static int ravb_remove(struct platform_device *pdev)
2121 struct net_device *ndev = platform_get_drvdata(pdev);
2122 struct ravb_private *priv = netdev_priv(ndev);
2124 /* Stop PTP Clock driver */
2125 if (priv->chip_id != RCAR_GEN2)
2126 ravb_ptp_stop(ndev);
2128 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2129 priv->desc_bat_dma);
2130 /* Set reset mode */
2131 ravb_write(ndev, CCC_OPC_RESET, CCC);
2132 pm_runtime_put_sync(&pdev->dev);
2133 unregister_netdev(ndev);
2134 netif_napi_del(&priv->napi[RAVB_NC]);
2135 netif_napi_del(&priv->napi[RAVB_BE]);
2136 ravb_mdio_release(priv);
2137 pm_runtime_disable(&pdev->dev);
2139 platform_set_drvdata(pdev, NULL);
2144 static int __maybe_unused ravb_suspend(struct device *dev)
2146 struct net_device *ndev = dev_get_drvdata(dev);
2149 if (netif_running(ndev)) {
2150 netif_device_detach(ndev);
2151 ret = ravb_close(ndev);
2157 static int __maybe_unused ravb_resume(struct device *dev)
2159 struct net_device *ndev = dev_get_drvdata(dev);
2160 struct ravb_private *priv = netdev_priv(ndev);
2163 /* All register have been reset to default values.
2164 * Restore all registers which where setup at probe time and
2165 * reopen device if it was running before system suspended.
2168 /* Set AVB config mode */
2169 ravb_set_config_mode(ndev);
2172 ret = ravb_set_gti(ndev);
2176 /* Request GTI loading */
2177 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2179 /* Restore descriptor base address table */
2180 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2182 if (netif_running(ndev)) {
2183 ret = ravb_open(ndev);
2186 netif_device_attach(ndev);
2192 static int __maybe_unused ravb_runtime_nop(struct device *dev)
2194 /* Runtime PM callback shared between ->runtime_suspend()
2195 * and ->runtime_resume(). Simply returns success.
2197 * This driver re-initializes all registers after
2198 * pm_runtime_get_sync() anyway so there is no need
2199 * to save and restore registers here.
2204 static const struct dev_pm_ops ravb_dev_pm_ops = {
2205 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
2206 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
2209 static struct platform_driver ravb_driver = {
2210 .probe = ravb_probe,
2211 .remove = ravb_remove,
2214 .pm = &ravb_dev_pm_ops,
2215 .of_match_table = ravb_match_table,
2219 module_platform_driver(ravb_driver);
2221 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2222 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2223 MODULE_LICENSE("GPL v2");