drivers/net/ethernet/realtek/r8169_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/in.h>
  22 #include <linux/io.h>
  23 #include <linux/ip.h>
  24 #include <linux/tcp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/bitfield.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include "r8169.h"
  34 #include "r8169_firmware.h"
  35
  36 #define MODULENAME "r8169"
  37
  38 #define FIRMWARE_8168D_1        "/*(DEBLOBBED)*/"
  39 #define FIRMWARE_8168D_2        "/*(DEBLOBBED)*/"
  40 #define FIRMWARE_8168E_1        "/*(DEBLOBBED)*/"
  41 #define FIRMWARE_8168E_2        "/*(DEBLOBBED)*/"
  42 #define FIRMWARE_8168E_3        "/*(DEBLOBBED)*/"
  43 #define FIRMWARE_8168F_1        "/*(DEBLOBBED)*/"
  44 #define FIRMWARE_8168F_2        "/*(DEBLOBBED)*/"
  45 #define FIRMWARE_8105E_1        "/*(DEBLOBBED)*/"
  46 #define FIRMWARE_8402_1         "/*(DEBLOBBED)*/"
  47 #define FIRMWARE_8411_1         "/*(DEBLOBBED)*/"
  48 #define FIRMWARE_8411_2         "/*(DEBLOBBED)*/"
  49 #define FIRMWARE_8106E_1        "/*(DEBLOBBED)*/"
  50 #define FIRMWARE_8106E_2        "/*(DEBLOBBED)*/"
  51 #define FIRMWARE_8168G_2        "/*(DEBLOBBED)*/"
  52 #define FIRMWARE_8168G_3        "/*(DEBLOBBED)*/"
  53 #define FIRMWARE_8168H_1        "/*(DEBLOBBED)*/"
  54 #define FIRMWARE_8168H_2        "/*(DEBLOBBED)*/"
  55 #define FIRMWARE_8168FP_3       "/*(DEBLOBBED)*/"
  56 #define FIRMWARE_8107E_1        "/*(DEBLOBBED)*/"
  57 #define FIRMWARE_8107E_2        "/*(DEBLOBBED)*/"
  58 #define FIRMWARE_8125A_3        "/*(DEBLOBBED)*/"
  59 #define FIRMWARE_8125B_2        "/*(DEBLOBBED)*/"
  60
  61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  62    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  63 #define MC_FILTER_LIMIT 32
  64
  65 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  66 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  67
  68 #define R8169_REGS_SIZE         256
  69 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  70 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  71 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  72 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  73 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  74
  75 #define OCP_STD_PHY_BASE        0xa400
  76
  77 #define RTL_CFG_NO_GBIT 1
  78
  79 /* write/read MMIO register */
  80 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  83 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  84 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  85 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  86
  87 #define JUMBO_4K        (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  88 #define JUMBO_6K        (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  89 #define JUMBO_7K        (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  90 #define JUMBO_9K        (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  91
  92 static const struct {
  93         const char *name;
  94         const char *fw_name;
  95 } rtl_chip_infos[] = {
  96         /* PCI devices. */
  97         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
  98         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
  99         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 100         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 101         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 102         /* PCI-E devices. */
 103         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 104         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 105         [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 106         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 107         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 108         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 109         [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e"                    },
 110         [RTL_GIGA_MAC_VER_14] = {"RTL8401"                              },
 111         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 112         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 113         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 114         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 115         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 116         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 117         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 118         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 119         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 120         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 121         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 122         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 123         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 124         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 125         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 126         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 127         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 128         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 129         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 130         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 131         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 132         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 133         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 134         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 135         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 136         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 137         [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 138         [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 139         [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 140         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 141         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 142         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 143         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 144         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 145         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 146         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 147         [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117",  FIRMWARE_8168FP_3},
 148         [RTL_GIGA_MAC_VER_60] = {"RTL8125A"                             },
 149         [RTL_GIGA_MAC_VER_61] = {"RTL8125A",            FIRMWARE_8125A_3},
 150         /* reserve 62 for CFG_METHOD_4 in the vendor driver */
 151         [RTL_GIGA_MAC_VER_63] = {"RTL8125B",            FIRMWARE_8125B_2},
 152 };
 153
 154 static const struct pci_device_id rtl8169_pci_tbl[] = {
 155         { PCI_VDEVICE(REALTEK,  0x2502) },
 156         { PCI_VDEVICE(REALTEK,  0x2600) },
 157         { PCI_VDEVICE(REALTEK,  0x8129) },
 158         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 159         { PCI_VDEVICE(REALTEK,  0x8161) },
 160         { PCI_VDEVICE(REALTEK,  0x8162) },
 161         { PCI_VDEVICE(REALTEK,  0x8167) },
 162         { PCI_VDEVICE(REALTEK,  0x8168) },
 163         { PCI_VDEVICE(NCUBE,    0x8168) },
 164         { PCI_VDEVICE(REALTEK,  0x8169) },
 165         { PCI_VENDOR_ID_DLINK,  0x4300,
 166                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 167         { PCI_VDEVICE(DLINK,    0x4300) },
 168         { PCI_VDEVICE(DLINK,    0x4302) },
 169         { PCI_VDEVICE(AT,       0xc107) },
 170         { PCI_VDEVICE(USR,      0x0116) },
 171         { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 172         { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 173         { PCI_VDEVICE(REALTEK,  0x8125) },
 174         { PCI_VDEVICE(REALTEK,  0x3000) },
 175         {}
 176 };
 177
 178 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 179
 180 enum rtl_registers {
 181         MAC0            = 0,    /* Ethernet hardware address. */
 182         MAC4            = 4,
 183         MAR0            = 8,    /* Multicast filter. */
 184         CounterAddrLow          = 0x10,
 185         CounterAddrHigh         = 0x14,
 186         TxDescStartAddrLow      = 0x20,
 187         TxDescStartAddrHigh     = 0x24,
 188         TxHDescStartAddrLow     = 0x28,
 189         TxHDescStartAddrHigh    = 0x2c,
 190         FLASH           = 0x30,
 191         ERSR            = 0x36,
 192         ChipCmd         = 0x37,
 193         TxPoll          = 0x38,
 194         IntrMask        = 0x3c,
 195         IntrStatus      = 0x3e,
 196
 197         TxConfig        = 0x40,
 198 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 199 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 200
 201         RxConfig        = 0x44,
 202 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 203 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 204 #define RXCFG_FIFO_SHIFT                13
 205                                         /* No threshold before first PCI xfer */
 206 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 207 #define RX_EARLY_OFF                    (1 << 11)
 208 #define RX_PAUSE_SLOT_ON                (1 << 11)       /* 8125b and later */
 209 #define RXCFG_DMA_SHIFT                 8
 210                                         /* Unlimited maximum PCI burst. */
 211 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 212
 213         Cfg9346         = 0x50,
 214         Config0         = 0x51,
 215         Config1         = 0x52,
 216         Config2         = 0x53,
 217 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 218
 219         Config3         = 0x54,
 220         Config4         = 0x55,
 221         Config5         = 0x56,
 222         PHYAR           = 0x60,
 223         PHYstatus       = 0x6c,
 224         RxMaxSize       = 0xda,
 225         CPlusCmd        = 0xe0,
 226         IntrMitigate    = 0xe2,
 227
 228 #define RTL_COALESCE_TX_USECS   GENMASK(15, 12)
 229 #define RTL_COALESCE_TX_FRAMES  GENMASK(11, 8)
 230 #define RTL_COALESCE_RX_USECS   GENMASK(7, 4)
 231 #define RTL_COALESCE_RX_FRAMES  GENMASK(3, 0)
 232
 233 #define RTL_COALESCE_T_MAX      0x0fU
 234 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_T_MAX * 4)
 235
 236         RxDescAddrLow   = 0xe4,
 237         RxDescAddrHigh  = 0xe8,
 238         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 239
 240 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 241
 242         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 243
 244 #define TxPacketMax     (8064 >> 7)
 245 #define EarlySize       0x27
 246
 247         FuncEvent       = 0xf0,
 248         FuncEventMask   = 0xf4,
 249         FuncPresetState = 0xf8,
 250         IBCR0           = 0xf8,
 251         IBCR2           = 0xf9,
 252         IBIMR0          = 0xfa,
 253         IBISR0          = 0xfb,
 254         FuncForceEvent  = 0xfc,
 255 };
 256
 257 enum rtl8168_8101_registers {
 258         CSIDR                   = 0x64,
 259         CSIAR                   = 0x68,
 260 #define CSIAR_FLAG                      0x80000000
 261 #define CSIAR_WRITE_CMD                 0x80000000
 262 #define CSIAR_BYTE_ENABLE               0x0000f000
 263 #define CSIAR_ADDR_MASK                 0x00000fff
 264         PMCH                    = 0x6f,
 265         EPHYAR                  = 0x80,
 266 #define EPHYAR_FLAG                     0x80000000
 267 #define EPHYAR_WRITE_CMD                0x80000000
 268 #define EPHYAR_REG_MASK                 0x1f
 269 #define EPHYAR_REG_SHIFT                16
 270 #define EPHYAR_DATA_MASK                0xffff
 271         DLLPR                   = 0xd0,
 272 #define PFM_EN                          (1 << 6)
 273 #define TX_10M_PS_EN                    (1 << 7)
 274         DBG_REG                 = 0xd1,
 275 #define FIX_NAK_1                       (1 << 4)
 276 #define FIX_NAK_2                       (1 << 3)
 277         TWSI                    = 0xd2,
 278         MCU                     = 0xd3,
 279 #define NOW_IS_OOB                      (1 << 7)
 280 #define TX_EMPTY                        (1 << 5)
 281 #define RX_EMPTY                        (1 << 4)
 282 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 283 #define EN_NDP                          (1 << 3)
 284 #define EN_OOB_RESET                    (1 << 2)
 285 #define LINK_LIST_RDY                   (1 << 1)
 286         EFUSEAR                 = 0xdc,
 287 #define EFUSEAR_FLAG                    0x80000000
 288 #define EFUSEAR_WRITE_CMD               0x80000000
 289 #define EFUSEAR_READ_CMD                0x00000000
 290 #define EFUSEAR_REG_MASK                0x03ff
 291 #define EFUSEAR_REG_SHIFT               8
 292 #define EFUSEAR_DATA_MASK               0xff
 293         MISC_1                  = 0xf2,
 294 #define PFM_D3COLD_EN                   (1 << 6)
 295 };
 296
 297 enum rtl8168_registers {
 298         LED_FREQ                = 0x1a,
 299         EEE_LED                 = 0x1b,
 300         ERIDR                   = 0x70,
 301         ERIAR                   = 0x74,
 302 #define ERIAR_FLAG                      0x80000000
 303 #define ERIAR_WRITE_CMD                 0x80000000
 304 #define ERIAR_READ_CMD                  0x00000000
 305 #define ERIAR_ADDR_BYTE_ALIGN           4
 306 #define ERIAR_TYPE_SHIFT                16
 307 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 308 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 309 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 310 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 311 #define ERIAR_MASK_SHIFT                12
 312 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 313 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 314 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 315 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 316 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 317         EPHY_RXER_NUM           = 0x7c,
 318         OCPDR                   = 0xb0, /* OCP GPHY access */
 319 #define OCPDR_WRITE_CMD                 0x80000000
 320 #define OCPDR_READ_CMD                  0x00000000
 321 #define OCPDR_REG_MASK                  0x7f
 322 #define OCPDR_GPHY_REG_SHIFT            16
 323 #define OCPDR_DATA_MASK                 0xffff
 324         OCPAR                   = 0xb4,
 325 #define OCPAR_FLAG                      0x80000000
 326 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 327 #define OCPAR_GPHY_READ_CMD             0x0000f060
 328         GPHY_OCP                = 0xb8,
 329         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 330         MISC                    = 0xf0, /* 8168e only. */
 331 #define TXPLA_RST                       (1 << 29)
 332 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 333 #define PWM_EN                          (1 << 22)
 334 #define RXDV_GATED_EN                   (1 << 19)
 335 #define EARLY_TALLY_EN                  (1 << 16)
 336 };
 337
 338 enum rtl8125_registers {
 339         IntrMask_8125           = 0x38,
 340         IntrStatus_8125         = 0x3c,
 341         TxPoll_8125             = 0x90,
 342         MAC0_BKP                = 0x19e0,
 343         EEE_TXIDLE_TIMER_8125   = 0x6048,
 344 };
 345
 346 #define RX_VLAN_INNER_8125      BIT(22)
 347 #define RX_VLAN_OUTER_8125      BIT(23)
 348 #define RX_VLAN_8125            (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
 349
 350 #define RX_FETCH_DFLT_8125      (8 << 27)
 351
 352 enum rtl_register_content {
 353         /* InterruptStatusBits */
 354         SYSErr          = 0x8000,
 355         PCSTimeout      = 0x4000,
 356         SWInt           = 0x0100,
 357         TxDescUnavail   = 0x0080,
 358         RxFIFOOver      = 0x0040,
 359         LinkChg         = 0x0020,
 360         RxOverflow      = 0x0010,
 361         TxErr           = 0x0008,
 362         TxOK            = 0x0004,
 363         RxErr           = 0x0002,
 364         RxOK            = 0x0001,
 365
 366         /* RxStatusDesc */
 367         RxRWT   = (1 << 22),
 368         RxRES   = (1 << 21),
 369         RxRUNT  = (1 << 20),
 370         RxCRC   = (1 << 19),
 371
 372         /* ChipCmdBits */
 373         StopReq         = 0x80,
 374         CmdReset        = 0x10,
 375         CmdRxEnb        = 0x08,
 376         CmdTxEnb        = 0x04,
 377         RxBufEmpty      = 0x01,
 378
 379         /* TXPoll register p.5 */
 380         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 381         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 382         FSWInt          = 0x01,         /* Forced software interrupt */
 383
 384         /* Cfg9346Bits */
 385         Cfg9346_Lock    = 0x00,
 386         Cfg9346_Unlock  = 0xc0,
 387
 388         /* rx_mode_bits */
 389         AcceptErr       = 0x20,
 390         AcceptRunt      = 0x10,
 391 #define RX_CONFIG_ACCEPT_ERR_MASK       0x30
 392         AcceptBroadcast = 0x08,
 393         AcceptMulticast = 0x04,
 394         AcceptMyPhys    = 0x02,
 395         AcceptAllPhys   = 0x01,
 396 #define RX_CONFIG_ACCEPT_OK_MASK        0x0f
 397 #define RX_CONFIG_ACCEPT_MASK           0x3f
 398
 399         /* TxConfigBits */
 400         TxInterFrameGapShift = 24,
 401         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 402
 403         /* Config1 register p.24 */
 404         LEDS1           = (1 << 7),
 405         LEDS0           = (1 << 6),
 406         Speed_down      = (1 << 4),
 407         MEMMAP          = (1 << 3),
 408         IOMAP           = (1 << 2),
 409         VPD             = (1 << 1),
 410         PMEnable        = (1 << 0),     /* Power Management Enable */
 411
 412         /* Config2 register p. 25 */
 413         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 414         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 415         PCI_Clock_66MHz = 0x01,
 416         PCI_Clock_33MHz = 0x00,
 417
 418         /* Config3 register p.25 */
 419         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 420         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 421         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 422         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 423         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 424
 425         /* Config4 register */
 426         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 427
 428         /* Config5 register p.27 */
 429         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 430         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 431         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 432         Spi_en          = (1 << 3),
 433         LanWake         = (1 << 1),     /* LanWake enable/disable */
 434         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 435         ASPM_en         = (1 << 0),     /* ASPM enable */
 436
 437         /* CPlusCmd p.31 */
 438         EnableBist      = (1 << 15),    // 8168 8101
 439         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 440         EnAnaPLL        = (1 << 14),    // 8169
 441         Normal_mode     = (1 << 13),    // unused
 442         Force_half_dup  = (1 << 12),    // 8168 8101
 443         Force_rxflow_en = (1 << 11),    // 8168 8101
 444         Force_txflow_en = (1 << 10),    // 8168 8101
 445         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 446         ASF             = (1 << 8),     // 8168 8101
 447         PktCntrDisable  = (1 << 7),     // 8168 8101
 448         Mac_dbgo_sel    = 0x001c,       // 8168
 449         RxVlan          = (1 << 6),
 450         RxChkSum        = (1 << 5),
 451         PCIDAC          = (1 << 4),
 452         PCIMulRW        = (1 << 3),
 453 #define INTT_MASK       GENMASK(1, 0)
 454 #define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 455
 456         /* rtl8169_PHYstatus */
 457         TBI_Enable      = 0x80,
 458         TxFlowCtrl      = 0x40,
 459         RxFlowCtrl      = 0x20,
 460         _1000bpsF       = 0x10,
 461         _100bps         = 0x08,
 462         _10bps          = 0x04,
 463         LinkStatus      = 0x02,
 464         FullDup         = 0x01,
 465
 466         /* ResetCounterCommand */
 467         CounterReset    = 0x1,
 468
 469         /* DumpCounterCommand */
 470         CounterDump     = 0x8,
 471
 472         /* magic enable v2 */
 473         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 474 };
 475
 476 enum rtl_desc_bit {
 477         /* First doubleword. */
 478         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 479         RingEnd         = (1 << 30), /* End of descriptor ring */
 480         FirstFrag       = (1 << 29), /* First segment of a packet */
 481         LastFrag        = (1 << 28), /* Final segment of a packet */
 482 };
 483
 484 /* Generic case. */
 485 enum rtl_tx_desc_bit {
 486         /* First doubleword. */
 487         TD_LSO          = (1 << 27),            /* Large Send Offload */
 488 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 489
 490         /* Second doubleword. */
 491         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 492 };
 493
 494 /* 8169, 8168b and 810x except 8102e. */
 495 enum rtl_tx_desc_bit_0 {
 496         /* First doubleword. */
 497 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 498         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 499         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 500         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 501 };
 502
 503 /* 8102e, 8168c and beyond. */
 504 enum rtl_tx_desc_bit_1 {
 505         /* First doubleword. */
 506         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 507         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 508 #define GTTCPHO_SHIFT                   18
 509 #define GTTCPHO_MAX                     0x7f
 510
 511         /* Second doubleword. */
 512 #define TCPHO_SHIFT                     18
 513 #define TCPHO_MAX                       0x3ff
 514 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 515         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 516         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 517         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 518         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 519 };
 520
 521 enum rtl_rx_desc_bit {
 522         /* Rx private */
 523         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 524         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 525
 526 #define RxProtoUDP      (PID1)
 527 #define RxProtoTCP      (PID0)
 528 #define RxProtoIP       (PID1 | PID0)
 529 #define RxProtoMask     RxProtoIP
 530
 531         IPFail          = (1 << 16), /* IP checksum failed */
 532         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 533         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 534         RxVlanTag       = (1 << 16), /* VLAN tag available */
 535 };
 536
 537 #define RTL_GSO_MAX_SIZE_V1     32000
 538 #define RTL_GSO_MAX_SEGS_V1     24
 539 #define RTL_GSO_MAX_SIZE_V2     64000
 540 #define RTL_GSO_MAX_SEGS_V2     64
 541
 542 struct TxDesc {
 543         __le32 opts1;
 544         __le32 opts2;
 545         __le64 addr;
 546 };
 547
 548 struct RxDesc {
 549         __le32 opts1;
 550         __le32 opts2;
 551         __le64 addr;
 552 };
 553
 554 struct ring_info {
 555         struct sk_buff  *skb;
 556         u32             len;
 557 };
 558
 559 struct rtl8169_counters {
 560         __le64  tx_packets;
 561         __le64  rx_packets;
 562         __le64  tx_errors;
 563         __le32  rx_errors;
 564         __le16  rx_missed;
 565         __le16  align_errors;
 566         __le32  tx_one_collision;
 567         __le32  tx_multi_collision;
 568         __le64  rx_unicast;
 569         __le64  rx_broadcast;
 570         __le32  rx_multicast;
 571         __le16  tx_aborted;
 572         __le16  tx_underun;
 573 };
 574
 575 struct rtl8169_tc_offsets {
 576         bool    inited;
 577         __le64  tx_errors;
 578         __le32  tx_multi_collision;
 579         __le16  tx_aborted;
 580         __le16  rx_missed;
 581 };
 582
 583 enum rtl_flag {
 584         RTL_FLAG_TASK_ENABLED = 0,
 585         RTL_FLAG_TASK_RESET_PENDING,
 586         RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE,
 587         RTL_FLAG_TASK_TX_TIMEOUT,
 588         RTL_FLAG_MAX
 589 };
 590
 591 struct rtl8169_stats {
 592         u64                     packets;
 593         u64                     bytes;
 594         struct u64_stats_sync   syncp;
 595 };
 596
 597 struct rtl8169_private {
 598         void __iomem *mmio_addr;        /* memory map physical address */
 599         struct pci_dev *pci_dev;
 600         struct net_device *dev;
 601         struct phy_device *phydev;
 602         struct napi_struct napi;
 603         enum mac_version mac_version;
 604         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 605         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 606         u32 dirty_tx;
 607         struct rtl8169_stats rx_stats;
 608         struct rtl8169_stats tx_stats;
 609         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 610         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 611         dma_addr_t TxPhyAddr;
 612         dma_addr_t RxPhyAddr;
 613         struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 614         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 615         u16 cp_cmd;
 616         u32 irq_mask;
 617         struct clk *clk;
 618
 619         struct {
 620                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 621                 struct work_struct work;
 622         } wk;
 623
 624         unsigned supports_gmii:1;
 625         unsigned aspm_manageable:1;
 626         dma_addr_t counters_phys_addr;
 627         struct rtl8169_counters *counters;
 628         struct rtl8169_tc_offsets tc_offset;
 629         u32 saved_wolopts;
 630         int eee_adv;
 631
 632         const char *fw_name;
 633         struct rtl_fw *rtl_fw;
 634
 635         u32 ocp_base;
 636 };
 637
 638 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 639
 640 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 641 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 642 MODULE_SOFTDEP("pre: realtek");
 643 MODULE_LICENSE("GPL");
 644 /*(DEBLOBBED)*/
 645
 646 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 647 {
 648         return &tp->pci_dev->dev;
 649 }
 650
 651 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 652 {
 653         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 654 }
 655
 656 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 657 {
 658         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 659 }
 660
 661 static void rtl_pci_commit(struct rtl8169_private *tp)
 662 {
 663         /* Read an arbitrary register to commit a preceding PCI write */
 664         RTL_R8(tp, ChipCmd);
 665 }
 666
 667 static bool rtl_is_8125(struct rtl8169_private *tp)
 668 {
 669         return tp->mac_version >= RTL_GIGA_MAC_VER_60;
 670 }
 671
 672 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 673 {
 674         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 675                tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 676                tp->mac_version <= RTL_GIGA_MAC_VER_52;
 677 }
 678
 679 static bool rtl_supports_eee(struct rtl8169_private *tp)
 680 {
 681         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 682                tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 683                tp->mac_version != RTL_GIGA_MAC_VER_39;
 684 }
 685
 686 static void rtl_get_priv_stats(struct rtl8169_stats *stats,
 687                                u64 *pkts, u64 *bytes)
 688 {
 689         unsigned int start;
 690
 691         do {
 692                 start = u64_stats_fetch_begin_irq(&stats->syncp);
 693                 *pkts = stats->packets;
 694                 *bytes = stats->bytes;
 695         } while (u64_stats_fetch_retry_irq(&stats->syncp, start));
 696 }
 697
 698 static void rtl_inc_priv_stats(struct rtl8169_stats *stats,
 699                                u64 pkts, u64 bytes)
 700 {
 701         u64_stats_update_begin(&stats->syncp);
 702         stats->packets += pkts;
 703         stats->bytes += bytes;
 704         u64_stats_update_end(&stats->syncp);
 705 }
 706
 707 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 708 {
 709         int i;
 710
 711         for (i = 0; i < ETH_ALEN; i++)
 712                 mac[i] = RTL_R8(tp, reg + i);
 713 }
 714
 715 struct rtl_cond {
 716         bool (*check)(struct rtl8169_private *);
 717         const char *msg;
 718 };
 719
 720 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 721                           unsigned long usecs, int n, bool high)
 722 {
 723         int i;
 724
 725         for (i = 0; i < n; i++) {
 726                 if (c->check(tp) == high)
 727                         return true;
 728                 fsleep(usecs);
 729         }
 730
 731         if (net_ratelimit())
 732                 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
 733                            c->msg, !high, n, usecs);
 734         return false;
 735 }
 736
 737 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
 738                                const struct rtl_cond *c,
 739                                unsigned long d, int n)
 740 {
 741         return rtl_loop_wait(tp, c, d, n, true);
 742 }
 743
 744 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
 745                               const struct rtl_cond *c,
 746                               unsigned long d, int n)
 747 {
 748         return rtl_loop_wait(tp, c, d, n, false);
 749 }
 750
 751 #define DECLARE_RTL_COND(name)                          \
 752 static bool name ## _check(struct rtl8169_private *);   \
 753                                                         \
 754 static const struct rtl_cond name = {                   \
 755         .check  = name ## _check,                       \
 756         .msg    = #name                                 \
 757 };                                                      \
 758                                                         \
 759 static bool name ## _check(struct rtl8169_private *tp)
 760
 761 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 762 {
 763         if (reg & 0xffff0001) {
 764                 if (net_ratelimit())
 765                         netdev_err(tp->dev, "Invalid ocp reg %x!\n", reg);
 766                 return true;
 767         }
 768         return false;
 769 }
 770
 771 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 772 {
 773         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 774 }
 775
 776 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 777 {
 778         if (rtl_ocp_reg_failure(tp, reg))
 779                 return;
 780
 781         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 782
 783         rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 784 }
 785
 786 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 787 {
 788         if (rtl_ocp_reg_failure(tp, reg))
 789                 return 0;
 790
 791         RTL_W32(tp, GPHY_OCP, reg << 15);
 792
 793         return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 794                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 795 }
 796
 797 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 798 {
 799         if (rtl_ocp_reg_failure(tp, reg))
 800                 return;
 801
 802         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 803 }
 804
 805 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 806 {
 807         if (rtl_ocp_reg_failure(tp, reg))
 808                 return 0;
 809
 810         RTL_W32(tp, OCPDR, reg << 15);
 811
 812         return RTL_R32(tp, OCPDR);
 813 }
 814
 815 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
 816                                  u16 set)
 817 {
 818         u16 data = r8168_mac_ocp_read(tp, reg);
 819
 820         r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
 821 }
 822
 823 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 824 {
 825         if (reg == 0x1f) {
 826                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 827                 return;
 828         }
 829
 830         if (tp->ocp_base != OCP_STD_PHY_BASE)
 831                 reg -= 0x10;
 832
 833         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 834 }
 835
 836 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 837 {
 838         if (reg == 0x1f)
 839                 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
 840
 841         if (tp->ocp_base != OCP_STD_PHY_BASE)
 842                 reg -= 0x10;
 843
 844         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 845 }
 846
 847 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 848 {
 849         if (reg == 0x1f) {
 850                 tp->ocp_base = value << 4;
 851                 return;
 852         }
 853
 854         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 855 }
 856
 857 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 858 {
 859         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 860 }
 861
 862 DECLARE_RTL_COND(rtl_phyar_cond)
 863 {
 864         return RTL_R32(tp, PHYAR) & 0x80000000;
 865 }
 866
 867 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 868 {
 869         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 870
 871         rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 872         /*
 873          * According to hardware specs a 20us delay is required after write
 874          * complete indication, but before sending next command.
 875          */
 876         udelay(20);
 877 }
 878
 879 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 880 {
 881         int value;
 882
 883         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 884
 885         value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 886                 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
 887
 888         /*
 889          * According to hardware specs a 20us delay is required after read
 890          * complete indication, but before sending next command.
 891          */
 892         udelay(20);
 893
 894         return value;
 895 }
 896
 897 DECLARE_RTL_COND(rtl_ocpar_cond)
 898 {
 899         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 900 }
 901
 902 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 903 {
 904         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 905         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 906         RTL_W32(tp, EPHY_RXER_NUM, 0);
 907
 908         rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 909 }
 910
 911 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 912 {
 913         r8168dp_1_mdio_access(tp, reg,
 914                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 915 }
 916
 917 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 918 {
 919         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 920
 921         mdelay(1);
 922         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 923         RTL_W32(tp, EPHY_RXER_NUM, 0);
 924
 925         return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 926                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
 927 }
 928
 929 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 930
 931 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 932 {
 933         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 934 }
 935
 936 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 937 {
 938         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 939 }
 940
 941 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 942 {
 943         r8168dp_2_mdio_start(tp);
 944
 945         r8169_mdio_write(tp, reg, value);
 946
 947         r8168dp_2_mdio_stop(tp);
 948 }
 949
 950 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
 951 {
 952         int value;
 953
 954         /* Work around issue with chip reporting wrong PHY ID */
 955         if (reg == MII_PHYSID2)
 956                 return 0xc912;
 957
 958         r8168dp_2_mdio_start(tp);
 959
 960         value = r8169_mdio_read(tp, reg);
 961
 962         r8168dp_2_mdio_stop(tp);
 963
 964         return value;
 965 }
 966
 967 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
 968 {
 969         switch (tp->mac_version) {
 970         case RTL_GIGA_MAC_VER_27:
 971                 r8168dp_1_mdio_write(tp, location, val);
 972                 break;
 973         case RTL_GIGA_MAC_VER_28:
 974         case RTL_GIGA_MAC_VER_31:
 975                 r8168dp_2_mdio_write(tp, location, val);
 976                 break;
 977         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
 978                 r8168g_mdio_write(tp, location, val);
 979                 break;
 980         default:
 981                 r8169_mdio_write(tp, location, val);
 982                 break;
 983         }
 984 }
 985
 986 static int rtl_readphy(struct rtl8169_private *tp, int location)
 987 {
 988         switch (tp->mac_version) {
 989         case RTL_GIGA_MAC_VER_27:
 990                 return r8168dp_1_mdio_read(tp, location);
 991         case RTL_GIGA_MAC_VER_28:
 992         case RTL_GIGA_MAC_VER_31:
 993                 return r8168dp_2_mdio_read(tp, location);
 994         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
 995                 return r8168g_mdio_read(tp, location);
 996         default:
 997                 return r8169_mdio_read(tp, location);
 998         }
 999 }
1000
1001 DECLARE_RTL_COND(rtl_ephyar_cond)
1002 {
1003         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1004 }
1005
1006 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1007 {
1008         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1009                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1010
1011         rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1012
1013         udelay(10);
1014 }
1015
1016 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1017 {
1018         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1019
1020         return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1021                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1022 }
1023
1024 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
1025 {
1026         /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
1027         if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB)
1028                 *cmd |= 0xf70 << 18;
1029 }
1030
1031 DECLARE_RTL_COND(rtl_eriar_cond)
1032 {
1033         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1034 }
1035
1036 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1037                            u32 val, int type)
1038 {
1039         u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
1040
1041         BUG_ON((addr & 3) || (mask == 0));
1042         RTL_W32(tp, ERIDR, val);
1043         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1044         RTL_W32(tp, ERIAR, cmd);
1045
1046         rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1047 }
1048
1049 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1050                           u32 val)
1051 {
1052         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1053 }
1054
1055 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1056 {
1057         u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
1058
1059         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1060         RTL_W32(tp, ERIAR, cmd);
1061
1062         return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1063                 RTL_R32(tp, ERIDR) : ~0;
1064 }
1065
1066 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1067 {
1068         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1069 }
1070
1071 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
1072 {
1073         u32 val = rtl_eri_read(tp, addr);
1074
1075         rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
1076 }
1077
1078 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
1079 {
1080         rtl_w0w1_eri(tp, addr, p, 0);
1081 }
1082
1083 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
1084 {
1085         rtl_w0w1_eri(tp, addr, 0, m);
1086 }
1087
1088 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1089 {
1090         RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1091         return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1092                 RTL_R32(tp, OCPDR) : ~0;
1093 }
1094
1095 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1096 {
1097         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1098 }
1099
1100 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1101                               u32 data)
1102 {
1103         RTL_W32(tp, OCPDR, data);
1104         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1105         rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1106 }
1107
1108 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1109                               u32 data)
1110 {
1111         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1112                        data, ERIAR_OOB);
1113 }
1114
1115 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1116 {
1117         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1118
1119         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1120 }
1121
1122 #define OOB_CMD_RESET           0x00
1123 #define OOB_CMD_DRIVER_START    0x05
1124 #define OOB_CMD_DRIVER_STOP     0x06
1125
1126 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1127 {
1128         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1129 }
1130
1131 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1132 {
1133         u16 reg;
1134
1135         reg = rtl8168_get_ocp_reg(tp);
1136
1137         return r8168dp_ocp_read(tp, reg) & 0x00000800;
1138 }
1139
1140 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1141 {
1142         return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1143 }
1144
1145 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1146 {
1147         return RTL_R8(tp, IBISR0) & 0x20;
1148 }
1149
1150 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1151 {
1152         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1153         rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1154         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1155         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1156 }
1157
1158 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1159 {
1160         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1161         rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1162 }
1163
1164 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1165 {
1166         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1167         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1168         rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1169 }
1170
1171 static void rtl8168_driver_start(struct rtl8169_private *tp)
1172 {
1173         switch (tp->mac_version) {
1174         case RTL_GIGA_MAC_VER_27:
1175         case RTL_GIGA_MAC_VER_28:
1176         case RTL_GIGA_MAC_VER_31:
1177                 rtl8168dp_driver_start(tp);
1178                 break;
1179         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1180                 rtl8168ep_driver_start(tp);
1181                 break;
1182         default:
1183                 BUG();
1184                 break;
1185         }
1186 }
1187
1188 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1189 {
1190         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1191         rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1192 }
1193
1194 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1195 {
1196         rtl8168ep_stop_cmac(tp);
1197         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1198         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1199         rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1200 }
1201
1202 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1203 {
1204         switch (tp->mac_version) {
1205         case RTL_GIGA_MAC_VER_27:
1206         case RTL_GIGA_MAC_VER_28:
1207         case RTL_GIGA_MAC_VER_31:
1208                 rtl8168dp_driver_stop(tp);
1209                 break;
1210         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1211                 rtl8168ep_driver_stop(tp);
1212                 break;
1213         default:
1214                 BUG();
1215                 break;
1216         }
1217 }
1218
1219 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1220 {
1221         u16 reg = rtl8168_get_ocp_reg(tp);
1222
1223         return !!(r8168dp_ocp_read(tp, reg) & 0x00008000);
1224 }
1225
1226 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1227 {
1228         return r8168ep_ocp_read(tp, 0x128) & 0x00000001;
1229 }
1230
1231 static bool r8168_check_dash(struct rtl8169_private *tp)
1232 {
1233         switch (tp->mac_version) {
1234         case RTL_GIGA_MAC_VER_27:
1235         case RTL_GIGA_MAC_VER_28:
1236         case RTL_GIGA_MAC_VER_31:
1237                 return r8168dp_check_dash(tp);
1238         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1239                 return r8168ep_check_dash(tp);
1240         default:
1241                 return false;
1242         }
1243 }
1244
1245 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1246 {
1247         rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1248         rtl_eri_set_bits(tp, 0xdc, BIT(0));
1249 }
1250
1251 DECLARE_RTL_COND(rtl_efusear_cond)
1252 {
1253         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1254 }
1255
1256 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1257 {
1258         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1259
1260         return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1261                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1262 }
1263
1264 static u32 rtl_get_events(struct rtl8169_private *tp)
1265 {
1266         if (rtl_is_8125(tp))
1267                 return RTL_R32(tp, IntrStatus_8125);
1268         else
1269                 return RTL_R16(tp, IntrStatus);
1270 }
1271
1272 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1273 {
1274         if (rtl_is_8125(tp))
1275                 RTL_W32(tp, IntrStatus_8125, bits);
1276         else
1277                 RTL_W16(tp, IntrStatus, bits);
1278 }
1279
1280 static void rtl_irq_disable(struct rtl8169_private *tp)
1281 {
1282         if (rtl_is_8125(tp))
1283                 RTL_W32(tp, IntrMask_8125, 0);
1284         else
1285                 RTL_W16(tp, IntrMask, 0);
1286 }
1287
1288 static void rtl_irq_enable(struct rtl8169_private *tp)
1289 {
1290         if (rtl_is_8125(tp))
1291                 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1292         else
1293                 RTL_W16(tp, IntrMask, tp->irq_mask);
1294 }
1295
1296 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1297 {
1298         rtl_irq_disable(tp);
1299         rtl_ack_events(tp, 0xffffffff);
1300         rtl_pci_commit(tp);
1301 }
1302
1303 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1304 {
1305         struct phy_device *phydev = tp->phydev;
1306
1307         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1308             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1309                 if (phydev->speed == SPEED_1000) {
1310                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1311                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1312                 } else if (phydev->speed == SPEED_100) {
1313                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1314                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1315                 } else {
1316                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1317                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1318                 }
1319                 rtl_reset_packet_filter(tp);
1320         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1321                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1322                 if (phydev->speed == SPEED_1000) {
1323                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1324                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1325                 } else {
1326                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1327                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1328                 }
1329         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1330                 if (phydev->speed == SPEED_10) {
1331                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1332                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1333                 } else {
1334                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1335                 }
1336         }
1337 }
1338
1339 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1340
1341 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1342 {
1343         struct rtl8169_private *tp = netdev_priv(dev);
1344
1345         wol->supported = WAKE_ANY;
1346         wol->wolopts = tp->saved_wolopts;
1347 }
1348
1349 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1350 {
1351         static const struct {
1352                 u32 opt;
1353                 u16 reg;
1354                 u8  mask;
1355         } cfg[] = {
1356                 { WAKE_PHY,   Config3, LinkUp },
1357                 { WAKE_UCAST, Config5, UWF },
1358                 { WAKE_BCAST, Config5, BWF },
1359                 { WAKE_MCAST, Config5, MWF },
1360                 { WAKE_ANY,   Config5, LanWake },
1361                 { WAKE_MAGIC, Config3, MagicPacket }
1362         };
1363         unsigned int i, tmp = ARRAY_SIZE(cfg);
1364         u8 options;
1365
1366         rtl_unlock_config_regs(tp);
1367
1368         if (rtl_is_8168evl_up(tp)) {
1369                 tmp--;
1370                 if (wolopts & WAKE_MAGIC)
1371                         rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1372                 else
1373                         rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1374         } else if (rtl_is_8125(tp)) {
1375                 tmp--;
1376                 if (wolopts & WAKE_MAGIC)
1377                         r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1378                 else
1379                         r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1380         }
1381
1382         for (i = 0; i < tmp; i++) {
1383                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1384                 if (wolopts & cfg[i].opt)
1385                         options |= cfg[i].mask;
1386                 RTL_W8(tp, cfg[i].reg, options);
1387         }
1388
1389         switch (tp->mac_version) {
1390         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1391                 options = RTL_R8(tp, Config1) & ~PMEnable;
1392                 if (wolopts)
1393                         options |= PMEnable;
1394                 RTL_W8(tp, Config1, options);
1395                 break;
1396         case RTL_GIGA_MAC_VER_34:
1397         case RTL_GIGA_MAC_VER_37:
1398         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1399                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1400                 if (wolopts)
1401                         options |= PME_SIGNAL;
1402                 RTL_W8(tp, Config2, options);
1403                 break;
1404         default:
1405                 break;
1406         }
1407
1408         rtl_lock_config_regs(tp);
1409
1410         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1411         tp->dev->wol_enabled = wolopts ? 1 : 0;
1412 }
1413
1414 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1415 {
1416         struct rtl8169_private *tp = netdev_priv(dev);
1417
1418         if (wol->wolopts & ~WAKE_ANY)
1419                 return -EINVAL;
1420
1421         tp->saved_wolopts = wol->wolopts;
1422         __rtl8169_set_wol(tp, tp->saved_wolopts);
1423
1424         return 0;
1425 }
1426
1427 static void rtl8169_get_drvinfo(struct net_device *dev,
1428                                 struct ethtool_drvinfo *info)
1429 {
1430         struct rtl8169_private *tp = netdev_priv(dev);
1431         struct rtl_fw *rtl_fw = tp->rtl_fw;
1432
1433         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1434         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1435         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1436         if (rtl_fw)
1437                 strlcpy(info->fw_version, rtl_fw->version,
1438                         sizeof(info->fw_version));
1439 }
1440
1441 static int rtl8169_get_regs_len(struct net_device *dev)
1442 {
1443         return R8169_REGS_SIZE;
1444 }
1445
1446 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1447         netdev_features_t features)
1448 {
1449         struct rtl8169_private *tp = netdev_priv(dev);
1450
1451         if (dev->mtu > TD_MSS_MAX)
1452                 features &= ~NETIF_F_ALL_TSO;
1453
1454         if (dev->mtu > ETH_DATA_LEN &&
1455             tp->mac_version > RTL_GIGA_MAC_VER_06)
1456                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1457
1458         return features;
1459 }
1460
1461 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1462                                        netdev_features_t features)
1463 {
1464         u32 rx_config = RTL_R32(tp, RxConfig);
1465
1466         if (features & NETIF_F_RXALL)
1467                 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1468         else
1469                 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1470
1471         if (rtl_is_8125(tp)) {
1472                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1473                         rx_config |= RX_VLAN_8125;
1474                 else
1475                         rx_config &= ~RX_VLAN_8125;
1476         }
1477
1478         RTL_W32(tp, RxConfig, rx_config);
1479 }
1480
1481 static int rtl8169_set_features(struct net_device *dev,
1482                                 netdev_features_t features)
1483 {
1484         struct rtl8169_private *tp = netdev_priv(dev);
1485
1486         rtl_set_rx_config_features(tp, features);
1487
1488         if (features & NETIF_F_RXCSUM)
1489                 tp->cp_cmd |= RxChkSum;
1490         else
1491                 tp->cp_cmd &= ~RxChkSum;
1492
1493         if (!rtl_is_8125(tp)) {
1494                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1495                         tp->cp_cmd |= RxVlan;
1496                 else
1497                         tp->cp_cmd &= ~RxVlan;
1498         }
1499
1500         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1501         rtl_pci_commit(tp);
1502
1503         return 0;
1504 }
1505
1506 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1507 {
1508         return (skb_vlan_tag_present(skb)) ?
1509                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1510 }
1511
1512 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1513 {
1514         u32 opts2 = le32_to_cpu(desc->opts2);
1515
1516         if (opts2 & RxVlanTag)
1517                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1518 }
1519
1520 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1521                              void *p)
1522 {
1523         struct rtl8169_private *tp = netdev_priv(dev);
1524         u32 __iomem *data = tp->mmio_addr;
1525         u32 *dw = p;
1526         int i;
1527
1528         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1529                 memcpy_fromio(dw++, data++, 4);
1530 }
1531
1532 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1533         "tx_packets",
1534         "rx_packets",
1535         "tx_errors",
1536         "rx_errors",
1537         "rx_missed",
1538         "align_errors",
1539         "tx_single_collisions",
1540         "tx_multi_collisions",
1541         "unicast",
1542         "broadcast",
1543         "multicast",
1544         "tx_aborted",
1545         "tx_underrun",
1546 };
1547
1548 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1549 {
1550         switch (sset) {
1551         case ETH_SS_STATS:
1552                 return ARRAY_SIZE(rtl8169_gstrings);
1553         default:
1554                 return -EOPNOTSUPP;
1555         }
1556 }
1557
1558 DECLARE_RTL_COND(rtl_counters_cond)
1559 {
1560         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1561 }
1562
1563 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1564 {
1565         dma_addr_t paddr = tp->counters_phys_addr;
1566         u32 cmd;
1567
1568         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1569         rtl_pci_commit(tp);
1570         cmd = (u64)paddr & DMA_BIT_MASK(32);
1571         RTL_W32(tp, CounterAddrLow, cmd);
1572         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1573
1574         rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1575 }
1576
1577 static void rtl8169_reset_counters(struct rtl8169_private *tp)
1578 {
1579         /*
1580          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1581          * tally counters.
1582          */
1583         if (tp->mac_version >= RTL_GIGA_MAC_VER_19)
1584                 rtl8169_do_counters(tp, CounterReset);
1585 }
1586
1587 static void rtl8169_update_counters(struct rtl8169_private *tp)
1588 {
1589         u8 val = RTL_R8(tp, ChipCmd);
1590
1591         /*
1592          * Some chips are unable to dump tally counters when the receiver
1593          * is disabled. If 0xff chip may be in a PCI power-save state.
1594          */
1595         if (val & CmdRxEnb && val != 0xff)
1596                 rtl8169_do_counters(tp, CounterDump);
1597 }
1598
1599 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1600 {
1601         struct rtl8169_counters *counters = tp->counters;
1602
1603         /*
1604          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1605          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1606          * reset by a power cycle, while the counter values collected by the
1607          * driver are reset at every driver unload/load cycle.
1608          *
1609          * To make sure the HW values returned by @get_stats64 match the SW
1610          * values, we collect the initial values at first open(*) and use them
1611          * as offsets to normalize the values returned by @get_stats64.
1612          *
1613          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1614          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1615          * set at open time by rtl_hw_start.
1616          */
1617
1618         if (tp->tc_offset.inited)
1619                 return;
1620
1621         rtl8169_reset_counters(tp);
1622         rtl8169_update_counters(tp);
1623
1624         tp->tc_offset.tx_errors = counters->tx_errors;
1625         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1626         tp->tc_offset.tx_aborted = counters->tx_aborted;
1627         tp->tc_offset.rx_missed = counters->rx_missed;
1628         tp->tc_offset.inited = true;
1629 }
1630
1631 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1632                                       struct ethtool_stats *stats, u64 *data)
1633 {
1634         struct rtl8169_private *tp = netdev_priv(dev);
1635         struct rtl8169_counters *counters;
1636
1637         counters = tp->counters;
1638         rtl8169_update_counters(tp);
1639
1640         data[0] = le64_to_cpu(counters->tx_packets);
1641         data[1] = le64_to_cpu(counters->rx_packets);
1642         data[2] = le64_to_cpu(counters->tx_errors);
1643         data[3] = le32_to_cpu(counters->rx_errors);
1644         data[4] = le16_to_cpu(counters->rx_missed);
1645         data[5] = le16_to_cpu(counters->align_errors);
1646         data[6] = le32_to_cpu(counters->tx_one_collision);
1647         data[7] = le32_to_cpu(counters->tx_multi_collision);
1648         data[8] = le64_to_cpu(counters->rx_unicast);
1649         data[9] = le64_to_cpu(counters->rx_broadcast);
1650         data[10] = le32_to_cpu(counters->rx_multicast);
1651         data[11] = le16_to_cpu(counters->tx_aborted);
1652         data[12] = le16_to_cpu(counters->tx_underun);
1653 }
1654
1655 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1656 {
1657         switch(stringset) {
1658         case ETH_SS_STATS:
1659                 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1660                 break;
1661         }
1662 }
1663
1664 /*
1665  * Interrupt coalescing
1666  *
1667  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1668  * >     8169, 8168 and 810x line of chipsets
1669  *
1670  * 8169, 8168, and 8136(810x) serial chipsets support it.
1671  *
1672  * > 2 - the Tx timer unit at gigabit speed
1673  *
1674  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1675  * (0xe0) bit 1 and bit 0.
1676  *
1677  * For 8169
1678  * bit[1:0] \ speed        1000M           100M            10M
1679  * 0 0                     320ns           2.56us          40.96us
1680  * 0 1                     2.56us          20.48us         327.7us
1681  * 1 0                     5.12us          40.96us         655.4us
1682  * 1 1                     10.24us         81.92us         1.31ms
1683  *
1684  * For the other
1685  * bit[1:0] \ speed        1000M           100M            10M
1686  * 0 0                     5us             2.56us          40.96us
1687  * 0 1                     40us            20.48us         327.7us
1688  * 1 0                     80us            40.96us         655.4us
1689  * 1 1                     160us           81.92us         1.31ms
1690  */
1691
1692 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1693 struct rtl_coalesce_info {
1694         u32 speed;
1695         u32 scale_nsecs[4];
1696 };
1697
1698 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1699 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1700
1701 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1702         { SPEED_1000,   COALESCE_DELAY(320) },
1703         { SPEED_100,    COALESCE_DELAY(2560) },
1704         { SPEED_10,     COALESCE_DELAY(40960) },
1705         { 0 },
1706 };
1707
1708 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1709         { SPEED_1000,   COALESCE_DELAY(5000) },
1710         { SPEED_100,    COALESCE_DELAY(2560) },
1711         { SPEED_10,     COALESCE_DELAY(40960) },
1712         { 0 },
1713 };
1714 #undef COALESCE_DELAY
1715
1716 /* get rx/tx scale vector corresponding to current speed */
1717 static const struct rtl_coalesce_info *
1718 rtl_coalesce_info(struct rtl8169_private *tp)
1719 {
1720         const struct rtl_coalesce_info *ci;
1721
1722         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1723                 ci = rtl_coalesce_info_8169;
1724         else
1725                 ci = rtl_coalesce_info_8168_8136;
1726
1727         /* if speed is unknown assume highest one */
1728         if (tp->phydev->speed == SPEED_UNKNOWN)
1729                 return ci;
1730
1731         for (; ci->speed; ci++) {
1732                 if (tp->phydev->speed == ci->speed)
1733                         return ci;
1734         }
1735
1736         return ERR_PTR(-ELNRNG);
1737 }
1738
1739 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1740 {
1741         struct rtl8169_private *tp = netdev_priv(dev);
1742         const struct rtl_coalesce_info *ci;
1743         u32 scale, c_us, c_fr;
1744         u16 intrmit;
1745
1746         if (rtl_is_8125(tp))
1747                 return -EOPNOTSUPP;
1748
1749         memset(ec, 0, sizeof(*ec));
1750
1751         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1752         ci = rtl_coalesce_info(tp);
1753         if (IS_ERR(ci))
1754                 return PTR_ERR(ci);
1755
1756         scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1757
1758         intrmit = RTL_R16(tp, IntrMitigate);
1759
1760         c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1761         ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1762
1763         c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1764         /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1765         ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1766
1767         c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1768         ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1769
1770         c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1771         ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1772
1773         return 0;
1774 }
1775
1776 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1777 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1778                                      u16 *cp01)
1779 {
1780         const struct rtl_coalesce_info *ci;
1781         u16 i;
1782
1783         ci = rtl_coalesce_info(tp);
1784         if (IS_ERR(ci))
1785                 return PTR_ERR(ci);
1786
1787         for (i = 0; i < 4; i++) {
1788                 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1789                         *cp01 = i;
1790                         return ci->scale_nsecs[i];
1791                 }
1792         }
1793
1794         return -ERANGE;
1795 }
1796
1797 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1798 {
1799         struct rtl8169_private *tp = netdev_priv(dev);
1800         u32 tx_fr = ec->tx_max_coalesced_frames;
1801         u32 rx_fr = ec->rx_max_coalesced_frames;
1802         u32 coal_usec_max, units;
1803         u16 w = 0, cp01 = 0;
1804         int scale;
1805
1806         if (rtl_is_8125(tp))
1807                 return -EOPNOTSUPP;
1808
1809         if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1810                 return -ERANGE;
1811
1812         coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1813         scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1814         if (scale < 0)
1815                 return scale;
1816
1817         /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1818          * not only when usecs=0 because of e.g. the following scenario:
1819          *
1820          * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1821          * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1822          * - then user does `ethtool -C eth0 rx-usecs 100`
1823          *
1824          * Since ethtool sends to kernel whole ethtool_coalesce settings,
1825          * if we want to ignore rx_frames then it has to be set to 0.
1826          */
1827         if (rx_fr == 1)
1828                 rx_fr = 0;
1829         if (tx_fr == 1)
1830                 tx_fr = 0;
1831
1832         /* HW requires time limit to be set if frame limit is set */
1833         if ((tx_fr && !ec->tx_coalesce_usecs) ||
1834             (rx_fr && !ec->rx_coalesce_usecs))
1835                 return -EINVAL;
1836
1837         w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1838         w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1839
1840         units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1841         w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1842         units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1843         w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1844
1845         RTL_W16(tp, IntrMitigate, w);
1846
1847         /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1848         if (rtl_is_8168evl_up(tp)) {
1849                 if (!rx_fr && !tx_fr)
1850                         /* disable packet counter */
1851                         tp->cp_cmd |= PktCntrDisable;
1852                 else
1853                         tp->cp_cmd &= ~PktCntrDisable;
1854         }
1855
1856         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1857         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1858         rtl_pci_commit(tp);
1859
1860         return 0;
1861 }
1862
1863 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1864 {
1865         struct rtl8169_private *tp = netdev_priv(dev);
1866
1867         if (!rtl_supports_eee(tp))
1868                 return -EOPNOTSUPP;
1869
1870         return phy_ethtool_get_eee(tp->phydev, data);
1871 }
1872
1873 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1874 {
1875         struct rtl8169_private *tp = netdev_priv(dev);
1876         int ret;
1877
1878         if (!rtl_supports_eee(tp))
1879                 return -EOPNOTSUPP;
1880
1881         ret = phy_ethtool_set_eee(tp->phydev, data);
1882
1883         if (!ret)
1884                 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1885                                            MDIO_AN_EEE_ADV);
1886         return ret;
1887 }
1888
1889 static const struct ethtool_ops rtl8169_ethtool_ops = {
1890         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1891                                      ETHTOOL_COALESCE_MAX_FRAMES,
1892         .get_drvinfo            = rtl8169_get_drvinfo,
1893         .get_regs_len           = rtl8169_get_regs_len,
1894         .get_link               = ethtool_op_get_link,
1895         .get_coalesce           = rtl_get_coalesce,
1896         .set_coalesce           = rtl_set_coalesce,
1897         .get_regs               = rtl8169_get_regs,
1898         .get_wol                = rtl8169_get_wol,
1899         .set_wol                = rtl8169_set_wol,
1900         .get_strings            = rtl8169_get_strings,
1901         .get_sset_count         = rtl8169_get_sset_count,
1902         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1903         .get_ts_info            = ethtool_op_get_ts_info,
1904         .nway_reset             = phy_ethtool_nway_reset,
1905         .get_eee                = rtl8169_get_eee,
1906         .set_eee                = rtl8169_set_eee,
1907         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
1908         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
1909 };
1910
1911 static void rtl_enable_eee(struct rtl8169_private *tp)
1912 {
1913         struct phy_device *phydev = tp->phydev;
1914         int adv;
1915
1916         /* respect EEE advertisement the user may have set */
1917         if (tp->eee_adv >= 0)
1918                 adv = tp->eee_adv;
1919         else
1920                 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1921
1922         if (adv >= 0)
1923                 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
1924 }
1925
1926 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
1927 {
1928         /*
1929          * The driver currently handles the 8168Bf and the 8168Be identically
1930          * but they can be identified more specifically through the test below
1931          * if needed:
1932          *
1933          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1934          *
1935          * Same thing for the 8101Eb and the 8101Ec:
1936          *
1937          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1938          */
1939         static const struct rtl_mac_info {
1940                 u16 mask;
1941                 u16 val;
1942                 enum mac_version ver;
1943         } mac_info[] = {
1944                 /* 8125B family. */
1945                 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
1946
1947                 /* 8125A family. */
1948                 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
1949                 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
1950
1951                 /* RTL8117 */
1952                 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
1953
1954                 /* 8168EP family. */
1955                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
1956                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
1957                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
1958
1959                 /* 8168H family. */
1960                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
1961                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
1962
1963                 /* 8168G family. */
1964                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
1965                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
1966                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
1967                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
1968
1969                 /* 8168F family. */
1970                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
1971                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
1972                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
1973
1974                 /* 8168E family. */
1975                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
1976                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
1977                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
1978
1979                 /* 8168D family. */
1980                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
1981                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
1982
1983                 /* 8168DP family. */
1984                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
1985                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
1986                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
1987
1988                 /* 8168C family. */
1989                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
1990                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
1991                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
1992                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
1993                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
1994                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
1995                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
1996
1997                 /* 8168B family. */
1998                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
1999                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2000                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2001
2002                 /* 8101 family. */
2003                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2004                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2005                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2006                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2007                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2008                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2009                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2010                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2011                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2012                 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2013                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2014                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2015                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2016                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2017                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2018                 /* FIXME: where did these entries come from ? -- FR */
2019                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 },
2020                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 },
2021
2022                 /* 8110 family. */
2023                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2024                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2025                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2026                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2027                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2028
2029                 /* Catch-all */
2030                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2031         };
2032         const struct rtl_mac_info *p = mac_info;
2033         enum mac_version ver;
2034
2035         while ((xid & p->mask) != p->val)
2036                 p++;
2037         ver = p->ver;
2038
2039         if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2040                 if (ver == RTL_GIGA_MAC_VER_42)
2041                         ver = RTL_GIGA_MAC_VER_43;
2042                 else if (ver == RTL_GIGA_MAC_VER_45)
2043                         ver = RTL_GIGA_MAC_VER_47;
2044                 else if (ver == RTL_GIGA_MAC_VER_46)
2045                         ver = RTL_GIGA_MAC_VER_48;
2046         }
2047
2048         return ver;
2049 }
2050
2051 static void rtl_release_firmware(struct rtl8169_private *tp)
2052 {
2053         if (tp->rtl_fw) {
2054                 rtl_fw_release_firmware(tp->rtl_fw);
2055                 kfree(tp->rtl_fw);
2056                 tp->rtl_fw = NULL;
2057         }
2058 }
2059
2060 void r8169_apply_firmware(struct rtl8169_private *tp)
2061 {
2062         int val;
2063
2064         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2065         if (tp->rtl_fw) {
2066                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2067                 /* At least one firmware doesn't reset tp->ocp_base. */
2068                 tp->ocp_base = OCP_STD_PHY_BASE;
2069
2070                 /* PHY soft reset may still be in progress */
2071                 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2072                                       !(val & BMCR_RESET),
2073                                       50000, 600000, true);
2074         }
2075 }
2076
2077 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2078 {
2079         /* Adjust EEE LED frequency */
2080         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2081                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2082
2083         rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2084 }
2085
2086 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2087 {
2088         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2089         r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2090 }
2091
2092 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2093 {
2094         RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2095 }
2096
2097 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2098 {
2099         rtl8125_set_eee_txidle_timer(tp);
2100         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2101 }
2102
2103 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2104 {
2105         const u16 w[] = {
2106                 addr[0] | (addr[1] << 8),
2107                 addr[2] | (addr[3] << 8),
2108                 addr[4] | (addr[5] << 8)
2109         };
2110
2111         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2112         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2113         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2114         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2115 }
2116
2117 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2118 {
2119         u16 data1, data2, ioffset;
2120
2121         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2122         data1 = r8168_mac_ocp_read(tp, 0xdd02);
2123         data2 = r8168_mac_ocp_read(tp, 0xdd00);
2124
2125         ioffset = (data2 >> 1) & 0x7ff8;
2126         ioffset |= data2 & 0x0007;
2127         if (data1 & BIT(7))
2128                 ioffset |= BIT(15);
2129
2130         return ioffset;
2131 }
2132
2133 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2134 {
2135         set_bit(flag, tp->wk.flags);
2136         schedule_work(&tp->wk.work);
2137 }
2138
2139 static void rtl8169_init_phy(struct rtl8169_private *tp)
2140 {
2141         r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2142
2143         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2144                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2145                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2146                 /* set undocumented MAC Reg C+CR Offset 0x82h */
2147                 RTL_W8(tp, 0x82, 0x01);
2148         }
2149
2150         if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2151             tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2152             tp->pci_dev->subsystem_device == 0xe000)
2153                 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2154
2155         /* We may have called phy_speed_down before */
2156         phy_speed_up(tp->phydev);
2157
2158         if (rtl_supports_eee(tp))
2159                 rtl_enable_eee(tp);
2160
2161         genphy_soft_reset(tp->phydev);
2162 }
2163
2164 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2165 {
2166         rtl_unlock_config_regs(tp);
2167
2168         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
2169         rtl_pci_commit(tp);
2170
2171         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
2172         rtl_pci_commit(tp);
2173
2174         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2175                 rtl_rar_exgmac_set(tp, addr);
2176
2177         rtl_lock_config_regs(tp);
2178 }
2179
2180 static int rtl_set_mac_address(struct net_device *dev, void *p)
2181 {
2182         struct rtl8169_private *tp = netdev_priv(dev);
2183         int ret;
2184
2185         ret = eth_mac_addr(dev, p);
2186         if (ret)
2187                 return ret;
2188
2189         rtl_rar_set(tp, dev->dev_addr);
2190
2191         return 0;
2192 }
2193
2194 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
2195 {
2196         switch (tp->mac_version) {
2197         case RTL_GIGA_MAC_VER_25:
2198         case RTL_GIGA_MAC_VER_26:
2199         case RTL_GIGA_MAC_VER_29:
2200         case RTL_GIGA_MAC_VER_30:
2201         case RTL_GIGA_MAC_VER_32:
2202         case RTL_GIGA_MAC_VER_33:
2203         case RTL_GIGA_MAC_VER_34:
2204         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_63:
2205                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2206                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2207                 break;
2208         default:
2209                 break;
2210         }
2211 }
2212
2213 static void rtl_pll_power_down(struct rtl8169_private *tp)
2214 {
2215         if (r8168_check_dash(tp))
2216                 return;
2217
2218         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2219             tp->mac_version == RTL_GIGA_MAC_VER_33)
2220                 rtl_ephy_write(tp, 0x19, 0xff64);
2221
2222         if (device_may_wakeup(tp_to_dev(tp))) {
2223                 phy_speed_down(tp->phydev, false);
2224                 rtl_wol_suspend_quirk(tp);
2225                 return;
2226         }
2227
2228         switch (tp->mac_version) {
2229         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
2230         case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
2231         case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_33:
2232         case RTL_GIGA_MAC_VER_37:
2233         case RTL_GIGA_MAC_VER_39:
2234         case RTL_GIGA_MAC_VER_43:
2235         case RTL_GIGA_MAC_VER_44:
2236         case RTL_GIGA_MAC_VER_45:
2237         case RTL_GIGA_MAC_VER_46:
2238         case RTL_GIGA_MAC_VER_47:
2239         case RTL_GIGA_MAC_VER_48:
2240         case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63:
2241                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2242                 break;
2243         case RTL_GIGA_MAC_VER_40:
2244         case RTL_GIGA_MAC_VER_41:
2245         case RTL_GIGA_MAC_VER_49:
2246                 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
2247                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2248                 break;
2249         default:
2250                 break;
2251         }
2252 }
2253
2254 static void rtl_pll_power_up(struct rtl8169_private *tp)
2255 {
2256         switch (tp->mac_version) {
2257         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
2258         case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
2259         case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_33:
2260         case RTL_GIGA_MAC_VER_37:
2261         case RTL_GIGA_MAC_VER_39:
2262         case RTL_GIGA_MAC_VER_43:
2263                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
2264                 break;
2265         case RTL_GIGA_MAC_VER_44:
2266         case RTL_GIGA_MAC_VER_45:
2267         case RTL_GIGA_MAC_VER_46:
2268         case RTL_GIGA_MAC_VER_47:
2269         case RTL_GIGA_MAC_VER_48:
2270         case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63:
2271                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2272                 break;
2273         case RTL_GIGA_MAC_VER_40:
2274         case RTL_GIGA_MAC_VER_41:
2275         case RTL_GIGA_MAC_VER_49:
2276                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2277                 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
2278                 break;
2279         default:
2280                 break;
2281         }
2282
2283         phy_resume(tp->phydev);
2284 }
2285
2286 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2287 {
2288         switch (tp->mac_version) {
2289         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2290         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2291                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2292                 break;
2293         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2294         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2295         case RTL_GIGA_MAC_VER_38:
2296                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2297                 break;
2298         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2299                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2300                 break;
2301         case RTL_GIGA_MAC_VER_61:
2302                 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2303                 break;
2304         case RTL_GIGA_MAC_VER_63:
2305                 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
2306                         RX_PAUSE_SLOT_ON);
2307                 break;
2308         default:
2309                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2310                 break;
2311         }
2312 }
2313
2314 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2315 {
2316         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2317 }
2318
2319 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2320 {
2321         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2322         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2323 }
2324
2325 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2326 {
2327         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2328         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2329 }
2330
2331 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2332 {
2333         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2334 }
2335
2336 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2337 {
2338         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2339 }
2340
2341 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2342 {
2343         RTL_W8(tp, MaxTxPacketSize, 0x24);
2344         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2345         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2346 }
2347
2348 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2349 {
2350         RTL_W8(tp, MaxTxPacketSize, 0x3f);
2351         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2352         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2353 }
2354
2355 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2356 {
2357         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2358 }
2359
2360 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2361 {
2362         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2363 }
2364
2365 static void rtl_jumbo_config(struct rtl8169_private *tp)
2366 {
2367         bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2368         int readrq = 4096;
2369
2370         rtl_unlock_config_regs(tp);
2371         switch (tp->mac_version) {
2372         case RTL_GIGA_MAC_VER_12:
2373         case RTL_GIGA_MAC_VER_17:
2374                 if (jumbo) {
2375                         readrq = 512;
2376                         r8168b_1_hw_jumbo_enable(tp);
2377                 } else {
2378                         r8168b_1_hw_jumbo_disable(tp);
2379                 }
2380                 break;
2381         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2382                 if (jumbo) {
2383                         readrq = 512;
2384                         r8168c_hw_jumbo_enable(tp);
2385                 } else {
2386                         r8168c_hw_jumbo_disable(tp);
2387                 }
2388                 break;
2389         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
2390                 if (jumbo)
2391                         r8168dp_hw_jumbo_enable(tp);
2392                 else
2393                         r8168dp_hw_jumbo_disable(tp);
2394                 break;
2395         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2396                 if (jumbo) {
2397                         pcie_set_readrq(tp->pci_dev, 512);
2398                         r8168e_hw_jumbo_enable(tp);
2399                 } else {
2400                         r8168e_hw_jumbo_disable(tp);
2401                 }
2402                 break;
2403         default:
2404                 break;
2405         }
2406         rtl_lock_config_regs(tp);
2407
2408         if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2409                 pcie_set_readrq(tp->pci_dev, readrq);
2410
2411         /* Chip doesn't support pause in jumbo mode */
2412         linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2413                          tp->phydev->advertising, !jumbo);
2414         linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2415                          tp->phydev->advertising, !jumbo);
2416         phy_start_aneg(tp->phydev);
2417 }
2418
2419 DECLARE_RTL_COND(rtl_chipcmd_cond)
2420 {
2421         return RTL_R8(tp, ChipCmd) & CmdReset;
2422 }
2423
2424 static void rtl_hw_reset(struct rtl8169_private *tp)
2425 {
2426         RTL_W8(tp, ChipCmd, CmdReset);
2427
2428         rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2429 }
2430
2431 static void rtl_request_firmware(struct rtl8169_private *tp)
2432 {
2433         struct rtl_fw *rtl_fw;
2434
2435         /* firmware loaded already or no firmware available */
2436         if (tp->rtl_fw || !tp->fw_name)
2437                 return;
2438
2439         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2440         if (!rtl_fw)
2441                 return;
2442
2443         rtl_fw->phy_write = rtl_writephy;
2444         rtl_fw->phy_read = rtl_readphy;
2445         rtl_fw->mac_mcu_write = mac_mcu_write;
2446         rtl_fw->mac_mcu_read = mac_mcu_read;
2447         rtl_fw->fw_name = tp->fw_name;
2448         rtl_fw->dev = tp_to_dev(tp);
2449
2450         if (rtl_fw_request_firmware(rtl_fw))
2451                 kfree(rtl_fw);
2452         else
2453                 tp->rtl_fw = rtl_fw;
2454 }
2455
2456 static void rtl_rx_close(struct rtl8169_private *tp)
2457 {
2458         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2459 }
2460
2461 DECLARE_RTL_COND(rtl_npq_cond)
2462 {
2463         return RTL_R8(tp, TxPoll) & NPQ;
2464 }
2465
2466 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2467 {
2468         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2469 }
2470
2471 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2472 {
2473         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2474 }
2475
2476 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2477 {
2478         /* IntrMitigate has new functionality on RTL8125 */
2479         return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2480 }
2481
2482 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2483 {
2484         switch (tp->mac_version) {
2485         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2486                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2487                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2488                 break;
2489         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
2490                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2491                 break;
2492         case RTL_GIGA_MAC_VER_63:
2493                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2494                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2495                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2496                 break;
2497         default:
2498                 break;
2499         }
2500 }
2501
2502 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2503 {
2504         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2505         fsleep(2000);
2506         rtl_wait_txrx_fifo_empty(tp);
2507 }
2508
2509 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2510 {
2511         u32 val = TX_DMA_BURST << TxDMAShift |
2512                   InterFrameGap << TxInterFrameGapShift;
2513
2514         if (rtl_is_8168evl_up(tp))
2515                 val |= TXCFG_AUTO_FIFO;
2516
2517         RTL_W32(tp, TxConfig, val);
2518 }
2519
2520 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2521 {
2522         /* Low hurts. Let's disable the filtering. */
2523         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2524 }
2525
2526 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2527 {
2528         /*
2529          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2530          * register to be written before TxDescAddrLow to work.
2531          * Switching from MMIO to I/O access fixes the issue as well.
2532          */
2533         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2534         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2535         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2536         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2537 }
2538
2539 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2540 {
2541         u32 val;
2542
2543         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2544                 val = 0x000fff00;
2545         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2546                 val = 0x00ffff00;
2547         else
2548                 return;
2549
2550         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2551                 val |= 0xff;
2552
2553         RTL_W32(tp, 0x7c, val);
2554 }
2555
2556 static void rtl_set_rx_mode(struct net_device *dev)
2557 {
2558         u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2559         /* Multicast hash filter */
2560         u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2561         struct rtl8169_private *tp = netdev_priv(dev);
2562         u32 tmp;
2563
2564         if (dev->flags & IFF_PROMISC) {
2565                 rx_mode |= AcceptAllPhys;
2566         } else if (!(dev->flags & IFF_MULTICAST)) {
2567                 rx_mode &= ~AcceptMulticast;
2568         } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2569                    dev->flags & IFF_ALLMULTI ||
2570                    tp->mac_version == RTL_GIGA_MAC_VER_35) {
2571                 /* accept all multicasts */
2572         } else if (netdev_mc_empty(dev)) {
2573                 rx_mode &= ~AcceptMulticast;
2574         } else {
2575                 struct netdev_hw_addr *ha;
2576
2577                 mc_filter[1] = mc_filter[0] = 0;
2578                 netdev_for_each_mc_addr(ha, dev) {
2579                         u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2580                         mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2581                 }
2582
2583                 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2584                         tmp = mc_filter[0];
2585                         mc_filter[0] = swab32(mc_filter[1]);
2586                         mc_filter[1] = swab32(tmp);
2587                 }
2588         }
2589
2590         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2591         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2592
2593         tmp = RTL_R32(tp, RxConfig);
2594         RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2595 }
2596
2597 DECLARE_RTL_COND(rtl_csiar_cond)
2598 {
2599         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2600 }
2601
2602 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2603 {
2604         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2605
2606         RTL_W32(tp, CSIDR, value);
2607         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2608                 CSIAR_BYTE_ENABLE | func << 16);
2609
2610         rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2611 }
2612
2613 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2614 {
2615         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2616
2617         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2618                 CSIAR_BYTE_ENABLE);
2619
2620         return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2621                 RTL_R32(tp, CSIDR) : ~0;
2622 }
2623
2624 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
2625 {
2626         struct pci_dev *pdev = tp->pci_dev;
2627         u32 csi;
2628
2629         /* According to Realtek the value at config space address 0x070f
2630          * controls the L0s/L1 entrance latency. We try standard ECAM access
2631          * first and if it fails fall back to CSI.
2632          */
2633         if (pdev->cfg_size > 0x070f &&
2634             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2635                 return;
2636
2637         netdev_notice_once(tp->dev,
2638                 "No native access to PCI extended config space, falling back to CSI\n");
2639         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2640         rtl_csi_write(tp, 0x070c, csi | val << 24);
2641 }
2642
2643 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2644 {
2645         rtl_csi_access_enable(tp, 0x27);
2646 }
2647
2648 struct ephy_info {
2649         unsigned int offset;
2650         u16 mask;
2651         u16 bits;
2652 };
2653
2654 static void __rtl_ephy_init(struct rtl8169_private *tp,
2655                             const struct ephy_info *e, int len)
2656 {
2657         u16 w;
2658
2659         while (len-- > 0) {
2660                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2661                 rtl_ephy_write(tp, e->offset, w);
2662                 e++;
2663         }
2664 }
2665
2666 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2667
2668 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2669 {
2670         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2671                                    PCI_EXP_LNKCTL_CLKREQ_EN);
2672 }
2673
2674 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2675 {
2676         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2677                                  PCI_EXP_LNKCTL_CLKREQ_EN);
2678 }
2679
2680 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2681 {
2682         /* work around an issue when PCI reset occurs during L2/L3 state */
2683         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2684 }
2685
2686 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2687 {
2688         /* Don't enable ASPM in the chip if OS can't control ASPM */
2689         if (enable && tp->aspm_manageable) {
2690                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2691                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2692         } else {
2693                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2694                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2695         }
2696
2697         udelay(10);
2698 }
2699
2700 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2701                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2702 {
2703         /* Usage of dynamic vs. static FIFO is controlled by bit
2704          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2705          */
2706         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2707         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2708 }
2709
2710 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2711                                           u8 low, u8 high)
2712 {
2713         /* FIFO thresholds for pause flow control */
2714         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2715         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2716 }
2717
2718 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2719 {
2720         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2721 }
2722
2723 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2724 {
2725         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2726
2727         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2728
2729         rtl_disable_clock_request(tp);
2730 }
2731
2732 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2733 {
2734         static const struct ephy_info e_info_8168cp[] = {
2735                 { 0x01, 0,      0x0001 },
2736                 { 0x02, 0x0800, 0x1000 },
2737                 { 0x03, 0,      0x0042 },
2738                 { 0x06, 0x0080, 0x0000 },
2739                 { 0x07, 0,      0x2000 }
2740         };
2741
2742         rtl_set_def_aspm_entry_latency(tp);
2743
2744         rtl_ephy_init(tp, e_info_8168cp);
2745
2746         __rtl_hw_start_8168cp(tp);
2747 }
2748
2749 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2750 {
2751         rtl_set_def_aspm_entry_latency(tp);
2752
2753         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2754 }
2755
2756 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2757 {
2758         rtl_set_def_aspm_entry_latency(tp);
2759
2760         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2761
2762         /* Magic. */
2763         RTL_W8(tp, DBG_REG, 0x20);
2764 }
2765
2766 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2767 {
2768         static const struct ephy_info e_info_8168c_1[] = {
2769                 { 0x02, 0x0800, 0x1000 },
2770                 { 0x03, 0,      0x0002 },
2771                 { 0x06, 0x0080, 0x0000 }
2772         };
2773
2774         rtl_set_def_aspm_entry_latency(tp);
2775
2776         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2777
2778         rtl_ephy_init(tp, e_info_8168c_1);
2779
2780         __rtl_hw_start_8168cp(tp);
2781 }
2782
2783 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2784 {
2785         static const struct ephy_info e_info_8168c_2[] = {
2786                 { 0x01, 0,      0x0001 },
2787                 { 0x03, 0x0400, 0x0020 }
2788         };
2789
2790         rtl_set_def_aspm_entry_latency(tp);
2791
2792         rtl_ephy_init(tp, e_info_8168c_2);
2793
2794         __rtl_hw_start_8168cp(tp);
2795 }
2796
2797 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
2798 {
2799         rtl_hw_start_8168c_2(tp);
2800 }
2801
2802 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2803 {
2804         rtl_set_def_aspm_entry_latency(tp);
2805
2806         __rtl_hw_start_8168cp(tp);
2807 }
2808
2809 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2810 {
2811         rtl_set_def_aspm_entry_latency(tp);
2812
2813         rtl_disable_clock_request(tp);
2814 }
2815
2816 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2817 {
2818         static const struct ephy_info e_info_8168d_4[] = {
2819                 { 0x0b, 0x0000, 0x0048 },
2820                 { 0x19, 0x0020, 0x0050 },
2821                 { 0x0c, 0x0100, 0x0020 },
2822                 { 0x10, 0x0004, 0x0000 },
2823         };
2824
2825         rtl_set_def_aspm_entry_latency(tp);
2826
2827         rtl_ephy_init(tp, e_info_8168d_4);
2828
2829         rtl_enable_clock_request(tp);
2830 }
2831
2832 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2833 {
2834         static const struct ephy_info e_info_8168e_1[] = {
2835                 { 0x00, 0x0200, 0x0100 },
2836                 { 0x00, 0x0000, 0x0004 },
2837                 { 0x06, 0x0002, 0x0001 },
2838                 { 0x06, 0x0000, 0x0030 },
2839                 { 0x07, 0x0000, 0x2000 },
2840                 { 0x00, 0x0000, 0x0020 },
2841                 { 0x03, 0x5800, 0x2000 },
2842                 { 0x03, 0x0000, 0x0001 },
2843                 { 0x01, 0x0800, 0x1000 },
2844                 { 0x07, 0x0000, 0x4000 },
2845                 { 0x1e, 0x0000, 0x2000 },
2846                 { 0x19, 0xffff, 0xfe6c },
2847                 { 0x0a, 0x0000, 0x0040 }
2848         };
2849
2850         rtl_set_def_aspm_entry_latency(tp);
2851
2852         rtl_ephy_init(tp, e_info_8168e_1);
2853
2854         rtl_disable_clock_request(tp);
2855
2856         /* Reset tx FIFO pointer */
2857         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2858         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2859
2860         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2861 }
2862
2863 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2864 {
2865         static const struct ephy_info e_info_8168e_2[] = {
2866                 { 0x09, 0x0000, 0x0080 },
2867                 { 0x19, 0x0000, 0x0224 },
2868                 { 0x00, 0x0000, 0x0004 },
2869                 { 0x0c, 0x3df0, 0x0200 },
2870         };
2871
2872         rtl_set_def_aspm_entry_latency(tp);
2873
2874         rtl_ephy_init(tp, e_info_8168e_2);
2875
2876         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2877         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2878         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2879         rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2880         rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2881         rtl_reset_packet_filter(tp);
2882         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2883         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2884         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2885
2886         rtl_disable_clock_request(tp);
2887
2888         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2889
2890         rtl8168_config_eee_mac(tp);
2891
2892         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2893         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2894         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2895
2896         rtl_hw_aspm_clkreq_enable(tp, true);
2897 }
2898
2899 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2900 {
2901         rtl_set_def_aspm_entry_latency(tp);
2902
2903         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2904         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2905         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2906         rtl_reset_packet_filter(tp);
2907         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2908         rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2909         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2910         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2911
2912         rtl_disable_clock_request(tp);
2913
2914         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2915         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2916         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2917         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2918
2919         rtl8168_config_eee_mac(tp);
2920 }
2921
2922 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
2923 {
2924         static const struct ephy_info e_info_8168f_1[] = {
2925                 { 0x06, 0x00c0, 0x0020 },
2926                 { 0x08, 0x0001, 0x0002 },
2927                 { 0x09, 0x0000, 0x0080 },
2928                 { 0x19, 0x0000, 0x0224 },
2929                 { 0x00, 0x0000, 0x0008 },
2930                 { 0x0c, 0x3df0, 0x0200 },
2931         };
2932
2933         rtl_hw_start_8168f(tp);
2934
2935         rtl_ephy_init(tp, e_info_8168f_1);
2936
2937         rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2938 }
2939
2940 static void rtl_hw_start_8411(struct rtl8169_private *tp)
2941 {
2942         static const struct ephy_info e_info_8168f_1[] = {
2943                 { 0x06, 0x00c0, 0x0020 },
2944                 { 0x0f, 0xffff, 0x5200 },
2945                 { 0x19, 0x0000, 0x0224 },
2946                 { 0x00, 0x0000, 0x0008 },
2947                 { 0x0c, 0x3df0, 0x0200 },
2948         };
2949
2950         rtl_hw_start_8168f(tp);
2951         rtl_pcie_state_l2l3_disable(tp);
2952
2953         rtl_ephy_init(tp, e_info_8168f_1);
2954
2955         rtl_eri_set_bits(tp, 0x0d4, 0x0c00);
2956 }
2957
2958 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
2959 {
2960         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
2961         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
2962
2963         rtl_set_def_aspm_entry_latency(tp);
2964
2965         rtl_reset_packet_filter(tp);
2966         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
2967
2968         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2969
2970         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2971         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2972         rtl_eri_set_bits(tp, 0x0d4, 0x1f80);
2973
2974         rtl8168_config_eee_mac(tp);
2975
2976         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
2977         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
2978
2979         rtl_pcie_state_l2l3_disable(tp);
2980 }
2981
2982 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
2983 {
2984         static const struct ephy_info e_info_8168g_1[] = {
2985                 { 0x00, 0x0008, 0x0000 },
2986                 { 0x0c, 0x3ff0, 0x0820 },
2987                 { 0x1e, 0x0000, 0x0001 },
2988                 { 0x19, 0x8000, 0x0000 }
2989         };
2990
2991         rtl_hw_start_8168g(tp);
2992
2993         /* disable aspm and clock request before access ephy */
2994         rtl_hw_aspm_clkreq_enable(tp, false);
2995         rtl_ephy_init(tp, e_info_8168g_1);
2996         rtl_hw_aspm_clkreq_enable(tp, true);
2997 }
2998
2999 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3000 {
3001         static const struct ephy_info e_info_8168g_2[] = {
3002                 { 0x00, 0x0008, 0x0000 },
3003                 { 0x0c, 0x3ff0, 0x0820 },
3004                 { 0x19, 0xffff, 0x7c00 },
3005                 { 0x1e, 0xffff, 0x20eb },
3006                 { 0x0d, 0xffff, 0x1666 },
3007                 { 0x00, 0xffff, 0x10a3 },
3008                 { 0x06, 0xffff, 0xf050 },
3009                 { 0x04, 0x0000, 0x0010 },
3010                 { 0x1d, 0x4000, 0x0000 },
3011         };
3012
3013         rtl_hw_start_8168g(tp);
3014
3015         /* disable aspm and clock request before access ephy */
3016         rtl_hw_aspm_clkreq_enable(tp, false);
3017         rtl_ephy_init(tp, e_info_8168g_2);
3018 }
3019
3020 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3021 {
3022         static const struct ephy_info e_info_8411_2[] = {
3023                 { 0x00, 0x0008, 0x0000 },
3024                 { 0x0c, 0x37d0, 0x0820 },
3025                 { 0x1e, 0x0000, 0x0001 },
3026                 { 0x19, 0x8021, 0x0000 },
3027                 { 0x1e, 0x0000, 0x2000 },
3028                 { 0x0d, 0x0100, 0x0200 },
3029                 { 0x00, 0x0000, 0x0080 },
3030                 { 0x06, 0x0000, 0x0010 },
3031                 { 0x04, 0x0000, 0x0010 },
3032                 { 0x1d, 0x0000, 0x4000 },
3033         };
3034
3035         rtl_hw_start_8168g(tp);
3036
3037         /* disable aspm and clock request before access ephy */
3038         rtl_hw_aspm_clkreq_enable(tp, false);
3039         rtl_ephy_init(tp, e_info_8411_2);
3040
3041         /* The following Realtek-provided magic fixes an issue with the RX unit
3042          * getting confused after the PHY having been powered-down.
3043          */
3044         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3045         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3046         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3047         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3048         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3049         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3050         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3051         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3052         mdelay(3);
3053         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3054
3055         r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3056         r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3057         r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3058         r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3059         r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3060         r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3061         r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3062         r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3063         r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3064         r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3065         r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3066         r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3067         r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3068         r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3069         r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3070         r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3071         r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3072         r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3073         r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3074         r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3075         r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3076         r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3077         r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3078         r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3079         r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3080         r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3081         r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3082         r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3083         r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3084         r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3085         r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3086         r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3087         r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3088         r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3089         r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3090         r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3091         r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3092         r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3093         r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3094         r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3095         r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3096         r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3097         r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3098         r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3099         r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3100         r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3101         r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3102         r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3103         r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3104         r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3105         r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3106         r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3107         r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3108         r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3109         r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3110         r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3111         r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3112         r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3113         r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3114         r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3115         r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3116         r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3117         r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3118         r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3119         r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3120         r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3121         r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3122         r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3123         r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3124         r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3125         r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3126         r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3127         r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3128         r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3129         r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3130         r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3131         r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3132         r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3133         r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3134         r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3135         r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3136         r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3137         r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3138         r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3139         r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3140         r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3141         r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3142         r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3143         r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3144         r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3145         r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3146         r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3147         r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3148         r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3149         r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3150         r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3151         r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3152         r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3153         r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3154         r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3155         r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3156         r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3157         r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3158         r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3159         r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3160         r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3161         r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3162         r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3163         r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3164         r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3165         r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3166
3167         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3168
3169         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3170         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3171         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3172         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3173         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3174         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3175         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3176
3177         rtl_hw_aspm_clkreq_enable(tp, true);
3178 }
3179
3180 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3181 {
3182         static const struct ephy_info e_info_8168h_1[] = {
3183                 { 0x1e, 0x0800, 0x0001 },
3184                 { 0x1d, 0x0000, 0x0800 },
3185                 { 0x05, 0xffff, 0x2089 },
3186                 { 0x06, 0xffff, 0x5881 },
3187                 { 0x04, 0xffff, 0x854a },
3188                 { 0x01, 0xffff, 0x068b }
3189         };
3190         int rg_saw_cnt;
3191
3192         /* disable aspm and clock request before access ephy */
3193         rtl_hw_aspm_clkreq_enable(tp, false);
3194         rtl_ephy_init(tp, e_info_8168h_1);
3195
3196         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3197         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3198
3199         rtl_set_def_aspm_entry_latency(tp);
3200
3201         rtl_reset_packet_filter(tp);
3202
3203         rtl_eri_set_bits(tp, 0xd4, 0x1f00);
3204         rtl_eri_set_bits(tp, 0xdc, 0x001c);
3205
3206         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3207
3208         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3209
3210         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3211         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3212
3213         rtl8168_config_eee_mac(tp);
3214
3215         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3216         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3217
3218         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3219
3220         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3221
3222         rtl_pcie_state_l2l3_disable(tp);
3223
3224         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3225         if (rg_saw_cnt > 0) {
3226                 u16 sw_cnt_1ms_ini;
3227
3228                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3229                 sw_cnt_1ms_ini &= 0x0fff;
3230                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3231         }
3232
3233         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3234         r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3235         r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3236         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3237
3238         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3239         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3240         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3241         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3242
3243         rtl_hw_aspm_clkreq_enable(tp, true);
3244 }
3245
3246 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3247 {
3248         rtl8168ep_stop_cmac(tp);
3249
3250         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3251         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3252
3253         rtl_set_def_aspm_entry_latency(tp);
3254
3255         rtl_reset_packet_filter(tp);
3256
3257         rtl_eri_set_bits(tp, 0xd4, 0x1f80);
3258
3259         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3260
3261         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3262
3263         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3264         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3265
3266         rtl8168_config_eee_mac(tp);
3267
3268         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3269
3270         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3271
3272         rtl_pcie_state_l2l3_disable(tp);
3273 }
3274
3275 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
3276 {
3277         static const struct ephy_info e_info_8168ep_1[] = {
3278                 { 0x00, 0xffff, 0x10ab },
3279                 { 0x06, 0xffff, 0xf030 },
3280                 { 0x08, 0xffff, 0x2006 },
3281                 { 0x0d, 0xffff, 0x1666 },
3282                 { 0x0c, 0x3ff0, 0x0000 }
3283         };
3284
3285         /* disable aspm and clock request before access ephy */
3286         rtl_hw_aspm_clkreq_enable(tp, false);
3287         rtl_ephy_init(tp, e_info_8168ep_1);
3288
3289         rtl_hw_start_8168ep(tp);
3290
3291         rtl_hw_aspm_clkreq_enable(tp, true);
3292 }
3293
3294 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
3295 {
3296         static const struct ephy_info e_info_8168ep_2[] = {
3297                 { 0x00, 0xffff, 0x10a3 },
3298                 { 0x19, 0xffff, 0xfc00 },
3299                 { 0x1e, 0xffff, 0x20ea }
3300         };
3301
3302         /* disable aspm and clock request before access ephy */
3303         rtl_hw_aspm_clkreq_enable(tp, false);
3304         rtl_ephy_init(tp, e_info_8168ep_2);
3305
3306         rtl_hw_start_8168ep(tp);
3307
3308         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3309         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3310
3311         rtl_hw_aspm_clkreq_enable(tp, true);
3312 }
3313
3314 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3315 {
3316         static const struct ephy_info e_info_8168ep_3[] = {
3317                 { 0x00, 0x0000, 0x0080 },
3318                 { 0x0d, 0x0100, 0x0200 },
3319                 { 0x19, 0x8021, 0x0000 },
3320                 { 0x1e, 0x0000, 0x2000 },
3321         };
3322
3323         /* disable aspm and clock request before access ephy */
3324         rtl_hw_aspm_clkreq_enable(tp, false);
3325         rtl_ephy_init(tp, e_info_8168ep_3);
3326
3327         rtl_hw_start_8168ep(tp);
3328
3329         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3330         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3331
3332         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3333         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3334         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3335
3336         rtl_hw_aspm_clkreq_enable(tp, true);
3337 }
3338
3339 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3340 {
3341         static const struct ephy_info e_info_8117[] = {
3342                 { 0x19, 0x0040, 0x1100 },
3343                 { 0x59, 0x0040, 0x1100 },
3344         };
3345         int rg_saw_cnt;
3346
3347         rtl8168ep_stop_cmac(tp);
3348
3349         /* disable aspm and clock request before access ephy */
3350         rtl_hw_aspm_clkreq_enable(tp, false);
3351         rtl_ephy_init(tp, e_info_8117);
3352
3353         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3354         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3355
3356         rtl_set_def_aspm_entry_latency(tp);
3357
3358         rtl_reset_packet_filter(tp);
3359
3360         rtl_eri_set_bits(tp, 0xd4, 0x1f90);
3361
3362         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3363
3364         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3365
3366         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3367         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3368
3369         rtl8168_config_eee_mac(tp);
3370
3371         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3372         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3373
3374         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3375
3376         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3377
3378         rtl_pcie_state_l2l3_disable(tp);
3379
3380         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3381         if (rg_saw_cnt > 0) {
3382                 u16 sw_cnt_1ms_ini;
3383
3384                 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3385                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3386         }
3387
3388         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3389         r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3390         r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3391         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3392
3393         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3394         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3395         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3396         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3397
3398         /* firmware is for MAC only */
3399         r8169_apply_firmware(tp);
3400
3401         rtl_hw_aspm_clkreq_enable(tp, true);
3402 }
3403
3404 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3405 {
3406         static const struct ephy_info e_info_8102e_1[] = {
3407                 { 0x01, 0, 0x6e65 },
3408                 { 0x02, 0, 0x091f },
3409                 { 0x03, 0, 0xc2f9 },
3410                 { 0x06, 0, 0xafb5 },
3411                 { 0x07, 0, 0x0e00 },
3412                 { 0x19, 0, 0xec80 },
3413                 { 0x01, 0, 0x2e65 },
3414                 { 0x01, 0, 0x6e65 }
3415         };
3416         u8 cfg1;
3417
3418         rtl_set_def_aspm_entry_latency(tp);
3419
3420         RTL_W8(tp, DBG_REG, FIX_NAK_1);
3421
3422         RTL_W8(tp, Config1,
3423                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3424         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3425
3426         cfg1 = RTL_R8(tp, Config1);
3427         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3428                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3429
3430         rtl_ephy_init(tp, e_info_8102e_1);
3431 }
3432
3433 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3434 {
3435         rtl_set_def_aspm_entry_latency(tp);
3436
3437         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3438         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3439 }
3440
3441 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3442 {
3443         rtl_hw_start_8102e_2(tp);
3444
3445         rtl_ephy_write(tp, 0x03, 0xc2f9);
3446 }
3447
3448 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3449 {
3450         static const struct ephy_info e_info_8401[] = {
3451                 { 0x01, 0xffff, 0x6fe5 },
3452                 { 0x03, 0xffff, 0x0599 },
3453                 { 0x06, 0xffff, 0xaf25 },
3454                 { 0x07, 0xffff, 0x8e68 },
3455         };
3456
3457         rtl_ephy_init(tp, e_info_8401);
3458         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3459 }
3460
3461 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3462 {
3463         static const struct ephy_info e_info_8105e_1[] = {
3464                 { 0x07, 0, 0x4000 },
3465                 { 0x19, 0, 0x0200 },
3466                 { 0x19, 0, 0x0020 },
3467                 { 0x1e, 0, 0x2000 },
3468                 { 0x03, 0, 0x0001 },
3469                 { 0x19, 0, 0x0100 },
3470                 { 0x19, 0, 0x0004 },
3471                 { 0x0a, 0, 0x0020 }
3472         };
3473
3474         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3475         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3476
3477         /* Disable Early Tally Counter */
3478         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3479
3480         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3481         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3482
3483         rtl_ephy_init(tp, e_info_8105e_1);
3484
3485         rtl_pcie_state_l2l3_disable(tp);
3486 }
3487
3488 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3489 {
3490         rtl_hw_start_8105e_1(tp);
3491         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3492 }
3493
3494 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3495 {
3496         static const struct ephy_info e_info_8402[] = {
3497                 { 0x19, 0xffff, 0xff64 },
3498                 { 0x1e, 0, 0x4000 }
3499         };
3500
3501         rtl_set_def_aspm_entry_latency(tp);
3502
3503         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3504         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3505
3506         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3507
3508         rtl_ephy_init(tp, e_info_8402);
3509
3510         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3511         rtl_reset_packet_filter(tp);
3512         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3513         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3514         rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3515
3516         /* disable EEE */
3517         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3518
3519         rtl_pcie_state_l2l3_disable(tp);
3520 }
3521
3522 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3523 {
3524         rtl_hw_aspm_clkreq_enable(tp, false);
3525
3526         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3527         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3528
3529         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3530         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3531         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3532
3533         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3534
3535         /* disable EEE */
3536         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3537
3538         rtl_pcie_state_l2l3_disable(tp);
3539         rtl_hw_aspm_clkreq_enable(tp, true);
3540 }
3541
3542 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3543 {
3544         return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3545 }
3546
3547 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3548 {
3549         rtl_pcie_state_l2l3_disable(tp);
3550
3551         RTL_W16(tp, 0x382, 0x221b);
3552         RTL_W8(tp, 0x4500, 0);
3553         RTL_W16(tp, 0x4800, 0);
3554
3555         /* disable UPS */
3556         r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3557
3558         RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3559
3560         r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3561         r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3562
3563         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3564         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3565         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3566
3567         /* disable new tx descriptor format */
3568         r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3569
3570         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3571                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3572         else
3573                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3574
3575         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3576                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3577         else
3578                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3579
3580         r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3581         r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3582         r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3583         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3584         r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3585         r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3586         r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3587         r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3588         r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
3589         r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3590
3591         r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3592         r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3593         udelay(1);
3594         r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3595         RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3596
3597         r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3598
3599         rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3600
3601         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3602                 rtl8125b_config_eee_mac(tp);
3603         else
3604                 rtl8125a_config_eee_mac(tp);
3605
3606         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3607         udelay(10);
3608 }
3609
3610 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp)
3611 {
3612         static const struct ephy_info e_info_8125a_1[] = {
3613                 { 0x01, 0xffff, 0xa812 },
3614                 { 0x09, 0xffff, 0x520c },
3615                 { 0x04, 0xffff, 0xd000 },
3616                 { 0x0d, 0xffff, 0xf702 },
3617                 { 0x0a, 0xffff, 0x8653 },
3618                 { 0x06, 0xffff, 0x001e },
3619                 { 0x08, 0xffff, 0x3595 },
3620                 { 0x20, 0xffff, 0x9455 },
3621                 { 0x21, 0xffff, 0x99ff },
3622                 { 0x02, 0xffff, 0x6046 },
3623                 { 0x29, 0xffff, 0xfe00 },
3624                 { 0x23, 0xffff, 0xab62 },
3625
3626                 { 0x41, 0xffff, 0xa80c },
3627                 { 0x49, 0xffff, 0x520c },
3628                 { 0x44, 0xffff, 0xd000 },
3629                 { 0x4d, 0xffff, 0xf702 },
3630                 { 0x4a, 0xffff, 0x8653 },
3631                 { 0x46, 0xffff, 0x001e },
3632                 { 0x48, 0xffff, 0x3595 },
3633                 { 0x60, 0xffff, 0x9455 },
3634                 { 0x61, 0xffff, 0x99ff },
3635                 { 0x42, 0xffff, 0x6046 },
3636                 { 0x69, 0xffff, 0xfe00 },
3637                 { 0x63, 0xffff, 0xab62 },
3638         };
3639
3640         rtl_set_def_aspm_entry_latency(tp);
3641
3642         /* disable aspm and clock request before access ephy */
3643         rtl_hw_aspm_clkreq_enable(tp, false);
3644         rtl_ephy_init(tp, e_info_8125a_1);
3645
3646         rtl_hw_start_8125_common(tp);
3647         rtl_hw_aspm_clkreq_enable(tp, true);
3648 }
3649
3650 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3651 {
3652         static const struct ephy_info e_info_8125a_2[] = {
3653                 { 0x04, 0xffff, 0xd000 },
3654                 { 0x0a, 0xffff, 0x8653 },
3655                 { 0x23, 0xffff, 0xab66 },
3656                 { 0x20, 0xffff, 0x9455 },
3657                 { 0x21, 0xffff, 0x99ff },
3658                 { 0x29, 0xffff, 0xfe04 },
3659
3660                 { 0x44, 0xffff, 0xd000 },
3661                 { 0x4a, 0xffff, 0x8653 },
3662                 { 0x63, 0xffff, 0xab66 },
3663                 { 0x60, 0xffff, 0x9455 },
3664                 { 0x61, 0xffff, 0x99ff },
3665                 { 0x69, 0xffff, 0xfe04 },
3666         };
3667
3668         rtl_set_def_aspm_entry_latency(tp);
3669
3670         /* disable aspm and clock request before access ephy */
3671         rtl_hw_aspm_clkreq_enable(tp, false);
3672         rtl_ephy_init(tp, e_info_8125a_2);
3673
3674         rtl_hw_start_8125_common(tp);
3675         rtl_hw_aspm_clkreq_enable(tp, true);
3676 }
3677
3678 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3679 {
3680         static const struct ephy_info e_info_8125b[] = {
3681                 { 0x0b, 0xffff, 0xa908 },
3682                 { 0x1e, 0xffff, 0x20eb },
3683                 { 0x4b, 0xffff, 0xa908 },
3684                 { 0x5e, 0xffff, 0x20eb },
3685                 { 0x22, 0x0030, 0x0020 },
3686                 { 0x62, 0x0030, 0x0020 },
3687         };
3688
3689         rtl_set_def_aspm_entry_latency(tp);
3690         rtl_hw_aspm_clkreq_enable(tp, false);
3691
3692         rtl_ephy_init(tp, e_info_8125b);
3693         rtl_hw_start_8125_common(tp);
3694
3695         rtl_hw_aspm_clkreq_enable(tp, true);
3696 }
3697
3698 static void rtl_hw_config(struct rtl8169_private *tp)
3699 {
3700         static const rtl_generic_fct hw_configs[] = {
3701                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3702                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3703                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3704                 [RTL_GIGA_MAC_VER_10] = NULL,
3705                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3706                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b,
3707                 [RTL_GIGA_MAC_VER_13] = NULL,
3708                 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3709                 [RTL_GIGA_MAC_VER_16] = NULL,
3710                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3711                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3712                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3713                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3714                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
3715                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3716                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3717                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3718                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3719                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3720                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
3721                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3722                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3723                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3724                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3725                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3726                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3727                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3728                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3729                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3730                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3731                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3732                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3733                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3734                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
3735                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3736                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3737                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3738                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
3739                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3740                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
3741                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3742                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
3743                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
3744                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3745                 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3746                 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1,
3747                 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3748                 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3749         };
3750
3751         if (hw_configs[tp->mac_version])
3752                 hw_configs[tp->mac_version](tp);
3753 }
3754
3755 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3756 {
3757         int i;
3758
3759         /* disable interrupt coalescing */
3760         for (i = 0xa00; i < 0xb00; i += 4)
3761                 RTL_W32(tp, i, 0);
3762
3763         rtl_hw_config(tp);
3764 }
3765
3766 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3767 {
3768         if (rtl_is_8168evl_up(tp))
3769                 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3770         else
3771                 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3772
3773         rtl_hw_config(tp);
3774
3775         /* disable interrupt coalescing */
3776         RTL_W16(tp, IntrMitigate, 0x0000);
3777 }
3778
3779 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3780 {
3781         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3782
3783         tp->cp_cmd |= PCIMulRW;
3784
3785         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3786             tp->mac_version == RTL_GIGA_MAC_VER_03)
3787                 tp->cp_cmd |= EnAnaPLL;
3788
3789         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3790
3791         rtl8169_set_magic_reg(tp);
3792
3793         /* disable interrupt coalescing */
3794         RTL_W16(tp, IntrMitigate, 0x0000);
3795 }
3796
3797 static void rtl_hw_start(struct  rtl8169_private *tp)
3798 {
3799         rtl_unlock_config_regs(tp);
3800
3801         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3802
3803         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3804                 rtl_hw_start_8169(tp);
3805         else if (rtl_is_8125(tp))
3806                 rtl_hw_start_8125(tp);
3807         else
3808                 rtl_hw_start_8168(tp);
3809
3810         rtl_set_rx_max_size(tp);
3811         rtl_set_rx_tx_desc_registers(tp);
3812         rtl_lock_config_regs(tp);
3813
3814         rtl_jumbo_config(tp);
3815
3816         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3817         rtl_pci_commit(tp);
3818
3819         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3820         rtl_init_rxcfg(tp);
3821         rtl_set_tx_config_registers(tp);
3822         rtl_set_rx_config_features(tp, tp->dev->features);
3823         rtl_set_rx_mode(tp->dev);
3824         rtl_irq_enable(tp);
3825 }
3826
3827 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3828 {
3829         struct rtl8169_private *tp = netdev_priv(dev);
3830
3831         dev->mtu = new_mtu;
3832         netdev_update_features(dev);
3833         rtl_jumbo_config(tp);
3834
3835         switch (tp->mac_version) {
3836         case RTL_GIGA_MAC_VER_61:
3837         case RTL_GIGA_MAC_VER_63:
3838                 rtl8125_set_eee_txidle_timer(tp);
3839                 break;
3840         default:
3841                 break;
3842         }
3843
3844         return 0;
3845 }
3846
3847 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3848 {
3849         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3850
3851         desc->opts2 = 0;
3852         /* Force memory writes to complete before releasing descriptor */
3853         dma_wmb();
3854         WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3855 }
3856
3857 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3858                                           struct RxDesc *desc)
3859 {
3860         struct device *d = tp_to_dev(tp);
3861         int node = dev_to_node(d);
3862         dma_addr_t mapping;
3863         struct page *data;
3864
3865         data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3866         if (!data)
3867                 return NULL;
3868
3869         mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3870         if (unlikely(dma_mapping_error(d, mapping))) {
3871                 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3872                 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3873                 return NULL;
3874         }
3875
3876         desc->addr = cpu_to_le64(mapping);
3877         rtl8169_mark_to_asic(desc);
3878
3879         return data;
3880 }
3881
3882 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3883 {
3884         unsigned int i;
3885
3886         for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3887                 dma_unmap_page(tp_to_dev(tp),
3888                                le64_to_cpu(tp->RxDescArray[i].addr),
3889                                R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3890                 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3891                 tp->Rx_databuff[i] = NULL;
3892                 tp->RxDescArray[i].addr = 0;
3893                 tp->RxDescArray[i].opts1 = 0;
3894         }
3895 }
3896
3897 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3898 {
3899         unsigned int i;
3900
3901         for (i = 0; i < NUM_RX_DESC; i++) {
3902                 struct page *data;
3903
3904                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3905                 if (!data) {
3906                         rtl8169_rx_clear(tp);
3907                         return -ENOMEM;
3908                 }
3909                 tp->Rx_databuff[i] = data;
3910         }
3911
3912         /* mark as last descriptor in the ring */
3913         tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3914
3915         return 0;
3916 }
3917
3918 static int rtl8169_init_ring(struct rtl8169_private *tp)
3919 {
3920         rtl8169_init_ring_indexes(tp);
3921
3922         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3923         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3924
3925         return rtl8169_rx_fill(tp);
3926 }
3927
3928 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3929 {
3930         struct ring_info *tx_skb = tp->tx_skb + entry;
3931         struct TxDesc *desc = tp->TxDescArray + entry;
3932
3933         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3934                          DMA_TO_DEVICE);
3935         memset(desc, 0, sizeof(*desc));
3936         memset(tx_skb, 0, sizeof(*tx_skb));
3937 }
3938
3939 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3940                                    unsigned int n)
3941 {
3942         unsigned int i;
3943
3944         for (i = 0; i < n; i++) {
3945                 unsigned int entry = (start + i) % NUM_TX_DESC;
3946                 struct ring_info *tx_skb = tp->tx_skb + entry;
3947                 unsigned int len = tx_skb->len;
3948
3949                 if (len) {
3950                         struct sk_buff *skb = tx_skb->skb;
3951
3952                         rtl8169_unmap_tx_skb(tp, entry);
3953                         if (skb)
3954                                 dev_consume_skb_any(skb);
3955                 }
3956         }
3957 }
3958
3959 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3960 {
3961         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3962         netdev_reset_queue(tp->dev);
3963 }
3964
3965 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
3966 {
3967         napi_disable(&tp->napi);
3968
3969         /* Give a racing hard_start_xmit a few cycles to complete. */
3970         synchronize_net();
3971
3972         /* Disable interrupts */
3973         rtl8169_irq_mask_and_ack(tp);
3974
3975         rtl_rx_close(tp);
3976
3977         if (going_down && tp->dev->wol_enabled)
3978                 goto no_reset;
3979
3980         switch (tp->mac_version) {
3981         case RTL_GIGA_MAC_VER_27:
3982         case RTL_GIGA_MAC_VER_28:
3983         case RTL_GIGA_MAC_VER_31:
3984                 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3985                 break;
3986         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3987                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3988                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3989                 break;
3990         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3991                 rtl_enable_rxdvgate(tp);
3992                 fsleep(2000);
3993                 break;
3994         default:
3995                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3996                 fsleep(100);
3997                 break;
3998         }
3999
4000         rtl_hw_reset(tp);
4001 no_reset:
4002         rtl8169_tx_clear(tp);
4003         rtl8169_init_ring_indexes(tp);
4004 }
4005
4006 static void rtl_reset_work(struct rtl8169_private *tp)
4007 {
4008         int i;
4009
4010         netif_stop_queue(tp->dev);
4011
4012         rtl8169_cleanup(tp, false);
4013
4014         for (i = 0; i < NUM_RX_DESC; i++)
4015                 rtl8169_mark_to_asic(tp->RxDescArray + i);
4016
4017         napi_enable(&tp->napi);
4018         rtl_hw_start(tp);
4019 }
4020
4021 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
4022 {
4023         struct rtl8169_private *tp = netdev_priv(dev);
4024
4025         rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT);
4026 }
4027
4028 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4029                           void *addr, unsigned int entry, bool desc_own)
4030 {
4031         struct TxDesc *txd = tp->TxDescArray + entry;
4032         struct device *d = tp_to_dev(tp);
4033         dma_addr_t mapping;
4034         u32 opts1;
4035         int ret;
4036
4037         mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4038         ret = dma_mapping_error(d, mapping);
4039         if (unlikely(ret)) {
4040                 if (net_ratelimit())
4041                         netdev_err(tp->dev, "Failed to map TX data!\n");
4042                 return ret;
4043         }
4044
4045         txd->addr = cpu_to_le64(mapping);
4046         txd->opts2 = cpu_to_le32(opts[1]);
4047
4048         opts1 = opts[0] | len;
4049         if (entry == NUM_TX_DESC - 1)
4050                 opts1 |= RingEnd;
4051         if (desc_own)
4052                 opts1 |= DescOwn;
4053         txd->opts1 = cpu_to_le32(opts1);
4054
4055         tp->tx_skb[entry].len = len;
4056
4057         return 0;
4058 }
4059
4060 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4061                               const u32 *opts, unsigned int entry)
4062 {
4063         struct skb_shared_info *info = skb_shinfo(skb);
4064         unsigned int cur_frag;
4065
4066         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4067                 const skb_frag_t *frag = info->frags + cur_frag;
4068                 void *addr = skb_frag_address(frag);
4069                 u32 len = skb_frag_size(frag);
4070
4071                 entry = (entry + 1) % NUM_TX_DESC;
4072
4073                 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4074                         goto err_out;
4075         }
4076
4077         return 0;
4078
4079 err_out:
4080         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4081         return -EIO;
4082 }
4083
4084 static bool rtl_skb_is_udp(struct sk_buff *skb)
4085 {
4086         int no = skb_network_offset(skb);
4087         struct ipv6hdr *i6h, _i6h;
4088         struct iphdr *ih, _ih;
4089
4090         switch (vlan_get_protocol(skb)) {
4091         case htons(ETH_P_IP):
4092                 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4093                 return ih && ih->protocol == IPPROTO_UDP;
4094         case htons(ETH_P_IPV6):
4095                 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4096                 return i6h && i6h->nexthdr == IPPROTO_UDP;
4097         default:
4098                 return false;
4099         }
4100 }
4101
4102 #define RTL_MIN_PATCH_LEN       47
4103
4104 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4105 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4106                                             struct sk_buff *skb)
4107 {
4108         unsigned int padto = 0, len = skb->len;
4109
4110         if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4111             rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) {
4112                 unsigned int trans_data_len = skb_tail_pointer(skb) -
4113                                               skb_transport_header(skb);
4114
4115                 if (trans_data_len >= offsetof(struct udphdr, len) &&
4116                     trans_data_len < RTL_MIN_PATCH_LEN) {
4117                         u16 dest = ntohs(udp_hdr(skb)->dest);
4118
4119                         /* dest is a standard PTP port */
4120                         if (dest == 319 || dest == 320)
4121                                 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4122                 }
4123
4124                 if (trans_data_len < sizeof(struct udphdr))
4125                         padto = max_t(unsigned int, padto,
4126                                       len + sizeof(struct udphdr) - trans_data_len);
4127         }
4128
4129         return padto;
4130 }
4131
4132 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4133                                            struct sk_buff *skb)
4134 {
4135         unsigned int padto;
4136
4137         padto = rtl8125_quirk_udp_padto(tp, skb);
4138
4139         switch (tp->mac_version) {
4140         case RTL_GIGA_MAC_VER_34:
4141         case RTL_GIGA_MAC_VER_60:
4142         case RTL_GIGA_MAC_VER_61:
4143         case RTL_GIGA_MAC_VER_63:
4144                 padto = max_t(unsigned int, padto, ETH_ZLEN);
4145         default:
4146                 break;
4147         }
4148
4149         return padto;
4150 }
4151
4152 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4153 {
4154         u32 mss = skb_shinfo(skb)->gso_size;
4155
4156         if (mss) {
4157                 opts[0] |= TD_LSO;
4158                 opts[0] |= mss << TD0_MSS_SHIFT;
4159         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4160                 const struct iphdr *ip = ip_hdr(skb);
4161
4162                 if (ip->protocol == IPPROTO_TCP)
4163                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4164                 else if (ip->protocol == IPPROTO_UDP)
4165                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4166                 else
4167                         WARN_ON_ONCE(1);
4168         }
4169 }
4170
4171 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4172                                 struct sk_buff *skb, u32 *opts)
4173 {
4174         struct skb_shared_info *shinfo = skb_shinfo(skb);
4175         u32 mss = shinfo->gso_size;
4176
4177         if (mss) {
4178                 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4179                         opts[0] |= TD1_GTSENV4;
4180                 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4181                         if (skb_cow_head(skb, 0))
4182                                 return false;
4183
4184                         tcp_v6_gso_csum_prep(skb);
4185                         opts[0] |= TD1_GTSENV6;
4186                 } else {
4187                         WARN_ON_ONCE(1);
4188                 }
4189
4190                 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4191                 opts[1] |= mss << TD1_MSS_SHIFT;
4192         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4193                 u8 ip_protocol;
4194
4195                 switch (vlan_get_protocol(skb)) {
4196                 case htons(ETH_P_IP):
4197                         opts[1] |= TD1_IPv4_CS;
4198                         ip_protocol = ip_hdr(skb)->protocol;
4199                         break;
4200
4201                 case htons(ETH_P_IPV6):
4202                         opts[1] |= TD1_IPv6_CS;
4203                         ip_protocol = ipv6_hdr(skb)->nexthdr;
4204                         break;
4205
4206                 default:
4207                         ip_protocol = IPPROTO_RAW;
4208                         break;
4209                 }
4210
4211                 if (ip_protocol == IPPROTO_TCP)
4212                         opts[1] |= TD1_TCP_CS;
4213                 else if (ip_protocol == IPPROTO_UDP)
4214                         opts[1] |= TD1_UDP_CS;
4215                 else
4216                         WARN_ON_ONCE(1);
4217
4218                 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
4219         } else {
4220                 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4221
4222                 /* skb_padto would free the skb on error */
4223                 return !__skb_put_padto(skb, padto, false);
4224         }
4225
4226         return true;
4227 }
4228
4229 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
4230                                unsigned int nr_frags)
4231 {
4232         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
4233
4234         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4235         return slots_avail > nr_frags;
4236 }
4237
4238 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4239 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4240 {
4241         switch (tp->mac_version) {
4242         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4243         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4244                 return false;
4245         default:
4246                 return true;
4247         }
4248 }
4249
4250 static void rtl8169_doorbell(struct rtl8169_private *tp)
4251 {
4252         if (rtl_is_8125(tp))
4253                 RTL_W16(tp, TxPoll_8125, BIT(0));
4254         else
4255                 RTL_W8(tp, TxPoll, NPQ);
4256 }
4257
4258 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4259                                       struct net_device *dev)
4260 {
4261         unsigned int frags = skb_shinfo(skb)->nr_frags;
4262         struct rtl8169_private *tp = netdev_priv(dev);
4263         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4264         struct TxDesc *txd_first, *txd_last;
4265         bool stop_queue, door_bell;
4266         u32 opts[2];
4267
4268         txd_first = tp->TxDescArray + entry;
4269
4270         if (unlikely(!rtl_tx_slots_avail(tp, frags))) {
4271                 if (net_ratelimit())
4272                         netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4273                 goto err_stop_0;
4274         }
4275
4276         if (unlikely(le32_to_cpu(txd_first->opts1) & DescOwn))
4277                 goto err_stop_0;
4278
4279         opts[1] = rtl8169_tx_vlan_tag(skb);
4280         opts[0] = 0;
4281
4282         if (!rtl_chip_supports_csum_v2(tp))
4283                 rtl8169_tso_csum_v1(skb, opts);
4284         else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4285                 goto err_dma_0;
4286
4287         if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4288                                     entry, false)))
4289                 goto err_dma_0;
4290
4291         if (frags) {
4292                 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4293                         goto err_dma_1;
4294                 entry = (entry + frags) % NUM_TX_DESC;
4295         }
4296
4297         txd_last = tp->TxDescArray + entry;
4298         txd_last->opts1 |= cpu_to_le32(LastFrag);
4299         tp->tx_skb[entry].skb = skb;
4300
4301         skb_tx_timestamp(skb);
4302
4303         /* Force memory writes to complete before releasing descriptor */
4304         dma_wmb();
4305
4306         door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4307
4308         txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4309
4310         /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4311         smp_wmb();
4312
4313         tp->cur_tx += frags + 1;
4314
4315         stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
4316         if (unlikely(stop_queue)) {
4317                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4318                  * not miss a ring update when it notices a stopped queue.
4319                  */
4320                 smp_wmb();
4321                 netif_stop_queue(dev);
4322                 door_bell = true;
4323         }
4324
4325         if (door_bell)
4326                 rtl8169_doorbell(tp);
4327
4328         if (unlikely(stop_queue)) {
4329                 /* Sync with rtl_tx:
4330                  * - publish queue status and cur_tx ring index (write barrier)
4331                  * - refresh dirty_tx ring index (read barrier).
4332                  * May the current thread have a pessimistic view of the ring
4333                  * status and forget to wake up queue, a racing rtl_tx thread
4334                  * can't.
4335                  */
4336                 smp_mb();
4337                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
4338                         netif_start_queue(dev);
4339         }
4340
4341         return NETDEV_TX_OK;
4342
4343 err_dma_1:
4344         rtl8169_unmap_tx_skb(tp, entry);
4345 err_dma_0:
4346         dev_kfree_skb_any(skb);
4347         dev->stats.tx_dropped++;
4348         return NETDEV_TX_OK;
4349
4350 err_stop_0:
4351         netif_stop_queue(dev);
4352         dev->stats.tx_dropped++;
4353         return NETDEV_TX_BUSY;
4354 }
4355
4356 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4357 {
4358         struct skb_shared_info *info = skb_shinfo(skb);
4359         unsigned int nr_frags = info->nr_frags;
4360
4361         if (!nr_frags)
4362                 return UINT_MAX;
4363
4364         return skb_frag_size(info->frags + nr_frags - 1);
4365 }
4366
4367 /* Workaround for hw issues with TSO on RTL8168evl */
4368 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4369                                             netdev_features_t features)
4370 {
4371         /* IPv4 header has options field */
4372         if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4373             ip_hdrlen(skb) > sizeof(struct iphdr))
4374                 features &= ~NETIF_F_ALL_TSO;
4375
4376         /* IPv4 TCP header has options field */
4377         else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4378                  tcp_hdrlen(skb) > sizeof(struct tcphdr))
4379                 features &= ~NETIF_F_ALL_TSO;
4380
4381         else if (rtl_last_frag_len(skb) <= 6)
4382                 features &= ~NETIF_F_ALL_TSO;
4383
4384         return features;
4385 }
4386
4387 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4388                                                 struct net_device *dev,
4389                                                 netdev_features_t features)
4390 {
4391         struct rtl8169_private *tp = netdev_priv(dev);
4392
4393         if (skb_is_gso(skb)) {
4394                 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4395                         features = rtl8168evl_fix_tso(skb, features);
4396
4397                 if (skb_transport_offset(skb) > GTTCPHO_MAX &&
4398                     rtl_chip_supports_csum_v2(tp))
4399                         features &= ~NETIF_F_ALL_TSO;
4400         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4401                 /* work around hw bug on some chip versions */
4402                 if (skb->len < ETH_ZLEN)
4403                         features &= ~NETIF_F_CSUM_MASK;
4404
4405                 if (rtl_quirk_packet_padto(tp, skb))
4406                         features &= ~NETIF_F_CSUM_MASK;
4407
4408                 if (skb_transport_offset(skb) > TCPHO_MAX &&
4409                     rtl_chip_supports_csum_v2(tp))
4410                         features &= ~NETIF_F_CSUM_MASK;
4411         }
4412
4413         return vlan_features_check(skb, features);
4414 }
4415
4416 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4417 {
4418         struct rtl8169_private *tp = netdev_priv(dev);
4419         struct pci_dev *pdev = tp->pci_dev;
4420         int pci_status_errs;
4421         u16 pci_cmd;
4422
4423         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4424
4425         pci_status_errs = pci_status_get_and_clear_errors(pdev);
4426
4427         if (net_ratelimit())
4428                 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4429                            pci_cmd, pci_status_errs);
4430         /*
4431          * The recovery sequence below admits a very elaborated explanation:
4432          * - it seems to work;
4433          * - I did not see what else could be done;
4434          * - it makes iop3xx happy.
4435          *
4436          * Feel free to adjust to your needs.
4437          */
4438         if (pdev->broken_parity_status)
4439                 pci_cmd &= ~PCI_COMMAND_PARITY;
4440         else
4441                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4442
4443         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4444
4445         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4446 }
4447
4448 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4449                    int budget)
4450 {
4451         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
4452
4453         dirty_tx = tp->dirty_tx;
4454         smp_rmb();
4455
4456         for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) {
4457                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4458                 struct sk_buff *skb = tp->tx_skb[entry].skb;
4459                 u32 status;
4460
4461                 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));
4462                 if (status & DescOwn)
4463                         break;
4464
4465                 rtl8169_unmap_tx_skb(tp, entry);
4466
4467                 if (skb) {
4468                         pkts_compl++;
4469                         bytes_compl += skb->len;
4470                         napi_consume_skb(skb, budget);
4471                 }
4472                 dirty_tx++;
4473         }
4474
4475         if (tp->dirty_tx != dirty_tx) {
4476                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
4477
4478                 rtl_inc_priv_stats(&tp->tx_stats, pkts_compl, bytes_compl);
4479
4480                 tp->dirty_tx = dirty_tx;
4481                 /* Sync with rtl8169_start_xmit:
4482                  * - publish dirty_tx ring index (write barrier)
4483                  * - refresh cur_tx ring index and queue status (read barrier)
4484                  * May the current thread miss the stopped queue condition,
4485                  * a racing xmit thread can only have a right view of the
4486                  * ring status.
4487                  */
4488                 smp_mb();
4489                 if (netif_queue_stopped(dev) &&
4490                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
4491                         netif_wake_queue(dev);
4492                 }
4493                 /*
4494                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4495                  * too close. Let's kick an extra TxPoll request when a burst
4496                  * of start_xmit activity is detected (if it is not detected,
4497                  * it is slow enough). -- FR
4498                  */
4499                 if (tp->cur_tx != dirty_tx)
4500                         rtl8169_doorbell(tp);
4501         }
4502 }
4503
4504 static inline int rtl8169_fragmented_frame(u32 status)
4505 {
4506         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4507 }
4508
4509 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4510 {
4511         u32 status = opts1 & RxProtoMask;
4512
4513         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4514             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4515                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4516         else
4517                 skb_checksum_none_assert(skb);
4518 }
4519
4520 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
4521 {
4522         unsigned int cur_rx, rx_left, count;
4523         struct device *d = tp_to_dev(tp);
4524
4525         cur_rx = tp->cur_rx;
4526
4527         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
4528                 unsigned int pkt_size, entry = cur_rx % NUM_RX_DESC;
4529                 struct RxDesc *desc = tp->RxDescArray + entry;
4530                 struct sk_buff *skb;
4531                 const void *rx_buf;
4532                 dma_addr_t addr;
4533                 u32 status;
4534
4535                 status = le32_to_cpu(READ_ONCE(desc->opts1));
4536                 if (status & DescOwn)
4537                         break;
4538
4539                 /* This barrier is needed to keep us from reading
4540                  * any other fields out of the Rx descriptor until
4541                  * we know the status of DescOwn
4542                  */
4543                 dma_rmb();
4544
4545                 if (unlikely(status & RxRES)) {
4546                         if (net_ratelimit())
4547                                 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4548                                             status);
4549                         dev->stats.rx_errors++;
4550                         if (status & (RxRWT | RxRUNT))
4551                                 dev->stats.rx_length_errors++;
4552                         if (status & RxCRC)
4553                                 dev->stats.rx_crc_errors++;
4554
4555                         if (!(dev->features & NETIF_F_RXALL))
4556                                 goto release_descriptor;
4557                         else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4558                                 goto release_descriptor;
4559                 }
4560
4561                 pkt_size = status & GENMASK(13, 0);
4562                 if (likely(!(dev->features & NETIF_F_RXFCS)))
4563                         pkt_size -= ETH_FCS_LEN;
4564
4565                 /* The driver does not support incoming fragmented frames.
4566                  * They are seen as a symptom of over-mtu sized frames.
4567                  */
4568                 if (unlikely(rtl8169_fragmented_frame(status))) {
4569                         dev->stats.rx_dropped++;
4570                         dev->stats.rx_length_errors++;
4571                         goto release_descriptor;
4572                 }
4573
4574                 skb = napi_alloc_skb(&tp->napi, pkt_size);
4575                 if (unlikely(!skb)) {
4576                         dev->stats.rx_dropped++;
4577                         goto release_descriptor;
4578                 }
4579
4580                 addr = le64_to_cpu(desc->addr);
4581                 rx_buf = page_address(tp->Rx_databuff[entry]);
4582
4583                 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4584                 prefetch(rx_buf);
4585                 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4586                 skb->tail += pkt_size;
4587                 skb->len = pkt_size;
4588                 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4589
4590                 rtl8169_rx_csum(skb, status);
4591                 skb->protocol = eth_type_trans(skb, dev);
4592
4593                 rtl8169_rx_vlan_tag(desc, skb);
4594
4595                 if (skb->pkt_type == PACKET_MULTICAST)
4596                         dev->stats.multicast++;
4597
4598                 napi_gro_receive(&tp->napi, skb);
4599
4600                 rtl_inc_priv_stats(&tp->rx_stats, 1, pkt_size);
4601 release_descriptor:
4602                 rtl8169_mark_to_asic(desc);
4603         }
4604
4605         count = cur_rx - tp->cur_rx;
4606         tp->cur_rx = cur_rx;
4607
4608         return count;
4609 }
4610
4611 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4612 {
4613         struct rtl8169_private *tp = dev_instance;
4614         u32 status = rtl_get_events(tp);
4615
4616         if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4617                 return IRQ_NONE;
4618
4619         if (unlikely(status & SYSErr)) {
4620                 rtl8169_pcierr_interrupt(tp->dev);
4621                 goto out;
4622         }
4623
4624         if (status & LinkChg)
4625                 phy_mac_interrupt(tp->phydev);
4626
4627         if (unlikely(status & RxFIFOOver &&
4628             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4629                 netif_stop_queue(tp->dev);
4630                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4631         }
4632
4633         rtl_irq_disable(tp);
4634         napi_schedule(&tp->napi);
4635 out:
4636         rtl_ack_events(tp, status);
4637
4638         return IRQ_HANDLED;
4639 }
4640
4641 static void rtl_task(struct work_struct *work)
4642 {
4643         struct rtl8169_private *tp =
4644                 container_of(work, struct rtl8169_private, wk.work);
4645         int ret;
4646
4647         rtnl_lock();
4648
4649         if (!netif_running(tp->dev) ||
4650             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4651                 goto out_unlock;
4652
4653         if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {
4654                 /* ASPM compatibility issues are a typical reason for tx timeouts */
4655                 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 |
4656                                                           PCIE_LINK_STATE_L0S);
4657                 if (!ret)
4658                         netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");
4659                 goto reset;
4660         }
4661
4662         if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4663 reset:
4664                 rtl_reset_work(tp);
4665                 netif_wake_queue(tp->dev);
4666         } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) {
4667                 rtl_reset_work(tp);
4668         }
4669 out_unlock:
4670         rtnl_unlock();
4671 }
4672
4673 static int rtl8169_poll(struct napi_struct *napi, int budget)
4674 {
4675         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4676         struct net_device *dev = tp->dev;
4677         int work_done;
4678
4679         work_done = rtl_rx(dev, tp, (u32) budget);
4680
4681         rtl_tx(dev, tp, budget);
4682
4683         if (work_done < budget && napi_complete_done(napi, work_done))
4684                 rtl_irq_enable(tp);
4685
4686         return work_done;
4687 }
4688
4689 static void r8169_phylink_handler(struct net_device *ndev)
4690 {
4691         struct rtl8169_private *tp = netdev_priv(ndev);
4692         struct device *d = tp_to_dev(tp);
4693
4694         if (netif_carrier_ok(ndev)) {
4695                 rtl_link_chg_patch(tp);
4696                 pm_request_resume(d);
4697                 netif_wake_queue(tp->dev);
4698         } else {
4699                 /* In few cases rx is broken after link-down otherwise */
4700                 if (rtl_is_8125(tp))
4701                         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE);
4702                 pm_runtime_idle(d);
4703         }
4704
4705         if (net_ratelimit())
4706                 phy_print_status(tp->phydev);
4707 }
4708
4709 static int r8169_phy_connect(struct rtl8169_private *tp)
4710 {
4711         struct phy_device *phydev = tp->phydev;
4712         phy_interface_t phy_mode;
4713         int ret;
4714
4715         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4716                    PHY_INTERFACE_MODE_MII;
4717
4718         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4719                                  phy_mode);
4720         if (ret)
4721                 return ret;
4722
4723         if (!tp->supports_gmii)
4724                 phy_set_max_speed(phydev, SPEED_100);
4725
4726         phy_attached_info(phydev);
4727
4728         return 0;
4729 }
4730
4731 static void rtl8169_down(struct rtl8169_private *tp)
4732 {
4733         /* Clear all task flags */
4734         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4735
4736         phy_stop(tp->phydev);
4737
4738         rtl8169_update_counters(tp);
4739
4740         pci_clear_master(tp->pci_dev);
4741         rtl_pci_commit(tp);
4742
4743         rtl8169_cleanup(tp, true);
4744
4745         rtl_pll_power_down(tp);
4746 }
4747
4748 static void rtl8169_up(struct rtl8169_private *tp)
4749 {
4750         pci_set_master(tp->pci_dev);
4751         rtl_pll_power_up(tp);
4752         rtl8169_init_phy(tp);
4753         napi_enable(&tp->napi);
4754         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4755         rtl_reset_work(tp);
4756
4757         phy_start(tp->phydev);
4758 }
4759
4760 static int rtl8169_close(struct net_device *dev)
4761 {
4762         struct rtl8169_private *tp = netdev_priv(dev);
4763         struct pci_dev *pdev = tp->pci_dev;
4764
4765         pm_runtime_get_sync(&pdev->dev);
4766
4767         netif_stop_queue(dev);
4768         rtl8169_down(tp);
4769         rtl8169_rx_clear(tp);
4770
4771         cancel_work(&tp->wk.work);
4772
4773         free_irq(pci_irq_vector(pdev, 0), tp);
4774
4775         phy_disconnect(tp->phydev);
4776
4777         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4778                           tp->RxPhyAddr);
4779         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4780                           tp->TxPhyAddr);
4781         tp->TxDescArray = NULL;
4782         tp->RxDescArray = NULL;
4783
4784         pm_runtime_put_sync(&pdev->dev);
4785
4786         return 0;
4787 }
4788
4789 #ifdef CONFIG_NET_POLL_CONTROLLER
4790 static void rtl8169_netpoll(struct net_device *dev)
4791 {
4792         struct rtl8169_private *tp = netdev_priv(dev);
4793
4794         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
4795 }
4796 #endif
4797
4798 static int rtl_open(struct net_device *dev)
4799 {
4800         struct rtl8169_private *tp = netdev_priv(dev);
4801         struct pci_dev *pdev = tp->pci_dev;
4802         int retval = -ENOMEM;
4803
4804         pm_runtime_get_sync(&pdev->dev);
4805
4806         /*
4807          * Rx and Tx descriptors needs 256 bytes alignment.
4808          * dma_alloc_coherent provides more.
4809          */
4810         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4811                                              &tp->TxPhyAddr, GFP_KERNEL);
4812         if (!tp->TxDescArray)
4813                 goto err_pm_runtime_put;
4814
4815         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4816                                              &tp->RxPhyAddr, GFP_KERNEL);
4817         if (!tp->RxDescArray)
4818                 goto err_free_tx_0;
4819
4820         retval = rtl8169_init_ring(tp);
4821         if (retval < 0)
4822                 goto err_free_rx_1;
4823
4824         rtl_request_firmware(tp);
4825
4826         retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt,
4827                              IRQF_SHARED, dev->name, tp);
4828         if (retval < 0)
4829                 goto err_release_fw_2;
4830
4831         retval = r8169_phy_connect(tp);
4832         if (retval)
4833                 goto err_free_irq;
4834
4835         rtl8169_up(tp);
4836         rtl8169_init_counter_offsets(tp);
4837         netif_start_queue(dev);
4838
4839         pm_runtime_put_sync(&pdev->dev);
4840 out:
4841         return retval;
4842
4843 err_free_irq:
4844         free_irq(pci_irq_vector(pdev, 0), tp);
4845 err_release_fw_2:
4846         rtl_release_firmware(tp);
4847         rtl8169_rx_clear(tp);
4848 err_free_rx_1:
4849         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4850                           tp->RxPhyAddr);
4851         tp->RxDescArray = NULL;
4852 err_free_tx_0:
4853         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4854                           tp->TxPhyAddr);
4855         tp->TxDescArray = NULL;
4856 err_pm_runtime_put:
4857         pm_runtime_put_noidle(&pdev->dev);
4858         goto out;
4859 }
4860
4861 static void
4862 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4863 {
4864         struct rtl8169_private *tp = netdev_priv(dev);
4865         struct pci_dev *pdev = tp->pci_dev;
4866         struct rtl8169_counters *counters = tp->counters;
4867
4868         pm_runtime_get_noresume(&pdev->dev);
4869
4870         netdev_stats_to_stats64(stats, &dev->stats);
4871
4872         rtl_get_priv_stats(&tp->rx_stats, &stats->rx_packets, &stats->rx_bytes);
4873         rtl_get_priv_stats(&tp->tx_stats, &stats->tx_packets, &stats->tx_bytes);
4874
4875         /*
4876          * Fetch additional counter values missing in stats collected by driver
4877          * from tally counters.
4878          */
4879         if (pm_runtime_active(&pdev->dev))
4880                 rtl8169_update_counters(tp);
4881
4882         /*
4883          * Subtract values fetched during initalization.
4884          * See rtl8169_init_counter_offsets for a description why we do that.
4885          */
4886         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4887                 le64_to_cpu(tp->tc_offset.tx_errors);
4888         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4889                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4890         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4891                 le16_to_cpu(tp->tc_offset.tx_aborted);
4892         stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4893                 le16_to_cpu(tp->tc_offset.rx_missed);
4894
4895         pm_runtime_put_noidle(&pdev->dev);
4896 }
4897
4898 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4899 {
4900         netif_device_detach(tp->dev);
4901
4902         if (netif_running(tp->dev))
4903                 rtl8169_down(tp);
4904 }
4905
4906 #ifdef CONFIG_PM
4907
4908 static int rtl8169_net_resume(struct rtl8169_private *tp)
4909 {
4910         rtl_rar_set(tp, tp->dev->dev_addr);
4911
4912         if (tp->TxDescArray)
4913                 rtl8169_up(tp);
4914
4915         netif_device_attach(tp->dev);
4916
4917         return 0;
4918 }
4919
4920 static int __maybe_unused rtl8169_suspend(struct device *device)
4921 {
4922         struct rtl8169_private *tp = dev_get_drvdata(device);
4923
4924         rtnl_lock();
4925         rtl8169_net_suspend(tp);
4926         if (!device_may_wakeup(tp_to_dev(tp)))
4927                 clk_disable_unprepare(tp->clk);
4928         rtnl_unlock();
4929
4930         return 0;
4931 }
4932
4933 static int __maybe_unused rtl8169_resume(struct device *device)
4934 {
4935         struct rtl8169_private *tp = dev_get_drvdata(device);
4936
4937         if (!device_may_wakeup(tp_to_dev(tp)))
4938                 clk_prepare_enable(tp->clk);
4939
4940         /* Reportedly at least Asus X453MA truncates packets otherwise */
4941         if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4942                 rtl_init_rxcfg(tp);
4943
4944         return rtl8169_net_resume(tp);
4945 }
4946
4947 static int rtl8169_runtime_suspend(struct device *device)
4948 {
4949         struct rtl8169_private *tp = dev_get_drvdata(device);
4950
4951         if (!tp->TxDescArray) {
4952                 netif_device_detach(tp->dev);
4953                 return 0;
4954         }
4955
4956         rtnl_lock();
4957         __rtl8169_set_wol(tp, WAKE_PHY);
4958         rtl8169_net_suspend(tp);
4959         rtnl_unlock();
4960
4961         return 0;
4962 }
4963
4964 static int rtl8169_runtime_resume(struct device *device)
4965 {
4966         struct rtl8169_private *tp = dev_get_drvdata(device);
4967
4968         __rtl8169_set_wol(tp, tp->saved_wolopts);
4969
4970         return rtl8169_net_resume(tp);
4971 }
4972
4973 static int rtl8169_runtime_idle(struct device *device)
4974 {
4975         struct rtl8169_private *tp = dev_get_drvdata(device);
4976
4977         if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4978                 pm_schedule_suspend(device, 10000);
4979
4980         return -EBUSY;
4981 }
4982
4983 static const struct dev_pm_ops rtl8169_pm_ops = {
4984         SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4985         SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4986                            rtl8169_runtime_idle)
4987 };
4988
4989 #endif /* CONFIG_PM */
4990
4991 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
4992 {
4993         /* WoL fails with 8168b when the receiver is disabled. */
4994         switch (tp->mac_version) {
4995         case RTL_GIGA_MAC_VER_11:
4996         case RTL_GIGA_MAC_VER_12:
4997         case RTL_GIGA_MAC_VER_17:
4998                 pci_clear_master(tp->pci_dev);
4999
5000                 RTL_W8(tp, ChipCmd, CmdRxEnb);
5001                 rtl_pci_commit(tp);
5002                 break;
5003         default:
5004                 break;
5005         }
5006 }
5007
5008 static void rtl_shutdown(struct pci_dev *pdev)
5009 {
5010         struct rtl8169_private *tp = pci_get_drvdata(pdev);
5011
5012         rtnl_lock();
5013         rtl8169_net_suspend(tp);
5014         rtnl_unlock();
5015
5016         /* Restore original MAC address */
5017         rtl_rar_set(tp, tp->dev->perm_addr);
5018
5019         if (system_state == SYSTEM_POWER_OFF) {
5020                 if (tp->saved_wolopts) {
5021                         rtl_wol_suspend_quirk(tp);
5022                         rtl_wol_shutdown_quirk(tp);
5023                 }
5024
5025                 pci_wake_from_d3(pdev, true);
5026                 pci_set_power_state(pdev, PCI_D3hot);
5027         }
5028 }
5029
5030 static void rtl_remove_one(struct pci_dev *pdev)
5031 {
5032         struct rtl8169_private *tp = pci_get_drvdata(pdev);
5033
5034         if (pci_dev_run_wake(pdev))
5035                 pm_runtime_get_noresume(&pdev->dev);
5036
5037         cancel_work_sync(&tp->wk.work);
5038
5039         unregister_netdev(tp->dev);
5040
5041         if (r8168_check_dash(tp))
5042                 rtl8168_driver_stop(tp);
5043
5044         rtl_release_firmware(tp);
5045
5046         /* restore original MAC address */
5047         rtl_rar_set(tp, tp->dev->perm_addr);
5048 }
5049
5050 static const struct net_device_ops rtl_netdev_ops = {
5051         .ndo_open               = rtl_open,
5052         .ndo_stop               = rtl8169_close,
5053         .ndo_get_stats64        = rtl8169_get_stats64,
5054         .ndo_start_xmit         = rtl8169_start_xmit,
5055         .ndo_features_check     = rtl8169_features_check,
5056         .ndo_tx_timeout         = rtl8169_tx_timeout,
5057         .ndo_validate_addr      = eth_validate_addr,
5058         .ndo_change_mtu         = rtl8169_change_mtu,
5059         .ndo_fix_features       = rtl8169_fix_features,
5060         .ndo_set_features       = rtl8169_set_features,
5061         .ndo_set_mac_address    = rtl_set_mac_address,
5062         .ndo_do_ioctl           = phy_do_ioctl_running,
5063         .ndo_set_rx_mode        = rtl_set_rx_mode,
5064 #ifdef CONFIG_NET_POLL_CONTROLLER
5065         .ndo_poll_controller    = rtl8169_netpoll,
5066 #endif
5067
5068 };
5069
5070 static void rtl_set_irq_mask(struct rtl8169_private *tp)
5071 {
5072         tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
5073
5074         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5075                 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
5076         else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
5077                 /* special workaround needed */
5078                 tp->irq_mask |= RxFIFOOver;
5079         else
5080                 tp->irq_mask |= RxOverflow;
5081 }
5082
5083 static int rtl_alloc_irq(struct rtl8169_private *tp)
5084 {
5085         unsigned int flags;
5086
5087         switch (tp->mac_version) {
5088         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5089                 rtl_unlock_config_regs(tp);
5090                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5091                 rtl_lock_config_regs(tp);
5092                 fallthrough;
5093         case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5094                 flags = PCI_IRQ_LEGACY;
5095                 break;
5096         default:
5097                 flags = PCI_IRQ_ALL_TYPES;
5098                 break;
5099         }
5100
5101         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5102 }
5103
5104 static void rtl_read_mac_address(struct rtl8169_private *tp,
5105                                  u8 mac_addr[ETH_ALEN])
5106 {
5107         /* Get MAC address */
5108         if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5109                 u32 value = rtl_eri_read(tp, 0xe0);
5110
5111                 mac_addr[0] = (value >>  0) & 0xff;
5112                 mac_addr[1] = (value >>  8) & 0xff;
5113                 mac_addr[2] = (value >> 16) & 0xff;
5114                 mac_addr[3] = (value >> 24) & 0xff;
5115
5116                 value = rtl_eri_read(tp, 0xe4);
5117                 mac_addr[4] = (value >>  0) & 0xff;
5118                 mac_addr[5] = (value >>  8) & 0xff;
5119         } else if (rtl_is_8125(tp)) {
5120                 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5121         }
5122 }
5123
5124 DECLARE_RTL_COND(rtl_link_list_ready_cond)
5125 {
5126         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5127 }
5128
5129 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5130 {
5131         rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5132 }
5133
5134 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5135 {
5136         struct rtl8169_private *tp = mii_bus->priv;
5137
5138         if (phyaddr > 0)
5139                 return -ENODEV;
5140
5141         return rtl_readphy(tp, phyreg);
5142 }
5143
5144 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5145                                 int phyreg, u16 val)
5146 {
5147         struct rtl8169_private *tp = mii_bus->priv;
5148
5149         if (phyaddr > 0)
5150                 return -ENODEV;
5151
5152         rtl_writephy(tp, phyreg, val);
5153
5154         return 0;
5155 }
5156
5157 static int r8169_mdio_register(struct rtl8169_private *tp)
5158 {
5159         struct pci_dev *pdev = tp->pci_dev;
5160         struct mii_bus *new_bus;
5161         int ret;
5162
5163         /* On some boards with this chip version the BIOS is buggy and misses
5164          * to reset the PHY page selector. This results in the PHY ID read
5165          * accessing registers on a different page, returning a more or
5166          * less random value. Fix this by resetting the page selector first.
5167          */
5168         if (tp->mac_version == RTL_GIGA_MAC_VER_25 ||
5169             tp->mac_version == RTL_GIGA_MAC_VER_26)
5170                 r8169_mdio_write(tp, 0x1f, 0);
5171
5172         new_bus = devm_mdiobus_alloc(&pdev->dev);
5173         if (!new_bus)
5174                 return -ENOMEM;
5175
5176         new_bus->name = "r8169";
5177         new_bus->priv = tp;
5178         new_bus->parent = &pdev->dev;
5179         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
5180         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
5181                  pci_domain_nr(pdev->bus), pci_dev_id(pdev));
5182
5183         new_bus->read = r8169_mdio_read_reg;
5184         new_bus->write = r8169_mdio_write_reg;
5185
5186         ret = devm_mdiobus_register(&pdev->dev, new_bus);
5187         if (ret)
5188                 return ret;
5189
5190         tp->phydev = mdiobus_get_phy(new_bus, 0);
5191         if (!tp->phydev) {
5192                 return -ENODEV;
5193         } else if (!tp->phydev->drv) {
5194                 /* Most chip versions fail with the genphy driver.
5195                  * Therefore ensure that the dedicated PHY driver is loaded.
5196                  */
5197                 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5198                         tp->phydev->phy_id);
5199                 return -EUNATCH;
5200         }
5201
5202         /* PHY will be woken up in rtl_open() */
5203         phy_suspend(tp->phydev);
5204
5205         return 0;
5206 }
5207
5208 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5209 {
5210         rtl_enable_rxdvgate(tp);
5211
5212         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5213         msleep(1);
5214         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5215
5216         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5217         r8168g_wait_ll_share_fifo_ready(tp);
5218
5219         r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5220         r8168g_wait_ll_share_fifo_ready(tp);
5221 }
5222
5223 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5224 {
5225         rtl_enable_rxdvgate(tp);
5226
5227         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5228         msleep(1);
5229         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5230
5231         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5232         r8168g_wait_ll_share_fifo_ready(tp);
5233
5234         r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5235         r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5236         r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5237         r8168g_wait_ll_share_fifo_ready(tp);
5238 }
5239
5240 static void rtl_hw_initialize(struct rtl8169_private *tp)
5241 {
5242         switch (tp->mac_version) {
5243         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
5244                 rtl8168ep_stop_cmac(tp);
5245                 fallthrough;
5246         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5247                 rtl_hw_init_8168g(tp);
5248                 break;
5249         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
5250                 rtl_hw_init_8125(tp);
5251                 break;
5252         default:
5253                 break;
5254         }
5255 }
5256
5257 static int rtl_jumbo_max(struct rtl8169_private *tp)
5258 {
5259         /* Non-GBit versions don't support jumbo frames */
5260         if (!tp->supports_gmii)
5261                 return 0;
5262
5263         switch (tp->mac_version) {
5264         /* RTL8169 */
5265         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5266                 return JUMBO_7K;
5267         /* RTL8168b */
5268         case RTL_GIGA_MAC_VER_11:
5269         case RTL_GIGA_MAC_VER_12:
5270         case RTL_GIGA_MAC_VER_17:
5271                 return JUMBO_4K;
5272         /* RTL8168c */
5273         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5274                 return JUMBO_6K;
5275         default:
5276                 return JUMBO_9K;
5277         }
5278 }
5279
5280 static void rtl_disable_clk(void *data)
5281 {
5282         clk_disable_unprepare(data);
5283 }
5284
5285 static int rtl_get_ether_clk(struct rtl8169_private *tp)
5286 {
5287         struct device *d = tp_to_dev(tp);
5288         struct clk *clk;
5289         int rc;
5290
5291         clk = devm_clk_get(d, "ether_clk");
5292         if (IS_ERR(clk)) {
5293                 rc = PTR_ERR(clk);
5294                 if (rc == -ENOENT)
5295                         /* clk-core allows NULL (for suspend / resume) */
5296                         rc = 0;
5297                 else if (rc != -EPROBE_DEFER)
5298                         dev_err(d, "failed to get clk: %d\n", rc);
5299         } else {
5300                 tp->clk = clk;
5301                 rc = clk_prepare_enable(clk);
5302                 if (rc)
5303                         dev_err(d, "failed to enable clk: %d\n", rc);
5304                 else
5305                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
5306         }
5307
5308         return rc;
5309 }
5310
5311 static void rtl_init_mac_address(struct rtl8169_private *tp)
5312 {
5313         struct net_device *dev = tp->dev;
5314         u8 *mac_addr = dev->dev_addr;
5315         int rc;
5316
5317         rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5318         if (!rc)
5319                 goto done;
5320
5321         rtl_read_mac_address(tp, mac_addr);
5322         if (is_valid_ether_addr(mac_addr))
5323                 goto done;
5324
5325         rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5326         if (is_valid_ether_addr(mac_addr))
5327                 goto done;
5328
5329         eth_hw_addr_random(dev);
5330         dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5331 done:
5332         rtl_rar_set(tp, mac_addr);
5333 }
5334
5335 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5336 {
5337         struct rtl8169_private *tp;
5338         int jumbo_max, region, rc;
5339         enum mac_version chipset;
5340         struct net_device *dev;
5341         u16 xid;
5342
5343         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5344         if (!dev)
5345                 return -ENOMEM;
5346
5347         SET_NETDEV_DEV(dev, &pdev->dev);
5348         dev->netdev_ops = &rtl_netdev_ops;
5349         tp = netdev_priv(dev);
5350         tp->dev = dev;
5351         tp->pci_dev = pdev;
5352         tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5353         tp->eee_adv = -1;
5354         tp->ocp_base = OCP_STD_PHY_BASE;
5355
5356         /* Get the *optional* external "ether_clk" used on some boards */
5357         rc = rtl_get_ether_clk(tp);
5358         if (rc)
5359                 return rc;
5360
5361         /* Disable ASPM completely as that cause random device stop working
5362          * problems as well as full system hangs for some PCIe devices users.
5363          */
5364         rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
5365                                           PCIE_LINK_STATE_L1);
5366         tp->aspm_manageable = !rc;
5367
5368         /* enable device (incl. PCI PM wakeup and hotplug setup) */
5369         rc = pcim_enable_device(pdev);
5370         if (rc < 0) {
5371                 dev_err(&pdev->dev, "enable failure\n");
5372                 return rc;
5373         }
5374
5375         if (pcim_set_mwi(pdev) < 0)
5376                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5377
5378         /* use first MMIO region */
5379         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5380         if (region < 0) {
5381                 dev_err(&pdev->dev, "no MMIO resource found\n");
5382                 return -ENODEV;
5383         }
5384
5385         /* check for weird/broken PCI region reporting */
5386         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
5387                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
5388                 return -ENODEV;
5389         }
5390
5391         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
5392         if (rc < 0) {
5393                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5394                 return rc;
5395         }
5396
5397         tp->mmio_addr = pcim_iomap_table(pdev)[region];
5398
5399         xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5400
5401         /* Identify chip attached to board */
5402         chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5403         if (chipset == RTL_GIGA_MAC_NONE) {
5404                 dev_err(&pdev->dev, "unknown chip XID %03x\n", xid);
5405                 return -ENODEV;
5406         }
5407
5408         tp->mac_version = chipset;
5409
5410         tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5411
5412         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5413             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5414                 dev->features |= NETIF_F_HIGHDMA;
5415
5416         rtl_init_rxcfg(tp);
5417
5418         rtl8169_irq_mask_and_ack(tp);
5419
5420         rtl_hw_initialize(tp);
5421
5422         rtl_hw_reset(tp);
5423
5424         rc = rtl_alloc_irq(tp);
5425         if (rc < 0) {
5426                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
5427                 return rc;
5428         }
5429
5430         INIT_WORK(&tp->wk.work, rtl_task);
5431         u64_stats_init(&tp->rx_stats.syncp);
5432         u64_stats_init(&tp->tx_stats.syncp);
5433
5434         rtl_init_mac_address(tp);
5435
5436         dev->ethtool_ops = &rtl8169_ethtool_ops;
5437
5438         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
5439
5440         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5441                            NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5442         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5443         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5444
5445         /*
5446          * Pretend we are using VLANs; This bypasses a nasty bug where
5447          * Interrupts stop flowing on high load on 8110SCd controllers.
5448          */
5449         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5450                 /* Disallow toggling */
5451                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5452
5453         if (rtl_chip_supports_csum_v2(tp))
5454                 dev->hw_features |= NETIF_F_IPV6_CSUM;
5455
5456         dev->features |= dev->hw_features;
5457
5458         /* There has been a number of reports that using SG/TSO results in
5459          * tx timeouts. However for a lot of people SG/TSO works fine.
5460          * Therefore disable both features by default, but allow users to
5461          * enable them. Use at own risk!
5462          */
5463         if (rtl_chip_supports_csum_v2(tp)) {
5464                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5465                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
5466                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
5467         } else {
5468                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5469                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
5470                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
5471         }
5472
5473         dev->hw_features |= NETIF_F_RXALL;
5474         dev->hw_features |= NETIF_F_RXFCS;
5475
5476         /* configure chip for default features */
5477         rtl8169_set_features(dev, dev->features);
5478
5479         jumbo_max = rtl_jumbo_max(tp);
5480         if (jumbo_max)
5481                 dev->max_mtu = jumbo_max;
5482
5483         rtl_set_irq_mask(tp);
5484
5485         tp->fw_name = rtl_chip_infos[chipset].fw_name;
5486
5487         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5488                                             &tp->counters_phys_addr,
5489                                             GFP_KERNEL);
5490         if (!tp->counters)
5491                 return -ENOMEM;
5492
5493         pci_set_drvdata(pdev, tp);
5494
5495         rc = r8169_mdio_register(tp);
5496         if (rc)
5497                 return rc;
5498
5499         /* chip gets powered up in rtl_open() */
5500         rtl_pll_power_down(tp);
5501
5502         rc = register_netdev(dev);
5503         if (rc)
5504                 return rc;
5505
5506         netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5507                     rtl_chip_infos[chipset].name, dev->dev_addr, xid,
5508                     pci_irq_vector(pdev, 0));
5509
5510         if (jumbo_max)
5511                 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5512                             jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5513                             "ok" : "ko");
5514
5515         if (r8168_check_dash(tp)) {
5516                 netdev_info(dev, "DASH enabled\n");
5517                 rtl8168_driver_start(tp);
5518         }
5519
5520         if (pci_dev_run_wake(pdev))
5521                 pm_runtime_put_sync(&pdev->dev);
5522
5523         return 0;
5524 }
5525
5526 static struct pci_driver rtl8169_pci_driver = {
5527         .name           = MODULENAME,
5528         .id_table       = rtl8169_pci_tbl,
5529         .probe          = rtl_init_one,
5530         .remove         = rtl_remove_one,
5531         .shutdown       = rtl_shutdown,
5532 #ifdef CONFIG_PM
5533         .driver.pm      = &rtl8169_pm_ops,
5534 #endif
5535 };
5536
5537 module_pci_driver(rtl8169_pci_driver);