drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "/*(DEBLOBBED)*/"
  41 #define FIRMWARE_8168D_2        "/*(DEBLOBBED)*/"
  42 #define FIRMWARE_8168E_1        "/*(DEBLOBBED)*/"
  43 #define FIRMWARE_8168E_2        "/*(DEBLOBBED)*/"
  44 #define FIRMWARE_8168E_3        "/*(DEBLOBBED)*/"
  45 #define FIRMWARE_8168F_1        "/*(DEBLOBBED)*/"
  46 #define FIRMWARE_8168F_2        "/*(DEBLOBBED)*/"
  47 #define FIRMWARE_8105E_1        "/*(DEBLOBBED)*/"
  48 #define FIRMWARE_8402_1         "/*(DEBLOBBED)*/"
  49 #define FIRMWARE_8411_1         "/*(DEBLOBBED)*/"
  50 #define FIRMWARE_8411_2         "/*(DEBLOBBED)*/"
  51 #define FIRMWARE_8106E_1        "/*(DEBLOBBED)*/"
  52 #define FIRMWARE_8106E_2        "/*(DEBLOBBED)*/"
  53 #define FIRMWARE_8168G_2        "/*(DEBLOBBED)*/"
  54 #define FIRMWARE_8168G_3        "/*(DEBLOBBED)*/"
  55 #define FIRMWARE_8168H_1        "/*(DEBLOBBED)*/"
  56 #define FIRMWARE_8168H_2        "/*(DEBLOBBED)*/"
  57 #define FIRMWARE_8107E_1        "/*(DEBLOBBED)*/"
  58 #define FIRMWARE_8107E_2        "/*(DEBLOBBED)*/"
  59
  60 #ifdef RTL8169_DEBUG
  61 #define assert(expr) \
  62         if (!(expr)) {                                  \
  63                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  64                 #expr,__FILE__,__func__,__LINE__);              \
  65         }
  66 #define dprintk(fmt, args...) \
  67         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  68 #else
  69 #define assert(expr) do {} while (0)
  70 #define dprintk(fmt, args...)   do {} while (0)
  71 #endif /* RTL8169_DEBUG */
  72
  73 #define R8169_MSG_DEFAULT \
  74         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  75
  76 #define TX_SLOTS_AVAIL(tp) \
  77         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  78
  79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  81         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  82
  83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  84    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  85 static const int multicast_filter_limit = 32;
  86
  87 #define MAX_READ_REQUEST_SHIFT  12
  88 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  89 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  90
  91 #define R8169_REGS_SIZE         256
  92 #define R8169_NAPI_WEIGHT       64
  93 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  94 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  95 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  96 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  97
  98 #define RTL8169_TX_TIMEOUT      (6*HZ)
  99 #define RTL8169_PHY_TIMEOUT     (10*HZ)
 100
 101 /* write/read MMIO register */
 102 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 103 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 104 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 105 #define RTL_R8(reg)             readb (ioaddr + (reg))
 106 #define RTL_R16(reg)            readw (ioaddr + (reg))
 107 #define RTL_R32(reg)            readl (ioaddr + (reg))
 108
 109 enum mac_version {
 110         RTL_GIGA_MAC_VER_01 = 0,
 111         RTL_GIGA_MAC_VER_02,
 112         RTL_GIGA_MAC_VER_03,
 113         RTL_GIGA_MAC_VER_04,
 114         RTL_GIGA_MAC_VER_05,
 115         RTL_GIGA_MAC_VER_06,
 116         RTL_GIGA_MAC_VER_07,
 117         RTL_GIGA_MAC_VER_08,
 118         RTL_GIGA_MAC_VER_09,
 119         RTL_GIGA_MAC_VER_10,
 120         RTL_GIGA_MAC_VER_11,
 121         RTL_GIGA_MAC_VER_12,
 122         RTL_GIGA_MAC_VER_13,
 123         RTL_GIGA_MAC_VER_14,
 124         RTL_GIGA_MAC_VER_15,
 125         RTL_GIGA_MAC_VER_16,
 126         RTL_GIGA_MAC_VER_17,
 127         RTL_GIGA_MAC_VER_18,
 128         RTL_GIGA_MAC_VER_19,
 129         RTL_GIGA_MAC_VER_20,
 130         RTL_GIGA_MAC_VER_21,
 131         RTL_GIGA_MAC_VER_22,
 132         RTL_GIGA_MAC_VER_23,
 133         RTL_GIGA_MAC_VER_24,
 134         RTL_GIGA_MAC_VER_25,
 135         RTL_GIGA_MAC_VER_26,
 136         RTL_GIGA_MAC_VER_27,
 137         RTL_GIGA_MAC_VER_28,
 138         RTL_GIGA_MAC_VER_29,
 139         RTL_GIGA_MAC_VER_30,
 140         RTL_GIGA_MAC_VER_31,
 141         RTL_GIGA_MAC_VER_32,
 142         RTL_GIGA_MAC_VER_33,
 143         RTL_GIGA_MAC_VER_34,
 144         RTL_GIGA_MAC_VER_35,
 145         RTL_GIGA_MAC_VER_36,
 146         RTL_GIGA_MAC_VER_37,
 147         RTL_GIGA_MAC_VER_38,
 148         RTL_GIGA_MAC_VER_39,
 149         RTL_GIGA_MAC_VER_40,
 150         RTL_GIGA_MAC_VER_41,
 151         RTL_GIGA_MAC_VER_42,
 152         RTL_GIGA_MAC_VER_43,
 153         RTL_GIGA_MAC_VER_44,
 154         RTL_GIGA_MAC_VER_45,
 155         RTL_GIGA_MAC_VER_46,
 156         RTL_GIGA_MAC_VER_47,
 157         RTL_GIGA_MAC_VER_48,
 158         RTL_GIGA_MAC_VER_49,
 159         RTL_GIGA_MAC_VER_50,
 160         RTL_GIGA_MAC_VER_51,
 161         RTL_GIGA_MAC_NONE   = 0xff,
 162 };
 163
 164 enum rtl_tx_desc_version {
 165         RTL_TD_0        = 0,
 166         RTL_TD_1        = 1,
 167 };
 168
 169 #define JUMBO_1K        ETH_DATA_LEN
 170 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 171 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 172 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 173 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 174
 175 #define _R(NAME,TD,FW,SZ,B) {   \
 176         .name = NAME,           \
 177         .txd_version = TD,      \
 178         .fw_name = FW,          \
 179         .jumbo_max = SZ,        \
 180         .jumbo_tx_csum = B      \
 181 }
 182
 183 static const struct {
 184         const char *name;
 185         enum rtl_tx_desc_version txd_version;
 186         const char *fw_name;
 187         u16 jumbo_max;
 188         bool jumbo_tx_csum;
 189 } rtl_chip_infos[] = {
 190         /* PCI devices. */
 191         [RTL_GIGA_MAC_VER_01] =
 192                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 193         [RTL_GIGA_MAC_VER_02] =
 194                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 195         [RTL_GIGA_MAC_VER_03] =
 196                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 197         [RTL_GIGA_MAC_VER_04] =
 198                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 199         [RTL_GIGA_MAC_VER_05] =
 200                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 201         [RTL_GIGA_MAC_VER_06] =
 202                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 203         /* PCI-E devices. */
 204         [RTL_GIGA_MAC_VER_07] =
 205                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 206         [RTL_GIGA_MAC_VER_08] =
 207                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 208         [RTL_GIGA_MAC_VER_09] =
 209                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 210         [RTL_GIGA_MAC_VER_10] =
 211                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 212         [RTL_GIGA_MAC_VER_11] =
 213                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 214         [RTL_GIGA_MAC_VER_12] =
 215                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 216         [RTL_GIGA_MAC_VER_13] =
 217                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 218         [RTL_GIGA_MAC_VER_14] =
 219                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 220         [RTL_GIGA_MAC_VER_15] =
 221                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 222         [RTL_GIGA_MAC_VER_16] =
 223                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 224         [RTL_GIGA_MAC_VER_17] =
 225                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 226         [RTL_GIGA_MAC_VER_18] =
 227                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 228         [RTL_GIGA_MAC_VER_19] =
 229                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 230         [RTL_GIGA_MAC_VER_20] =
 231                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 232         [RTL_GIGA_MAC_VER_21] =
 233                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 234         [RTL_GIGA_MAC_VER_22] =
 235                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 236         [RTL_GIGA_MAC_VER_23] =
 237                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 238         [RTL_GIGA_MAC_VER_24] =
 239                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 240         [RTL_GIGA_MAC_VER_25] =
 241                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_26] =
 244                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_27] =
 247                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 248         [RTL_GIGA_MAC_VER_28] =
 249                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 250         [RTL_GIGA_MAC_VER_29] =
 251                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 252                                                         JUMBO_1K, true),
 253         [RTL_GIGA_MAC_VER_30] =
 254                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 255                                                         JUMBO_1K, true),
 256         [RTL_GIGA_MAC_VER_31] =
 257                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 258         [RTL_GIGA_MAC_VER_32] =
 259                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 260                                                         JUMBO_9K, false),
 261         [RTL_GIGA_MAC_VER_33] =
 262                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 263                                                         JUMBO_9K, false),
 264         [RTL_GIGA_MAC_VER_34] =
 265                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 266                                                         JUMBO_9K, false),
 267         [RTL_GIGA_MAC_VER_35] =
 268                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 269                                                         JUMBO_9K, false),
 270         [RTL_GIGA_MAC_VER_36] =
 271                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 272                                                         JUMBO_9K, false),
 273         [RTL_GIGA_MAC_VER_37] =
 274                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 275                                                         JUMBO_1K, true),
 276         [RTL_GIGA_MAC_VER_38] =
 277                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 278                                                         JUMBO_9K, false),
 279         [RTL_GIGA_MAC_VER_39] =
 280                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 281                                                         JUMBO_1K, true),
 282         [RTL_GIGA_MAC_VER_40] =
 283                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 284                                                         JUMBO_9K, false),
 285         [RTL_GIGA_MAC_VER_41] =
 286                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 287         [RTL_GIGA_MAC_VER_42] =
 288                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 289                                                         JUMBO_9K, false),
 290         [RTL_GIGA_MAC_VER_43] =
 291                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 292                                                         JUMBO_1K, true),
 293         [RTL_GIGA_MAC_VER_44] =
 294                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
 295                                                         JUMBO_9K, false),
 296         [RTL_GIGA_MAC_VER_45] =
 297                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1,
 298                                                         JUMBO_9K, false),
 299         [RTL_GIGA_MAC_VER_46] =
 300                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2,
 301                                                         JUMBO_9K, false),
 302         [RTL_GIGA_MAC_VER_47] =
 303                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1,
 304                                                         JUMBO_1K, false),
 305         [RTL_GIGA_MAC_VER_48] =
 306                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2,
 307                                                         JUMBO_1K, false),
 308         [RTL_GIGA_MAC_VER_49] =
 309                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 310                                                         JUMBO_9K, false),
 311         [RTL_GIGA_MAC_VER_50] =
 312                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 313                                                         JUMBO_9K, false),
 314         [RTL_GIGA_MAC_VER_51] =
 315                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 316                                                         JUMBO_9K, false),
 317 };
 318 #undef _R
 319
 320 enum cfg_version {
 321         RTL_CFG_0 = 0x00,
 322         RTL_CFG_1,
 323         RTL_CFG_2
 324 };
 325
 326 static const struct pci_device_id rtl8169_pci_tbl[] = {
 327         { PCI_VDEVICE(REALTEK,  0x2502), RTL_CFG_1 },
 328         { PCI_VDEVICE(REALTEK,  0x2600), RTL_CFG_1 },
 329         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 330         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 331         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
 332         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 333         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 334         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 335         { PCI_VENDOR_ID_DLINK,                  0x4300,
 336                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 337         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 338         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 339         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 340         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 341         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 342                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 343         { 0x0001,                               0x8168,
 344                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 345         {0,},
 346 };
 347
 348 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 349
 350 static int rx_buf_sz = 16383;
 351 static int use_dac;
 352 static struct {
 353         u32 msg_enable;
 354 } debug = { -1 };
 355
 356 enum rtl_registers {
 357         MAC0            = 0,    /* Ethernet hardware address. */
 358         MAC4            = 4,
 359         MAR0            = 8,    /* Multicast filter. */
 360         CounterAddrLow          = 0x10,
 361         CounterAddrHigh         = 0x14,
 362         TxDescStartAddrLow      = 0x20,
 363         TxDescStartAddrHigh     = 0x24,
 364         TxHDescStartAddrLow     = 0x28,
 365         TxHDescStartAddrHigh    = 0x2c,
 366         FLASH           = 0x30,
 367         ERSR            = 0x36,
 368         ChipCmd         = 0x37,
 369         TxPoll          = 0x38,
 370         IntrMask        = 0x3c,
 371         IntrStatus      = 0x3e,
 372
 373         TxConfig        = 0x40,
 374 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 375 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 376
 377         RxConfig        = 0x44,
 378 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 379 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 380 #define RXCFG_FIFO_SHIFT                13
 381                                         /* No threshold before first PCI xfer */
 382 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 383 #define RX_EARLY_OFF                    (1 << 11)
 384 #define RXCFG_DMA_SHIFT                 8
 385                                         /* Unlimited maximum PCI burst. */
 386 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 387
 388         RxMissed        = 0x4c,
 389         Cfg9346         = 0x50,
 390         Config0         = 0x51,
 391         Config1         = 0x52,
 392         Config2         = 0x53,
 393 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 394
 395         Config3         = 0x54,
 396         Config4         = 0x55,
 397         Config5         = 0x56,
 398         MultiIntr       = 0x5c,
 399         PHYAR           = 0x60,
 400         PHYstatus       = 0x6c,
 401         RxMaxSize       = 0xda,
 402         CPlusCmd        = 0xe0,
 403         IntrMitigate    = 0xe2,
 404         RxDescAddrLow   = 0xe4,
 405         RxDescAddrHigh  = 0xe8,
 406         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 407
 408 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 409
 410         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 411
 412 #define TxPacketMax     (8064 >> 7)
 413 #define EarlySize       0x27
 414
 415         FuncEvent       = 0xf0,
 416         FuncEventMask   = 0xf4,
 417         FuncPresetState = 0xf8,
 418         IBCR0           = 0xf8,
 419         IBCR2           = 0xf9,
 420         IBIMR0          = 0xfa,
 421         IBISR0          = 0xfb,
 422         FuncForceEvent  = 0xfc,
 423 };
 424
 425 enum rtl8110_registers {
 426         TBICSR                  = 0x64,
 427         TBI_ANAR                = 0x68,
 428         TBI_LPAR                = 0x6a,
 429 };
 430
 431 enum rtl8168_8101_registers {
 432         CSIDR                   = 0x64,
 433         CSIAR                   = 0x68,
 434 #define CSIAR_FLAG                      0x80000000
 435 #define CSIAR_WRITE_CMD                 0x80000000
 436 #define CSIAR_BYTE_ENABLE               0x0f
 437 #define CSIAR_BYTE_ENABLE_SHIFT         12
 438 #define CSIAR_ADDR_MASK                 0x0fff
 439 #define CSIAR_FUNC_CARD                 0x00000000
 440 #define CSIAR_FUNC_SDIO                 0x00010000
 441 #define CSIAR_FUNC_NIC                  0x00020000
 442 #define CSIAR_FUNC_NIC2                 0x00010000
 443         PMCH                    = 0x6f,
 444         EPHYAR                  = 0x80,
 445 #define EPHYAR_FLAG                     0x80000000
 446 #define EPHYAR_WRITE_CMD                0x80000000
 447 #define EPHYAR_REG_MASK                 0x1f
 448 #define EPHYAR_REG_SHIFT                16
 449 #define EPHYAR_DATA_MASK                0xffff
 450         DLLPR                   = 0xd0,
 451 #define PFM_EN                          (1 << 6)
 452 #define TX_10M_PS_EN                    (1 << 7)
 453         DBG_REG                 = 0xd1,
 454 #define FIX_NAK_1                       (1 << 4)
 455 #define FIX_NAK_2                       (1 << 3)
 456         TWSI                    = 0xd2,
 457         MCU                     = 0xd3,
 458 #define NOW_IS_OOB                      (1 << 7)
 459 #define TX_EMPTY                        (1 << 5)
 460 #define RX_EMPTY                        (1 << 4)
 461 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 462 #define EN_NDP                          (1 << 3)
 463 #define EN_OOB_RESET                    (1 << 2)
 464 #define LINK_LIST_RDY                   (1 << 1)
 465         EFUSEAR                 = 0xdc,
 466 #define EFUSEAR_FLAG                    0x80000000
 467 #define EFUSEAR_WRITE_CMD               0x80000000
 468 #define EFUSEAR_READ_CMD                0x00000000
 469 #define EFUSEAR_REG_MASK                0x03ff
 470 #define EFUSEAR_REG_SHIFT               8
 471 #define EFUSEAR_DATA_MASK               0xff
 472         MISC_1                  = 0xf2,
 473 #define PFM_D3COLD_EN                   (1 << 6)
 474 };
 475
 476 enum rtl8168_registers {
 477         LED_FREQ                = 0x1a,
 478         EEE_LED                 = 0x1b,
 479         ERIDR                   = 0x70,
 480         ERIAR                   = 0x74,
 481 #define ERIAR_FLAG                      0x80000000
 482 #define ERIAR_WRITE_CMD                 0x80000000
 483 #define ERIAR_READ_CMD                  0x00000000
 484 #define ERIAR_ADDR_BYTE_ALIGN           4
 485 #define ERIAR_TYPE_SHIFT                16
 486 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 487 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 488 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 489 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 490 #define ERIAR_MASK_SHIFT                12
 491 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 492 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 493 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 494 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 495 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 496         EPHY_RXER_NUM           = 0x7c,
 497         OCPDR                   = 0xb0, /* OCP GPHY access */
 498 #define OCPDR_WRITE_CMD                 0x80000000
 499 #define OCPDR_READ_CMD                  0x00000000
 500 #define OCPDR_REG_MASK                  0x7f
 501 #define OCPDR_GPHY_REG_SHIFT            16
 502 #define OCPDR_DATA_MASK                 0xffff
 503         OCPAR                   = 0xb4,
 504 #define OCPAR_FLAG                      0x80000000
 505 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 506 #define OCPAR_GPHY_READ_CMD             0x0000f060
 507         GPHY_OCP                = 0xb8,
 508         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 509         MISC                    = 0xf0, /* 8168e only. */
 510 #define TXPLA_RST                       (1 << 29)
 511 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 512 #define PWM_EN                          (1 << 22)
 513 #define RXDV_GATED_EN                   (1 << 19)
 514 #define EARLY_TALLY_EN                  (1 << 16)
 515 };
 516
 517 enum rtl_register_content {
 518         /* InterruptStatusBits */
 519         SYSErr          = 0x8000,
 520         PCSTimeout      = 0x4000,
 521         SWInt           = 0x0100,
 522         TxDescUnavail   = 0x0080,
 523         RxFIFOOver      = 0x0040,
 524         LinkChg         = 0x0020,
 525         RxOverflow      = 0x0010,
 526         TxErr           = 0x0008,
 527         TxOK            = 0x0004,
 528         RxErr           = 0x0002,
 529         RxOK            = 0x0001,
 530
 531         /* RxStatusDesc */
 532         RxBOVF  = (1 << 24),
 533         RxFOVF  = (1 << 23),
 534         RxRWT   = (1 << 22),
 535         RxRES   = (1 << 21),
 536         RxRUNT  = (1 << 20),
 537         RxCRC   = (1 << 19),
 538
 539         /* ChipCmdBits */
 540         StopReq         = 0x80,
 541         CmdReset        = 0x10,
 542         CmdRxEnb        = 0x08,
 543         CmdTxEnb        = 0x04,
 544         RxBufEmpty      = 0x01,
 545
 546         /* TXPoll register p.5 */
 547         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 548         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 549         FSWInt          = 0x01,         /* Forced software interrupt */
 550
 551         /* Cfg9346Bits */
 552         Cfg9346_Lock    = 0x00,
 553         Cfg9346_Unlock  = 0xc0,
 554
 555         /* rx_mode_bits */
 556         AcceptErr       = 0x20,
 557         AcceptRunt      = 0x10,
 558         AcceptBroadcast = 0x08,
 559         AcceptMulticast = 0x04,
 560         AcceptMyPhys    = 0x02,
 561         AcceptAllPhys   = 0x01,
 562 #define RX_CONFIG_ACCEPT_MASK           0x3f
 563
 564         /* TxConfigBits */
 565         TxInterFrameGapShift = 24,
 566         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 567
 568         /* Config1 register p.24 */
 569         LEDS1           = (1 << 7),
 570         LEDS0           = (1 << 6),
 571         Speed_down      = (1 << 4),
 572         MEMMAP          = (1 << 3),
 573         IOMAP           = (1 << 2),
 574         VPD             = (1 << 1),
 575         PMEnable        = (1 << 0),     /* Power Management Enable */
 576
 577         /* Config2 register p. 25 */
 578         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 579         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 580         PCI_Clock_66MHz = 0x01,
 581         PCI_Clock_33MHz = 0x00,
 582
 583         /* Config3 register p.25 */
 584         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 585         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 586         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 587         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 588         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 589
 590         /* Config4 register */
 591         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 592
 593         /* Config5 register p.27 */
 594         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 595         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 596         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 597         Spi_en          = (1 << 3),
 598         LanWake         = (1 << 1),     /* LanWake enable/disable */
 599         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 600         ASPM_en         = (1 << 0),     /* ASPM enable */
 601
 602         /* TBICSR p.28 */
 603         TBIReset        = 0x80000000,
 604         TBILoopback     = 0x40000000,
 605         TBINwEnable     = 0x20000000,
 606         TBINwRestart    = 0x10000000,
 607         TBILinkOk       = 0x02000000,
 608         TBINwComplete   = 0x01000000,
 609
 610         /* CPlusCmd p.31 */
 611         EnableBist      = (1 << 15),    // 8168 8101
 612         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 613         Normal_mode     = (1 << 13),    // unused
 614         Force_half_dup  = (1 << 12),    // 8168 8101
 615         Force_rxflow_en = (1 << 11),    // 8168 8101
 616         Force_txflow_en = (1 << 10),    // 8168 8101
 617         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 618         ASF             = (1 << 8),     // 8168 8101
 619         PktCntrDisable  = (1 << 7),     // 8168 8101
 620         Mac_dbgo_sel    = 0x001c,       // 8168
 621         RxVlan          = (1 << 6),
 622         RxChkSum        = (1 << 5),
 623         PCIDAC          = (1 << 4),
 624         PCIMulRW        = (1 << 3),
 625         INTT_0          = 0x0000,       // 8168
 626         INTT_1          = 0x0001,       // 8168
 627         INTT_2          = 0x0002,       // 8168
 628         INTT_3          = 0x0003,       // 8168
 629
 630         /* rtl8169_PHYstatus */
 631         TBI_Enable      = 0x80,
 632         TxFlowCtrl      = 0x40,
 633         RxFlowCtrl      = 0x20,
 634         _1000bpsF       = 0x10,
 635         _100bps         = 0x08,
 636         _10bps          = 0x04,
 637         LinkStatus      = 0x02,
 638         FullDup         = 0x01,
 639
 640         /* _TBICSRBit */
 641         TBILinkOK       = 0x02000000,
 642
 643         /* ResetCounterCommand */
 644         CounterReset    = 0x1,
 645
 646         /* DumpCounterCommand */
 647         CounterDump     = 0x8,
 648
 649         /* magic enable v2 */
 650         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 651 };
 652
 653 enum rtl_desc_bit {
 654         /* First doubleword. */
 655         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 656         RingEnd         = (1 << 30), /* End of descriptor ring */
 657         FirstFrag       = (1 << 29), /* First segment of a packet */
 658         LastFrag        = (1 << 28), /* Final segment of a packet */
 659 };
 660
 661 /* Generic case. */
 662 enum rtl_tx_desc_bit {
 663         /* First doubleword. */
 664         TD_LSO          = (1 << 27),            /* Large Send Offload */
 665 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 666
 667         /* Second doubleword. */
 668         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 669 };
 670
 671 /* 8169, 8168b and 810x except 8102e. */
 672 enum rtl_tx_desc_bit_0 {
 673         /* First doubleword. */
 674 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 675         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 676         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 677         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 678 };
 679
 680 /* 8102e, 8168c and beyond. */
 681 enum rtl_tx_desc_bit_1 {
 682         /* First doubleword. */
 683         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 684         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 685 #define GTTCPHO_SHIFT                   18
 686 #define GTTCPHO_MAX                     0x7fU
 687
 688         /* Second doubleword. */
 689 #define TCPHO_SHIFT                     18
 690 #define TCPHO_MAX                       0x3ffU
 691 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 692         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 693         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 694         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 695         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 696 };
 697
 698 enum rtl_rx_desc_bit {
 699         /* Rx private */
 700         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 701         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 702
 703 #define RxProtoUDP      (PID1)
 704 #define RxProtoTCP      (PID0)
 705 #define RxProtoIP       (PID1 | PID0)
 706 #define RxProtoMask     RxProtoIP
 707
 708         IPFail          = (1 << 16), /* IP checksum failed */
 709         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 710         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 711         RxVlanTag       = (1 << 16), /* VLAN tag available */
 712 };
 713
 714 #define RsvdMask        0x3fffc000
 715
 716 struct TxDesc {
 717         __le32 opts1;
 718         __le32 opts2;
 719         __le64 addr;
 720 };
 721
 722 struct RxDesc {
 723         __le32 opts1;
 724         __le32 opts2;
 725         __le64 addr;
 726 };
 727
 728 struct ring_info {
 729         struct sk_buff  *skb;
 730         u32             len;
 731         u8              __pad[sizeof(void *) - sizeof(u32)];
 732 };
 733
 734 enum features {
 735         RTL_FEATURE_WOL         = (1 << 0),
 736         RTL_FEATURE_MSI         = (1 << 1),
 737         RTL_FEATURE_GMII        = (1 << 2),
 738 };
 739
 740 struct rtl8169_counters {
 741         __le64  tx_packets;
 742         __le64  rx_packets;
 743         __le64  tx_errors;
 744         __le32  rx_errors;
 745         __le16  rx_missed;
 746         __le16  align_errors;
 747         __le32  tx_one_collision;
 748         __le32  tx_multi_collision;
 749         __le64  rx_unicast;
 750         __le64  rx_broadcast;
 751         __le32  rx_multicast;
 752         __le16  tx_aborted;
 753         __le16  tx_underun;
 754 };
 755
 756 struct rtl8169_tc_offsets {
 757         bool    inited;
 758         __le64  tx_errors;
 759         __le32  tx_multi_collision;
 760         __le16  tx_aborted;
 761 };
 762
 763 enum rtl_flag {
 764         RTL_FLAG_TASK_ENABLED = 0,
 765         RTL_FLAG_TASK_SLOW_PENDING,
 766         RTL_FLAG_TASK_RESET_PENDING,
 767         RTL_FLAG_TASK_PHY_PENDING,
 768         RTL_FLAG_MAX
 769 };
 770
 771 struct rtl8169_stats {
 772         u64                     packets;
 773         u64                     bytes;
 774         struct u64_stats_sync   syncp;
 775 };
 776
 777 struct rtl8169_private {
 778         void __iomem *mmio_addr;        /* memory map physical address */
 779         struct pci_dev *pci_dev;
 780         struct net_device *dev;
 781         struct napi_struct napi;
 782         u32 msg_enable;
 783         u16 txd_version;
 784         u16 mac_version;
 785         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 786         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 787         u32 dirty_tx;
 788         struct rtl8169_stats rx_stats;
 789         struct rtl8169_stats tx_stats;
 790         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 791         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 792         dma_addr_t TxPhyAddr;
 793         dma_addr_t RxPhyAddr;
 794         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 795         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 796         struct timer_list timer;
 797         u16 cp_cmd;
 798
 799         u16 event_slow;
 800
 801         struct mdio_ops {
 802                 void (*write)(struct rtl8169_private *, int, int);
 803                 int (*read)(struct rtl8169_private *, int);
 804         } mdio_ops;
 805
 806         struct pll_power_ops {
 807                 void (*down)(struct rtl8169_private *);
 808                 void (*up)(struct rtl8169_private *);
 809         } pll_power_ops;
 810
 811         struct jumbo_ops {
 812                 void (*enable)(struct rtl8169_private *);
 813                 void (*disable)(struct rtl8169_private *);
 814         } jumbo_ops;
 815
 816         struct csi_ops {
 817                 void (*write)(struct rtl8169_private *, int, int);
 818                 u32 (*read)(struct rtl8169_private *, int);
 819         } csi_ops;
 820
 821         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 822         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 823         void (*phy_reset_enable)(struct rtl8169_private *tp);
 824         void (*hw_start)(struct net_device *);
 825         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 826         unsigned int (*link_ok)(void __iomem *);
 827         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 828         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 829
 830         struct {
 831                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 832                 struct mutex mutex;
 833                 struct work_struct work;
 834         } wk;
 835
 836         unsigned features;
 837
 838         struct mii_if_info mii;
 839         dma_addr_t counters_phys_addr;
 840         struct rtl8169_counters *counters;
 841         struct rtl8169_tc_offsets tc_offset;
 842         u32 saved_wolopts;
 843         u32 opts1_mask;
 844
 845         struct rtl_fw {
 846                 const struct firmware *fw;
 847
 848 #define RTL_VER_SIZE            32
 849
 850                 char version[RTL_VER_SIZE];
 851
 852                 struct rtl_fw_phy_action {
 853                         __le32 *code;
 854                         size_t size;
 855                 } phy_action;
 856         } *rtl_fw;
 857 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 858
 859         u32 ocp_base;
 860 };
 861
 862 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 863 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 864 module_param(use_dac, int, 0);
 865 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 866 module_param_named(debug, debug.msg_enable, int, 0);
 867 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 868 MODULE_LICENSE("GPL");
 869 MODULE_VERSION(RTL8169_VERSION);
 870 /*(DEBLOBBED)*/
 871
 872 static void rtl_lock_work(struct rtl8169_private *tp)
 873 {
 874         mutex_lock(&tp->wk.mutex);
 875 }
 876
 877 static void rtl_unlock_work(struct rtl8169_private *tp)
 878 {
 879         mutex_unlock(&tp->wk.mutex);
 880 }
 881
 882 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 883 {
 884         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 885                                            PCI_EXP_DEVCTL_READRQ, force);
 886 }
 887
 888 struct rtl_cond {
 889         bool (*check)(struct rtl8169_private *);
 890         const char *msg;
 891 };
 892
 893 static void rtl_udelay(unsigned int d)
 894 {
 895         udelay(d);
 896 }
 897
 898 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 899                           void (*delay)(unsigned int), unsigned int d, int n,
 900                           bool high)
 901 {
 902         int i;
 903
 904         for (i = 0; i < n; i++) {
 905                 delay(d);
 906                 if (c->check(tp) == high)
 907                         return true;
 908         }
 909         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 910                   c->msg, !high, n, d);
 911         return false;
 912 }
 913
 914 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 915                                       const struct rtl_cond *c,
 916                                       unsigned int d, int n)
 917 {
 918         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 919 }
 920
 921 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 922                                      const struct rtl_cond *c,
 923                                      unsigned int d, int n)
 924 {
 925         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 926 }
 927
 928 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 929                                       const struct rtl_cond *c,
 930                                       unsigned int d, int n)
 931 {
 932         return rtl_loop_wait(tp, c, msleep, d, n, true);
 933 }
 934
 935 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 936                                      const struct rtl_cond *c,
 937                                      unsigned int d, int n)
 938 {
 939         return rtl_loop_wait(tp, c, msleep, d, n, false);
 940 }
 941
 942 #define DECLARE_RTL_COND(name)                          \
 943 static bool name ## _check(struct rtl8169_private *);   \
 944                                                         \
 945 static const struct rtl_cond name = {                   \
 946         .check  = name ## _check,                       \
 947         .msg    = #name                                 \
 948 };                                                      \
 949                                                         \
 950 static bool name ## _check(struct rtl8169_private *tp)
 951
 952 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 953 {
 954         if (reg & 0xffff0001) {
 955                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 956                 return true;
 957         }
 958         return false;
 959 }
 960
 961 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 962 {
 963         void __iomem *ioaddr = tp->mmio_addr;
 964
 965         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
 966 }
 967
 968 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 969 {
 970         void __iomem *ioaddr = tp->mmio_addr;
 971
 972         if (rtl_ocp_reg_failure(tp, reg))
 973                 return;
 974
 975         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 976
 977         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 978 }
 979
 980 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 981 {
 982         void __iomem *ioaddr = tp->mmio_addr;
 983
 984         if (rtl_ocp_reg_failure(tp, reg))
 985                 return 0;
 986
 987         RTL_W32(GPHY_OCP, reg << 15);
 988
 989         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 990                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
 991 }
 992
 993 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 994 {
 995         void __iomem *ioaddr = tp->mmio_addr;
 996
 997         if (rtl_ocp_reg_failure(tp, reg))
 998                 return;
 999
1000         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1001 }
1002
1003 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1004 {
1005         void __iomem *ioaddr = tp->mmio_addr;
1006
1007         if (rtl_ocp_reg_failure(tp, reg))
1008                 return 0;
1009
1010         RTL_W32(OCPDR, reg << 15);
1011
1012         return RTL_R32(OCPDR);
1013 }
1014
1015 #define OCP_STD_PHY_BASE        0xa400
1016
1017 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1018 {
1019         if (reg == 0x1f) {
1020                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1021                 return;
1022         }
1023
1024         if (tp->ocp_base != OCP_STD_PHY_BASE)
1025                 reg -= 0x10;
1026
1027         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1028 }
1029
1030 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1031 {
1032         if (tp->ocp_base != OCP_STD_PHY_BASE)
1033                 reg -= 0x10;
1034
1035         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1036 }
1037
1038 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1039 {
1040         if (reg == 0x1f) {
1041                 tp->ocp_base = value << 4;
1042                 return;
1043         }
1044
1045         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1046 }
1047
1048 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1049 {
1050         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1051 }
1052
1053 DECLARE_RTL_COND(rtl_phyar_cond)
1054 {
1055         void __iomem *ioaddr = tp->mmio_addr;
1056
1057         return RTL_R32(PHYAR) & 0x80000000;
1058 }
1059
1060 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1061 {
1062         void __iomem *ioaddr = tp->mmio_addr;
1063
1064         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1065
1066         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1067         /*
1068          * According to hardware specs a 20us delay is required after write
1069          * complete indication, but before sending next command.
1070          */
1071         udelay(20);
1072 }
1073
1074 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1075 {
1076         void __iomem *ioaddr = tp->mmio_addr;
1077         int value;
1078
1079         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1080
1081         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1082                 RTL_R32(PHYAR) & 0xffff : ~0;
1083
1084         /*
1085          * According to hardware specs a 20us delay is required after read
1086          * complete indication, but before sending next command.
1087          */
1088         udelay(20);
1089
1090         return value;
1091 }
1092
1093 DECLARE_RTL_COND(rtl_ocpar_cond)
1094 {
1095         void __iomem *ioaddr = tp->mmio_addr;
1096
1097         return RTL_R32(OCPAR) & OCPAR_FLAG;
1098 }
1099
1100 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1101 {
1102         void __iomem *ioaddr = tp->mmio_addr;
1103
1104         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1105         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1106         RTL_W32(EPHY_RXER_NUM, 0);
1107
1108         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1109 }
1110
1111 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1112 {
1113         r8168dp_1_mdio_access(tp, reg,
1114                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1115 }
1116
1117 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1118 {
1119         void __iomem *ioaddr = tp->mmio_addr;
1120
1121         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1122
1123         mdelay(1);
1124         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1125         RTL_W32(EPHY_RXER_NUM, 0);
1126
1127         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1128                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1129 }
1130
1131 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1132
1133 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1134 {
1135         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1136 }
1137
1138 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1139 {
1140         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1141 }
1142
1143 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1144 {
1145         void __iomem *ioaddr = tp->mmio_addr;
1146
1147         r8168dp_2_mdio_start(ioaddr);
1148
1149         r8169_mdio_write(tp, reg, value);
1150
1151         r8168dp_2_mdio_stop(ioaddr);
1152 }
1153
1154 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1155 {
1156         void __iomem *ioaddr = tp->mmio_addr;
1157         int value;
1158
1159         r8168dp_2_mdio_start(ioaddr);
1160
1161         value = r8169_mdio_read(tp, reg);
1162
1163         r8168dp_2_mdio_stop(ioaddr);
1164
1165         return value;
1166 }
1167
1168 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1169 {
1170         tp->mdio_ops.write(tp, location, val);
1171 }
1172
1173 static int rtl_readphy(struct rtl8169_private *tp, int location)
1174 {
1175         return tp->mdio_ops.read(tp, location);
1176 }
1177
1178 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1179 {
1180         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1181 }
1182
1183 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1184 {
1185         int val;
1186
1187         val = rtl_readphy(tp, reg_addr);
1188         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1189 }
1190
1191 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1192                            int val)
1193 {
1194         struct rtl8169_private *tp = netdev_priv(dev);
1195
1196         rtl_writephy(tp, location, val);
1197 }
1198
1199 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1200 {
1201         struct rtl8169_private *tp = netdev_priv(dev);
1202
1203         return rtl_readphy(tp, location);
1204 }
1205
1206 DECLARE_RTL_COND(rtl_ephyar_cond)
1207 {
1208         void __iomem *ioaddr = tp->mmio_addr;
1209
1210         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1211 }
1212
1213 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1214 {
1215         void __iomem *ioaddr = tp->mmio_addr;
1216
1217         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1218                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1219
1220         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1221
1222         udelay(10);
1223 }
1224
1225 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1226 {
1227         void __iomem *ioaddr = tp->mmio_addr;
1228
1229         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1230
1231         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1232                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1233 }
1234
1235 DECLARE_RTL_COND(rtl_eriar_cond)
1236 {
1237         void __iomem *ioaddr = tp->mmio_addr;
1238
1239         return RTL_R32(ERIAR) & ERIAR_FLAG;
1240 }
1241
1242 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1243                           u32 val, int type)
1244 {
1245         void __iomem *ioaddr = tp->mmio_addr;
1246
1247         BUG_ON((addr & 3) || (mask == 0));
1248         RTL_W32(ERIDR, val);
1249         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1250
1251         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1252 }
1253
1254 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1255 {
1256         void __iomem *ioaddr = tp->mmio_addr;
1257
1258         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1259
1260         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1261                 RTL_R32(ERIDR) : ~0;
1262 }
1263
1264 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1265                          u32 m, int type)
1266 {
1267         u32 val;
1268
1269         val = rtl_eri_read(tp, addr, type);
1270         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1271 }
1272
1273 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1274 {
1275         void __iomem *ioaddr = tp->mmio_addr;
1276
1277         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1278         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1279                 RTL_R32(OCPDR) : ~0;
1280 }
1281
1282 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1283 {
1284         return rtl_eri_read(tp, reg, ERIAR_OOB);
1285 }
1286
1287 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1288 {
1289         switch (tp->mac_version) {
1290         case RTL_GIGA_MAC_VER_27:
1291         case RTL_GIGA_MAC_VER_28:
1292         case RTL_GIGA_MAC_VER_31:
1293                 return r8168dp_ocp_read(tp, mask, reg);
1294         case RTL_GIGA_MAC_VER_49:
1295         case RTL_GIGA_MAC_VER_50:
1296         case RTL_GIGA_MAC_VER_51:
1297                 return r8168ep_ocp_read(tp, mask, reg);
1298         default:
1299                 BUG();
1300                 return ~0;
1301         }
1302 }
1303
1304 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1305                               u32 data)
1306 {
1307         void __iomem *ioaddr = tp->mmio_addr;
1308
1309         RTL_W32(OCPDR, data);
1310         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1311         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1312 }
1313
1314 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1315                               u32 data)
1316 {
1317         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1318                       data, ERIAR_OOB);
1319 }
1320
1321 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1322 {
1323         switch (tp->mac_version) {
1324         case RTL_GIGA_MAC_VER_27:
1325         case RTL_GIGA_MAC_VER_28:
1326         case RTL_GIGA_MAC_VER_31:
1327                 r8168dp_ocp_write(tp, mask, reg, data);
1328                 break;
1329         case RTL_GIGA_MAC_VER_49:
1330         case RTL_GIGA_MAC_VER_50:
1331         case RTL_GIGA_MAC_VER_51:
1332                 r8168ep_ocp_write(tp, mask, reg, data);
1333                 break;
1334         default:
1335                 BUG();
1336                 break;
1337         }
1338 }
1339
1340 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1341 {
1342         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1343
1344         ocp_write(tp, 0x1, 0x30, 0x00000001);
1345 }
1346
1347 #define OOB_CMD_RESET           0x00
1348 #define OOB_CMD_DRIVER_START    0x05
1349 #define OOB_CMD_DRIVER_STOP     0x06
1350
1351 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1352 {
1353         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1354 }
1355
1356 DECLARE_RTL_COND(rtl_ocp_read_cond)
1357 {
1358         u16 reg;
1359
1360         reg = rtl8168_get_ocp_reg(tp);
1361
1362         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1363 }
1364
1365 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1366 {
1367         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1368 }
1369
1370 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1371 {
1372         void __iomem *ioaddr = tp->mmio_addr;
1373
1374         return RTL_R8(IBISR0) & 0x20;
1375 }
1376
1377 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1378 {
1379         void __iomem *ioaddr = tp->mmio_addr;
1380
1381         RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1382         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1383         RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1384         RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1385 }
1386
1387 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1388 {
1389         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1390         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1391 }
1392
1393 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1394 {
1395         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1396         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1397         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1398 }
1399
1400 static void rtl8168_driver_start(struct rtl8169_private *tp)
1401 {
1402         switch (tp->mac_version) {
1403         case RTL_GIGA_MAC_VER_27:
1404         case RTL_GIGA_MAC_VER_28:
1405         case RTL_GIGA_MAC_VER_31:
1406                 rtl8168dp_driver_start(tp);
1407                 break;
1408         case RTL_GIGA_MAC_VER_49:
1409         case RTL_GIGA_MAC_VER_50:
1410         case RTL_GIGA_MAC_VER_51:
1411                 rtl8168ep_driver_start(tp);
1412                 break;
1413         default:
1414                 BUG();
1415                 break;
1416         }
1417 }
1418
1419 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1420 {
1421         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1422         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1423 }
1424
1425 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1426 {
1427         rtl8168ep_stop_cmac(tp);
1428         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1429         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1430         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1431 }
1432
1433 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1434 {
1435         switch (tp->mac_version) {
1436         case RTL_GIGA_MAC_VER_27:
1437         case RTL_GIGA_MAC_VER_28:
1438         case RTL_GIGA_MAC_VER_31:
1439                 rtl8168dp_driver_stop(tp);
1440                 break;
1441         case RTL_GIGA_MAC_VER_49:
1442         case RTL_GIGA_MAC_VER_50:
1443         case RTL_GIGA_MAC_VER_51:
1444                 rtl8168ep_driver_stop(tp);
1445                 break;
1446         default:
1447                 BUG();
1448                 break;
1449         }
1450 }
1451
1452 static int r8168dp_check_dash(struct rtl8169_private *tp)
1453 {
1454         u16 reg = rtl8168_get_ocp_reg(tp);
1455
1456         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1457 }
1458
1459 static int r8168ep_check_dash(struct rtl8169_private *tp)
1460 {
1461         return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1462 }
1463
1464 static int r8168_check_dash(struct rtl8169_private *tp)
1465 {
1466         switch (tp->mac_version) {
1467         case RTL_GIGA_MAC_VER_27:
1468         case RTL_GIGA_MAC_VER_28:
1469         case RTL_GIGA_MAC_VER_31:
1470                 return r8168dp_check_dash(tp);
1471         case RTL_GIGA_MAC_VER_49:
1472         case RTL_GIGA_MAC_VER_50:
1473         case RTL_GIGA_MAC_VER_51:
1474                 return r8168ep_check_dash(tp);
1475         default:
1476                 return 0;
1477         }
1478 }
1479
1480 struct exgmac_reg {
1481         u16 addr;
1482         u16 mask;
1483         u32 val;
1484 };
1485
1486 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1487                                    const struct exgmac_reg *r, int len)
1488 {
1489         while (len-- > 0) {
1490                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1491                 r++;
1492         }
1493 }
1494
1495 DECLARE_RTL_COND(rtl_efusear_cond)
1496 {
1497         void __iomem *ioaddr = tp->mmio_addr;
1498
1499         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1500 }
1501
1502 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1503 {
1504         void __iomem *ioaddr = tp->mmio_addr;
1505
1506         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1507
1508         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1509                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1510 }
1511
1512 static u16 rtl_get_events(struct rtl8169_private *tp)
1513 {
1514         void __iomem *ioaddr = tp->mmio_addr;
1515
1516         return RTL_R16(IntrStatus);
1517 }
1518
1519 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1520 {
1521         void __iomem *ioaddr = tp->mmio_addr;
1522
1523         RTL_W16(IntrStatus, bits);
1524         mmiowb();
1525 }
1526
1527 static void rtl_irq_disable(struct rtl8169_private *tp)
1528 {
1529         void __iomem *ioaddr = tp->mmio_addr;
1530
1531         RTL_W16(IntrMask, 0);
1532         mmiowb();
1533 }
1534
1535 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1536 {
1537         void __iomem *ioaddr = tp->mmio_addr;
1538
1539         RTL_W16(IntrMask, bits);
1540 }
1541
1542 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1543 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1544 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1545
1546 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1547 {
1548         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1549 }
1550
1551 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1552 {
1553         void __iomem *ioaddr = tp->mmio_addr;
1554
1555         rtl_irq_disable(tp);
1556         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1557         RTL_R8(ChipCmd);
1558 }
1559
1560 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1561 {
1562         void __iomem *ioaddr = tp->mmio_addr;
1563
1564         return RTL_R32(TBICSR) & TBIReset;
1565 }
1566
1567 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1568 {
1569         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1570 }
1571
1572 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1573 {
1574         return RTL_R32(TBICSR) & TBILinkOk;
1575 }
1576
1577 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1578 {
1579         return RTL_R8(PHYstatus) & LinkStatus;
1580 }
1581
1582 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1583 {
1584         void __iomem *ioaddr = tp->mmio_addr;
1585
1586         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1587 }
1588
1589 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1590 {
1591         unsigned int val;
1592
1593         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1594         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1595 }
1596
1597 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1598 {
1599         void __iomem *ioaddr = tp->mmio_addr;
1600         struct net_device *dev = tp->dev;
1601
1602         if (!netif_running(dev))
1603                 return;
1604
1605         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1606             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1607                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1608                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1609                                       ERIAR_EXGMAC);
1610                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1611                                       ERIAR_EXGMAC);
1612                 } else if (RTL_R8(PHYstatus) & _100bps) {
1613                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1614                                       ERIAR_EXGMAC);
1615                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1616                                       ERIAR_EXGMAC);
1617                 } else {
1618                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1619                                       ERIAR_EXGMAC);
1620                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1621                                       ERIAR_EXGMAC);
1622                 }
1623                 /* Reset packet filter */
1624                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1625                              ERIAR_EXGMAC);
1626                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1627                              ERIAR_EXGMAC);
1628         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1629                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1630                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1631                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1632                                       ERIAR_EXGMAC);
1633                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1634                                       ERIAR_EXGMAC);
1635                 } else {
1636                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1637                                       ERIAR_EXGMAC);
1638                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1639                                       ERIAR_EXGMAC);
1640                 }
1641         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1642                 if (RTL_R8(PHYstatus) & _10bps) {
1643                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1644                                       ERIAR_EXGMAC);
1645                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1646                                       ERIAR_EXGMAC);
1647                 } else {
1648                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1649                                       ERIAR_EXGMAC);
1650                 }
1651         }
1652 }
1653
1654 static void __rtl8169_check_link_status(struct net_device *dev,
1655                                         struct rtl8169_private *tp,
1656                                         void __iomem *ioaddr, bool pm)
1657 {
1658         if (tp->link_ok(ioaddr)) {
1659                 rtl_link_chg_patch(tp);
1660                 /* This is to cancel a scheduled suspend if there's one. */
1661                 if (pm)
1662                         pm_request_resume(&tp->pci_dev->dev);
1663                 netif_carrier_on(dev);
1664                 if (net_ratelimit())
1665                         netif_info(tp, ifup, dev, "link up\n");
1666         } else {
1667                 netif_carrier_off(dev);
1668                 netif_info(tp, ifdown, dev, "link down\n");
1669                 if (pm)
1670                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1671         }
1672 }
1673
1674 static void rtl8169_check_link_status(struct net_device *dev,
1675                                       struct rtl8169_private *tp,
1676                                       void __iomem *ioaddr)
1677 {
1678         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1679 }
1680
1681 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1682
1683 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1684 {
1685         void __iomem *ioaddr = tp->mmio_addr;
1686         u8 options;
1687         u32 wolopts = 0;
1688
1689         options = RTL_R8(Config1);
1690         if (!(options & PMEnable))
1691                 return 0;
1692
1693         options = RTL_R8(Config3);
1694         if (options & LinkUp)
1695                 wolopts |= WAKE_PHY;
1696         switch (tp->mac_version) {
1697         case RTL_GIGA_MAC_VER_34:
1698         case RTL_GIGA_MAC_VER_35:
1699         case RTL_GIGA_MAC_VER_36:
1700         case RTL_GIGA_MAC_VER_37:
1701         case RTL_GIGA_MAC_VER_38:
1702         case RTL_GIGA_MAC_VER_40:
1703         case RTL_GIGA_MAC_VER_41:
1704         case RTL_GIGA_MAC_VER_42:
1705         case RTL_GIGA_MAC_VER_43:
1706         case RTL_GIGA_MAC_VER_44:
1707         case RTL_GIGA_MAC_VER_45:
1708         case RTL_GIGA_MAC_VER_46:
1709         case RTL_GIGA_MAC_VER_47:
1710         case RTL_GIGA_MAC_VER_48:
1711         case RTL_GIGA_MAC_VER_49:
1712         case RTL_GIGA_MAC_VER_50:
1713         case RTL_GIGA_MAC_VER_51:
1714                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1715                         wolopts |= WAKE_MAGIC;
1716                 break;
1717         default:
1718                 if (options & MagicPacket)
1719                         wolopts |= WAKE_MAGIC;
1720                 break;
1721         }
1722
1723         options = RTL_R8(Config5);
1724         if (options & UWF)
1725                 wolopts |= WAKE_UCAST;
1726         if (options & BWF)
1727                 wolopts |= WAKE_BCAST;
1728         if (options & MWF)
1729                 wolopts |= WAKE_MCAST;
1730
1731         return wolopts;
1732 }
1733
1734 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1735 {
1736         struct rtl8169_private *tp = netdev_priv(dev);
1737
1738         rtl_lock_work(tp);
1739
1740         wol->supported = WAKE_ANY;
1741         wol->wolopts = __rtl8169_get_wol(tp);
1742
1743         rtl_unlock_work(tp);
1744 }
1745
1746 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1747 {
1748         void __iomem *ioaddr = tp->mmio_addr;
1749         unsigned int i, tmp;
1750         static const struct {
1751                 u32 opt;
1752                 u16 reg;
1753                 u8  mask;
1754         } cfg[] = {
1755                 { WAKE_PHY,   Config3, LinkUp },
1756                 { WAKE_UCAST, Config5, UWF },
1757                 { WAKE_BCAST, Config5, BWF },
1758                 { WAKE_MCAST, Config5, MWF },
1759                 { WAKE_ANY,   Config5, LanWake },
1760                 { WAKE_MAGIC, Config3, MagicPacket }
1761         };
1762         u8 options;
1763
1764         RTL_W8(Cfg9346, Cfg9346_Unlock);
1765
1766         switch (tp->mac_version) {
1767         case RTL_GIGA_MAC_VER_34:
1768         case RTL_GIGA_MAC_VER_35:
1769         case RTL_GIGA_MAC_VER_36:
1770         case RTL_GIGA_MAC_VER_37:
1771         case RTL_GIGA_MAC_VER_38:
1772         case RTL_GIGA_MAC_VER_40:
1773         case RTL_GIGA_MAC_VER_41:
1774         case RTL_GIGA_MAC_VER_42:
1775         case RTL_GIGA_MAC_VER_43:
1776         case RTL_GIGA_MAC_VER_44:
1777         case RTL_GIGA_MAC_VER_45:
1778         case RTL_GIGA_MAC_VER_46:
1779         case RTL_GIGA_MAC_VER_47:
1780         case RTL_GIGA_MAC_VER_48:
1781         case RTL_GIGA_MAC_VER_49:
1782         case RTL_GIGA_MAC_VER_50:
1783         case RTL_GIGA_MAC_VER_51:
1784                 tmp = ARRAY_SIZE(cfg) - 1;
1785                 if (wolopts & WAKE_MAGIC)
1786                         rtl_w0w1_eri(tp,
1787                                      0x0dc,
1788                                      ERIAR_MASK_0100,
1789                                      MagicPacket_v2,
1790                                      0x0000,
1791                                      ERIAR_EXGMAC);
1792                 else
1793                         rtl_w0w1_eri(tp,
1794                                      0x0dc,
1795                                      ERIAR_MASK_0100,
1796                                      0x0000,
1797                                      MagicPacket_v2,
1798                                      ERIAR_EXGMAC);
1799                 break;
1800         default:
1801                 tmp = ARRAY_SIZE(cfg);
1802                 break;
1803         }
1804
1805         for (i = 0; i < tmp; i++) {
1806                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1807                 if (wolopts & cfg[i].opt)
1808                         options |= cfg[i].mask;
1809                 RTL_W8(cfg[i].reg, options);
1810         }
1811
1812         switch (tp->mac_version) {
1813         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1814                 options = RTL_R8(Config1) & ~PMEnable;
1815                 if (wolopts)
1816                         options |= PMEnable;
1817                 RTL_W8(Config1, options);
1818                 break;
1819         default:
1820                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1821                 if (wolopts)
1822                         options |= PME_SIGNAL;
1823                 RTL_W8(Config2, options);
1824                 break;
1825         }
1826
1827         RTL_W8(Cfg9346, Cfg9346_Lock);
1828 }
1829
1830 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1831 {
1832         struct rtl8169_private *tp = netdev_priv(dev);
1833
1834         rtl_lock_work(tp);
1835
1836         if (wol->wolopts)
1837                 tp->features |= RTL_FEATURE_WOL;
1838         else
1839                 tp->features &= ~RTL_FEATURE_WOL;
1840         __rtl8169_set_wol(tp, wol->wolopts);
1841
1842         rtl_unlock_work(tp);
1843
1844         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1845
1846         return 0;
1847 }
1848
1849 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1850 {
1851         return rtl_chip_infos[tp->mac_version].fw_name;
1852 }
1853
1854 static void rtl8169_get_drvinfo(struct net_device *dev,
1855                                 struct ethtool_drvinfo *info)
1856 {
1857         struct rtl8169_private *tp = netdev_priv(dev);
1858         struct rtl_fw *rtl_fw = tp->rtl_fw;
1859
1860         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1861         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1862         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1863         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1864         if (!IS_ERR_OR_NULL(rtl_fw))
1865                 strlcpy(info->fw_version, rtl_fw->version,
1866                         sizeof(info->fw_version));
1867 }
1868
1869 static int rtl8169_get_regs_len(struct net_device *dev)
1870 {
1871         return R8169_REGS_SIZE;
1872 }
1873
1874 static int rtl8169_set_speed_tbi(struct net_device *dev,
1875                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1876 {
1877         struct rtl8169_private *tp = netdev_priv(dev);
1878         void __iomem *ioaddr = tp->mmio_addr;
1879         int ret = 0;
1880         u32 reg;
1881
1882         reg = RTL_R32(TBICSR);
1883         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1884             (duplex == DUPLEX_FULL)) {
1885                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1886         } else if (autoneg == AUTONEG_ENABLE)
1887                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1888         else {
1889                 netif_warn(tp, link, dev,
1890                            "incorrect speed setting refused in TBI mode\n");
1891                 ret = -EOPNOTSUPP;
1892         }
1893
1894         return ret;
1895 }
1896
1897 static int rtl8169_set_speed_xmii(struct net_device *dev,
1898                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1899 {
1900         struct rtl8169_private *tp = netdev_priv(dev);
1901         int giga_ctrl, bmcr;
1902         int rc = -EINVAL;
1903
1904         rtl_writephy(tp, 0x1f, 0x0000);
1905
1906         if (autoneg == AUTONEG_ENABLE) {
1907                 int auto_nego;
1908
1909                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1910                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1911                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1912
1913                 if (adv & ADVERTISED_10baseT_Half)
1914                         auto_nego |= ADVERTISE_10HALF;
1915                 if (adv & ADVERTISED_10baseT_Full)
1916                         auto_nego |= ADVERTISE_10FULL;
1917                 if (adv & ADVERTISED_100baseT_Half)
1918                         auto_nego |= ADVERTISE_100HALF;
1919                 if (adv & ADVERTISED_100baseT_Full)
1920                         auto_nego |= ADVERTISE_100FULL;
1921
1922                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1923
1924                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1925                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1926
1927                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1928                 if (tp->mii.supports_gmii) {
1929                         if (adv & ADVERTISED_1000baseT_Half)
1930                                 giga_ctrl |= ADVERTISE_1000HALF;
1931                         if (adv & ADVERTISED_1000baseT_Full)
1932                                 giga_ctrl |= ADVERTISE_1000FULL;
1933                 } else if (adv & (ADVERTISED_1000baseT_Half |
1934                                   ADVERTISED_1000baseT_Full)) {
1935                         netif_info(tp, link, dev,
1936                                    "PHY does not support 1000Mbps\n");
1937                         goto out;
1938                 }
1939
1940                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1941
1942                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1943                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1944         } else {
1945                 giga_ctrl = 0;
1946
1947                 if (speed == SPEED_10)
1948                         bmcr = 0;
1949                 else if (speed == SPEED_100)
1950                         bmcr = BMCR_SPEED100;
1951                 else
1952                         goto out;
1953
1954                 if (duplex == DUPLEX_FULL)
1955                         bmcr |= BMCR_FULLDPLX;
1956         }
1957
1958         rtl_writephy(tp, MII_BMCR, bmcr);
1959
1960         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1961             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1962                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1963                         rtl_writephy(tp, 0x17, 0x2138);
1964                         rtl_writephy(tp, 0x0e, 0x0260);
1965                 } else {
1966                         rtl_writephy(tp, 0x17, 0x2108);
1967                         rtl_writephy(tp, 0x0e, 0x0000);
1968                 }
1969         }
1970
1971         rc = 0;
1972 out:
1973         return rc;
1974 }
1975
1976 static int rtl8169_set_speed(struct net_device *dev,
1977                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1978 {
1979         struct rtl8169_private *tp = netdev_priv(dev);
1980         int ret;
1981
1982         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1983         if (ret < 0)
1984                 goto out;
1985
1986         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1987             (advertising & ADVERTISED_1000baseT_Full)) {
1988                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1989         }
1990 out:
1991         return ret;
1992 }
1993
1994 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1995 {
1996         struct rtl8169_private *tp = netdev_priv(dev);
1997         int ret;
1998
1999         del_timer_sync(&tp->timer);
2000
2001         rtl_lock_work(tp);
2002         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
2003                                 cmd->duplex, cmd->advertising);
2004         rtl_unlock_work(tp);
2005
2006         return ret;
2007 }
2008
2009 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2010         netdev_features_t features)
2011 {
2012         struct rtl8169_private *tp = netdev_priv(dev);
2013
2014         if (dev->mtu > TD_MSS_MAX)
2015                 features &= ~NETIF_F_ALL_TSO;
2016
2017         if (dev->mtu > JUMBO_1K &&
2018             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2019                 features &= ~NETIF_F_IP_CSUM;
2020
2021         return features;
2022 }
2023
2024 static void __rtl8169_set_features(struct net_device *dev,
2025                                    netdev_features_t features)
2026 {
2027         struct rtl8169_private *tp = netdev_priv(dev);
2028         void __iomem *ioaddr = tp->mmio_addr;
2029         u32 rx_config;
2030
2031         rx_config = RTL_R32(RxConfig);
2032         if (features & NETIF_F_RXALL)
2033                 rx_config |= (AcceptErr | AcceptRunt);
2034         else
2035                 rx_config &= ~(AcceptErr | AcceptRunt);
2036
2037         RTL_W32(RxConfig, rx_config);
2038
2039         if (features & NETIF_F_RXCSUM)
2040                 tp->cp_cmd |= RxChkSum;
2041         else
2042                 tp->cp_cmd &= ~RxChkSum;
2043
2044         if (features & NETIF_F_HW_VLAN_CTAG_RX)
2045                 tp->cp_cmd |= RxVlan;
2046         else
2047                 tp->cp_cmd &= ~RxVlan;
2048
2049         tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2050
2051         RTL_W16(CPlusCmd, tp->cp_cmd);
2052         RTL_R16(CPlusCmd);
2053 }
2054
2055 static int rtl8169_set_features(struct net_device *dev,
2056                                 netdev_features_t features)
2057 {
2058         struct rtl8169_private *tp = netdev_priv(dev);
2059
2060         features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2061
2062         rtl_lock_work(tp);
2063         if (features ^ dev->features)
2064                 __rtl8169_set_features(dev, features);
2065         rtl_unlock_work(tp);
2066
2067         return 0;
2068 }
2069
2070
2071 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2072 {
2073         return (skb_vlan_tag_present(skb)) ?
2074                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2075 }
2076
2077 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2078 {
2079         u32 opts2 = le32_to_cpu(desc->opts2);
2080
2081         if (opts2 & RxVlanTag)
2082                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2083 }
2084
2085 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
2086 {
2087         struct rtl8169_private *tp = netdev_priv(dev);
2088         void __iomem *ioaddr = tp->mmio_addr;
2089         u32 status;
2090
2091         cmd->supported =
2092                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2093         cmd->port = PORT_FIBRE;
2094         cmd->transceiver = XCVR_INTERNAL;
2095
2096         status = RTL_R32(TBICSR);
2097         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
2098         cmd->autoneg = !!(status & TBINwEnable);
2099
2100         ethtool_cmd_speed_set(cmd, SPEED_1000);
2101         cmd->duplex = DUPLEX_FULL; /* Always set */
2102
2103         return 0;
2104 }
2105
2106 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
2107 {
2108         struct rtl8169_private *tp = netdev_priv(dev);
2109
2110         return mii_ethtool_gset(&tp->mii, cmd);
2111 }
2112
2113 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2114 {
2115         struct rtl8169_private *tp = netdev_priv(dev);
2116         int rc;
2117
2118         rtl_lock_work(tp);
2119         rc = tp->get_settings(dev, cmd);
2120         rtl_unlock_work(tp);
2121
2122         return rc;
2123 }
2124
2125 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2126                              void *p)
2127 {
2128         struct rtl8169_private *tp = netdev_priv(dev);
2129         u32 __iomem *data = tp->mmio_addr;
2130         u32 *dw = p;
2131         int i;
2132
2133         rtl_lock_work(tp);
2134         for (i = 0; i < R8169_REGS_SIZE; i += 4)
2135                 memcpy_fromio(dw++, data++, 4);
2136         rtl_unlock_work(tp);
2137 }
2138
2139 static u32 rtl8169_get_msglevel(struct net_device *dev)
2140 {
2141         struct rtl8169_private *tp = netdev_priv(dev);
2142
2143         return tp->msg_enable;
2144 }
2145
2146 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2147 {
2148         struct rtl8169_private *tp = netdev_priv(dev);
2149
2150         tp->msg_enable = value;
2151 }
2152
2153 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2154         "tx_packets",
2155         "rx_packets",
2156         "tx_errors",
2157         "rx_errors",
2158         "rx_missed",
2159         "align_errors",
2160         "tx_single_collisions",
2161         "tx_multi_collisions",
2162         "unicast",
2163         "broadcast",
2164         "multicast",
2165         "tx_aborted",
2166         "tx_underrun",
2167 };
2168
2169 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2170 {
2171         switch (sset) {
2172         case ETH_SS_STATS:
2173                 return ARRAY_SIZE(rtl8169_gstrings);
2174         default:
2175                 return -EOPNOTSUPP;
2176         }
2177 }
2178
2179 DECLARE_RTL_COND(rtl_counters_cond)
2180 {
2181         void __iomem *ioaddr = tp->mmio_addr;
2182
2183         return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
2184 }
2185
2186 static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
2187 {
2188         struct rtl8169_private *tp = netdev_priv(dev);
2189         void __iomem *ioaddr = tp->mmio_addr;
2190         dma_addr_t paddr = tp->counters_phys_addr;
2191         u32 cmd;
2192
2193         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2194         RTL_R32(CounterAddrHigh);
2195         cmd = (u64)paddr & DMA_BIT_MASK(32);
2196         RTL_W32(CounterAddrLow, cmd);
2197         RTL_W32(CounterAddrLow, cmd | counter_cmd);
2198
2199         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2200 }
2201
2202 static bool rtl8169_reset_counters(struct net_device *dev)
2203 {
2204         struct rtl8169_private *tp = netdev_priv(dev);
2205
2206         /*
2207          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2208          * tally counters.
2209          */
2210         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2211                 return true;
2212
2213         return rtl8169_do_counters(dev, CounterReset);
2214 }
2215
2216 static bool rtl8169_update_counters(struct net_device *dev)
2217 {
2218         struct rtl8169_private *tp = netdev_priv(dev);
2219         void __iomem *ioaddr = tp->mmio_addr;
2220
2221         /*
2222          * Some chips are unable to dump tally counters when the receiver
2223          * is disabled.
2224          */
2225         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2226                 return true;
2227
2228         return rtl8169_do_counters(dev, CounterDump);
2229 }
2230
2231 static bool rtl8169_init_counter_offsets(struct net_device *dev)
2232 {
2233         struct rtl8169_private *tp = netdev_priv(dev);
2234         struct rtl8169_counters *counters = tp->counters;
2235         bool ret = false;
2236
2237         /*
2238          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
2239          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2240          * reset by a power cycle, while the counter values collected by the
2241          * driver are reset at every driver unload/load cycle.
2242          *
2243          * To make sure the HW values returned by @get_stats64 match the SW
2244          * values, we collect the initial values at first open(*) and use them
2245          * as offsets to normalize the values returned by @get_stats64.
2246          *
2247          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2248          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2249          * set at open time by rtl_hw_start.
2250          */
2251
2252         if (tp->tc_offset.inited)
2253                 return true;
2254
2255         /* If both, reset and update fail, propagate to caller. */
2256         if (rtl8169_reset_counters(dev))
2257                 ret = true;
2258
2259         if (rtl8169_update_counters(dev))
2260                 ret = true;
2261
2262         tp->tc_offset.tx_errors = counters->tx_errors;
2263         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2264         tp->tc_offset.tx_aborted = counters->tx_aborted;
2265         tp->tc_offset.inited = true;
2266
2267         return ret;
2268 }
2269
2270 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2271                                       struct ethtool_stats *stats, u64 *data)
2272 {
2273         struct rtl8169_private *tp = netdev_priv(dev);
2274         struct rtl8169_counters *counters = tp->counters;
2275
2276         ASSERT_RTNL();
2277
2278         rtl8169_update_counters(dev);
2279
2280         data[0] = le64_to_cpu(counters->tx_packets);
2281         data[1] = le64_to_cpu(counters->rx_packets);
2282         data[2] = le64_to_cpu(counters->tx_errors);
2283         data[3] = le32_to_cpu(counters->rx_errors);
2284         data[4] = le16_to_cpu(counters->rx_missed);
2285         data[5] = le16_to_cpu(counters->align_errors);
2286         data[6] = le32_to_cpu(counters->tx_one_collision);
2287         data[7] = le32_to_cpu(counters->tx_multi_collision);
2288         data[8] = le64_to_cpu(counters->rx_unicast);
2289         data[9] = le64_to_cpu(counters->rx_broadcast);
2290         data[10] = le32_to_cpu(counters->rx_multicast);
2291         data[11] = le16_to_cpu(counters->tx_aborted);
2292         data[12] = le16_to_cpu(counters->tx_underun);
2293 }
2294
2295 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2296 {
2297         switch(stringset) {
2298         case ETH_SS_STATS:
2299                 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
2300                 break;
2301         }
2302 }
2303
2304 static const struct ethtool_ops rtl8169_ethtool_ops = {
2305         .get_drvinfo            = rtl8169_get_drvinfo,
2306         .get_regs_len           = rtl8169_get_regs_len,
2307         .get_link               = ethtool_op_get_link,
2308         .get_settings           = rtl8169_get_settings,
2309         .set_settings           = rtl8169_set_settings,
2310         .get_msglevel           = rtl8169_get_msglevel,
2311         .set_msglevel           = rtl8169_set_msglevel,
2312         .get_regs               = rtl8169_get_regs,
2313         .get_wol                = rtl8169_get_wol,
2314         .set_wol                = rtl8169_set_wol,
2315         .get_strings            = rtl8169_get_strings,
2316         .get_sset_count         = rtl8169_get_sset_count,
2317         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2318         .get_ts_info            = ethtool_op_get_ts_info,
2319 };
2320
2321 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2322                                     struct net_device *dev, u8 default_version)
2323 {
2324         void __iomem *ioaddr = tp->mmio_addr;
2325         /*
2326          * The driver currently handles the 8168Bf and the 8168Be identically
2327          * but they can be identified more specifically through the test below
2328          * if needed:
2329          *
2330          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2331          *
2332          * Same thing for the 8101Eb and the 8101Ec:
2333          *
2334          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2335          */
2336         static const struct rtl_mac_info {
2337                 u32 mask;
2338                 u32 val;
2339                 int mac_version;
2340         } mac_info[] = {
2341                 /* 8168EP family. */
2342                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2343                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2344                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2345
2346                 /* 8168H family. */
2347                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2348                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2349
2350                 /* 8168G family. */
2351                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2352                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2353                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2354                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2355
2356                 /* 8168F family. */
2357                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2358                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2359                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2360
2361                 /* 8168E family. */
2362                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2363                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2364                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2365                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2366
2367                 /* 8168D family. */
2368                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2369                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2370                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2371
2372                 /* 8168DP family. */
2373                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2374                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2375                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2376
2377                 /* 8168C family. */
2378                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2379                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2380                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2381                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2382                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2383                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2384                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2385                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2386                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2387
2388                 /* 8168B family. */
2389                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2390                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2391                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2392                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2393
2394                 /* 8101 family. */
2395                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2396                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2397                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2398                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2399                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2400                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2401                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2402                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2403                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2404                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2405                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2406                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2407                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2408                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2409                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2410                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2411                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2412                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2413                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2414                 /* FIXME: where did these entries come from ? -- FR */
2415                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2416                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2417
2418                 /* 8110 family. */
2419                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2420                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2421                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2422                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2423                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2424                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2425
2426                 /* Catch-all */
2427                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2428         };
2429         const struct rtl_mac_info *p = mac_info;
2430         u32 reg;
2431
2432         reg = RTL_R32(TxConfig);
2433         while ((reg & p->mask) != p->val)
2434                 p++;
2435         tp->mac_version = p->mac_version;
2436
2437         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2438                 netif_notice(tp, probe, dev,
2439                              "unknown MAC, using family default\n");
2440                 tp->mac_version = default_version;
2441         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2442                 tp->mac_version = tp->mii.supports_gmii ?
2443                                   RTL_GIGA_MAC_VER_42 :
2444                                   RTL_GIGA_MAC_VER_43;
2445         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2446                 tp->mac_version = tp->mii.supports_gmii ?
2447                                   RTL_GIGA_MAC_VER_45 :
2448                                   RTL_GIGA_MAC_VER_47;
2449         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2450                 tp->mac_version = tp->mii.supports_gmii ?
2451                                   RTL_GIGA_MAC_VER_46 :
2452                                   RTL_GIGA_MAC_VER_48;
2453         }
2454 }
2455
2456 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2457 {
2458         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2459 }
2460
2461 struct phy_reg {
2462         u16 reg;
2463         u16 val;
2464 };
2465
2466 static void rtl_writephy_batch(struct rtl8169_private *tp,
2467                                const struct phy_reg *regs, int len)
2468 {
2469         while (len-- > 0) {
2470                 rtl_writephy(tp, regs->reg, regs->val);
2471                 regs++;
2472         }
2473 }
2474
2475 #define PHY_READ                0x00000000
2476 #define PHY_DATA_OR             0x10000000
2477 #define PHY_DATA_AND            0x20000000
2478 #define PHY_BJMPN               0x30000000
2479 #define PHY_MDIO_CHG            0x40000000
2480 #define PHY_CLEAR_READCOUNT     0x70000000
2481 #define PHY_WRITE               0x80000000
2482 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2483 #define PHY_COMP_EQ_SKIPN       0xa0000000
2484 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2485 #define PHY_WRITE_PREVIOUS      0xc0000000
2486 #define PHY_SKIPN               0xd0000000
2487 #define PHY_DELAY_MS            0xe0000000
2488
2489 struct fw_info {
2490         u32     magic;
2491         char    version[RTL_VER_SIZE];
2492         __le32  fw_start;
2493         __le32  fw_len;
2494         u8      chksum;
2495 } __packed;
2496
2497 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2498
2499 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2500 {
2501         const struct firmware *fw = rtl_fw->fw;
2502         struct fw_info *fw_info = (struct fw_info *)fw->data;
2503         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2504         char *version = rtl_fw->version;
2505         bool rc = false;
2506
2507         if (fw->size < FW_OPCODE_SIZE)
2508                 goto out;
2509
2510         if (!fw_info->magic) {
2511                 size_t i, size, start;
2512                 u8 checksum = 0;
2513
2514                 if (fw->size < sizeof(*fw_info))
2515                         goto out;
2516
2517                 for (i = 0; i < fw->size; i++)
2518                         checksum += fw->data[i];
2519                 if (checksum != 0)
2520                         goto out;
2521
2522                 start = le32_to_cpu(fw_info->fw_start);
2523                 if (start > fw->size)
2524                         goto out;
2525
2526                 size = le32_to_cpu(fw_info->fw_len);
2527                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2528                         goto out;
2529
2530                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2531
2532                 pa->code = (__le32 *)(fw->data + start);
2533                 pa->size = size;
2534         } else {
2535                 if (fw->size % FW_OPCODE_SIZE)
2536                         goto out;
2537
2538                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2539
2540                 pa->code = (__le32 *)fw->data;
2541                 pa->size = fw->size / FW_OPCODE_SIZE;
2542         }
2543         version[RTL_VER_SIZE - 1] = 0;
2544
2545         rc = true;
2546 out:
2547         return rc;
2548 }
2549
2550 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2551                            struct rtl_fw_phy_action *pa)
2552 {
2553         bool rc = false;
2554         size_t index;
2555
2556         for (index = 0; index < pa->size; index++) {
2557                 u32 action = le32_to_cpu(pa->code[index]);
2558                 u32 regno = (action & 0x0fff0000) >> 16;
2559
2560                 switch(action & 0xf0000000) {
2561                 case PHY_READ:
2562                 case PHY_DATA_OR:
2563                 case PHY_DATA_AND:
2564                 case PHY_MDIO_CHG:
2565                 case PHY_CLEAR_READCOUNT:
2566                 case PHY_WRITE:
2567                 case PHY_WRITE_PREVIOUS:
2568                 case PHY_DELAY_MS:
2569                         break;
2570
2571                 case PHY_BJMPN:
2572                         if (regno > index) {
2573                                 netif_err(tp, ifup, tp->dev,
2574                                           "Out of range of firmware\n");
2575                                 goto out;
2576                         }
2577                         break;
2578                 case PHY_READCOUNT_EQ_SKIP:
2579                         if (index + 2 >= pa->size) {
2580                                 netif_err(tp, ifup, tp->dev,
2581                                           "Out of range of firmware\n");
2582                                 goto out;
2583                         }
2584                         break;
2585                 case PHY_COMP_EQ_SKIPN:
2586                 case PHY_COMP_NEQ_SKIPN:
2587                 case PHY_SKIPN:
2588                         if (index + 1 + regno >= pa->size) {
2589                                 netif_err(tp, ifup, tp->dev,
2590                                           "Out of range of firmware\n");
2591                                 goto out;
2592                         }
2593                         break;
2594
2595                 default:
2596                         netif_err(tp, ifup, tp->dev,
2597                                   "Invalid action 0x%08x\n", action);
2598                         goto out;
2599                 }
2600         }
2601         rc = true;
2602 out:
2603         return rc;
2604 }
2605
2606 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2607 {
2608         struct net_device *dev = tp->dev;
2609         int rc = -EINVAL;
2610
2611         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2612                 netif_err(tp, ifup, dev, "invalid firmware\n");
2613                 goto out;
2614         }
2615
2616         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2617                 rc = 0;
2618 out:
2619         return rc;
2620 }
2621
2622 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2623 {
2624         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2625         struct mdio_ops org, *ops = &tp->mdio_ops;
2626         u32 predata, count;
2627         size_t index;
2628
2629         predata = count = 0;
2630         org.write = ops->write;
2631         org.read = ops->read;
2632
2633         for (index = 0; index < pa->size; ) {
2634                 u32 action = le32_to_cpu(pa->code[index]);
2635                 u32 data = action & 0x0000ffff;
2636                 u32 regno = (action & 0x0fff0000) >> 16;
2637
2638                 if (!action)
2639                         break;
2640
2641                 switch(action & 0xf0000000) {
2642                 case PHY_READ:
2643                         predata = rtl_readphy(tp, regno);
2644                         count++;
2645                         index++;
2646                         break;
2647                 case PHY_DATA_OR:
2648                         predata |= data;
2649                         index++;
2650                         break;
2651                 case PHY_DATA_AND:
2652                         predata &= data;
2653                         index++;
2654                         break;
2655                 case PHY_BJMPN:
2656                         index -= regno;
2657                         break;
2658                 case PHY_MDIO_CHG:
2659                         if (data == 0) {
2660                                 ops->write = org.write;
2661                                 ops->read = org.read;
2662                         } else if (data == 1) {
2663                                 ops->write = mac_mcu_write;
2664                                 ops->read = mac_mcu_read;
2665                         }
2666
2667                         index++;
2668                         break;
2669                 case PHY_CLEAR_READCOUNT:
2670                         count = 0;
2671                         index++;
2672                         break;
2673                 case PHY_WRITE:
2674                         rtl_writephy(tp, regno, data);
2675                         index++;
2676                         break;
2677                 case PHY_READCOUNT_EQ_SKIP:
2678                         index += (count == data) ? 2 : 1;
2679                         break;
2680                 case PHY_COMP_EQ_SKIPN:
2681                         if (predata == data)
2682                                 index += regno;
2683                         index++;
2684                         break;
2685                 case PHY_COMP_NEQ_SKIPN:
2686                         if (predata != data)
2687                                 index += regno;
2688                         index++;
2689                         break;
2690                 case PHY_WRITE_PREVIOUS:
2691                         rtl_writephy(tp, regno, predata);
2692                         index++;
2693                         break;
2694                 case PHY_SKIPN:
2695                         index += regno + 1;
2696                         break;
2697                 case PHY_DELAY_MS:
2698                         mdelay(data);
2699                         index++;
2700                         break;
2701
2702                 default:
2703                         BUG();
2704                 }
2705         }
2706
2707         ops->write = org.write;
2708         ops->read = org.read;
2709 }
2710
2711 static void rtl_release_firmware(struct rtl8169_private *tp)
2712 {
2713         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2714                 release_firmware(tp->rtl_fw->fw);
2715                 kfree(tp->rtl_fw);
2716         }
2717         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2718 }
2719
2720 static void rtl_apply_firmware(struct rtl8169_private *tp)
2721 {
2722         struct rtl_fw *rtl_fw = tp->rtl_fw;
2723
2724         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2725         if (!IS_ERR_OR_NULL(rtl_fw))
2726                 rtl_phy_write_fw(tp, rtl_fw);
2727 }
2728
2729 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2730 {
2731         if (rtl_readphy(tp, reg) != val)
2732                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2733         else
2734                 rtl_apply_firmware(tp);
2735 }
2736
2737 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2738 {
2739         static const struct phy_reg phy_reg_init[] = {
2740                 { 0x1f, 0x0001 },
2741                 { 0x06, 0x006e },
2742                 { 0x08, 0x0708 },
2743                 { 0x15, 0x4000 },
2744                 { 0x18, 0x65c7 },
2745
2746                 { 0x1f, 0x0001 },
2747                 { 0x03, 0x00a1 },
2748                 { 0x02, 0x0008 },
2749                 { 0x01, 0x0120 },
2750                 { 0x00, 0x1000 },
2751                 { 0x04, 0x0800 },
2752                 { 0x04, 0x0000 },
2753
2754                 { 0x03, 0xff41 },
2755                 { 0x02, 0xdf60 },
2756                 { 0x01, 0x0140 },
2757                 { 0x00, 0x0077 },
2758                 { 0x04, 0x7800 },
2759                 { 0x04, 0x7000 },
2760
2761                 { 0x03, 0x802f },
2762                 { 0x02, 0x4f02 },
2763                 { 0x01, 0x0409 },
2764                 { 0x00, 0xf0f9 },
2765                 { 0x04, 0x9800 },
2766                 { 0x04, 0x9000 },
2767
2768                 { 0x03, 0xdf01 },
2769                 { 0x02, 0xdf20 },
2770                 { 0x01, 0xff95 },
2771                 { 0x00, 0xba00 },
2772                 { 0x04, 0xa800 },
2773                 { 0x04, 0xa000 },
2774
2775                 { 0x03, 0xff41 },
2776                 { 0x02, 0xdf20 },
2777                 { 0x01, 0x0140 },
2778                 { 0x00, 0x00bb },
2779                 { 0x04, 0xb800 },
2780                 { 0x04, 0xb000 },
2781
2782                 { 0x03, 0xdf41 },
2783                 { 0x02, 0xdc60 },
2784                 { 0x01, 0x6340 },
2785                 { 0x00, 0x007d },
2786                 { 0x04, 0xd800 },
2787                 { 0x04, 0xd000 },
2788
2789                 { 0x03, 0xdf01 },
2790                 { 0x02, 0xdf20 },
2791                 { 0x01, 0x100a },
2792                 { 0x00, 0xa0ff },
2793                 { 0x04, 0xf800 },
2794                 { 0x04, 0xf000 },
2795
2796                 { 0x1f, 0x0000 },
2797                 { 0x0b, 0x0000 },
2798                 { 0x00, 0x9200 }
2799         };
2800
2801         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2802 }
2803
2804 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2805 {
2806         static const struct phy_reg phy_reg_init[] = {
2807                 { 0x1f, 0x0002 },
2808                 { 0x01, 0x90d0 },
2809                 { 0x1f, 0x0000 }
2810         };
2811
2812         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2813 }
2814
2815 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2816 {
2817         struct pci_dev *pdev = tp->pci_dev;
2818
2819         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2820             (pdev->subsystem_device != 0xe000))
2821                 return;
2822
2823         rtl_writephy(tp, 0x1f, 0x0001);
2824         rtl_writephy(tp, 0x10, 0xf01b);
2825         rtl_writephy(tp, 0x1f, 0x0000);
2826 }
2827
2828 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2829 {
2830         static const struct phy_reg phy_reg_init[] = {
2831                 { 0x1f, 0x0001 },
2832                 { 0x04, 0x0000 },
2833                 { 0x03, 0x00a1 },
2834                 { 0x02, 0x0008 },
2835                 { 0x01, 0x0120 },
2836                 { 0x00, 0x1000 },
2837                 { 0x04, 0x0800 },
2838                 { 0x04, 0x9000 },
2839                 { 0x03, 0x802f },
2840                 { 0x02, 0x4f02 },
2841                 { 0x01, 0x0409 },
2842                 { 0x00, 0xf099 },
2843                 { 0x04, 0x9800 },
2844                 { 0x04, 0xa000 },
2845                 { 0x03, 0xdf01 },
2846                 { 0x02, 0xdf20 },
2847                 { 0x01, 0xff95 },
2848                 { 0x00, 0xba00 },
2849                 { 0x04, 0xa800 },
2850                 { 0x04, 0xf000 },
2851                 { 0x03, 0xdf01 },
2852                 { 0x02, 0xdf20 },
2853                 { 0x01, 0x101a },
2854                 { 0x00, 0xa0ff },
2855                 { 0x04, 0xf800 },
2856                 { 0x04, 0x0000 },
2857                 { 0x1f, 0x0000 },
2858
2859                 { 0x1f, 0x0001 },
2860                 { 0x10, 0xf41b },
2861                 { 0x14, 0xfb54 },
2862                 { 0x18, 0xf5c7 },
2863                 { 0x1f, 0x0000 },
2864
2865                 { 0x1f, 0x0001 },
2866                 { 0x17, 0x0cc0 },
2867                 { 0x1f, 0x0000 }
2868         };
2869
2870         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2871
2872         rtl8169scd_hw_phy_config_quirk(tp);
2873 }
2874
2875 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2876 {
2877         static const struct phy_reg phy_reg_init[] = {
2878                 { 0x1f, 0x0001 },
2879                 { 0x04, 0x0000 },
2880                 { 0x03, 0x00a1 },
2881                 { 0x02, 0x0008 },
2882                 { 0x01, 0x0120 },
2883                 { 0x00, 0x1000 },
2884                 { 0x04, 0x0800 },
2885                 { 0x04, 0x9000 },
2886                 { 0x03, 0x802f },
2887                 { 0x02, 0x4f02 },
2888                 { 0x01, 0x0409 },
2889                 { 0x00, 0xf099 },
2890                 { 0x04, 0x9800 },
2891                 { 0x04, 0xa000 },
2892                 { 0x03, 0xdf01 },
2893                 { 0x02, 0xdf20 },
2894                 { 0x01, 0xff95 },
2895                 { 0x00, 0xba00 },
2896                 { 0x04, 0xa800 },
2897                 { 0x04, 0xf000 },
2898                 { 0x03, 0xdf01 },
2899                 { 0x02, 0xdf20 },
2900                 { 0x01, 0x101a },
2901                 { 0x00, 0xa0ff },
2902                 { 0x04, 0xf800 },
2903                 { 0x04, 0x0000 },
2904                 { 0x1f, 0x0000 },
2905
2906                 { 0x1f, 0x0001 },
2907                 { 0x0b, 0x8480 },
2908                 { 0x1f, 0x0000 },
2909
2910                 { 0x1f, 0x0001 },
2911                 { 0x18, 0x67c7 },
2912                 { 0x04, 0x2000 },
2913                 { 0x03, 0x002f },
2914                 { 0x02, 0x4360 },
2915                 { 0x01, 0x0109 },
2916                 { 0x00, 0x3022 },
2917                 { 0x04, 0x2800 },
2918                 { 0x1f, 0x0000 },
2919
2920                 { 0x1f, 0x0001 },
2921                 { 0x17, 0x0cc0 },
2922                 { 0x1f, 0x0000 }
2923         };
2924
2925         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2926 }
2927
2928 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2929 {
2930         static const struct phy_reg phy_reg_init[] = {
2931                 { 0x10, 0xf41b },
2932                 { 0x1f, 0x0000 }
2933         };
2934
2935         rtl_writephy(tp, 0x1f, 0x0001);
2936         rtl_patchphy(tp, 0x16, 1 << 0);
2937
2938         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2939 }
2940
2941 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2942 {
2943         static const struct phy_reg phy_reg_init[] = {
2944                 { 0x1f, 0x0001 },
2945                 { 0x10, 0xf41b },
2946                 { 0x1f, 0x0000 }
2947         };
2948
2949         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2950 }
2951
2952 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2953 {
2954         static const struct phy_reg phy_reg_init[] = {
2955                 { 0x1f, 0x0000 },
2956                 { 0x1d, 0x0f00 },
2957                 { 0x1f, 0x0002 },
2958                 { 0x0c, 0x1ec8 },
2959                 { 0x1f, 0x0000 }
2960         };
2961
2962         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2963 }
2964
2965 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2966 {
2967         static const struct phy_reg phy_reg_init[] = {
2968                 { 0x1f, 0x0001 },
2969                 { 0x1d, 0x3d98 },
2970                 { 0x1f, 0x0000 }
2971         };
2972
2973         rtl_writephy(tp, 0x1f, 0x0000);
2974         rtl_patchphy(tp, 0x14, 1 << 5);
2975         rtl_patchphy(tp, 0x0d, 1 << 5);
2976
2977         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2978 }
2979
2980 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2981 {
2982         static const struct phy_reg phy_reg_init[] = {
2983                 { 0x1f, 0x0001 },
2984                 { 0x12, 0x2300 },
2985                 { 0x1f, 0x0002 },
2986                 { 0x00, 0x88d4 },
2987                 { 0x01, 0x82b1 },
2988                 { 0x03, 0x7002 },
2989                 { 0x08, 0x9e30 },
2990                 { 0x09, 0x01f0 },
2991                 { 0x0a, 0x5500 },
2992                 { 0x0c, 0x00c8 },
2993                 { 0x1f, 0x0003 },
2994                 { 0x12, 0xc096 },
2995                 { 0x16, 0x000a },
2996                 { 0x1f, 0x0000 },
2997                 { 0x1f, 0x0000 },
2998                 { 0x09, 0x2000 },
2999                 { 0x09, 0x0000 }
3000         };
3001
3002         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3003
3004         rtl_patchphy(tp, 0x14, 1 << 5);
3005         rtl_patchphy(tp, 0x0d, 1 << 5);
3006         rtl_writephy(tp, 0x1f, 0x0000);
3007 }
3008
3009 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3010 {
3011         static const struct phy_reg phy_reg_init[] = {
3012                 { 0x1f, 0x0001 },
3013                 { 0x12, 0x2300 },
3014                 { 0x03, 0x802f },
3015                 { 0x02, 0x4f02 },
3016                 { 0x01, 0x0409 },
3017                 { 0x00, 0xf099 },
3018                 { 0x04, 0x9800 },
3019                 { 0x04, 0x9000 },
3020                 { 0x1d, 0x3d98 },
3021                 { 0x1f, 0x0002 },
3022                 { 0x0c, 0x7eb8 },
3023                 { 0x06, 0x0761 },
3024                 { 0x1f, 0x0003 },
3025                 { 0x16, 0x0f0a },
3026                 { 0x1f, 0x0000 }
3027         };
3028
3029         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3030
3031         rtl_patchphy(tp, 0x16, 1 << 0);
3032         rtl_patchphy(tp, 0x14, 1 << 5);
3033         rtl_patchphy(tp, 0x0d, 1 << 5);
3034         rtl_writephy(tp, 0x1f, 0x0000);
3035 }
3036
3037 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3038 {
3039         static const struct phy_reg phy_reg_init[] = {
3040                 { 0x1f, 0x0001 },
3041                 { 0x12, 0x2300 },
3042                 { 0x1d, 0x3d98 },
3043                 { 0x1f, 0x0002 },
3044                 { 0x0c, 0x7eb8 },
3045                 { 0x06, 0x5461 },
3046                 { 0x1f, 0x0003 },
3047                 { 0x16, 0x0f0a },
3048                 { 0x1f, 0x0000 }
3049         };
3050
3051         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3052
3053         rtl_patchphy(tp, 0x16, 1 << 0);
3054         rtl_patchphy(tp, 0x14, 1 << 5);
3055         rtl_patchphy(tp, 0x0d, 1 << 5);
3056         rtl_writephy(tp, 0x1f, 0x0000);
3057 }
3058
3059 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3060 {
3061         rtl8168c_3_hw_phy_config(tp);
3062 }
3063
3064 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3065 {
3066         static const struct phy_reg phy_reg_init_0[] = {
3067                 /* Channel Estimation */
3068                 { 0x1f, 0x0001 },
3069                 { 0x06, 0x4064 },
3070                 { 0x07, 0x2863 },
3071                 { 0x08, 0x059c },
3072                 { 0x09, 0x26b4 },
3073                 { 0x0a, 0x6a19 },
3074                 { 0x0b, 0xdcc8 },
3075                 { 0x10, 0xf06d },
3076                 { 0x14, 0x7f68 },
3077                 { 0x18, 0x7fd9 },
3078                 { 0x1c, 0xf0ff },
3079                 { 0x1d, 0x3d9c },
3080                 { 0x1f, 0x0003 },
3081                 { 0x12, 0xf49f },
3082                 { 0x13, 0x070b },
3083                 { 0x1a, 0x05ad },
3084                 { 0x14, 0x94c0 },
3085
3086                 /*
3087                  * Tx Error Issue
3088                  * Enhance line driver power
3089                  */
3090                 { 0x1f, 0x0002 },
3091                 { 0x06, 0x5561 },
3092                 { 0x1f, 0x0005 },
3093                 { 0x05, 0x8332 },
3094                 { 0x06, 0x5561 },
3095
3096                 /*
3097                  * Can not link to 1Gbps with bad cable
3098                  * Decrease SNR threshold form 21.07dB to 19.04dB
3099                  */
3100                 { 0x1f, 0x0001 },
3101                 { 0x17, 0x0cc0 },
3102
3103                 { 0x1f, 0x0000 },
3104                 { 0x0d, 0xf880 }
3105         };
3106
3107         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3108
3109         /*
3110          * Rx Error Issue
3111          * Fine Tune Switching regulator parameter
3112          */
3113         rtl_writephy(tp, 0x1f, 0x0002);
3114         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3115         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3116
3117         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3118                 static const struct phy_reg phy_reg_init[] = {
3119                         { 0x1f, 0x0002 },
3120                         { 0x05, 0x669a },
3121                         { 0x1f, 0x0005 },
3122                         { 0x05, 0x8330 },
3123                         { 0x06, 0x669a },
3124                         { 0x1f, 0x0002 }
3125                 };
3126                 int val;
3127
3128                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3129
3130                 val = rtl_readphy(tp, 0x0d);
3131
3132                 if ((val & 0x00ff) != 0x006c) {
3133                         static const u32 set[] = {
3134                                 0x0065, 0x0066, 0x0067, 0x0068,
3135                                 0x0069, 0x006a, 0x006b, 0x006c
3136                         };
3137                         int i;
3138
3139                         rtl_writephy(tp, 0x1f, 0x0002);
3140
3141                         val &= 0xff00;
3142                         for (i = 0; i < ARRAY_SIZE(set); i++)
3143                                 rtl_writephy(tp, 0x0d, val | set[i]);
3144                 }
3145         } else {
3146                 static const struct phy_reg phy_reg_init[] = {
3147                         { 0x1f, 0x0002 },
3148                         { 0x05, 0x6662 },
3149                         { 0x1f, 0x0005 },
3150                         { 0x05, 0x8330 },
3151                         { 0x06, 0x6662 }
3152                 };
3153
3154                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3155         }
3156
3157         /* RSET couple improve */
3158         rtl_writephy(tp, 0x1f, 0x0002);
3159         rtl_patchphy(tp, 0x0d, 0x0300);
3160         rtl_patchphy(tp, 0x0f, 0x0010);
3161
3162         /* Fine tune PLL performance */
3163         rtl_writephy(tp, 0x1f, 0x0002);
3164         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3165         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3166
3167         rtl_writephy(tp, 0x1f, 0x0005);
3168         rtl_writephy(tp, 0x05, 0x001b);
3169
3170         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3171
3172         rtl_writephy(tp, 0x1f, 0x0000);
3173 }
3174
3175 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3176 {
3177         static const struct phy_reg phy_reg_init_0[] = {
3178                 /* Channel Estimation */
3179                 { 0x1f, 0x0001 },
3180                 { 0x06, 0x4064 },
3181                 { 0x07, 0x2863 },
3182                 { 0x08, 0x059c },
3183                 { 0x09, 0x26b4 },
3184                 { 0x0a, 0x6a19 },
3185                 { 0x0b, 0xdcc8 },
3186                 { 0x10, 0xf06d },
3187                 { 0x14, 0x7f68 },
3188                 { 0x18, 0x7fd9 },
3189                 { 0x1c, 0xf0ff },
3190                 { 0x1d, 0x3d9c },
3191                 { 0x1f, 0x0003 },
3192                 { 0x12, 0xf49f },
3193                 { 0x13, 0x070b },
3194                 { 0x1a, 0x05ad },
3195                 { 0x14, 0x94c0 },
3196
3197                 /*
3198                  * Tx Error Issue
3199                  * Enhance line driver power
3200                  */
3201                 { 0x1f, 0x0002 },
3202                 { 0x06, 0x5561 },
3203                 { 0x1f, 0x0005 },
3204                 { 0x05, 0x8332 },
3205                 { 0x06, 0x5561 },
3206
3207                 /*
3208                  * Can not link to 1Gbps with bad cable
3209                  * Decrease SNR threshold form 21.07dB to 19.04dB
3210                  */
3211                 { 0x1f, 0x0001 },
3212                 { 0x17, 0x0cc0 },
3213
3214                 { 0x1f, 0x0000 },
3215                 { 0x0d, 0xf880 }
3216         };
3217
3218         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3219
3220         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3221                 static const struct phy_reg phy_reg_init[] = {
3222                         { 0x1f, 0x0002 },
3223                         { 0x05, 0x669a },
3224                         { 0x1f, 0x0005 },
3225                         { 0x05, 0x8330 },
3226                         { 0x06, 0x669a },
3227
3228                         { 0x1f, 0x0002 }
3229                 };
3230                 int val;
3231
3232                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3233
3234                 val = rtl_readphy(tp, 0x0d);
3235                 if ((val & 0x00ff) != 0x006c) {
3236                         static const u32 set[] = {
3237                                 0x0065, 0x0066, 0x0067, 0x0068,
3238                                 0x0069, 0x006a, 0x006b, 0x006c
3239                         };
3240                         int i;
3241
3242                         rtl_writephy(tp, 0x1f, 0x0002);
3243
3244                         val &= 0xff00;
3245                         for (i = 0; i < ARRAY_SIZE(set); i++)
3246                                 rtl_writephy(tp, 0x0d, val | set[i]);
3247                 }
3248         } else {
3249                 static const struct phy_reg phy_reg_init[] = {
3250                         { 0x1f, 0x0002 },
3251                         { 0x05, 0x2642 },
3252                         { 0x1f, 0x0005 },
3253                         { 0x05, 0x8330 },
3254                         { 0x06, 0x2642 }
3255                 };
3256
3257                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3258         }
3259
3260         /* Fine tune PLL performance */
3261         rtl_writephy(tp, 0x1f, 0x0002);
3262         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3263         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3264
3265         /* Switching regulator Slew rate */
3266         rtl_writephy(tp, 0x1f, 0x0002);
3267         rtl_patchphy(tp, 0x0f, 0x0017);
3268
3269         rtl_writephy(tp, 0x1f, 0x0005);
3270         rtl_writephy(tp, 0x05, 0x001b);
3271
3272         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3273
3274         rtl_writephy(tp, 0x1f, 0x0000);
3275 }
3276
3277 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3278 {
3279         static const struct phy_reg phy_reg_init[] = {
3280                 { 0x1f, 0x0002 },
3281                 { 0x10, 0x0008 },
3282                 { 0x0d, 0x006c },
3283
3284                 { 0x1f, 0x0000 },
3285                 { 0x0d, 0xf880 },
3286
3287                 { 0x1f, 0x0001 },
3288                 { 0x17, 0x0cc0 },
3289
3290                 { 0x1f, 0x0001 },
3291                 { 0x0b, 0xa4d8 },
3292                 { 0x09, 0x281c },
3293                 { 0x07, 0x2883 },
3294                 { 0x0a, 0x6b35 },
3295                 { 0x1d, 0x3da4 },
3296                 { 0x1c, 0xeffd },
3297                 { 0x14, 0x7f52 },
3298                 { 0x18, 0x7fc6 },
3299                 { 0x08, 0x0601 },
3300                 { 0x06, 0x4063 },
3301                 { 0x10, 0xf074 },
3302                 { 0x1f, 0x0003 },
3303                 { 0x13, 0x0789 },
3304                 { 0x12, 0xf4bd },
3305                 { 0x1a, 0x04fd },
3306                 { 0x14, 0x84b0 },
3307                 { 0x1f, 0x0000 },
3308                 { 0x00, 0x9200 },
3309
3310                 { 0x1f, 0x0005 },
3311                 { 0x01, 0x0340 },
3312                 { 0x1f, 0x0001 },
3313                 { 0x04, 0x4000 },
3314                 { 0x03, 0x1d21 },
3315                 { 0x02, 0x0c32 },
3316                 { 0x01, 0x0200 },
3317                 { 0x00, 0x5554 },
3318                 { 0x04, 0x4800 },
3319                 { 0x04, 0x4000 },
3320                 { 0x04, 0xf000 },
3321                 { 0x03, 0xdf01 },
3322                 { 0x02, 0xdf20 },
3323                 { 0x01, 0x101a },
3324                 { 0x00, 0xa0ff },
3325                 { 0x04, 0xf800 },
3326                 { 0x04, 0xf000 },
3327                 { 0x1f, 0x0000 },
3328
3329                 { 0x1f, 0x0007 },
3330                 { 0x1e, 0x0023 },
3331                 { 0x16, 0x0000 },
3332                 { 0x1f, 0x0000 }
3333         };
3334
3335         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3336 }
3337
3338 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3339 {
3340         static const struct phy_reg phy_reg_init[] = {
3341                 { 0x1f, 0x0001 },
3342                 { 0x17, 0x0cc0 },
3343
3344                 { 0x1f, 0x0007 },
3345                 { 0x1e, 0x002d },
3346                 { 0x18, 0x0040 },
3347                 { 0x1f, 0x0000 }
3348         };
3349
3350         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3351         rtl_patchphy(tp, 0x0d, 1 << 5);
3352 }
3353
3354 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3355 {
3356         static const struct phy_reg phy_reg_init[] = {
3357                 /* Enable Delay cap */
3358                 { 0x1f, 0x0005 },
3359                 { 0x05, 0x8b80 },
3360                 { 0x06, 0xc896 },
3361                 { 0x1f, 0x0000 },
3362
3363                 /* Channel estimation fine tune */
3364                 { 0x1f, 0x0001 },
3365                 { 0x0b, 0x6c20 },
3366                 { 0x07, 0x2872 },
3367                 { 0x1c, 0xefff },
3368                 { 0x1f, 0x0003 },
3369                 { 0x14, 0x6420 },
3370                 { 0x1f, 0x0000 },
3371
3372                 /* Update PFM & 10M TX idle timer */
3373                 { 0x1f, 0x0007 },
3374                 { 0x1e, 0x002f },
3375                 { 0x15, 0x1919 },
3376                 { 0x1f, 0x0000 },
3377
3378                 { 0x1f, 0x0007 },
3379                 { 0x1e, 0x00ac },
3380                 { 0x18, 0x0006 },
3381                 { 0x1f, 0x0000 }
3382         };
3383
3384         rtl_apply_firmware(tp);
3385
3386         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3387
3388         /* DCO enable for 10M IDLE Power */
3389         rtl_writephy(tp, 0x1f, 0x0007);
3390         rtl_writephy(tp, 0x1e, 0x0023);
3391         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3392         rtl_writephy(tp, 0x1f, 0x0000);
3393
3394         /* For impedance matching */
3395         rtl_writephy(tp, 0x1f, 0x0002);
3396         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3397         rtl_writephy(tp, 0x1f, 0x0000);
3398
3399         /* PHY auto speed down */
3400         rtl_writephy(tp, 0x1f, 0x0007);
3401         rtl_writephy(tp, 0x1e, 0x002d);
3402         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3403         rtl_writephy(tp, 0x1f, 0x0000);
3404         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3405
3406         rtl_writephy(tp, 0x1f, 0x0005);
3407         rtl_writephy(tp, 0x05, 0x8b86);
3408         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3409         rtl_writephy(tp, 0x1f, 0x0000);
3410
3411         rtl_writephy(tp, 0x1f, 0x0005);
3412         rtl_writephy(tp, 0x05, 0x8b85);
3413         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3414         rtl_writephy(tp, 0x1f, 0x0007);
3415         rtl_writephy(tp, 0x1e, 0x0020);
3416         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3417         rtl_writephy(tp, 0x1f, 0x0006);
3418         rtl_writephy(tp, 0x00, 0x5a00);
3419         rtl_writephy(tp, 0x1f, 0x0000);
3420         rtl_writephy(tp, 0x0d, 0x0007);
3421         rtl_writephy(tp, 0x0e, 0x003c);
3422         rtl_writephy(tp, 0x0d, 0x4007);
3423         rtl_writephy(tp, 0x0e, 0x0000);
3424         rtl_writephy(tp, 0x0d, 0x0000);
3425 }
3426
3427 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3428 {
3429         const u16 w[] = {
3430                 addr[0] | (addr[1] << 8),
3431                 addr[2] | (addr[3] << 8),
3432                 addr[4] | (addr[5] << 8)
3433         };
3434         const struct exgmac_reg e[] = {
3435                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3436                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3437                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3438                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3439         };
3440
3441         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3442 }
3443
3444 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3445 {
3446         static const struct phy_reg phy_reg_init[] = {
3447                 /* Enable Delay cap */
3448                 { 0x1f, 0x0004 },
3449                 { 0x1f, 0x0007 },
3450                 { 0x1e, 0x00ac },
3451                 { 0x18, 0x0006 },
3452                 { 0x1f, 0x0002 },
3453                 { 0x1f, 0x0000 },
3454                 { 0x1f, 0x0000 },
3455
3456                 /* Channel estimation fine tune */
3457                 { 0x1f, 0x0003 },
3458                 { 0x09, 0xa20f },
3459                 { 0x1f, 0x0000 },
3460                 { 0x1f, 0x0000 },
3461
3462                 /* Green Setting */
3463                 { 0x1f, 0x0005 },
3464                 { 0x05, 0x8b5b },
3465                 { 0x06, 0x9222 },
3466                 { 0x05, 0x8b6d },
3467                 { 0x06, 0x8000 },
3468                 { 0x05, 0x8b76 },
3469                 { 0x06, 0x8000 },
3470                 { 0x1f, 0x0000 }
3471         };
3472
3473         rtl_apply_firmware(tp);
3474
3475         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3476
3477         /* For 4-corner performance improve */
3478         rtl_writephy(tp, 0x1f, 0x0005);
3479         rtl_writephy(tp, 0x05, 0x8b80);
3480         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3481         rtl_writephy(tp, 0x1f, 0x0000);
3482
3483         /* PHY auto speed down */
3484         rtl_writephy(tp, 0x1f, 0x0004);
3485         rtl_writephy(tp, 0x1f, 0x0007);
3486         rtl_writephy(tp, 0x1e, 0x002d);
3487         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3488         rtl_writephy(tp, 0x1f, 0x0002);
3489         rtl_writephy(tp, 0x1f, 0x0000);
3490         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3491
3492         /* improve 10M EEE waveform */
3493         rtl_writephy(tp, 0x1f, 0x0005);
3494         rtl_writephy(tp, 0x05, 0x8b86);
3495         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3496         rtl_writephy(tp, 0x1f, 0x0000);
3497
3498         /* Improve 2-pair detection performance */
3499         rtl_writephy(tp, 0x1f, 0x0005);
3500         rtl_writephy(tp, 0x05, 0x8b85);
3501         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3502         rtl_writephy(tp, 0x1f, 0x0000);
3503
3504         /* EEE setting */
3505         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3506         rtl_writephy(tp, 0x1f, 0x0005);
3507         rtl_writephy(tp, 0x05, 0x8b85);
3508         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3509         rtl_writephy(tp, 0x1f, 0x0004);
3510         rtl_writephy(tp, 0x1f, 0x0007);
3511         rtl_writephy(tp, 0x1e, 0x0020);
3512         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3513         rtl_writephy(tp, 0x1f, 0x0002);
3514         rtl_writephy(tp, 0x1f, 0x0000);
3515         rtl_writephy(tp, 0x0d, 0x0007);
3516         rtl_writephy(tp, 0x0e, 0x003c);
3517         rtl_writephy(tp, 0x0d, 0x4007);
3518         rtl_writephy(tp, 0x0e, 0x0000);
3519         rtl_writephy(tp, 0x0d, 0x0000);
3520
3521         /* Green feature */
3522         rtl_writephy(tp, 0x1f, 0x0003);
3523         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3524         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3525         rtl_writephy(tp, 0x1f, 0x0000);
3526
3527         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3528         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3529 }
3530
3531 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3532 {
3533         /* For 4-corner performance improve */
3534         rtl_writephy(tp, 0x1f, 0x0005);
3535         rtl_writephy(tp, 0x05, 0x8b80);
3536         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3537         rtl_writephy(tp, 0x1f, 0x0000);
3538
3539         /* PHY auto speed down */
3540         rtl_writephy(tp, 0x1f, 0x0007);
3541         rtl_writephy(tp, 0x1e, 0x002d);
3542         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3543         rtl_writephy(tp, 0x1f, 0x0000);
3544         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3545
3546         /* Improve 10M EEE waveform */
3547         rtl_writephy(tp, 0x1f, 0x0005);
3548         rtl_writephy(tp, 0x05, 0x8b86);
3549         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3550         rtl_writephy(tp, 0x1f, 0x0000);
3551 }
3552
3553 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3554 {
3555         static const struct phy_reg phy_reg_init[] = {
3556                 /* Channel estimation fine tune */
3557                 { 0x1f, 0x0003 },
3558                 { 0x09, 0xa20f },
3559                 { 0x1f, 0x0000 },
3560
3561                 /* Modify green table for giga & fnet */
3562                 { 0x1f, 0x0005 },
3563                 { 0x05, 0x8b55 },
3564                 { 0x06, 0x0000 },
3565                 { 0x05, 0x8b5e },
3566                 { 0x06, 0x0000 },
3567                 { 0x05, 0x8b67 },
3568                 { 0x06, 0x0000 },
3569                 { 0x05, 0x8b70 },
3570                 { 0x06, 0x0000 },
3571                 { 0x1f, 0x0000 },
3572                 { 0x1f, 0x0007 },
3573                 { 0x1e, 0x0078 },
3574                 { 0x17, 0x0000 },
3575                 { 0x19, 0x00fb },
3576                 { 0x1f, 0x0000 },
3577
3578                 /* Modify green table for 10M */
3579                 { 0x1f, 0x0005 },
3580                 { 0x05, 0x8b79 },
3581                 { 0x06, 0xaa00 },
3582                 { 0x1f, 0x0000 },
3583
3584                 /* Disable hiimpedance detection (RTCT) */
3585                 { 0x1f, 0x0003 },
3586                 { 0x01, 0x328a },
3587                 { 0x1f, 0x0000 }
3588         };
3589
3590         rtl_apply_firmware(tp);
3591
3592         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3593
3594         rtl8168f_hw_phy_config(tp);
3595
3596         /* Improve 2-pair detection performance */
3597         rtl_writephy(tp, 0x1f, 0x0005);
3598         rtl_writephy(tp, 0x05, 0x8b85);
3599         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3600         rtl_writephy(tp, 0x1f, 0x0000);
3601 }
3602
3603 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3604 {
3605         rtl_apply_firmware(tp);
3606
3607         rtl8168f_hw_phy_config(tp);
3608 }
3609
3610 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3611 {
3612         static const struct phy_reg phy_reg_init[] = {
3613                 /* Channel estimation fine tune */
3614                 { 0x1f, 0x0003 },
3615                 { 0x09, 0xa20f },
3616                 { 0x1f, 0x0000 },
3617
3618                 /* Modify green table for giga & fnet */
3619                 { 0x1f, 0x0005 },
3620                 { 0x05, 0x8b55 },
3621                 { 0x06, 0x0000 },
3622                 { 0x05, 0x8b5e },
3623                 { 0x06, 0x0000 },
3624                 { 0x05, 0x8b67 },
3625                 { 0x06, 0x0000 },
3626                 { 0x05, 0x8b70 },
3627                 { 0x06, 0x0000 },
3628                 { 0x1f, 0x0000 },
3629                 { 0x1f, 0x0007 },
3630                 { 0x1e, 0x0078 },
3631                 { 0x17, 0x0000 },
3632                 { 0x19, 0x00aa },
3633                 { 0x1f, 0x0000 },
3634
3635                 /* Modify green table for 10M */
3636                 { 0x1f, 0x0005 },
3637                 { 0x05, 0x8b79 },
3638                 { 0x06, 0xaa00 },
3639                 { 0x1f, 0x0000 },
3640
3641                 /* Disable hiimpedance detection (RTCT) */
3642                 { 0x1f, 0x0003 },
3643                 { 0x01, 0x328a },
3644                 { 0x1f, 0x0000 }
3645         };
3646
3647
3648         rtl_apply_firmware(tp);
3649
3650         rtl8168f_hw_phy_config(tp);
3651
3652         /* Improve 2-pair detection performance */
3653         rtl_writephy(tp, 0x1f, 0x0005);
3654         rtl_writephy(tp, 0x05, 0x8b85);
3655         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3656         rtl_writephy(tp, 0x1f, 0x0000);
3657
3658         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3659
3660         /* Modify green table for giga */
3661         rtl_writephy(tp, 0x1f, 0x0005);
3662         rtl_writephy(tp, 0x05, 0x8b54);
3663         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3664         rtl_writephy(tp, 0x05, 0x8b5d);
3665         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3666         rtl_writephy(tp, 0x05, 0x8a7c);
3667         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3668         rtl_writephy(tp, 0x05, 0x8a7f);
3669         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3670         rtl_writephy(tp, 0x05, 0x8a82);
3671         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3672         rtl_writephy(tp, 0x05, 0x8a85);
3673         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3674         rtl_writephy(tp, 0x05, 0x8a88);
3675         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3676         rtl_writephy(tp, 0x1f, 0x0000);
3677
3678         /* uc same-seed solution */
3679         rtl_writephy(tp, 0x1f, 0x0005);
3680         rtl_writephy(tp, 0x05, 0x8b85);
3681         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3682         rtl_writephy(tp, 0x1f, 0x0000);
3683
3684         /* eee setting */
3685         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3686         rtl_writephy(tp, 0x1f, 0x0005);
3687         rtl_writephy(tp, 0x05, 0x8b85);
3688         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3689         rtl_writephy(tp, 0x1f, 0x0004);
3690         rtl_writephy(tp, 0x1f, 0x0007);
3691         rtl_writephy(tp, 0x1e, 0x0020);
3692         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3693         rtl_writephy(tp, 0x1f, 0x0000);
3694         rtl_writephy(tp, 0x0d, 0x0007);
3695         rtl_writephy(tp, 0x0e, 0x003c);
3696         rtl_writephy(tp, 0x0d, 0x4007);
3697         rtl_writephy(tp, 0x0e, 0x0000);
3698         rtl_writephy(tp, 0x0d, 0x0000);
3699
3700         /* Green feature */
3701         rtl_writephy(tp, 0x1f, 0x0003);
3702         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3703         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3704         rtl_writephy(tp, 0x1f, 0x0000);
3705 }
3706
3707 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3708 {
3709         rtl_apply_firmware(tp);
3710
3711         rtl_writephy(tp, 0x1f, 0x0a46);
3712         if (rtl_readphy(tp, 0x10) & 0x0100) {
3713                 rtl_writephy(tp, 0x1f, 0x0bcc);
3714                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3715         } else {
3716                 rtl_writephy(tp, 0x1f, 0x0bcc);
3717                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3718         }
3719
3720         rtl_writephy(tp, 0x1f, 0x0a46);
3721         if (rtl_readphy(tp, 0x13) & 0x0100) {
3722                 rtl_writephy(tp, 0x1f, 0x0c41);
3723                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3724         } else {
3725                 rtl_writephy(tp, 0x1f, 0x0c41);
3726                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3727         }
3728
3729         /* Enable PHY auto speed down */
3730         rtl_writephy(tp, 0x1f, 0x0a44);
3731         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3732
3733         rtl_writephy(tp, 0x1f, 0x0bcc);
3734         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3735         rtl_writephy(tp, 0x1f, 0x0a44);
3736         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3737         rtl_writephy(tp, 0x1f, 0x0a43);
3738         rtl_writephy(tp, 0x13, 0x8084);
3739         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3740         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3741
3742         /* EEE auto-fallback function */
3743         rtl_writephy(tp, 0x1f, 0x0a4b);
3744         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3745
3746         /* Enable UC LPF tune function */
3747         rtl_writephy(tp, 0x1f, 0x0a43);
3748         rtl_writephy(tp, 0x13, 0x8012);
3749         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3750
3751         rtl_writephy(tp, 0x1f, 0x0c42);
3752         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3753
3754         /* Improve SWR Efficiency */
3755         rtl_writephy(tp, 0x1f, 0x0bcd);
3756         rtl_writephy(tp, 0x14, 0x5065);
3757         rtl_writephy(tp, 0x14, 0xd065);
3758         rtl_writephy(tp, 0x1f, 0x0bc8);
3759         rtl_writephy(tp, 0x11, 0x5655);
3760         rtl_writephy(tp, 0x1f, 0x0bcd);
3761         rtl_writephy(tp, 0x14, 0x1065);
3762         rtl_writephy(tp, 0x14, 0x9065);
3763         rtl_writephy(tp, 0x14, 0x1065);
3764
3765         /* Check ALDPS bit, disable it if enabled */
3766         rtl_writephy(tp, 0x1f, 0x0a43);
3767         if (rtl_readphy(tp, 0x10) & 0x0004)
3768                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3769
3770         rtl_writephy(tp, 0x1f, 0x0000);
3771 }
3772
3773 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3774 {
3775         rtl_apply_firmware(tp);
3776 }
3777
3778 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3779 {
3780         u16 dout_tapbin;
3781         u32 data;
3782
3783         rtl_apply_firmware(tp);
3784
3785         /* CHN EST parameters adjust - giga master */
3786         rtl_writephy(tp, 0x1f, 0x0a43);
3787         rtl_writephy(tp, 0x13, 0x809b);
3788         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3789         rtl_writephy(tp, 0x13, 0x80a2);
3790         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3791         rtl_writephy(tp, 0x13, 0x80a4);
3792         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3793         rtl_writephy(tp, 0x13, 0x809c);
3794         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3795         rtl_writephy(tp, 0x1f, 0x0000);
3796
3797         /* CHN EST parameters adjust - giga slave */
3798         rtl_writephy(tp, 0x1f, 0x0a43);
3799         rtl_writephy(tp, 0x13, 0x80ad);
3800         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3801         rtl_writephy(tp, 0x13, 0x80b4);
3802         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3803         rtl_writephy(tp, 0x13, 0x80ac);
3804         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3805         rtl_writephy(tp, 0x1f, 0x0000);
3806
3807         /* CHN EST parameters adjust - fnet */
3808         rtl_writephy(tp, 0x1f, 0x0a43);
3809         rtl_writephy(tp, 0x13, 0x808e);
3810         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3811         rtl_writephy(tp, 0x13, 0x8090);
3812         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3813         rtl_writephy(tp, 0x13, 0x8092);
3814         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3815         rtl_writephy(tp, 0x1f, 0x0000);
3816
3817         /* enable R-tune & PGA-retune function */
3818         dout_tapbin = 0;
3819         rtl_writephy(tp, 0x1f, 0x0a46);
3820         data = rtl_readphy(tp, 0x13);
3821         data &= 3;
3822         data <<= 2;
3823         dout_tapbin |= data;
3824         data = rtl_readphy(tp, 0x12);
3825         data &= 0xc000;
3826         data >>= 14;
3827         dout_tapbin |= data;
3828         dout_tapbin = ~(dout_tapbin^0x08);
3829         dout_tapbin <<= 12;
3830         dout_tapbin &= 0xf000;
3831         rtl_writephy(tp, 0x1f, 0x0a43);
3832         rtl_writephy(tp, 0x13, 0x827a);
3833         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3834         rtl_writephy(tp, 0x13, 0x827b);
3835         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3836         rtl_writephy(tp, 0x13, 0x827c);
3837         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3838         rtl_writephy(tp, 0x13, 0x827d);
3839         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3840
3841         rtl_writephy(tp, 0x1f, 0x0a43);
3842         rtl_writephy(tp, 0x13, 0x0811);
3843         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3844         rtl_writephy(tp, 0x1f, 0x0a42);
3845         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3846         rtl_writephy(tp, 0x1f, 0x0000);
3847
3848         /* enable GPHY 10M */
3849         rtl_writephy(tp, 0x1f, 0x0a44);
3850         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3851         rtl_writephy(tp, 0x1f, 0x0000);
3852
3853         /* SAR ADC performance */
3854         rtl_writephy(tp, 0x1f, 0x0bca);
3855         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3856         rtl_writephy(tp, 0x1f, 0x0000);
3857
3858         rtl_writephy(tp, 0x1f, 0x0a43);
3859         rtl_writephy(tp, 0x13, 0x803f);
3860         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3861         rtl_writephy(tp, 0x13, 0x8047);
3862         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3863         rtl_writephy(tp, 0x13, 0x804f);
3864         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3865         rtl_writephy(tp, 0x13, 0x8057);
3866         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3867         rtl_writephy(tp, 0x13, 0x805f);
3868         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3869         rtl_writephy(tp, 0x13, 0x8067);
3870         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3871         rtl_writephy(tp, 0x13, 0x806f);
3872         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3873         rtl_writephy(tp, 0x1f, 0x0000);
3874
3875         /* disable phy pfm mode */
3876         rtl_writephy(tp, 0x1f, 0x0a44);
3877         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3878         rtl_writephy(tp, 0x1f, 0x0000);
3879
3880         /* Check ALDPS bit, disable it if enabled */
3881         rtl_writephy(tp, 0x1f, 0x0a43);
3882         if (rtl_readphy(tp, 0x10) & 0x0004)
3883                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3884
3885         rtl_writephy(tp, 0x1f, 0x0000);
3886 }
3887
3888 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3889 {
3890         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3891         u16 rlen;
3892         u32 data;
3893
3894         rtl_apply_firmware(tp);
3895
3896         /* CHIN EST parameter update */
3897         rtl_writephy(tp, 0x1f, 0x0a43);
3898         rtl_writephy(tp, 0x13, 0x808a);
3899         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3900         rtl_writephy(tp, 0x1f, 0x0000);
3901
3902         /* enable R-tune & PGA-retune function */
3903         rtl_writephy(tp, 0x1f, 0x0a43);
3904         rtl_writephy(tp, 0x13, 0x0811);
3905         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3906         rtl_writephy(tp, 0x1f, 0x0a42);
3907         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3908         rtl_writephy(tp, 0x1f, 0x0000);
3909
3910         /* enable GPHY 10M */
3911         rtl_writephy(tp, 0x1f, 0x0a44);
3912         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3913         rtl_writephy(tp, 0x1f, 0x0000);
3914
3915         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3916         data = r8168_mac_ocp_read(tp, 0xdd02);
3917         ioffset_p3 = ((data & 0x80)>>7);
3918         ioffset_p3 <<= 3;
3919
3920         data = r8168_mac_ocp_read(tp, 0xdd00);
3921         ioffset_p3 |= ((data & (0xe000))>>13);
3922         ioffset_p2 = ((data & (0x1e00))>>9);
3923         ioffset_p1 = ((data & (0x01e0))>>5);
3924         ioffset_p0 = ((data & 0x0010)>>4);
3925         ioffset_p0 <<= 3;
3926         ioffset_p0 |= (data & (0x07));
3927         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3928
3929         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3930             (ioffset_p1 != 0x0f) || (ioffset_p0 == 0x0f)) {
3931                 rtl_writephy(tp, 0x1f, 0x0bcf);
3932                 rtl_writephy(tp, 0x16, data);
3933                 rtl_writephy(tp, 0x1f, 0x0000);
3934         }
3935
3936         /* Modify rlen (TX LPF corner frequency) level */
3937         rtl_writephy(tp, 0x1f, 0x0bcd);
3938         data = rtl_readphy(tp, 0x16);
3939         data &= 0x000f;
3940         rlen = 0;
3941         if (data > 3)
3942                 rlen = data - 3;
3943         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3944         rtl_writephy(tp, 0x17, data);
3945         rtl_writephy(tp, 0x1f, 0x0bcd);
3946         rtl_writephy(tp, 0x1f, 0x0000);
3947
3948         /* disable phy pfm mode */
3949         rtl_writephy(tp, 0x1f, 0x0a44);
3950         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3951         rtl_writephy(tp, 0x1f, 0x0000);
3952
3953         /* Check ALDPS bit, disable it if enabled */
3954         rtl_writephy(tp, 0x1f, 0x0a43);
3955         if (rtl_readphy(tp, 0x10) & 0x0004)
3956                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3957
3958         rtl_writephy(tp, 0x1f, 0x0000);
3959 }
3960
3961 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3962 {
3963         /* Enable PHY auto speed down */
3964         rtl_writephy(tp, 0x1f, 0x0a44);
3965         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3966         rtl_writephy(tp, 0x1f, 0x0000);
3967
3968         /* patch 10M & ALDPS */
3969         rtl_writephy(tp, 0x1f, 0x0bcc);
3970         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3971         rtl_writephy(tp, 0x1f, 0x0a44);
3972         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3973         rtl_writephy(tp, 0x1f, 0x0a43);
3974         rtl_writephy(tp, 0x13, 0x8084);
3975         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3976         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3977         rtl_writephy(tp, 0x1f, 0x0000);
3978
3979         /* Enable EEE auto-fallback function */
3980         rtl_writephy(tp, 0x1f, 0x0a4b);
3981         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3982         rtl_writephy(tp, 0x1f, 0x0000);
3983
3984         /* Enable UC LPF tune function */
3985         rtl_writephy(tp, 0x1f, 0x0a43);
3986         rtl_writephy(tp, 0x13, 0x8012);
3987         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3988         rtl_writephy(tp, 0x1f, 0x0000);
3989
3990         /* set rg_sel_sdm_rate */
3991         rtl_writephy(tp, 0x1f, 0x0c42);
3992         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3993         rtl_writephy(tp, 0x1f, 0x0000);
3994
3995         /* Check ALDPS bit, disable it if enabled */
3996         rtl_writephy(tp, 0x1f, 0x0a43);
3997         if (rtl_readphy(tp, 0x10) & 0x0004)
3998                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3999
4000         rtl_writephy(tp, 0x1f, 0x0000);
4001 }
4002
4003 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4004 {
4005         /* patch 10M & ALDPS */
4006         rtl_writephy(tp, 0x1f, 0x0bcc);
4007         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4008         rtl_writephy(tp, 0x1f, 0x0a44);
4009         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4010         rtl_writephy(tp, 0x1f, 0x0a43);
4011         rtl_writephy(tp, 0x13, 0x8084);
4012         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4013         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4014         rtl_writephy(tp, 0x1f, 0x0000);
4015
4016         /* Enable UC LPF tune function */
4017         rtl_writephy(tp, 0x1f, 0x0a43);
4018         rtl_writephy(tp, 0x13, 0x8012);
4019         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4020         rtl_writephy(tp, 0x1f, 0x0000);
4021
4022         /* Set rg_sel_sdm_rate */
4023         rtl_writephy(tp, 0x1f, 0x0c42);
4024         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4025         rtl_writephy(tp, 0x1f, 0x0000);
4026
4027         /* Channel estimation parameters */
4028         rtl_writephy(tp, 0x1f, 0x0a43);
4029         rtl_writephy(tp, 0x13, 0x80f3);
4030         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4031         rtl_writephy(tp, 0x13, 0x80f0);
4032         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4033         rtl_writephy(tp, 0x13, 0x80ef);
4034         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4035         rtl_writephy(tp, 0x13, 0x80f6);
4036         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4037         rtl_writephy(tp, 0x13, 0x80ec);
4038         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4039         rtl_writephy(tp, 0x13, 0x80ed);
4040         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4041         rtl_writephy(tp, 0x13, 0x80f2);
4042         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4043         rtl_writephy(tp, 0x13, 0x80f4);
4044         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4045         rtl_writephy(tp, 0x1f, 0x0a43);
4046         rtl_writephy(tp, 0x13, 0x8110);
4047         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4048         rtl_writephy(tp, 0x13, 0x810f);
4049         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4050         rtl_writephy(tp, 0x13, 0x8111);
4051         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4052         rtl_writephy(tp, 0x13, 0x8113);
4053         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4054         rtl_writephy(tp, 0x13, 0x8115);
4055         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4056         rtl_writephy(tp, 0x13, 0x810e);
4057         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4058         rtl_writephy(tp, 0x13, 0x810c);
4059         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4060         rtl_writephy(tp, 0x13, 0x810b);
4061         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4062         rtl_writephy(tp, 0x1f, 0x0a43);
4063         rtl_writephy(tp, 0x13, 0x80d1);
4064         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4065         rtl_writephy(tp, 0x13, 0x80cd);
4066         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4067         rtl_writephy(tp, 0x13, 0x80d3);
4068         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4069         rtl_writephy(tp, 0x13, 0x80d5);
4070         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4071         rtl_writephy(tp, 0x13, 0x80d7);
4072         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4073
4074         /* Force PWM-mode */
4075         rtl_writephy(tp, 0x1f, 0x0bcd);
4076         rtl_writephy(tp, 0x14, 0x5065);
4077         rtl_writephy(tp, 0x14, 0xd065);
4078         rtl_writephy(tp, 0x1f, 0x0bc8);
4079         rtl_writephy(tp, 0x12, 0x00ed);
4080         rtl_writephy(tp, 0x1f, 0x0bcd);
4081         rtl_writephy(tp, 0x14, 0x1065);
4082         rtl_writephy(tp, 0x14, 0x9065);
4083         rtl_writephy(tp, 0x14, 0x1065);
4084         rtl_writephy(tp, 0x1f, 0x0000);
4085
4086         /* Check ALDPS bit, disable it if enabled */
4087         rtl_writephy(tp, 0x1f, 0x0a43);
4088         if (rtl_readphy(tp, 0x10) & 0x0004)
4089                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4090
4091         rtl_writephy(tp, 0x1f, 0x0000);
4092 }
4093
4094 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4095 {
4096         static const struct phy_reg phy_reg_init[] = {
4097                 { 0x1f, 0x0003 },
4098                 { 0x08, 0x441d },
4099                 { 0x01, 0x9100 },
4100                 { 0x1f, 0x0000 }
4101         };
4102
4103         rtl_writephy(tp, 0x1f, 0x0000);
4104         rtl_patchphy(tp, 0x11, 1 << 12);
4105         rtl_patchphy(tp, 0x19, 1 << 13);
4106         rtl_patchphy(tp, 0x10, 1 << 15);
4107
4108         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4109 }
4110
4111 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4112 {
4113         static const struct phy_reg phy_reg_init[] = {
4114                 { 0x1f, 0x0005 },
4115                 { 0x1a, 0x0000 },
4116                 { 0x1f, 0x0000 },
4117
4118                 { 0x1f, 0x0004 },
4119                 { 0x1c, 0x0000 },
4120                 { 0x1f, 0x0000 },
4121
4122                 { 0x1f, 0x0001 },
4123                 { 0x15, 0x7701 },
4124                 { 0x1f, 0x0000 }
4125         };
4126
4127         /* Disable ALDPS before ram code */
4128         rtl_writephy(tp, 0x1f, 0x0000);
4129         rtl_writephy(tp, 0x18, 0x0310);
4130         msleep(100);
4131
4132         rtl_apply_firmware(tp);
4133
4134         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4135 }
4136
4137 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4138 {
4139         /* Disable ALDPS before setting firmware */
4140         rtl_writephy(tp, 0x1f, 0x0000);
4141         rtl_writephy(tp, 0x18, 0x0310);
4142         msleep(20);
4143
4144         rtl_apply_firmware(tp);
4145
4146         /* EEE setting */
4147         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4148         rtl_writephy(tp, 0x1f, 0x0004);
4149         rtl_writephy(tp, 0x10, 0x401f);
4150         rtl_writephy(tp, 0x19, 0x7030);
4151         rtl_writephy(tp, 0x1f, 0x0000);
4152 }
4153
4154 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4155 {
4156         static const struct phy_reg phy_reg_init[] = {
4157                 { 0x1f, 0x0004 },
4158                 { 0x10, 0xc07f },
4159                 { 0x19, 0x7030 },
4160                 { 0x1f, 0x0000 }
4161         };
4162
4163         /* Disable ALDPS before ram code */
4164         rtl_writephy(tp, 0x1f, 0x0000);
4165         rtl_writephy(tp, 0x18, 0x0310);
4166         msleep(100);
4167
4168         rtl_apply_firmware(tp);
4169
4170         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4171         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4172
4173         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4174 }
4175
4176 static void rtl_hw_phy_config(struct net_device *dev)
4177 {
4178         struct rtl8169_private *tp = netdev_priv(dev);
4179
4180         rtl8169_print_mac_version(tp);
4181
4182         switch (tp->mac_version) {
4183         case RTL_GIGA_MAC_VER_01:
4184                 break;
4185         case RTL_GIGA_MAC_VER_02:
4186         case RTL_GIGA_MAC_VER_03:
4187                 rtl8169s_hw_phy_config(tp);
4188                 break;
4189         case RTL_GIGA_MAC_VER_04:
4190                 rtl8169sb_hw_phy_config(tp);
4191                 break;
4192         case RTL_GIGA_MAC_VER_05:
4193                 rtl8169scd_hw_phy_config(tp);
4194                 break;
4195         case RTL_GIGA_MAC_VER_06:
4196                 rtl8169sce_hw_phy_config(tp);
4197                 break;
4198         case RTL_GIGA_MAC_VER_07:
4199         case RTL_GIGA_MAC_VER_08:
4200         case RTL_GIGA_MAC_VER_09:
4201                 rtl8102e_hw_phy_config(tp);
4202                 break;
4203         case RTL_GIGA_MAC_VER_11:
4204                 rtl8168bb_hw_phy_config(tp);
4205                 break;
4206         case RTL_GIGA_MAC_VER_12:
4207                 rtl8168bef_hw_phy_config(tp);
4208                 break;
4209         case RTL_GIGA_MAC_VER_17:
4210                 rtl8168bef_hw_phy_config(tp);
4211                 break;
4212         case RTL_GIGA_MAC_VER_18:
4213                 rtl8168cp_1_hw_phy_config(tp);
4214                 break;
4215         case RTL_GIGA_MAC_VER_19:
4216                 rtl8168c_1_hw_phy_config(tp);
4217                 break;
4218         case RTL_GIGA_MAC_VER_20:
4219                 rtl8168c_2_hw_phy_config(tp);
4220                 break;
4221         case RTL_GIGA_MAC_VER_21:
4222                 rtl8168c_3_hw_phy_config(tp);
4223                 break;
4224         case RTL_GIGA_MAC_VER_22:
4225                 rtl8168c_4_hw_phy_config(tp);
4226                 break;
4227         case RTL_GIGA_MAC_VER_23:
4228         case RTL_GIGA_MAC_VER_24:
4229                 rtl8168cp_2_hw_phy_config(tp);
4230                 break;
4231         case RTL_GIGA_MAC_VER_25:
4232                 rtl8168d_1_hw_phy_config(tp);
4233                 break;
4234         case RTL_GIGA_MAC_VER_26:
4235                 rtl8168d_2_hw_phy_config(tp);
4236                 break;
4237         case RTL_GIGA_MAC_VER_27:
4238                 rtl8168d_3_hw_phy_config(tp);
4239                 break;
4240         case RTL_GIGA_MAC_VER_28:
4241                 rtl8168d_4_hw_phy_config(tp);
4242                 break;
4243         case RTL_GIGA_MAC_VER_29:
4244         case RTL_GIGA_MAC_VER_30:
4245                 rtl8105e_hw_phy_config(tp);
4246                 break;
4247         case RTL_GIGA_MAC_VER_31:
4248                 /* None. */
4249                 break;
4250         case RTL_GIGA_MAC_VER_32:
4251         case RTL_GIGA_MAC_VER_33:
4252                 rtl8168e_1_hw_phy_config(tp);
4253                 break;
4254         case RTL_GIGA_MAC_VER_34:
4255                 rtl8168e_2_hw_phy_config(tp);
4256                 break;
4257         case RTL_GIGA_MAC_VER_35:
4258                 rtl8168f_1_hw_phy_config(tp);
4259                 break;
4260         case RTL_GIGA_MAC_VER_36:
4261                 rtl8168f_2_hw_phy_config(tp);
4262                 break;
4263
4264         case RTL_GIGA_MAC_VER_37:
4265                 rtl8402_hw_phy_config(tp);
4266                 break;
4267
4268         case RTL_GIGA_MAC_VER_38:
4269                 rtl8411_hw_phy_config(tp);
4270                 break;
4271
4272         case RTL_GIGA_MAC_VER_39:
4273                 rtl8106e_hw_phy_config(tp);
4274                 break;
4275
4276         case RTL_GIGA_MAC_VER_40:
4277                 rtl8168g_1_hw_phy_config(tp);
4278                 break;
4279         case RTL_GIGA_MAC_VER_42:
4280         case RTL_GIGA_MAC_VER_43:
4281         case RTL_GIGA_MAC_VER_44:
4282                 rtl8168g_2_hw_phy_config(tp);
4283                 break;
4284         case RTL_GIGA_MAC_VER_45:
4285         case RTL_GIGA_MAC_VER_47:
4286                 rtl8168h_1_hw_phy_config(tp);
4287                 break;
4288         case RTL_GIGA_MAC_VER_46:
4289         case RTL_GIGA_MAC_VER_48:
4290                 rtl8168h_2_hw_phy_config(tp);
4291                 break;
4292
4293         case RTL_GIGA_MAC_VER_49:
4294                 rtl8168ep_1_hw_phy_config(tp);
4295                 break;
4296         case RTL_GIGA_MAC_VER_50:
4297         case RTL_GIGA_MAC_VER_51:
4298                 rtl8168ep_2_hw_phy_config(tp);
4299                 break;
4300
4301         case RTL_GIGA_MAC_VER_41:
4302         default:
4303                 break;
4304         }
4305 }
4306
4307 static void rtl_phy_work(struct rtl8169_private *tp)
4308 {
4309         struct timer_list *timer = &tp->timer;
4310         void __iomem *ioaddr = tp->mmio_addr;
4311         unsigned long timeout = RTL8169_PHY_TIMEOUT;
4312
4313         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4314
4315         if (tp->phy_reset_pending(tp)) {
4316                 /*
4317                  * A busy loop could burn quite a few cycles on nowadays CPU.
4318                  * Let's delay the execution of the timer for a few ticks.
4319                  */
4320                 timeout = HZ/10;
4321                 goto out_mod_timer;
4322         }
4323
4324         if (tp->link_ok(ioaddr))
4325                 return;
4326
4327         netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4328
4329         tp->phy_reset_enable(tp);
4330
4331 out_mod_timer:
4332         mod_timer(timer, jiffies + timeout);
4333 }
4334
4335 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4336 {
4337         if (!test_and_set_bit(flag, tp->wk.flags))
4338                 schedule_work(&tp->wk.work);
4339 }
4340
4341 static void rtl8169_phy_timer(unsigned long __opaque)
4342 {
4343         struct net_device *dev = (struct net_device *)__opaque;
4344         struct rtl8169_private *tp = netdev_priv(dev);
4345
4346         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4347 }
4348
4349 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4350                                   void __iomem *ioaddr)
4351 {
4352         iounmap(ioaddr);
4353         pci_release_regions(pdev);
4354         pci_clear_mwi(pdev);
4355         pci_disable_device(pdev);
4356         free_netdev(dev);
4357 }
4358
4359 DECLARE_RTL_COND(rtl_phy_reset_cond)
4360 {
4361         return tp->phy_reset_pending(tp);
4362 }
4363
4364 static void rtl8169_phy_reset(struct net_device *dev,
4365                               struct rtl8169_private *tp)
4366 {
4367         tp->phy_reset_enable(tp);
4368         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4369 }
4370
4371 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4372 {
4373         void __iomem *ioaddr = tp->mmio_addr;
4374
4375         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4376             (RTL_R8(PHYstatus) & TBI_Enable);
4377 }
4378
4379 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4380 {
4381         void __iomem *ioaddr = tp->mmio_addr;
4382
4383         rtl_hw_phy_config(dev);
4384
4385         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4386                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4387                 RTL_W8(0x82, 0x01);
4388         }
4389
4390         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4391
4392         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4393                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4394
4395         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4396                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4397                 RTL_W8(0x82, 0x01);
4398                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4399                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4400         }
4401
4402         rtl8169_phy_reset(dev, tp);
4403
4404         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4405                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4406                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4407                           (tp->mii.supports_gmii ?
4408                            ADVERTISED_1000baseT_Half |
4409                            ADVERTISED_1000baseT_Full : 0));
4410
4411         if (rtl_tbi_enabled(tp))
4412                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4413 }
4414
4415 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4416 {
4417         void __iomem *ioaddr = tp->mmio_addr;
4418
4419         rtl_lock_work(tp);
4420
4421         RTL_W8(Cfg9346, Cfg9346_Unlock);
4422
4423         RTL_W32(MAC4, addr[4] | addr[5] << 8);
4424         RTL_R32(MAC4);
4425
4426         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4427         RTL_R32(MAC0);
4428
4429         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4430                 rtl_rar_exgmac_set(tp, addr);
4431
4432         RTL_W8(Cfg9346, Cfg9346_Lock);
4433
4434         rtl_unlock_work(tp);
4435 }
4436
4437 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4438 {
4439         void __iomem *ioaddr = tp->mmio_addr;
4440
4441         switch (tp->mac_version) {
4442         case RTL_GIGA_MAC_VER_01:
4443         case RTL_GIGA_MAC_VER_02:
4444         case RTL_GIGA_MAC_VER_03:
4445         case RTL_GIGA_MAC_VER_04:
4446         case RTL_GIGA_MAC_VER_05:
4447         case RTL_GIGA_MAC_VER_06:
4448         case RTL_GIGA_MAC_VER_10:
4449         case RTL_GIGA_MAC_VER_11:
4450         case RTL_GIGA_MAC_VER_12:
4451         case RTL_GIGA_MAC_VER_13:
4452         case RTL_GIGA_MAC_VER_14:
4453         case RTL_GIGA_MAC_VER_15:
4454         case RTL_GIGA_MAC_VER_16:
4455         case RTL_GIGA_MAC_VER_17:
4456                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4457                 break;
4458         case RTL_GIGA_MAC_VER_18:
4459         case RTL_GIGA_MAC_VER_19:
4460         case RTL_GIGA_MAC_VER_20:
4461         case RTL_GIGA_MAC_VER_21:
4462         case RTL_GIGA_MAC_VER_22:
4463         case RTL_GIGA_MAC_VER_23:
4464         case RTL_GIGA_MAC_VER_24:
4465         case RTL_GIGA_MAC_VER_34:
4466         case RTL_GIGA_MAC_VER_35:
4467                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4468                 break;
4469         case RTL_GIGA_MAC_VER_40:
4470                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4471                 break;
4472         case RTL_GIGA_MAC_VER_41:
4473         case RTL_GIGA_MAC_VER_42:
4474         case RTL_GIGA_MAC_VER_43:
4475         case RTL_GIGA_MAC_VER_44:
4476         case RTL_GIGA_MAC_VER_45:
4477         case RTL_GIGA_MAC_VER_46:
4478         case RTL_GIGA_MAC_VER_47:
4479         case RTL_GIGA_MAC_VER_48:
4480                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4481                 break;
4482         case RTL_GIGA_MAC_VER_49:
4483         case RTL_GIGA_MAC_VER_50:
4484         case RTL_GIGA_MAC_VER_51:
4485                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4486                 break;
4487         default:
4488                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4489                 break;
4490         }
4491 }
4492
4493 static int rtl_set_mac_address(struct net_device *dev, void *p)
4494 {
4495         struct rtl8169_private *tp = netdev_priv(dev);
4496         struct sockaddr *addr = p;
4497
4498         if (!is_valid_ether_addr(addr->sa_data))
4499                 return -EADDRNOTAVAIL;
4500
4501         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4502
4503         rtl_rar_set(tp, dev->dev_addr);
4504
4505         /* Reportedly at least Asus X453MA truncates packets otherwise */
4506         if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4507                 rtl_init_rxcfg(tp);
4508
4509         return 0;
4510 }
4511
4512 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4513 {
4514         struct rtl8169_private *tp = netdev_priv(dev);
4515         struct mii_ioctl_data *data = if_mii(ifr);
4516
4517         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4518 }
4519
4520 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4521                           struct mii_ioctl_data *data, int cmd)
4522 {
4523         switch (cmd) {
4524         case SIOCGMIIPHY:
4525                 data->phy_id = 32; /* Internal PHY */
4526                 return 0;
4527
4528         case SIOCGMIIREG:
4529                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4530                 return 0;
4531
4532         case SIOCSMIIREG:
4533                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4534                 return 0;
4535         }
4536         return -EOPNOTSUPP;
4537 }
4538
4539 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4540 {
4541         return -EOPNOTSUPP;
4542 }
4543
4544 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4545 {
4546         if (tp->features & RTL_FEATURE_MSI) {
4547                 pci_disable_msi(pdev);
4548                 tp->features &= ~RTL_FEATURE_MSI;
4549         }
4550 }
4551
4552 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4553 {
4554         struct mdio_ops *ops = &tp->mdio_ops;
4555
4556         switch (tp->mac_version) {
4557         case RTL_GIGA_MAC_VER_27:
4558                 ops->write      = r8168dp_1_mdio_write;
4559                 ops->read       = r8168dp_1_mdio_read;
4560                 break;
4561         case RTL_GIGA_MAC_VER_28:
4562         case RTL_GIGA_MAC_VER_31:
4563                 ops->write      = r8168dp_2_mdio_write;
4564                 ops->read       = r8168dp_2_mdio_read;
4565                 break;
4566         case RTL_GIGA_MAC_VER_40:
4567         case RTL_GIGA_MAC_VER_41:
4568         case RTL_GIGA_MAC_VER_42:
4569         case RTL_GIGA_MAC_VER_43:
4570         case RTL_GIGA_MAC_VER_44:
4571         case RTL_GIGA_MAC_VER_45:
4572         case RTL_GIGA_MAC_VER_46:
4573         case RTL_GIGA_MAC_VER_47:
4574         case RTL_GIGA_MAC_VER_48:
4575         case RTL_GIGA_MAC_VER_49:
4576         case RTL_GIGA_MAC_VER_50:
4577         case RTL_GIGA_MAC_VER_51:
4578                 ops->write      = r8168g_mdio_write;
4579                 ops->read       = r8168g_mdio_read;
4580                 break;
4581         default:
4582                 ops->write      = r8169_mdio_write;
4583                 ops->read       = r8169_mdio_read;
4584                 break;
4585         }
4586 }
4587
4588 static void rtl_speed_down(struct rtl8169_private *tp)
4589 {
4590         u32 adv;
4591         int lpa;
4592
4593         rtl_writephy(tp, 0x1f, 0x0000);
4594         lpa = rtl_readphy(tp, MII_LPA);
4595
4596         if (lpa & (LPA_10HALF | LPA_10FULL))
4597                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4598         else if (lpa & (LPA_100HALF | LPA_100FULL))
4599                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4600                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4601         else
4602                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4603                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4604                       (tp->mii.supports_gmii ?
4605                        ADVERTISED_1000baseT_Half |
4606                        ADVERTISED_1000baseT_Full : 0);
4607
4608         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4609                           adv);
4610 }
4611
4612 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4613 {
4614         void __iomem *ioaddr = tp->mmio_addr;
4615
4616         switch (tp->mac_version) {
4617         case RTL_GIGA_MAC_VER_25:
4618         case RTL_GIGA_MAC_VER_26:
4619         case RTL_GIGA_MAC_VER_29:
4620         case RTL_GIGA_MAC_VER_30:
4621         case RTL_GIGA_MAC_VER_32:
4622         case RTL_GIGA_MAC_VER_33:
4623         case RTL_GIGA_MAC_VER_34:
4624         case RTL_GIGA_MAC_VER_37:
4625         case RTL_GIGA_MAC_VER_38:
4626         case RTL_GIGA_MAC_VER_39:
4627         case RTL_GIGA_MAC_VER_40:
4628         case RTL_GIGA_MAC_VER_41:
4629         case RTL_GIGA_MAC_VER_42:
4630         case RTL_GIGA_MAC_VER_43:
4631         case RTL_GIGA_MAC_VER_44:
4632         case RTL_GIGA_MAC_VER_45:
4633         case RTL_GIGA_MAC_VER_46:
4634         case RTL_GIGA_MAC_VER_47:
4635         case RTL_GIGA_MAC_VER_48:
4636         case RTL_GIGA_MAC_VER_49:
4637         case RTL_GIGA_MAC_VER_50:
4638         case RTL_GIGA_MAC_VER_51:
4639                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4640                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4641                 break;
4642         default:
4643                 break;
4644         }
4645 }
4646
4647 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4648 {
4649         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4650                 return false;
4651
4652         rtl_speed_down(tp);
4653         rtl_wol_suspend_quirk(tp);
4654
4655         return true;
4656 }
4657
4658 static void r810x_phy_power_down(struct rtl8169_private *tp)
4659 {
4660         rtl_writephy(tp, 0x1f, 0x0000);
4661         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4662 }
4663
4664 static void r810x_phy_power_up(struct rtl8169_private *tp)
4665 {
4666         rtl_writephy(tp, 0x1f, 0x0000);
4667         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4668 }
4669
4670 static void r810x_pll_power_down(struct rtl8169_private *tp)
4671 {
4672         void __iomem *ioaddr = tp->mmio_addr;
4673
4674         if (rtl_wol_pll_power_down(tp))
4675                 return;
4676
4677         r810x_phy_power_down(tp);
4678
4679         switch (tp->mac_version) {
4680         case RTL_GIGA_MAC_VER_07:
4681         case RTL_GIGA_MAC_VER_08:
4682         case RTL_GIGA_MAC_VER_09:
4683         case RTL_GIGA_MAC_VER_10:
4684         case RTL_GIGA_MAC_VER_13:
4685         case RTL_GIGA_MAC_VER_16:
4686                 break;
4687         default:
4688                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4689                 break;
4690         }
4691 }
4692
4693 static void r810x_pll_power_up(struct rtl8169_private *tp)
4694 {
4695         void __iomem *ioaddr = tp->mmio_addr;
4696
4697         r810x_phy_power_up(tp);
4698
4699         switch (tp->mac_version) {
4700         case RTL_GIGA_MAC_VER_07:
4701         case RTL_GIGA_MAC_VER_08:
4702         case RTL_GIGA_MAC_VER_09:
4703         case RTL_GIGA_MAC_VER_10:
4704         case RTL_GIGA_MAC_VER_13:
4705         case RTL_GIGA_MAC_VER_16:
4706                 break;
4707         case RTL_GIGA_MAC_VER_47:
4708         case RTL_GIGA_MAC_VER_48:
4709                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4710                 break;
4711         default:
4712                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4713                 break;
4714         }
4715 }
4716
4717 static void r8168_phy_power_up(struct rtl8169_private *tp)
4718 {
4719         rtl_writephy(tp, 0x1f, 0x0000);
4720         switch (tp->mac_version) {
4721         case RTL_GIGA_MAC_VER_11:
4722         case RTL_GIGA_MAC_VER_12:
4723         case RTL_GIGA_MAC_VER_17:
4724         case RTL_GIGA_MAC_VER_18:
4725         case RTL_GIGA_MAC_VER_19:
4726         case RTL_GIGA_MAC_VER_20:
4727         case RTL_GIGA_MAC_VER_21:
4728         case RTL_GIGA_MAC_VER_22:
4729         case RTL_GIGA_MAC_VER_23:
4730         case RTL_GIGA_MAC_VER_24:
4731         case RTL_GIGA_MAC_VER_25:
4732         case RTL_GIGA_MAC_VER_26:
4733         case RTL_GIGA_MAC_VER_27:
4734         case RTL_GIGA_MAC_VER_28:
4735         case RTL_GIGA_MAC_VER_31:
4736                 rtl_writephy(tp, 0x0e, 0x0000);
4737                 break;
4738         default:
4739                 break;
4740         }
4741         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4742 }
4743
4744 static void r8168_phy_power_down(struct rtl8169_private *tp)
4745 {
4746         rtl_writephy(tp, 0x1f, 0x0000);
4747         switch (tp->mac_version) {
4748         case RTL_GIGA_MAC_VER_32:
4749         case RTL_GIGA_MAC_VER_33:
4750         case RTL_GIGA_MAC_VER_40:
4751         case RTL_GIGA_MAC_VER_41:
4752                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4753                 break;
4754
4755         case RTL_GIGA_MAC_VER_11:
4756         case RTL_GIGA_MAC_VER_12:
4757         case RTL_GIGA_MAC_VER_17:
4758         case RTL_GIGA_MAC_VER_18:
4759         case RTL_GIGA_MAC_VER_19:
4760         case RTL_GIGA_MAC_VER_20:
4761         case RTL_GIGA_MAC_VER_21:
4762         case RTL_GIGA_MAC_VER_22:
4763         case RTL_GIGA_MAC_VER_23:
4764         case RTL_GIGA_MAC_VER_24:
4765         case RTL_GIGA_MAC_VER_25:
4766         case RTL_GIGA_MAC_VER_26:
4767         case RTL_GIGA_MAC_VER_27:
4768         case RTL_GIGA_MAC_VER_28:
4769         case RTL_GIGA_MAC_VER_31:
4770                 rtl_writephy(tp, 0x0e, 0x0200);
4771         default:
4772                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4773                 break;
4774         }
4775 }
4776
4777 static void r8168_pll_power_down(struct rtl8169_private *tp)
4778 {
4779         void __iomem *ioaddr = tp->mmio_addr;
4780
4781         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4782              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4783              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4784              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4785              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4786              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4787             r8168_check_dash(tp)) {
4788                 return;
4789         }
4790
4791         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4792              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4793             (RTL_R16(CPlusCmd) & ASF)) {
4794                 return;
4795         }
4796
4797         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4798             tp->mac_version == RTL_GIGA_MAC_VER_33)
4799                 rtl_ephy_write(tp, 0x19, 0xff64);
4800
4801         if (rtl_wol_pll_power_down(tp))
4802                 return;
4803
4804         r8168_phy_power_down(tp);
4805
4806         switch (tp->mac_version) {
4807         case RTL_GIGA_MAC_VER_25:
4808         case RTL_GIGA_MAC_VER_26:
4809         case RTL_GIGA_MAC_VER_27:
4810         case RTL_GIGA_MAC_VER_28:
4811         case RTL_GIGA_MAC_VER_31:
4812         case RTL_GIGA_MAC_VER_32:
4813         case RTL_GIGA_MAC_VER_33:
4814         case RTL_GIGA_MAC_VER_44:
4815         case RTL_GIGA_MAC_VER_45:
4816         case RTL_GIGA_MAC_VER_46:
4817         case RTL_GIGA_MAC_VER_50:
4818         case RTL_GIGA_MAC_VER_51:
4819                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4820                 break;
4821         case RTL_GIGA_MAC_VER_40:
4822         case RTL_GIGA_MAC_VER_41:
4823         case RTL_GIGA_MAC_VER_49:
4824                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4825                              0xfc000000, ERIAR_EXGMAC);
4826                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4827                 break;
4828         }
4829 }
4830
4831 static void r8168_pll_power_up(struct rtl8169_private *tp)
4832 {
4833         void __iomem *ioaddr = tp->mmio_addr;
4834
4835         switch (tp->mac_version) {
4836         case RTL_GIGA_MAC_VER_25:
4837         case RTL_GIGA_MAC_VER_26:
4838         case RTL_GIGA_MAC_VER_27:
4839         case RTL_GIGA_MAC_VER_28:
4840         case RTL_GIGA_MAC_VER_31:
4841         case RTL_GIGA_MAC_VER_32:
4842         case RTL_GIGA_MAC_VER_33:
4843                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4844                 break;
4845         case RTL_GIGA_MAC_VER_44:
4846         case RTL_GIGA_MAC_VER_45:
4847         case RTL_GIGA_MAC_VER_46:
4848         case RTL_GIGA_MAC_VER_50:
4849         case RTL_GIGA_MAC_VER_51:
4850                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4851                 break;
4852         case RTL_GIGA_MAC_VER_40:
4853         case RTL_GIGA_MAC_VER_41:
4854         case RTL_GIGA_MAC_VER_49:
4855                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4856                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4857                              0x00000000, ERIAR_EXGMAC);
4858                 break;
4859         }
4860
4861         r8168_phy_power_up(tp);
4862 }
4863
4864 static void rtl_generic_op(struct rtl8169_private *tp,
4865                            void (*op)(struct rtl8169_private *))
4866 {
4867         if (op)
4868                 op(tp);
4869 }
4870
4871 static void rtl_pll_power_down(struct rtl8169_private *tp)
4872 {
4873         rtl_generic_op(tp, tp->pll_power_ops.down);
4874 }
4875
4876 static void rtl_pll_power_up(struct rtl8169_private *tp)
4877 {
4878         rtl_generic_op(tp, tp->pll_power_ops.up);
4879
4880         /* give MAC/PHY some time to resume */
4881         msleep(20);
4882 }
4883
4884 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4885 {
4886         struct pll_power_ops *ops = &tp->pll_power_ops;
4887
4888         switch (tp->mac_version) {
4889         case RTL_GIGA_MAC_VER_07:
4890         case RTL_GIGA_MAC_VER_08:
4891         case RTL_GIGA_MAC_VER_09:
4892         case RTL_GIGA_MAC_VER_10:
4893         case RTL_GIGA_MAC_VER_16:
4894         case RTL_GIGA_MAC_VER_29:
4895         case RTL_GIGA_MAC_VER_30:
4896         case RTL_GIGA_MAC_VER_37:
4897         case RTL_GIGA_MAC_VER_39:
4898         case RTL_GIGA_MAC_VER_43:
4899         case RTL_GIGA_MAC_VER_47:
4900         case RTL_GIGA_MAC_VER_48:
4901                 ops->down       = r810x_pll_power_down;
4902                 ops->up         = r810x_pll_power_up;
4903                 break;
4904
4905         case RTL_GIGA_MAC_VER_11:
4906         case RTL_GIGA_MAC_VER_12:
4907         case RTL_GIGA_MAC_VER_17:
4908         case RTL_GIGA_MAC_VER_18:
4909         case RTL_GIGA_MAC_VER_19:
4910         case RTL_GIGA_MAC_VER_20:
4911         case RTL_GIGA_MAC_VER_21:
4912         case RTL_GIGA_MAC_VER_22:
4913         case RTL_GIGA_MAC_VER_23:
4914         case RTL_GIGA_MAC_VER_24:
4915         case RTL_GIGA_MAC_VER_25:
4916         case RTL_GIGA_MAC_VER_26:
4917         case RTL_GIGA_MAC_VER_27:
4918         case RTL_GIGA_MAC_VER_28:
4919         case RTL_GIGA_MAC_VER_31:
4920         case RTL_GIGA_MAC_VER_32:
4921         case RTL_GIGA_MAC_VER_33:
4922         case RTL_GIGA_MAC_VER_34:
4923         case RTL_GIGA_MAC_VER_35:
4924         case RTL_GIGA_MAC_VER_36:
4925         case RTL_GIGA_MAC_VER_38:
4926         case RTL_GIGA_MAC_VER_40:
4927         case RTL_GIGA_MAC_VER_41:
4928         case RTL_GIGA_MAC_VER_42:
4929         case RTL_GIGA_MAC_VER_44:
4930         case RTL_GIGA_MAC_VER_45:
4931         case RTL_GIGA_MAC_VER_46:
4932         case RTL_GIGA_MAC_VER_49:
4933         case RTL_GIGA_MAC_VER_50:
4934         case RTL_GIGA_MAC_VER_51:
4935                 ops->down       = r8168_pll_power_down;
4936                 ops->up         = r8168_pll_power_up;
4937                 break;
4938
4939         default:
4940                 ops->down       = NULL;
4941                 ops->up         = NULL;
4942                 break;
4943         }
4944 }
4945
4946 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4947 {
4948         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4949 }
4950
4951 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4952 {
4953         void __iomem *ioaddr = tp->mmio_addr;
4954
4955         RTL_W8(Cfg9346, Cfg9346_Unlock);
4956         rtl_generic_op(tp, tp->jumbo_ops.enable);
4957         RTL_W8(Cfg9346, Cfg9346_Lock);
4958 }
4959
4960 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4961 {
4962         void __iomem *ioaddr = tp->mmio_addr;
4963
4964         RTL_W8(Cfg9346, Cfg9346_Unlock);
4965         rtl_generic_op(tp, tp->jumbo_ops.disable);
4966         RTL_W8(Cfg9346, Cfg9346_Lock);
4967 }
4968
4969 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4970 {
4971         void __iomem *ioaddr = tp->mmio_addr;
4972
4973         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4974         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4975         rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
4976 }
4977
4978 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4979 {
4980         void __iomem *ioaddr = tp->mmio_addr;
4981
4982         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4983         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4984         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4985 }
4986
4987 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4988 {
4989         void __iomem *ioaddr = tp->mmio_addr;
4990
4991         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4992 }
4993
4994 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4995 {
4996         void __iomem *ioaddr = tp->mmio_addr;
4997
4998         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4999 }
5000
5001 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5002 {
5003         void __iomem *ioaddr = tp->mmio_addr;
5004
5005         RTL_W8(MaxTxPacketSize, 0x3f);
5006         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5007         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
5008         rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5009 }
5010
5011 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5012 {
5013         void __iomem *ioaddr = tp->mmio_addr;
5014
5015         RTL_W8(MaxTxPacketSize, 0x0c);
5016         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5017         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
5018         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5019 }
5020
5021 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5022 {
5023         rtl_tx_performance_tweak(tp->pci_dev,
5024                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5025 }
5026
5027 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5028 {
5029         rtl_tx_performance_tweak(tp->pci_dev,
5030                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5031 }
5032
5033 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5034 {
5035         void __iomem *ioaddr = tp->mmio_addr;
5036
5037         r8168b_0_hw_jumbo_enable(tp);
5038
5039         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5040 }
5041
5042 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5043 {
5044         void __iomem *ioaddr = tp->mmio_addr;
5045
5046         r8168b_0_hw_jumbo_disable(tp);
5047
5048         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5049 }
5050
5051 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5052 {
5053         struct jumbo_ops *ops = &tp->jumbo_ops;
5054
5055         switch (tp->mac_version) {
5056         case RTL_GIGA_MAC_VER_11:
5057                 ops->disable    = r8168b_0_hw_jumbo_disable;
5058                 ops->enable     = r8168b_0_hw_jumbo_enable;
5059                 break;
5060         case RTL_GIGA_MAC_VER_12:
5061         case RTL_GIGA_MAC_VER_17:
5062                 ops->disable    = r8168b_1_hw_jumbo_disable;
5063                 ops->enable     = r8168b_1_hw_jumbo_enable;
5064                 break;
5065         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5066         case RTL_GIGA_MAC_VER_19:
5067         case RTL_GIGA_MAC_VER_20:
5068         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5069         case RTL_GIGA_MAC_VER_22:
5070         case RTL_GIGA_MAC_VER_23:
5071         case RTL_GIGA_MAC_VER_24:
5072         case RTL_GIGA_MAC_VER_25:
5073         case RTL_GIGA_MAC_VER_26:
5074                 ops->disable    = r8168c_hw_jumbo_disable;
5075                 ops->enable     = r8168c_hw_jumbo_enable;
5076                 break;
5077         case RTL_GIGA_MAC_VER_27:
5078         case RTL_GIGA_MAC_VER_28:
5079                 ops->disable    = r8168dp_hw_jumbo_disable;
5080                 ops->enable     = r8168dp_hw_jumbo_enable;
5081                 break;
5082         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5083         case RTL_GIGA_MAC_VER_32:
5084         case RTL_GIGA_MAC_VER_33:
5085         case RTL_GIGA_MAC_VER_34:
5086                 ops->disable    = r8168e_hw_jumbo_disable;
5087                 ops->enable     = r8168e_hw_jumbo_enable;
5088                 break;
5089
5090         /*
5091          * No action needed for jumbo frames with 8169.
5092          * No jumbo for 810x at all.
5093          */
5094         case RTL_GIGA_MAC_VER_40:
5095         case RTL_GIGA_MAC_VER_41:
5096         case RTL_GIGA_MAC_VER_42:
5097         case RTL_GIGA_MAC_VER_43:
5098         case RTL_GIGA_MAC_VER_44:
5099         case RTL_GIGA_MAC_VER_45:
5100         case RTL_GIGA_MAC_VER_46:
5101         case RTL_GIGA_MAC_VER_47:
5102         case RTL_GIGA_MAC_VER_48:
5103         case RTL_GIGA_MAC_VER_49:
5104         case RTL_GIGA_MAC_VER_50:
5105         case RTL_GIGA_MAC_VER_51:
5106         default:
5107                 ops->disable    = NULL;
5108                 ops->enable     = NULL;
5109                 break;
5110         }
5111 }
5112
5113 DECLARE_RTL_COND(rtl_chipcmd_cond)
5114 {
5115         void __iomem *ioaddr = tp->mmio_addr;
5116
5117         return RTL_R8(ChipCmd) & CmdReset;
5118 }
5119
5120 static void rtl_hw_reset(struct rtl8169_private *tp)
5121 {
5122         void __iomem *ioaddr = tp->mmio_addr;
5123
5124         RTL_W8(ChipCmd, CmdReset);
5125
5126         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5127 }
5128
5129 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5130 {
5131         struct rtl_fw *rtl_fw;
5132         const char *name;
5133         int rc = -ENOMEM;
5134
5135         name = rtl_lookup_firmware_name(tp);
5136         if (!name)
5137                 goto out_no_firmware;
5138
5139         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5140         if (!rtl_fw)
5141                 goto err_warn;
5142
5143         rc = reject_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5144         if (rc < 0)
5145                 goto err_free;
5146
5147         rc = rtl_check_firmware(tp, rtl_fw);
5148         if (rc < 0)
5149                 goto err_release_firmware;
5150
5151         tp->rtl_fw = rtl_fw;
5152 out:
5153         return;
5154
5155 err_release_firmware:
5156         release_firmware(rtl_fw->fw);
5157 err_free:
5158         kfree(rtl_fw);
5159 err_warn:
5160         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5161                    name, rc);
5162 out_no_firmware:
5163         tp->rtl_fw = NULL;
5164         goto out;
5165 }
5166
5167 static void rtl_request_firmware(struct rtl8169_private *tp)
5168 {
5169         if (IS_ERR(tp->rtl_fw))
5170                 rtl_request_uncached_firmware(tp);
5171 }
5172
5173 static void rtl_rx_close(struct rtl8169_private *tp)
5174 {
5175         void __iomem *ioaddr = tp->mmio_addr;
5176
5177         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5178 }
5179
5180 DECLARE_RTL_COND(rtl_npq_cond)
5181 {
5182         void __iomem *ioaddr = tp->mmio_addr;
5183
5184         return RTL_R8(TxPoll) & NPQ;
5185 }
5186
5187 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5188 {
5189         void __iomem *ioaddr = tp->mmio_addr;
5190
5191         return RTL_R32(TxConfig) & TXCFG_EMPTY;
5192 }
5193
5194 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5195 {
5196         void __iomem *ioaddr = tp->mmio_addr;
5197
5198         /* Disable interrupts */
5199         rtl8169_irq_mask_and_ack(tp);
5200
5201         rtl_rx_close(tp);
5202
5203         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5204             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5205             tp->mac_version == RTL_GIGA_MAC_VER_31) {
5206                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5207         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5208                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5209                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5210                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5211                    tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5212                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5213                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5214                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5215                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5216                    tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5217                    tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5218                    tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5219                    tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5220                    tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5221                    tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5222                    tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5223                    tp->mac_version == RTL_GIGA_MAC_VER_51) {
5224                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5225                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5226         } else {
5227                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5228                 udelay(100);
5229         }
5230
5231         rtl_hw_reset(tp);
5232 }
5233
5234 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5235 {
5236         void __iomem *ioaddr = tp->mmio_addr;
5237
5238         /* Set DMA burst size and Interframe Gap Time */
5239         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5240                 (InterFrameGap << TxInterFrameGapShift));
5241 }
5242
5243 static void rtl_hw_start(struct net_device *dev)
5244 {
5245         struct rtl8169_private *tp = netdev_priv(dev);
5246
5247         tp->hw_start(dev);
5248
5249         rtl_irq_enable_all(tp);
5250 }
5251
5252 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5253                                          void __iomem *ioaddr)
5254 {
5255         /*
5256          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5257          * register to be written before TxDescAddrLow to work.
5258          * Switching from MMIO to I/O access fixes the issue as well.
5259          */
5260         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5261         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5262         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5263         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5264 }
5265
5266 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5267 {
5268         u16 cmd;
5269
5270         cmd = RTL_R16(CPlusCmd);
5271         RTL_W16(CPlusCmd, cmd);
5272         return cmd;
5273 }
5274
5275 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5276 {
5277         /* Low hurts. Let's disable the filtering. */
5278         RTL_W16(RxMaxSize, rx_buf_sz + 1);
5279 }
5280
5281 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5282 {
5283         static const struct rtl_cfg2_info {
5284                 u32 mac_version;
5285                 u32 clk;
5286                 u32 val;
5287         } cfg2_info [] = {
5288                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5289                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5290                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5291                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5292         };
5293         const struct rtl_cfg2_info *p = cfg2_info;
5294         unsigned int i;
5295         u32 clk;
5296
5297         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5298         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5299                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5300                         RTL_W32(0x7c, p->val);
5301                         break;
5302                 }
5303         }
5304 }
5305
5306 static void rtl_set_rx_mode(struct net_device *dev)
5307 {
5308         struct rtl8169_private *tp = netdev_priv(dev);
5309         void __iomem *ioaddr = tp->mmio_addr;
5310         u32 mc_filter[2];       /* Multicast hash filter */
5311         int rx_mode;
5312         u32 tmp = 0;
5313
5314         if (dev->flags & IFF_PROMISC) {
5315                 /* Unconditionally log net taps. */
5316                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5317                 rx_mode =
5318                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5319                     AcceptAllPhys;
5320                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5321         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5322                    (dev->flags & IFF_ALLMULTI)) {
5323                 /* Too many to filter perfectly -- accept all multicasts. */
5324                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5325                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5326         } else {
5327                 struct netdev_hw_addr *ha;
5328
5329                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5330                 mc_filter[1] = mc_filter[0] = 0;
5331                 netdev_for_each_mc_addr(ha, dev) {
5332                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5333                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5334                         rx_mode |= AcceptMulticast;
5335                 }
5336         }
5337
5338         if (dev->features & NETIF_F_RXALL)
5339                 rx_mode |= (AcceptErr | AcceptRunt);
5340
5341         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5342
5343         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5344                 u32 data = mc_filter[0];
5345
5346                 mc_filter[0] = swab32(mc_filter[1]);
5347                 mc_filter[1] = swab32(data);
5348         }
5349
5350         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5351                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5352
5353         RTL_W32(MAR0 + 4, mc_filter[1]);
5354         RTL_W32(MAR0 + 0, mc_filter[0]);
5355
5356         RTL_W32(RxConfig, tmp);
5357 }
5358
5359 static void rtl_hw_start_8169(struct net_device *dev)
5360 {
5361         struct rtl8169_private *tp = netdev_priv(dev);
5362         void __iomem *ioaddr = tp->mmio_addr;
5363         struct pci_dev *pdev = tp->pci_dev;
5364
5365         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5366                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5367                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5368         }
5369
5370         RTL_W8(Cfg9346, Cfg9346_Unlock);
5371         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5372             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5373             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5374             tp->mac_version == RTL_GIGA_MAC_VER_04)
5375                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5376
5377         rtl_init_rxcfg(tp);
5378
5379         RTL_W8(EarlyTxThres, NoEarlyTx);
5380
5381         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5382
5383         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5384             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5385             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5386             tp->mac_version == RTL_GIGA_MAC_VER_04)
5387                 rtl_set_rx_tx_config_registers(tp);
5388
5389         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5390
5391         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5392             tp->mac_version == RTL_GIGA_MAC_VER_03) {
5393                 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5394                         "Bit-3 and bit-14 MUST be 1\n");
5395                 tp->cp_cmd |= (1 << 14);
5396         }
5397
5398         RTL_W16(CPlusCmd, tp->cp_cmd);
5399
5400         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5401
5402         /*
5403          * Undocumented corner. Supposedly:
5404          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5405          */
5406         RTL_W16(IntrMitigate, 0x0000);
5407
5408         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5409
5410         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5411             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5412             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5413             tp->mac_version != RTL_GIGA_MAC_VER_04) {
5414                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5415                 rtl_set_rx_tx_config_registers(tp);
5416         }
5417
5418         RTL_W8(Cfg9346, Cfg9346_Lock);
5419
5420         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5421         RTL_R8(IntrMask);
5422
5423         RTL_W32(RxMissed, 0);
5424
5425         rtl_set_rx_mode(dev);
5426
5427         /* no early-rx interrupts */
5428         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5429 }
5430
5431 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5432 {
5433         if (tp->csi_ops.write)
5434                 tp->csi_ops.write(tp, addr, value);
5435 }
5436
5437 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5438 {
5439         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5440 }
5441
5442 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5443 {
5444         u32 csi;
5445
5446         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5447         rtl_csi_write(tp, 0x070c, csi | bits);
5448 }
5449
5450 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5451 {
5452         rtl_csi_access_enable(tp, 0x17000000);
5453 }
5454
5455 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5456 {
5457         rtl_csi_access_enable(tp, 0x27000000);
5458 }
5459
5460 DECLARE_RTL_COND(rtl_csiar_cond)
5461 {
5462         void __iomem *ioaddr = tp->mmio_addr;
5463
5464         return RTL_R32(CSIAR) & CSIAR_FLAG;
5465 }
5466
5467 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5468 {
5469         void __iomem *ioaddr = tp->mmio_addr;
5470
5471         RTL_W32(CSIDR, value);
5472         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5473                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5474
5475         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5476 }
5477
5478 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5479 {
5480         void __iomem *ioaddr = tp->mmio_addr;
5481
5482         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5483                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5484
5485         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5486                 RTL_R32(CSIDR) : ~0;
5487 }
5488
5489 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5490 {
5491         void __iomem *ioaddr = tp->mmio_addr;
5492
5493         RTL_W32(CSIDR, value);
5494         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5495                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5496                 CSIAR_FUNC_NIC);
5497
5498         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5499 }
5500
5501 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5502 {
5503         void __iomem *ioaddr = tp->mmio_addr;
5504
5505         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5506                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5507
5508         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5509                 RTL_R32(CSIDR) : ~0;
5510 }
5511
5512 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5513 {
5514         void __iomem *ioaddr = tp->mmio_addr;
5515
5516         RTL_W32(CSIDR, value);
5517         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5518                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5519                 CSIAR_FUNC_NIC2);
5520
5521         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5522 }
5523
5524 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5525 {
5526         void __iomem *ioaddr = tp->mmio_addr;
5527
5528         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5529                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5530
5531         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5532                 RTL_R32(CSIDR) : ~0;
5533 }
5534
5535 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5536 {
5537         struct csi_ops *ops = &tp->csi_ops;
5538
5539         switch (tp->mac_version) {
5540         case RTL_GIGA_MAC_VER_01:
5541         case RTL_GIGA_MAC_VER_02:
5542         case RTL_GIGA_MAC_VER_03:
5543         case RTL_GIGA_MAC_VER_04:
5544         case RTL_GIGA_MAC_VER_05:
5545         case RTL_GIGA_MAC_VER_06:
5546         case RTL_GIGA_MAC_VER_10:
5547         case RTL_GIGA_MAC_VER_11:
5548         case RTL_GIGA_MAC_VER_12:
5549         case RTL_GIGA_MAC_VER_13:
5550         case RTL_GIGA_MAC_VER_14:
5551         case RTL_GIGA_MAC_VER_15:
5552         case RTL_GIGA_MAC_VER_16:
5553         case RTL_GIGA_MAC_VER_17:
5554                 ops->write      = NULL;
5555                 ops->read       = NULL;
5556                 break;
5557
5558         case RTL_GIGA_MAC_VER_37:
5559         case RTL_GIGA_MAC_VER_38:
5560                 ops->write      = r8402_csi_write;
5561                 ops->read       = r8402_csi_read;
5562                 break;
5563
5564         case RTL_GIGA_MAC_VER_44:
5565                 ops->write      = r8411_csi_write;
5566                 ops->read       = r8411_csi_read;
5567                 break;
5568
5569         default:
5570                 ops->write      = r8169_csi_write;
5571                 ops->read       = r8169_csi_read;
5572                 break;
5573         }
5574 }
5575
5576 struct ephy_info {
5577         unsigned int offset;
5578         u16 mask;
5579         u16 bits;
5580 };
5581
5582 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5583                           int len)
5584 {
5585         u16 w;
5586
5587         while (len-- > 0) {
5588                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5589                 rtl_ephy_write(tp, e->offset, w);
5590                 e++;
5591         }
5592 }
5593
5594 static void rtl_disable_clock_request(struct pci_dev *pdev)
5595 {
5596         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5597                                    PCI_EXP_LNKCTL_CLKREQ_EN);
5598 }
5599
5600 static void rtl_enable_clock_request(struct pci_dev *pdev)
5601 {
5602         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5603                                  PCI_EXP_LNKCTL_CLKREQ_EN);
5604 }
5605
5606 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5607 {
5608         void __iomem *ioaddr = tp->mmio_addr;
5609         u8 data;
5610
5611         data = RTL_R8(Config3);
5612
5613         if (enable)
5614                 data |= Rdy_to_L23;
5615         else
5616                 data &= ~Rdy_to_L23;
5617
5618         RTL_W8(Config3, data);
5619 }
5620
5621 #define R8168_CPCMD_QUIRK_MASK (\
5622         EnableBist | \
5623         Mac_dbgo_oe | \
5624         Force_half_dup | \
5625         Force_rxflow_en | \
5626         Force_txflow_en | \
5627         Cxpl_dbg_sel | \
5628         ASF | \
5629         PktCntrDisable | \
5630         Mac_dbgo_sel)
5631
5632 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5633 {
5634         void __iomem *ioaddr = tp->mmio_addr;
5635         struct pci_dev *pdev = tp->pci_dev;
5636
5637         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5638
5639         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5640
5641         if (tp->dev->mtu <= ETH_DATA_LEN) {
5642                 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5643                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5644         }
5645 }
5646
5647 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5648 {
5649         void __iomem *ioaddr = tp->mmio_addr;
5650
5651         rtl_hw_start_8168bb(tp);
5652
5653         RTL_W8(MaxTxPacketSize, TxPacketMax);
5654
5655         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5656 }
5657
5658 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5659 {
5660         void __iomem *ioaddr = tp->mmio_addr;
5661         struct pci_dev *pdev = tp->pci_dev;
5662
5663         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5664
5665         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5666
5667         if (tp->dev->mtu <= ETH_DATA_LEN)
5668                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5669
5670         rtl_disable_clock_request(pdev);
5671
5672         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5673 }
5674
5675 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5676 {
5677         static const struct ephy_info e_info_8168cp[] = {
5678                 { 0x01, 0,      0x0001 },
5679                 { 0x02, 0x0800, 0x1000 },
5680                 { 0x03, 0,      0x0042 },
5681                 { 0x06, 0x0080, 0x0000 },
5682                 { 0x07, 0,      0x2000 }
5683         };
5684
5685         rtl_csi_access_enable_2(tp);
5686
5687         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5688
5689         __rtl_hw_start_8168cp(tp);
5690 }
5691
5692 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5693 {
5694         void __iomem *ioaddr = tp->mmio_addr;
5695         struct pci_dev *pdev = tp->pci_dev;
5696
5697         rtl_csi_access_enable_2(tp);
5698
5699         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5700
5701         if (tp->dev->mtu <= ETH_DATA_LEN)
5702                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5703
5704         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5705 }
5706
5707 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5708 {
5709         void __iomem *ioaddr = tp->mmio_addr;
5710         struct pci_dev *pdev = tp->pci_dev;
5711
5712         rtl_csi_access_enable_2(tp);
5713
5714         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5715
5716         /* Magic. */
5717         RTL_W8(DBG_REG, 0x20);
5718
5719         RTL_W8(MaxTxPacketSize, TxPacketMax);
5720
5721         if (tp->dev->mtu <= ETH_DATA_LEN)
5722                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5723
5724         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5725 }
5726
5727 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5728 {
5729         void __iomem *ioaddr = tp->mmio_addr;
5730         static const struct ephy_info e_info_8168c_1[] = {
5731                 { 0x02, 0x0800, 0x1000 },
5732                 { 0x03, 0,      0x0002 },
5733                 { 0x06, 0x0080, 0x0000 }
5734         };
5735
5736         rtl_csi_access_enable_2(tp);
5737
5738         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5739
5740         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5741
5742         __rtl_hw_start_8168cp(tp);
5743 }
5744
5745 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5746 {
5747         static const struct ephy_info e_info_8168c_2[] = {
5748                 { 0x01, 0,      0x0001 },
5749                 { 0x03, 0x0400, 0x0220 }
5750         };
5751
5752         rtl_csi_access_enable_2(tp);
5753
5754         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5755
5756         __rtl_hw_start_8168cp(tp);
5757 }
5758
5759 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5760 {
5761         rtl_hw_start_8168c_2(tp);
5762 }
5763
5764 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5765 {
5766         rtl_csi_access_enable_2(tp);
5767
5768         __rtl_hw_start_8168cp(tp);
5769 }
5770
5771 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5772 {
5773         void __iomem *ioaddr = tp->mmio_addr;
5774         struct pci_dev *pdev = tp->pci_dev;
5775
5776         rtl_csi_access_enable_2(tp);
5777
5778         rtl_disable_clock_request(pdev);
5779
5780         RTL_W8(MaxTxPacketSize, TxPacketMax);
5781
5782         if (tp->dev->mtu <= ETH_DATA_LEN)
5783                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5784
5785         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5786 }
5787
5788 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5789 {
5790         void __iomem *ioaddr = tp->mmio_addr;
5791         struct pci_dev *pdev = tp->pci_dev;
5792
5793         rtl_csi_access_enable_1(tp);
5794
5795         if (tp->dev->mtu <= ETH_DATA_LEN)
5796                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5797
5798         RTL_W8(MaxTxPacketSize, TxPacketMax);
5799
5800         rtl_disable_clock_request(pdev);
5801 }
5802
5803 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5804 {
5805         void __iomem *ioaddr = tp->mmio_addr;
5806         struct pci_dev *pdev = tp->pci_dev;
5807         static const struct ephy_info e_info_8168d_4[] = {
5808                 { 0x0b, ~0,     0x48 },
5809                 { 0x19, 0x20,   0x50 },
5810                 { 0x0c, ~0,     0x20 }
5811         };
5812         int i;
5813
5814         rtl_csi_access_enable_1(tp);
5815
5816         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5817
5818         RTL_W8(MaxTxPacketSize, TxPacketMax);
5819
5820         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5821                 const struct ephy_info *e = e_info_8168d_4 + i;
5822                 u16 w;
5823
5824                 w = rtl_ephy_read(tp, e->offset);
5825                 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5826         }
5827
5828         rtl_enable_clock_request(pdev);
5829 }
5830
5831 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5832 {
5833         void __iomem *ioaddr = tp->mmio_addr;
5834         struct pci_dev *pdev = tp->pci_dev;
5835         static const struct ephy_info e_info_8168e_1[] = {
5836                 { 0x00, 0x0200, 0x0100 },
5837                 { 0x00, 0x0000, 0x0004 },
5838                 { 0x06, 0x0002, 0x0001 },
5839                 { 0x06, 0x0000, 0x0030 },
5840                 { 0x07, 0x0000, 0x2000 },
5841                 { 0x00, 0x0000, 0x0020 },
5842                 { 0x03, 0x5800, 0x2000 },
5843                 { 0x03, 0x0000, 0x0001 },
5844                 { 0x01, 0x0800, 0x1000 },
5845                 { 0x07, 0x0000, 0x4000 },
5846                 { 0x1e, 0x0000, 0x2000 },
5847                 { 0x19, 0xffff, 0xfe6c },
5848                 { 0x0a, 0x0000, 0x0040 }
5849         };
5850
5851         rtl_csi_access_enable_2(tp);
5852
5853         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5854
5855         if (tp->dev->mtu <= ETH_DATA_LEN)
5856                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5857
5858         RTL_W8(MaxTxPacketSize, TxPacketMax);
5859
5860         rtl_disable_clock_request(pdev);
5861
5862         /* Reset tx FIFO pointer */
5863         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5864         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5865
5866         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5867 }
5868
5869 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5870 {
5871         void __iomem *ioaddr = tp->mmio_addr;
5872         struct pci_dev *pdev = tp->pci_dev;
5873         static const struct ephy_info e_info_8168e_2[] = {
5874                 { 0x09, 0x0000, 0x0080 },
5875                 { 0x19, 0x0000, 0x0224 }
5876         };
5877
5878         rtl_csi_access_enable_1(tp);
5879
5880         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5881
5882         if (tp->dev->mtu <= ETH_DATA_LEN)
5883                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5884
5885         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5886         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5887         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5888         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5889         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5890         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5891         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5892         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5893
5894         RTL_W8(MaxTxPacketSize, EarlySize);
5895
5896         rtl_disable_clock_request(pdev);
5897
5898         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5899         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5900
5901         /* Adjust EEE LED frequency */
5902         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5903
5904         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5905         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5906         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5907 }
5908
5909 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5910 {
5911         void __iomem *ioaddr = tp->mmio_addr;
5912         struct pci_dev *pdev = tp->pci_dev;
5913
5914         rtl_csi_access_enable_2(tp);
5915
5916         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5917
5918         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5919         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5920         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5921         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5922         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5923         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5924         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5925         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5926         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5927         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5928
5929         RTL_W8(MaxTxPacketSize, EarlySize);
5930
5931         rtl_disable_clock_request(pdev);
5932
5933         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5934         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5935         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5936         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5937         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5938 }
5939
5940 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5941 {
5942         void __iomem *ioaddr = tp->mmio_addr;
5943         static const struct ephy_info e_info_8168f_1[] = {
5944                 { 0x06, 0x00c0, 0x0020 },
5945                 { 0x08, 0x0001, 0x0002 },
5946                 { 0x09, 0x0000, 0x0080 },
5947                 { 0x19, 0x0000, 0x0224 }
5948         };
5949
5950         rtl_hw_start_8168f(tp);
5951
5952         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5953
5954         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5955
5956         /* Adjust EEE LED frequency */
5957         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5958 }
5959
5960 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5961 {
5962         static const struct ephy_info e_info_8168f_1[] = {
5963                 { 0x06, 0x00c0, 0x0020 },
5964                 { 0x0f, 0xffff, 0x5200 },
5965                 { 0x1e, 0x0000, 0x4000 },
5966                 { 0x19, 0x0000, 0x0224 }
5967         };
5968
5969         rtl_hw_start_8168f(tp);
5970         rtl_pcie_state_l2l3_enable(tp, false);
5971
5972         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5973
5974         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5975 }
5976
5977 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5978 {
5979         void __iomem *ioaddr = tp->mmio_addr;
5980         struct pci_dev *pdev = tp->pci_dev;
5981
5982         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5983
5984         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5985         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5986         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5987         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5988
5989         rtl_csi_access_enable_1(tp);
5990
5991         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5992
5993         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5994         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5995         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5996
5997         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5998         RTL_W8(MaxTxPacketSize, EarlySize);
5999
6000         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6001         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6002
6003         /* Adjust EEE LED frequency */
6004         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6005
6006         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6007         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6008
6009         rtl_pcie_state_l2l3_enable(tp, false);
6010 }
6011
6012 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6013 {
6014         void __iomem *ioaddr = tp->mmio_addr;
6015         static const struct ephy_info e_info_8168g_1[] = {
6016                 { 0x00, 0x0000, 0x0008 },
6017                 { 0x0c, 0x37d0, 0x0820 },
6018                 { 0x1e, 0x0000, 0x0001 },
6019                 { 0x19, 0x8000, 0x0000 }
6020         };
6021
6022         rtl_hw_start_8168g(tp);
6023
6024         /* disable aspm and clock request before access ephy */
6025         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6026         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6027         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6028 }
6029
6030 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6031 {
6032         void __iomem *ioaddr = tp->mmio_addr;
6033         static const struct ephy_info e_info_8168g_2[] = {
6034                 { 0x00, 0x0000, 0x0008 },
6035                 { 0x0c, 0x3df0, 0x0200 },
6036                 { 0x19, 0xffff, 0xfc00 },
6037                 { 0x1e, 0xffff, 0x20eb }
6038         };
6039
6040         rtl_hw_start_8168g(tp);
6041
6042         /* disable aspm and clock request before access ephy */
6043         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6044         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6045         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6046 }
6047
6048 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6049 {
6050         void __iomem *ioaddr = tp->mmio_addr;
6051         static const struct ephy_info e_info_8411_2[] = {
6052                 { 0x00, 0x0000, 0x0008 },
6053                 { 0x0c, 0x3df0, 0x0200 },
6054                 { 0x0f, 0xffff, 0x5200 },
6055                 { 0x19, 0x0020, 0x0000 },
6056                 { 0x1e, 0x0000, 0x2000 }
6057         };
6058
6059         rtl_hw_start_8168g(tp);
6060
6061         /* disable aspm and clock request before access ephy */
6062         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6063         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6064         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6065 }
6066
6067 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6068 {
6069         void __iomem *ioaddr = tp->mmio_addr;
6070         struct pci_dev *pdev = tp->pci_dev;
6071         int rg_saw_cnt;
6072         u32 data;
6073         static const struct ephy_info e_info_8168h_1[] = {
6074                 { 0x1e, 0x0800, 0x0001 },
6075                 { 0x1d, 0x0000, 0x0800 },
6076                 { 0x05, 0xffff, 0x2089 },
6077                 { 0x06, 0xffff, 0x5881 },
6078                 { 0x04, 0xffff, 0x154a },
6079                 { 0x01, 0xffff, 0x068b }
6080         };
6081
6082         /* disable aspm and clock request before access ephy */
6083         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6084         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6085         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6086
6087         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6088
6089         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6090         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6091         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6092         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6093
6094         rtl_csi_access_enable_1(tp);
6095
6096         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6097
6098         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6099         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6100
6101         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6102
6103         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6104
6105         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6106
6107         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6108         RTL_W8(MaxTxPacketSize, EarlySize);
6109
6110         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6111         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6112
6113         /* Adjust EEE LED frequency */
6114         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6115
6116         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6117         RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6118
6119         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6120
6121         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6122
6123         rtl_pcie_state_l2l3_enable(tp, false);
6124
6125         rtl_writephy(tp, 0x1f, 0x0c42);
6126         rg_saw_cnt = rtl_readphy(tp, 0x13);
6127         rtl_writephy(tp, 0x1f, 0x0000);
6128         if (rg_saw_cnt > 0) {
6129                 u16 sw_cnt_1ms_ini;
6130
6131                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6132                 sw_cnt_1ms_ini &= 0x0fff;
6133                 data = r8168_mac_ocp_read(tp, 0xd412);
6134                 data &= 0x0fff;
6135                 data |= sw_cnt_1ms_ini;
6136                 r8168_mac_ocp_write(tp, 0xd412, data);
6137         }
6138
6139         data = r8168_mac_ocp_read(tp, 0xe056);
6140         data &= 0xf0;
6141         data |= 0x07;
6142         r8168_mac_ocp_write(tp, 0xe056, data);
6143
6144         data = r8168_mac_ocp_read(tp, 0xe052);
6145         data &= 0x8008;
6146         data |= 0x6000;
6147         r8168_mac_ocp_write(tp, 0xe052, data);
6148
6149         data = r8168_mac_ocp_read(tp, 0xe0d6);
6150         data &= 0x01ff;
6151         data |= 0x017f;
6152         r8168_mac_ocp_write(tp, 0xe0d6, data);
6153
6154         data = r8168_mac_ocp_read(tp, 0xd420);
6155         data &= 0x0fff;
6156         data |= 0x047f;
6157         r8168_mac_ocp_write(tp, 0xd420, data);
6158
6159         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6160         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6161         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6162         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6163 }
6164
6165 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6166 {
6167         void __iomem *ioaddr = tp->mmio_addr;
6168         struct pci_dev *pdev = tp->pci_dev;
6169
6170         rtl8168ep_stop_cmac(tp);
6171
6172         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6173
6174         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6175         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6176         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6177         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6178
6179         rtl_csi_access_enable_1(tp);
6180
6181         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6182
6183         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6184         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6185
6186         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6187
6188         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6189
6190         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6191         RTL_W8(MaxTxPacketSize, EarlySize);
6192
6193         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6194         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6195
6196         /* Adjust EEE LED frequency */
6197         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6198
6199         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6200
6201         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6202
6203         rtl_pcie_state_l2l3_enable(tp, false);
6204 }
6205
6206 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6207 {
6208         void __iomem *ioaddr = tp->mmio_addr;
6209         static const struct ephy_info e_info_8168ep_1[] = {
6210                 { 0x00, 0xffff, 0x10ab },
6211                 { 0x06, 0xffff, 0xf030 },
6212                 { 0x08, 0xffff, 0x2006 },
6213                 { 0x0d, 0xffff, 0x1666 },
6214                 { 0x0c, 0x3ff0, 0x0000 }
6215         };
6216
6217         /* disable aspm and clock request before access ephy */
6218         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6219         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6220         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6221
6222         rtl_hw_start_8168ep(tp);
6223 }
6224
6225 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6226 {
6227         void __iomem *ioaddr = tp->mmio_addr;
6228         static const struct ephy_info e_info_8168ep_2[] = {
6229                 { 0x00, 0xffff, 0x10a3 },
6230                 { 0x19, 0xffff, 0xfc00 },
6231                 { 0x1e, 0xffff, 0x20ea }
6232         };
6233
6234         /* disable aspm and clock request before access ephy */
6235         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6236         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6237         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6238
6239         rtl_hw_start_8168ep(tp);
6240
6241         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6242         RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6243 }
6244
6245 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6246 {
6247         void __iomem *ioaddr = tp->mmio_addr;
6248         u32 data;
6249         static const struct ephy_info e_info_8168ep_3[] = {
6250                 { 0x00, 0xffff, 0x10a3 },
6251                 { 0x19, 0xffff, 0x7c00 },
6252                 { 0x1e, 0xffff, 0x20eb },
6253                 { 0x0d, 0xffff, 0x1666 }
6254         };
6255
6256         /* disable aspm and clock request before access ephy */
6257         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6258         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6259         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6260
6261         rtl_hw_start_8168ep(tp);
6262
6263         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6264         RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6265
6266         data = r8168_mac_ocp_read(tp, 0xd3e2);
6267         data &= 0xf000;
6268         data |= 0x0271;
6269         r8168_mac_ocp_write(tp, 0xd3e2, data);
6270
6271         data = r8168_mac_ocp_read(tp, 0xd3e4);
6272         data &= 0xff00;
6273         r8168_mac_ocp_write(tp, 0xd3e4, data);
6274
6275         data = r8168_mac_ocp_read(tp, 0xe860);
6276         data |= 0x0080;
6277         r8168_mac_ocp_write(tp, 0xe860, data);
6278 }
6279
6280 static void rtl_hw_start_8168(struct net_device *dev)
6281 {
6282         struct rtl8169_private *tp = netdev_priv(dev);
6283         void __iomem *ioaddr = tp->mmio_addr;
6284
6285         RTL_W8(Cfg9346, Cfg9346_Unlock);
6286
6287         RTL_W8(MaxTxPacketSize, TxPacketMax);
6288
6289         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6290
6291         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6292
6293         RTL_W16(CPlusCmd, tp->cp_cmd);
6294
6295         RTL_W16(IntrMitigate, 0x5151);
6296
6297         /* Work around for RxFIFO overflow. */
6298         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6299                 tp->event_slow |= RxFIFOOver | PCSTimeout;
6300                 tp->event_slow &= ~RxOverflow;
6301         }
6302
6303         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6304
6305         rtl_set_rx_tx_config_registers(tp);
6306
6307         RTL_R8(IntrMask);
6308
6309         switch (tp->mac_version) {
6310         case RTL_GIGA_MAC_VER_11:
6311                 rtl_hw_start_8168bb(tp);
6312                 break;
6313
6314         case RTL_GIGA_MAC_VER_12:
6315         case RTL_GIGA_MAC_VER_17:
6316                 rtl_hw_start_8168bef(tp);
6317                 break;
6318
6319         case RTL_GIGA_MAC_VER_18:
6320                 rtl_hw_start_8168cp_1(tp);
6321                 break;
6322
6323         case RTL_GIGA_MAC_VER_19:
6324                 rtl_hw_start_8168c_1(tp);
6325                 break;
6326
6327         case RTL_GIGA_MAC_VER_20:
6328                 rtl_hw_start_8168c_2(tp);
6329                 break;
6330
6331         case RTL_GIGA_MAC_VER_21:
6332                 rtl_hw_start_8168c_3(tp);
6333                 break;
6334
6335         case RTL_GIGA_MAC_VER_22:
6336                 rtl_hw_start_8168c_4(tp);
6337                 break;
6338
6339         case RTL_GIGA_MAC_VER_23:
6340                 rtl_hw_start_8168cp_2(tp);
6341                 break;
6342
6343         case RTL_GIGA_MAC_VER_24:
6344                 rtl_hw_start_8168cp_3(tp);
6345                 break;
6346
6347         case RTL_GIGA_MAC_VER_25:
6348         case RTL_GIGA_MAC_VER_26:
6349         case RTL_GIGA_MAC_VER_27:
6350                 rtl_hw_start_8168d(tp);
6351                 break;
6352
6353         case RTL_GIGA_MAC_VER_28:
6354                 rtl_hw_start_8168d_4(tp);
6355                 break;
6356
6357         case RTL_GIGA_MAC_VER_31:
6358                 rtl_hw_start_8168dp(tp);
6359                 break;
6360
6361         case RTL_GIGA_MAC_VER_32:
6362         case RTL_GIGA_MAC_VER_33:
6363                 rtl_hw_start_8168e_1(tp);
6364                 break;
6365         case RTL_GIGA_MAC_VER_34:
6366                 rtl_hw_start_8168e_2(tp);
6367                 break;
6368
6369         case RTL_GIGA_MAC_VER_35:
6370         case RTL_GIGA_MAC_VER_36:
6371                 rtl_hw_start_8168f_1(tp);
6372                 break;
6373
6374         case RTL_GIGA_MAC_VER_38:
6375                 rtl_hw_start_8411(tp);
6376                 break;
6377
6378         case RTL_GIGA_MAC_VER_40:
6379         case RTL_GIGA_MAC_VER_41:
6380                 rtl_hw_start_8168g_1(tp);
6381                 break;
6382         case RTL_GIGA_MAC_VER_42:
6383                 rtl_hw_start_8168g_2(tp);
6384                 break;
6385
6386         case RTL_GIGA_MAC_VER_44:
6387                 rtl_hw_start_8411_2(tp);
6388                 break;
6389
6390         case RTL_GIGA_MAC_VER_45:
6391         case RTL_GIGA_MAC_VER_46:
6392                 rtl_hw_start_8168h_1(tp);
6393                 break;
6394
6395         case RTL_GIGA_MAC_VER_49:
6396                 rtl_hw_start_8168ep_1(tp);
6397                 break;
6398
6399         case RTL_GIGA_MAC_VER_50:
6400                 rtl_hw_start_8168ep_2(tp);
6401                 break;
6402
6403         case RTL_GIGA_MAC_VER_51:
6404                 rtl_hw_start_8168ep_3(tp);
6405                 break;
6406
6407         default:
6408                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6409                         dev->name, tp->mac_version);
6410                 break;
6411         }
6412
6413         RTL_W8(Cfg9346, Cfg9346_Lock);
6414
6415         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6416
6417         rtl_set_rx_mode(dev);
6418
6419         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6420 }
6421
6422 #define R810X_CPCMD_QUIRK_MASK (\
6423         EnableBist | \
6424         Mac_dbgo_oe | \
6425         Force_half_dup | \
6426         Force_rxflow_en | \
6427         Force_txflow_en | \
6428         Cxpl_dbg_sel | \
6429         ASF | \
6430         PktCntrDisable | \
6431         Mac_dbgo_sel)
6432
6433 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6434 {
6435         void __iomem *ioaddr = tp->mmio_addr;
6436         struct pci_dev *pdev = tp->pci_dev;
6437         static const struct ephy_info e_info_8102e_1[] = {
6438                 { 0x01, 0, 0x6e65 },
6439                 { 0x02, 0, 0x091f },
6440                 { 0x03, 0, 0xc2f9 },
6441                 { 0x06, 0, 0xafb5 },
6442                 { 0x07, 0, 0x0e00 },
6443                 { 0x19, 0, 0xec80 },
6444                 { 0x01, 0, 0x2e65 },
6445                 { 0x01, 0, 0x6e65 }
6446         };
6447         u8 cfg1;
6448
6449         rtl_csi_access_enable_2(tp);
6450
6451         RTL_W8(DBG_REG, FIX_NAK_1);
6452
6453         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6454
6455         RTL_W8(Config1,
6456                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6457         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6458
6459         cfg1 = RTL_R8(Config1);
6460         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6461                 RTL_W8(Config1, cfg1 & ~LEDS0);
6462
6463         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6464 }
6465
6466 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6467 {
6468         void __iomem *ioaddr = tp->mmio_addr;
6469         struct pci_dev *pdev = tp->pci_dev;
6470
6471         rtl_csi_access_enable_2(tp);
6472
6473         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6474
6475         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6476         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6477 }
6478
6479 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6480 {
6481         rtl_hw_start_8102e_2(tp);
6482
6483         rtl_ephy_write(tp, 0x03, 0xc2f9);
6484 }
6485
6486 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6487 {
6488         void __iomem *ioaddr = tp->mmio_addr;
6489         static const struct ephy_info e_info_8105e_1[] = {
6490                 { 0x07, 0, 0x4000 },
6491                 { 0x19, 0, 0x0200 },
6492                 { 0x19, 0, 0x0020 },
6493                 { 0x1e, 0, 0x2000 },
6494                 { 0x03, 0, 0x0001 },
6495                 { 0x19, 0, 0x0100 },
6496                 { 0x19, 0, 0x0004 },
6497                 { 0x0a, 0, 0x0020 }
6498         };
6499
6500         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6501         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6502
6503         /* Disable Early Tally Counter */
6504         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6505
6506         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6507         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6508
6509         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6510
6511         rtl_pcie_state_l2l3_enable(tp, false);
6512 }
6513
6514 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6515 {
6516         rtl_hw_start_8105e_1(tp);
6517         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6518 }
6519
6520 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6521 {
6522         void __iomem *ioaddr = tp->mmio_addr;
6523         static const struct ephy_info e_info_8402[] = {
6524                 { 0x19, 0xffff, 0xff64 },
6525                 { 0x1e, 0, 0x4000 }
6526         };
6527
6528         rtl_csi_access_enable_2(tp);
6529
6530         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6531         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6532
6533         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6534         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6535
6536         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6537
6538         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6539
6540         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6541         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6542         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6543         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6544         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6545         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6546         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6547
6548         rtl_pcie_state_l2l3_enable(tp, false);
6549 }
6550
6551 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6552 {
6553         void __iomem *ioaddr = tp->mmio_addr;
6554
6555         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6556         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6557
6558         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6559         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6560         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6561
6562         rtl_pcie_state_l2l3_enable(tp, false);
6563 }
6564
6565 static void rtl_hw_start_8101(struct net_device *dev)
6566 {
6567         struct rtl8169_private *tp = netdev_priv(dev);
6568         void __iomem *ioaddr = tp->mmio_addr;
6569         struct pci_dev *pdev = tp->pci_dev;
6570
6571         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6572                 tp->event_slow &= ~RxFIFOOver;
6573
6574         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6575             tp->mac_version == RTL_GIGA_MAC_VER_16)
6576                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6577                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
6578
6579         RTL_W8(Cfg9346, Cfg9346_Unlock);
6580
6581         RTL_W8(MaxTxPacketSize, TxPacketMax);
6582
6583         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6584
6585         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6586         RTL_W16(CPlusCmd, tp->cp_cmd);
6587
6588         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6589
6590         rtl_set_rx_tx_config_registers(tp);
6591
6592         switch (tp->mac_version) {
6593         case RTL_GIGA_MAC_VER_07:
6594                 rtl_hw_start_8102e_1(tp);
6595                 break;
6596
6597         case RTL_GIGA_MAC_VER_08:
6598                 rtl_hw_start_8102e_3(tp);
6599                 break;
6600
6601         case RTL_GIGA_MAC_VER_09:
6602                 rtl_hw_start_8102e_2(tp);
6603                 break;
6604
6605         case RTL_GIGA_MAC_VER_29:
6606                 rtl_hw_start_8105e_1(tp);
6607                 break;
6608         case RTL_GIGA_MAC_VER_30:
6609                 rtl_hw_start_8105e_2(tp);
6610                 break;
6611
6612         case RTL_GIGA_MAC_VER_37:
6613                 rtl_hw_start_8402(tp);
6614                 break;
6615
6616         case RTL_GIGA_MAC_VER_39:
6617                 rtl_hw_start_8106(tp);
6618                 break;
6619         case RTL_GIGA_MAC_VER_43:
6620                 rtl_hw_start_8168g_2(tp);
6621                 break;
6622         case RTL_GIGA_MAC_VER_47:
6623         case RTL_GIGA_MAC_VER_48:
6624                 rtl_hw_start_8168h_1(tp);
6625                 break;
6626         }
6627
6628         RTL_W8(Cfg9346, Cfg9346_Lock);
6629
6630         RTL_W16(IntrMitigate, 0x0000);
6631
6632         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6633
6634         rtl_set_rx_mode(dev);
6635
6636         RTL_R8(IntrMask);
6637
6638         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6639 }
6640
6641 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6642 {
6643         struct rtl8169_private *tp = netdev_priv(dev);
6644
6645         if (new_mtu < ETH_ZLEN ||
6646             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
6647                 return -EINVAL;
6648
6649         if (new_mtu > ETH_DATA_LEN)
6650                 rtl_hw_jumbo_enable(tp);
6651         else
6652                 rtl_hw_jumbo_disable(tp);
6653
6654         dev->mtu = new_mtu;
6655         netdev_update_features(dev);
6656
6657         return 0;
6658 }
6659
6660 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6661 {
6662         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6663         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6664 }
6665
6666 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6667                                      void **data_buff, struct RxDesc *desc)
6668 {
6669         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6670                          DMA_FROM_DEVICE);
6671
6672         kfree(*data_buff);
6673         *data_buff = NULL;
6674         rtl8169_make_unusable_by_asic(desc);
6675 }
6676
6677 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6678 {
6679         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6680
6681         /* Force memory writes to complete before releasing descriptor */
6682         dma_wmb();
6683
6684         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6685 }
6686
6687 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6688                                        u32 rx_buf_sz)
6689 {
6690         desc->addr = cpu_to_le64(mapping);
6691         rtl8169_mark_to_asic(desc, rx_buf_sz);
6692 }
6693
6694 static inline void *rtl8169_align(void *data)
6695 {
6696         return (void *)ALIGN((long)data, 16);
6697 }
6698
6699 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6700                                              struct RxDesc *desc)
6701 {
6702         void *data;
6703         dma_addr_t mapping;
6704         struct device *d = &tp->pci_dev->dev;
6705         struct net_device *dev = tp->dev;
6706         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6707
6708         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6709         if (!data)
6710                 return NULL;
6711
6712         if (rtl8169_align(data) != data) {
6713                 kfree(data);
6714                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6715                 if (!data)
6716                         return NULL;
6717         }
6718
6719         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6720                                  DMA_FROM_DEVICE);
6721         if (unlikely(dma_mapping_error(d, mapping))) {
6722                 if (net_ratelimit())
6723                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6724                 goto err_out;
6725         }
6726
6727         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6728         return data;
6729
6730 err_out:
6731         kfree(data);
6732         return NULL;
6733 }
6734
6735 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6736 {
6737         unsigned int i;
6738
6739         for (i = 0; i < NUM_RX_DESC; i++) {
6740                 if (tp->Rx_databuff[i]) {
6741                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6742                                             tp->RxDescArray + i);
6743                 }
6744         }
6745 }
6746
6747 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6748 {
6749         desc->opts1 |= cpu_to_le32(RingEnd);
6750 }
6751
6752 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6753 {
6754         unsigned int i;
6755
6756         for (i = 0; i < NUM_RX_DESC; i++) {
6757                 void *data;
6758
6759                 if (tp->Rx_databuff[i])
6760                         continue;
6761
6762                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6763                 if (!data) {
6764                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6765                         goto err_out;
6766                 }
6767                 tp->Rx_databuff[i] = data;
6768         }
6769
6770         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6771         return 0;
6772
6773 err_out:
6774         rtl8169_rx_clear(tp);
6775         return -ENOMEM;
6776 }
6777
6778 static int rtl8169_init_ring(struct net_device *dev)
6779 {
6780         struct rtl8169_private *tp = netdev_priv(dev);
6781
6782         rtl8169_init_ring_indexes(tp);
6783
6784         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6785         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6786
6787         return rtl8169_rx_fill(tp);
6788 }
6789
6790 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6791                                  struct TxDesc *desc)
6792 {
6793         unsigned int len = tx_skb->len;
6794
6795         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6796
6797         desc->opts1 = 0x00;
6798         desc->opts2 = 0x00;
6799         desc->addr = 0x00;
6800         tx_skb->len = 0;
6801 }
6802
6803 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6804                                    unsigned int n)
6805 {
6806         unsigned int i;
6807
6808         for (i = 0; i < n; i++) {
6809                 unsigned int entry = (start + i) % NUM_TX_DESC;
6810                 struct ring_info *tx_skb = tp->tx_skb + entry;
6811                 unsigned int len = tx_skb->len;
6812
6813                 if (len) {
6814                         struct sk_buff *skb = tx_skb->skb;
6815
6816                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6817                                              tp->TxDescArray + entry);
6818                         if (skb) {
6819                                 tp->dev->stats.tx_dropped++;
6820                                 dev_kfree_skb_any(skb);
6821                                 tx_skb->skb = NULL;
6822                         }
6823                 }
6824         }
6825 }
6826
6827 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6828 {
6829         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6830         tp->cur_tx = tp->dirty_tx = 0;
6831 }
6832
6833 static void rtl_reset_work(struct rtl8169_private *tp)
6834 {
6835         struct net_device *dev = tp->dev;
6836         int i;
6837
6838         napi_disable(&tp->napi);
6839         netif_stop_queue(dev);
6840         synchronize_sched();
6841
6842         rtl8169_hw_reset(tp);
6843
6844         for (i = 0; i < NUM_RX_DESC; i++)
6845                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6846
6847         rtl8169_tx_clear(tp);
6848         rtl8169_init_ring_indexes(tp);
6849
6850         napi_enable(&tp->napi);
6851         rtl_hw_start(dev);
6852         netif_wake_queue(dev);
6853         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6854 }
6855
6856 static void rtl8169_tx_timeout(struct net_device *dev)
6857 {
6858         struct rtl8169_private *tp = netdev_priv(dev);
6859
6860         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6861 }
6862
6863 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6864                               u32 *opts)
6865 {
6866         struct skb_shared_info *info = skb_shinfo(skb);
6867         unsigned int cur_frag, entry;
6868         struct TxDesc *uninitialized_var(txd);
6869         struct device *d = &tp->pci_dev->dev;
6870
6871         entry = tp->cur_tx;
6872         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6873                 const skb_frag_t *frag = info->frags + cur_frag;
6874                 dma_addr_t mapping;
6875                 u32 status, len;
6876                 void *addr;
6877
6878                 entry = (entry + 1) % NUM_TX_DESC;
6879
6880                 txd = tp->TxDescArray + entry;
6881                 len = skb_frag_size(frag);
6882                 addr = skb_frag_address(frag);
6883                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6884                 if (unlikely(dma_mapping_error(d, mapping))) {
6885                         if (net_ratelimit())
6886                                 netif_err(tp, drv, tp->dev,
6887                                           "Failed to map TX fragments DMA!\n");
6888                         goto err_out;
6889                 }
6890
6891                 /* Anti gcc 2.95.3 bugware (sic) */
6892                 status = opts[0] | len |
6893                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
6894
6895                 txd->opts1 = cpu_to_le32(status);
6896                 txd->opts2 = cpu_to_le32(opts[1]);
6897                 txd->addr = cpu_to_le64(mapping);
6898
6899                 tp->tx_skb[entry].len = len;
6900         }
6901
6902         if (cur_frag) {
6903                 tp->tx_skb[entry].skb = skb;
6904                 txd->opts1 |= cpu_to_le32(LastFrag);
6905         }
6906
6907         return cur_frag;
6908
6909 err_out:
6910         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6911         return -EIO;
6912 }
6913
6914 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6915 {
6916         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6917 }
6918
6919 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6920                                       struct net_device *dev);
6921 /* r8169_csum_workaround()
6922  * The hw limites the value the transport offset. When the offset is out of the
6923  * range, calculate the checksum by sw.
6924  */
6925 static void r8169_csum_workaround(struct rtl8169_private *tp,
6926                                   struct sk_buff *skb)
6927 {
6928         if (skb_shinfo(skb)->gso_size) {
6929                 netdev_features_t features = tp->dev->features;
6930                 struct sk_buff *segs, *nskb;
6931
6932                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6933                 segs = skb_gso_segment(skb, features);
6934                 if (IS_ERR(segs) || !segs)
6935                         goto drop;
6936
6937                 do {
6938                         nskb = segs;
6939                         segs = segs->next;
6940                         nskb->next = NULL;
6941                         rtl8169_start_xmit(nskb, tp->dev);
6942                 } while (segs);
6943
6944                 dev_consume_skb_any(skb);
6945         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6946                 if (skb_checksum_help(skb) < 0)
6947                         goto drop;
6948
6949                 rtl8169_start_xmit(skb, tp->dev);
6950         } else {
6951                 struct net_device_stats *stats;
6952
6953 drop:
6954                 stats = &tp->dev->stats;
6955                 stats->tx_dropped++;
6956                 dev_kfree_skb_any(skb);
6957         }
6958 }
6959
6960 /* msdn_giant_send_check()
6961  * According to the document of microsoft, the TCP Pseudo Header excludes the
6962  * packet length for IPv6 TCP large packets.
6963  */
6964 static int msdn_giant_send_check(struct sk_buff *skb)
6965 {
6966         const struct ipv6hdr *ipv6h;
6967         struct tcphdr *th;
6968         int ret;
6969
6970         ret = skb_cow_head(skb, 0);
6971         if (ret)
6972                 return ret;
6973
6974         ipv6h = ipv6_hdr(skb);
6975         th = tcp_hdr(skb);
6976
6977         th->check = 0;
6978         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6979
6980         return ret;
6981 }
6982
6983 static inline __be16 get_protocol(struct sk_buff *skb)
6984 {
6985         __be16 protocol;
6986
6987         if (skb->protocol == htons(ETH_P_8021Q))
6988                 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6989         else
6990                 protocol = skb->protocol;
6991
6992         return protocol;
6993 }
6994
6995 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6996                                 struct sk_buff *skb, u32 *opts)
6997 {
6998         u32 mss = skb_shinfo(skb)->gso_size;
6999
7000         if (mss) {
7001                 opts[0] |= TD_LSO;
7002                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7003         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7004                 const struct iphdr *ip = ip_hdr(skb);
7005
7006                 if (ip->protocol == IPPROTO_TCP)
7007                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7008                 else if (ip->protocol == IPPROTO_UDP)
7009                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7010                 else
7011                         WARN_ON_ONCE(1);
7012         }
7013
7014         return true;
7015 }
7016
7017 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7018                                 struct sk_buff *skb, u32 *opts)
7019 {
7020         u32 transport_offset = (u32)skb_transport_offset(skb);
7021         u32 mss = skb_shinfo(skb)->gso_size;
7022
7023         if (mss) {
7024                 if (transport_offset > GTTCPHO_MAX) {
7025                         netif_warn(tp, tx_err, tp->dev,
7026                                    "Invalid transport offset 0x%x for TSO\n",
7027                                    transport_offset);
7028                         return false;
7029                 }
7030
7031                 switch (get_protocol(skb)) {
7032                 case htons(ETH_P_IP):
7033                         opts[0] |= TD1_GTSENV4;
7034                         break;
7035
7036                 case htons(ETH_P_IPV6):
7037                         if (msdn_giant_send_check(skb))
7038                                 return false;
7039
7040                         opts[0] |= TD1_GTSENV6;
7041                         break;
7042
7043                 default:
7044                         WARN_ON_ONCE(1);
7045                         break;
7046                 }
7047
7048                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7049                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7050         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7051                 u8 ip_protocol;
7052
7053                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7054                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7055
7056                 if (transport_offset > TCPHO_MAX) {
7057                         netif_warn(tp, tx_err, tp->dev,
7058                                    "Invalid transport offset 0x%x\n",
7059                                    transport_offset);
7060                         return false;
7061                 }
7062
7063                 switch (get_protocol(skb)) {
7064                 case htons(ETH_P_IP):
7065                         opts[1] |= TD1_IPv4_CS;
7066                         ip_protocol = ip_hdr(skb)->protocol;
7067                         break;
7068
7069                 case htons(ETH_P_IPV6):
7070                         opts[1] |= TD1_IPv6_CS;
7071                         ip_protocol = ipv6_hdr(skb)->nexthdr;
7072                         break;
7073
7074                 default:
7075                         ip_protocol = IPPROTO_RAW;
7076                         break;
7077                 }
7078
7079                 if (ip_protocol == IPPROTO_TCP)
7080                         opts[1] |= TD1_TCP_CS;
7081                 else if (ip_protocol == IPPROTO_UDP)
7082                         opts[1] |= TD1_UDP_CS;
7083                 else
7084                         WARN_ON_ONCE(1);
7085
7086                 opts[1] |= transport_offset << TCPHO_SHIFT;
7087         } else {
7088                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7089                         return !eth_skb_pad(skb);
7090         }
7091
7092         return true;
7093 }
7094
7095 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7096                                       struct net_device *dev)
7097 {
7098         struct rtl8169_private *tp = netdev_priv(dev);
7099         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7100         struct TxDesc *txd = tp->TxDescArray + entry;
7101         void __iomem *ioaddr = tp->mmio_addr;
7102         struct device *d = &tp->pci_dev->dev;
7103         dma_addr_t mapping;
7104         u32 status, len;
7105         u32 opts[2];
7106         int frags;
7107
7108         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7109                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7110                 goto err_stop_0;
7111         }
7112
7113         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7114                 goto err_stop_0;
7115
7116         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7117         opts[0] = DescOwn;
7118
7119         if (!tp->tso_csum(tp, skb, opts)) {
7120                 r8169_csum_workaround(tp, skb);
7121                 return NETDEV_TX_OK;
7122         }
7123
7124         len = skb_headlen(skb);
7125         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7126         if (unlikely(dma_mapping_error(d, mapping))) {
7127                 if (net_ratelimit())
7128                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7129                 goto err_dma_0;
7130         }
7131
7132         tp->tx_skb[entry].len = len;
7133         txd->addr = cpu_to_le64(mapping);
7134
7135         frags = rtl8169_xmit_frags(tp, skb, opts);
7136         if (frags < 0)
7137                 goto err_dma_1;
7138         else if (frags)
7139                 opts[0] |= FirstFrag;
7140         else {
7141                 opts[0] |= FirstFrag | LastFrag;
7142                 tp->tx_skb[entry].skb = skb;
7143         }
7144
7145         txd->opts2 = cpu_to_le32(opts[1]);
7146
7147         skb_tx_timestamp(skb);
7148
7149         /* Force memory writes to complete before releasing descriptor */
7150         dma_wmb();
7151
7152         /* Anti gcc 2.95.3 bugware (sic) */
7153         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7154         txd->opts1 = cpu_to_le32(status);
7155
7156         /* Force all memory writes to complete before notifying device */
7157         wmb();
7158
7159         tp->cur_tx += frags + 1;
7160
7161         RTL_W8(TxPoll, NPQ);
7162
7163         mmiowb();
7164
7165         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7166                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7167                  * not miss a ring update when it notices a stopped queue.
7168                  */
7169                 smp_wmb();
7170                 netif_stop_queue(dev);
7171                 /* Sync with rtl_tx:
7172                  * - publish queue status and cur_tx ring index (write barrier)
7173                  * - refresh dirty_tx ring index (read barrier).
7174                  * May the current thread have a pessimistic view of the ring
7175                  * status and forget to wake up queue, a racing rtl_tx thread
7176                  * can't.
7177                  */
7178                 smp_mb();
7179                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7180                         netif_wake_queue(dev);
7181         }
7182
7183         return NETDEV_TX_OK;
7184
7185 err_dma_1:
7186         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7187 err_dma_0:
7188         dev_kfree_skb_any(skb);
7189         dev->stats.tx_dropped++;
7190         return NETDEV_TX_OK;
7191
7192 err_stop_0:
7193         netif_stop_queue(dev);
7194         dev->stats.tx_dropped++;
7195         return NETDEV_TX_BUSY;
7196 }
7197
7198 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7199 {
7200         struct rtl8169_private *tp = netdev_priv(dev);
7201         struct pci_dev *pdev = tp->pci_dev;
7202         u16 pci_status, pci_cmd;
7203
7204         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7205         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7206
7207         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7208                   pci_cmd, pci_status);
7209
7210         /*
7211          * The recovery sequence below admits a very elaborated explanation:
7212          * - it seems to work;
7213          * - I did not see what else could be done;
7214          * - it makes iop3xx happy.
7215          *
7216          * Feel free to adjust to your needs.
7217          */
7218         if (pdev->broken_parity_status)
7219                 pci_cmd &= ~PCI_COMMAND_PARITY;
7220         else
7221                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7222
7223         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7224
7225         pci_write_config_word(pdev, PCI_STATUS,
7226                 pci_status & (PCI_STATUS_DETECTED_PARITY |
7227                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7228                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7229
7230         /* The infamous DAC f*ckup only happens at boot time */
7231         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7232                 void __iomem *ioaddr = tp->mmio_addr;
7233
7234                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7235                 tp->cp_cmd &= ~PCIDAC;
7236                 RTL_W16(CPlusCmd, tp->cp_cmd);
7237                 dev->features &= ~NETIF_F_HIGHDMA;
7238         }
7239
7240         rtl8169_hw_reset(tp);
7241
7242         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7243 }
7244
7245 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7246 {
7247         unsigned int dirty_tx, tx_left;
7248
7249         dirty_tx = tp->dirty_tx;
7250         smp_rmb();
7251         tx_left = tp->cur_tx - dirty_tx;
7252
7253         while (tx_left > 0) {
7254                 unsigned int entry = dirty_tx % NUM_TX_DESC;
7255                 struct ring_info *tx_skb = tp->tx_skb + entry;
7256                 u32 status;
7257
7258                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7259                 if (status & DescOwn)
7260                         break;
7261
7262                 /* This barrier is needed to keep us from reading
7263                  * any other fields out of the Tx descriptor until
7264                  * we know the status of DescOwn
7265                  */
7266                 dma_rmb();
7267
7268                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7269                                      tp->TxDescArray + entry);
7270                 if (status & LastFrag) {
7271                         u64_stats_update_begin(&tp->tx_stats.syncp);
7272                         tp->tx_stats.packets++;
7273                         tp->tx_stats.bytes += tx_skb->skb->len;
7274                         u64_stats_update_end(&tp->tx_stats.syncp);
7275                         dev_kfree_skb_any(tx_skb->skb);
7276                         tx_skb->skb = NULL;
7277                 }
7278                 dirty_tx++;
7279                 tx_left--;
7280         }
7281
7282         if (tp->dirty_tx != dirty_tx) {
7283                 tp->dirty_tx = dirty_tx;
7284                 /* Sync with rtl8169_start_xmit:
7285                  * - publish dirty_tx ring index (write barrier)
7286                  * - refresh cur_tx ring index and queue status (read barrier)
7287                  * May the current thread miss the stopped queue condition,
7288                  * a racing xmit thread can only have a right view of the
7289                  * ring status.
7290                  */
7291                 smp_mb();
7292                 if (netif_queue_stopped(dev) &&
7293                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7294                         netif_wake_queue(dev);
7295                 }
7296                 /*
7297                  * 8168 hack: TxPoll requests are lost when the Tx packets are
7298                  * too close. Let's kick an extra TxPoll request when a burst
7299                  * of start_xmit activity is detected (if it is not detected,
7300                  * it is slow enough). -- FR
7301                  */
7302                 if (tp->cur_tx != dirty_tx) {
7303                         void __iomem *ioaddr = tp->mmio_addr;
7304
7305                         RTL_W8(TxPoll, NPQ);
7306                 }
7307         }
7308 }
7309
7310 static inline int rtl8169_fragmented_frame(u32 status)
7311 {
7312         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7313 }
7314
7315 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7316 {
7317         u32 status = opts1 & RxProtoMask;
7318
7319         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7320             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7321                 skb->ip_summed = CHECKSUM_UNNECESSARY;
7322         else
7323                 skb_checksum_none_assert(skb);
7324 }
7325
7326 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7327                                            struct rtl8169_private *tp,
7328                                            int pkt_size,
7329                                            dma_addr_t addr)
7330 {
7331         struct sk_buff *skb;
7332         struct device *d = &tp->pci_dev->dev;
7333
7334         data = rtl8169_align(data);
7335         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7336         prefetch(data);
7337         skb = napi_alloc_skb(&tp->napi, pkt_size);
7338         if (skb)
7339                 memcpy(skb->data, data, pkt_size);
7340         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7341
7342         return skb;
7343 }
7344
7345 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7346 {
7347         unsigned int cur_rx, rx_left;
7348         unsigned int count;
7349
7350         cur_rx = tp->cur_rx;
7351
7352         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7353                 unsigned int entry = cur_rx % NUM_RX_DESC;
7354                 struct RxDesc *desc = tp->RxDescArray + entry;
7355                 u32 status;
7356
7357                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7358                 if (status & DescOwn)
7359                         break;
7360
7361                 /* This barrier is needed to keep us from reading
7362                  * any other fields out of the Rx descriptor until
7363                  * we know the status of DescOwn
7364                  */
7365                 dma_rmb();
7366
7367                 if (unlikely(status & RxRES)) {
7368                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7369                                    status);
7370                         dev->stats.rx_errors++;
7371                         if (status & (RxRWT | RxRUNT))
7372                                 dev->stats.rx_length_errors++;
7373                         if (status & RxCRC)
7374                                 dev->stats.rx_crc_errors++;
7375                         if (status & RxFOVF) {
7376                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7377                                 dev->stats.rx_fifo_errors++;
7378                         }
7379                         if ((status & (RxRUNT | RxCRC)) &&
7380                             !(status & (RxRWT | RxFOVF)) &&
7381                             (dev->features & NETIF_F_RXALL))
7382                                 goto process_pkt;
7383                 } else {
7384                         struct sk_buff *skb;
7385                         dma_addr_t addr;
7386                         int pkt_size;
7387
7388 process_pkt:
7389                         addr = le64_to_cpu(desc->addr);
7390                         if (likely(!(dev->features & NETIF_F_RXFCS)))
7391                                 pkt_size = (status & 0x00003fff) - 4;
7392                         else
7393                                 pkt_size = status & 0x00003fff;
7394
7395                         /*
7396                          * The driver does not support incoming fragmented
7397                          * frames. They are seen as a symptom of over-mtu
7398                          * sized frames.
7399                          */
7400                         if (unlikely(rtl8169_fragmented_frame(status))) {
7401                                 dev->stats.rx_dropped++;
7402                                 dev->stats.rx_length_errors++;
7403                                 goto release_descriptor;
7404                         }
7405
7406                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7407                                                   tp, pkt_size, addr);
7408                         if (!skb) {
7409                                 dev->stats.rx_dropped++;
7410                                 goto release_descriptor;
7411                         }
7412
7413                         rtl8169_rx_csum(skb, status);
7414                         skb_put(skb, pkt_size);
7415                         skb->protocol = eth_type_trans(skb, dev);
7416
7417                         rtl8169_rx_vlan_tag(desc, skb);
7418
7419                         if (skb->pkt_type == PACKET_MULTICAST)
7420                                 dev->stats.multicast++;
7421
7422                         napi_gro_receive(&tp->napi, skb);
7423
7424                         u64_stats_update_begin(&tp->rx_stats.syncp);
7425                         tp->rx_stats.packets++;
7426                         tp->rx_stats.bytes += pkt_size;
7427                         u64_stats_update_end(&tp->rx_stats.syncp);
7428                 }
7429 release_descriptor:
7430                 desc->opts2 = 0;
7431                 rtl8169_mark_to_asic(desc, rx_buf_sz);
7432         }
7433
7434         count = cur_rx - tp->cur_rx;
7435         tp->cur_rx = cur_rx;
7436
7437         return count;
7438 }
7439
7440 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7441 {
7442         struct net_device *dev = dev_instance;
7443         struct rtl8169_private *tp = netdev_priv(dev);
7444         int handled = 0;
7445         u16 status;
7446
7447         status = rtl_get_events(tp);
7448         if (status && status != 0xffff) {
7449                 status &= RTL_EVENT_NAPI | tp->event_slow;
7450                 if (status) {
7451                         handled = 1;
7452
7453                         rtl_irq_disable(tp);
7454                         napi_schedule(&tp->napi);
7455                 }
7456         }
7457         return IRQ_RETVAL(handled);
7458 }
7459
7460 /*
7461  * Workqueue context.
7462  */
7463 static void rtl_slow_event_work(struct rtl8169_private *tp)
7464 {
7465         struct net_device *dev = tp->dev;
7466         u16 status;
7467
7468         status = rtl_get_events(tp) & tp->event_slow;
7469         rtl_ack_events(tp, status);
7470
7471         if (unlikely(status & RxFIFOOver)) {
7472                 switch (tp->mac_version) {
7473                 /* Work around for rx fifo overflow */
7474                 case RTL_GIGA_MAC_VER_11:
7475                         netif_stop_queue(dev);
7476                         /* XXX - Hack alert. See rtl_task(). */
7477                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7478                 default:
7479                         break;
7480                 }
7481         }
7482
7483         if (unlikely(status & SYSErr))
7484                 rtl8169_pcierr_interrupt(dev);
7485
7486         if (status & LinkChg)
7487                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
7488
7489         rtl_irq_enable_all(tp);
7490 }
7491
7492 static void rtl_task(struct work_struct *work)
7493 {
7494         static const struct {
7495                 int bitnr;
7496                 void (*action)(struct rtl8169_private *);
7497         } rtl_work[] = {
7498                 /* XXX - keep rtl_slow_event_work() as first element. */
7499                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
7500                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
7501                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
7502         };
7503         struct rtl8169_private *tp =
7504                 container_of(work, struct rtl8169_private, wk.work);
7505         struct net_device *dev = tp->dev;
7506         int i;
7507
7508         rtl_lock_work(tp);
7509
7510         if (!netif_running(dev) ||
7511             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7512                 goto out_unlock;
7513
7514         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7515                 bool pending;
7516
7517                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7518                 if (pending)
7519                         rtl_work[i].action(tp);
7520         }
7521
7522 out_unlock:
7523         rtl_unlock_work(tp);
7524 }
7525
7526 static int rtl8169_poll(struct napi_struct *napi, int budget)
7527 {
7528         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7529         struct net_device *dev = tp->dev;
7530         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7531         int work_done;
7532         u16 status;
7533
7534         status = rtl_get_events(tp);
7535         rtl_ack_events(tp, status & ~tp->event_slow);
7536
7537         work_done = rtl_rx(dev, tp, (u32) budget);
7538
7539         rtl_tx(dev, tp);
7540
7541         if (status & tp->event_slow) {
7542                 enable_mask &= ~tp->event_slow;
7543
7544                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7545         }
7546
7547         if (work_done < budget) {
7548                 napi_complete(napi);
7549
7550                 rtl_irq_enable(tp, enable_mask);
7551                 mmiowb();
7552         }
7553
7554         return work_done;
7555 }
7556
7557 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7558 {
7559         struct rtl8169_private *tp = netdev_priv(dev);
7560
7561         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7562                 return;
7563
7564         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7565         RTL_W32(RxMissed, 0);
7566 }
7567
7568 static void rtl8169_down(struct net_device *dev)
7569 {
7570         struct rtl8169_private *tp = netdev_priv(dev);
7571         void __iomem *ioaddr = tp->mmio_addr;
7572
7573         del_timer_sync(&tp->timer);
7574
7575         napi_disable(&tp->napi);
7576         netif_stop_queue(dev);
7577
7578         rtl8169_hw_reset(tp);
7579         /*
7580          * At this point device interrupts can not be enabled in any function,
7581          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7582          * and napi is disabled (rtl8169_poll).
7583          */
7584         rtl8169_rx_missed(dev, ioaddr);
7585
7586         /* Give a racing hard_start_xmit a few cycles to complete. */
7587         synchronize_sched();
7588
7589         rtl8169_tx_clear(tp);
7590
7591         rtl8169_rx_clear(tp);
7592
7593         rtl_pll_power_down(tp);
7594 }
7595
7596 static int rtl8169_close(struct net_device *dev)
7597 {
7598         struct rtl8169_private *tp = netdev_priv(dev);
7599         struct pci_dev *pdev = tp->pci_dev;
7600
7601         pm_runtime_get_sync(&pdev->dev);
7602
7603         /* Update counters before going down */
7604         rtl8169_update_counters(dev);
7605
7606         rtl_lock_work(tp);
7607         /* Clear all task flags */
7608         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
7609
7610         rtl8169_down(dev);
7611         rtl_unlock_work(tp);
7612
7613         cancel_work_sync(&tp->wk.work);
7614
7615         free_irq(pdev->irq, dev);
7616
7617         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7618                           tp->RxPhyAddr);
7619         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7620                           tp->TxPhyAddr);
7621         tp->TxDescArray = NULL;
7622         tp->RxDescArray = NULL;
7623
7624         pm_runtime_put_sync(&pdev->dev);
7625
7626         return 0;
7627 }
7628
7629 #ifdef CONFIG_NET_POLL_CONTROLLER
7630 static void rtl8169_netpoll(struct net_device *dev)
7631 {
7632         struct rtl8169_private *tp = netdev_priv(dev);
7633
7634         rtl8169_interrupt(tp->pci_dev->irq, dev);
7635 }
7636 #endif
7637
7638 static int rtl_open(struct net_device *dev)
7639 {
7640         struct rtl8169_private *tp = netdev_priv(dev);
7641         void __iomem *ioaddr = tp->mmio_addr;
7642         struct pci_dev *pdev = tp->pci_dev;
7643         int retval = -ENOMEM;
7644
7645         pm_runtime_get_sync(&pdev->dev);
7646
7647         /*
7648          * Rx and Tx descriptors needs 256 bytes alignment.
7649          * dma_alloc_coherent provides more.
7650          */
7651         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7652                                              &tp->TxPhyAddr, GFP_KERNEL);
7653         if (!tp->TxDescArray)
7654                 goto err_pm_runtime_put;
7655
7656         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7657                                              &tp->RxPhyAddr, GFP_KERNEL);
7658         if (!tp->RxDescArray)
7659                 goto err_free_tx_0;
7660
7661         retval = rtl8169_init_ring(dev);
7662         if (retval < 0)
7663                 goto err_free_rx_1;
7664
7665         INIT_WORK(&tp->wk.work, rtl_task);
7666
7667         smp_mb();
7668
7669         rtl_request_firmware(tp);
7670
7671         retval = request_irq(pdev->irq, rtl8169_interrupt,
7672                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7673                              dev->name, dev);
7674         if (retval < 0)
7675                 goto err_release_fw_2;
7676
7677         rtl_lock_work(tp);
7678
7679         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7680
7681         napi_enable(&tp->napi);
7682
7683         rtl8169_init_phy(dev, tp);
7684
7685         __rtl8169_set_features(dev, dev->features);
7686
7687         rtl_pll_power_up(tp);
7688
7689         rtl_hw_start(dev);
7690
7691         if (!rtl8169_init_counter_offsets(dev))
7692                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7693
7694         netif_start_queue(dev);
7695
7696         rtl_unlock_work(tp);
7697
7698         tp->saved_wolopts = 0;
7699         pm_runtime_put_noidle(&pdev->dev);
7700
7701         rtl8169_check_link_status(dev, tp, ioaddr);
7702 out:
7703         return retval;
7704
7705 err_release_fw_2:
7706         rtl_release_firmware(tp);
7707         rtl8169_rx_clear(tp);
7708 err_free_rx_1:
7709         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7710                           tp->RxPhyAddr);
7711         tp->RxDescArray = NULL;
7712 err_free_tx_0:
7713         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7714                           tp->TxPhyAddr);
7715         tp->TxDescArray = NULL;
7716 err_pm_runtime_put:
7717         pm_runtime_put_noidle(&pdev->dev);
7718         goto out;
7719 }
7720
7721 static struct rtnl_link_stats64 *
7722 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7723 {
7724         struct rtl8169_private *tp = netdev_priv(dev);
7725         void __iomem *ioaddr = tp->mmio_addr;
7726         struct rtl8169_counters *counters = tp->counters;
7727         unsigned int start;
7728
7729         if (netif_running(dev))
7730                 rtl8169_rx_missed(dev, ioaddr);
7731
7732         do {
7733                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7734                 stats->rx_packets = tp->rx_stats.packets;
7735                 stats->rx_bytes = tp->rx_stats.bytes;
7736         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7737
7738         do {
7739                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7740                 stats->tx_packets = tp->tx_stats.packets;
7741                 stats->tx_bytes = tp->tx_stats.bytes;
7742         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7743
7744         stats->rx_dropped       = dev->stats.rx_dropped;
7745         stats->tx_dropped       = dev->stats.tx_dropped;
7746         stats->rx_length_errors = dev->stats.rx_length_errors;
7747         stats->rx_errors        = dev->stats.rx_errors;
7748         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
7749         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
7750         stats->rx_missed_errors = dev->stats.rx_missed_errors;
7751         stats->multicast        = dev->stats.multicast;
7752
7753         /*
7754          * Fetch additonal counter values missing in stats collected by driver
7755          * from tally counters.
7756          */
7757         rtl8169_update_counters(dev);
7758
7759         /*
7760          * Subtract values fetched during initalization.
7761          * See rtl8169_init_counter_offsets for a description why we do that.
7762          */
7763         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
7764                 le64_to_cpu(tp->tc_offset.tx_errors);
7765         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
7766                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
7767         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
7768                 le16_to_cpu(tp->tc_offset.tx_aborted);
7769
7770         return stats;
7771 }
7772
7773 static void rtl8169_net_suspend(struct net_device *dev)
7774 {
7775         struct rtl8169_private *tp = netdev_priv(dev);
7776
7777         if (!netif_running(dev))
7778                 return;
7779
7780         netif_device_detach(dev);
7781         netif_stop_queue(dev);
7782
7783         rtl_lock_work(tp);
7784         napi_disable(&tp->napi);
7785         /* Clear all task flags */
7786         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
7787
7788         rtl_unlock_work(tp);
7789
7790         rtl_pll_power_down(tp);
7791 }
7792
7793 #ifdef CONFIG_PM
7794
7795 static int rtl8169_suspend(struct device *device)
7796 {
7797         struct pci_dev *pdev = to_pci_dev(device);
7798         struct net_device *dev = pci_get_drvdata(pdev);
7799
7800         rtl8169_net_suspend(dev);
7801
7802         return 0;
7803 }
7804
7805 static void __rtl8169_resume(struct net_device *dev)
7806 {
7807         struct rtl8169_private *tp = netdev_priv(dev);
7808
7809         netif_device_attach(dev);
7810
7811         rtl_pll_power_up(tp);
7812
7813         rtl_lock_work(tp);
7814         napi_enable(&tp->napi);
7815         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7816         rtl_unlock_work(tp);
7817
7818         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7819 }
7820
7821 static int rtl8169_resume(struct device *device)
7822 {
7823         struct pci_dev *pdev = to_pci_dev(device);
7824         struct net_device *dev = pci_get_drvdata(pdev);
7825         struct rtl8169_private *tp = netdev_priv(dev);
7826
7827         rtl8169_init_phy(dev, tp);
7828
7829         if (netif_running(dev))
7830                 __rtl8169_resume(dev);
7831
7832         return 0;
7833 }
7834
7835 static int rtl8169_runtime_suspend(struct device *device)
7836 {
7837         struct pci_dev *pdev = to_pci_dev(device);
7838         struct net_device *dev = pci_get_drvdata(pdev);
7839         struct rtl8169_private *tp = netdev_priv(dev);
7840
7841         if (!tp->TxDescArray)
7842                 return 0;
7843
7844         rtl_lock_work(tp);
7845         tp->saved_wolopts = __rtl8169_get_wol(tp);
7846         __rtl8169_set_wol(tp, WAKE_ANY);
7847         rtl_unlock_work(tp);
7848
7849         rtl8169_net_suspend(dev);
7850
7851         return 0;
7852 }
7853
7854 static int rtl8169_runtime_resume(struct device *device)
7855 {
7856         struct pci_dev *pdev = to_pci_dev(device);
7857         struct net_device *dev = pci_get_drvdata(pdev);
7858         struct rtl8169_private *tp = netdev_priv(dev);
7859
7860         if (!tp->TxDescArray)
7861                 return 0;
7862
7863         rtl_lock_work(tp);
7864         __rtl8169_set_wol(tp, tp->saved_wolopts);
7865         tp->saved_wolopts = 0;
7866         rtl_unlock_work(tp);
7867
7868         rtl8169_init_phy(dev, tp);
7869
7870         __rtl8169_resume(dev);
7871
7872         return 0;
7873 }
7874
7875 static int rtl8169_runtime_idle(struct device *device)
7876 {
7877         struct pci_dev *pdev = to_pci_dev(device);
7878         struct net_device *dev = pci_get_drvdata(pdev);
7879         struct rtl8169_private *tp = netdev_priv(dev);
7880
7881         return tp->TxDescArray ? -EBUSY : 0;
7882 }
7883
7884 static const struct dev_pm_ops rtl8169_pm_ops = {
7885         .suspend                = rtl8169_suspend,
7886         .resume                 = rtl8169_resume,
7887         .freeze                 = rtl8169_suspend,
7888         .thaw                   = rtl8169_resume,
7889         .poweroff               = rtl8169_suspend,
7890         .restore                = rtl8169_resume,
7891         .runtime_suspend        = rtl8169_runtime_suspend,
7892         .runtime_resume         = rtl8169_runtime_resume,
7893         .runtime_idle           = rtl8169_runtime_idle,
7894 };
7895
7896 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
7897
7898 #else /* !CONFIG_PM */
7899
7900 #define RTL8169_PM_OPS  NULL
7901
7902 #endif /* !CONFIG_PM */
7903
7904 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7905 {
7906         void __iomem *ioaddr = tp->mmio_addr;
7907
7908         /* WoL fails with 8168b when the receiver is disabled. */
7909         switch (tp->mac_version) {
7910         case RTL_GIGA_MAC_VER_11:
7911         case RTL_GIGA_MAC_VER_12:
7912         case RTL_GIGA_MAC_VER_17:
7913                 pci_clear_master(tp->pci_dev);
7914
7915                 RTL_W8(ChipCmd, CmdRxEnb);
7916                 /* PCI commit */
7917                 RTL_R8(ChipCmd);
7918                 break;
7919         default:
7920                 break;
7921         }
7922 }
7923
7924 static void rtl_shutdown(struct pci_dev *pdev)
7925 {
7926         struct net_device *dev = pci_get_drvdata(pdev);
7927         struct rtl8169_private *tp = netdev_priv(dev);
7928         struct device *d = &pdev->dev;
7929
7930         pm_runtime_get_sync(d);
7931
7932         rtl8169_net_suspend(dev);
7933
7934         /* Restore original MAC address */
7935         rtl_rar_set(tp, dev->perm_addr);
7936
7937         rtl8169_hw_reset(tp);
7938
7939         if (system_state == SYSTEM_POWER_OFF) {
7940                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7941                         rtl_wol_suspend_quirk(tp);
7942                         rtl_wol_shutdown_quirk(tp);
7943                 }
7944
7945                 pci_wake_from_d3(pdev, true);
7946                 pci_set_power_state(pdev, PCI_D3hot);
7947         }
7948
7949         pm_runtime_put_noidle(d);
7950 }
7951
7952 static void rtl_remove_one(struct pci_dev *pdev)
7953 {
7954         struct net_device *dev = pci_get_drvdata(pdev);
7955         struct rtl8169_private *tp = netdev_priv(dev);
7956
7957         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7958              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7959              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
7960              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
7961              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
7962              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
7963             r8168_check_dash(tp)) {
7964                 rtl8168_driver_stop(tp);
7965         }
7966
7967         netif_napi_del(&tp->napi);
7968
7969         unregister_netdev(dev);
7970
7971         dma_free_coherent(&tp->pci_dev->dev, sizeof(*tp->counters),
7972                           tp->counters, tp->counters_phys_addr);
7973
7974         rtl_release_firmware(tp);
7975
7976         if (pci_dev_run_wake(pdev))
7977                 pm_runtime_get_noresume(&pdev->dev);
7978
7979         /* restore original MAC address */
7980         rtl_rar_set(tp, dev->perm_addr);
7981
7982         rtl_disable_msi(pdev, tp);
7983         rtl8169_release_board(pdev, dev, tp->mmio_addr);
7984 }
7985
7986 static const struct net_device_ops rtl_netdev_ops = {
7987         .ndo_open               = rtl_open,
7988         .ndo_stop               = rtl8169_close,
7989         .ndo_get_stats64        = rtl8169_get_stats64,
7990         .ndo_start_xmit         = rtl8169_start_xmit,
7991         .ndo_tx_timeout         = rtl8169_tx_timeout,
7992         .ndo_validate_addr      = eth_validate_addr,
7993         .ndo_change_mtu         = rtl8169_change_mtu,
7994         .ndo_fix_features       = rtl8169_fix_features,
7995         .ndo_set_features       = rtl8169_set_features,
7996         .ndo_set_mac_address    = rtl_set_mac_address,
7997         .ndo_do_ioctl           = rtl8169_ioctl,
7998         .ndo_set_rx_mode        = rtl_set_rx_mode,
7999 #ifdef CONFIG_NET_POLL_CONTROLLER
8000         .ndo_poll_controller    = rtl8169_netpoll,
8001 #endif
8002
8003 };
8004
8005 static const struct rtl_cfg_info {
8006         void (*hw_start)(struct net_device *);
8007         unsigned int region;
8008         unsigned int align;
8009         u16 event_slow;
8010         unsigned features;
8011         u8 default_ver;
8012 } rtl_cfg_infos [] = {
8013         [RTL_CFG_0] = {
8014                 .hw_start       = rtl_hw_start_8169,
8015                 .region         = 1,
8016                 .align          = 0,
8017                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8018                 .features       = RTL_FEATURE_GMII,
8019                 .default_ver    = RTL_GIGA_MAC_VER_01,
8020         },
8021         [RTL_CFG_1] = {
8022                 .hw_start       = rtl_hw_start_8168,
8023                 .region         = 2,
8024                 .align          = 8,
8025                 .event_slow     = SYSErr | LinkChg | RxOverflow,
8026                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8027                 .default_ver    = RTL_GIGA_MAC_VER_11,
8028         },
8029         [RTL_CFG_2] = {
8030                 .hw_start       = rtl_hw_start_8101,
8031                 .region         = 2,
8032                 .align          = 8,
8033                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8034                                   PCSTimeout,
8035                 .features       = RTL_FEATURE_MSI,
8036                 .default_ver    = RTL_GIGA_MAC_VER_13,
8037         }
8038 };
8039
8040 /* Cfg9346_Unlock assumed. */
8041 static unsigned rtl_try_msi(struct rtl8169_private *tp,
8042                             const struct rtl_cfg_info *cfg)
8043 {
8044         void __iomem *ioaddr = tp->mmio_addr;
8045         unsigned msi = 0;
8046         u8 cfg2;
8047
8048         cfg2 = RTL_R8(Config2) & ~MSIEnable;
8049         if (cfg->features & RTL_FEATURE_MSI) {
8050                 if (pci_enable_msi(tp->pci_dev)) {
8051                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8052                 } else {
8053                         cfg2 |= MSIEnable;
8054                         msi = RTL_FEATURE_MSI;
8055                 }
8056         }
8057         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8058                 RTL_W8(Config2, cfg2);
8059         return msi;
8060 }
8061
8062 DECLARE_RTL_COND(rtl_link_list_ready_cond)
8063 {
8064         void __iomem *ioaddr = tp->mmio_addr;
8065
8066         return RTL_R8(MCU) & LINK_LIST_RDY;
8067 }
8068
8069 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8070 {
8071         void __iomem *ioaddr = tp->mmio_addr;
8072
8073         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8074 }
8075
8076 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8077 {
8078         void __iomem *ioaddr = tp->mmio_addr;
8079         u32 data;
8080
8081         tp->ocp_base = OCP_STD_PHY_BASE;
8082
8083         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8084
8085         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8086                 return;
8087
8088         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8089                 return;
8090
8091         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8092         msleep(1);
8093         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8094
8095         data = r8168_mac_ocp_read(tp, 0xe8de);
8096         data &= ~(1 << 14);
8097         r8168_mac_ocp_write(tp, 0xe8de, data);
8098
8099         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8100                 return;
8101
8102         data = r8168_mac_ocp_read(tp, 0xe8de);
8103         data |= (1 << 15);
8104         r8168_mac_ocp_write(tp, 0xe8de, data);
8105
8106         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8107                 return;
8108 }
8109
8110 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8111 {
8112         rtl8168ep_stop_cmac(tp);
8113         rtl_hw_init_8168g(tp);
8114 }
8115
8116 static void rtl_hw_initialize(struct rtl8169_private *tp)
8117 {
8118         switch (tp->mac_version) {
8119         case RTL_GIGA_MAC_VER_40:
8120         case RTL_GIGA_MAC_VER_41:
8121         case RTL_GIGA_MAC_VER_42:
8122         case RTL_GIGA_MAC_VER_43:
8123         case RTL_GIGA_MAC_VER_44:
8124         case RTL_GIGA_MAC_VER_45:
8125         case RTL_GIGA_MAC_VER_46:
8126         case RTL_GIGA_MAC_VER_47:
8127         case RTL_GIGA_MAC_VER_48:
8128                 rtl_hw_init_8168g(tp);
8129                 break;
8130         case RTL_GIGA_MAC_VER_49:
8131         case RTL_GIGA_MAC_VER_50:
8132         case RTL_GIGA_MAC_VER_51:
8133                 rtl_hw_init_8168ep(tp);
8134                 break;
8135         default:
8136                 break;
8137         }
8138 }
8139
8140 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8141 {
8142         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8143         const unsigned int region = cfg->region;
8144         struct rtl8169_private *tp;
8145         struct mii_if_info *mii;
8146         struct net_device *dev;
8147         void __iomem *ioaddr;
8148         int chipset, i;
8149         int rc;
8150
8151         if (netif_msg_drv(&debug)) {
8152                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8153                        MODULENAME, RTL8169_VERSION);
8154         }
8155
8156         dev = alloc_etherdev(sizeof (*tp));
8157         if (!dev) {
8158                 rc = -ENOMEM;
8159                 goto out;
8160         }
8161
8162         SET_NETDEV_DEV(dev, &pdev->dev);
8163         dev->netdev_ops = &rtl_netdev_ops;
8164         tp = netdev_priv(dev);
8165         tp->dev = dev;
8166         tp->pci_dev = pdev;
8167         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8168
8169         mii = &tp->mii;
8170         mii->dev = dev;
8171         mii->mdio_read = rtl_mdio_read;
8172         mii->mdio_write = rtl_mdio_write;
8173         mii->phy_id_mask = 0x1f;
8174         mii->reg_num_mask = 0x1f;
8175         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8176
8177         /* disable ASPM completely as that cause random device stop working
8178          * problems as well as full system hangs for some PCIe devices users */
8179         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8180                                      PCIE_LINK_STATE_CLKPM);
8181
8182         /* enable device (incl. PCI PM wakeup and hotplug setup) */
8183         rc = pci_enable_device(pdev);
8184         if (rc < 0) {
8185                 netif_err(tp, probe, dev, "enable failure\n");
8186                 goto err_out_free_dev_1;
8187         }
8188
8189         if (pci_set_mwi(pdev) < 0)
8190                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8191
8192         /* make sure PCI base addr 1 is MMIO */
8193         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8194                 netif_err(tp, probe, dev,
8195                           "region #%d not an MMIO resource, aborting\n",
8196                           region);
8197                 rc = -ENODEV;
8198                 goto err_out_mwi_2;
8199         }
8200
8201         /* check for weird/broken PCI region reporting */
8202         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8203                 netif_err(tp, probe, dev,
8204                           "Invalid PCI region size(s), aborting\n");
8205                 rc = -ENODEV;
8206                 goto err_out_mwi_2;
8207         }
8208
8209         rc = pci_request_regions(pdev, MODULENAME);
8210         if (rc < 0) {
8211                 netif_err(tp, probe, dev, "could not request regions\n");
8212                 goto err_out_mwi_2;
8213         }
8214
8215         tp->cp_cmd = 0;
8216
8217         if ((sizeof(dma_addr_t) > 4) &&
8218             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
8219                 tp->cp_cmd |= PCIDAC;
8220                 dev->features |= NETIF_F_HIGHDMA;
8221         } else {
8222                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8223                 if (rc < 0) {
8224                         netif_err(tp, probe, dev, "DMA configuration failed\n");
8225                         goto err_out_free_res_3;
8226                 }
8227         }
8228
8229         /* ioremap MMIO region */
8230         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8231         if (!ioaddr) {
8232                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8233                 rc = -EIO;
8234                 goto err_out_free_res_3;
8235         }
8236         tp->mmio_addr = ioaddr;
8237
8238         if (!pci_is_pcie(pdev))
8239                 netif_info(tp, probe, dev, "not PCI Express\n");
8240
8241         /* Identify chip attached to board */
8242         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8243
8244         rtl_init_rxcfg(tp);
8245
8246         rtl_irq_disable(tp);
8247
8248         rtl_hw_initialize(tp);
8249
8250         rtl_hw_reset(tp);
8251
8252         rtl_ack_events(tp, 0xffff);
8253
8254         pci_set_master(pdev);
8255
8256         rtl_init_mdio_ops(tp);
8257         rtl_init_pll_power_ops(tp);
8258         rtl_init_jumbo_ops(tp);
8259         rtl_init_csi_ops(tp);
8260
8261         rtl8169_print_mac_version(tp);
8262
8263         chipset = tp->mac_version;
8264         tp->txd_version = rtl_chip_infos[chipset].txd_version;
8265
8266         RTL_W8(Cfg9346, Cfg9346_Unlock);
8267         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8268         RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8269         switch (tp->mac_version) {
8270         case RTL_GIGA_MAC_VER_34:
8271         case RTL_GIGA_MAC_VER_35:
8272         case RTL_GIGA_MAC_VER_36:
8273         case RTL_GIGA_MAC_VER_37:
8274         case RTL_GIGA_MAC_VER_38:
8275         case RTL_GIGA_MAC_VER_40:
8276         case RTL_GIGA_MAC_VER_41:
8277         case RTL_GIGA_MAC_VER_42:
8278         case RTL_GIGA_MAC_VER_43:
8279         case RTL_GIGA_MAC_VER_44:
8280         case RTL_GIGA_MAC_VER_45:
8281         case RTL_GIGA_MAC_VER_46:
8282         case RTL_GIGA_MAC_VER_47:
8283         case RTL_GIGA_MAC_VER_48:
8284         case RTL_GIGA_MAC_VER_49:
8285         case RTL_GIGA_MAC_VER_50:
8286         case RTL_GIGA_MAC_VER_51:
8287                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8288                         tp->features |= RTL_FEATURE_WOL;
8289                 if ((RTL_R8(Config3) & LinkUp) != 0)
8290                         tp->features |= RTL_FEATURE_WOL;
8291                 break;
8292         default:
8293                 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8294                         tp->features |= RTL_FEATURE_WOL;
8295                 break;
8296         }
8297         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8298                 tp->features |= RTL_FEATURE_WOL;
8299         tp->features |= rtl_try_msi(tp, cfg);
8300         RTL_W8(Cfg9346, Cfg9346_Lock);
8301
8302         if (rtl_tbi_enabled(tp)) {
8303                 tp->set_speed = rtl8169_set_speed_tbi;
8304                 tp->get_settings = rtl8169_gset_tbi;
8305                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8306                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8307                 tp->link_ok = rtl8169_tbi_link_ok;
8308                 tp->do_ioctl = rtl_tbi_ioctl;
8309         } else {
8310                 tp->set_speed = rtl8169_set_speed_xmii;
8311                 tp->get_settings = rtl8169_gset_xmii;
8312                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8313                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8314                 tp->link_ok = rtl8169_xmii_link_ok;
8315                 tp->do_ioctl = rtl_xmii_ioctl;
8316         }
8317
8318         mutex_init(&tp->wk.mutex);
8319         u64_stats_init(&tp->rx_stats.syncp);
8320         u64_stats_init(&tp->tx_stats.syncp);
8321
8322         /* Get MAC address */
8323         if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8324             tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8325             tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8326             tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8327             tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8328             tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8329             tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8330             tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8331             tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8332             tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8333             tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8334             tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8335             tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8336             tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8337             tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8338             tp->mac_version == RTL_GIGA_MAC_VER_51) {
8339                 u16 mac_addr[3];
8340
8341                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8342                 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8343
8344                 if (is_valid_ether_addr((u8 *)mac_addr))
8345                         rtl_rar_set(tp, (u8 *)mac_addr);
8346         }
8347         for (i = 0; i < ETH_ALEN; i++)
8348                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8349
8350         dev->ethtool_ops = &rtl8169_ethtool_ops;
8351         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8352
8353         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8354
8355         /* don't enable SG, IP_CSUM and TSO by default - it might not work
8356          * properly for all devices */
8357         dev->features |= NETIF_F_RXCSUM |
8358                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8359
8360         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8361                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8362                 NETIF_F_HW_VLAN_CTAG_RX;
8363         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8364                 NETIF_F_HIGHDMA;
8365
8366         tp->cp_cmd |= RxChkSum | RxVlan;
8367
8368         /*
8369          * Pretend we are using VLANs; This bypasses a nasty bug where
8370          * Interrupts stop flowing on high load on 8110SCd controllers.
8371          */
8372         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8373                 /* Disallow toggling */
8374                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8375
8376         if (tp->txd_version == RTL_TD_0)
8377                 tp->tso_csum = rtl8169_tso_csum_v1;
8378         else if (tp->txd_version == RTL_TD_1) {
8379                 tp->tso_csum = rtl8169_tso_csum_v2;
8380                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8381         } else
8382                 WARN_ON_ONCE(1);
8383
8384         dev->hw_features |= NETIF_F_RXALL;
8385         dev->hw_features |= NETIF_F_RXFCS;
8386
8387         tp->hw_start = cfg->hw_start;
8388         tp->event_slow = cfg->event_slow;
8389
8390         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8391                 ~(RxBOVF | RxFOVF) : ~0;
8392
8393         init_timer(&tp->timer);
8394         tp->timer.data = (unsigned long) dev;
8395         tp->timer.function = rtl8169_phy_timer;
8396
8397         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8398
8399         tp->counters = dma_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8400                                            &tp->counters_phys_addr, GFP_KERNEL);
8401         if (!tp->counters) {
8402                 rc = -ENOMEM;
8403                 goto err_out_msi_4;
8404         }
8405
8406         pci_set_drvdata(pdev, dev);
8407
8408         rc = register_netdev(dev);
8409         if (rc < 0)
8410                 goto err_out_cnt_5;
8411
8412         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8413                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8414                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8415         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8416                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8417                            "tx checksumming: %s]\n",
8418                            rtl_chip_infos[chipset].jumbo_max,
8419                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8420         }
8421
8422         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8423              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8424              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8425              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8426              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8427              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8428             r8168_check_dash(tp)) {
8429                 rtl8168_driver_start(tp);
8430         }
8431
8432         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8433
8434         if (pci_dev_run_wake(pdev))
8435                 pm_runtime_put_noidle(&pdev->dev);
8436
8437         netif_carrier_off(dev);
8438
8439 out:
8440         return rc;
8441
8442 err_out_cnt_5:
8443         dma_free_coherent(&pdev->dev, sizeof(*tp->counters), tp->counters,
8444                           tp->counters_phys_addr);
8445 err_out_msi_4:
8446         netif_napi_del(&tp->napi);
8447         rtl_disable_msi(pdev, tp);
8448         iounmap(ioaddr);
8449 err_out_free_res_3:
8450         pci_release_regions(pdev);
8451 err_out_mwi_2:
8452         pci_clear_mwi(pdev);
8453         pci_disable_device(pdev);
8454 err_out_free_dev_1:
8455         free_netdev(dev);
8456         goto out;
8457 }
8458
8459 static struct pci_driver rtl8169_pci_driver = {
8460         .name           = MODULENAME,
8461         .id_table       = rtl8169_pci_tbl,
8462         .probe          = rtl_init_one,
8463         .remove         = rtl_remove_one,
8464         .shutdown       = rtl_shutdown,
8465         .driver.pm      = RTL8169_PM_OPS,
8466 };
8467
8468 module_pci_driver(rtl8169_pci_driver);