2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "/*(DEBLOBBED)*/"
41 #define FIRMWARE_8168D_2 "/*(DEBLOBBED)*/"
42 #define FIRMWARE_8168E_1 "/*(DEBLOBBED)*/"
43 #define FIRMWARE_8168E_2 "/*(DEBLOBBED)*/"
44 #define FIRMWARE_8168E_3 "/*(DEBLOBBED)*/"
45 #define FIRMWARE_8168F_1 "/*(DEBLOBBED)*/"
46 #define FIRMWARE_8168F_2 "/*(DEBLOBBED)*/"
47 #define FIRMWARE_8105E_1 "/*(DEBLOBBED)*/"
48 #define FIRMWARE_8402_1 "/*(DEBLOBBED)*/"
49 #define FIRMWARE_8411_1 "/*(DEBLOBBED)*/"
50 #define FIRMWARE_8411_2 "/*(DEBLOBBED)*/"
51 #define FIRMWARE_8106E_1 "/*(DEBLOBBED)*/"
52 #define FIRMWARE_8106E_2 "/*(DEBLOBBED)*/"
53 #define FIRMWARE_8168G_2 "/*(DEBLOBBED)*/"
54 #define FIRMWARE_8168G_3 "/*(DEBLOBBED)*/"
55 #define FIRMWARE_8168H_1 "/*(DEBLOBBED)*/"
56 #define FIRMWARE_8168H_2 "/*(DEBLOBBED)*/"
57 #define FIRMWARE_8107E_1 "/*(DEBLOBBED)*/"
58 #define FIRMWARE_8107E_2 "/*(DEBLOBBED)*/"
61 #define assert(expr) \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
64 #expr,__FILE__,__func__,__LINE__); \
66 #define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
69 #define assert(expr) do {} while (0)
70 #define dprintk(fmt, args...) do {} while (0)
71 #endif /* RTL8169_DEBUG */
73 #define R8169_MSG_DEFAULT \
74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
76 #define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit = 32;
87 #define MAX_READ_REQUEST_SHIFT 12
88 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
89 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
91 #define R8169_REGS_SIZE 256
92 #define R8169_NAPI_WEIGHT 64
93 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
94 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
95 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
98 #define RTL8169_TX_TIMEOUT (6*HZ)
99 #define RTL8169_PHY_TIMEOUT (10*HZ)
101 /* write/read MMIO register */
102 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105 #define RTL_R8(reg) readb (ioaddr + (reg))
106 #define RTL_R16(reg) readw (ioaddr + (reg))
107 #define RTL_R32(reg) readl (ioaddr + (reg))
110 RTL_GIGA_MAC_VER_01 = 0,
161 RTL_GIGA_MAC_NONE = 0xff,
164 enum rtl_tx_desc_version {
169 #define JUMBO_1K ETH_DATA_LEN
170 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
175 #define _R(NAME,TD,FW,SZ,B) { \
183 static const struct {
185 enum rtl_tx_desc_version txd_version;
189 } rtl_chip_infos[] = {
191 [RTL_GIGA_MAC_VER_01] =
192 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
193 [RTL_GIGA_MAC_VER_02] =
194 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
195 [RTL_GIGA_MAC_VER_03] =
196 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
197 [RTL_GIGA_MAC_VER_04] =
198 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
199 [RTL_GIGA_MAC_VER_05] =
200 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
201 [RTL_GIGA_MAC_VER_06] =
202 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
204 [RTL_GIGA_MAC_VER_07] =
205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
206 [RTL_GIGA_MAC_VER_08] =
207 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
208 [RTL_GIGA_MAC_VER_09] =
209 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
210 [RTL_GIGA_MAC_VER_10] =
211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
212 [RTL_GIGA_MAC_VER_11] =
213 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
214 [RTL_GIGA_MAC_VER_12] =
215 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
216 [RTL_GIGA_MAC_VER_13] =
217 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
218 [RTL_GIGA_MAC_VER_14] =
219 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
220 [RTL_GIGA_MAC_VER_15] =
221 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
222 [RTL_GIGA_MAC_VER_16] =
223 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
224 [RTL_GIGA_MAC_VER_17] =
225 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
226 [RTL_GIGA_MAC_VER_18] =
227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
228 [RTL_GIGA_MAC_VER_19] =
229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
230 [RTL_GIGA_MAC_VER_20] =
231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
232 [RTL_GIGA_MAC_VER_21] =
233 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
234 [RTL_GIGA_MAC_VER_22] =
235 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
236 [RTL_GIGA_MAC_VER_23] =
237 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
238 [RTL_GIGA_MAC_VER_24] =
239 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
240 [RTL_GIGA_MAC_VER_25] =
241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
243 [RTL_GIGA_MAC_VER_26] =
244 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
246 [RTL_GIGA_MAC_VER_27] =
247 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
248 [RTL_GIGA_MAC_VER_28] =
249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
250 [RTL_GIGA_MAC_VER_29] =
251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
253 [RTL_GIGA_MAC_VER_30] =
254 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
256 [RTL_GIGA_MAC_VER_31] =
257 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
258 [RTL_GIGA_MAC_VER_32] =
259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
261 [RTL_GIGA_MAC_VER_33] =
262 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
264 [RTL_GIGA_MAC_VER_34] =
265 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
267 [RTL_GIGA_MAC_VER_35] =
268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
270 [RTL_GIGA_MAC_VER_36] =
271 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
273 [RTL_GIGA_MAC_VER_37] =
274 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
276 [RTL_GIGA_MAC_VER_38] =
277 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
279 [RTL_GIGA_MAC_VER_39] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
282 [RTL_GIGA_MAC_VER_40] =
283 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
285 [RTL_GIGA_MAC_VER_41] =
286 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
287 [RTL_GIGA_MAC_VER_42] =
288 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
290 [RTL_GIGA_MAC_VER_43] =
291 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
293 [RTL_GIGA_MAC_VER_44] =
294 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
296 [RTL_GIGA_MAC_VER_45] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
299 [RTL_GIGA_MAC_VER_46] =
300 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
302 [RTL_GIGA_MAC_VER_47] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
305 [RTL_GIGA_MAC_VER_48] =
306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
326 static const struct pci_device_id rtl8169_pci_tbl[] = {
327 { PCI_VDEVICE(REALTEK, 0x2502), RTL_CFG_1 },
328 { PCI_VDEVICE(REALTEK, 0x2600), RTL_CFG_1 },
329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
332 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
333 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
334 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
335 { PCI_VENDOR_ID_DLINK, 0x4300,
336 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
337 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
338 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
339 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
340 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
341 { PCI_VENDOR_ID_LINKSYS, 0x1032,
342 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
344 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
348 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
350 static int rx_buf_sz = 16383;
357 MAC0 = 0, /* Ethernet hardware address. */
359 MAR0 = 8, /* Multicast filter. */
360 CounterAddrLow = 0x10,
361 CounterAddrHigh = 0x14,
362 TxDescStartAddrLow = 0x20,
363 TxDescStartAddrHigh = 0x24,
364 TxHDescStartAddrLow = 0x28,
365 TxHDescStartAddrHigh = 0x2c,
374 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
375 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
378 #define RX128_INT_EN (1 << 15) /* 8111c and later */
379 #define RX_MULTI_EN (1 << 14) /* 8111c only */
380 #define RXCFG_FIFO_SHIFT 13
381 /* No threshold before first PCI xfer */
382 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
383 #define RX_EARLY_OFF (1 << 11)
384 #define RXCFG_DMA_SHIFT 8
385 /* Unlimited maximum PCI burst. */
386 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
393 #define PME_SIGNAL (1 << 5) /* 8168c and later */
404 RxDescAddrLow = 0xe4,
405 RxDescAddrHigh = 0xe8,
406 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
408 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
410 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
412 #define TxPacketMax (8064 >> 7)
413 #define EarlySize 0x27
416 FuncEventMask = 0xf4,
417 FuncPresetState = 0xf8,
422 FuncForceEvent = 0xfc,
425 enum rtl8110_registers {
431 enum rtl8168_8101_registers {
434 #define CSIAR_FLAG 0x80000000
435 #define CSIAR_WRITE_CMD 0x80000000
436 #define CSIAR_BYTE_ENABLE 0x0f
437 #define CSIAR_BYTE_ENABLE_SHIFT 12
438 #define CSIAR_ADDR_MASK 0x0fff
439 #define CSIAR_FUNC_CARD 0x00000000
440 #define CSIAR_FUNC_SDIO 0x00010000
441 #define CSIAR_FUNC_NIC 0x00020000
442 #define CSIAR_FUNC_NIC2 0x00010000
445 #define EPHYAR_FLAG 0x80000000
446 #define EPHYAR_WRITE_CMD 0x80000000
447 #define EPHYAR_REG_MASK 0x1f
448 #define EPHYAR_REG_SHIFT 16
449 #define EPHYAR_DATA_MASK 0xffff
451 #define PFM_EN (1 << 6)
452 #define TX_10M_PS_EN (1 << 7)
454 #define FIX_NAK_1 (1 << 4)
455 #define FIX_NAK_2 (1 << 3)
458 #define NOW_IS_OOB (1 << 7)
459 #define TX_EMPTY (1 << 5)
460 #define RX_EMPTY (1 << 4)
461 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
462 #define EN_NDP (1 << 3)
463 #define EN_OOB_RESET (1 << 2)
464 #define LINK_LIST_RDY (1 << 1)
466 #define EFUSEAR_FLAG 0x80000000
467 #define EFUSEAR_WRITE_CMD 0x80000000
468 #define EFUSEAR_READ_CMD 0x00000000
469 #define EFUSEAR_REG_MASK 0x03ff
470 #define EFUSEAR_REG_SHIFT 8
471 #define EFUSEAR_DATA_MASK 0xff
473 #define PFM_D3COLD_EN (1 << 6)
476 enum rtl8168_registers {
481 #define ERIAR_FLAG 0x80000000
482 #define ERIAR_WRITE_CMD 0x80000000
483 #define ERIAR_READ_CMD 0x00000000
484 #define ERIAR_ADDR_BYTE_ALIGN 4
485 #define ERIAR_TYPE_SHIFT 16
486 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
487 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
488 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
489 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
490 #define ERIAR_MASK_SHIFT 12
491 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
492 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
493 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
494 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
495 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
496 EPHY_RXER_NUM = 0x7c,
497 OCPDR = 0xb0, /* OCP GPHY access */
498 #define OCPDR_WRITE_CMD 0x80000000
499 #define OCPDR_READ_CMD 0x00000000
500 #define OCPDR_REG_MASK 0x7f
501 #define OCPDR_GPHY_REG_SHIFT 16
502 #define OCPDR_DATA_MASK 0xffff
504 #define OCPAR_FLAG 0x80000000
505 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
506 #define OCPAR_GPHY_READ_CMD 0x0000f060
508 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
509 MISC = 0xf0, /* 8168e only. */
510 #define TXPLA_RST (1 << 29)
511 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
512 #define PWM_EN (1 << 22)
513 #define RXDV_GATED_EN (1 << 19)
514 #define EARLY_TALLY_EN (1 << 16)
517 enum rtl_register_content {
518 /* InterruptStatusBits */
522 TxDescUnavail = 0x0080,
546 /* TXPoll register p.5 */
547 HPQ = 0x80, /* Poll cmd on the high prio queue */
548 NPQ = 0x40, /* Poll cmd on the low prio queue */
549 FSWInt = 0x01, /* Forced software interrupt */
553 Cfg9346_Unlock = 0xc0,
558 AcceptBroadcast = 0x08,
559 AcceptMulticast = 0x04,
561 AcceptAllPhys = 0x01,
562 #define RX_CONFIG_ACCEPT_MASK 0x3f
565 TxInterFrameGapShift = 24,
566 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
568 /* Config1 register p.24 */
571 Speed_down = (1 << 4),
575 PMEnable = (1 << 0), /* Power Management Enable */
577 /* Config2 register p. 25 */
578 ClkReqEn = (1 << 7), /* Clock Request Enable */
579 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
580 PCI_Clock_66MHz = 0x01,
581 PCI_Clock_33MHz = 0x00,
583 /* Config3 register p.25 */
584 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
585 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
586 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
587 Rdy_to_L23 = (1 << 1), /* L23 Enable */
588 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
590 /* Config4 register */
591 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
593 /* Config5 register p.27 */
594 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
595 MWF = (1 << 5), /* Accept Multicast wakeup frame */
596 UWF = (1 << 4), /* Accept Unicast wakeup frame */
598 LanWake = (1 << 1), /* LanWake enable/disable */
599 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
600 ASPM_en = (1 << 0), /* ASPM enable */
603 TBIReset = 0x80000000,
604 TBILoopback = 0x40000000,
605 TBINwEnable = 0x20000000,
606 TBINwRestart = 0x10000000,
607 TBILinkOk = 0x02000000,
608 TBINwComplete = 0x01000000,
611 EnableBist = (1 << 15), // 8168 8101
612 Mac_dbgo_oe = (1 << 14), // 8168 8101
613 Normal_mode = (1 << 13), // unused
614 Force_half_dup = (1 << 12), // 8168 8101
615 Force_rxflow_en = (1 << 11), // 8168 8101
616 Force_txflow_en = (1 << 10), // 8168 8101
617 Cxpl_dbg_sel = (1 << 9), // 8168 8101
618 ASF = (1 << 8), // 8168 8101
619 PktCntrDisable = (1 << 7), // 8168 8101
620 Mac_dbgo_sel = 0x001c, // 8168
625 INTT_0 = 0x0000, // 8168
626 INTT_1 = 0x0001, // 8168
627 INTT_2 = 0x0002, // 8168
628 INTT_3 = 0x0003, // 8168
630 /* rtl8169_PHYstatus */
641 TBILinkOK = 0x02000000,
643 /* ResetCounterCommand */
646 /* DumpCounterCommand */
649 /* magic enable v2 */
650 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
654 /* First doubleword. */
655 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
656 RingEnd = (1 << 30), /* End of descriptor ring */
657 FirstFrag = (1 << 29), /* First segment of a packet */
658 LastFrag = (1 << 28), /* Final segment of a packet */
662 enum rtl_tx_desc_bit {
663 /* First doubleword. */
664 TD_LSO = (1 << 27), /* Large Send Offload */
665 #define TD_MSS_MAX 0x07ffu /* MSS value */
667 /* Second doubleword. */
668 TxVlanTag = (1 << 17), /* Add VLAN tag */
671 /* 8169, 8168b and 810x except 8102e. */
672 enum rtl_tx_desc_bit_0 {
673 /* First doubleword. */
674 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
675 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
676 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
677 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
680 /* 8102e, 8168c and beyond. */
681 enum rtl_tx_desc_bit_1 {
682 /* First doubleword. */
683 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
684 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
685 #define GTTCPHO_SHIFT 18
686 #define GTTCPHO_MAX 0x7fU
688 /* Second doubleword. */
689 #define TCPHO_SHIFT 18
690 #define TCPHO_MAX 0x3ffU
691 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
692 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
693 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
694 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
695 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
698 enum rtl_rx_desc_bit {
700 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
701 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
703 #define RxProtoUDP (PID1)
704 #define RxProtoTCP (PID0)
705 #define RxProtoIP (PID1 | PID0)
706 #define RxProtoMask RxProtoIP
708 IPFail = (1 << 16), /* IP checksum failed */
709 UDPFail = (1 << 15), /* UDP/IP checksum failed */
710 TCPFail = (1 << 14), /* TCP/IP checksum failed */
711 RxVlanTag = (1 << 16), /* VLAN tag available */
714 #define RsvdMask 0x3fffc000
731 u8 __pad[sizeof(void *) - sizeof(u32)];
735 RTL_FEATURE_WOL = (1 << 0),
736 RTL_FEATURE_MSI = (1 << 1),
737 RTL_FEATURE_GMII = (1 << 2),
740 struct rtl8169_counters {
747 __le32 tx_one_collision;
748 __le32 tx_multi_collision;
756 struct rtl8169_tc_offsets {
759 __le32 tx_multi_collision;
764 RTL_FLAG_TASK_ENABLED = 0,
765 RTL_FLAG_TASK_SLOW_PENDING,
766 RTL_FLAG_TASK_RESET_PENDING,
767 RTL_FLAG_TASK_PHY_PENDING,
771 struct rtl8169_stats {
774 struct u64_stats_sync syncp;
777 struct rtl8169_private {
778 void __iomem *mmio_addr; /* memory map physical address */
779 struct pci_dev *pci_dev;
780 struct net_device *dev;
781 struct napi_struct napi;
785 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
786 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
788 struct rtl8169_stats rx_stats;
789 struct rtl8169_stats tx_stats;
790 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
791 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
792 dma_addr_t TxPhyAddr;
793 dma_addr_t RxPhyAddr;
794 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
795 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
796 struct timer_list timer;
802 void (*write)(struct rtl8169_private *, int, int);
803 int (*read)(struct rtl8169_private *, int);
806 struct pll_power_ops {
807 void (*down)(struct rtl8169_private *);
808 void (*up)(struct rtl8169_private *);
812 void (*enable)(struct rtl8169_private *);
813 void (*disable)(struct rtl8169_private *);
817 void (*write)(struct rtl8169_private *, int, int);
818 u32 (*read)(struct rtl8169_private *, int);
821 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
822 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
823 void (*phy_reset_enable)(struct rtl8169_private *tp);
824 void (*hw_start)(struct net_device *);
825 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
826 unsigned int (*link_ok)(void __iomem *);
827 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
828 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
831 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
833 struct work_struct work;
838 struct mii_if_info mii;
839 dma_addr_t counters_phys_addr;
840 struct rtl8169_counters *counters;
841 struct rtl8169_tc_offsets tc_offset;
846 const struct firmware *fw;
848 #define RTL_VER_SIZE 32
850 char version[RTL_VER_SIZE];
852 struct rtl_fw_phy_action {
857 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
862 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
863 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
864 module_param(use_dac, int, 0);
865 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
866 module_param_named(debug, debug.msg_enable, int, 0);
867 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
868 MODULE_LICENSE("GPL");
869 MODULE_VERSION(RTL8169_VERSION);
872 static void rtl_lock_work(struct rtl8169_private *tp)
874 mutex_lock(&tp->wk.mutex);
877 static void rtl_unlock_work(struct rtl8169_private *tp)
879 mutex_unlock(&tp->wk.mutex);
882 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
884 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
885 PCI_EXP_DEVCTL_READRQ, force);
889 bool (*check)(struct rtl8169_private *);
893 static void rtl_udelay(unsigned int d)
898 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
899 void (*delay)(unsigned int), unsigned int d, int n,
904 for (i = 0; i < n; i++) {
906 if (c->check(tp) == high)
909 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
910 c->msg, !high, n, d);
914 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
915 const struct rtl_cond *c,
916 unsigned int d, int n)
918 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
921 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
922 const struct rtl_cond *c,
923 unsigned int d, int n)
925 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
928 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
929 const struct rtl_cond *c,
930 unsigned int d, int n)
932 return rtl_loop_wait(tp, c, msleep, d, n, true);
935 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
936 const struct rtl_cond *c,
937 unsigned int d, int n)
939 return rtl_loop_wait(tp, c, msleep, d, n, false);
942 #define DECLARE_RTL_COND(name) \
943 static bool name ## _check(struct rtl8169_private *); \
945 static const struct rtl_cond name = { \
946 .check = name ## _check, \
950 static bool name ## _check(struct rtl8169_private *tp)
952 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
954 if (reg & 0xffff0001) {
955 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
961 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
963 void __iomem *ioaddr = tp->mmio_addr;
965 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
968 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
970 void __iomem *ioaddr = tp->mmio_addr;
972 if (rtl_ocp_reg_failure(tp, reg))
975 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
977 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
980 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
982 void __iomem *ioaddr = tp->mmio_addr;
984 if (rtl_ocp_reg_failure(tp, reg))
987 RTL_W32(GPHY_OCP, reg << 15);
989 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
990 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
993 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
995 void __iomem *ioaddr = tp->mmio_addr;
997 if (rtl_ocp_reg_failure(tp, reg))
1000 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1003 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1005 void __iomem *ioaddr = tp->mmio_addr;
1007 if (rtl_ocp_reg_failure(tp, reg))
1010 RTL_W32(OCPDR, reg << 15);
1012 return RTL_R32(OCPDR);
1015 #define OCP_STD_PHY_BASE 0xa400
1017 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1020 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1024 if (tp->ocp_base != OCP_STD_PHY_BASE)
1027 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1030 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1032 if (tp->ocp_base != OCP_STD_PHY_BASE)
1035 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1038 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1041 tp->ocp_base = value << 4;
1045 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1048 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1050 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1053 DECLARE_RTL_COND(rtl_phyar_cond)
1055 void __iomem *ioaddr = tp->mmio_addr;
1057 return RTL_R32(PHYAR) & 0x80000000;
1060 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1062 void __iomem *ioaddr = tp->mmio_addr;
1064 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1066 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1068 * According to hardware specs a 20us delay is required after write
1069 * complete indication, but before sending next command.
1074 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1076 void __iomem *ioaddr = tp->mmio_addr;
1079 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1081 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1082 RTL_R32(PHYAR) & 0xffff : ~0;
1085 * According to hardware specs a 20us delay is required after read
1086 * complete indication, but before sending next command.
1093 DECLARE_RTL_COND(rtl_ocpar_cond)
1095 void __iomem *ioaddr = tp->mmio_addr;
1097 return RTL_R32(OCPAR) & OCPAR_FLAG;
1100 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1102 void __iomem *ioaddr = tp->mmio_addr;
1104 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1105 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1106 RTL_W32(EPHY_RXER_NUM, 0);
1108 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1111 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1113 r8168dp_1_mdio_access(tp, reg,
1114 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1117 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1119 void __iomem *ioaddr = tp->mmio_addr;
1121 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1124 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1125 RTL_W32(EPHY_RXER_NUM, 0);
1127 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1128 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1131 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1133 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1135 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1138 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1140 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1143 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1145 void __iomem *ioaddr = tp->mmio_addr;
1147 r8168dp_2_mdio_start(ioaddr);
1149 r8169_mdio_write(tp, reg, value);
1151 r8168dp_2_mdio_stop(ioaddr);
1154 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1156 void __iomem *ioaddr = tp->mmio_addr;
1159 r8168dp_2_mdio_start(ioaddr);
1161 value = r8169_mdio_read(tp, reg);
1163 r8168dp_2_mdio_stop(ioaddr);
1168 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1170 tp->mdio_ops.write(tp, location, val);
1173 static int rtl_readphy(struct rtl8169_private *tp, int location)
1175 return tp->mdio_ops.read(tp, location);
1178 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1180 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1183 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1187 val = rtl_readphy(tp, reg_addr);
1188 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1191 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1194 struct rtl8169_private *tp = netdev_priv(dev);
1196 rtl_writephy(tp, location, val);
1199 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1201 struct rtl8169_private *tp = netdev_priv(dev);
1203 return rtl_readphy(tp, location);
1206 DECLARE_RTL_COND(rtl_ephyar_cond)
1208 void __iomem *ioaddr = tp->mmio_addr;
1210 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1213 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1215 void __iomem *ioaddr = tp->mmio_addr;
1217 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1218 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1220 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1225 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1227 void __iomem *ioaddr = tp->mmio_addr;
1229 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1231 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1232 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1235 DECLARE_RTL_COND(rtl_eriar_cond)
1237 void __iomem *ioaddr = tp->mmio_addr;
1239 return RTL_R32(ERIAR) & ERIAR_FLAG;
1242 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1245 void __iomem *ioaddr = tp->mmio_addr;
1247 BUG_ON((addr & 3) || (mask == 0));
1248 RTL_W32(ERIDR, val);
1249 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1251 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1254 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1256 void __iomem *ioaddr = tp->mmio_addr;
1258 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1260 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1261 RTL_R32(ERIDR) : ~0;
1264 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1269 val = rtl_eri_read(tp, addr, type);
1270 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1273 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1275 void __iomem *ioaddr = tp->mmio_addr;
1277 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1278 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1279 RTL_R32(OCPDR) : ~0;
1282 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1284 return rtl_eri_read(tp, reg, ERIAR_OOB);
1287 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1289 switch (tp->mac_version) {
1290 case RTL_GIGA_MAC_VER_27:
1291 case RTL_GIGA_MAC_VER_28:
1292 case RTL_GIGA_MAC_VER_31:
1293 return r8168dp_ocp_read(tp, mask, reg);
1294 case RTL_GIGA_MAC_VER_49:
1295 case RTL_GIGA_MAC_VER_50:
1296 case RTL_GIGA_MAC_VER_51:
1297 return r8168ep_ocp_read(tp, mask, reg);
1304 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1307 void __iomem *ioaddr = tp->mmio_addr;
1309 RTL_W32(OCPDR, data);
1310 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1311 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1314 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1317 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1321 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1323 switch (tp->mac_version) {
1324 case RTL_GIGA_MAC_VER_27:
1325 case RTL_GIGA_MAC_VER_28:
1326 case RTL_GIGA_MAC_VER_31:
1327 r8168dp_ocp_write(tp, mask, reg, data);
1329 case RTL_GIGA_MAC_VER_49:
1330 case RTL_GIGA_MAC_VER_50:
1331 case RTL_GIGA_MAC_VER_51:
1332 r8168ep_ocp_write(tp, mask, reg, data);
1340 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1342 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1344 ocp_write(tp, 0x1, 0x30, 0x00000001);
1347 #define OOB_CMD_RESET 0x00
1348 #define OOB_CMD_DRIVER_START 0x05
1349 #define OOB_CMD_DRIVER_STOP 0x06
1351 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1353 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1356 DECLARE_RTL_COND(rtl_ocp_read_cond)
1360 reg = rtl8168_get_ocp_reg(tp);
1362 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1365 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1367 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1370 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1372 void __iomem *ioaddr = tp->mmio_addr;
1374 return RTL_R8(IBISR0) & 0x20;
1377 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1379 void __iomem *ioaddr = tp->mmio_addr;
1381 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1382 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1383 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1384 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1387 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1389 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1390 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1393 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1395 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1396 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1397 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1400 static void rtl8168_driver_start(struct rtl8169_private *tp)
1402 switch (tp->mac_version) {
1403 case RTL_GIGA_MAC_VER_27:
1404 case RTL_GIGA_MAC_VER_28:
1405 case RTL_GIGA_MAC_VER_31:
1406 rtl8168dp_driver_start(tp);
1408 case RTL_GIGA_MAC_VER_49:
1409 case RTL_GIGA_MAC_VER_50:
1410 case RTL_GIGA_MAC_VER_51:
1411 rtl8168ep_driver_start(tp);
1419 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1421 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1422 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1425 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1427 rtl8168ep_stop_cmac(tp);
1428 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1429 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1430 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1433 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1435 switch (tp->mac_version) {
1436 case RTL_GIGA_MAC_VER_27:
1437 case RTL_GIGA_MAC_VER_28:
1438 case RTL_GIGA_MAC_VER_31:
1439 rtl8168dp_driver_stop(tp);
1441 case RTL_GIGA_MAC_VER_49:
1442 case RTL_GIGA_MAC_VER_50:
1443 case RTL_GIGA_MAC_VER_51:
1444 rtl8168ep_driver_stop(tp);
1452 static int r8168dp_check_dash(struct rtl8169_private *tp)
1454 u16 reg = rtl8168_get_ocp_reg(tp);
1456 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1459 static int r8168ep_check_dash(struct rtl8169_private *tp)
1461 return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1464 static int r8168_check_dash(struct rtl8169_private *tp)
1466 switch (tp->mac_version) {
1467 case RTL_GIGA_MAC_VER_27:
1468 case RTL_GIGA_MAC_VER_28:
1469 case RTL_GIGA_MAC_VER_31:
1470 return r8168dp_check_dash(tp);
1471 case RTL_GIGA_MAC_VER_49:
1472 case RTL_GIGA_MAC_VER_50:
1473 case RTL_GIGA_MAC_VER_51:
1474 return r8168ep_check_dash(tp);
1486 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1487 const struct exgmac_reg *r, int len)
1490 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1495 DECLARE_RTL_COND(rtl_efusear_cond)
1497 void __iomem *ioaddr = tp->mmio_addr;
1499 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1502 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1504 void __iomem *ioaddr = tp->mmio_addr;
1506 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1508 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1509 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1512 static u16 rtl_get_events(struct rtl8169_private *tp)
1514 void __iomem *ioaddr = tp->mmio_addr;
1516 return RTL_R16(IntrStatus);
1519 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1521 void __iomem *ioaddr = tp->mmio_addr;
1523 RTL_W16(IntrStatus, bits);
1527 static void rtl_irq_disable(struct rtl8169_private *tp)
1529 void __iomem *ioaddr = tp->mmio_addr;
1531 RTL_W16(IntrMask, 0);
1535 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1537 void __iomem *ioaddr = tp->mmio_addr;
1539 RTL_W16(IntrMask, bits);
1542 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1543 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1544 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1546 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1548 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1551 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1553 void __iomem *ioaddr = tp->mmio_addr;
1555 rtl_irq_disable(tp);
1556 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1560 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1562 void __iomem *ioaddr = tp->mmio_addr;
1564 return RTL_R32(TBICSR) & TBIReset;
1567 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1569 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1572 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1574 return RTL_R32(TBICSR) & TBILinkOk;
1577 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1579 return RTL_R8(PHYstatus) & LinkStatus;
1582 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1584 void __iomem *ioaddr = tp->mmio_addr;
1586 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1589 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1593 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1594 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1597 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1599 void __iomem *ioaddr = tp->mmio_addr;
1600 struct net_device *dev = tp->dev;
1602 if (!netif_running(dev))
1605 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1606 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1607 if (RTL_R8(PHYstatus) & _1000bpsF) {
1608 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1610 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1612 } else if (RTL_R8(PHYstatus) & _100bps) {
1613 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1615 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1618 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1620 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1623 /* Reset packet filter */
1624 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1626 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1628 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1629 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1630 if (RTL_R8(PHYstatus) & _1000bpsF) {
1631 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1633 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1636 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1638 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1641 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1642 if (RTL_R8(PHYstatus) & _10bps) {
1643 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1645 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1648 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1654 static void __rtl8169_check_link_status(struct net_device *dev,
1655 struct rtl8169_private *tp,
1656 void __iomem *ioaddr, bool pm)
1658 if (tp->link_ok(ioaddr)) {
1659 rtl_link_chg_patch(tp);
1660 /* This is to cancel a scheduled suspend if there's one. */
1662 pm_request_resume(&tp->pci_dev->dev);
1663 netif_carrier_on(dev);
1664 if (net_ratelimit())
1665 netif_info(tp, ifup, dev, "link up\n");
1667 netif_carrier_off(dev);
1668 netif_info(tp, ifdown, dev, "link down\n");
1670 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1674 static void rtl8169_check_link_status(struct net_device *dev,
1675 struct rtl8169_private *tp,
1676 void __iomem *ioaddr)
1678 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1681 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1683 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1685 void __iomem *ioaddr = tp->mmio_addr;
1689 options = RTL_R8(Config1);
1690 if (!(options & PMEnable))
1693 options = RTL_R8(Config3);
1694 if (options & LinkUp)
1695 wolopts |= WAKE_PHY;
1696 switch (tp->mac_version) {
1697 case RTL_GIGA_MAC_VER_34:
1698 case RTL_GIGA_MAC_VER_35:
1699 case RTL_GIGA_MAC_VER_36:
1700 case RTL_GIGA_MAC_VER_37:
1701 case RTL_GIGA_MAC_VER_38:
1702 case RTL_GIGA_MAC_VER_40:
1703 case RTL_GIGA_MAC_VER_41:
1704 case RTL_GIGA_MAC_VER_42:
1705 case RTL_GIGA_MAC_VER_43:
1706 case RTL_GIGA_MAC_VER_44:
1707 case RTL_GIGA_MAC_VER_45:
1708 case RTL_GIGA_MAC_VER_46:
1709 case RTL_GIGA_MAC_VER_47:
1710 case RTL_GIGA_MAC_VER_48:
1711 case RTL_GIGA_MAC_VER_49:
1712 case RTL_GIGA_MAC_VER_50:
1713 case RTL_GIGA_MAC_VER_51:
1714 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1715 wolopts |= WAKE_MAGIC;
1718 if (options & MagicPacket)
1719 wolopts |= WAKE_MAGIC;
1723 options = RTL_R8(Config5);
1725 wolopts |= WAKE_UCAST;
1727 wolopts |= WAKE_BCAST;
1729 wolopts |= WAKE_MCAST;
1734 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1736 struct rtl8169_private *tp = netdev_priv(dev);
1740 wol->supported = WAKE_ANY;
1741 wol->wolopts = __rtl8169_get_wol(tp);
1743 rtl_unlock_work(tp);
1746 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1748 void __iomem *ioaddr = tp->mmio_addr;
1749 unsigned int i, tmp;
1750 static const struct {
1755 { WAKE_PHY, Config3, LinkUp },
1756 { WAKE_UCAST, Config5, UWF },
1757 { WAKE_BCAST, Config5, BWF },
1758 { WAKE_MCAST, Config5, MWF },
1759 { WAKE_ANY, Config5, LanWake },
1760 { WAKE_MAGIC, Config3, MagicPacket }
1764 RTL_W8(Cfg9346, Cfg9346_Unlock);
1766 switch (tp->mac_version) {
1767 case RTL_GIGA_MAC_VER_34:
1768 case RTL_GIGA_MAC_VER_35:
1769 case RTL_GIGA_MAC_VER_36:
1770 case RTL_GIGA_MAC_VER_37:
1771 case RTL_GIGA_MAC_VER_38:
1772 case RTL_GIGA_MAC_VER_40:
1773 case RTL_GIGA_MAC_VER_41:
1774 case RTL_GIGA_MAC_VER_42:
1775 case RTL_GIGA_MAC_VER_43:
1776 case RTL_GIGA_MAC_VER_44:
1777 case RTL_GIGA_MAC_VER_45:
1778 case RTL_GIGA_MAC_VER_46:
1779 case RTL_GIGA_MAC_VER_47:
1780 case RTL_GIGA_MAC_VER_48:
1781 case RTL_GIGA_MAC_VER_49:
1782 case RTL_GIGA_MAC_VER_50:
1783 case RTL_GIGA_MAC_VER_51:
1784 tmp = ARRAY_SIZE(cfg) - 1;
1785 if (wolopts & WAKE_MAGIC)
1801 tmp = ARRAY_SIZE(cfg);
1805 for (i = 0; i < tmp; i++) {
1806 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1807 if (wolopts & cfg[i].opt)
1808 options |= cfg[i].mask;
1809 RTL_W8(cfg[i].reg, options);
1812 switch (tp->mac_version) {
1813 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1814 options = RTL_R8(Config1) & ~PMEnable;
1816 options |= PMEnable;
1817 RTL_W8(Config1, options);
1820 options = RTL_R8(Config2) & ~PME_SIGNAL;
1822 options |= PME_SIGNAL;
1823 RTL_W8(Config2, options);
1827 RTL_W8(Cfg9346, Cfg9346_Lock);
1830 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1832 struct rtl8169_private *tp = netdev_priv(dev);
1837 tp->features |= RTL_FEATURE_WOL;
1839 tp->features &= ~RTL_FEATURE_WOL;
1840 __rtl8169_set_wol(tp, wol->wolopts);
1842 rtl_unlock_work(tp);
1844 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1849 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1851 return rtl_chip_infos[tp->mac_version].fw_name;
1854 static void rtl8169_get_drvinfo(struct net_device *dev,
1855 struct ethtool_drvinfo *info)
1857 struct rtl8169_private *tp = netdev_priv(dev);
1858 struct rtl_fw *rtl_fw = tp->rtl_fw;
1860 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1861 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1862 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1863 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1864 if (!IS_ERR_OR_NULL(rtl_fw))
1865 strlcpy(info->fw_version, rtl_fw->version,
1866 sizeof(info->fw_version));
1869 static int rtl8169_get_regs_len(struct net_device *dev)
1871 return R8169_REGS_SIZE;
1874 static int rtl8169_set_speed_tbi(struct net_device *dev,
1875 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1877 struct rtl8169_private *tp = netdev_priv(dev);
1878 void __iomem *ioaddr = tp->mmio_addr;
1882 reg = RTL_R32(TBICSR);
1883 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1884 (duplex == DUPLEX_FULL)) {
1885 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1886 } else if (autoneg == AUTONEG_ENABLE)
1887 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1889 netif_warn(tp, link, dev,
1890 "incorrect speed setting refused in TBI mode\n");
1897 static int rtl8169_set_speed_xmii(struct net_device *dev,
1898 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1900 struct rtl8169_private *tp = netdev_priv(dev);
1901 int giga_ctrl, bmcr;
1904 rtl_writephy(tp, 0x1f, 0x0000);
1906 if (autoneg == AUTONEG_ENABLE) {
1909 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1910 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1911 ADVERTISE_100HALF | ADVERTISE_100FULL);
1913 if (adv & ADVERTISED_10baseT_Half)
1914 auto_nego |= ADVERTISE_10HALF;
1915 if (adv & ADVERTISED_10baseT_Full)
1916 auto_nego |= ADVERTISE_10FULL;
1917 if (adv & ADVERTISED_100baseT_Half)
1918 auto_nego |= ADVERTISE_100HALF;
1919 if (adv & ADVERTISED_100baseT_Full)
1920 auto_nego |= ADVERTISE_100FULL;
1922 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1924 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1925 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1927 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1928 if (tp->mii.supports_gmii) {
1929 if (adv & ADVERTISED_1000baseT_Half)
1930 giga_ctrl |= ADVERTISE_1000HALF;
1931 if (adv & ADVERTISED_1000baseT_Full)
1932 giga_ctrl |= ADVERTISE_1000FULL;
1933 } else if (adv & (ADVERTISED_1000baseT_Half |
1934 ADVERTISED_1000baseT_Full)) {
1935 netif_info(tp, link, dev,
1936 "PHY does not support 1000Mbps\n");
1940 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1942 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1943 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1947 if (speed == SPEED_10)
1949 else if (speed == SPEED_100)
1950 bmcr = BMCR_SPEED100;
1954 if (duplex == DUPLEX_FULL)
1955 bmcr |= BMCR_FULLDPLX;
1958 rtl_writephy(tp, MII_BMCR, bmcr);
1960 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1961 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1962 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1963 rtl_writephy(tp, 0x17, 0x2138);
1964 rtl_writephy(tp, 0x0e, 0x0260);
1966 rtl_writephy(tp, 0x17, 0x2108);
1967 rtl_writephy(tp, 0x0e, 0x0000);
1976 static int rtl8169_set_speed(struct net_device *dev,
1977 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1979 struct rtl8169_private *tp = netdev_priv(dev);
1982 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1986 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1987 (advertising & ADVERTISED_1000baseT_Full)) {
1988 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1994 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1996 struct rtl8169_private *tp = netdev_priv(dev);
1999 del_timer_sync(&tp->timer);
2002 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
2003 cmd->duplex, cmd->advertising);
2004 rtl_unlock_work(tp);
2009 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2010 netdev_features_t features)
2012 struct rtl8169_private *tp = netdev_priv(dev);
2014 if (dev->mtu > TD_MSS_MAX)
2015 features &= ~NETIF_F_ALL_TSO;
2017 if (dev->mtu > JUMBO_1K &&
2018 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2019 features &= ~NETIF_F_IP_CSUM;
2024 static void __rtl8169_set_features(struct net_device *dev,
2025 netdev_features_t features)
2027 struct rtl8169_private *tp = netdev_priv(dev);
2028 void __iomem *ioaddr = tp->mmio_addr;
2031 rx_config = RTL_R32(RxConfig);
2032 if (features & NETIF_F_RXALL)
2033 rx_config |= (AcceptErr | AcceptRunt);
2035 rx_config &= ~(AcceptErr | AcceptRunt);
2037 RTL_W32(RxConfig, rx_config);
2039 if (features & NETIF_F_RXCSUM)
2040 tp->cp_cmd |= RxChkSum;
2042 tp->cp_cmd &= ~RxChkSum;
2044 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2045 tp->cp_cmd |= RxVlan;
2047 tp->cp_cmd &= ~RxVlan;
2049 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2051 RTL_W16(CPlusCmd, tp->cp_cmd);
2055 static int rtl8169_set_features(struct net_device *dev,
2056 netdev_features_t features)
2058 struct rtl8169_private *tp = netdev_priv(dev);
2060 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2063 if (features ^ dev->features)
2064 __rtl8169_set_features(dev, features);
2065 rtl_unlock_work(tp);
2071 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2073 return (skb_vlan_tag_present(skb)) ?
2074 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2077 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2079 u32 opts2 = le32_to_cpu(desc->opts2);
2081 if (opts2 & RxVlanTag)
2082 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2085 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
2087 struct rtl8169_private *tp = netdev_priv(dev);
2088 void __iomem *ioaddr = tp->mmio_addr;
2092 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2093 cmd->port = PORT_FIBRE;
2094 cmd->transceiver = XCVR_INTERNAL;
2096 status = RTL_R32(TBICSR);
2097 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2098 cmd->autoneg = !!(status & TBINwEnable);
2100 ethtool_cmd_speed_set(cmd, SPEED_1000);
2101 cmd->duplex = DUPLEX_FULL; /* Always set */
2106 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
2108 struct rtl8169_private *tp = netdev_priv(dev);
2110 return mii_ethtool_gset(&tp->mii, cmd);
2113 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2115 struct rtl8169_private *tp = netdev_priv(dev);
2119 rc = tp->get_settings(dev, cmd);
2120 rtl_unlock_work(tp);
2125 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2128 struct rtl8169_private *tp = netdev_priv(dev);
2129 u32 __iomem *data = tp->mmio_addr;
2134 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2135 memcpy_fromio(dw++, data++, 4);
2136 rtl_unlock_work(tp);
2139 static u32 rtl8169_get_msglevel(struct net_device *dev)
2141 struct rtl8169_private *tp = netdev_priv(dev);
2143 return tp->msg_enable;
2146 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2148 struct rtl8169_private *tp = netdev_priv(dev);
2150 tp->msg_enable = value;
2153 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2160 "tx_single_collisions",
2161 "tx_multi_collisions",
2169 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2173 return ARRAY_SIZE(rtl8169_gstrings);
2179 DECLARE_RTL_COND(rtl_counters_cond)
2181 void __iomem *ioaddr = tp->mmio_addr;
2183 return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
2186 static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
2188 struct rtl8169_private *tp = netdev_priv(dev);
2189 void __iomem *ioaddr = tp->mmio_addr;
2190 dma_addr_t paddr = tp->counters_phys_addr;
2193 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2194 RTL_R32(CounterAddrHigh);
2195 cmd = (u64)paddr & DMA_BIT_MASK(32);
2196 RTL_W32(CounterAddrLow, cmd);
2197 RTL_W32(CounterAddrLow, cmd | counter_cmd);
2199 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2202 static bool rtl8169_reset_counters(struct net_device *dev)
2204 struct rtl8169_private *tp = netdev_priv(dev);
2207 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2210 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2213 return rtl8169_do_counters(dev, CounterReset);
2216 static bool rtl8169_update_counters(struct net_device *dev)
2218 struct rtl8169_private *tp = netdev_priv(dev);
2219 void __iomem *ioaddr = tp->mmio_addr;
2222 * Some chips are unable to dump tally counters when the receiver
2225 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2228 return rtl8169_do_counters(dev, CounterDump);
2231 static bool rtl8169_init_counter_offsets(struct net_device *dev)
2233 struct rtl8169_private *tp = netdev_priv(dev);
2234 struct rtl8169_counters *counters = tp->counters;
2238 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2239 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2240 * reset by a power cycle, while the counter values collected by the
2241 * driver are reset at every driver unload/load cycle.
2243 * To make sure the HW values returned by @get_stats64 match the SW
2244 * values, we collect the initial values at first open(*) and use them
2245 * as offsets to normalize the values returned by @get_stats64.
2247 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2248 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2249 * set at open time by rtl_hw_start.
2252 if (tp->tc_offset.inited)
2255 /* If both, reset and update fail, propagate to caller. */
2256 if (rtl8169_reset_counters(dev))
2259 if (rtl8169_update_counters(dev))
2262 tp->tc_offset.tx_errors = counters->tx_errors;
2263 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2264 tp->tc_offset.tx_aborted = counters->tx_aborted;
2265 tp->tc_offset.inited = true;
2270 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2271 struct ethtool_stats *stats, u64 *data)
2273 struct rtl8169_private *tp = netdev_priv(dev);
2274 struct rtl8169_counters *counters = tp->counters;
2278 rtl8169_update_counters(dev);
2280 data[0] = le64_to_cpu(counters->tx_packets);
2281 data[1] = le64_to_cpu(counters->rx_packets);
2282 data[2] = le64_to_cpu(counters->tx_errors);
2283 data[3] = le32_to_cpu(counters->rx_errors);
2284 data[4] = le16_to_cpu(counters->rx_missed);
2285 data[5] = le16_to_cpu(counters->align_errors);
2286 data[6] = le32_to_cpu(counters->tx_one_collision);
2287 data[7] = le32_to_cpu(counters->tx_multi_collision);
2288 data[8] = le64_to_cpu(counters->rx_unicast);
2289 data[9] = le64_to_cpu(counters->rx_broadcast);
2290 data[10] = le32_to_cpu(counters->rx_multicast);
2291 data[11] = le16_to_cpu(counters->tx_aborted);
2292 data[12] = le16_to_cpu(counters->tx_underun);
2295 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2299 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
2304 static const struct ethtool_ops rtl8169_ethtool_ops = {
2305 .get_drvinfo = rtl8169_get_drvinfo,
2306 .get_regs_len = rtl8169_get_regs_len,
2307 .get_link = ethtool_op_get_link,
2308 .get_settings = rtl8169_get_settings,
2309 .set_settings = rtl8169_set_settings,
2310 .get_msglevel = rtl8169_get_msglevel,
2311 .set_msglevel = rtl8169_set_msglevel,
2312 .get_regs = rtl8169_get_regs,
2313 .get_wol = rtl8169_get_wol,
2314 .set_wol = rtl8169_set_wol,
2315 .get_strings = rtl8169_get_strings,
2316 .get_sset_count = rtl8169_get_sset_count,
2317 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2318 .get_ts_info = ethtool_op_get_ts_info,
2321 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2322 struct net_device *dev, u8 default_version)
2324 void __iomem *ioaddr = tp->mmio_addr;
2326 * The driver currently handles the 8168Bf and the 8168Be identically
2327 * but they can be identified more specifically through the test below
2330 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2332 * Same thing for the 8101Eb and the 8101Ec:
2334 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2336 static const struct rtl_mac_info {
2341 /* 8168EP family. */
2342 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2343 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2344 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2347 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2348 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2351 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2352 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2353 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2354 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2357 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2358 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2359 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2362 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2363 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2364 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2365 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2368 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2369 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2370 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2372 /* 8168DP family. */
2373 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2374 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2375 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2378 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
2379 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2380 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2381 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2382 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2383 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2384 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2385 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
2386 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2389 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2390 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2391 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2392 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2395 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2396 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2397 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2398 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
2399 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2400 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2401 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2402 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2403 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2404 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2405 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2406 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2407 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2408 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2409 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2410 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2411 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2412 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2413 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2414 /* FIXME: where did these entries come from ? -- FR */
2415 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2416 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2419 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2420 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2421 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2422 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2423 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2424 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2427 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2429 const struct rtl_mac_info *p = mac_info;
2432 reg = RTL_R32(TxConfig);
2433 while ((reg & p->mask) != p->val)
2435 tp->mac_version = p->mac_version;
2437 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2438 netif_notice(tp, probe, dev,
2439 "unknown MAC, using family default\n");
2440 tp->mac_version = default_version;
2441 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2442 tp->mac_version = tp->mii.supports_gmii ?
2443 RTL_GIGA_MAC_VER_42 :
2444 RTL_GIGA_MAC_VER_43;
2445 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2446 tp->mac_version = tp->mii.supports_gmii ?
2447 RTL_GIGA_MAC_VER_45 :
2448 RTL_GIGA_MAC_VER_47;
2449 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2450 tp->mac_version = tp->mii.supports_gmii ?
2451 RTL_GIGA_MAC_VER_46 :
2452 RTL_GIGA_MAC_VER_48;
2456 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2458 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2466 static void rtl_writephy_batch(struct rtl8169_private *tp,
2467 const struct phy_reg *regs, int len)
2470 rtl_writephy(tp, regs->reg, regs->val);
2475 #define PHY_READ 0x00000000
2476 #define PHY_DATA_OR 0x10000000
2477 #define PHY_DATA_AND 0x20000000
2478 #define PHY_BJMPN 0x30000000
2479 #define PHY_MDIO_CHG 0x40000000
2480 #define PHY_CLEAR_READCOUNT 0x70000000
2481 #define PHY_WRITE 0x80000000
2482 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2483 #define PHY_COMP_EQ_SKIPN 0xa0000000
2484 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2485 #define PHY_WRITE_PREVIOUS 0xc0000000
2486 #define PHY_SKIPN 0xd0000000
2487 #define PHY_DELAY_MS 0xe0000000
2491 char version[RTL_VER_SIZE];
2497 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2499 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2501 const struct firmware *fw = rtl_fw->fw;
2502 struct fw_info *fw_info = (struct fw_info *)fw->data;
2503 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2504 char *version = rtl_fw->version;
2507 if (fw->size < FW_OPCODE_SIZE)
2510 if (!fw_info->magic) {
2511 size_t i, size, start;
2514 if (fw->size < sizeof(*fw_info))
2517 for (i = 0; i < fw->size; i++)
2518 checksum += fw->data[i];
2522 start = le32_to_cpu(fw_info->fw_start);
2523 if (start > fw->size)
2526 size = le32_to_cpu(fw_info->fw_len);
2527 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2530 memcpy(version, fw_info->version, RTL_VER_SIZE);
2532 pa->code = (__le32 *)(fw->data + start);
2535 if (fw->size % FW_OPCODE_SIZE)
2538 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2540 pa->code = (__le32 *)fw->data;
2541 pa->size = fw->size / FW_OPCODE_SIZE;
2543 version[RTL_VER_SIZE - 1] = 0;
2550 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2551 struct rtl_fw_phy_action *pa)
2556 for (index = 0; index < pa->size; index++) {
2557 u32 action = le32_to_cpu(pa->code[index]);
2558 u32 regno = (action & 0x0fff0000) >> 16;
2560 switch(action & 0xf0000000) {
2565 case PHY_CLEAR_READCOUNT:
2567 case PHY_WRITE_PREVIOUS:
2572 if (regno > index) {
2573 netif_err(tp, ifup, tp->dev,
2574 "Out of range of firmware\n");
2578 case PHY_READCOUNT_EQ_SKIP:
2579 if (index + 2 >= pa->size) {
2580 netif_err(tp, ifup, tp->dev,
2581 "Out of range of firmware\n");
2585 case PHY_COMP_EQ_SKIPN:
2586 case PHY_COMP_NEQ_SKIPN:
2588 if (index + 1 + regno >= pa->size) {
2589 netif_err(tp, ifup, tp->dev,
2590 "Out of range of firmware\n");
2596 netif_err(tp, ifup, tp->dev,
2597 "Invalid action 0x%08x\n", action);
2606 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2608 struct net_device *dev = tp->dev;
2611 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2612 netif_err(tp, ifup, dev, "invalid firmware\n");
2616 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2622 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2624 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2625 struct mdio_ops org, *ops = &tp->mdio_ops;
2629 predata = count = 0;
2630 org.write = ops->write;
2631 org.read = ops->read;
2633 for (index = 0; index < pa->size; ) {
2634 u32 action = le32_to_cpu(pa->code[index]);
2635 u32 data = action & 0x0000ffff;
2636 u32 regno = (action & 0x0fff0000) >> 16;
2641 switch(action & 0xf0000000) {
2643 predata = rtl_readphy(tp, regno);
2660 ops->write = org.write;
2661 ops->read = org.read;
2662 } else if (data == 1) {
2663 ops->write = mac_mcu_write;
2664 ops->read = mac_mcu_read;
2669 case PHY_CLEAR_READCOUNT:
2674 rtl_writephy(tp, regno, data);
2677 case PHY_READCOUNT_EQ_SKIP:
2678 index += (count == data) ? 2 : 1;
2680 case PHY_COMP_EQ_SKIPN:
2681 if (predata == data)
2685 case PHY_COMP_NEQ_SKIPN:
2686 if (predata != data)
2690 case PHY_WRITE_PREVIOUS:
2691 rtl_writephy(tp, regno, predata);
2707 ops->write = org.write;
2708 ops->read = org.read;
2711 static void rtl_release_firmware(struct rtl8169_private *tp)
2713 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2714 release_firmware(tp->rtl_fw->fw);
2717 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2720 static void rtl_apply_firmware(struct rtl8169_private *tp)
2722 struct rtl_fw *rtl_fw = tp->rtl_fw;
2724 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2725 if (!IS_ERR_OR_NULL(rtl_fw))
2726 rtl_phy_write_fw(tp, rtl_fw);
2729 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2731 if (rtl_readphy(tp, reg) != val)
2732 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2734 rtl_apply_firmware(tp);
2737 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2739 static const struct phy_reg phy_reg_init[] = {
2801 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2804 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2806 static const struct phy_reg phy_reg_init[] = {
2812 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2815 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2817 struct pci_dev *pdev = tp->pci_dev;
2819 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2820 (pdev->subsystem_device != 0xe000))
2823 rtl_writephy(tp, 0x1f, 0x0001);
2824 rtl_writephy(tp, 0x10, 0xf01b);
2825 rtl_writephy(tp, 0x1f, 0x0000);
2828 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2830 static const struct phy_reg phy_reg_init[] = {
2870 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2872 rtl8169scd_hw_phy_config_quirk(tp);
2875 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2877 static const struct phy_reg phy_reg_init[] = {
2925 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2928 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2930 static const struct phy_reg phy_reg_init[] = {
2935 rtl_writephy(tp, 0x1f, 0x0001);
2936 rtl_patchphy(tp, 0x16, 1 << 0);
2938 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2941 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2943 static const struct phy_reg phy_reg_init[] = {
2949 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2952 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2954 static const struct phy_reg phy_reg_init[] = {
2962 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2965 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2967 static const struct phy_reg phy_reg_init[] = {
2973 rtl_writephy(tp, 0x1f, 0x0000);
2974 rtl_patchphy(tp, 0x14, 1 << 5);
2975 rtl_patchphy(tp, 0x0d, 1 << 5);
2977 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2980 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2982 static const struct phy_reg phy_reg_init[] = {
3002 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3004 rtl_patchphy(tp, 0x14, 1 << 5);
3005 rtl_patchphy(tp, 0x0d, 1 << 5);
3006 rtl_writephy(tp, 0x1f, 0x0000);
3009 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3011 static const struct phy_reg phy_reg_init[] = {
3029 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3031 rtl_patchphy(tp, 0x16, 1 << 0);
3032 rtl_patchphy(tp, 0x14, 1 << 5);
3033 rtl_patchphy(tp, 0x0d, 1 << 5);
3034 rtl_writephy(tp, 0x1f, 0x0000);
3037 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3039 static const struct phy_reg phy_reg_init[] = {
3051 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3053 rtl_patchphy(tp, 0x16, 1 << 0);
3054 rtl_patchphy(tp, 0x14, 1 << 5);
3055 rtl_patchphy(tp, 0x0d, 1 << 5);
3056 rtl_writephy(tp, 0x1f, 0x0000);
3059 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3061 rtl8168c_3_hw_phy_config(tp);
3064 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3066 static const struct phy_reg phy_reg_init_0[] = {
3067 /* Channel Estimation */
3088 * Enhance line driver power
3097 * Can not link to 1Gbps with bad cable
3098 * Decrease SNR threshold form 21.07dB to 19.04dB
3107 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3111 * Fine Tune Switching regulator parameter
3113 rtl_writephy(tp, 0x1f, 0x0002);
3114 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3115 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3117 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3118 static const struct phy_reg phy_reg_init[] = {
3128 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3130 val = rtl_readphy(tp, 0x0d);
3132 if ((val & 0x00ff) != 0x006c) {
3133 static const u32 set[] = {
3134 0x0065, 0x0066, 0x0067, 0x0068,
3135 0x0069, 0x006a, 0x006b, 0x006c
3139 rtl_writephy(tp, 0x1f, 0x0002);
3142 for (i = 0; i < ARRAY_SIZE(set); i++)
3143 rtl_writephy(tp, 0x0d, val | set[i]);
3146 static const struct phy_reg phy_reg_init[] = {
3154 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3157 /* RSET couple improve */
3158 rtl_writephy(tp, 0x1f, 0x0002);
3159 rtl_patchphy(tp, 0x0d, 0x0300);
3160 rtl_patchphy(tp, 0x0f, 0x0010);
3162 /* Fine tune PLL performance */
3163 rtl_writephy(tp, 0x1f, 0x0002);
3164 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3165 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3167 rtl_writephy(tp, 0x1f, 0x0005);
3168 rtl_writephy(tp, 0x05, 0x001b);
3170 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3172 rtl_writephy(tp, 0x1f, 0x0000);
3175 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3177 static const struct phy_reg phy_reg_init_0[] = {
3178 /* Channel Estimation */
3199 * Enhance line driver power
3208 * Can not link to 1Gbps with bad cable
3209 * Decrease SNR threshold form 21.07dB to 19.04dB
3218 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3220 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3221 static const struct phy_reg phy_reg_init[] = {
3232 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3234 val = rtl_readphy(tp, 0x0d);
3235 if ((val & 0x00ff) != 0x006c) {
3236 static const u32 set[] = {
3237 0x0065, 0x0066, 0x0067, 0x0068,
3238 0x0069, 0x006a, 0x006b, 0x006c
3242 rtl_writephy(tp, 0x1f, 0x0002);
3245 for (i = 0; i < ARRAY_SIZE(set); i++)
3246 rtl_writephy(tp, 0x0d, val | set[i]);
3249 static const struct phy_reg phy_reg_init[] = {
3257 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3260 /* Fine tune PLL performance */
3261 rtl_writephy(tp, 0x1f, 0x0002);
3262 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3263 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3265 /* Switching regulator Slew rate */
3266 rtl_writephy(tp, 0x1f, 0x0002);
3267 rtl_patchphy(tp, 0x0f, 0x0017);
3269 rtl_writephy(tp, 0x1f, 0x0005);
3270 rtl_writephy(tp, 0x05, 0x001b);
3272 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3274 rtl_writephy(tp, 0x1f, 0x0000);
3277 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3279 static const struct phy_reg phy_reg_init[] = {
3335 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3338 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3340 static const struct phy_reg phy_reg_init[] = {
3350 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3351 rtl_patchphy(tp, 0x0d, 1 << 5);
3354 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3356 static const struct phy_reg phy_reg_init[] = {
3357 /* Enable Delay cap */
3363 /* Channel estimation fine tune */
3372 /* Update PFM & 10M TX idle timer */
3384 rtl_apply_firmware(tp);
3386 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3388 /* DCO enable for 10M IDLE Power */
3389 rtl_writephy(tp, 0x1f, 0x0007);
3390 rtl_writephy(tp, 0x1e, 0x0023);
3391 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3392 rtl_writephy(tp, 0x1f, 0x0000);
3394 /* For impedance matching */
3395 rtl_writephy(tp, 0x1f, 0x0002);
3396 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3397 rtl_writephy(tp, 0x1f, 0x0000);
3399 /* PHY auto speed down */
3400 rtl_writephy(tp, 0x1f, 0x0007);
3401 rtl_writephy(tp, 0x1e, 0x002d);
3402 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3403 rtl_writephy(tp, 0x1f, 0x0000);
3404 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3406 rtl_writephy(tp, 0x1f, 0x0005);
3407 rtl_writephy(tp, 0x05, 0x8b86);
3408 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3409 rtl_writephy(tp, 0x1f, 0x0000);
3411 rtl_writephy(tp, 0x1f, 0x0005);
3412 rtl_writephy(tp, 0x05, 0x8b85);
3413 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3414 rtl_writephy(tp, 0x1f, 0x0007);
3415 rtl_writephy(tp, 0x1e, 0x0020);
3416 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3417 rtl_writephy(tp, 0x1f, 0x0006);
3418 rtl_writephy(tp, 0x00, 0x5a00);
3419 rtl_writephy(tp, 0x1f, 0x0000);
3420 rtl_writephy(tp, 0x0d, 0x0007);
3421 rtl_writephy(tp, 0x0e, 0x003c);
3422 rtl_writephy(tp, 0x0d, 0x4007);
3423 rtl_writephy(tp, 0x0e, 0x0000);
3424 rtl_writephy(tp, 0x0d, 0x0000);
3427 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3430 addr[0] | (addr[1] << 8),
3431 addr[2] | (addr[3] << 8),
3432 addr[4] | (addr[5] << 8)
3434 const struct exgmac_reg e[] = {
3435 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3436 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3437 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3438 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3441 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3444 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3446 static const struct phy_reg phy_reg_init[] = {
3447 /* Enable Delay cap */
3456 /* Channel estimation fine tune */
3473 rtl_apply_firmware(tp);
3475 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3477 /* For 4-corner performance improve */
3478 rtl_writephy(tp, 0x1f, 0x0005);
3479 rtl_writephy(tp, 0x05, 0x8b80);
3480 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3481 rtl_writephy(tp, 0x1f, 0x0000);
3483 /* PHY auto speed down */
3484 rtl_writephy(tp, 0x1f, 0x0004);
3485 rtl_writephy(tp, 0x1f, 0x0007);
3486 rtl_writephy(tp, 0x1e, 0x002d);
3487 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3488 rtl_writephy(tp, 0x1f, 0x0002);
3489 rtl_writephy(tp, 0x1f, 0x0000);
3490 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3492 /* improve 10M EEE waveform */
3493 rtl_writephy(tp, 0x1f, 0x0005);
3494 rtl_writephy(tp, 0x05, 0x8b86);
3495 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3496 rtl_writephy(tp, 0x1f, 0x0000);
3498 /* Improve 2-pair detection performance */
3499 rtl_writephy(tp, 0x1f, 0x0005);
3500 rtl_writephy(tp, 0x05, 0x8b85);
3501 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3502 rtl_writephy(tp, 0x1f, 0x0000);
3505 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3506 rtl_writephy(tp, 0x1f, 0x0005);
3507 rtl_writephy(tp, 0x05, 0x8b85);
3508 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3509 rtl_writephy(tp, 0x1f, 0x0004);
3510 rtl_writephy(tp, 0x1f, 0x0007);
3511 rtl_writephy(tp, 0x1e, 0x0020);
3512 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3513 rtl_writephy(tp, 0x1f, 0x0002);
3514 rtl_writephy(tp, 0x1f, 0x0000);
3515 rtl_writephy(tp, 0x0d, 0x0007);
3516 rtl_writephy(tp, 0x0e, 0x003c);
3517 rtl_writephy(tp, 0x0d, 0x4007);
3518 rtl_writephy(tp, 0x0e, 0x0000);
3519 rtl_writephy(tp, 0x0d, 0x0000);
3522 rtl_writephy(tp, 0x1f, 0x0003);
3523 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3524 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3525 rtl_writephy(tp, 0x1f, 0x0000);
3527 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3528 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3531 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3533 /* For 4-corner performance improve */
3534 rtl_writephy(tp, 0x1f, 0x0005);
3535 rtl_writephy(tp, 0x05, 0x8b80);
3536 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3537 rtl_writephy(tp, 0x1f, 0x0000);
3539 /* PHY auto speed down */
3540 rtl_writephy(tp, 0x1f, 0x0007);
3541 rtl_writephy(tp, 0x1e, 0x002d);
3542 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3543 rtl_writephy(tp, 0x1f, 0x0000);
3544 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3546 /* Improve 10M EEE waveform */
3547 rtl_writephy(tp, 0x1f, 0x0005);
3548 rtl_writephy(tp, 0x05, 0x8b86);
3549 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3550 rtl_writephy(tp, 0x1f, 0x0000);
3553 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3555 static const struct phy_reg phy_reg_init[] = {
3556 /* Channel estimation fine tune */
3561 /* Modify green table for giga & fnet */
3578 /* Modify green table for 10M */
3584 /* Disable hiimpedance detection (RTCT) */
3590 rtl_apply_firmware(tp);
3592 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3594 rtl8168f_hw_phy_config(tp);
3596 /* Improve 2-pair detection performance */
3597 rtl_writephy(tp, 0x1f, 0x0005);
3598 rtl_writephy(tp, 0x05, 0x8b85);
3599 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3600 rtl_writephy(tp, 0x1f, 0x0000);
3603 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3605 rtl_apply_firmware(tp);
3607 rtl8168f_hw_phy_config(tp);
3610 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3612 static const struct phy_reg phy_reg_init[] = {
3613 /* Channel estimation fine tune */
3618 /* Modify green table for giga & fnet */
3635 /* Modify green table for 10M */
3641 /* Disable hiimpedance detection (RTCT) */
3648 rtl_apply_firmware(tp);
3650 rtl8168f_hw_phy_config(tp);
3652 /* Improve 2-pair detection performance */
3653 rtl_writephy(tp, 0x1f, 0x0005);
3654 rtl_writephy(tp, 0x05, 0x8b85);
3655 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3656 rtl_writephy(tp, 0x1f, 0x0000);
3658 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3660 /* Modify green table for giga */
3661 rtl_writephy(tp, 0x1f, 0x0005);
3662 rtl_writephy(tp, 0x05, 0x8b54);
3663 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3664 rtl_writephy(tp, 0x05, 0x8b5d);
3665 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3666 rtl_writephy(tp, 0x05, 0x8a7c);
3667 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3668 rtl_writephy(tp, 0x05, 0x8a7f);
3669 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3670 rtl_writephy(tp, 0x05, 0x8a82);
3671 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3672 rtl_writephy(tp, 0x05, 0x8a85);
3673 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3674 rtl_writephy(tp, 0x05, 0x8a88);
3675 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3676 rtl_writephy(tp, 0x1f, 0x0000);
3678 /* uc same-seed solution */
3679 rtl_writephy(tp, 0x1f, 0x0005);
3680 rtl_writephy(tp, 0x05, 0x8b85);
3681 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3682 rtl_writephy(tp, 0x1f, 0x0000);
3685 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3686 rtl_writephy(tp, 0x1f, 0x0005);
3687 rtl_writephy(tp, 0x05, 0x8b85);
3688 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3689 rtl_writephy(tp, 0x1f, 0x0004);
3690 rtl_writephy(tp, 0x1f, 0x0007);
3691 rtl_writephy(tp, 0x1e, 0x0020);
3692 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3693 rtl_writephy(tp, 0x1f, 0x0000);
3694 rtl_writephy(tp, 0x0d, 0x0007);
3695 rtl_writephy(tp, 0x0e, 0x003c);
3696 rtl_writephy(tp, 0x0d, 0x4007);
3697 rtl_writephy(tp, 0x0e, 0x0000);
3698 rtl_writephy(tp, 0x0d, 0x0000);
3701 rtl_writephy(tp, 0x1f, 0x0003);
3702 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3703 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3704 rtl_writephy(tp, 0x1f, 0x0000);
3707 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3709 rtl_apply_firmware(tp);
3711 rtl_writephy(tp, 0x1f, 0x0a46);
3712 if (rtl_readphy(tp, 0x10) & 0x0100) {
3713 rtl_writephy(tp, 0x1f, 0x0bcc);
3714 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3716 rtl_writephy(tp, 0x1f, 0x0bcc);
3717 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3720 rtl_writephy(tp, 0x1f, 0x0a46);
3721 if (rtl_readphy(tp, 0x13) & 0x0100) {
3722 rtl_writephy(tp, 0x1f, 0x0c41);
3723 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3725 rtl_writephy(tp, 0x1f, 0x0c41);
3726 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3729 /* Enable PHY auto speed down */
3730 rtl_writephy(tp, 0x1f, 0x0a44);
3731 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3733 rtl_writephy(tp, 0x1f, 0x0bcc);
3734 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3735 rtl_writephy(tp, 0x1f, 0x0a44);
3736 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3737 rtl_writephy(tp, 0x1f, 0x0a43);
3738 rtl_writephy(tp, 0x13, 0x8084);
3739 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3740 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3742 /* EEE auto-fallback function */
3743 rtl_writephy(tp, 0x1f, 0x0a4b);
3744 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3746 /* Enable UC LPF tune function */
3747 rtl_writephy(tp, 0x1f, 0x0a43);
3748 rtl_writephy(tp, 0x13, 0x8012);
3749 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3751 rtl_writephy(tp, 0x1f, 0x0c42);
3752 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3754 /* Improve SWR Efficiency */
3755 rtl_writephy(tp, 0x1f, 0x0bcd);
3756 rtl_writephy(tp, 0x14, 0x5065);
3757 rtl_writephy(tp, 0x14, 0xd065);
3758 rtl_writephy(tp, 0x1f, 0x0bc8);
3759 rtl_writephy(tp, 0x11, 0x5655);
3760 rtl_writephy(tp, 0x1f, 0x0bcd);
3761 rtl_writephy(tp, 0x14, 0x1065);
3762 rtl_writephy(tp, 0x14, 0x9065);
3763 rtl_writephy(tp, 0x14, 0x1065);
3765 /* Check ALDPS bit, disable it if enabled */
3766 rtl_writephy(tp, 0x1f, 0x0a43);
3767 if (rtl_readphy(tp, 0x10) & 0x0004)
3768 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3770 rtl_writephy(tp, 0x1f, 0x0000);
3773 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3775 rtl_apply_firmware(tp);
3778 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3783 rtl_apply_firmware(tp);
3785 /* CHN EST parameters adjust - giga master */
3786 rtl_writephy(tp, 0x1f, 0x0a43);
3787 rtl_writephy(tp, 0x13, 0x809b);
3788 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3789 rtl_writephy(tp, 0x13, 0x80a2);
3790 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3791 rtl_writephy(tp, 0x13, 0x80a4);
3792 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3793 rtl_writephy(tp, 0x13, 0x809c);
3794 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3795 rtl_writephy(tp, 0x1f, 0x0000);
3797 /* CHN EST parameters adjust - giga slave */
3798 rtl_writephy(tp, 0x1f, 0x0a43);
3799 rtl_writephy(tp, 0x13, 0x80ad);
3800 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3801 rtl_writephy(tp, 0x13, 0x80b4);
3802 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3803 rtl_writephy(tp, 0x13, 0x80ac);
3804 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3805 rtl_writephy(tp, 0x1f, 0x0000);
3807 /* CHN EST parameters adjust - fnet */
3808 rtl_writephy(tp, 0x1f, 0x0a43);
3809 rtl_writephy(tp, 0x13, 0x808e);
3810 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3811 rtl_writephy(tp, 0x13, 0x8090);
3812 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3813 rtl_writephy(tp, 0x13, 0x8092);
3814 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3815 rtl_writephy(tp, 0x1f, 0x0000);
3817 /* enable R-tune & PGA-retune function */
3819 rtl_writephy(tp, 0x1f, 0x0a46);
3820 data = rtl_readphy(tp, 0x13);
3823 dout_tapbin |= data;
3824 data = rtl_readphy(tp, 0x12);
3827 dout_tapbin |= data;
3828 dout_tapbin = ~(dout_tapbin^0x08);
3830 dout_tapbin &= 0xf000;
3831 rtl_writephy(tp, 0x1f, 0x0a43);
3832 rtl_writephy(tp, 0x13, 0x827a);
3833 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3834 rtl_writephy(tp, 0x13, 0x827b);
3835 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3836 rtl_writephy(tp, 0x13, 0x827c);
3837 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3838 rtl_writephy(tp, 0x13, 0x827d);
3839 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3841 rtl_writephy(tp, 0x1f, 0x0a43);
3842 rtl_writephy(tp, 0x13, 0x0811);
3843 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3844 rtl_writephy(tp, 0x1f, 0x0a42);
3845 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3846 rtl_writephy(tp, 0x1f, 0x0000);
3848 /* enable GPHY 10M */
3849 rtl_writephy(tp, 0x1f, 0x0a44);
3850 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3851 rtl_writephy(tp, 0x1f, 0x0000);
3853 /* SAR ADC performance */
3854 rtl_writephy(tp, 0x1f, 0x0bca);
3855 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3856 rtl_writephy(tp, 0x1f, 0x0000);
3858 rtl_writephy(tp, 0x1f, 0x0a43);
3859 rtl_writephy(tp, 0x13, 0x803f);
3860 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3861 rtl_writephy(tp, 0x13, 0x8047);
3862 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3863 rtl_writephy(tp, 0x13, 0x804f);
3864 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3865 rtl_writephy(tp, 0x13, 0x8057);
3866 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3867 rtl_writephy(tp, 0x13, 0x805f);
3868 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3869 rtl_writephy(tp, 0x13, 0x8067);
3870 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3871 rtl_writephy(tp, 0x13, 0x806f);
3872 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3873 rtl_writephy(tp, 0x1f, 0x0000);
3875 /* disable phy pfm mode */
3876 rtl_writephy(tp, 0x1f, 0x0a44);
3877 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3878 rtl_writephy(tp, 0x1f, 0x0000);
3880 /* Check ALDPS bit, disable it if enabled */
3881 rtl_writephy(tp, 0x1f, 0x0a43);
3882 if (rtl_readphy(tp, 0x10) & 0x0004)
3883 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3885 rtl_writephy(tp, 0x1f, 0x0000);
3888 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3890 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3894 rtl_apply_firmware(tp);
3896 /* CHIN EST parameter update */
3897 rtl_writephy(tp, 0x1f, 0x0a43);
3898 rtl_writephy(tp, 0x13, 0x808a);
3899 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3900 rtl_writephy(tp, 0x1f, 0x0000);
3902 /* enable R-tune & PGA-retune function */
3903 rtl_writephy(tp, 0x1f, 0x0a43);
3904 rtl_writephy(tp, 0x13, 0x0811);
3905 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3906 rtl_writephy(tp, 0x1f, 0x0a42);
3907 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3908 rtl_writephy(tp, 0x1f, 0x0000);
3910 /* enable GPHY 10M */
3911 rtl_writephy(tp, 0x1f, 0x0a44);
3912 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3913 rtl_writephy(tp, 0x1f, 0x0000);
3915 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3916 data = r8168_mac_ocp_read(tp, 0xdd02);
3917 ioffset_p3 = ((data & 0x80)>>7);
3920 data = r8168_mac_ocp_read(tp, 0xdd00);
3921 ioffset_p3 |= ((data & (0xe000))>>13);
3922 ioffset_p2 = ((data & (0x1e00))>>9);
3923 ioffset_p1 = ((data & (0x01e0))>>5);
3924 ioffset_p0 = ((data & 0x0010)>>4);
3926 ioffset_p0 |= (data & (0x07));
3927 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3929 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3930 (ioffset_p1 != 0x0f) || (ioffset_p0 == 0x0f)) {
3931 rtl_writephy(tp, 0x1f, 0x0bcf);
3932 rtl_writephy(tp, 0x16, data);
3933 rtl_writephy(tp, 0x1f, 0x0000);
3936 /* Modify rlen (TX LPF corner frequency) level */
3937 rtl_writephy(tp, 0x1f, 0x0bcd);
3938 data = rtl_readphy(tp, 0x16);
3943 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3944 rtl_writephy(tp, 0x17, data);
3945 rtl_writephy(tp, 0x1f, 0x0bcd);
3946 rtl_writephy(tp, 0x1f, 0x0000);
3948 /* disable phy pfm mode */
3949 rtl_writephy(tp, 0x1f, 0x0a44);
3950 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3951 rtl_writephy(tp, 0x1f, 0x0000);
3953 /* Check ALDPS bit, disable it if enabled */
3954 rtl_writephy(tp, 0x1f, 0x0a43);
3955 if (rtl_readphy(tp, 0x10) & 0x0004)
3956 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3958 rtl_writephy(tp, 0x1f, 0x0000);
3961 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3963 /* Enable PHY auto speed down */
3964 rtl_writephy(tp, 0x1f, 0x0a44);
3965 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3966 rtl_writephy(tp, 0x1f, 0x0000);
3968 /* patch 10M & ALDPS */
3969 rtl_writephy(tp, 0x1f, 0x0bcc);
3970 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3971 rtl_writephy(tp, 0x1f, 0x0a44);
3972 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3973 rtl_writephy(tp, 0x1f, 0x0a43);
3974 rtl_writephy(tp, 0x13, 0x8084);
3975 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3976 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3977 rtl_writephy(tp, 0x1f, 0x0000);
3979 /* Enable EEE auto-fallback function */
3980 rtl_writephy(tp, 0x1f, 0x0a4b);
3981 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3982 rtl_writephy(tp, 0x1f, 0x0000);
3984 /* Enable UC LPF tune function */
3985 rtl_writephy(tp, 0x1f, 0x0a43);
3986 rtl_writephy(tp, 0x13, 0x8012);
3987 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3988 rtl_writephy(tp, 0x1f, 0x0000);
3990 /* set rg_sel_sdm_rate */
3991 rtl_writephy(tp, 0x1f, 0x0c42);
3992 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3993 rtl_writephy(tp, 0x1f, 0x0000);
3995 /* Check ALDPS bit, disable it if enabled */
3996 rtl_writephy(tp, 0x1f, 0x0a43);
3997 if (rtl_readphy(tp, 0x10) & 0x0004)
3998 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4000 rtl_writephy(tp, 0x1f, 0x0000);
4003 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4005 /* patch 10M & ALDPS */
4006 rtl_writephy(tp, 0x1f, 0x0bcc);
4007 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4008 rtl_writephy(tp, 0x1f, 0x0a44);
4009 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4010 rtl_writephy(tp, 0x1f, 0x0a43);
4011 rtl_writephy(tp, 0x13, 0x8084);
4012 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4013 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4014 rtl_writephy(tp, 0x1f, 0x0000);
4016 /* Enable UC LPF tune function */
4017 rtl_writephy(tp, 0x1f, 0x0a43);
4018 rtl_writephy(tp, 0x13, 0x8012);
4019 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4020 rtl_writephy(tp, 0x1f, 0x0000);
4022 /* Set rg_sel_sdm_rate */
4023 rtl_writephy(tp, 0x1f, 0x0c42);
4024 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4025 rtl_writephy(tp, 0x1f, 0x0000);
4027 /* Channel estimation parameters */
4028 rtl_writephy(tp, 0x1f, 0x0a43);
4029 rtl_writephy(tp, 0x13, 0x80f3);
4030 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4031 rtl_writephy(tp, 0x13, 0x80f0);
4032 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4033 rtl_writephy(tp, 0x13, 0x80ef);
4034 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4035 rtl_writephy(tp, 0x13, 0x80f6);
4036 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4037 rtl_writephy(tp, 0x13, 0x80ec);
4038 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4039 rtl_writephy(tp, 0x13, 0x80ed);
4040 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4041 rtl_writephy(tp, 0x13, 0x80f2);
4042 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4043 rtl_writephy(tp, 0x13, 0x80f4);
4044 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4045 rtl_writephy(tp, 0x1f, 0x0a43);
4046 rtl_writephy(tp, 0x13, 0x8110);
4047 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4048 rtl_writephy(tp, 0x13, 0x810f);
4049 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4050 rtl_writephy(tp, 0x13, 0x8111);
4051 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4052 rtl_writephy(tp, 0x13, 0x8113);
4053 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4054 rtl_writephy(tp, 0x13, 0x8115);
4055 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4056 rtl_writephy(tp, 0x13, 0x810e);
4057 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4058 rtl_writephy(tp, 0x13, 0x810c);
4059 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4060 rtl_writephy(tp, 0x13, 0x810b);
4061 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4062 rtl_writephy(tp, 0x1f, 0x0a43);
4063 rtl_writephy(tp, 0x13, 0x80d1);
4064 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4065 rtl_writephy(tp, 0x13, 0x80cd);
4066 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4067 rtl_writephy(tp, 0x13, 0x80d3);
4068 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4069 rtl_writephy(tp, 0x13, 0x80d5);
4070 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4071 rtl_writephy(tp, 0x13, 0x80d7);
4072 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4074 /* Force PWM-mode */
4075 rtl_writephy(tp, 0x1f, 0x0bcd);
4076 rtl_writephy(tp, 0x14, 0x5065);
4077 rtl_writephy(tp, 0x14, 0xd065);
4078 rtl_writephy(tp, 0x1f, 0x0bc8);
4079 rtl_writephy(tp, 0x12, 0x00ed);
4080 rtl_writephy(tp, 0x1f, 0x0bcd);
4081 rtl_writephy(tp, 0x14, 0x1065);
4082 rtl_writephy(tp, 0x14, 0x9065);
4083 rtl_writephy(tp, 0x14, 0x1065);
4084 rtl_writephy(tp, 0x1f, 0x0000);
4086 /* Check ALDPS bit, disable it if enabled */
4087 rtl_writephy(tp, 0x1f, 0x0a43);
4088 if (rtl_readphy(tp, 0x10) & 0x0004)
4089 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4091 rtl_writephy(tp, 0x1f, 0x0000);
4094 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4096 static const struct phy_reg phy_reg_init[] = {
4103 rtl_writephy(tp, 0x1f, 0x0000);
4104 rtl_patchphy(tp, 0x11, 1 << 12);
4105 rtl_patchphy(tp, 0x19, 1 << 13);
4106 rtl_patchphy(tp, 0x10, 1 << 15);
4108 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4111 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4113 static const struct phy_reg phy_reg_init[] = {
4127 /* Disable ALDPS before ram code */
4128 rtl_writephy(tp, 0x1f, 0x0000);
4129 rtl_writephy(tp, 0x18, 0x0310);
4132 rtl_apply_firmware(tp);
4134 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4137 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4139 /* Disable ALDPS before setting firmware */
4140 rtl_writephy(tp, 0x1f, 0x0000);
4141 rtl_writephy(tp, 0x18, 0x0310);
4144 rtl_apply_firmware(tp);
4147 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4148 rtl_writephy(tp, 0x1f, 0x0004);
4149 rtl_writephy(tp, 0x10, 0x401f);
4150 rtl_writephy(tp, 0x19, 0x7030);
4151 rtl_writephy(tp, 0x1f, 0x0000);
4154 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4156 static const struct phy_reg phy_reg_init[] = {
4163 /* Disable ALDPS before ram code */
4164 rtl_writephy(tp, 0x1f, 0x0000);
4165 rtl_writephy(tp, 0x18, 0x0310);
4168 rtl_apply_firmware(tp);
4170 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4171 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4173 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4176 static void rtl_hw_phy_config(struct net_device *dev)
4178 struct rtl8169_private *tp = netdev_priv(dev);
4180 rtl8169_print_mac_version(tp);
4182 switch (tp->mac_version) {
4183 case RTL_GIGA_MAC_VER_01:
4185 case RTL_GIGA_MAC_VER_02:
4186 case RTL_GIGA_MAC_VER_03:
4187 rtl8169s_hw_phy_config(tp);
4189 case RTL_GIGA_MAC_VER_04:
4190 rtl8169sb_hw_phy_config(tp);
4192 case RTL_GIGA_MAC_VER_05:
4193 rtl8169scd_hw_phy_config(tp);
4195 case RTL_GIGA_MAC_VER_06:
4196 rtl8169sce_hw_phy_config(tp);
4198 case RTL_GIGA_MAC_VER_07:
4199 case RTL_GIGA_MAC_VER_08:
4200 case RTL_GIGA_MAC_VER_09:
4201 rtl8102e_hw_phy_config(tp);
4203 case RTL_GIGA_MAC_VER_11:
4204 rtl8168bb_hw_phy_config(tp);
4206 case RTL_GIGA_MAC_VER_12:
4207 rtl8168bef_hw_phy_config(tp);
4209 case RTL_GIGA_MAC_VER_17:
4210 rtl8168bef_hw_phy_config(tp);
4212 case RTL_GIGA_MAC_VER_18:
4213 rtl8168cp_1_hw_phy_config(tp);
4215 case RTL_GIGA_MAC_VER_19:
4216 rtl8168c_1_hw_phy_config(tp);
4218 case RTL_GIGA_MAC_VER_20:
4219 rtl8168c_2_hw_phy_config(tp);
4221 case RTL_GIGA_MAC_VER_21:
4222 rtl8168c_3_hw_phy_config(tp);
4224 case RTL_GIGA_MAC_VER_22:
4225 rtl8168c_4_hw_phy_config(tp);
4227 case RTL_GIGA_MAC_VER_23:
4228 case RTL_GIGA_MAC_VER_24:
4229 rtl8168cp_2_hw_phy_config(tp);
4231 case RTL_GIGA_MAC_VER_25:
4232 rtl8168d_1_hw_phy_config(tp);
4234 case RTL_GIGA_MAC_VER_26:
4235 rtl8168d_2_hw_phy_config(tp);
4237 case RTL_GIGA_MAC_VER_27:
4238 rtl8168d_3_hw_phy_config(tp);
4240 case RTL_GIGA_MAC_VER_28:
4241 rtl8168d_4_hw_phy_config(tp);
4243 case RTL_GIGA_MAC_VER_29:
4244 case RTL_GIGA_MAC_VER_30:
4245 rtl8105e_hw_phy_config(tp);
4247 case RTL_GIGA_MAC_VER_31:
4250 case RTL_GIGA_MAC_VER_32:
4251 case RTL_GIGA_MAC_VER_33:
4252 rtl8168e_1_hw_phy_config(tp);
4254 case RTL_GIGA_MAC_VER_34:
4255 rtl8168e_2_hw_phy_config(tp);
4257 case RTL_GIGA_MAC_VER_35:
4258 rtl8168f_1_hw_phy_config(tp);
4260 case RTL_GIGA_MAC_VER_36:
4261 rtl8168f_2_hw_phy_config(tp);
4264 case RTL_GIGA_MAC_VER_37:
4265 rtl8402_hw_phy_config(tp);
4268 case RTL_GIGA_MAC_VER_38:
4269 rtl8411_hw_phy_config(tp);
4272 case RTL_GIGA_MAC_VER_39:
4273 rtl8106e_hw_phy_config(tp);
4276 case RTL_GIGA_MAC_VER_40:
4277 rtl8168g_1_hw_phy_config(tp);
4279 case RTL_GIGA_MAC_VER_42:
4280 case RTL_GIGA_MAC_VER_43:
4281 case RTL_GIGA_MAC_VER_44:
4282 rtl8168g_2_hw_phy_config(tp);
4284 case RTL_GIGA_MAC_VER_45:
4285 case RTL_GIGA_MAC_VER_47:
4286 rtl8168h_1_hw_phy_config(tp);
4288 case RTL_GIGA_MAC_VER_46:
4289 case RTL_GIGA_MAC_VER_48:
4290 rtl8168h_2_hw_phy_config(tp);
4293 case RTL_GIGA_MAC_VER_49:
4294 rtl8168ep_1_hw_phy_config(tp);
4296 case RTL_GIGA_MAC_VER_50:
4297 case RTL_GIGA_MAC_VER_51:
4298 rtl8168ep_2_hw_phy_config(tp);
4301 case RTL_GIGA_MAC_VER_41:
4307 static void rtl_phy_work(struct rtl8169_private *tp)
4309 struct timer_list *timer = &tp->timer;
4310 void __iomem *ioaddr = tp->mmio_addr;
4311 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4313 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4315 if (tp->phy_reset_pending(tp)) {
4317 * A busy loop could burn quite a few cycles on nowadays CPU.
4318 * Let's delay the execution of the timer for a few ticks.
4324 if (tp->link_ok(ioaddr))
4327 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4329 tp->phy_reset_enable(tp);
4332 mod_timer(timer, jiffies + timeout);
4335 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4337 if (!test_and_set_bit(flag, tp->wk.flags))
4338 schedule_work(&tp->wk.work);
4341 static void rtl8169_phy_timer(unsigned long __opaque)
4343 struct net_device *dev = (struct net_device *)__opaque;
4344 struct rtl8169_private *tp = netdev_priv(dev);
4346 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4349 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4350 void __iomem *ioaddr)
4353 pci_release_regions(pdev);
4354 pci_clear_mwi(pdev);
4355 pci_disable_device(pdev);
4359 DECLARE_RTL_COND(rtl_phy_reset_cond)
4361 return tp->phy_reset_pending(tp);
4364 static void rtl8169_phy_reset(struct net_device *dev,
4365 struct rtl8169_private *tp)
4367 tp->phy_reset_enable(tp);
4368 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4371 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4373 void __iomem *ioaddr = tp->mmio_addr;
4375 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4376 (RTL_R8(PHYstatus) & TBI_Enable);
4379 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4381 void __iomem *ioaddr = tp->mmio_addr;
4383 rtl_hw_phy_config(dev);
4385 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4386 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4390 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4392 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4393 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4395 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4396 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4398 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4399 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4402 rtl8169_phy_reset(dev, tp);
4404 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4405 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4406 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4407 (tp->mii.supports_gmii ?
4408 ADVERTISED_1000baseT_Half |
4409 ADVERTISED_1000baseT_Full : 0));
4411 if (rtl_tbi_enabled(tp))
4412 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4415 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4417 void __iomem *ioaddr = tp->mmio_addr;
4421 RTL_W8(Cfg9346, Cfg9346_Unlock);
4423 RTL_W32(MAC4, addr[4] | addr[5] << 8);
4426 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4429 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4430 rtl_rar_exgmac_set(tp, addr);
4432 RTL_W8(Cfg9346, Cfg9346_Lock);
4434 rtl_unlock_work(tp);
4437 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4439 void __iomem *ioaddr = tp->mmio_addr;
4441 switch (tp->mac_version) {
4442 case RTL_GIGA_MAC_VER_01:
4443 case RTL_GIGA_MAC_VER_02:
4444 case RTL_GIGA_MAC_VER_03:
4445 case RTL_GIGA_MAC_VER_04:
4446 case RTL_GIGA_MAC_VER_05:
4447 case RTL_GIGA_MAC_VER_06:
4448 case RTL_GIGA_MAC_VER_10:
4449 case RTL_GIGA_MAC_VER_11:
4450 case RTL_GIGA_MAC_VER_12:
4451 case RTL_GIGA_MAC_VER_13:
4452 case RTL_GIGA_MAC_VER_14:
4453 case RTL_GIGA_MAC_VER_15:
4454 case RTL_GIGA_MAC_VER_16:
4455 case RTL_GIGA_MAC_VER_17:
4456 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4458 case RTL_GIGA_MAC_VER_18:
4459 case RTL_GIGA_MAC_VER_19:
4460 case RTL_GIGA_MAC_VER_20:
4461 case RTL_GIGA_MAC_VER_21:
4462 case RTL_GIGA_MAC_VER_22:
4463 case RTL_GIGA_MAC_VER_23:
4464 case RTL_GIGA_MAC_VER_24:
4465 case RTL_GIGA_MAC_VER_34:
4466 case RTL_GIGA_MAC_VER_35:
4467 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4469 case RTL_GIGA_MAC_VER_40:
4470 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4472 case RTL_GIGA_MAC_VER_41:
4473 case RTL_GIGA_MAC_VER_42:
4474 case RTL_GIGA_MAC_VER_43:
4475 case RTL_GIGA_MAC_VER_44:
4476 case RTL_GIGA_MAC_VER_45:
4477 case RTL_GIGA_MAC_VER_46:
4478 case RTL_GIGA_MAC_VER_47:
4479 case RTL_GIGA_MAC_VER_48:
4480 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4482 case RTL_GIGA_MAC_VER_49:
4483 case RTL_GIGA_MAC_VER_50:
4484 case RTL_GIGA_MAC_VER_51:
4485 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4488 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4493 static int rtl_set_mac_address(struct net_device *dev, void *p)
4495 struct rtl8169_private *tp = netdev_priv(dev);
4496 struct sockaddr *addr = p;
4498 if (!is_valid_ether_addr(addr->sa_data))
4499 return -EADDRNOTAVAIL;
4501 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4503 rtl_rar_set(tp, dev->dev_addr);
4505 /* Reportedly at least Asus X453MA truncates packets otherwise */
4506 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4512 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4514 struct rtl8169_private *tp = netdev_priv(dev);
4515 struct mii_ioctl_data *data = if_mii(ifr);
4517 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4520 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4521 struct mii_ioctl_data *data, int cmd)
4525 data->phy_id = 32; /* Internal PHY */
4529 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4533 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4539 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4544 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4546 if (tp->features & RTL_FEATURE_MSI) {
4547 pci_disable_msi(pdev);
4548 tp->features &= ~RTL_FEATURE_MSI;
4552 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4554 struct mdio_ops *ops = &tp->mdio_ops;
4556 switch (tp->mac_version) {
4557 case RTL_GIGA_MAC_VER_27:
4558 ops->write = r8168dp_1_mdio_write;
4559 ops->read = r8168dp_1_mdio_read;
4561 case RTL_GIGA_MAC_VER_28:
4562 case RTL_GIGA_MAC_VER_31:
4563 ops->write = r8168dp_2_mdio_write;
4564 ops->read = r8168dp_2_mdio_read;
4566 case RTL_GIGA_MAC_VER_40:
4567 case RTL_GIGA_MAC_VER_41:
4568 case RTL_GIGA_MAC_VER_42:
4569 case RTL_GIGA_MAC_VER_43:
4570 case RTL_GIGA_MAC_VER_44:
4571 case RTL_GIGA_MAC_VER_45:
4572 case RTL_GIGA_MAC_VER_46:
4573 case RTL_GIGA_MAC_VER_47:
4574 case RTL_GIGA_MAC_VER_48:
4575 case RTL_GIGA_MAC_VER_49:
4576 case RTL_GIGA_MAC_VER_50:
4577 case RTL_GIGA_MAC_VER_51:
4578 ops->write = r8168g_mdio_write;
4579 ops->read = r8168g_mdio_read;
4582 ops->write = r8169_mdio_write;
4583 ops->read = r8169_mdio_read;
4588 static void rtl_speed_down(struct rtl8169_private *tp)
4593 rtl_writephy(tp, 0x1f, 0x0000);
4594 lpa = rtl_readphy(tp, MII_LPA);
4596 if (lpa & (LPA_10HALF | LPA_10FULL))
4597 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4598 else if (lpa & (LPA_100HALF | LPA_100FULL))
4599 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4600 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4602 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4603 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4604 (tp->mii.supports_gmii ?
4605 ADVERTISED_1000baseT_Half |
4606 ADVERTISED_1000baseT_Full : 0);
4608 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4612 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4614 void __iomem *ioaddr = tp->mmio_addr;
4616 switch (tp->mac_version) {
4617 case RTL_GIGA_MAC_VER_25:
4618 case RTL_GIGA_MAC_VER_26:
4619 case RTL_GIGA_MAC_VER_29:
4620 case RTL_GIGA_MAC_VER_30:
4621 case RTL_GIGA_MAC_VER_32:
4622 case RTL_GIGA_MAC_VER_33:
4623 case RTL_GIGA_MAC_VER_34:
4624 case RTL_GIGA_MAC_VER_37:
4625 case RTL_GIGA_MAC_VER_38:
4626 case RTL_GIGA_MAC_VER_39:
4627 case RTL_GIGA_MAC_VER_40:
4628 case RTL_GIGA_MAC_VER_41:
4629 case RTL_GIGA_MAC_VER_42:
4630 case RTL_GIGA_MAC_VER_43:
4631 case RTL_GIGA_MAC_VER_44:
4632 case RTL_GIGA_MAC_VER_45:
4633 case RTL_GIGA_MAC_VER_46:
4634 case RTL_GIGA_MAC_VER_47:
4635 case RTL_GIGA_MAC_VER_48:
4636 case RTL_GIGA_MAC_VER_49:
4637 case RTL_GIGA_MAC_VER_50:
4638 case RTL_GIGA_MAC_VER_51:
4639 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4640 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4647 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4649 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4653 rtl_wol_suspend_quirk(tp);
4658 static void r810x_phy_power_down(struct rtl8169_private *tp)
4660 rtl_writephy(tp, 0x1f, 0x0000);
4661 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4664 static void r810x_phy_power_up(struct rtl8169_private *tp)
4666 rtl_writephy(tp, 0x1f, 0x0000);
4667 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4670 static void r810x_pll_power_down(struct rtl8169_private *tp)
4672 void __iomem *ioaddr = tp->mmio_addr;
4674 if (rtl_wol_pll_power_down(tp))
4677 r810x_phy_power_down(tp);
4679 switch (tp->mac_version) {
4680 case RTL_GIGA_MAC_VER_07:
4681 case RTL_GIGA_MAC_VER_08:
4682 case RTL_GIGA_MAC_VER_09:
4683 case RTL_GIGA_MAC_VER_10:
4684 case RTL_GIGA_MAC_VER_13:
4685 case RTL_GIGA_MAC_VER_16:
4688 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4693 static void r810x_pll_power_up(struct rtl8169_private *tp)
4695 void __iomem *ioaddr = tp->mmio_addr;
4697 r810x_phy_power_up(tp);
4699 switch (tp->mac_version) {
4700 case RTL_GIGA_MAC_VER_07:
4701 case RTL_GIGA_MAC_VER_08:
4702 case RTL_GIGA_MAC_VER_09:
4703 case RTL_GIGA_MAC_VER_10:
4704 case RTL_GIGA_MAC_VER_13:
4705 case RTL_GIGA_MAC_VER_16:
4707 case RTL_GIGA_MAC_VER_47:
4708 case RTL_GIGA_MAC_VER_48:
4709 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4712 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4717 static void r8168_phy_power_up(struct rtl8169_private *tp)
4719 rtl_writephy(tp, 0x1f, 0x0000);
4720 switch (tp->mac_version) {
4721 case RTL_GIGA_MAC_VER_11:
4722 case RTL_GIGA_MAC_VER_12:
4723 case RTL_GIGA_MAC_VER_17:
4724 case RTL_GIGA_MAC_VER_18:
4725 case RTL_GIGA_MAC_VER_19:
4726 case RTL_GIGA_MAC_VER_20:
4727 case RTL_GIGA_MAC_VER_21:
4728 case RTL_GIGA_MAC_VER_22:
4729 case RTL_GIGA_MAC_VER_23:
4730 case RTL_GIGA_MAC_VER_24:
4731 case RTL_GIGA_MAC_VER_25:
4732 case RTL_GIGA_MAC_VER_26:
4733 case RTL_GIGA_MAC_VER_27:
4734 case RTL_GIGA_MAC_VER_28:
4735 case RTL_GIGA_MAC_VER_31:
4736 rtl_writephy(tp, 0x0e, 0x0000);
4741 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4744 static void r8168_phy_power_down(struct rtl8169_private *tp)
4746 rtl_writephy(tp, 0x1f, 0x0000);
4747 switch (tp->mac_version) {
4748 case RTL_GIGA_MAC_VER_32:
4749 case RTL_GIGA_MAC_VER_33:
4750 case RTL_GIGA_MAC_VER_40:
4751 case RTL_GIGA_MAC_VER_41:
4752 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4755 case RTL_GIGA_MAC_VER_11:
4756 case RTL_GIGA_MAC_VER_12:
4757 case RTL_GIGA_MAC_VER_17:
4758 case RTL_GIGA_MAC_VER_18:
4759 case RTL_GIGA_MAC_VER_19:
4760 case RTL_GIGA_MAC_VER_20:
4761 case RTL_GIGA_MAC_VER_21:
4762 case RTL_GIGA_MAC_VER_22:
4763 case RTL_GIGA_MAC_VER_23:
4764 case RTL_GIGA_MAC_VER_24:
4765 case RTL_GIGA_MAC_VER_25:
4766 case RTL_GIGA_MAC_VER_26:
4767 case RTL_GIGA_MAC_VER_27:
4768 case RTL_GIGA_MAC_VER_28:
4769 case RTL_GIGA_MAC_VER_31:
4770 rtl_writephy(tp, 0x0e, 0x0200);
4772 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4777 static void r8168_pll_power_down(struct rtl8169_private *tp)
4779 void __iomem *ioaddr = tp->mmio_addr;
4781 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4782 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4783 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4784 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4785 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4786 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4787 r8168_check_dash(tp)) {
4791 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4792 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4793 (RTL_R16(CPlusCmd) & ASF)) {
4797 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4798 tp->mac_version == RTL_GIGA_MAC_VER_33)
4799 rtl_ephy_write(tp, 0x19, 0xff64);
4801 if (rtl_wol_pll_power_down(tp))
4804 r8168_phy_power_down(tp);
4806 switch (tp->mac_version) {
4807 case RTL_GIGA_MAC_VER_25:
4808 case RTL_GIGA_MAC_VER_26:
4809 case RTL_GIGA_MAC_VER_27:
4810 case RTL_GIGA_MAC_VER_28:
4811 case RTL_GIGA_MAC_VER_31:
4812 case RTL_GIGA_MAC_VER_32:
4813 case RTL_GIGA_MAC_VER_33:
4814 case RTL_GIGA_MAC_VER_44:
4815 case RTL_GIGA_MAC_VER_45:
4816 case RTL_GIGA_MAC_VER_46:
4817 case RTL_GIGA_MAC_VER_50:
4818 case RTL_GIGA_MAC_VER_51:
4819 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4821 case RTL_GIGA_MAC_VER_40:
4822 case RTL_GIGA_MAC_VER_41:
4823 case RTL_GIGA_MAC_VER_49:
4824 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4825 0xfc000000, ERIAR_EXGMAC);
4826 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4831 static void r8168_pll_power_up(struct rtl8169_private *tp)
4833 void __iomem *ioaddr = tp->mmio_addr;
4835 switch (tp->mac_version) {
4836 case RTL_GIGA_MAC_VER_25:
4837 case RTL_GIGA_MAC_VER_26:
4838 case RTL_GIGA_MAC_VER_27:
4839 case RTL_GIGA_MAC_VER_28:
4840 case RTL_GIGA_MAC_VER_31:
4841 case RTL_GIGA_MAC_VER_32:
4842 case RTL_GIGA_MAC_VER_33:
4843 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4845 case RTL_GIGA_MAC_VER_44:
4846 case RTL_GIGA_MAC_VER_45:
4847 case RTL_GIGA_MAC_VER_46:
4848 case RTL_GIGA_MAC_VER_50:
4849 case RTL_GIGA_MAC_VER_51:
4850 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4852 case RTL_GIGA_MAC_VER_40:
4853 case RTL_GIGA_MAC_VER_41:
4854 case RTL_GIGA_MAC_VER_49:
4855 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4856 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4857 0x00000000, ERIAR_EXGMAC);
4861 r8168_phy_power_up(tp);
4864 static void rtl_generic_op(struct rtl8169_private *tp,
4865 void (*op)(struct rtl8169_private *))
4871 static void rtl_pll_power_down(struct rtl8169_private *tp)
4873 rtl_generic_op(tp, tp->pll_power_ops.down);
4876 static void rtl_pll_power_up(struct rtl8169_private *tp)
4878 rtl_generic_op(tp, tp->pll_power_ops.up);
4880 /* give MAC/PHY some time to resume */
4884 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4886 struct pll_power_ops *ops = &tp->pll_power_ops;
4888 switch (tp->mac_version) {
4889 case RTL_GIGA_MAC_VER_07:
4890 case RTL_GIGA_MAC_VER_08:
4891 case RTL_GIGA_MAC_VER_09:
4892 case RTL_GIGA_MAC_VER_10:
4893 case RTL_GIGA_MAC_VER_16:
4894 case RTL_GIGA_MAC_VER_29:
4895 case RTL_GIGA_MAC_VER_30:
4896 case RTL_GIGA_MAC_VER_37:
4897 case RTL_GIGA_MAC_VER_39:
4898 case RTL_GIGA_MAC_VER_43:
4899 case RTL_GIGA_MAC_VER_47:
4900 case RTL_GIGA_MAC_VER_48:
4901 ops->down = r810x_pll_power_down;
4902 ops->up = r810x_pll_power_up;
4905 case RTL_GIGA_MAC_VER_11:
4906 case RTL_GIGA_MAC_VER_12:
4907 case RTL_GIGA_MAC_VER_17:
4908 case RTL_GIGA_MAC_VER_18:
4909 case RTL_GIGA_MAC_VER_19:
4910 case RTL_GIGA_MAC_VER_20:
4911 case RTL_GIGA_MAC_VER_21:
4912 case RTL_GIGA_MAC_VER_22:
4913 case RTL_GIGA_MAC_VER_23:
4914 case RTL_GIGA_MAC_VER_24:
4915 case RTL_GIGA_MAC_VER_25:
4916 case RTL_GIGA_MAC_VER_26:
4917 case RTL_GIGA_MAC_VER_27:
4918 case RTL_GIGA_MAC_VER_28:
4919 case RTL_GIGA_MAC_VER_31:
4920 case RTL_GIGA_MAC_VER_32:
4921 case RTL_GIGA_MAC_VER_33:
4922 case RTL_GIGA_MAC_VER_34:
4923 case RTL_GIGA_MAC_VER_35:
4924 case RTL_GIGA_MAC_VER_36:
4925 case RTL_GIGA_MAC_VER_38:
4926 case RTL_GIGA_MAC_VER_40:
4927 case RTL_GIGA_MAC_VER_41:
4928 case RTL_GIGA_MAC_VER_42:
4929 case RTL_GIGA_MAC_VER_44:
4930 case RTL_GIGA_MAC_VER_45:
4931 case RTL_GIGA_MAC_VER_46:
4932 case RTL_GIGA_MAC_VER_49:
4933 case RTL_GIGA_MAC_VER_50:
4934 case RTL_GIGA_MAC_VER_51:
4935 ops->down = r8168_pll_power_down;
4936 ops->up = r8168_pll_power_up;
4946 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4948 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4951 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4953 void __iomem *ioaddr = tp->mmio_addr;
4955 RTL_W8(Cfg9346, Cfg9346_Unlock);
4956 rtl_generic_op(tp, tp->jumbo_ops.enable);
4957 RTL_W8(Cfg9346, Cfg9346_Lock);
4960 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4962 void __iomem *ioaddr = tp->mmio_addr;
4964 RTL_W8(Cfg9346, Cfg9346_Unlock);
4965 rtl_generic_op(tp, tp->jumbo_ops.disable);
4966 RTL_W8(Cfg9346, Cfg9346_Lock);
4969 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4971 void __iomem *ioaddr = tp->mmio_addr;
4973 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4974 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4975 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
4978 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4980 void __iomem *ioaddr = tp->mmio_addr;
4982 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4983 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4984 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4987 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4989 void __iomem *ioaddr = tp->mmio_addr;
4991 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4994 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4996 void __iomem *ioaddr = tp->mmio_addr;
4998 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5001 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5003 void __iomem *ioaddr = tp->mmio_addr;
5005 RTL_W8(MaxTxPacketSize, 0x3f);
5006 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5007 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
5008 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5011 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5013 void __iomem *ioaddr = tp->mmio_addr;
5015 RTL_W8(MaxTxPacketSize, 0x0c);
5016 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5017 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
5018 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5021 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5023 rtl_tx_performance_tweak(tp->pci_dev,
5024 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5027 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5029 rtl_tx_performance_tweak(tp->pci_dev,
5030 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5033 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5035 void __iomem *ioaddr = tp->mmio_addr;
5037 r8168b_0_hw_jumbo_enable(tp);
5039 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5042 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5044 void __iomem *ioaddr = tp->mmio_addr;
5046 r8168b_0_hw_jumbo_disable(tp);
5048 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5051 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5053 struct jumbo_ops *ops = &tp->jumbo_ops;
5055 switch (tp->mac_version) {
5056 case RTL_GIGA_MAC_VER_11:
5057 ops->disable = r8168b_0_hw_jumbo_disable;
5058 ops->enable = r8168b_0_hw_jumbo_enable;
5060 case RTL_GIGA_MAC_VER_12:
5061 case RTL_GIGA_MAC_VER_17:
5062 ops->disable = r8168b_1_hw_jumbo_disable;
5063 ops->enable = r8168b_1_hw_jumbo_enable;
5065 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5066 case RTL_GIGA_MAC_VER_19:
5067 case RTL_GIGA_MAC_VER_20:
5068 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5069 case RTL_GIGA_MAC_VER_22:
5070 case RTL_GIGA_MAC_VER_23:
5071 case RTL_GIGA_MAC_VER_24:
5072 case RTL_GIGA_MAC_VER_25:
5073 case RTL_GIGA_MAC_VER_26:
5074 ops->disable = r8168c_hw_jumbo_disable;
5075 ops->enable = r8168c_hw_jumbo_enable;
5077 case RTL_GIGA_MAC_VER_27:
5078 case RTL_GIGA_MAC_VER_28:
5079 ops->disable = r8168dp_hw_jumbo_disable;
5080 ops->enable = r8168dp_hw_jumbo_enable;
5082 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5083 case RTL_GIGA_MAC_VER_32:
5084 case RTL_GIGA_MAC_VER_33:
5085 case RTL_GIGA_MAC_VER_34:
5086 ops->disable = r8168e_hw_jumbo_disable;
5087 ops->enable = r8168e_hw_jumbo_enable;
5091 * No action needed for jumbo frames with 8169.
5092 * No jumbo for 810x at all.
5094 case RTL_GIGA_MAC_VER_40:
5095 case RTL_GIGA_MAC_VER_41:
5096 case RTL_GIGA_MAC_VER_42:
5097 case RTL_GIGA_MAC_VER_43:
5098 case RTL_GIGA_MAC_VER_44:
5099 case RTL_GIGA_MAC_VER_45:
5100 case RTL_GIGA_MAC_VER_46:
5101 case RTL_GIGA_MAC_VER_47:
5102 case RTL_GIGA_MAC_VER_48:
5103 case RTL_GIGA_MAC_VER_49:
5104 case RTL_GIGA_MAC_VER_50:
5105 case RTL_GIGA_MAC_VER_51:
5107 ops->disable = NULL;
5113 DECLARE_RTL_COND(rtl_chipcmd_cond)
5115 void __iomem *ioaddr = tp->mmio_addr;
5117 return RTL_R8(ChipCmd) & CmdReset;
5120 static void rtl_hw_reset(struct rtl8169_private *tp)
5122 void __iomem *ioaddr = tp->mmio_addr;
5124 RTL_W8(ChipCmd, CmdReset);
5126 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5129 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5131 struct rtl_fw *rtl_fw;
5135 name = rtl_lookup_firmware_name(tp);
5137 goto out_no_firmware;
5139 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5143 rc = reject_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5147 rc = rtl_check_firmware(tp, rtl_fw);
5149 goto err_release_firmware;
5151 tp->rtl_fw = rtl_fw;
5155 err_release_firmware:
5156 release_firmware(rtl_fw->fw);
5160 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5167 static void rtl_request_firmware(struct rtl8169_private *tp)
5169 if (IS_ERR(tp->rtl_fw))
5170 rtl_request_uncached_firmware(tp);
5173 static void rtl_rx_close(struct rtl8169_private *tp)
5175 void __iomem *ioaddr = tp->mmio_addr;
5177 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5180 DECLARE_RTL_COND(rtl_npq_cond)
5182 void __iomem *ioaddr = tp->mmio_addr;
5184 return RTL_R8(TxPoll) & NPQ;
5187 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5189 void __iomem *ioaddr = tp->mmio_addr;
5191 return RTL_R32(TxConfig) & TXCFG_EMPTY;
5194 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5196 void __iomem *ioaddr = tp->mmio_addr;
5198 /* Disable interrupts */
5199 rtl8169_irq_mask_and_ack(tp);
5203 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5204 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5205 tp->mac_version == RTL_GIGA_MAC_VER_31) {
5206 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5207 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5208 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5209 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5210 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5211 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5212 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5213 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5214 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5215 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5216 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5217 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5218 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5219 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5220 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5221 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5222 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5223 tp->mac_version == RTL_GIGA_MAC_VER_51) {
5224 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5225 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5227 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5234 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5236 void __iomem *ioaddr = tp->mmio_addr;
5238 /* Set DMA burst size and Interframe Gap Time */
5239 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5240 (InterFrameGap << TxInterFrameGapShift));
5243 static void rtl_hw_start(struct net_device *dev)
5245 struct rtl8169_private *tp = netdev_priv(dev);
5249 rtl_irq_enable_all(tp);
5252 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5253 void __iomem *ioaddr)
5256 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5257 * register to be written before TxDescAddrLow to work.
5258 * Switching from MMIO to I/O access fixes the issue as well.
5260 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5261 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5262 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5263 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5266 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5270 cmd = RTL_R16(CPlusCmd);
5271 RTL_W16(CPlusCmd, cmd);
5275 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5277 /* Low hurts. Let's disable the filtering. */
5278 RTL_W16(RxMaxSize, rx_buf_sz + 1);
5281 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5283 static const struct rtl_cfg2_info {
5288 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5289 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5290 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5291 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5293 const struct rtl_cfg2_info *p = cfg2_info;
5297 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5298 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5299 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5300 RTL_W32(0x7c, p->val);
5306 static void rtl_set_rx_mode(struct net_device *dev)
5308 struct rtl8169_private *tp = netdev_priv(dev);
5309 void __iomem *ioaddr = tp->mmio_addr;
5310 u32 mc_filter[2]; /* Multicast hash filter */
5314 if (dev->flags & IFF_PROMISC) {
5315 /* Unconditionally log net taps. */
5316 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5318 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5320 mc_filter[1] = mc_filter[0] = 0xffffffff;
5321 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5322 (dev->flags & IFF_ALLMULTI)) {
5323 /* Too many to filter perfectly -- accept all multicasts. */
5324 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5325 mc_filter[1] = mc_filter[0] = 0xffffffff;
5327 struct netdev_hw_addr *ha;
5329 rx_mode = AcceptBroadcast | AcceptMyPhys;
5330 mc_filter[1] = mc_filter[0] = 0;
5331 netdev_for_each_mc_addr(ha, dev) {
5332 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5333 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5334 rx_mode |= AcceptMulticast;
5338 if (dev->features & NETIF_F_RXALL)
5339 rx_mode |= (AcceptErr | AcceptRunt);
5341 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5343 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5344 u32 data = mc_filter[0];
5346 mc_filter[0] = swab32(mc_filter[1]);
5347 mc_filter[1] = swab32(data);
5350 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5351 mc_filter[1] = mc_filter[0] = 0xffffffff;
5353 RTL_W32(MAR0 + 4, mc_filter[1]);
5354 RTL_W32(MAR0 + 0, mc_filter[0]);
5356 RTL_W32(RxConfig, tmp);
5359 static void rtl_hw_start_8169(struct net_device *dev)
5361 struct rtl8169_private *tp = netdev_priv(dev);
5362 void __iomem *ioaddr = tp->mmio_addr;
5363 struct pci_dev *pdev = tp->pci_dev;
5365 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5366 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5367 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5370 RTL_W8(Cfg9346, Cfg9346_Unlock);
5371 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5372 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5373 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5374 tp->mac_version == RTL_GIGA_MAC_VER_04)
5375 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5379 RTL_W8(EarlyTxThres, NoEarlyTx);
5381 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5383 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5384 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5385 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5386 tp->mac_version == RTL_GIGA_MAC_VER_04)
5387 rtl_set_rx_tx_config_registers(tp);
5389 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5391 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5392 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5393 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5394 "Bit-3 and bit-14 MUST be 1\n");
5395 tp->cp_cmd |= (1 << 14);
5398 RTL_W16(CPlusCmd, tp->cp_cmd);
5400 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5403 * Undocumented corner. Supposedly:
5404 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5406 RTL_W16(IntrMitigate, 0x0000);
5408 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5410 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5411 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5412 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5413 tp->mac_version != RTL_GIGA_MAC_VER_04) {
5414 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5415 rtl_set_rx_tx_config_registers(tp);
5418 RTL_W8(Cfg9346, Cfg9346_Lock);
5420 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5423 RTL_W32(RxMissed, 0);
5425 rtl_set_rx_mode(dev);
5427 /* no early-rx interrupts */
5428 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5431 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5433 if (tp->csi_ops.write)
5434 tp->csi_ops.write(tp, addr, value);
5437 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5439 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5442 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5446 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5447 rtl_csi_write(tp, 0x070c, csi | bits);
5450 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5452 rtl_csi_access_enable(tp, 0x17000000);
5455 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5457 rtl_csi_access_enable(tp, 0x27000000);
5460 DECLARE_RTL_COND(rtl_csiar_cond)
5462 void __iomem *ioaddr = tp->mmio_addr;
5464 return RTL_R32(CSIAR) & CSIAR_FLAG;
5467 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5469 void __iomem *ioaddr = tp->mmio_addr;
5471 RTL_W32(CSIDR, value);
5472 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5473 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5475 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5478 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5480 void __iomem *ioaddr = tp->mmio_addr;
5482 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5483 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5485 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5486 RTL_R32(CSIDR) : ~0;
5489 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5491 void __iomem *ioaddr = tp->mmio_addr;
5493 RTL_W32(CSIDR, value);
5494 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5495 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5498 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5501 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5503 void __iomem *ioaddr = tp->mmio_addr;
5505 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5506 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5508 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5509 RTL_R32(CSIDR) : ~0;
5512 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5514 void __iomem *ioaddr = tp->mmio_addr;
5516 RTL_W32(CSIDR, value);
5517 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5518 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5521 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5524 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5526 void __iomem *ioaddr = tp->mmio_addr;
5528 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5529 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5531 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5532 RTL_R32(CSIDR) : ~0;
5535 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5537 struct csi_ops *ops = &tp->csi_ops;
5539 switch (tp->mac_version) {
5540 case RTL_GIGA_MAC_VER_01:
5541 case RTL_GIGA_MAC_VER_02:
5542 case RTL_GIGA_MAC_VER_03:
5543 case RTL_GIGA_MAC_VER_04:
5544 case RTL_GIGA_MAC_VER_05:
5545 case RTL_GIGA_MAC_VER_06:
5546 case RTL_GIGA_MAC_VER_10:
5547 case RTL_GIGA_MAC_VER_11:
5548 case RTL_GIGA_MAC_VER_12:
5549 case RTL_GIGA_MAC_VER_13:
5550 case RTL_GIGA_MAC_VER_14:
5551 case RTL_GIGA_MAC_VER_15:
5552 case RTL_GIGA_MAC_VER_16:
5553 case RTL_GIGA_MAC_VER_17:
5558 case RTL_GIGA_MAC_VER_37:
5559 case RTL_GIGA_MAC_VER_38:
5560 ops->write = r8402_csi_write;
5561 ops->read = r8402_csi_read;
5564 case RTL_GIGA_MAC_VER_44:
5565 ops->write = r8411_csi_write;
5566 ops->read = r8411_csi_read;
5570 ops->write = r8169_csi_write;
5571 ops->read = r8169_csi_read;
5577 unsigned int offset;
5582 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5588 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5589 rtl_ephy_write(tp, e->offset, w);
5594 static void rtl_disable_clock_request(struct pci_dev *pdev)
5596 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5597 PCI_EXP_LNKCTL_CLKREQ_EN);
5600 static void rtl_enable_clock_request(struct pci_dev *pdev)
5602 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5603 PCI_EXP_LNKCTL_CLKREQ_EN);
5606 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5608 void __iomem *ioaddr = tp->mmio_addr;
5611 data = RTL_R8(Config3);
5616 data &= ~Rdy_to_L23;
5618 RTL_W8(Config3, data);
5621 #define R8168_CPCMD_QUIRK_MASK (\
5632 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5634 void __iomem *ioaddr = tp->mmio_addr;
5635 struct pci_dev *pdev = tp->pci_dev;
5637 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5639 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5641 if (tp->dev->mtu <= ETH_DATA_LEN) {
5642 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5643 PCI_EXP_DEVCTL_NOSNOOP_EN);
5647 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5649 void __iomem *ioaddr = tp->mmio_addr;
5651 rtl_hw_start_8168bb(tp);
5653 RTL_W8(MaxTxPacketSize, TxPacketMax);
5655 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5658 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5660 void __iomem *ioaddr = tp->mmio_addr;
5661 struct pci_dev *pdev = tp->pci_dev;
5663 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5665 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5667 if (tp->dev->mtu <= ETH_DATA_LEN)
5668 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5670 rtl_disable_clock_request(pdev);
5672 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5675 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5677 static const struct ephy_info e_info_8168cp[] = {
5678 { 0x01, 0, 0x0001 },
5679 { 0x02, 0x0800, 0x1000 },
5680 { 0x03, 0, 0x0042 },
5681 { 0x06, 0x0080, 0x0000 },
5685 rtl_csi_access_enable_2(tp);
5687 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5689 __rtl_hw_start_8168cp(tp);
5692 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5694 void __iomem *ioaddr = tp->mmio_addr;
5695 struct pci_dev *pdev = tp->pci_dev;
5697 rtl_csi_access_enable_2(tp);
5699 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5701 if (tp->dev->mtu <= ETH_DATA_LEN)
5702 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5704 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5707 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5709 void __iomem *ioaddr = tp->mmio_addr;
5710 struct pci_dev *pdev = tp->pci_dev;
5712 rtl_csi_access_enable_2(tp);
5714 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5717 RTL_W8(DBG_REG, 0x20);
5719 RTL_W8(MaxTxPacketSize, TxPacketMax);
5721 if (tp->dev->mtu <= ETH_DATA_LEN)
5722 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5724 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5727 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5729 void __iomem *ioaddr = tp->mmio_addr;
5730 static const struct ephy_info e_info_8168c_1[] = {
5731 { 0x02, 0x0800, 0x1000 },
5732 { 0x03, 0, 0x0002 },
5733 { 0x06, 0x0080, 0x0000 }
5736 rtl_csi_access_enable_2(tp);
5738 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5740 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5742 __rtl_hw_start_8168cp(tp);
5745 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5747 static const struct ephy_info e_info_8168c_2[] = {
5748 { 0x01, 0, 0x0001 },
5749 { 0x03, 0x0400, 0x0220 }
5752 rtl_csi_access_enable_2(tp);
5754 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5756 __rtl_hw_start_8168cp(tp);
5759 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5761 rtl_hw_start_8168c_2(tp);
5764 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5766 rtl_csi_access_enable_2(tp);
5768 __rtl_hw_start_8168cp(tp);
5771 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5773 void __iomem *ioaddr = tp->mmio_addr;
5774 struct pci_dev *pdev = tp->pci_dev;
5776 rtl_csi_access_enable_2(tp);
5778 rtl_disable_clock_request(pdev);
5780 RTL_W8(MaxTxPacketSize, TxPacketMax);
5782 if (tp->dev->mtu <= ETH_DATA_LEN)
5783 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5785 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5788 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5790 void __iomem *ioaddr = tp->mmio_addr;
5791 struct pci_dev *pdev = tp->pci_dev;
5793 rtl_csi_access_enable_1(tp);
5795 if (tp->dev->mtu <= ETH_DATA_LEN)
5796 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5798 RTL_W8(MaxTxPacketSize, TxPacketMax);
5800 rtl_disable_clock_request(pdev);
5803 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5805 void __iomem *ioaddr = tp->mmio_addr;
5806 struct pci_dev *pdev = tp->pci_dev;
5807 static const struct ephy_info e_info_8168d_4[] = {
5809 { 0x19, 0x20, 0x50 },
5814 rtl_csi_access_enable_1(tp);
5816 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5818 RTL_W8(MaxTxPacketSize, TxPacketMax);
5820 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5821 const struct ephy_info *e = e_info_8168d_4 + i;
5824 w = rtl_ephy_read(tp, e->offset);
5825 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5828 rtl_enable_clock_request(pdev);
5831 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5833 void __iomem *ioaddr = tp->mmio_addr;
5834 struct pci_dev *pdev = tp->pci_dev;
5835 static const struct ephy_info e_info_8168e_1[] = {
5836 { 0x00, 0x0200, 0x0100 },
5837 { 0x00, 0x0000, 0x0004 },
5838 { 0x06, 0x0002, 0x0001 },
5839 { 0x06, 0x0000, 0x0030 },
5840 { 0x07, 0x0000, 0x2000 },
5841 { 0x00, 0x0000, 0x0020 },
5842 { 0x03, 0x5800, 0x2000 },
5843 { 0x03, 0x0000, 0x0001 },
5844 { 0x01, 0x0800, 0x1000 },
5845 { 0x07, 0x0000, 0x4000 },
5846 { 0x1e, 0x0000, 0x2000 },
5847 { 0x19, 0xffff, 0xfe6c },
5848 { 0x0a, 0x0000, 0x0040 }
5851 rtl_csi_access_enable_2(tp);
5853 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5855 if (tp->dev->mtu <= ETH_DATA_LEN)
5856 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5858 RTL_W8(MaxTxPacketSize, TxPacketMax);
5860 rtl_disable_clock_request(pdev);
5862 /* Reset tx FIFO pointer */
5863 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5864 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5866 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5869 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5871 void __iomem *ioaddr = tp->mmio_addr;
5872 struct pci_dev *pdev = tp->pci_dev;
5873 static const struct ephy_info e_info_8168e_2[] = {
5874 { 0x09, 0x0000, 0x0080 },
5875 { 0x19, 0x0000, 0x0224 }
5878 rtl_csi_access_enable_1(tp);
5880 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5882 if (tp->dev->mtu <= ETH_DATA_LEN)
5883 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5885 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5886 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5887 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5888 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5889 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5890 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5891 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5892 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5894 RTL_W8(MaxTxPacketSize, EarlySize);
5896 rtl_disable_clock_request(pdev);
5898 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5899 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5901 /* Adjust EEE LED frequency */
5902 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5904 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5905 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5906 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5909 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5911 void __iomem *ioaddr = tp->mmio_addr;
5912 struct pci_dev *pdev = tp->pci_dev;
5914 rtl_csi_access_enable_2(tp);
5916 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5918 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5919 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5920 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5921 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5922 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5923 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5924 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5925 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5926 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5927 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5929 RTL_W8(MaxTxPacketSize, EarlySize);
5931 rtl_disable_clock_request(pdev);
5933 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5934 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5935 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5936 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5937 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5940 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5942 void __iomem *ioaddr = tp->mmio_addr;
5943 static const struct ephy_info e_info_8168f_1[] = {
5944 { 0x06, 0x00c0, 0x0020 },
5945 { 0x08, 0x0001, 0x0002 },
5946 { 0x09, 0x0000, 0x0080 },
5947 { 0x19, 0x0000, 0x0224 }
5950 rtl_hw_start_8168f(tp);
5952 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5954 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5956 /* Adjust EEE LED frequency */
5957 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5960 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5962 static const struct ephy_info e_info_8168f_1[] = {
5963 { 0x06, 0x00c0, 0x0020 },
5964 { 0x0f, 0xffff, 0x5200 },
5965 { 0x1e, 0x0000, 0x4000 },
5966 { 0x19, 0x0000, 0x0224 }
5969 rtl_hw_start_8168f(tp);
5970 rtl_pcie_state_l2l3_enable(tp, false);
5972 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5974 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5977 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5979 void __iomem *ioaddr = tp->mmio_addr;
5980 struct pci_dev *pdev = tp->pci_dev;
5982 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5984 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5985 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5986 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5987 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5989 rtl_csi_access_enable_1(tp);
5991 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5993 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5994 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5995 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5997 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5998 RTL_W8(MaxTxPacketSize, EarlySize);
6000 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6001 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6003 /* Adjust EEE LED frequency */
6004 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6006 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6007 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6009 rtl_pcie_state_l2l3_enable(tp, false);
6012 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6014 void __iomem *ioaddr = tp->mmio_addr;
6015 static const struct ephy_info e_info_8168g_1[] = {
6016 { 0x00, 0x0000, 0x0008 },
6017 { 0x0c, 0x37d0, 0x0820 },
6018 { 0x1e, 0x0000, 0x0001 },
6019 { 0x19, 0x8000, 0x0000 }
6022 rtl_hw_start_8168g(tp);
6024 /* disable aspm and clock request before access ephy */
6025 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6026 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6027 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6030 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6032 void __iomem *ioaddr = tp->mmio_addr;
6033 static const struct ephy_info e_info_8168g_2[] = {
6034 { 0x00, 0x0000, 0x0008 },
6035 { 0x0c, 0x3df0, 0x0200 },
6036 { 0x19, 0xffff, 0xfc00 },
6037 { 0x1e, 0xffff, 0x20eb }
6040 rtl_hw_start_8168g(tp);
6042 /* disable aspm and clock request before access ephy */
6043 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6044 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6045 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6048 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6050 void __iomem *ioaddr = tp->mmio_addr;
6051 static const struct ephy_info e_info_8411_2[] = {
6052 { 0x00, 0x0000, 0x0008 },
6053 { 0x0c, 0x3df0, 0x0200 },
6054 { 0x0f, 0xffff, 0x5200 },
6055 { 0x19, 0x0020, 0x0000 },
6056 { 0x1e, 0x0000, 0x2000 }
6059 rtl_hw_start_8168g(tp);
6061 /* disable aspm and clock request before access ephy */
6062 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6063 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6064 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6067 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6069 void __iomem *ioaddr = tp->mmio_addr;
6070 struct pci_dev *pdev = tp->pci_dev;
6073 static const struct ephy_info e_info_8168h_1[] = {
6074 { 0x1e, 0x0800, 0x0001 },
6075 { 0x1d, 0x0000, 0x0800 },
6076 { 0x05, 0xffff, 0x2089 },
6077 { 0x06, 0xffff, 0x5881 },
6078 { 0x04, 0xffff, 0x154a },
6079 { 0x01, 0xffff, 0x068b }
6082 /* disable aspm and clock request before access ephy */
6083 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6084 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6085 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6087 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6089 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6090 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6091 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6092 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6094 rtl_csi_access_enable_1(tp);
6096 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6098 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6099 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6101 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6103 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6105 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6107 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6108 RTL_W8(MaxTxPacketSize, EarlySize);
6110 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6111 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6113 /* Adjust EEE LED frequency */
6114 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6116 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6117 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6119 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6121 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6123 rtl_pcie_state_l2l3_enable(tp, false);
6125 rtl_writephy(tp, 0x1f, 0x0c42);
6126 rg_saw_cnt = rtl_readphy(tp, 0x13);
6127 rtl_writephy(tp, 0x1f, 0x0000);
6128 if (rg_saw_cnt > 0) {
6131 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6132 sw_cnt_1ms_ini &= 0x0fff;
6133 data = r8168_mac_ocp_read(tp, 0xd412);
6135 data |= sw_cnt_1ms_ini;
6136 r8168_mac_ocp_write(tp, 0xd412, data);
6139 data = r8168_mac_ocp_read(tp, 0xe056);
6142 r8168_mac_ocp_write(tp, 0xe056, data);
6144 data = r8168_mac_ocp_read(tp, 0xe052);
6147 r8168_mac_ocp_write(tp, 0xe052, data);
6149 data = r8168_mac_ocp_read(tp, 0xe0d6);
6152 r8168_mac_ocp_write(tp, 0xe0d6, data);
6154 data = r8168_mac_ocp_read(tp, 0xd420);
6157 r8168_mac_ocp_write(tp, 0xd420, data);
6159 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6160 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6161 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6162 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6165 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6167 void __iomem *ioaddr = tp->mmio_addr;
6168 struct pci_dev *pdev = tp->pci_dev;
6170 rtl8168ep_stop_cmac(tp);
6172 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6174 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6175 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6176 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6177 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6179 rtl_csi_access_enable_1(tp);
6181 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6183 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6184 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6186 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6188 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6190 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6191 RTL_W8(MaxTxPacketSize, EarlySize);
6193 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6194 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6196 /* Adjust EEE LED frequency */
6197 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6199 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6201 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6203 rtl_pcie_state_l2l3_enable(tp, false);
6206 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6208 void __iomem *ioaddr = tp->mmio_addr;
6209 static const struct ephy_info e_info_8168ep_1[] = {
6210 { 0x00, 0xffff, 0x10ab },
6211 { 0x06, 0xffff, 0xf030 },
6212 { 0x08, 0xffff, 0x2006 },
6213 { 0x0d, 0xffff, 0x1666 },
6214 { 0x0c, 0x3ff0, 0x0000 }
6217 /* disable aspm and clock request before access ephy */
6218 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6219 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6220 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6222 rtl_hw_start_8168ep(tp);
6225 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6227 void __iomem *ioaddr = tp->mmio_addr;
6228 static const struct ephy_info e_info_8168ep_2[] = {
6229 { 0x00, 0xffff, 0x10a3 },
6230 { 0x19, 0xffff, 0xfc00 },
6231 { 0x1e, 0xffff, 0x20ea }
6234 /* disable aspm and clock request before access ephy */
6235 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6236 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6237 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6239 rtl_hw_start_8168ep(tp);
6241 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6242 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6245 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6247 void __iomem *ioaddr = tp->mmio_addr;
6249 static const struct ephy_info e_info_8168ep_3[] = {
6250 { 0x00, 0xffff, 0x10a3 },
6251 { 0x19, 0xffff, 0x7c00 },
6252 { 0x1e, 0xffff, 0x20eb },
6253 { 0x0d, 0xffff, 0x1666 }
6256 /* disable aspm and clock request before access ephy */
6257 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6258 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6259 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6261 rtl_hw_start_8168ep(tp);
6263 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6264 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6266 data = r8168_mac_ocp_read(tp, 0xd3e2);
6269 r8168_mac_ocp_write(tp, 0xd3e2, data);
6271 data = r8168_mac_ocp_read(tp, 0xd3e4);
6273 r8168_mac_ocp_write(tp, 0xd3e4, data);
6275 data = r8168_mac_ocp_read(tp, 0xe860);
6277 r8168_mac_ocp_write(tp, 0xe860, data);
6280 static void rtl_hw_start_8168(struct net_device *dev)
6282 struct rtl8169_private *tp = netdev_priv(dev);
6283 void __iomem *ioaddr = tp->mmio_addr;
6285 RTL_W8(Cfg9346, Cfg9346_Unlock);
6287 RTL_W8(MaxTxPacketSize, TxPacketMax);
6289 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6291 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6293 RTL_W16(CPlusCmd, tp->cp_cmd);
6295 RTL_W16(IntrMitigate, 0x5151);
6297 /* Work around for RxFIFO overflow. */
6298 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6299 tp->event_slow |= RxFIFOOver | PCSTimeout;
6300 tp->event_slow &= ~RxOverflow;
6303 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6305 rtl_set_rx_tx_config_registers(tp);
6309 switch (tp->mac_version) {
6310 case RTL_GIGA_MAC_VER_11:
6311 rtl_hw_start_8168bb(tp);
6314 case RTL_GIGA_MAC_VER_12:
6315 case RTL_GIGA_MAC_VER_17:
6316 rtl_hw_start_8168bef(tp);
6319 case RTL_GIGA_MAC_VER_18:
6320 rtl_hw_start_8168cp_1(tp);
6323 case RTL_GIGA_MAC_VER_19:
6324 rtl_hw_start_8168c_1(tp);
6327 case RTL_GIGA_MAC_VER_20:
6328 rtl_hw_start_8168c_2(tp);
6331 case RTL_GIGA_MAC_VER_21:
6332 rtl_hw_start_8168c_3(tp);
6335 case RTL_GIGA_MAC_VER_22:
6336 rtl_hw_start_8168c_4(tp);
6339 case RTL_GIGA_MAC_VER_23:
6340 rtl_hw_start_8168cp_2(tp);
6343 case RTL_GIGA_MAC_VER_24:
6344 rtl_hw_start_8168cp_3(tp);
6347 case RTL_GIGA_MAC_VER_25:
6348 case RTL_GIGA_MAC_VER_26:
6349 case RTL_GIGA_MAC_VER_27:
6350 rtl_hw_start_8168d(tp);
6353 case RTL_GIGA_MAC_VER_28:
6354 rtl_hw_start_8168d_4(tp);
6357 case RTL_GIGA_MAC_VER_31:
6358 rtl_hw_start_8168dp(tp);
6361 case RTL_GIGA_MAC_VER_32:
6362 case RTL_GIGA_MAC_VER_33:
6363 rtl_hw_start_8168e_1(tp);
6365 case RTL_GIGA_MAC_VER_34:
6366 rtl_hw_start_8168e_2(tp);
6369 case RTL_GIGA_MAC_VER_35:
6370 case RTL_GIGA_MAC_VER_36:
6371 rtl_hw_start_8168f_1(tp);
6374 case RTL_GIGA_MAC_VER_38:
6375 rtl_hw_start_8411(tp);
6378 case RTL_GIGA_MAC_VER_40:
6379 case RTL_GIGA_MAC_VER_41:
6380 rtl_hw_start_8168g_1(tp);
6382 case RTL_GIGA_MAC_VER_42:
6383 rtl_hw_start_8168g_2(tp);
6386 case RTL_GIGA_MAC_VER_44:
6387 rtl_hw_start_8411_2(tp);
6390 case RTL_GIGA_MAC_VER_45:
6391 case RTL_GIGA_MAC_VER_46:
6392 rtl_hw_start_8168h_1(tp);
6395 case RTL_GIGA_MAC_VER_49:
6396 rtl_hw_start_8168ep_1(tp);
6399 case RTL_GIGA_MAC_VER_50:
6400 rtl_hw_start_8168ep_2(tp);
6403 case RTL_GIGA_MAC_VER_51:
6404 rtl_hw_start_8168ep_3(tp);
6408 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6409 dev->name, tp->mac_version);
6413 RTL_W8(Cfg9346, Cfg9346_Lock);
6415 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6417 rtl_set_rx_mode(dev);
6419 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6422 #define R810X_CPCMD_QUIRK_MASK (\
6433 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6435 void __iomem *ioaddr = tp->mmio_addr;
6436 struct pci_dev *pdev = tp->pci_dev;
6437 static const struct ephy_info e_info_8102e_1[] = {
6438 { 0x01, 0, 0x6e65 },
6439 { 0x02, 0, 0x091f },
6440 { 0x03, 0, 0xc2f9 },
6441 { 0x06, 0, 0xafb5 },
6442 { 0x07, 0, 0x0e00 },
6443 { 0x19, 0, 0xec80 },
6444 { 0x01, 0, 0x2e65 },
6449 rtl_csi_access_enable_2(tp);
6451 RTL_W8(DBG_REG, FIX_NAK_1);
6453 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6456 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6457 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6459 cfg1 = RTL_R8(Config1);
6460 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6461 RTL_W8(Config1, cfg1 & ~LEDS0);
6463 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6466 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6468 void __iomem *ioaddr = tp->mmio_addr;
6469 struct pci_dev *pdev = tp->pci_dev;
6471 rtl_csi_access_enable_2(tp);
6473 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6475 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6476 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6479 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6481 rtl_hw_start_8102e_2(tp);
6483 rtl_ephy_write(tp, 0x03, 0xc2f9);
6486 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6488 void __iomem *ioaddr = tp->mmio_addr;
6489 static const struct ephy_info e_info_8105e_1[] = {
6490 { 0x07, 0, 0x4000 },
6491 { 0x19, 0, 0x0200 },
6492 { 0x19, 0, 0x0020 },
6493 { 0x1e, 0, 0x2000 },
6494 { 0x03, 0, 0x0001 },
6495 { 0x19, 0, 0x0100 },
6496 { 0x19, 0, 0x0004 },
6500 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6501 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6503 /* Disable Early Tally Counter */
6504 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6506 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6507 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6509 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6511 rtl_pcie_state_l2l3_enable(tp, false);
6514 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6516 rtl_hw_start_8105e_1(tp);
6517 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6520 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6522 void __iomem *ioaddr = tp->mmio_addr;
6523 static const struct ephy_info e_info_8402[] = {
6524 { 0x19, 0xffff, 0xff64 },
6528 rtl_csi_access_enable_2(tp);
6530 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6531 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6533 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6534 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6536 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6538 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6540 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6541 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6542 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6543 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6544 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6545 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6546 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6548 rtl_pcie_state_l2l3_enable(tp, false);
6551 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6553 void __iomem *ioaddr = tp->mmio_addr;
6555 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6556 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6558 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6559 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6560 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6562 rtl_pcie_state_l2l3_enable(tp, false);
6565 static void rtl_hw_start_8101(struct net_device *dev)
6567 struct rtl8169_private *tp = netdev_priv(dev);
6568 void __iomem *ioaddr = tp->mmio_addr;
6569 struct pci_dev *pdev = tp->pci_dev;
6571 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6572 tp->event_slow &= ~RxFIFOOver;
6574 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6575 tp->mac_version == RTL_GIGA_MAC_VER_16)
6576 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6577 PCI_EXP_DEVCTL_NOSNOOP_EN);
6579 RTL_W8(Cfg9346, Cfg9346_Unlock);
6581 RTL_W8(MaxTxPacketSize, TxPacketMax);
6583 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6585 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6586 RTL_W16(CPlusCmd, tp->cp_cmd);
6588 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6590 rtl_set_rx_tx_config_registers(tp);
6592 switch (tp->mac_version) {
6593 case RTL_GIGA_MAC_VER_07:
6594 rtl_hw_start_8102e_1(tp);
6597 case RTL_GIGA_MAC_VER_08:
6598 rtl_hw_start_8102e_3(tp);
6601 case RTL_GIGA_MAC_VER_09:
6602 rtl_hw_start_8102e_2(tp);
6605 case RTL_GIGA_MAC_VER_29:
6606 rtl_hw_start_8105e_1(tp);
6608 case RTL_GIGA_MAC_VER_30:
6609 rtl_hw_start_8105e_2(tp);
6612 case RTL_GIGA_MAC_VER_37:
6613 rtl_hw_start_8402(tp);
6616 case RTL_GIGA_MAC_VER_39:
6617 rtl_hw_start_8106(tp);
6619 case RTL_GIGA_MAC_VER_43:
6620 rtl_hw_start_8168g_2(tp);
6622 case RTL_GIGA_MAC_VER_47:
6623 case RTL_GIGA_MAC_VER_48:
6624 rtl_hw_start_8168h_1(tp);
6628 RTL_W8(Cfg9346, Cfg9346_Lock);
6630 RTL_W16(IntrMitigate, 0x0000);
6632 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6634 rtl_set_rx_mode(dev);
6638 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6641 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6643 struct rtl8169_private *tp = netdev_priv(dev);
6645 if (new_mtu < ETH_ZLEN ||
6646 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
6649 if (new_mtu > ETH_DATA_LEN)
6650 rtl_hw_jumbo_enable(tp);
6652 rtl_hw_jumbo_disable(tp);
6655 netdev_update_features(dev);
6660 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6662 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6663 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6666 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6667 void **data_buff, struct RxDesc *desc)
6669 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6674 rtl8169_make_unusable_by_asic(desc);
6677 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6679 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6681 /* Force memory writes to complete before releasing descriptor */
6684 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6687 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6690 desc->addr = cpu_to_le64(mapping);
6691 rtl8169_mark_to_asic(desc, rx_buf_sz);
6694 static inline void *rtl8169_align(void *data)
6696 return (void *)ALIGN((long)data, 16);
6699 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6700 struct RxDesc *desc)
6704 struct device *d = &tp->pci_dev->dev;
6705 struct net_device *dev = tp->dev;
6706 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6708 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6712 if (rtl8169_align(data) != data) {
6714 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6719 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6721 if (unlikely(dma_mapping_error(d, mapping))) {
6722 if (net_ratelimit())
6723 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6727 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6735 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6739 for (i = 0; i < NUM_RX_DESC; i++) {
6740 if (tp->Rx_databuff[i]) {
6741 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6742 tp->RxDescArray + i);
6747 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6749 desc->opts1 |= cpu_to_le32(RingEnd);
6752 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6756 for (i = 0; i < NUM_RX_DESC; i++) {
6759 if (tp->Rx_databuff[i])
6762 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6764 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6767 tp->Rx_databuff[i] = data;
6770 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6774 rtl8169_rx_clear(tp);
6778 static int rtl8169_init_ring(struct net_device *dev)
6780 struct rtl8169_private *tp = netdev_priv(dev);
6782 rtl8169_init_ring_indexes(tp);
6784 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6785 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6787 return rtl8169_rx_fill(tp);
6790 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6791 struct TxDesc *desc)
6793 unsigned int len = tx_skb->len;
6795 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6803 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6808 for (i = 0; i < n; i++) {
6809 unsigned int entry = (start + i) % NUM_TX_DESC;
6810 struct ring_info *tx_skb = tp->tx_skb + entry;
6811 unsigned int len = tx_skb->len;
6814 struct sk_buff *skb = tx_skb->skb;
6816 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6817 tp->TxDescArray + entry);
6819 tp->dev->stats.tx_dropped++;
6820 dev_kfree_skb_any(skb);
6827 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6829 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6830 tp->cur_tx = tp->dirty_tx = 0;
6833 static void rtl_reset_work(struct rtl8169_private *tp)
6835 struct net_device *dev = tp->dev;
6838 napi_disable(&tp->napi);
6839 netif_stop_queue(dev);
6840 synchronize_sched();
6842 rtl8169_hw_reset(tp);
6844 for (i = 0; i < NUM_RX_DESC; i++)
6845 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6847 rtl8169_tx_clear(tp);
6848 rtl8169_init_ring_indexes(tp);
6850 napi_enable(&tp->napi);
6852 netif_wake_queue(dev);
6853 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6856 static void rtl8169_tx_timeout(struct net_device *dev)
6858 struct rtl8169_private *tp = netdev_priv(dev);
6860 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6863 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6866 struct skb_shared_info *info = skb_shinfo(skb);
6867 unsigned int cur_frag, entry;
6868 struct TxDesc *uninitialized_var(txd);
6869 struct device *d = &tp->pci_dev->dev;
6872 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6873 const skb_frag_t *frag = info->frags + cur_frag;
6878 entry = (entry + 1) % NUM_TX_DESC;
6880 txd = tp->TxDescArray + entry;
6881 len = skb_frag_size(frag);
6882 addr = skb_frag_address(frag);
6883 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6884 if (unlikely(dma_mapping_error(d, mapping))) {
6885 if (net_ratelimit())
6886 netif_err(tp, drv, tp->dev,
6887 "Failed to map TX fragments DMA!\n");
6891 /* Anti gcc 2.95.3 bugware (sic) */
6892 status = opts[0] | len |
6893 (RingEnd * !((entry + 1) % NUM_TX_DESC));
6895 txd->opts1 = cpu_to_le32(status);
6896 txd->opts2 = cpu_to_le32(opts[1]);
6897 txd->addr = cpu_to_le64(mapping);
6899 tp->tx_skb[entry].len = len;
6903 tp->tx_skb[entry].skb = skb;
6904 txd->opts1 |= cpu_to_le32(LastFrag);
6910 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6914 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6916 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6919 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6920 struct net_device *dev);
6921 /* r8169_csum_workaround()
6922 * The hw limites the value the transport offset. When the offset is out of the
6923 * range, calculate the checksum by sw.
6925 static void r8169_csum_workaround(struct rtl8169_private *tp,
6926 struct sk_buff *skb)
6928 if (skb_shinfo(skb)->gso_size) {
6929 netdev_features_t features = tp->dev->features;
6930 struct sk_buff *segs, *nskb;
6932 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6933 segs = skb_gso_segment(skb, features);
6934 if (IS_ERR(segs) || !segs)
6941 rtl8169_start_xmit(nskb, tp->dev);
6944 dev_consume_skb_any(skb);
6945 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6946 if (skb_checksum_help(skb) < 0)
6949 rtl8169_start_xmit(skb, tp->dev);
6951 struct net_device_stats *stats;
6954 stats = &tp->dev->stats;
6955 stats->tx_dropped++;
6956 dev_kfree_skb_any(skb);
6960 /* msdn_giant_send_check()
6961 * According to the document of microsoft, the TCP Pseudo Header excludes the
6962 * packet length for IPv6 TCP large packets.
6964 static int msdn_giant_send_check(struct sk_buff *skb)
6966 const struct ipv6hdr *ipv6h;
6970 ret = skb_cow_head(skb, 0);
6974 ipv6h = ipv6_hdr(skb);
6978 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6983 static inline __be16 get_protocol(struct sk_buff *skb)
6987 if (skb->protocol == htons(ETH_P_8021Q))
6988 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6990 protocol = skb->protocol;
6995 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6996 struct sk_buff *skb, u32 *opts)
6998 u32 mss = skb_shinfo(skb)->gso_size;
7002 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7003 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7004 const struct iphdr *ip = ip_hdr(skb);
7006 if (ip->protocol == IPPROTO_TCP)
7007 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7008 else if (ip->protocol == IPPROTO_UDP)
7009 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7017 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7018 struct sk_buff *skb, u32 *opts)
7020 u32 transport_offset = (u32)skb_transport_offset(skb);
7021 u32 mss = skb_shinfo(skb)->gso_size;
7024 if (transport_offset > GTTCPHO_MAX) {
7025 netif_warn(tp, tx_err, tp->dev,
7026 "Invalid transport offset 0x%x for TSO\n",
7031 switch (get_protocol(skb)) {
7032 case htons(ETH_P_IP):
7033 opts[0] |= TD1_GTSENV4;
7036 case htons(ETH_P_IPV6):
7037 if (msdn_giant_send_check(skb))
7040 opts[0] |= TD1_GTSENV6;
7048 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7049 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7050 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7053 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7054 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7056 if (transport_offset > TCPHO_MAX) {
7057 netif_warn(tp, tx_err, tp->dev,
7058 "Invalid transport offset 0x%x\n",
7063 switch (get_protocol(skb)) {
7064 case htons(ETH_P_IP):
7065 opts[1] |= TD1_IPv4_CS;
7066 ip_protocol = ip_hdr(skb)->protocol;
7069 case htons(ETH_P_IPV6):
7070 opts[1] |= TD1_IPv6_CS;
7071 ip_protocol = ipv6_hdr(skb)->nexthdr;
7075 ip_protocol = IPPROTO_RAW;
7079 if (ip_protocol == IPPROTO_TCP)
7080 opts[1] |= TD1_TCP_CS;
7081 else if (ip_protocol == IPPROTO_UDP)
7082 opts[1] |= TD1_UDP_CS;
7086 opts[1] |= transport_offset << TCPHO_SHIFT;
7088 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7089 return !eth_skb_pad(skb);
7095 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7096 struct net_device *dev)
7098 struct rtl8169_private *tp = netdev_priv(dev);
7099 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7100 struct TxDesc *txd = tp->TxDescArray + entry;
7101 void __iomem *ioaddr = tp->mmio_addr;
7102 struct device *d = &tp->pci_dev->dev;
7108 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7109 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7113 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7116 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7119 if (!tp->tso_csum(tp, skb, opts)) {
7120 r8169_csum_workaround(tp, skb);
7121 return NETDEV_TX_OK;
7124 len = skb_headlen(skb);
7125 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7126 if (unlikely(dma_mapping_error(d, mapping))) {
7127 if (net_ratelimit())
7128 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7132 tp->tx_skb[entry].len = len;
7133 txd->addr = cpu_to_le64(mapping);
7135 frags = rtl8169_xmit_frags(tp, skb, opts);
7139 opts[0] |= FirstFrag;
7141 opts[0] |= FirstFrag | LastFrag;
7142 tp->tx_skb[entry].skb = skb;
7145 txd->opts2 = cpu_to_le32(opts[1]);
7147 skb_tx_timestamp(skb);
7149 /* Force memory writes to complete before releasing descriptor */
7152 /* Anti gcc 2.95.3 bugware (sic) */
7153 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7154 txd->opts1 = cpu_to_le32(status);
7156 /* Force all memory writes to complete before notifying device */
7159 tp->cur_tx += frags + 1;
7161 RTL_W8(TxPoll, NPQ);
7165 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7166 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7167 * not miss a ring update when it notices a stopped queue.
7170 netif_stop_queue(dev);
7171 /* Sync with rtl_tx:
7172 * - publish queue status and cur_tx ring index (write barrier)
7173 * - refresh dirty_tx ring index (read barrier).
7174 * May the current thread have a pessimistic view of the ring
7175 * status and forget to wake up queue, a racing rtl_tx thread
7179 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7180 netif_wake_queue(dev);
7183 return NETDEV_TX_OK;
7186 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7188 dev_kfree_skb_any(skb);
7189 dev->stats.tx_dropped++;
7190 return NETDEV_TX_OK;
7193 netif_stop_queue(dev);
7194 dev->stats.tx_dropped++;
7195 return NETDEV_TX_BUSY;
7198 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7200 struct rtl8169_private *tp = netdev_priv(dev);
7201 struct pci_dev *pdev = tp->pci_dev;
7202 u16 pci_status, pci_cmd;
7204 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7205 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7207 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7208 pci_cmd, pci_status);
7211 * The recovery sequence below admits a very elaborated explanation:
7212 * - it seems to work;
7213 * - I did not see what else could be done;
7214 * - it makes iop3xx happy.
7216 * Feel free to adjust to your needs.
7218 if (pdev->broken_parity_status)
7219 pci_cmd &= ~PCI_COMMAND_PARITY;
7221 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7223 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7225 pci_write_config_word(pdev, PCI_STATUS,
7226 pci_status & (PCI_STATUS_DETECTED_PARITY |
7227 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7228 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7230 /* The infamous DAC f*ckup only happens at boot time */
7231 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7232 void __iomem *ioaddr = tp->mmio_addr;
7234 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7235 tp->cp_cmd &= ~PCIDAC;
7236 RTL_W16(CPlusCmd, tp->cp_cmd);
7237 dev->features &= ~NETIF_F_HIGHDMA;
7240 rtl8169_hw_reset(tp);
7242 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7245 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7247 unsigned int dirty_tx, tx_left;
7249 dirty_tx = tp->dirty_tx;
7251 tx_left = tp->cur_tx - dirty_tx;
7253 while (tx_left > 0) {
7254 unsigned int entry = dirty_tx % NUM_TX_DESC;
7255 struct ring_info *tx_skb = tp->tx_skb + entry;
7258 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7259 if (status & DescOwn)
7262 /* This barrier is needed to keep us from reading
7263 * any other fields out of the Tx descriptor until
7264 * we know the status of DescOwn
7268 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7269 tp->TxDescArray + entry);
7270 if (status & LastFrag) {
7271 u64_stats_update_begin(&tp->tx_stats.syncp);
7272 tp->tx_stats.packets++;
7273 tp->tx_stats.bytes += tx_skb->skb->len;
7274 u64_stats_update_end(&tp->tx_stats.syncp);
7275 dev_kfree_skb_any(tx_skb->skb);
7282 if (tp->dirty_tx != dirty_tx) {
7283 tp->dirty_tx = dirty_tx;
7284 /* Sync with rtl8169_start_xmit:
7285 * - publish dirty_tx ring index (write barrier)
7286 * - refresh cur_tx ring index and queue status (read barrier)
7287 * May the current thread miss the stopped queue condition,
7288 * a racing xmit thread can only have a right view of the
7292 if (netif_queue_stopped(dev) &&
7293 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7294 netif_wake_queue(dev);
7297 * 8168 hack: TxPoll requests are lost when the Tx packets are
7298 * too close. Let's kick an extra TxPoll request when a burst
7299 * of start_xmit activity is detected (if it is not detected,
7300 * it is slow enough). -- FR
7302 if (tp->cur_tx != dirty_tx) {
7303 void __iomem *ioaddr = tp->mmio_addr;
7305 RTL_W8(TxPoll, NPQ);
7310 static inline int rtl8169_fragmented_frame(u32 status)
7312 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7315 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7317 u32 status = opts1 & RxProtoMask;
7319 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7320 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7321 skb->ip_summed = CHECKSUM_UNNECESSARY;
7323 skb_checksum_none_assert(skb);
7326 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7327 struct rtl8169_private *tp,
7331 struct sk_buff *skb;
7332 struct device *d = &tp->pci_dev->dev;
7334 data = rtl8169_align(data);
7335 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7337 skb = napi_alloc_skb(&tp->napi, pkt_size);
7339 memcpy(skb->data, data, pkt_size);
7340 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7345 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7347 unsigned int cur_rx, rx_left;
7350 cur_rx = tp->cur_rx;
7352 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7353 unsigned int entry = cur_rx % NUM_RX_DESC;
7354 struct RxDesc *desc = tp->RxDescArray + entry;
7357 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7358 if (status & DescOwn)
7361 /* This barrier is needed to keep us from reading
7362 * any other fields out of the Rx descriptor until
7363 * we know the status of DescOwn
7367 if (unlikely(status & RxRES)) {
7368 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7370 dev->stats.rx_errors++;
7371 if (status & (RxRWT | RxRUNT))
7372 dev->stats.rx_length_errors++;
7374 dev->stats.rx_crc_errors++;
7375 if (status & RxFOVF) {
7376 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7377 dev->stats.rx_fifo_errors++;
7379 if ((status & (RxRUNT | RxCRC)) &&
7380 !(status & (RxRWT | RxFOVF)) &&
7381 (dev->features & NETIF_F_RXALL))
7384 struct sk_buff *skb;
7389 addr = le64_to_cpu(desc->addr);
7390 if (likely(!(dev->features & NETIF_F_RXFCS)))
7391 pkt_size = (status & 0x00003fff) - 4;
7393 pkt_size = status & 0x00003fff;
7396 * The driver does not support incoming fragmented
7397 * frames. They are seen as a symptom of over-mtu
7400 if (unlikely(rtl8169_fragmented_frame(status))) {
7401 dev->stats.rx_dropped++;
7402 dev->stats.rx_length_errors++;
7403 goto release_descriptor;
7406 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7407 tp, pkt_size, addr);
7409 dev->stats.rx_dropped++;
7410 goto release_descriptor;
7413 rtl8169_rx_csum(skb, status);
7414 skb_put(skb, pkt_size);
7415 skb->protocol = eth_type_trans(skb, dev);
7417 rtl8169_rx_vlan_tag(desc, skb);
7419 if (skb->pkt_type == PACKET_MULTICAST)
7420 dev->stats.multicast++;
7422 napi_gro_receive(&tp->napi, skb);
7424 u64_stats_update_begin(&tp->rx_stats.syncp);
7425 tp->rx_stats.packets++;
7426 tp->rx_stats.bytes += pkt_size;
7427 u64_stats_update_end(&tp->rx_stats.syncp);
7431 rtl8169_mark_to_asic(desc, rx_buf_sz);
7434 count = cur_rx - tp->cur_rx;
7435 tp->cur_rx = cur_rx;
7440 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7442 struct net_device *dev = dev_instance;
7443 struct rtl8169_private *tp = netdev_priv(dev);
7447 status = rtl_get_events(tp);
7448 if (status && status != 0xffff) {
7449 status &= RTL_EVENT_NAPI | tp->event_slow;
7453 rtl_irq_disable(tp);
7454 napi_schedule(&tp->napi);
7457 return IRQ_RETVAL(handled);
7461 * Workqueue context.
7463 static void rtl_slow_event_work(struct rtl8169_private *tp)
7465 struct net_device *dev = tp->dev;
7468 status = rtl_get_events(tp) & tp->event_slow;
7469 rtl_ack_events(tp, status);
7471 if (unlikely(status & RxFIFOOver)) {
7472 switch (tp->mac_version) {
7473 /* Work around for rx fifo overflow */
7474 case RTL_GIGA_MAC_VER_11:
7475 netif_stop_queue(dev);
7476 /* XXX - Hack alert. See rtl_task(). */
7477 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7483 if (unlikely(status & SYSErr))
7484 rtl8169_pcierr_interrupt(dev);
7486 if (status & LinkChg)
7487 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
7489 rtl_irq_enable_all(tp);
7492 static void rtl_task(struct work_struct *work)
7494 static const struct {
7496 void (*action)(struct rtl8169_private *);
7498 /* XXX - keep rtl_slow_event_work() as first element. */
7499 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7500 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7501 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7503 struct rtl8169_private *tp =
7504 container_of(work, struct rtl8169_private, wk.work);
7505 struct net_device *dev = tp->dev;
7510 if (!netif_running(dev) ||
7511 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7514 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7517 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7519 rtl_work[i].action(tp);
7523 rtl_unlock_work(tp);
7526 static int rtl8169_poll(struct napi_struct *napi, int budget)
7528 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7529 struct net_device *dev = tp->dev;
7530 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7534 status = rtl_get_events(tp);
7535 rtl_ack_events(tp, status & ~tp->event_slow);
7537 work_done = rtl_rx(dev, tp, (u32) budget);
7541 if (status & tp->event_slow) {
7542 enable_mask &= ~tp->event_slow;
7544 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7547 if (work_done < budget) {
7548 napi_complete(napi);
7550 rtl_irq_enable(tp, enable_mask);
7557 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7559 struct rtl8169_private *tp = netdev_priv(dev);
7561 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7564 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7565 RTL_W32(RxMissed, 0);
7568 static void rtl8169_down(struct net_device *dev)
7570 struct rtl8169_private *tp = netdev_priv(dev);
7571 void __iomem *ioaddr = tp->mmio_addr;
7573 del_timer_sync(&tp->timer);
7575 napi_disable(&tp->napi);
7576 netif_stop_queue(dev);
7578 rtl8169_hw_reset(tp);
7580 * At this point device interrupts can not be enabled in any function,
7581 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7582 * and napi is disabled (rtl8169_poll).
7584 rtl8169_rx_missed(dev, ioaddr);
7586 /* Give a racing hard_start_xmit a few cycles to complete. */
7587 synchronize_sched();
7589 rtl8169_tx_clear(tp);
7591 rtl8169_rx_clear(tp);
7593 rtl_pll_power_down(tp);
7596 static int rtl8169_close(struct net_device *dev)
7598 struct rtl8169_private *tp = netdev_priv(dev);
7599 struct pci_dev *pdev = tp->pci_dev;
7601 pm_runtime_get_sync(&pdev->dev);
7603 /* Update counters before going down */
7604 rtl8169_update_counters(dev);
7607 /* Clear all task flags */
7608 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
7611 rtl_unlock_work(tp);
7613 cancel_work_sync(&tp->wk.work);
7615 free_irq(pdev->irq, dev);
7617 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7619 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7621 tp->TxDescArray = NULL;
7622 tp->RxDescArray = NULL;
7624 pm_runtime_put_sync(&pdev->dev);
7629 #ifdef CONFIG_NET_POLL_CONTROLLER
7630 static void rtl8169_netpoll(struct net_device *dev)
7632 struct rtl8169_private *tp = netdev_priv(dev);
7634 rtl8169_interrupt(tp->pci_dev->irq, dev);
7638 static int rtl_open(struct net_device *dev)
7640 struct rtl8169_private *tp = netdev_priv(dev);
7641 void __iomem *ioaddr = tp->mmio_addr;
7642 struct pci_dev *pdev = tp->pci_dev;
7643 int retval = -ENOMEM;
7645 pm_runtime_get_sync(&pdev->dev);
7648 * Rx and Tx descriptors needs 256 bytes alignment.
7649 * dma_alloc_coherent provides more.
7651 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7652 &tp->TxPhyAddr, GFP_KERNEL);
7653 if (!tp->TxDescArray)
7654 goto err_pm_runtime_put;
7656 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7657 &tp->RxPhyAddr, GFP_KERNEL);
7658 if (!tp->RxDescArray)
7661 retval = rtl8169_init_ring(dev);
7665 INIT_WORK(&tp->wk.work, rtl_task);
7669 rtl_request_firmware(tp);
7671 retval = request_irq(pdev->irq, rtl8169_interrupt,
7672 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7675 goto err_release_fw_2;
7679 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7681 napi_enable(&tp->napi);
7683 rtl8169_init_phy(dev, tp);
7685 __rtl8169_set_features(dev, dev->features);
7687 rtl_pll_power_up(tp);
7691 if (!rtl8169_init_counter_offsets(dev))
7692 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7694 netif_start_queue(dev);
7696 rtl_unlock_work(tp);
7698 tp->saved_wolopts = 0;
7699 pm_runtime_put_noidle(&pdev->dev);
7701 rtl8169_check_link_status(dev, tp, ioaddr);
7706 rtl_release_firmware(tp);
7707 rtl8169_rx_clear(tp);
7709 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7711 tp->RxDescArray = NULL;
7713 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7715 tp->TxDescArray = NULL;
7717 pm_runtime_put_noidle(&pdev->dev);
7721 static struct rtnl_link_stats64 *
7722 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7724 struct rtl8169_private *tp = netdev_priv(dev);
7725 void __iomem *ioaddr = tp->mmio_addr;
7726 struct rtl8169_counters *counters = tp->counters;
7729 if (netif_running(dev))
7730 rtl8169_rx_missed(dev, ioaddr);
7733 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7734 stats->rx_packets = tp->rx_stats.packets;
7735 stats->rx_bytes = tp->rx_stats.bytes;
7736 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7739 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7740 stats->tx_packets = tp->tx_stats.packets;
7741 stats->tx_bytes = tp->tx_stats.bytes;
7742 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7744 stats->rx_dropped = dev->stats.rx_dropped;
7745 stats->tx_dropped = dev->stats.tx_dropped;
7746 stats->rx_length_errors = dev->stats.rx_length_errors;
7747 stats->rx_errors = dev->stats.rx_errors;
7748 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7749 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7750 stats->rx_missed_errors = dev->stats.rx_missed_errors;
7751 stats->multicast = dev->stats.multicast;
7754 * Fetch additonal counter values missing in stats collected by driver
7755 * from tally counters.
7757 rtl8169_update_counters(dev);
7760 * Subtract values fetched during initalization.
7761 * See rtl8169_init_counter_offsets for a description why we do that.
7763 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
7764 le64_to_cpu(tp->tc_offset.tx_errors);
7765 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
7766 le32_to_cpu(tp->tc_offset.tx_multi_collision);
7767 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
7768 le16_to_cpu(tp->tc_offset.tx_aborted);
7773 static void rtl8169_net_suspend(struct net_device *dev)
7775 struct rtl8169_private *tp = netdev_priv(dev);
7777 if (!netif_running(dev))
7780 netif_device_detach(dev);
7781 netif_stop_queue(dev);
7784 napi_disable(&tp->napi);
7785 /* Clear all task flags */
7786 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
7788 rtl_unlock_work(tp);
7790 rtl_pll_power_down(tp);
7795 static int rtl8169_suspend(struct device *device)
7797 struct pci_dev *pdev = to_pci_dev(device);
7798 struct net_device *dev = pci_get_drvdata(pdev);
7800 rtl8169_net_suspend(dev);
7805 static void __rtl8169_resume(struct net_device *dev)
7807 struct rtl8169_private *tp = netdev_priv(dev);
7809 netif_device_attach(dev);
7811 rtl_pll_power_up(tp);
7814 napi_enable(&tp->napi);
7815 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7816 rtl_unlock_work(tp);
7818 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7821 static int rtl8169_resume(struct device *device)
7823 struct pci_dev *pdev = to_pci_dev(device);
7824 struct net_device *dev = pci_get_drvdata(pdev);
7825 struct rtl8169_private *tp = netdev_priv(dev);
7827 rtl8169_init_phy(dev, tp);
7829 if (netif_running(dev))
7830 __rtl8169_resume(dev);
7835 static int rtl8169_runtime_suspend(struct device *device)
7837 struct pci_dev *pdev = to_pci_dev(device);
7838 struct net_device *dev = pci_get_drvdata(pdev);
7839 struct rtl8169_private *tp = netdev_priv(dev);
7841 if (!tp->TxDescArray)
7845 tp->saved_wolopts = __rtl8169_get_wol(tp);
7846 __rtl8169_set_wol(tp, WAKE_ANY);
7847 rtl_unlock_work(tp);
7849 rtl8169_net_suspend(dev);
7854 static int rtl8169_runtime_resume(struct device *device)
7856 struct pci_dev *pdev = to_pci_dev(device);
7857 struct net_device *dev = pci_get_drvdata(pdev);
7858 struct rtl8169_private *tp = netdev_priv(dev);
7860 if (!tp->TxDescArray)
7864 __rtl8169_set_wol(tp, tp->saved_wolopts);
7865 tp->saved_wolopts = 0;
7866 rtl_unlock_work(tp);
7868 rtl8169_init_phy(dev, tp);
7870 __rtl8169_resume(dev);
7875 static int rtl8169_runtime_idle(struct device *device)
7877 struct pci_dev *pdev = to_pci_dev(device);
7878 struct net_device *dev = pci_get_drvdata(pdev);
7879 struct rtl8169_private *tp = netdev_priv(dev);
7881 return tp->TxDescArray ? -EBUSY : 0;
7884 static const struct dev_pm_ops rtl8169_pm_ops = {
7885 .suspend = rtl8169_suspend,
7886 .resume = rtl8169_resume,
7887 .freeze = rtl8169_suspend,
7888 .thaw = rtl8169_resume,
7889 .poweroff = rtl8169_suspend,
7890 .restore = rtl8169_resume,
7891 .runtime_suspend = rtl8169_runtime_suspend,
7892 .runtime_resume = rtl8169_runtime_resume,
7893 .runtime_idle = rtl8169_runtime_idle,
7896 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
7898 #else /* !CONFIG_PM */
7900 #define RTL8169_PM_OPS NULL
7902 #endif /* !CONFIG_PM */
7904 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7906 void __iomem *ioaddr = tp->mmio_addr;
7908 /* WoL fails with 8168b when the receiver is disabled. */
7909 switch (tp->mac_version) {
7910 case RTL_GIGA_MAC_VER_11:
7911 case RTL_GIGA_MAC_VER_12:
7912 case RTL_GIGA_MAC_VER_17:
7913 pci_clear_master(tp->pci_dev);
7915 RTL_W8(ChipCmd, CmdRxEnb);
7924 static void rtl_shutdown(struct pci_dev *pdev)
7926 struct net_device *dev = pci_get_drvdata(pdev);
7927 struct rtl8169_private *tp = netdev_priv(dev);
7928 struct device *d = &pdev->dev;
7930 pm_runtime_get_sync(d);
7932 rtl8169_net_suspend(dev);
7934 /* Restore original MAC address */
7935 rtl_rar_set(tp, dev->perm_addr);
7937 rtl8169_hw_reset(tp);
7939 if (system_state == SYSTEM_POWER_OFF) {
7940 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7941 rtl_wol_suspend_quirk(tp);
7942 rtl_wol_shutdown_quirk(tp);
7945 pci_wake_from_d3(pdev, true);
7946 pci_set_power_state(pdev, PCI_D3hot);
7949 pm_runtime_put_noidle(d);
7952 static void rtl_remove_one(struct pci_dev *pdev)
7954 struct net_device *dev = pci_get_drvdata(pdev);
7955 struct rtl8169_private *tp = netdev_priv(dev);
7957 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7958 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7959 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
7960 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
7961 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
7962 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
7963 r8168_check_dash(tp)) {
7964 rtl8168_driver_stop(tp);
7967 netif_napi_del(&tp->napi);
7969 unregister_netdev(dev);
7971 dma_free_coherent(&tp->pci_dev->dev, sizeof(*tp->counters),
7972 tp->counters, tp->counters_phys_addr);
7974 rtl_release_firmware(tp);
7976 if (pci_dev_run_wake(pdev))
7977 pm_runtime_get_noresume(&pdev->dev);
7979 /* restore original MAC address */
7980 rtl_rar_set(tp, dev->perm_addr);
7982 rtl_disable_msi(pdev, tp);
7983 rtl8169_release_board(pdev, dev, tp->mmio_addr);
7986 static const struct net_device_ops rtl_netdev_ops = {
7987 .ndo_open = rtl_open,
7988 .ndo_stop = rtl8169_close,
7989 .ndo_get_stats64 = rtl8169_get_stats64,
7990 .ndo_start_xmit = rtl8169_start_xmit,
7991 .ndo_tx_timeout = rtl8169_tx_timeout,
7992 .ndo_validate_addr = eth_validate_addr,
7993 .ndo_change_mtu = rtl8169_change_mtu,
7994 .ndo_fix_features = rtl8169_fix_features,
7995 .ndo_set_features = rtl8169_set_features,
7996 .ndo_set_mac_address = rtl_set_mac_address,
7997 .ndo_do_ioctl = rtl8169_ioctl,
7998 .ndo_set_rx_mode = rtl_set_rx_mode,
7999 #ifdef CONFIG_NET_POLL_CONTROLLER
8000 .ndo_poll_controller = rtl8169_netpoll,
8005 static const struct rtl_cfg_info {
8006 void (*hw_start)(struct net_device *);
8007 unsigned int region;
8012 } rtl_cfg_infos [] = {
8014 .hw_start = rtl_hw_start_8169,
8017 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8018 .features = RTL_FEATURE_GMII,
8019 .default_ver = RTL_GIGA_MAC_VER_01,
8022 .hw_start = rtl_hw_start_8168,
8025 .event_slow = SYSErr | LinkChg | RxOverflow,
8026 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8027 .default_ver = RTL_GIGA_MAC_VER_11,
8030 .hw_start = rtl_hw_start_8101,
8033 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8035 .features = RTL_FEATURE_MSI,
8036 .default_ver = RTL_GIGA_MAC_VER_13,
8040 /* Cfg9346_Unlock assumed. */
8041 static unsigned rtl_try_msi(struct rtl8169_private *tp,
8042 const struct rtl_cfg_info *cfg)
8044 void __iomem *ioaddr = tp->mmio_addr;
8048 cfg2 = RTL_R8(Config2) & ~MSIEnable;
8049 if (cfg->features & RTL_FEATURE_MSI) {
8050 if (pci_enable_msi(tp->pci_dev)) {
8051 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8054 msi = RTL_FEATURE_MSI;
8057 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8058 RTL_W8(Config2, cfg2);
8062 DECLARE_RTL_COND(rtl_link_list_ready_cond)
8064 void __iomem *ioaddr = tp->mmio_addr;
8066 return RTL_R8(MCU) & LINK_LIST_RDY;
8069 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8071 void __iomem *ioaddr = tp->mmio_addr;
8073 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8076 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8078 void __iomem *ioaddr = tp->mmio_addr;
8081 tp->ocp_base = OCP_STD_PHY_BASE;
8083 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8085 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8088 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8091 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8093 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8095 data = r8168_mac_ocp_read(tp, 0xe8de);
8097 r8168_mac_ocp_write(tp, 0xe8de, data);
8099 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8102 data = r8168_mac_ocp_read(tp, 0xe8de);
8104 r8168_mac_ocp_write(tp, 0xe8de, data);
8106 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8110 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8112 rtl8168ep_stop_cmac(tp);
8113 rtl_hw_init_8168g(tp);
8116 static void rtl_hw_initialize(struct rtl8169_private *tp)
8118 switch (tp->mac_version) {
8119 case RTL_GIGA_MAC_VER_40:
8120 case RTL_GIGA_MAC_VER_41:
8121 case RTL_GIGA_MAC_VER_42:
8122 case RTL_GIGA_MAC_VER_43:
8123 case RTL_GIGA_MAC_VER_44:
8124 case RTL_GIGA_MAC_VER_45:
8125 case RTL_GIGA_MAC_VER_46:
8126 case RTL_GIGA_MAC_VER_47:
8127 case RTL_GIGA_MAC_VER_48:
8128 rtl_hw_init_8168g(tp);
8130 case RTL_GIGA_MAC_VER_49:
8131 case RTL_GIGA_MAC_VER_50:
8132 case RTL_GIGA_MAC_VER_51:
8133 rtl_hw_init_8168ep(tp);
8140 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8142 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8143 const unsigned int region = cfg->region;
8144 struct rtl8169_private *tp;
8145 struct mii_if_info *mii;
8146 struct net_device *dev;
8147 void __iomem *ioaddr;
8151 if (netif_msg_drv(&debug)) {
8152 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8153 MODULENAME, RTL8169_VERSION);
8156 dev = alloc_etherdev(sizeof (*tp));
8162 SET_NETDEV_DEV(dev, &pdev->dev);
8163 dev->netdev_ops = &rtl_netdev_ops;
8164 tp = netdev_priv(dev);
8167 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8171 mii->mdio_read = rtl_mdio_read;
8172 mii->mdio_write = rtl_mdio_write;
8173 mii->phy_id_mask = 0x1f;
8174 mii->reg_num_mask = 0x1f;
8175 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8177 /* disable ASPM completely as that cause random device stop working
8178 * problems as well as full system hangs for some PCIe devices users */
8179 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8180 PCIE_LINK_STATE_CLKPM);
8182 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8183 rc = pci_enable_device(pdev);
8185 netif_err(tp, probe, dev, "enable failure\n");
8186 goto err_out_free_dev_1;
8189 if (pci_set_mwi(pdev) < 0)
8190 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8192 /* make sure PCI base addr 1 is MMIO */
8193 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8194 netif_err(tp, probe, dev,
8195 "region #%d not an MMIO resource, aborting\n",
8201 /* check for weird/broken PCI region reporting */
8202 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8203 netif_err(tp, probe, dev,
8204 "Invalid PCI region size(s), aborting\n");
8209 rc = pci_request_regions(pdev, MODULENAME);
8211 netif_err(tp, probe, dev, "could not request regions\n");
8217 if ((sizeof(dma_addr_t) > 4) &&
8218 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
8219 tp->cp_cmd |= PCIDAC;
8220 dev->features |= NETIF_F_HIGHDMA;
8222 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8224 netif_err(tp, probe, dev, "DMA configuration failed\n");
8225 goto err_out_free_res_3;
8229 /* ioremap MMIO region */
8230 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8232 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8234 goto err_out_free_res_3;
8236 tp->mmio_addr = ioaddr;
8238 if (!pci_is_pcie(pdev))
8239 netif_info(tp, probe, dev, "not PCI Express\n");
8241 /* Identify chip attached to board */
8242 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8246 rtl_irq_disable(tp);
8248 rtl_hw_initialize(tp);
8252 rtl_ack_events(tp, 0xffff);
8254 pci_set_master(pdev);
8256 rtl_init_mdio_ops(tp);
8257 rtl_init_pll_power_ops(tp);
8258 rtl_init_jumbo_ops(tp);
8259 rtl_init_csi_ops(tp);
8261 rtl8169_print_mac_version(tp);
8263 chipset = tp->mac_version;
8264 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8266 RTL_W8(Cfg9346, Cfg9346_Unlock);
8267 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8268 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8269 switch (tp->mac_version) {
8270 case RTL_GIGA_MAC_VER_34:
8271 case RTL_GIGA_MAC_VER_35:
8272 case RTL_GIGA_MAC_VER_36:
8273 case RTL_GIGA_MAC_VER_37:
8274 case RTL_GIGA_MAC_VER_38:
8275 case RTL_GIGA_MAC_VER_40:
8276 case RTL_GIGA_MAC_VER_41:
8277 case RTL_GIGA_MAC_VER_42:
8278 case RTL_GIGA_MAC_VER_43:
8279 case RTL_GIGA_MAC_VER_44:
8280 case RTL_GIGA_MAC_VER_45:
8281 case RTL_GIGA_MAC_VER_46:
8282 case RTL_GIGA_MAC_VER_47:
8283 case RTL_GIGA_MAC_VER_48:
8284 case RTL_GIGA_MAC_VER_49:
8285 case RTL_GIGA_MAC_VER_50:
8286 case RTL_GIGA_MAC_VER_51:
8287 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8288 tp->features |= RTL_FEATURE_WOL;
8289 if ((RTL_R8(Config3) & LinkUp) != 0)
8290 tp->features |= RTL_FEATURE_WOL;
8293 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8294 tp->features |= RTL_FEATURE_WOL;
8297 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8298 tp->features |= RTL_FEATURE_WOL;
8299 tp->features |= rtl_try_msi(tp, cfg);
8300 RTL_W8(Cfg9346, Cfg9346_Lock);
8302 if (rtl_tbi_enabled(tp)) {
8303 tp->set_speed = rtl8169_set_speed_tbi;
8304 tp->get_settings = rtl8169_gset_tbi;
8305 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8306 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8307 tp->link_ok = rtl8169_tbi_link_ok;
8308 tp->do_ioctl = rtl_tbi_ioctl;
8310 tp->set_speed = rtl8169_set_speed_xmii;
8311 tp->get_settings = rtl8169_gset_xmii;
8312 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8313 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8314 tp->link_ok = rtl8169_xmii_link_ok;
8315 tp->do_ioctl = rtl_xmii_ioctl;
8318 mutex_init(&tp->wk.mutex);
8319 u64_stats_init(&tp->rx_stats.syncp);
8320 u64_stats_init(&tp->tx_stats.syncp);
8322 /* Get MAC address */
8323 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8324 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8325 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8326 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8327 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8328 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8329 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8330 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8331 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8332 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8333 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8334 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8335 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8336 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8337 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8338 tp->mac_version == RTL_GIGA_MAC_VER_51) {
8341 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8342 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8344 if (is_valid_ether_addr((u8 *)mac_addr))
8345 rtl_rar_set(tp, (u8 *)mac_addr);
8347 for (i = 0; i < ETH_ALEN; i++)
8348 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8350 dev->ethtool_ops = &rtl8169_ethtool_ops;
8351 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8353 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8355 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8356 * properly for all devices */
8357 dev->features |= NETIF_F_RXCSUM |
8358 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8360 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8361 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8362 NETIF_F_HW_VLAN_CTAG_RX;
8363 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8366 tp->cp_cmd |= RxChkSum | RxVlan;
8369 * Pretend we are using VLANs; This bypasses a nasty bug where
8370 * Interrupts stop flowing on high load on 8110SCd controllers.
8372 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8373 /* Disallow toggling */
8374 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8376 if (tp->txd_version == RTL_TD_0)
8377 tp->tso_csum = rtl8169_tso_csum_v1;
8378 else if (tp->txd_version == RTL_TD_1) {
8379 tp->tso_csum = rtl8169_tso_csum_v2;
8380 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8384 dev->hw_features |= NETIF_F_RXALL;
8385 dev->hw_features |= NETIF_F_RXFCS;
8387 tp->hw_start = cfg->hw_start;
8388 tp->event_slow = cfg->event_slow;
8390 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8391 ~(RxBOVF | RxFOVF) : ~0;
8393 init_timer(&tp->timer);
8394 tp->timer.data = (unsigned long) dev;
8395 tp->timer.function = rtl8169_phy_timer;
8397 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8399 tp->counters = dma_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8400 &tp->counters_phys_addr, GFP_KERNEL);
8401 if (!tp->counters) {
8406 pci_set_drvdata(pdev, dev);
8408 rc = register_netdev(dev);
8412 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8413 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8414 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8415 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8416 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8417 "tx checksumming: %s]\n",
8418 rtl_chip_infos[chipset].jumbo_max,
8419 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8422 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8423 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8424 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8425 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8426 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8427 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8428 r8168_check_dash(tp)) {
8429 rtl8168_driver_start(tp);
8432 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8434 if (pci_dev_run_wake(pdev))
8435 pm_runtime_put_noidle(&pdev->dev);
8437 netif_carrier_off(dev);
8443 dma_free_coherent(&pdev->dev, sizeof(*tp->counters), tp->counters,
8444 tp->counters_phys_addr);
8446 netif_napi_del(&tp->napi);
8447 rtl_disable_msi(pdev, tp);
8450 pci_release_regions(pdev);
8452 pci_clear_mwi(pdev);
8453 pci_disable_device(pdev);
8459 static struct pci_driver rtl8169_pci_driver = {
8461 .id_table = rtl8169_pci_tbl,
8462 .probe = rtl_init_one,
8463 .remove = rtl_remove_one,
8464 .shutdown = rtl_shutdown,
8465 .driver.pm = RTL8169_PM_OPS,
8468 module_pci_driver(rtl8169_pci_driver);