drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "/*(DEBLOBBED)*/"
  41 #define FIRMWARE_8168D_2        "/*(DEBLOBBED)*/"
  42 #define FIRMWARE_8168E_1        "/*(DEBLOBBED)*/"
  43 #define FIRMWARE_8168E_2        "/*(DEBLOBBED)*/"
  44 #define FIRMWARE_8168E_3        "/*(DEBLOBBED)*/"
  45 #define FIRMWARE_8168F_1        "/*(DEBLOBBED)*/"
  46 #define FIRMWARE_8168F_2        "/*(DEBLOBBED)*/"
  47 #define FIRMWARE_8105E_1        "/*(DEBLOBBED)*/"
  48 #define FIRMWARE_8402_1         "/*(DEBLOBBED)*/"
  49 #define FIRMWARE_8411_1         "/*(DEBLOBBED)*/"
  50 #define FIRMWARE_8411_2         "/*(DEBLOBBED)*/"
  51 #define FIRMWARE_8106E_1        "/*(DEBLOBBED)*/"
  52 #define FIRMWARE_8106E_2        "/*(DEBLOBBED)*/"
  53 #define FIRMWARE_8168G_2        "/*(DEBLOBBED)*/"
  54 #define FIRMWARE_8168G_3        "/*(DEBLOBBED)*/"
  55 #define FIRMWARE_8168H_1        "/*(DEBLOBBED)*/"
  56 #define FIRMWARE_8168H_2        "/*(DEBLOBBED)*/"
  57 #define FIRMWARE_8107E_1        "/*(DEBLOBBED)*/"
  58 #define FIRMWARE_8107E_2        "/*(DEBLOBBED)*/"
  59
  60 #ifdef RTL8169_DEBUG
  61 #define assert(expr) \
  62         if (!(expr)) {                                  \
  63                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  64                 #expr,__FILE__,__func__,__LINE__);              \
  65         }
  66 #define dprintk(fmt, args...) \
  67         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  68 #else
  69 #define assert(expr) do {} while (0)
  70 #define dprintk(fmt, args...)   do {} while (0)
  71 #endif /* RTL8169_DEBUG */
  72
  73 #define R8169_MSG_DEFAULT \
  74         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  75
  76 #define TX_SLOTS_AVAIL(tp) \
  77         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  78
  79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  81         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  82
  83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  84    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  85 static const int multicast_filter_limit = 32;
  86
  87 #define MAX_READ_REQUEST_SHIFT  12
  88 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  89 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  90
  91 #define R8169_REGS_SIZE         256
  92 #define R8169_NAPI_WEIGHT       64
  93 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  94 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  95 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  96 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  97
  98 #define RTL8169_TX_TIMEOUT      (6*HZ)
  99 #define RTL8169_PHY_TIMEOUT     (10*HZ)
 100
 101 /* write/read MMIO register */
 102 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 103 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 104 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 105 #define RTL_R8(reg)             readb (ioaddr + (reg))
 106 #define RTL_R16(reg)            readw (ioaddr + (reg))
 107 #define RTL_R32(reg)            readl (ioaddr + (reg))
 108
 109 enum mac_version {
 110         RTL_GIGA_MAC_VER_01 = 0,
 111         RTL_GIGA_MAC_VER_02,
 112         RTL_GIGA_MAC_VER_03,
 113         RTL_GIGA_MAC_VER_04,
 114         RTL_GIGA_MAC_VER_05,
 115         RTL_GIGA_MAC_VER_06,
 116         RTL_GIGA_MAC_VER_07,
 117         RTL_GIGA_MAC_VER_08,
 118         RTL_GIGA_MAC_VER_09,
 119         RTL_GIGA_MAC_VER_10,
 120         RTL_GIGA_MAC_VER_11,
 121         RTL_GIGA_MAC_VER_12,
 122         RTL_GIGA_MAC_VER_13,
 123         RTL_GIGA_MAC_VER_14,
 124         RTL_GIGA_MAC_VER_15,
 125         RTL_GIGA_MAC_VER_16,
 126         RTL_GIGA_MAC_VER_17,
 127         RTL_GIGA_MAC_VER_18,
 128         RTL_GIGA_MAC_VER_19,
 129         RTL_GIGA_MAC_VER_20,
 130         RTL_GIGA_MAC_VER_21,
 131         RTL_GIGA_MAC_VER_22,
 132         RTL_GIGA_MAC_VER_23,
 133         RTL_GIGA_MAC_VER_24,
 134         RTL_GIGA_MAC_VER_25,
 135         RTL_GIGA_MAC_VER_26,
 136         RTL_GIGA_MAC_VER_27,
 137         RTL_GIGA_MAC_VER_28,
 138         RTL_GIGA_MAC_VER_29,
 139         RTL_GIGA_MAC_VER_30,
 140         RTL_GIGA_MAC_VER_31,
 141         RTL_GIGA_MAC_VER_32,
 142         RTL_GIGA_MAC_VER_33,
 143         RTL_GIGA_MAC_VER_34,
 144         RTL_GIGA_MAC_VER_35,
 145         RTL_GIGA_MAC_VER_36,
 146         RTL_GIGA_MAC_VER_37,
 147         RTL_GIGA_MAC_VER_38,
 148         RTL_GIGA_MAC_VER_39,
 149         RTL_GIGA_MAC_VER_40,
 150         RTL_GIGA_MAC_VER_41,
 151         RTL_GIGA_MAC_VER_42,
 152         RTL_GIGA_MAC_VER_43,
 153         RTL_GIGA_MAC_VER_44,
 154         RTL_GIGA_MAC_VER_45,
 155         RTL_GIGA_MAC_VER_46,
 156         RTL_GIGA_MAC_VER_47,
 157         RTL_GIGA_MAC_VER_48,
 158         RTL_GIGA_MAC_VER_49,
 159         RTL_GIGA_MAC_VER_50,
 160         RTL_GIGA_MAC_VER_51,
 161         RTL_GIGA_MAC_NONE   = 0xff,
 162 };
 163
 164 enum rtl_tx_desc_version {
 165         RTL_TD_0        = 0,
 166         RTL_TD_1        = 1,
 167 };
 168
 169 #define JUMBO_1K        ETH_DATA_LEN
 170 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 171 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 172 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 173 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 174
 175 #define _R(NAME,TD,FW,SZ,B) {   \
 176         .name = NAME,           \
 177         .txd_version = TD,      \
 178         .fw_name = FW,          \
 179         .jumbo_max = SZ,        \
 180         .jumbo_tx_csum = B      \
 181 }
 182
 183 static const struct {
 184         const char *name;
 185         enum rtl_tx_desc_version txd_version;
 186         const char *fw_name;
 187         u16 jumbo_max;
 188         bool jumbo_tx_csum;
 189 } rtl_chip_infos[] = {
 190         /* PCI devices. */
 191         [RTL_GIGA_MAC_VER_01] =
 192                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 193         [RTL_GIGA_MAC_VER_02] =
 194                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 195         [RTL_GIGA_MAC_VER_03] =
 196                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 197         [RTL_GIGA_MAC_VER_04] =
 198                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 199         [RTL_GIGA_MAC_VER_05] =
 200                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 201         [RTL_GIGA_MAC_VER_06] =
 202                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 203         /* PCI-E devices. */
 204         [RTL_GIGA_MAC_VER_07] =
 205                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 206         [RTL_GIGA_MAC_VER_08] =
 207                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 208         [RTL_GIGA_MAC_VER_09] =
 209                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 210         [RTL_GIGA_MAC_VER_10] =
 211                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 212         [RTL_GIGA_MAC_VER_11] =
 213                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 214         [RTL_GIGA_MAC_VER_12] =
 215                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 216         [RTL_GIGA_MAC_VER_13] =
 217                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 218         [RTL_GIGA_MAC_VER_14] =
 219                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 220         [RTL_GIGA_MAC_VER_15] =
 221                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 222         [RTL_GIGA_MAC_VER_16] =
 223                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 224         [RTL_GIGA_MAC_VER_17] =
 225                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 226         [RTL_GIGA_MAC_VER_18] =
 227                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 228         [RTL_GIGA_MAC_VER_19] =
 229                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 230         [RTL_GIGA_MAC_VER_20] =
 231                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 232         [RTL_GIGA_MAC_VER_21] =
 233                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 234         [RTL_GIGA_MAC_VER_22] =
 235                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 236         [RTL_GIGA_MAC_VER_23] =
 237                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 238         [RTL_GIGA_MAC_VER_24] =
 239                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 240         [RTL_GIGA_MAC_VER_25] =
 241                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_26] =
 244                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_27] =
 247                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 248         [RTL_GIGA_MAC_VER_28] =
 249                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 250         [RTL_GIGA_MAC_VER_29] =
 251                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 252                                                         JUMBO_1K, true),
 253         [RTL_GIGA_MAC_VER_30] =
 254                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 255                                                         JUMBO_1K, true),
 256         [RTL_GIGA_MAC_VER_31] =
 257                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 258         [RTL_GIGA_MAC_VER_32] =
 259                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 260                                                         JUMBO_9K, false),
 261         [RTL_GIGA_MAC_VER_33] =
 262                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 263                                                         JUMBO_9K, false),
 264         [RTL_GIGA_MAC_VER_34] =
 265                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 266                                                         JUMBO_9K, false),
 267         [RTL_GIGA_MAC_VER_35] =
 268                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 269                                                         JUMBO_9K, false),
 270         [RTL_GIGA_MAC_VER_36] =
 271                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 272                                                         JUMBO_9K, false),
 273         [RTL_GIGA_MAC_VER_37] =
 274                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 275                                                         JUMBO_1K, true),
 276         [RTL_GIGA_MAC_VER_38] =
 277                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 278                                                         JUMBO_9K, false),
 279         [RTL_GIGA_MAC_VER_39] =
 280                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 281                                                         JUMBO_1K, true),
 282         [RTL_GIGA_MAC_VER_40] =
 283                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 284                                                         JUMBO_9K, false),
 285         [RTL_GIGA_MAC_VER_41] =
 286                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 287         [RTL_GIGA_MAC_VER_42] =
 288                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 289                                                         JUMBO_9K, false),
 290         [RTL_GIGA_MAC_VER_43] =
 291                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 292                                                         JUMBO_1K, true),
 293         [RTL_GIGA_MAC_VER_44] =
 294                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
 295                                                         JUMBO_9K, false),
 296         [RTL_GIGA_MAC_VER_45] =
 297                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1,
 298                                                         JUMBO_9K, false),
 299         [RTL_GIGA_MAC_VER_46] =
 300                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2,
 301                                                         JUMBO_9K, false),
 302         [RTL_GIGA_MAC_VER_47] =
 303                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1,
 304                                                         JUMBO_1K, false),
 305         [RTL_GIGA_MAC_VER_48] =
 306                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2,
 307                                                         JUMBO_1K, false),
 308         [RTL_GIGA_MAC_VER_49] =
 309                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 310                                                         JUMBO_9K, false),
 311         [RTL_GIGA_MAC_VER_50] =
 312                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 313                                                         JUMBO_9K, false),
 314         [RTL_GIGA_MAC_VER_51] =
 315                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 316                                                         JUMBO_9K, false),
 317 };
 318 #undef _R
 319
 320 enum cfg_version {
 321         RTL_CFG_0 = 0x00,
 322         RTL_CFG_1,
 323         RTL_CFG_2
 324 };
 325
 326 static const struct pci_device_id rtl8169_pci_tbl[] = {
 327         { PCI_VDEVICE(REALTEK,  0x2502), RTL_CFG_1 },
 328         { PCI_VDEVICE(REALTEK,  0x2600), RTL_CFG_1 },
 329         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 330         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 331         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
 332         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 333         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 334         { PCI_DEVICE(PCI_VENDOR_ID_NCUBE,       0x8168), 0, 0, RTL_CFG_1 },
 335         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 336         { PCI_VENDOR_ID_DLINK,                  0x4300,
 337                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 338         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 339         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 340         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 341         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 342         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 343                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 344         { 0x0001,                               0x8168,
 345                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 346         {0,},
 347 };
 348
 349 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 350
 351 static int rx_buf_sz = 16383;
 352 static int use_dac = -1;
 353 static struct {
 354         u32 msg_enable;
 355 } debug = { -1 };
 356
 357 enum rtl_registers {
 358         MAC0            = 0,    /* Ethernet hardware address. */
 359         MAC4            = 4,
 360         MAR0            = 8,    /* Multicast filter. */
 361         CounterAddrLow          = 0x10,
 362         CounterAddrHigh         = 0x14,
 363         TxDescStartAddrLow      = 0x20,
 364         TxDescStartAddrHigh     = 0x24,
 365         TxHDescStartAddrLow     = 0x28,
 366         TxHDescStartAddrHigh    = 0x2c,
 367         FLASH           = 0x30,
 368         ERSR            = 0x36,
 369         ChipCmd         = 0x37,
 370         TxPoll          = 0x38,
 371         IntrMask        = 0x3c,
 372         IntrStatus      = 0x3e,
 373
 374         TxConfig        = 0x40,
 375 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 376 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 377
 378         RxConfig        = 0x44,
 379 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 380 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 381 #define RXCFG_FIFO_SHIFT                13
 382                                         /* No threshold before first PCI xfer */
 383 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 384 #define RX_EARLY_OFF                    (1 << 11)
 385 #define RXCFG_DMA_SHIFT                 8
 386                                         /* Unlimited maximum PCI burst. */
 387 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 388
 389         RxMissed        = 0x4c,
 390         Cfg9346         = 0x50,
 391         Config0         = 0x51,
 392         Config1         = 0x52,
 393         Config2         = 0x53,
 394 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 395
 396         Config3         = 0x54,
 397         Config4         = 0x55,
 398         Config5         = 0x56,
 399         MultiIntr       = 0x5c,
 400         PHYAR           = 0x60,
 401         PHYstatus       = 0x6c,
 402         RxMaxSize       = 0xda,
 403         CPlusCmd        = 0xe0,
 404         IntrMitigate    = 0xe2,
 405         RxDescAddrLow   = 0xe4,
 406         RxDescAddrHigh  = 0xe8,
 407         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 408
 409 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 410
 411         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 412
 413 #define TxPacketMax     (8064 >> 7)
 414 #define EarlySize       0x27
 415
 416         FuncEvent       = 0xf0,
 417         FuncEventMask   = 0xf4,
 418         FuncPresetState = 0xf8,
 419         IBCR0           = 0xf8,
 420         IBCR2           = 0xf9,
 421         IBIMR0          = 0xfa,
 422         IBISR0          = 0xfb,
 423         FuncForceEvent  = 0xfc,
 424 };
 425
 426 enum rtl8110_registers {
 427         TBICSR                  = 0x64,
 428         TBI_ANAR                = 0x68,
 429         TBI_LPAR                = 0x6a,
 430 };
 431
 432 enum rtl8168_8101_registers {
 433         CSIDR                   = 0x64,
 434         CSIAR                   = 0x68,
 435 #define CSIAR_FLAG                      0x80000000
 436 #define CSIAR_WRITE_CMD                 0x80000000
 437 #define CSIAR_BYTE_ENABLE               0x0f
 438 #define CSIAR_BYTE_ENABLE_SHIFT         12
 439 #define CSIAR_ADDR_MASK                 0x0fff
 440 #define CSIAR_FUNC_CARD                 0x00000000
 441 #define CSIAR_FUNC_SDIO                 0x00010000
 442 #define CSIAR_FUNC_NIC                  0x00020000
 443 #define CSIAR_FUNC_NIC2                 0x00010000
 444         PMCH                    = 0x6f,
 445         EPHYAR                  = 0x80,
 446 #define EPHYAR_FLAG                     0x80000000
 447 #define EPHYAR_WRITE_CMD                0x80000000
 448 #define EPHYAR_REG_MASK                 0x1f
 449 #define EPHYAR_REG_SHIFT                16
 450 #define EPHYAR_DATA_MASK                0xffff
 451         DLLPR                   = 0xd0,
 452 #define PFM_EN                          (1 << 6)
 453 #define TX_10M_PS_EN                    (1 << 7)
 454         DBG_REG                 = 0xd1,
 455 #define FIX_NAK_1                       (1 << 4)
 456 #define FIX_NAK_2                       (1 << 3)
 457         TWSI                    = 0xd2,
 458         MCU                     = 0xd3,
 459 #define NOW_IS_OOB                      (1 << 7)
 460 #define TX_EMPTY                        (1 << 5)
 461 #define RX_EMPTY                        (1 << 4)
 462 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 463 #define EN_NDP                          (1 << 3)
 464 #define EN_OOB_RESET                    (1 << 2)
 465 #define LINK_LIST_RDY                   (1 << 1)
 466         EFUSEAR                 = 0xdc,
 467 #define EFUSEAR_FLAG                    0x80000000
 468 #define EFUSEAR_WRITE_CMD               0x80000000
 469 #define EFUSEAR_READ_CMD                0x00000000
 470 #define EFUSEAR_REG_MASK                0x03ff
 471 #define EFUSEAR_REG_SHIFT               8
 472 #define EFUSEAR_DATA_MASK               0xff
 473         MISC_1                  = 0xf2,
 474 #define PFM_D3COLD_EN                   (1 << 6)
 475 };
 476
 477 enum rtl8168_registers {
 478         LED_FREQ                = 0x1a,
 479         EEE_LED                 = 0x1b,
 480         ERIDR                   = 0x70,
 481         ERIAR                   = 0x74,
 482 #define ERIAR_FLAG                      0x80000000
 483 #define ERIAR_WRITE_CMD                 0x80000000
 484 #define ERIAR_READ_CMD                  0x00000000
 485 #define ERIAR_ADDR_BYTE_ALIGN           4
 486 #define ERIAR_TYPE_SHIFT                16
 487 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 488 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 489 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 490 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 491 #define ERIAR_MASK_SHIFT                12
 492 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 493 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 494 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 495 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 496 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 497         EPHY_RXER_NUM           = 0x7c,
 498         OCPDR                   = 0xb0, /* OCP GPHY access */
 499 #define OCPDR_WRITE_CMD                 0x80000000
 500 #define OCPDR_READ_CMD                  0x00000000
 501 #define OCPDR_REG_MASK                  0x7f
 502 #define OCPDR_GPHY_REG_SHIFT            16
 503 #define OCPDR_DATA_MASK                 0xffff
 504         OCPAR                   = 0xb4,
 505 #define OCPAR_FLAG                      0x80000000
 506 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 507 #define OCPAR_GPHY_READ_CMD             0x0000f060
 508         GPHY_OCP                = 0xb8,
 509         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 510         MISC                    = 0xf0, /* 8168e only. */
 511 #define TXPLA_RST                       (1 << 29)
 512 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 513 #define PWM_EN                          (1 << 22)
 514 #define RXDV_GATED_EN                   (1 << 19)
 515 #define EARLY_TALLY_EN                  (1 << 16)
 516 };
 517
 518 enum rtl_register_content {
 519         /* InterruptStatusBits */
 520         SYSErr          = 0x8000,
 521         PCSTimeout      = 0x4000,
 522         SWInt           = 0x0100,
 523         TxDescUnavail   = 0x0080,
 524         RxFIFOOver      = 0x0040,
 525         LinkChg         = 0x0020,
 526         RxOverflow      = 0x0010,
 527         TxErr           = 0x0008,
 528         TxOK            = 0x0004,
 529         RxErr           = 0x0002,
 530         RxOK            = 0x0001,
 531
 532         /* RxStatusDesc */
 533         RxBOVF  = (1 << 24),
 534         RxFOVF  = (1 << 23),
 535         RxRWT   = (1 << 22),
 536         RxRES   = (1 << 21),
 537         RxRUNT  = (1 << 20),
 538         RxCRC   = (1 << 19),
 539
 540         /* ChipCmdBits */
 541         StopReq         = 0x80,
 542         CmdReset        = 0x10,
 543         CmdRxEnb        = 0x08,
 544         CmdTxEnb        = 0x04,
 545         RxBufEmpty      = 0x01,
 546
 547         /* TXPoll register p.5 */
 548         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 549         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 550         FSWInt          = 0x01,         /* Forced software interrupt */
 551
 552         /* Cfg9346Bits */
 553         Cfg9346_Lock    = 0x00,
 554         Cfg9346_Unlock  = 0xc0,
 555
 556         /* rx_mode_bits */
 557         AcceptErr       = 0x20,
 558         AcceptRunt      = 0x10,
 559         AcceptBroadcast = 0x08,
 560         AcceptMulticast = 0x04,
 561         AcceptMyPhys    = 0x02,
 562         AcceptAllPhys   = 0x01,
 563 #define RX_CONFIG_ACCEPT_MASK           0x3f
 564
 565         /* TxConfigBits */
 566         TxInterFrameGapShift = 24,
 567         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 568
 569         /* Config1 register p.24 */
 570         LEDS1           = (1 << 7),
 571         LEDS0           = (1 << 6),
 572         Speed_down      = (1 << 4),
 573         MEMMAP          = (1 << 3),
 574         IOMAP           = (1 << 2),
 575         VPD             = (1 << 1),
 576         PMEnable        = (1 << 0),     /* Power Management Enable */
 577
 578         /* Config2 register p. 25 */
 579         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 580         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 581         PCI_Clock_66MHz = 0x01,
 582         PCI_Clock_33MHz = 0x00,
 583
 584         /* Config3 register p.25 */
 585         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 586         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 587         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 588         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 589         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 590
 591         /* Config4 register */
 592         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 593
 594         /* Config5 register p.27 */
 595         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 596         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 597         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 598         Spi_en          = (1 << 3),
 599         LanWake         = (1 << 1),     /* LanWake enable/disable */
 600         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 601         ASPM_en         = (1 << 0),     /* ASPM enable */
 602
 603         /* TBICSR p.28 */
 604         TBIReset        = 0x80000000,
 605         TBILoopback     = 0x40000000,
 606         TBINwEnable     = 0x20000000,
 607         TBINwRestart    = 0x10000000,
 608         TBILinkOk       = 0x02000000,
 609         TBINwComplete   = 0x01000000,
 610
 611         /* CPlusCmd p.31 */
 612         EnableBist      = (1 << 15),    // 8168 8101
 613         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 614         Normal_mode     = (1 << 13),    // unused
 615         Force_half_dup  = (1 << 12),    // 8168 8101
 616         Force_rxflow_en = (1 << 11),    // 8168 8101
 617         Force_txflow_en = (1 << 10),    // 8168 8101
 618         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 619         ASF             = (1 << 8),     // 8168 8101
 620         PktCntrDisable  = (1 << 7),     // 8168 8101
 621         Mac_dbgo_sel    = 0x001c,       // 8168
 622         RxVlan          = (1 << 6),
 623         RxChkSum        = (1 << 5),
 624         PCIDAC          = (1 << 4),
 625         PCIMulRW        = (1 << 3),
 626         INTT_0          = 0x0000,       // 8168
 627         INTT_1          = 0x0001,       // 8168
 628         INTT_2          = 0x0002,       // 8168
 629         INTT_3          = 0x0003,       // 8168
 630
 631         /* rtl8169_PHYstatus */
 632         TBI_Enable      = 0x80,
 633         TxFlowCtrl      = 0x40,
 634         RxFlowCtrl      = 0x20,
 635         _1000bpsF       = 0x10,
 636         _100bps         = 0x08,
 637         _10bps          = 0x04,
 638         LinkStatus      = 0x02,
 639         FullDup         = 0x01,
 640
 641         /* _TBICSRBit */
 642         TBILinkOK       = 0x02000000,
 643
 644         /* ResetCounterCommand */
 645         CounterReset    = 0x1,
 646
 647         /* DumpCounterCommand */
 648         CounterDump     = 0x8,
 649
 650         /* magic enable v2 */
 651         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 652 };
 653
 654 enum rtl_desc_bit {
 655         /* First doubleword. */
 656         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 657         RingEnd         = (1 << 30), /* End of descriptor ring */
 658         FirstFrag       = (1 << 29), /* First segment of a packet */
 659         LastFrag        = (1 << 28), /* Final segment of a packet */
 660 };
 661
 662 /* Generic case. */
 663 enum rtl_tx_desc_bit {
 664         /* First doubleword. */
 665         TD_LSO          = (1 << 27),            /* Large Send Offload */
 666 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 667
 668         /* Second doubleword. */
 669         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 670 };
 671
 672 /* 8169, 8168b and 810x except 8102e. */
 673 enum rtl_tx_desc_bit_0 {
 674         /* First doubleword. */
 675 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 676         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 677         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 678         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 679 };
 680
 681 /* 8102e, 8168c and beyond. */
 682 enum rtl_tx_desc_bit_1 {
 683         /* First doubleword. */
 684         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 685         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 686 #define GTTCPHO_SHIFT                   18
 687 #define GTTCPHO_MAX                     0x7fU
 688
 689         /* Second doubleword. */
 690 #define TCPHO_SHIFT                     18
 691 #define TCPHO_MAX                       0x3ffU
 692 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 693         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 694         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 695         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 696         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 697 };
 698
 699 enum rtl_rx_desc_bit {
 700         /* Rx private */
 701         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 702         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 703
 704 #define RxProtoUDP      (PID1)
 705 #define RxProtoTCP      (PID0)
 706 #define RxProtoIP       (PID1 | PID0)
 707 #define RxProtoMask     RxProtoIP
 708
 709         IPFail          = (1 << 16), /* IP checksum failed */
 710         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 711         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 712         RxVlanTag       = (1 << 16), /* VLAN tag available */
 713 };
 714
 715 #define RsvdMask        0x3fffc000
 716
 717 struct TxDesc {
 718         __le32 opts1;
 719         __le32 opts2;
 720         __le64 addr;
 721 };
 722
 723 struct RxDesc {
 724         __le32 opts1;
 725         __le32 opts2;
 726         __le64 addr;
 727 };
 728
 729 struct ring_info {
 730         struct sk_buff  *skb;
 731         u32             len;
 732         u8              __pad[sizeof(void *) - sizeof(u32)];
 733 };
 734
 735 enum features {
 736         RTL_FEATURE_WOL         = (1 << 0),
 737         RTL_FEATURE_MSI         = (1 << 1),
 738         RTL_FEATURE_GMII        = (1 << 2),
 739 };
 740
 741 struct rtl8169_counters {
 742         __le64  tx_packets;
 743         __le64  rx_packets;
 744         __le64  tx_errors;
 745         __le32  rx_errors;
 746         __le16  rx_missed;
 747         __le16  align_errors;
 748         __le32  tx_one_collision;
 749         __le32  tx_multi_collision;
 750         __le64  rx_unicast;
 751         __le64  rx_broadcast;
 752         __le32  rx_multicast;
 753         __le16  tx_aborted;
 754         __le16  tx_underun;
 755 };
 756
 757 struct rtl8169_tc_offsets {
 758         bool    inited;
 759         __le64  tx_errors;
 760         __le32  tx_multi_collision;
 761         __le16  tx_aborted;
 762 };
 763
 764 enum rtl_flag {
 765         RTL_FLAG_TASK_ENABLED = 0,
 766         RTL_FLAG_TASK_SLOW_PENDING,
 767         RTL_FLAG_TASK_RESET_PENDING,
 768         RTL_FLAG_TASK_PHY_PENDING,
 769         RTL_FLAG_MAX
 770 };
 771
 772 struct rtl8169_stats {
 773         u64                     packets;
 774         u64                     bytes;
 775         struct u64_stats_sync   syncp;
 776 };
 777
 778 struct rtl8169_private {
 779         void __iomem *mmio_addr;        /* memory map physical address */
 780         struct pci_dev *pci_dev;
 781         struct net_device *dev;
 782         struct napi_struct napi;
 783         u32 msg_enable;
 784         u16 txd_version;
 785         u16 mac_version;
 786         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 787         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 788         u32 dirty_tx;
 789         struct rtl8169_stats rx_stats;
 790         struct rtl8169_stats tx_stats;
 791         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 792         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 793         dma_addr_t TxPhyAddr;
 794         dma_addr_t RxPhyAddr;
 795         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 796         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 797         struct timer_list timer;
 798         u16 cp_cmd;
 799
 800         u16 event_slow;
 801
 802         struct mdio_ops {
 803                 void (*write)(struct rtl8169_private *, int, int);
 804                 int (*read)(struct rtl8169_private *, int);
 805         } mdio_ops;
 806
 807         struct pll_power_ops {
 808                 void (*down)(struct rtl8169_private *);
 809                 void (*up)(struct rtl8169_private *);
 810         } pll_power_ops;
 811
 812         struct jumbo_ops {
 813                 void (*enable)(struct rtl8169_private *);
 814                 void (*disable)(struct rtl8169_private *);
 815         } jumbo_ops;
 816
 817         struct csi_ops {
 818                 void (*write)(struct rtl8169_private *, int, int);
 819                 u32 (*read)(struct rtl8169_private *, int);
 820         } csi_ops;
 821
 822         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 823         int (*get_link_ksettings)(struct net_device *,
 824                                   struct ethtool_link_ksettings *);
 825         void (*phy_reset_enable)(struct rtl8169_private *tp);
 826         void (*hw_start)(struct net_device *);
 827         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 828         unsigned int (*link_ok)(void __iomem *);
 829         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 830         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 831
 832         struct {
 833                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 834                 struct mutex mutex;
 835                 struct work_struct work;
 836         } wk;
 837
 838         unsigned features;
 839
 840         struct mii_if_info mii;
 841         dma_addr_t counters_phys_addr;
 842         struct rtl8169_counters *counters;
 843         struct rtl8169_tc_offsets tc_offset;
 844         u32 saved_wolopts;
 845         u32 opts1_mask;
 846
 847         struct rtl_fw {
 848                 const struct firmware *fw;
 849
 850 #define RTL_VER_SIZE            32
 851
 852                 char version[RTL_VER_SIZE];
 853
 854                 struct rtl_fw_phy_action {
 855                         __le32 *code;
 856                         size_t size;
 857                 } phy_action;
 858         } *rtl_fw;
 859 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 860
 861         u32 ocp_base;
 862 };
 863
 864 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 865 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 866 module_param(use_dac, int, 0);
 867 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 868 module_param_named(debug, debug.msg_enable, int, 0);
 869 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 870 MODULE_LICENSE("GPL");
 871 MODULE_VERSION(RTL8169_VERSION);
 872 /*(DEBLOBBED)*/
 873
 874 static void rtl_lock_work(struct rtl8169_private *tp)
 875 {
 876         mutex_lock(&tp->wk.mutex);
 877 }
 878
 879 static void rtl_unlock_work(struct rtl8169_private *tp)
 880 {
 881         mutex_unlock(&tp->wk.mutex);
 882 }
 883
 884 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 885 {
 886         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 887                                            PCI_EXP_DEVCTL_READRQ, force);
 888 }
 889
 890 struct rtl_cond {
 891         bool (*check)(struct rtl8169_private *);
 892         const char *msg;
 893 };
 894
 895 static void rtl_udelay(unsigned int d)
 896 {
 897         udelay(d);
 898 }
 899
 900 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 901                           void (*delay)(unsigned int), unsigned int d, int n,
 902                           bool high)
 903 {
 904         int i;
 905
 906         for (i = 0; i < n; i++) {
 907                 delay(d);
 908                 if (c->check(tp) == high)
 909                         return true;
 910         }
 911         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 912                   c->msg, !high, n, d);
 913         return false;
 914 }
 915
 916 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 917                                       const struct rtl_cond *c,
 918                                       unsigned int d, int n)
 919 {
 920         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 921 }
 922
 923 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 924                                      const struct rtl_cond *c,
 925                                      unsigned int d, int n)
 926 {
 927         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 928 }
 929
 930 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 931                                       const struct rtl_cond *c,
 932                                       unsigned int d, int n)
 933 {
 934         return rtl_loop_wait(tp, c, msleep, d, n, true);
 935 }
 936
 937 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 938                                      const struct rtl_cond *c,
 939                                      unsigned int d, int n)
 940 {
 941         return rtl_loop_wait(tp, c, msleep, d, n, false);
 942 }
 943
 944 #define DECLARE_RTL_COND(name)                          \
 945 static bool name ## _check(struct rtl8169_private *);   \
 946                                                         \
 947 static const struct rtl_cond name = {                   \
 948         .check  = name ## _check,                       \
 949         .msg    = #name                                 \
 950 };                                                      \
 951                                                         \
 952 static bool name ## _check(struct rtl8169_private *tp)
 953
 954 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 955 {
 956         if (reg & 0xffff0001) {
 957                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 958                 return true;
 959         }
 960         return false;
 961 }
 962
 963 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 964 {
 965         void __iomem *ioaddr = tp->mmio_addr;
 966
 967         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
 968 }
 969
 970 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 971 {
 972         void __iomem *ioaddr = tp->mmio_addr;
 973
 974         if (rtl_ocp_reg_failure(tp, reg))
 975                 return;
 976
 977         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 978
 979         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 980 }
 981
 982 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 983 {
 984         void __iomem *ioaddr = tp->mmio_addr;
 985
 986         if (rtl_ocp_reg_failure(tp, reg))
 987                 return 0;
 988
 989         RTL_W32(GPHY_OCP, reg << 15);
 990
 991         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 992                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
 993 }
 994
 995 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 996 {
 997         void __iomem *ioaddr = tp->mmio_addr;
 998
 999         if (rtl_ocp_reg_failure(tp, reg))
1000                 return;
1001
1002         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1003 }
1004
1005 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1006 {
1007         void __iomem *ioaddr = tp->mmio_addr;
1008
1009         if (rtl_ocp_reg_failure(tp, reg))
1010                 return 0;
1011
1012         RTL_W32(OCPDR, reg << 15);
1013
1014         return RTL_R32(OCPDR);
1015 }
1016
1017 #define OCP_STD_PHY_BASE        0xa400
1018
1019 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1020 {
1021         if (reg == 0x1f) {
1022                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1023                 return;
1024         }
1025
1026         if (tp->ocp_base != OCP_STD_PHY_BASE)
1027                 reg -= 0x10;
1028
1029         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1030 }
1031
1032 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1033 {
1034         if (tp->ocp_base != OCP_STD_PHY_BASE)
1035                 reg -= 0x10;
1036
1037         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1038 }
1039
1040 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1041 {
1042         if (reg == 0x1f) {
1043                 tp->ocp_base = value << 4;
1044                 return;
1045         }
1046
1047         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1048 }
1049
1050 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1051 {
1052         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1053 }
1054
1055 DECLARE_RTL_COND(rtl_phyar_cond)
1056 {
1057         void __iomem *ioaddr = tp->mmio_addr;
1058
1059         return RTL_R32(PHYAR) & 0x80000000;
1060 }
1061
1062 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1063 {
1064         void __iomem *ioaddr = tp->mmio_addr;
1065
1066         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1067
1068         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1069         /*
1070          * According to hardware specs a 20us delay is required after write
1071          * complete indication, but before sending next command.
1072          */
1073         udelay(20);
1074 }
1075
1076 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1077 {
1078         void __iomem *ioaddr = tp->mmio_addr;
1079         int value;
1080
1081         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1082
1083         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1084                 RTL_R32(PHYAR) & 0xffff : ~0;
1085
1086         /*
1087          * According to hardware specs a 20us delay is required after read
1088          * complete indication, but before sending next command.
1089          */
1090         udelay(20);
1091
1092         return value;
1093 }
1094
1095 DECLARE_RTL_COND(rtl_ocpar_cond)
1096 {
1097         void __iomem *ioaddr = tp->mmio_addr;
1098
1099         return RTL_R32(OCPAR) & OCPAR_FLAG;
1100 }
1101
1102 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1103 {
1104         void __iomem *ioaddr = tp->mmio_addr;
1105
1106         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1107         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1108         RTL_W32(EPHY_RXER_NUM, 0);
1109
1110         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1111 }
1112
1113 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1114 {
1115         r8168dp_1_mdio_access(tp, reg,
1116                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1117 }
1118
1119 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1120 {
1121         void __iomem *ioaddr = tp->mmio_addr;
1122
1123         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1124
1125         mdelay(1);
1126         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1127         RTL_W32(EPHY_RXER_NUM, 0);
1128
1129         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1130                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1131 }
1132
1133 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1134
1135 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1136 {
1137         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1138 }
1139
1140 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1141 {
1142         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1143 }
1144
1145 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1146 {
1147         void __iomem *ioaddr = tp->mmio_addr;
1148
1149         r8168dp_2_mdio_start(ioaddr);
1150
1151         r8169_mdio_write(tp, reg, value);
1152
1153         r8168dp_2_mdio_stop(ioaddr);
1154 }
1155
1156 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1157 {
1158         void __iomem *ioaddr = tp->mmio_addr;
1159         int value;
1160
1161         r8168dp_2_mdio_start(ioaddr);
1162
1163         value = r8169_mdio_read(tp, reg);
1164
1165         r8168dp_2_mdio_stop(ioaddr);
1166
1167         return value;
1168 }
1169
1170 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1171 {
1172         tp->mdio_ops.write(tp, location, val);
1173 }
1174
1175 static int rtl_readphy(struct rtl8169_private *tp, int location)
1176 {
1177         return tp->mdio_ops.read(tp, location);
1178 }
1179
1180 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1181 {
1182         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1183 }
1184
1185 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1186 {
1187         int val;
1188
1189         val = rtl_readphy(tp, reg_addr);
1190         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1191 }
1192
1193 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1194                            int val)
1195 {
1196         struct rtl8169_private *tp = netdev_priv(dev);
1197
1198         rtl_writephy(tp, location, val);
1199 }
1200
1201 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1202 {
1203         struct rtl8169_private *tp = netdev_priv(dev);
1204
1205         return rtl_readphy(tp, location);
1206 }
1207
1208 DECLARE_RTL_COND(rtl_ephyar_cond)
1209 {
1210         void __iomem *ioaddr = tp->mmio_addr;
1211
1212         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1213 }
1214
1215 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1216 {
1217         void __iomem *ioaddr = tp->mmio_addr;
1218
1219         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1220                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1221
1222         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1223
1224         udelay(10);
1225 }
1226
1227 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1228 {
1229         void __iomem *ioaddr = tp->mmio_addr;
1230
1231         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1232
1233         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1234                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1235 }
1236
1237 DECLARE_RTL_COND(rtl_eriar_cond)
1238 {
1239         void __iomem *ioaddr = tp->mmio_addr;
1240
1241         return RTL_R32(ERIAR) & ERIAR_FLAG;
1242 }
1243
1244 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1245                           u32 val, int type)
1246 {
1247         void __iomem *ioaddr = tp->mmio_addr;
1248
1249         BUG_ON((addr & 3) || (mask == 0));
1250         RTL_W32(ERIDR, val);
1251         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1252
1253         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1254 }
1255
1256 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1257 {
1258         void __iomem *ioaddr = tp->mmio_addr;
1259
1260         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1261
1262         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1263                 RTL_R32(ERIDR) : ~0;
1264 }
1265
1266 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1267                          u32 m, int type)
1268 {
1269         u32 val;
1270
1271         val = rtl_eri_read(tp, addr, type);
1272         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1273 }
1274
1275 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1276 {
1277         void __iomem *ioaddr = tp->mmio_addr;
1278
1279         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1280         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1281                 RTL_R32(OCPDR) : ~0;
1282 }
1283
1284 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1285 {
1286         return rtl_eri_read(tp, reg, ERIAR_OOB);
1287 }
1288
1289 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1290 {
1291         switch (tp->mac_version) {
1292         case RTL_GIGA_MAC_VER_27:
1293         case RTL_GIGA_MAC_VER_28:
1294         case RTL_GIGA_MAC_VER_31:
1295                 return r8168dp_ocp_read(tp, mask, reg);
1296         case RTL_GIGA_MAC_VER_49:
1297         case RTL_GIGA_MAC_VER_50:
1298         case RTL_GIGA_MAC_VER_51:
1299                 return r8168ep_ocp_read(tp, mask, reg);
1300         default:
1301                 BUG();
1302                 return ~0;
1303         }
1304 }
1305
1306 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1307                               u32 data)
1308 {
1309         void __iomem *ioaddr = tp->mmio_addr;
1310
1311         RTL_W32(OCPDR, data);
1312         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1313         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1314 }
1315
1316 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1317                               u32 data)
1318 {
1319         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1320                       data, ERIAR_OOB);
1321 }
1322
1323 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1324 {
1325         switch (tp->mac_version) {
1326         case RTL_GIGA_MAC_VER_27:
1327         case RTL_GIGA_MAC_VER_28:
1328         case RTL_GIGA_MAC_VER_31:
1329                 r8168dp_ocp_write(tp, mask, reg, data);
1330                 break;
1331         case RTL_GIGA_MAC_VER_49:
1332         case RTL_GIGA_MAC_VER_50:
1333         case RTL_GIGA_MAC_VER_51:
1334                 r8168ep_ocp_write(tp, mask, reg, data);
1335                 break;
1336         default:
1337                 BUG();
1338                 break;
1339         }
1340 }
1341
1342 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1343 {
1344         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1345
1346         ocp_write(tp, 0x1, 0x30, 0x00000001);
1347 }
1348
1349 #define OOB_CMD_RESET           0x00
1350 #define OOB_CMD_DRIVER_START    0x05
1351 #define OOB_CMD_DRIVER_STOP     0x06
1352
1353 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1354 {
1355         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1356 }
1357
1358 DECLARE_RTL_COND(rtl_ocp_read_cond)
1359 {
1360         u16 reg;
1361
1362         reg = rtl8168_get_ocp_reg(tp);
1363
1364         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1365 }
1366
1367 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1368 {
1369         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1370 }
1371
1372 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1373 {
1374         void __iomem *ioaddr = tp->mmio_addr;
1375
1376         return RTL_R8(IBISR0) & 0x20;
1377 }
1378
1379 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1380 {
1381         void __iomem *ioaddr = tp->mmio_addr;
1382
1383         RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1384         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1385         RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1386         RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1387 }
1388
1389 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1390 {
1391         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1392         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1393 }
1394
1395 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1396 {
1397         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1398         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1399         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1400 }
1401
1402 static void rtl8168_driver_start(struct rtl8169_private *tp)
1403 {
1404         switch (tp->mac_version) {
1405         case RTL_GIGA_MAC_VER_27:
1406         case RTL_GIGA_MAC_VER_28:
1407         case RTL_GIGA_MAC_VER_31:
1408                 rtl8168dp_driver_start(tp);
1409                 break;
1410         case RTL_GIGA_MAC_VER_49:
1411         case RTL_GIGA_MAC_VER_50:
1412         case RTL_GIGA_MAC_VER_51:
1413                 rtl8168ep_driver_start(tp);
1414                 break;
1415         default:
1416                 BUG();
1417                 break;
1418         }
1419 }
1420
1421 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1422 {
1423         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1424         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1425 }
1426
1427 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1428 {
1429         rtl8168ep_stop_cmac(tp);
1430         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1431         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1432         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1433 }
1434
1435 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1436 {
1437         switch (tp->mac_version) {
1438         case RTL_GIGA_MAC_VER_27:
1439         case RTL_GIGA_MAC_VER_28:
1440         case RTL_GIGA_MAC_VER_31:
1441                 rtl8168dp_driver_stop(tp);
1442                 break;
1443         case RTL_GIGA_MAC_VER_49:
1444         case RTL_GIGA_MAC_VER_50:
1445         case RTL_GIGA_MAC_VER_51:
1446                 rtl8168ep_driver_stop(tp);
1447                 break;
1448         default:
1449                 BUG();
1450                 break;
1451         }
1452 }
1453
1454 static int r8168dp_check_dash(struct rtl8169_private *tp)
1455 {
1456         u16 reg = rtl8168_get_ocp_reg(tp);
1457
1458         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1459 }
1460
1461 static int r8168ep_check_dash(struct rtl8169_private *tp)
1462 {
1463         return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1464 }
1465
1466 static int r8168_check_dash(struct rtl8169_private *tp)
1467 {
1468         switch (tp->mac_version) {
1469         case RTL_GIGA_MAC_VER_27:
1470         case RTL_GIGA_MAC_VER_28:
1471         case RTL_GIGA_MAC_VER_31:
1472                 return r8168dp_check_dash(tp);
1473         case RTL_GIGA_MAC_VER_49:
1474         case RTL_GIGA_MAC_VER_50:
1475         case RTL_GIGA_MAC_VER_51:
1476                 return r8168ep_check_dash(tp);
1477         default:
1478                 return 0;
1479         }
1480 }
1481
1482 struct exgmac_reg {
1483         u16 addr;
1484         u16 mask;
1485         u32 val;
1486 };
1487
1488 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1489                                    const struct exgmac_reg *r, int len)
1490 {
1491         while (len-- > 0) {
1492                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1493                 r++;
1494         }
1495 }
1496
1497 DECLARE_RTL_COND(rtl_efusear_cond)
1498 {
1499         void __iomem *ioaddr = tp->mmio_addr;
1500
1501         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1502 }
1503
1504 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1505 {
1506         void __iomem *ioaddr = tp->mmio_addr;
1507
1508         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1509
1510         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1511                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1512 }
1513
1514 static u16 rtl_get_events(struct rtl8169_private *tp)
1515 {
1516         void __iomem *ioaddr = tp->mmio_addr;
1517
1518         return RTL_R16(IntrStatus);
1519 }
1520
1521 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1522 {
1523         void __iomem *ioaddr = tp->mmio_addr;
1524
1525         RTL_W16(IntrStatus, bits);
1526         mmiowb();
1527 }
1528
1529 static void rtl_irq_disable(struct rtl8169_private *tp)
1530 {
1531         void __iomem *ioaddr = tp->mmio_addr;
1532
1533         RTL_W16(IntrMask, 0);
1534         mmiowb();
1535 }
1536
1537 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1538 {
1539         void __iomem *ioaddr = tp->mmio_addr;
1540
1541         RTL_W16(IntrMask, bits);
1542 }
1543
1544 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1545 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1546 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1547
1548 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1549 {
1550         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1551 }
1552
1553 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1554 {
1555         void __iomem *ioaddr = tp->mmio_addr;
1556
1557         rtl_irq_disable(tp);
1558         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1559         RTL_R8(ChipCmd);
1560 }
1561
1562 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1563 {
1564         void __iomem *ioaddr = tp->mmio_addr;
1565
1566         return RTL_R32(TBICSR) & TBIReset;
1567 }
1568
1569 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1570 {
1571         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1572 }
1573
1574 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1575 {
1576         return RTL_R32(TBICSR) & TBILinkOk;
1577 }
1578
1579 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1580 {
1581         return RTL_R8(PHYstatus) & LinkStatus;
1582 }
1583
1584 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1585 {
1586         void __iomem *ioaddr = tp->mmio_addr;
1587
1588         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1589 }
1590
1591 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1592 {
1593         unsigned int val;
1594
1595         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1596         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1597 }
1598
1599 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1600 {
1601         void __iomem *ioaddr = tp->mmio_addr;
1602         struct net_device *dev = tp->dev;
1603
1604         if (!netif_running(dev))
1605                 return;
1606
1607         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1608             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1609                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1610                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1611                                       ERIAR_EXGMAC);
1612                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1613                                       ERIAR_EXGMAC);
1614                 } else if (RTL_R8(PHYstatus) & _100bps) {
1615                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1616                                       ERIAR_EXGMAC);
1617                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1618                                       ERIAR_EXGMAC);
1619                 } else {
1620                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1621                                       ERIAR_EXGMAC);
1622                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1623                                       ERIAR_EXGMAC);
1624                 }
1625                 /* Reset packet filter */
1626                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1627                              ERIAR_EXGMAC);
1628                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1629                              ERIAR_EXGMAC);
1630         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1631                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1632                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1633                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1634                                       ERIAR_EXGMAC);
1635                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1636                                       ERIAR_EXGMAC);
1637                 } else {
1638                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1639                                       ERIAR_EXGMAC);
1640                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1641                                       ERIAR_EXGMAC);
1642                 }
1643         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1644                 if (RTL_R8(PHYstatus) & _10bps) {
1645                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1646                                       ERIAR_EXGMAC);
1647                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1648                                       ERIAR_EXGMAC);
1649                 } else {
1650                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1651                                       ERIAR_EXGMAC);
1652                 }
1653         }
1654 }
1655
1656 static void __rtl8169_check_link_status(struct net_device *dev,
1657                                         struct rtl8169_private *tp,
1658                                         void __iomem *ioaddr, bool pm)
1659 {
1660         if (tp->link_ok(ioaddr)) {
1661                 rtl_link_chg_patch(tp);
1662                 /* This is to cancel a scheduled suspend if there's one. */
1663                 if (pm)
1664                         pm_request_resume(&tp->pci_dev->dev);
1665                 netif_carrier_on(dev);
1666                 if (net_ratelimit())
1667                         netif_info(tp, ifup, dev, "link up\n");
1668         } else {
1669                 netif_carrier_off(dev);
1670                 netif_info(tp, ifdown, dev, "link down\n");
1671                 if (pm)
1672                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1673         }
1674 }
1675
1676 static void rtl8169_check_link_status(struct net_device *dev,
1677                                       struct rtl8169_private *tp,
1678                                       void __iomem *ioaddr)
1679 {
1680         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1681 }
1682
1683 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1684
1685 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1686 {
1687         void __iomem *ioaddr = tp->mmio_addr;
1688         u8 options;
1689         u32 wolopts = 0;
1690
1691         options = RTL_R8(Config1);
1692         if (!(options & PMEnable))
1693                 return 0;
1694
1695         options = RTL_R8(Config3);
1696         if (options & LinkUp)
1697                 wolopts |= WAKE_PHY;
1698         switch (tp->mac_version) {
1699         case RTL_GIGA_MAC_VER_34:
1700         case RTL_GIGA_MAC_VER_35:
1701         case RTL_GIGA_MAC_VER_36:
1702         case RTL_GIGA_MAC_VER_37:
1703         case RTL_GIGA_MAC_VER_38:
1704         case RTL_GIGA_MAC_VER_40:
1705         case RTL_GIGA_MAC_VER_41:
1706         case RTL_GIGA_MAC_VER_42:
1707         case RTL_GIGA_MAC_VER_43:
1708         case RTL_GIGA_MAC_VER_44:
1709         case RTL_GIGA_MAC_VER_45:
1710         case RTL_GIGA_MAC_VER_46:
1711         case RTL_GIGA_MAC_VER_47:
1712         case RTL_GIGA_MAC_VER_48:
1713         case RTL_GIGA_MAC_VER_49:
1714         case RTL_GIGA_MAC_VER_50:
1715         case RTL_GIGA_MAC_VER_51:
1716                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1717                         wolopts |= WAKE_MAGIC;
1718                 break;
1719         default:
1720                 if (options & MagicPacket)
1721                         wolopts |= WAKE_MAGIC;
1722                 break;
1723         }
1724
1725         options = RTL_R8(Config5);
1726         if (options & UWF)
1727                 wolopts |= WAKE_UCAST;
1728         if (options & BWF)
1729                 wolopts |= WAKE_BCAST;
1730         if (options & MWF)
1731                 wolopts |= WAKE_MCAST;
1732
1733         return wolopts;
1734 }
1735
1736 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1737 {
1738         struct rtl8169_private *tp = netdev_priv(dev);
1739         struct device *d = &tp->pci_dev->dev;
1740
1741         pm_runtime_get_noresume(d);
1742
1743         rtl_lock_work(tp);
1744
1745         wol->supported = WAKE_ANY;
1746         if (pm_runtime_active(d))
1747                 wol->wolopts = __rtl8169_get_wol(tp);
1748         else
1749                 wol->wolopts = tp->saved_wolopts;
1750
1751         rtl_unlock_work(tp);
1752
1753         pm_runtime_put_noidle(d);
1754 }
1755
1756 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1757 {
1758         void __iomem *ioaddr = tp->mmio_addr;
1759         unsigned int i, tmp;
1760         static const struct {
1761                 u32 opt;
1762                 u16 reg;
1763                 u8  mask;
1764         } cfg[] = {
1765                 { WAKE_PHY,   Config3, LinkUp },
1766                 { WAKE_UCAST, Config5, UWF },
1767                 { WAKE_BCAST, Config5, BWF },
1768                 { WAKE_MCAST, Config5, MWF },
1769                 { WAKE_ANY,   Config5, LanWake },
1770                 { WAKE_MAGIC, Config3, MagicPacket }
1771         };
1772         u8 options;
1773
1774         RTL_W8(Cfg9346, Cfg9346_Unlock);
1775
1776         switch (tp->mac_version) {
1777         case RTL_GIGA_MAC_VER_34:
1778         case RTL_GIGA_MAC_VER_35:
1779         case RTL_GIGA_MAC_VER_36:
1780         case RTL_GIGA_MAC_VER_37:
1781         case RTL_GIGA_MAC_VER_38:
1782         case RTL_GIGA_MAC_VER_40:
1783         case RTL_GIGA_MAC_VER_41:
1784         case RTL_GIGA_MAC_VER_42:
1785         case RTL_GIGA_MAC_VER_43:
1786         case RTL_GIGA_MAC_VER_44:
1787         case RTL_GIGA_MAC_VER_45:
1788         case RTL_GIGA_MAC_VER_46:
1789         case RTL_GIGA_MAC_VER_47:
1790         case RTL_GIGA_MAC_VER_48:
1791         case RTL_GIGA_MAC_VER_49:
1792         case RTL_GIGA_MAC_VER_50:
1793         case RTL_GIGA_MAC_VER_51:
1794                 tmp = ARRAY_SIZE(cfg) - 1;
1795                 if (wolopts & WAKE_MAGIC)
1796                         rtl_w0w1_eri(tp,
1797                                      0x0dc,
1798                                      ERIAR_MASK_0100,
1799                                      MagicPacket_v2,
1800                                      0x0000,
1801                                      ERIAR_EXGMAC);
1802                 else
1803                         rtl_w0w1_eri(tp,
1804                                      0x0dc,
1805                                      ERIAR_MASK_0100,
1806                                      0x0000,
1807                                      MagicPacket_v2,
1808                                      ERIAR_EXGMAC);
1809                 break;
1810         default:
1811                 tmp = ARRAY_SIZE(cfg);
1812                 break;
1813         }
1814
1815         for (i = 0; i < tmp; i++) {
1816                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1817                 if (wolopts & cfg[i].opt)
1818                         options |= cfg[i].mask;
1819                 RTL_W8(cfg[i].reg, options);
1820         }
1821
1822         switch (tp->mac_version) {
1823         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1824                 options = RTL_R8(Config1) & ~PMEnable;
1825                 if (wolopts)
1826                         options |= PMEnable;
1827                 RTL_W8(Config1, options);
1828                 break;
1829         default:
1830                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1831                 if (wolopts)
1832                         options |= PME_SIGNAL;
1833                 RTL_W8(Config2, options);
1834                 break;
1835         }
1836
1837         RTL_W8(Cfg9346, Cfg9346_Lock);
1838 }
1839
1840 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1841 {
1842         struct rtl8169_private *tp = netdev_priv(dev);
1843         struct device *d = &tp->pci_dev->dev;
1844
1845         pm_runtime_get_noresume(d);
1846
1847         rtl_lock_work(tp);
1848
1849         if (wol->wolopts)
1850                 tp->features |= RTL_FEATURE_WOL;
1851         else
1852                 tp->features &= ~RTL_FEATURE_WOL;
1853         if (pm_runtime_active(d))
1854                 __rtl8169_set_wol(tp, wol->wolopts);
1855         else
1856                 tp->saved_wolopts = wol->wolopts;
1857
1858         rtl_unlock_work(tp);
1859
1860         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1861
1862         pm_runtime_put_noidle(d);
1863
1864         return 0;
1865 }
1866
1867 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1868 {
1869         return rtl_chip_infos[tp->mac_version].fw_name;
1870 }
1871
1872 static void rtl8169_get_drvinfo(struct net_device *dev,
1873                                 struct ethtool_drvinfo *info)
1874 {
1875         struct rtl8169_private *tp = netdev_priv(dev);
1876         struct rtl_fw *rtl_fw = tp->rtl_fw;
1877
1878         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1879         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1880         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1881         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1882         if (!IS_ERR_OR_NULL(rtl_fw))
1883                 strlcpy(info->fw_version, rtl_fw->version,
1884                         sizeof(info->fw_version));
1885 }
1886
1887 static int rtl8169_get_regs_len(struct net_device *dev)
1888 {
1889         return R8169_REGS_SIZE;
1890 }
1891
1892 static int rtl8169_set_speed_tbi(struct net_device *dev,
1893                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1894 {
1895         struct rtl8169_private *tp = netdev_priv(dev);
1896         void __iomem *ioaddr = tp->mmio_addr;
1897         int ret = 0;
1898         u32 reg;
1899
1900         reg = RTL_R32(TBICSR);
1901         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1902             (duplex == DUPLEX_FULL)) {
1903                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1904         } else if (autoneg == AUTONEG_ENABLE)
1905                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1906         else {
1907                 netif_warn(tp, link, dev,
1908                            "incorrect speed setting refused in TBI mode\n");
1909                 ret = -EOPNOTSUPP;
1910         }
1911
1912         return ret;
1913 }
1914
1915 static int rtl8169_set_speed_xmii(struct net_device *dev,
1916                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1917 {
1918         struct rtl8169_private *tp = netdev_priv(dev);
1919         int giga_ctrl, bmcr;
1920         int rc = -EINVAL;
1921
1922         rtl_writephy(tp, 0x1f, 0x0000);
1923
1924         if (autoneg == AUTONEG_ENABLE) {
1925                 int auto_nego;
1926
1927                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1928                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1929                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1930
1931                 if (adv & ADVERTISED_10baseT_Half)
1932                         auto_nego |= ADVERTISE_10HALF;
1933                 if (adv & ADVERTISED_10baseT_Full)
1934                         auto_nego |= ADVERTISE_10FULL;
1935                 if (adv & ADVERTISED_100baseT_Half)
1936                         auto_nego |= ADVERTISE_100HALF;
1937                 if (adv & ADVERTISED_100baseT_Full)
1938                         auto_nego |= ADVERTISE_100FULL;
1939
1940                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1941
1942                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1943                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1944
1945                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1946                 if (tp->mii.supports_gmii) {
1947                         if (adv & ADVERTISED_1000baseT_Half)
1948                                 giga_ctrl |= ADVERTISE_1000HALF;
1949                         if (adv & ADVERTISED_1000baseT_Full)
1950                                 giga_ctrl |= ADVERTISE_1000FULL;
1951                 } else if (adv & (ADVERTISED_1000baseT_Half |
1952                                   ADVERTISED_1000baseT_Full)) {
1953                         netif_info(tp, link, dev,
1954                                    "PHY does not support 1000Mbps\n");
1955                         goto out;
1956                 }
1957
1958                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1959
1960                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1961                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1962         } else {
1963                 giga_ctrl = 0;
1964
1965                 if (speed == SPEED_10)
1966                         bmcr = 0;
1967                 else if (speed == SPEED_100)
1968                         bmcr = BMCR_SPEED100;
1969                 else
1970                         goto out;
1971
1972                 if (duplex == DUPLEX_FULL)
1973                         bmcr |= BMCR_FULLDPLX;
1974         }
1975
1976         rtl_writephy(tp, MII_BMCR, bmcr);
1977
1978         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1979             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1980                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1981                         rtl_writephy(tp, 0x17, 0x2138);
1982                         rtl_writephy(tp, 0x0e, 0x0260);
1983                 } else {
1984                         rtl_writephy(tp, 0x17, 0x2108);
1985                         rtl_writephy(tp, 0x0e, 0x0000);
1986                 }
1987         }
1988
1989         rc = 0;
1990 out:
1991         return rc;
1992 }
1993
1994 static int rtl8169_set_speed(struct net_device *dev,
1995                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1996 {
1997         struct rtl8169_private *tp = netdev_priv(dev);
1998         int ret;
1999
2000         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
2001         if (ret < 0)
2002                 goto out;
2003
2004         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
2005             (advertising & ADVERTISED_1000baseT_Full) &&
2006             !pci_is_pcie(tp->pci_dev)) {
2007                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
2008         }
2009 out:
2010         return ret;
2011 }
2012
2013 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2014         netdev_features_t features)
2015 {
2016         struct rtl8169_private *tp = netdev_priv(dev);
2017
2018         if (dev->mtu > TD_MSS_MAX)
2019                 features &= ~NETIF_F_ALL_TSO;
2020
2021         if (dev->mtu > JUMBO_1K &&
2022             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2023                 features &= ~NETIF_F_IP_CSUM;
2024
2025         return features;
2026 }
2027
2028 static void __rtl8169_set_features(struct net_device *dev,
2029                                    netdev_features_t features)
2030 {
2031         struct rtl8169_private *tp = netdev_priv(dev);
2032         void __iomem *ioaddr = tp->mmio_addr;
2033         u32 rx_config;
2034
2035         rx_config = RTL_R32(RxConfig);
2036         if (features & NETIF_F_RXALL)
2037                 rx_config |= (AcceptErr | AcceptRunt);
2038         else
2039                 rx_config &= ~(AcceptErr | AcceptRunt);
2040
2041         RTL_W32(RxConfig, rx_config);
2042
2043         if (features & NETIF_F_RXCSUM)
2044                 tp->cp_cmd |= RxChkSum;
2045         else
2046                 tp->cp_cmd &= ~RxChkSum;
2047
2048         if (features & NETIF_F_HW_VLAN_CTAG_RX)
2049                 tp->cp_cmd |= RxVlan;
2050         else
2051                 tp->cp_cmd &= ~RxVlan;
2052
2053         tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2054
2055         RTL_W16(CPlusCmd, tp->cp_cmd);
2056         RTL_R16(CPlusCmd);
2057 }
2058
2059 static int rtl8169_set_features(struct net_device *dev,
2060                                 netdev_features_t features)
2061 {
2062         struct rtl8169_private *tp = netdev_priv(dev);
2063
2064         features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2065
2066         rtl_lock_work(tp);
2067         if (features ^ dev->features)
2068                 __rtl8169_set_features(dev, features);
2069         rtl_unlock_work(tp);
2070
2071         return 0;
2072 }
2073
2074
2075 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2076 {
2077         return (skb_vlan_tag_present(skb)) ?
2078                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2079 }
2080
2081 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2082 {
2083         u32 opts2 = le32_to_cpu(desc->opts2);
2084
2085         if (opts2 & RxVlanTag)
2086                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2087 }
2088
2089 static int rtl8169_get_link_ksettings_tbi(struct net_device *dev,
2090                                           struct ethtool_link_ksettings *cmd)
2091 {
2092         struct rtl8169_private *tp = netdev_priv(dev);
2093         void __iomem *ioaddr = tp->mmio_addr;
2094         u32 status;
2095         u32 supported, advertising;
2096
2097         supported =
2098                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2099         cmd->base.port = PORT_FIBRE;
2100
2101         status = RTL_R32(TBICSR);
2102         advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
2103         cmd->base.autoneg = !!(status & TBINwEnable);
2104
2105         cmd->base.speed = SPEED_1000;
2106         cmd->base.duplex = DUPLEX_FULL; /* Always set */
2107
2108         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2109                                                 supported);
2110         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2111                                                 advertising);
2112
2113         return 0;
2114 }
2115
2116 static int rtl8169_get_link_ksettings_xmii(struct net_device *dev,
2117                                            struct ethtool_link_ksettings *cmd)
2118 {
2119         struct rtl8169_private *tp = netdev_priv(dev);
2120
2121         mii_ethtool_get_link_ksettings(&tp->mii, cmd);
2122
2123         return 0;
2124 }
2125
2126 static int rtl8169_get_link_ksettings(struct net_device *dev,
2127                                       struct ethtool_link_ksettings *cmd)
2128 {
2129         struct rtl8169_private *tp = netdev_priv(dev);
2130         int rc;
2131
2132         rtl_lock_work(tp);
2133         rc = tp->get_link_ksettings(dev, cmd);
2134         rtl_unlock_work(tp);
2135
2136         return rc;
2137 }
2138
2139 static int rtl8169_set_link_ksettings(struct net_device *dev,
2140                                       const struct ethtool_link_ksettings *cmd)
2141 {
2142         struct rtl8169_private *tp = netdev_priv(dev);
2143         int rc;
2144         u32 advertising;
2145
2146         if (!ethtool_convert_link_mode_to_legacy_u32(&advertising,
2147             cmd->link_modes.advertising))
2148                 return -EINVAL;
2149
2150         del_timer_sync(&tp->timer);
2151
2152         rtl_lock_work(tp);
2153         rc = rtl8169_set_speed(dev, cmd->base.autoneg, cmd->base.speed,
2154                                cmd->base.duplex, advertising);
2155         rtl_unlock_work(tp);
2156
2157         return rc;
2158 }
2159
2160 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2161                              void *p)
2162 {
2163         struct rtl8169_private *tp = netdev_priv(dev);
2164         u32 __iomem *data = tp->mmio_addr;
2165         u32 *dw = p;
2166         int i;
2167
2168         rtl_lock_work(tp);
2169         for (i = 0; i < R8169_REGS_SIZE; i += 4)
2170                 memcpy_fromio(dw++, data++, 4);
2171         rtl_unlock_work(tp);
2172 }
2173
2174 static u32 rtl8169_get_msglevel(struct net_device *dev)
2175 {
2176         struct rtl8169_private *tp = netdev_priv(dev);
2177
2178         return tp->msg_enable;
2179 }
2180
2181 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2182 {
2183         struct rtl8169_private *tp = netdev_priv(dev);
2184
2185         tp->msg_enable = value;
2186 }
2187
2188 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2189         "tx_packets",
2190         "rx_packets",
2191         "tx_errors",
2192         "rx_errors",
2193         "rx_missed",
2194         "align_errors",
2195         "tx_single_collisions",
2196         "tx_multi_collisions",
2197         "unicast",
2198         "broadcast",
2199         "multicast",
2200         "tx_aborted",
2201         "tx_underrun",
2202 };
2203
2204 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2205 {
2206         switch (sset) {
2207         case ETH_SS_STATS:
2208                 return ARRAY_SIZE(rtl8169_gstrings);
2209         default:
2210                 return -EOPNOTSUPP;
2211         }
2212 }
2213
2214 DECLARE_RTL_COND(rtl_counters_cond)
2215 {
2216         void __iomem *ioaddr = tp->mmio_addr;
2217
2218         return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
2219 }
2220
2221 static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
2222 {
2223         struct rtl8169_private *tp = netdev_priv(dev);
2224         void __iomem *ioaddr = tp->mmio_addr;
2225         dma_addr_t paddr = tp->counters_phys_addr;
2226         u32 cmd;
2227
2228         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2229         RTL_R32(CounterAddrHigh);
2230         cmd = (u64)paddr & DMA_BIT_MASK(32);
2231         RTL_W32(CounterAddrLow, cmd);
2232         RTL_W32(CounterAddrLow, cmd | counter_cmd);
2233
2234         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2235 }
2236
2237 static bool rtl8169_reset_counters(struct net_device *dev)
2238 {
2239         struct rtl8169_private *tp = netdev_priv(dev);
2240
2241         /*
2242          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2243          * tally counters.
2244          */
2245         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2246                 return true;
2247
2248         return rtl8169_do_counters(dev, CounterReset);
2249 }
2250
2251 static bool rtl8169_update_counters(struct net_device *dev)
2252 {
2253         struct rtl8169_private *tp = netdev_priv(dev);
2254         void __iomem *ioaddr = tp->mmio_addr;
2255
2256         /*
2257          * Some chips are unable to dump tally counters when the receiver
2258          * is disabled.
2259          */
2260         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2261                 return true;
2262
2263         return rtl8169_do_counters(dev, CounterDump);
2264 }
2265
2266 static bool rtl8169_init_counter_offsets(struct net_device *dev)
2267 {
2268         struct rtl8169_private *tp = netdev_priv(dev);
2269         struct rtl8169_counters *counters = tp->counters;
2270         bool ret = false;
2271
2272         /*
2273          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
2274          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2275          * reset by a power cycle, while the counter values collected by the
2276          * driver are reset at every driver unload/load cycle.
2277          *
2278          * To make sure the HW values returned by @get_stats64 match the SW
2279          * values, we collect the initial values at first open(*) and use them
2280          * as offsets to normalize the values returned by @get_stats64.
2281          *
2282          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2283          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2284          * set at open time by rtl_hw_start.
2285          */
2286
2287         if (tp->tc_offset.inited)
2288                 return true;
2289
2290         /* If both, reset and update fail, propagate to caller. */
2291         if (rtl8169_reset_counters(dev))
2292                 ret = true;
2293
2294         if (rtl8169_update_counters(dev))
2295                 ret = true;
2296
2297         tp->tc_offset.tx_errors = counters->tx_errors;
2298         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2299         tp->tc_offset.tx_aborted = counters->tx_aborted;
2300         tp->tc_offset.inited = true;
2301
2302         return ret;
2303 }
2304
2305 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2306                                       struct ethtool_stats *stats, u64 *data)
2307 {
2308         struct rtl8169_private *tp = netdev_priv(dev);
2309         struct device *d = &tp->pci_dev->dev;
2310         struct rtl8169_counters *counters = tp->counters;
2311
2312         ASSERT_RTNL();
2313
2314         pm_runtime_get_noresume(d);
2315
2316         if (pm_runtime_active(d))
2317                 rtl8169_update_counters(dev);
2318
2319         pm_runtime_put_noidle(d);
2320
2321         data[0] = le64_to_cpu(counters->tx_packets);
2322         data[1] = le64_to_cpu(counters->rx_packets);
2323         data[2] = le64_to_cpu(counters->tx_errors);
2324         data[3] = le32_to_cpu(counters->rx_errors);
2325         data[4] = le16_to_cpu(counters->rx_missed);
2326         data[5] = le16_to_cpu(counters->align_errors);
2327         data[6] = le32_to_cpu(counters->tx_one_collision);
2328         data[7] = le32_to_cpu(counters->tx_multi_collision);
2329         data[8] = le64_to_cpu(counters->rx_unicast);
2330         data[9] = le64_to_cpu(counters->rx_broadcast);
2331         data[10] = le32_to_cpu(counters->rx_multicast);
2332         data[11] = le16_to_cpu(counters->tx_aborted);
2333         data[12] = le16_to_cpu(counters->tx_underun);
2334 }
2335
2336 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2337 {
2338         switch(stringset) {
2339         case ETH_SS_STATS:
2340                 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
2341                 break;
2342         }
2343 }
2344
2345 static int rtl8169_nway_reset(struct net_device *dev)
2346 {
2347         struct rtl8169_private *tp = netdev_priv(dev);
2348
2349         return mii_nway_restart(&tp->mii);
2350 }
2351
2352 static const struct ethtool_ops rtl8169_ethtool_ops = {
2353         .get_drvinfo            = rtl8169_get_drvinfo,
2354         .get_regs_len           = rtl8169_get_regs_len,
2355         .get_link               = ethtool_op_get_link,
2356         .get_msglevel           = rtl8169_get_msglevel,
2357         .set_msglevel           = rtl8169_set_msglevel,
2358         .get_regs               = rtl8169_get_regs,
2359         .get_wol                = rtl8169_get_wol,
2360         .set_wol                = rtl8169_set_wol,
2361         .get_strings            = rtl8169_get_strings,
2362         .get_sset_count         = rtl8169_get_sset_count,
2363         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2364         .get_ts_info            = ethtool_op_get_ts_info,
2365         .nway_reset             = rtl8169_nway_reset,
2366         .get_link_ksettings     = rtl8169_get_link_ksettings,
2367         .set_link_ksettings     = rtl8169_set_link_ksettings,
2368 };
2369
2370 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2371                                     struct net_device *dev, u8 default_version)
2372 {
2373         void __iomem *ioaddr = tp->mmio_addr;
2374         /*
2375          * The driver currently handles the 8168Bf and the 8168Be identically
2376          * but they can be identified more specifically through the test below
2377          * if needed:
2378          *
2379          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2380          *
2381          * Same thing for the 8101Eb and the 8101Ec:
2382          *
2383          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2384          */
2385         static const struct rtl_mac_info {
2386                 u32 mask;
2387                 u32 val;
2388                 int mac_version;
2389         } mac_info[] = {
2390                 /* 8168EP family. */
2391                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2392                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2393                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2394
2395                 /* 8168H family. */
2396                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2397                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2398
2399                 /* 8168G family. */
2400                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2401                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2402                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2403                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2404
2405                 /* 8168F family. */
2406                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2407                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2408                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2409
2410                 /* 8168E family. */
2411                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2412                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2413                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2414                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2415
2416                 /* 8168D family. */
2417                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2418                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2419                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2420
2421                 /* 8168DP family. */
2422                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2423                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2424                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2425
2426                 /* 8168C family. */
2427                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2428                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2429                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2430                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2431                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2432                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2433                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2434                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2435                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2436
2437                 /* 8168B family. */
2438                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2439                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2440                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2441                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2442
2443                 /* 8101 family. */
2444                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2445                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2446                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2447                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2448                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2449                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2450                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2451                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2452                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2453                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2454                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2455                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2456                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2457                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2458                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2459                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2460                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2461                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2462                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2463                 /* FIXME: where did these entries come from ? -- FR */
2464                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2465                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2466
2467                 /* 8110 family. */
2468                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2469                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2470                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2471                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2472                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2473                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2474
2475                 /* Catch-all */
2476                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2477         };
2478         const struct rtl_mac_info *p = mac_info;
2479         u32 reg;
2480
2481         reg = RTL_R32(TxConfig);
2482         while ((reg & p->mask) != p->val)
2483                 p++;
2484         tp->mac_version = p->mac_version;
2485
2486         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2487                 netif_notice(tp, probe, dev,
2488                              "unknown MAC, using family default\n");
2489                 tp->mac_version = default_version;
2490         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2491                 tp->mac_version = tp->mii.supports_gmii ?
2492                                   RTL_GIGA_MAC_VER_42 :
2493                                   RTL_GIGA_MAC_VER_43;
2494         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2495                 tp->mac_version = tp->mii.supports_gmii ?
2496                                   RTL_GIGA_MAC_VER_45 :
2497                                   RTL_GIGA_MAC_VER_47;
2498         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2499                 tp->mac_version = tp->mii.supports_gmii ?
2500                                   RTL_GIGA_MAC_VER_46 :
2501                                   RTL_GIGA_MAC_VER_48;
2502         }
2503 }
2504
2505 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2506 {
2507         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2508 }
2509
2510 struct phy_reg {
2511         u16 reg;
2512         u16 val;
2513 };
2514
2515 static void rtl_writephy_batch(struct rtl8169_private *tp,
2516                                const struct phy_reg *regs, int len)
2517 {
2518         while (len-- > 0) {
2519                 rtl_writephy(tp, regs->reg, regs->val);
2520                 regs++;
2521         }
2522 }
2523
2524 #define PHY_READ                0x00000000
2525 #define PHY_DATA_OR             0x10000000
2526 #define PHY_DATA_AND            0x20000000
2527 #define PHY_BJMPN               0x30000000
2528 #define PHY_MDIO_CHG            0x40000000
2529 #define PHY_CLEAR_READCOUNT     0x70000000
2530 #define PHY_WRITE               0x80000000
2531 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2532 #define PHY_COMP_EQ_SKIPN       0xa0000000
2533 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2534 #define PHY_WRITE_PREVIOUS      0xc0000000
2535 #define PHY_SKIPN               0xd0000000
2536 #define PHY_DELAY_MS            0xe0000000
2537
2538 struct fw_info {
2539         u32     magic;
2540         char    version[RTL_VER_SIZE];
2541         __le32  fw_start;
2542         __le32  fw_len;
2543         u8      chksum;
2544 } __packed;
2545
2546 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2547
2548 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2549 {
2550         const struct firmware *fw = rtl_fw->fw;
2551         struct fw_info *fw_info = (struct fw_info *)fw->data;
2552         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2553         char *version = rtl_fw->version;
2554         bool rc = false;
2555
2556         if (fw->size < FW_OPCODE_SIZE)
2557                 goto out;
2558
2559         if (!fw_info->magic) {
2560                 size_t i, size, start;
2561                 u8 checksum = 0;
2562
2563                 if (fw->size < sizeof(*fw_info))
2564                         goto out;
2565
2566                 for (i = 0; i < fw->size; i++)
2567                         checksum += fw->data[i];
2568                 if (checksum != 0)
2569                         goto out;
2570
2571                 start = le32_to_cpu(fw_info->fw_start);
2572                 if (start > fw->size)
2573                         goto out;
2574
2575                 size = le32_to_cpu(fw_info->fw_len);
2576                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2577                         goto out;
2578
2579                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2580
2581                 pa->code = (__le32 *)(fw->data + start);
2582                 pa->size = size;
2583         } else {
2584                 if (fw->size % FW_OPCODE_SIZE)
2585                         goto out;
2586
2587                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2588
2589                 pa->code = (__le32 *)fw->data;
2590                 pa->size = fw->size / FW_OPCODE_SIZE;
2591         }
2592         version[RTL_VER_SIZE - 1] = 0;
2593
2594         rc = true;
2595 out:
2596         return rc;
2597 }
2598
2599 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2600                            struct rtl_fw_phy_action *pa)
2601 {
2602         bool rc = false;
2603         size_t index;
2604
2605         for (index = 0; index < pa->size; index++) {
2606                 u32 action = le32_to_cpu(pa->code[index]);
2607                 u32 regno = (action & 0x0fff0000) >> 16;
2608
2609                 switch(action & 0xf0000000) {
2610                 case PHY_READ:
2611                 case PHY_DATA_OR:
2612                 case PHY_DATA_AND:
2613                 case PHY_MDIO_CHG:
2614                 case PHY_CLEAR_READCOUNT:
2615                 case PHY_WRITE:
2616                 case PHY_WRITE_PREVIOUS:
2617                 case PHY_DELAY_MS:
2618                         break;
2619
2620                 case PHY_BJMPN:
2621                         if (regno > index) {
2622                                 netif_err(tp, ifup, tp->dev,
2623                                           "Out of range of firmware\n");
2624                                 goto out;
2625                         }
2626                         break;
2627                 case PHY_READCOUNT_EQ_SKIP:
2628                         if (index + 2 >= pa->size) {
2629                                 netif_err(tp, ifup, tp->dev,
2630                                           "Out of range of firmware\n");
2631                                 goto out;
2632                         }
2633                         break;
2634                 case PHY_COMP_EQ_SKIPN:
2635                 case PHY_COMP_NEQ_SKIPN:
2636                 case PHY_SKIPN:
2637                         if (index + 1 + regno >= pa->size) {
2638                                 netif_err(tp, ifup, tp->dev,
2639                                           "Out of range of firmware\n");
2640                                 goto out;
2641                         }
2642                         break;
2643
2644                 default:
2645                         netif_err(tp, ifup, tp->dev,
2646                                   "Invalid action 0x%08x\n", action);
2647                         goto out;
2648                 }
2649         }
2650         rc = true;
2651 out:
2652         return rc;
2653 }
2654
2655 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2656 {
2657         struct net_device *dev = tp->dev;
2658         int rc = -EINVAL;
2659
2660         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2661                 netif_err(tp, ifup, dev, "invalid firmware\n");
2662                 goto out;
2663         }
2664
2665         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2666                 rc = 0;
2667 out:
2668         return rc;
2669 }
2670
2671 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2672 {
2673         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2674         struct mdio_ops org, *ops = &tp->mdio_ops;
2675         u32 predata, count;
2676         size_t index;
2677
2678         predata = count = 0;
2679         org.write = ops->write;
2680         org.read = ops->read;
2681
2682         for (index = 0; index < pa->size; ) {
2683                 u32 action = le32_to_cpu(pa->code[index]);
2684                 u32 data = action & 0x0000ffff;
2685                 u32 regno = (action & 0x0fff0000) >> 16;
2686
2687                 if (!action)
2688                         break;
2689
2690                 switch(action & 0xf0000000) {
2691                 case PHY_READ:
2692                         predata = rtl_readphy(tp, regno);
2693                         count++;
2694                         index++;
2695                         break;
2696                 case PHY_DATA_OR:
2697                         predata |= data;
2698                         index++;
2699                         break;
2700                 case PHY_DATA_AND:
2701                         predata &= data;
2702                         index++;
2703                         break;
2704                 case PHY_BJMPN:
2705                         index -= regno;
2706                         break;
2707                 case PHY_MDIO_CHG:
2708                         if (data == 0) {
2709                                 ops->write = org.write;
2710                                 ops->read = org.read;
2711                         } else if (data == 1) {
2712                                 ops->write = mac_mcu_write;
2713                                 ops->read = mac_mcu_read;
2714                         }
2715
2716                         index++;
2717                         break;
2718                 case PHY_CLEAR_READCOUNT:
2719                         count = 0;
2720                         index++;
2721                         break;
2722                 case PHY_WRITE:
2723                         rtl_writephy(tp, regno, data);
2724                         index++;
2725                         break;
2726                 case PHY_READCOUNT_EQ_SKIP:
2727                         index += (count == data) ? 2 : 1;
2728                         break;
2729                 case PHY_COMP_EQ_SKIPN:
2730                         if (predata == data)
2731                                 index += regno;
2732                         index++;
2733                         break;
2734                 case PHY_COMP_NEQ_SKIPN:
2735                         if (predata != data)
2736                                 index += regno;
2737                         index++;
2738                         break;
2739                 case PHY_WRITE_PREVIOUS:
2740                         rtl_writephy(tp, regno, predata);
2741                         index++;
2742                         break;
2743                 case PHY_SKIPN:
2744                         index += regno + 1;
2745                         break;
2746                 case PHY_DELAY_MS:
2747                         mdelay(data);
2748                         index++;
2749                         break;
2750
2751                 default:
2752                         BUG();
2753                 }
2754         }
2755
2756         ops->write = org.write;
2757         ops->read = org.read;
2758 }
2759
2760 static void rtl_release_firmware(struct rtl8169_private *tp)
2761 {
2762         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2763                 release_firmware(tp->rtl_fw->fw);
2764                 kfree(tp->rtl_fw);
2765         }
2766         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2767 }
2768
2769 static void rtl_apply_firmware(struct rtl8169_private *tp)
2770 {
2771         struct rtl_fw *rtl_fw = tp->rtl_fw;
2772
2773         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2774         if (!IS_ERR_OR_NULL(rtl_fw))
2775                 rtl_phy_write_fw(tp, rtl_fw);
2776 }
2777
2778 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2779 {
2780         if (rtl_readphy(tp, reg) != val)
2781                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2782         else
2783                 rtl_apply_firmware(tp);
2784 }
2785
2786 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2787 {
2788         static const struct phy_reg phy_reg_init[] = {
2789                 { 0x1f, 0x0001 },
2790                 { 0x06, 0x006e },
2791                 { 0x08, 0x0708 },
2792                 { 0x15, 0x4000 },
2793                 { 0x18, 0x65c7 },
2794
2795                 { 0x1f, 0x0001 },
2796                 { 0x03, 0x00a1 },
2797                 { 0x02, 0x0008 },
2798                 { 0x01, 0x0120 },
2799                 { 0x00, 0x1000 },
2800                 { 0x04, 0x0800 },
2801                 { 0x04, 0x0000 },
2802
2803                 { 0x03, 0xff41 },
2804                 { 0x02, 0xdf60 },
2805                 { 0x01, 0x0140 },
2806                 { 0x00, 0x0077 },
2807                 { 0x04, 0x7800 },
2808                 { 0x04, 0x7000 },
2809
2810                 { 0x03, 0x802f },
2811                 { 0x02, 0x4f02 },
2812                 { 0x01, 0x0409 },
2813                 { 0x00, 0xf0f9 },
2814                 { 0x04, 0x9800 },
2815                 { 0x04, 0x9000 },
2816
2817                 { 0x03, 0xdf01 },
2818                 { 0x02, 0xdf20 },
2819                 { 0x01, 0xff95 },
2820                 { 0x00, 0xba00 },
2821                 { 0x04, 0xa800 },
2822                 { 0x04, 0xa000 },
2823
2824                 { 0x03, 0xff41 },
2825                 { 0x02, 0xdf20 },
2826                 { 0x01, 0x0140 },
2827                 { 0x00, 0x00bb },
2828                 { 0x04, 0xb800 },
2829                 { 0x04, 0xb000 },
2830
2831                 { 0x03, 0xdf41 },
2832                 { 0x02, 0xdc60 },
2833                 { 0x01, 0x6340 },
2834                 { 0x00, 0x007d },
2835                 { 0x04, 0xd800 },
2836                 { 0x04, 0xd000 },
2837
2838                 { 0x03, 0xdf01 },
2839                 { 0x02, 0xdf20 },
2840                 { 0x01, 0x100a },
2841                 { 0x00, 0xa0ff },
2842                 { 0x04, 0xf800 },
2843                 { 0x04, 0xf000 },
2844
2845                 { 0x1f, 0x0000 },
2846                 { 0x0b, 0x0000 },
2847                 { 0x00, 0x9200 }
2848         };
2849
2850         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2851 }
2852
2853 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2854 {
2855         static const struct phy_reg phy_reg_init[] = {
2856                 { 0x1f, 0x0002 },
2857                 { 0x01, 0x90d0 },
2858                 { 0x1f, 0x0000 }
2859         };
2860
2861         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2862 }
2863
2864 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2865 {
2866         struct pci_dev *pdev = tp->pci_dev;
2867
2868         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2869             (pdev->subsystem_device != 0xe000))
2870                 return;
2871
2872         rtl_writephy(tp, 0x1f, 0x0001);
2873         rtl_writephy(tp, 0x10, 0xf01b);
2874         rtl_writephy(tp, 0x1f, 0x0000);
2875 }
2876
2877 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2878 {
2879         static const struct phy_reg phy_reg_init[] = {
2880                 { 0x1f, 0x0001 },
2881                 { 0x04, 0x0000 },
2882                 { 0x03, 0x00a1 },
2883                 { 0x02, 0x0008 },
2884                 { 0x01, 0x0120 },
2885                 { 0x00, 0x1000 },
2886                 { 0x04, 0x0800 },
2887                 { 0x04, 0x9000 },
2888                 { 0x03, 0x802f },
2889                 { 0x02, 0x4f02 },
2890                 { 0x01, 0x0409 },
2891                 { 0x00, 0xf099 },
2892                 { 0x04, 0x9800 },
2893                 { 0x04, 0xa000 },
2894                 { 0x03, 0xdf01 },
2895                 { 0x02, 0xdf20 },
2896                 { 0x01, 0xff95 },
2897                 { 0x00, 0xba00 },
2898                 { 0x04, 0xa800 },
2899                 { 0x04, 0xf000 },
2900                 { 0x03, 0xdf01 },
2901                 { 0x02, 0xdf20 },
2902                 { 0x01, 0x101a },
2903                 { 0x00, 0xa0ff },
2904                 { 0x04, 0xf800 },
2905                 { 0x04, 0x0000 },
2906                 { 0x1f, 0x0000 },
2907
2908                 { 0x1f, 0x0001 },
2909                 { 0x10, 0xf41b },
2910                 { 0x14, 0xfb54 },
2911                 { 0x18, 0xf5c7 },
2912                 { 0x1f, 0x0000 },
2913
2914                 { 0x1f, 0x0001 },
2915                 { 0x17, 0x0cc0 },
2916                 { 0x1f, 0x0000 }
2917         };
2918
2919         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2920
2921         rtl8169scd_hw_phy_config_quirk(tp);
2922 }
2923
2924 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2925 {
2926         static const struct phy_reg phy_reg_init[] = {
2927                 { 0x1f, 0x0001 },
2928                 { 0x04, 0x0000 },
2929                 { 0x03, 0x00a1 },
2930                 { 0x02, 0x0008 },
2931                 { 0x01, 0x0120 },
2932                 { 0x00, 0x1000 },
2933                 { 0x04, 0x0800 },
2934                 { 0x04, 0x9000 },
2935                 { 0x03, 0x802f },
2936                 { 0x02, 0x4f02 },
2937                 { 0x01, 0x0409 },
2938                 { 0x00, 0xf099 },
2939                 { 0x04, 0x9800 },
2940                 { 0x04, 0xa000 },
2941                 { 0x03, 0xdf01 },
2942                 { 0x02, 0xdf20 },
2943                 { 0x01, 0xff95 },
2944                 { 0x00, 0xba00 },
2945                 { 0x04, 0xa800 },
2946                 { 0x04, 0xf000 },
2947                 { 0x03, 0xdf01 },
2948                 { 0x02, 0xdf20 },
2949                 { 0x01, 0x101a },
2950                 { 0x00, 0xa0ff },
2951                 { 0x04, 0xf800 },
2952                 { 0x04, 0x0000 },
2953                 { 0x1f, 0x0000 },
2954
2955                 { 0x1f, 0x0001 },
2956                 { 0x0b, 0x8480 },
2957                 { 0x1f, 0x0000 },
2958
2959                 { 0x1f, 0x0001 },
2960                 { 0x18, 0x67c7 },
2961                 { 0x04, 0x2000 },
2962                 { 0x03, 0x002f },
2963                 { 0x02, 0x4360 },
2964                 { 0x01, 0x0109 },
2965                 { 0x00, 0x3022 },
2966                 { 0x04, 0x2800 },
2967                 { 0x1f, 0x0000 },
2968
2969                 { 0x1f, 0x0001 },
2970                 { 0x17, 0x0cc0 },
2971                 { 0x1f, 0x0000 }
2972         };
2973
2974         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2975 }
2976
2977 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2978 {
2979         static const struct phy_reg phy_reg_init[] = {
2980                 { 0x10, 0xf41b },
2981                 { 0x1f, 0x0000 }
2982         };
2983
2984         rtl_writephy(tp, 0x1f, 0x0001);
2985         rtl_patchphy(tp, 0x16, 1 << 0);
2986
2987         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2988 }
2989
2990 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2991 {
2992         static const struct phy_reg phy_reg_init[] = {
2993                 { 0x1f, 0x0001 },
2994                 { 0x10, 0xf41b },
2995                 { 0x1f, 0x0000 }
2996         };
2997
2998         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2999 }
3000
3001 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
3002 {
3003         static const struct phy_reg phy_reg_init[] = {
3004                 { 0x1f, 0x0000 },
3005                 { 0x1d, 0x0f00 },
3006                 { 0x1f, 0x0002 },
3007                 { 0x0c, 0x1ec8 },
3008                 { 0x1f, 0x0000 }
3009         };
3010
3011         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3012 }
3013
3014 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
3015 {
3016         static const struct phy_reg phy_reg_init[] = {
3017                 { 0x1f, 0x0001 },
3018                 { 0x1d, 0x3d98 },
3019                 { 0x1f, 0x0000 }
3020         };
3021
3022         rtl_writephy(tp, 0x1f, 0x0000);
3023         rtl_patchphy(tp, 0x14, 1 << 5);
3024         rtl_patchphy(tp, 0x0d, 1 << 5);
3025
3026         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3027 }
3028
3029 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3030 {
3031         static const struct phy_reg phy_reg_init[] = {
3032                 { 0x1f, 0x0001 },
3033                 { 0x12, 0x2300 },
3034                 { 0x1f, 0x0002 },
3035                 { 0x00, 0x88d4 },
3036                 { 0x01, 0x82b1 },
3037                 { 0x03, 0x7002 },
3038                 { 0x08, 0x9e30 },
3039                 { 0x09, 0x01f0 },
3040                 { 0x0a, 0x5500 },
3041                 { 0x0c, 0x00c8 },
3042                 { 0x1f, 0x0003 },
3043                 { 0x12, 0xc096 },
3044                 { 0x16, 0x000a },
3045                 { 0x1f, 0x0000 },
3046                 { 0x1f, 0x0000 },
3047                 { 0x09, 0x2000 },
3048                 { 0x09, 0x0000 }
3049         };
3050
3051         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3052
3053         rtl_patchphy(tp, 0x14, 1 << 5);
3054         rtl_patchphy(tp, 0x0d, 1 << 5);
3055         rtl_writephy(tp, 0x1f, 0x0000);
3056 }
3057
3058 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3059 {
3060         static const struct phy_reg phy_reg_init[] = {
3061                 { 0x1f, 0x0001 },
3062                 { 0x12, 0x2300 },
3063                 { 0x03, 0x802f },
3064                 { 0x02, 0x4f02 },
3065                 { 0x01, 0x0409 },
3066                 { 0x00, 0xf099 },
3067                 { 0x04, 0x9800 },
3068                 { 0x04, 0x9000 },
3069                 { 0x1d, 0x3d98 },
3070                 { 0x1f, 0x0002 },
3071                 { 0x0c, 0x7eb8 },
3072                 { 0x06, 0x0761 },
3073                 { 0x1f, 0x0003 },
3074                 { 0x16, 0x0f0a },
3075                 { 0x1f, 0x0000 }
3076         };
3077
3078         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3079
3080         rtl_patchphy(tp, 0x16, 1 << 0);
3081         rtl_patchphy(tp, 0x14, 1 << 5);
3082         rtl_patchphy(tp, 0x0d, 1 << 5);
3083         rtl_writephy(tp, 0x1f, 0x0000);
3084 }
3085
3086 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3087 {
3088         static const struct phy_reg phy_reg_init[] = {
3089                 { 0x1f, 0x0001 },
3090                 { 0x12, 0x2300 },
3091                 { 0x1d, 0x3d98 },
3092                 { 0x1f, 0x0002 },
3093                 { 0x0c, 0x7eb8 },
3094                 { 0x06, 0x5461 },
3095                 { 0x1f, 0x0003 },
3096                 { 0x16, 0x0f0a },
3097                 { 0x1f, 0x0000 }
3098         };
3099
3100         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3101
3102         rtl_patchphy(tp, 0x16, 1 << 0);
3103         rtl_patchphy(tp, 0x14, 1 << 5);
3104         rtl_patchphy(tp, 0x0d, 1 << 5);
3105         rtl_writephy(tp, 0x1f, 0x0000);
3106 }
3107
3108 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3109 {
3110         rtl8168c_3_hw_phy_config(tp);
3111 }
3112
3113 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3114 {
3115         static const struct phy_reg phy_reg_init_0[] = {
3116                 /* Channel Estimation */
3117                 { 0x1f, 0x0001 },
3118                 { 0x06, 0x4064 },
3119                 { 0x07, 0x2863 },
3120                 { 0x08, 0x059c },
3121                 { 0x09, 0x26b4 },
3122                 { 0x0a, 0x6a19 },
3123                 { 0x0b, 0xdcc8 },
3124                 { 0x10, 0xf06d },
3125                 { 0x14, 0x7f68 },
3126                 { 0x18, 0x7fd9 },
3127                 { 0x1c, 0xf0ff },
3128                 { 0x1d, 0x3d9c },
3129                 { 0x1f, 0x0003 },
3130                 { 0x12, 0xf49f },
3131                 { 0x13, 0x070b },
3132                 { 0x1a, 0x05ad },
3133                 { 0x14, 0x94c0 },
3134
3135                 /*
3136                  * Tx Error Issue
3137                  * Enhance line driver power
3138                  */
3139                 { 0x1f, 0x0002 },
3140                 { 0x06, 0x5561 },
3141                 { 0x1f, 0x0005 },
3142                 { 0x05, 0x8332 },
3143                 { 0x06, 0x5561 },
3144
3145                 /*
3146                  * Can not link to 1Gbps with bad cable
3147                  * Decrease SNR threshold form 21.07dB to 19.04dB
3148                  */
3149                 { 0x1f, 0x0001 },
3150                 { 0x17, 0x0cc0 },
3151
3152                 { 0x1f, 0x0000 },
3153                 { 0x0d, 0xf880 }
3154         };
3155
3156         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3157
3158         /*
3159          * Rx Error Issue
3160          * Fine Tune Switching regulator parameter
3161          */
3162         rtl_writephy(tp, 0x1f, 0x0002);
3163         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3164         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3165
3166         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3167                 static const struct phy_reg phy_reg_init[] = {
3168                         { 0x1f, 0x0002 },
3169                         { 0x05, 0x669a },
3170                         { 0x1f, 0x0005 },
3171                         { 0x05, 0x8330 },
3172                         { 0x06, 0x669a },
3173                         { 0x1f, 0x0002 }
3174                 };
3175                 int val;
3176
3177                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3178
3179                 val = rtl_readphy(tp, 0x0d);
3180
3181                 if ((val & 0x00ff) != 0x006c) {
3182                         static const u32 set[] = {
3183                                 0x0065, 0x0066, 0x0067, 0x0068,
3184                                 0x0069, 0x006a, 0x006b, 0x006c
3185                         };
3186                         int i;
3187
3188                         rtl_writephy(tp, 0x1f, 0x0002);
3189
3190                         val &= 0xff00;
3191                         for (i = 0; i < ARRAY_SIZE(set); i++)
3192                                 rtl_writephy(tp, 0x0d, val | set[i]);
3193                 }
3194         } else {
3195                 static const struct phy_reg phy_reg_init[] = {
3196                         { 0x1f, 0x0002 },
3197                         { 0x05, 0x6662 },
3198                         { 0x1f, 0x0005 },
3199                         { 0x05, 0x8330 },
3200                         { 0x06, 0x6662 }
3201                 };
3202
3203                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3204         }
3205
3206         /* RSET couple improve */
3207         rtl_writephy(tp, 0x1f, 0x0002);
3208         rtl_patchphy(tp, 0x0d, 0x0300);
3209         rtl_patchphy(tp, 0x0f, 0x0010);
3210
3211         /* Fine tune PLL performance */
3212         rtl_writephy(tp, 0x1f, 0x0002);
3213         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3214         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3215
3216         rtl_writephy(tp, 0x1f, 0x0005);
3217         rtl_writephy(tp, 0x05, 0x001b);
3218
3219         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3220
3221         rtl_writephy(tp, 0x1f, 0x0000);
3222 }
3223
3224 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3225 {
3226         static const struct phy_reg phy_reg_init_0[] = {
3227                 /* Channel Estimation */
3228                 { 0x1f, 0x0001 },
3229                 { 0x06, 0x4064 },
3230                 { 0x07, 0x2863 },
3231                 { 0x08, 0x059c },
3232                 { 0x09, 0x26b4 },
3233                 { 0x0a, 0x6a19 },
3234                 { 0x0b, 0xdcc8 },
3235                 { 0x10, 0xf06d },
3236                 { 0x14, 0x7f68 },
3237                 { 0x18, 0x7fd9 },
3238                 { 0x1c, 0xf0ff },
3239                 { 0x1d, 0x3d9c },
3240                 { 0x1f, 0x0003 },
3241                 { 0x12, 0xf49f },
3242                 { 0x13, 0x070b },
3243                 { 0x1a, 0x05ad },
3244                 { 0x14, 0x94c0 },
3245
3246                 /*
3247                  * Tx Error Issue
3248                  * Enhance line driver power
3249                  */
3250                 { 0x1f, 0x0002 },
3251                 { 0x06, 0x5561 },
3252                 { 0x1f, 0x0005 },
3253                 { 0x05, 0x8332 },
3254                 { 0x06, 0x5561 },
3255
3256                 /*
3257                  * Can not link to 1Gbps with bad cable
3258                  * Decrease SNR threshold form 21.07dB to 19.04dB
3259                  */
3260                 { 0x1f, 0x0001 },
3261                 { 0x17, 0x0cc0 },
3262
3263                 { 0x1f, 0x0000 },
3264                 { 0x0d, 0xf880 }
3265         };
3266
3267         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3268
3269         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3270                 static const struct phy_reg phy_reg_init[] = {
3271                         { 0x1f, 0x0002 },
3272                         { 0x05, 0x669a },
3273                         { 0x1f, 0x0005 },
3274                         { 0x05, 0x8330 },
3275                         { 0x06, 0x669a },
3276
3277                         { 0x1f, 0x0002 }
3278                 };
3279                 int val;
3280
3281                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3282
3283                 val = rtl_readphy(tp, 0x0d);
3284                 if ((val & 0x00ff) != 0x006c) {
3285                         static const u32 set[] = {
3286                                 0x0065, 0x0066, 0x0067, 0x0068,
3287                                 0x0069, 0x006a, 0x006b, 0x006c
3288                         };
3289                         int i;
3290
3291                         rtl_writephy(tp, 0x1f, 0x0002);
3292
3293                         val &= 0xff00;
3294                         for (i = 0; i < ARRAY_SIZE(set); i++)
3295                                 rtl_writephy(tp, 0x0d, val | set[i]);
3296                 }
3297         } else {
3298                 static const struct phy_reg phy_reg_init[] = {
3299                         { 0x1f, 0x0002 },
3300                         { 0x05, 0x2642 },
3301                         { 0x1f, 0x0005 },
3302                         { 0x05, 0x8330 },
3303                         { 0x06, 0x2642 }
3304                 };
3305
3306                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3307         }
3308
3309         /* Fine tune PLL performance */
3310         rtl_writephy(tp, 0x1f, 0x0002);
3311         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3312         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3313
3314         /* Switching regulator Slew rate */
3315         rtl_writephy(tp, 0x1f, 0x0002);
3316         rtl_patchphy(tp, 0x0f, 0x0017);
3317
3318         rtl_writephy(tp, 0x1f, 0x0005);
3319         rtl_writephy(tp, 0x05, 0x001b);
3320
3321         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3322
3323         rtl_writephy(tp, 0x1f, 0x0000);
3324 }
3325
3326 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3327 {
3328         static const struct phy_reg phy_reg_init[] = {
3329                 { 0x1f, 0x0002 },
3330                 { 0x10, 0x0008 },
3331                 { 0x0d, 0x006c },
3332
3333                 { 0x1f, 0x0000 },
3334                 { 0x0d, 0xf880 },
3335
3336                 { 0x1f, 0x0001 },
3337                 { 0x17, 0x0cc0 },
3338
3339                 { 0x1f, 0x0001 },
3340                 { 0x0b, 0xa4d8 },
3341                 { 0x09, 0x281c },
3342                 { 0x07, 0x2883 },
3343                 { 0x0a, 0x6b35 },
3344                 { 0x1d, 0x3da4 },
3345                 { 0x1c, 0xeffd },
3346                 { 0x14, 0x7f52 },
3347                 { 0x18, 0x7fc6 },
3348                 { 0x08, 0x0601 },
3349                 { 0x06, 0x4063 },
3350                 { 0x10, 0xf074 },
3351                 { 0x1f, 0x0003 },
3352                 { 0x13, 0x0789 },
3353                 { 0x12, 0xf4bd },
3354                 { 0x1a, 0x04fd },
3355                 { 0x14, 0x84b0 },
3356                 { 0x1f, 0x0000 },
3357                 { 0x00, 0x9200 },
3358
3359                 { 0x1f, 0x0005 },
3360                 { 0x01, 0x0340 },
3361                 { 0x1f, 0x0001 },
3362                 { 0x04, 0x4000 },
3363                 { 0x03, 0x1d21 },
3364                 { 0x02, 0x0c32 },
3365                 { 0x01, 0x0200 },
3366                 { 0x00, 0x5554 },
3367                 { 0x04, 0x4800 },
3368                 { 0x04, 0x4000 },
3369                 { 0x04, 0xf000 },
3370                 { 0x03, 0xdf01 },
3371                 { 0x02, 0xdf20 },
3372                 { 0x01, 0x101a },
3373                 { 0x00, 0xa0ff },
3374                 { 0x04, 0xf800 },
3375                 { 0x04, 0xf000 },
3376                 { 0x1f, 0x0000 },
3377
3378                 { 0x1f, 0x0007 },
3379                 { 0x1e, 0x0023 },
3380                 { 0x16, 0x0000 },
3381                 { 0x1f, 0x0000 }
3382         };
3383
3384         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3385 }
3386
3387 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3388 {
3389         static const struct phy_reg phy_reg_init[] = {
3390                 { 0x1f, 0x0001 },
3391                 { 0x17, 0x0cc0 },
3392
3393                 { 0x1f, 0x0007 },
3394                 { 0x1e, 0x002d },
3395                 { 0x18, 0x0040 },
3396                 { 0x1f, 0x0000 }
3397         };
3398
3399         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3400         rtl_patchphy(tp, 0x0d, 1 << 5);
3401 }
3402
3403 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3404 {
3405         static const struct phy_reg phy_reg_init[] = {
3406                 /* Enable Delay cap */
3407                 { 0x1f, 0x0005 },
3408                 { 0x05, 0x8b80 },
3409                 { 0x06, 0xc896 },
3410                 { 0x1f, 0x0000 },
3411
3412                 /* Channel estimation fine tune */
3413                 { 0x1f, 0x0001 },
3414                 { 0x0b, 0x6c20 },
3415                 { 0x07, 0x2872 },
3416                 { 0x1c, 0xefff },
3417                 { 0x1f, 0x0003 },
3418                 { 0x14, 0x6420 },
3419                 { 0x1f, 0x0000 },
3420
3421                 /* Update PFM & 10M TX idle timer */
3422                 { 0x1f, 0x0007 },
3423                 { 0x1e, 0x002f },
3424                 { 0x15, 0x1919 },
3425                 { 0x1f, 0x0000 },
3426
3427                 { 0x1f, 0x0007 },
3428                 { 0x1e, 0x00ac },
3429                 { 0x18, 0x0006 },
3430                 { 0x1f, 0x0000 }
3431         };
3432
3433         rtl_apply_firmware(tp);
3434
3435         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3436
3437         /* DCO enable for 10M IDLE Power */
3438         rtl_writephy(tp, 0x1f, 0x0007);
3439         rtl_writephy(tp, 0x1e, 0x0023);
3440         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3441         rtl_writephy(tp, 0x1f, 0x0000);
3442
3443         /* For impedance matching */
3444         rtl_writephy(tp, 0x1f, 0x0002);
3445         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3446         rtl_writephy(tp, 0x1f, 0x0000);
3447
3448         /* PHY auto speed down */
3449         rtl_writephy(tp, 0x1f, 0x0007);
3450         rtl_writephy(tp, 0x1e, 0x002d);
3451         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3452         rtl_writephy(tp, 0x1f, 0x0000);
3453         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3454
3455         rtl_writephy(tp, 0x1f, 0x0005);
3456         rtl_writephy(tp, 0x05, 0x8b86);
3457         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3458         rtl_writephy(tp, 0x1f, 0x0000);
3459
3460         rtl_writephy(tp, 0x1f, 0x0005);
3461         rtl_writephy(tp, 0x05, 0x8b85);
3462         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3463         rtl_writephy(tp, 0x1f, 0x0007);
3464         rtl_writephy(tp, 0x1e, 0x0020);
3465         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3466         rtl_writephy(tp, 0x1f, 0x0006);
3467         rtl_writephy(tp, 0x00, 0x5a00);
3468         rtl_writephy(tp, 0x1f, 0x0000);
3469         rtl_writephy(tp, 0x0d, 0x0007);
3470         rtl_writephy(tp, 0x0e, 0x003c);
3471         rtl_writephy(tp, 0x0d, 0x4007);
3472         rtl_writephy(tp, 0x0e, 0x0000);
3473         rtl_writephy(tp, 0x0d, 0x0000);
3474 }
3475
3476 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3477 {
3478         const u16 w[] = {
3479                 addr[0] | (addr[1] << 8),
3480                 addr[2] | (addr[3] << 8),
3481                 addr[4] | (addr[5] << 8)
3482         };
3483         const struct exgmac_reg e[] = {
3484                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3485                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3486                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3487                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3488         };
3489
3490         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3491 }
3492
3493 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3494 {
3495         static const struct phy_reg phy_reg_init[] = {
3496                 /* Enable Delay cap */
3497                 { 0x1f, 0x0004 },
3498                 { 0x1f, 0x0007 },
3499                 { 0x1e, 0x00ac },
3500                 { 0x18, 0x0006 },
3501                 { 0x1f, 0x0002 },
3502                 { 0x1f, 0x0000 },
3503                 { 0x1f, 0x0000 },
3504
3505                 /* Channel estimation fine tune */
3506                 { 0x1f, 0x0003 },
3507                 { 0x09, 0xa20f },
3508                 { 0x1f, 0x0000 },
3509                 { 0x1f, 0x0000 },
3510
3511                 /* Green Setting */
3512                 { 0x1f, 0x0005 },
3513                 { 0x05, 0x8b5b },
3514                 { 0x06, 0x9222 },
3515                 { 0x05, 0x8b6d },
3516                 { 0x06, 0x8000 },
3517                 { 0x05, 0x8b76 },
3518                 { 0x06, 0x8000 },
3519                 { 0x1f, 0x0000 }
3520         };
3521
3522         rtl_apply_firmware(tp);
3523
3524         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3525
3526         /* For 4-corner performance improve */
3527         rtl_writephy(tp, 0x1f, 0x0005);
3528         rtl_writephy(tp, 0x05, 0x8b80);
3529         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3530         rtl_writephy(tp, 0x1f, 0x0000);
3531
3532         /* PHY auto speed down */
3533         rtl_writephy(tp, 0x1f, 0x0004);
3534         rtl_writephy(tp, 0x1f, 0x0007);
3535         rtl_writephy(tp, 0x1e, 0x002d);
3536         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3537         rtl_writephy(tp, 0x1f, 0x0002);
3538         rtl_writephy(tp, 0x1f, 0x0000);
3539         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3540
3541         /* improve 10M EEE waveform */
3542         rtl_writephy(tp, 0x1f, 0x0005);
3543         rtl_writephy(tp, 0x05, 0x8b86);
3544         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3545         rtl_writephy(tp, 0x1f, 0x0000);
3546
3547         /* Improve 2-pair detection performance */
3548         rtl_writephy(tp, 0x1f, 0x0005);
3549         rtl_writephy(tp, 0x05, 0x8b85);
3550         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3551         rtl_writephy(tp, 0x1f, 0x0000);
3552
3553         /* EEE setting */
3554         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3555         rtl_writephy(tp, 0x1f, 0x0005);
3556         rtl_writephy(tp, 0x05, 0x8b85);
3557         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3558         rtl_writephy(tp, 0x1f, 0x0004);
3559         rtl_writephy(tp, 0x1f, 0x0007);
3560         rtl_writephy(tp, 0x1e, 0x0020);
3561         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3562         rtl_writephy(tp, 0x1f, 0x0002);
3563         rtl_writephy(tp, 0x1f, 0x0000);
3564         rtl_writephy(tp, 0x0d, 0x0007);
3565         rtl_writephy(tp, 0x0e, 0x003c);
3566         rtl_writephy(tp, 0x0d, 0x4007);
3567         rtl_writephy(tp, 0x0e, 0x0000);
3568         rtl_writephy(tp, 0x0d, 0x0000);
3569
3570         /* Green feature */
3571         rtl_writephy(tp, 0x1f, 0x0003);
3572         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3573         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3574         rtl_writephy(tp, 0x1f, 0x0000);
3575
3576         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3577         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3578 }
3579
3580 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3581 {
3582         /* For 4-corner performance improve */
3583         rtl_writephy(tp, 0x1f, 0x0005);
3584         rtl_writephy(tp, 0x05, 0x8b80);
3585         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3586         rtl_writephy(tp, 0x1f, 0x0000);
3587
3588         /* PHY auto speed down */
3589         rtl_writephy(tp, 0x1f, 0x0007);
3590         rtl_writephy(tp, 0x1e, 0x002d);
3591         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3592         rtl_writephy(tp, 0x1f, 0x0000);
3593         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3594
3595         /* Improve 10M EEE waveform */
3596         rtl_writephy(tp, 0x1f, 0x0005);
3597         rtl_writephy(tp, 0x05, 0x8b86);
3598         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3599         rtl_writephy(tp, 0x1f, 0x0000);
3600 }
3601
3602 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3603 {
3604         static const struct phy_reg phy_reg_init[] = {
3605                 /* Channel estimation fine tune */
3606                 { 0x1f, 0x0003 },
3607                 { 0x09, 0xa20f },
3608                 { 0x1f, 0x0000 },
3609
3610                 /* Modify green table for giga & fnet */
3611                 { 0x1f, 0x0005 },
3612                 { 0x05, 0x8b55 },
3613                 { 0x06, 0x0000 },
3614                 { 0x05, 0x8b5e },
3615                 { 0x06, 0x0000 },
3616                 { 0x05, 0x8b67 },
3617                 { 0x06, 0x0000 },
3618                 { 0x05, 0x8b70 },
3619                 { 0x06, 0x0000 },
3620                 { 0x1f, 0x0000 },
3621                 { 0x1f, 0x0007 },
3622                 { 0x1e, 0x0078 },
3623                 { 0x17, 0x0000 },
3624                 { 0x19, 0x00fb },
3625                 { 0x1f, 0x0000 },
3626
3627                 /* Modify green table for 10M */
3628                 { 0x1f, 0x0005 },
3629                 { 0x05, 0x8b79 },
3630                 { 0x06, 0xaa00 },
3631                 { 0x1f, 0x0000 },
3632
3633                 /* Disable hiimpedance detection (RTCT) */
3634                 { 0x1f, 0x0003 },
3635                 { 0x01, 0x328a },
3636                 { 0x1f, 0x0000 }
3637         };
3638
3639         rtl_apply_firmware(tp);
3640
3641         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3642
3643         rtl8168f_hw_phy_config(tp);
3644
3645         /* Improve 2-pair detection performance */
3646         rtl_writephy(tp, 0x1f, 0x0005);
3647         rtl_writephy(tp, 0x05, 0x8b85);
3648         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3649         rtl_writephy(tp, 0x1f, 0x0000);
3650 }
3651
3652 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3653 {
3654         rtl_apply_firmware(tp);
3655
3656         rtl8168f_hw_phy_config(tp);
3657 }
3658
3659 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3660 {
3661         static const struct phy_reg phy_reg_init[] = {
3662                 /* Channel estimation fine tune */
3663                 { 0x1f, 0x0003 },
3664                 { 0x09, 0xa20f },
3665                 { 0x1f, 0x0000 },
3666
3667                 /* Modify green table for giga & fnet */
3668                 { 0x1f, 0x0005 },
3669                 { 0x05, 0x8b55 },
3670                 { 0x06, 0x0000 },
3671                 { 0x05, 0x8b5e },
3672                 { 0x06, 0x0000 },
3673                 { 0x05, 0x8b67 },
3674                 { 0x06, 0x0000 },
3675                 { 0x05, 0x8b70 },
3676                 { 0x06, 0x0000 },
3677                 { 0x1f, 0x0000 },
3678                 { 0x1f, 0x0007 },
3679                 { 0x1e, 0x0078 },
3680                 { 0x17, 0x0000 },
3681                 { 0x19, 0x00aa },
3682                 { 0x1f, 0x0000 },
3683
3684                 /* Modify green table for 10M */
3685                 { 0x1f, 0x0005 },
3686                 { 0x05, 0x8b79 },
3687                 { 0x06, 0xaa00 },
3688                 { 0x1f, 0x0000 },
3689
3690                 /* Disable hiimpedance detection (RTCT) */
3691                 { 0x1f, 0x0003 },
3692                 { 0x01, 0x328a },
3693                 { 0x1f, 0x0000 }
3694         };
3695
3696
3697         rtl_apply_firmware(tp);
3698
3699         rtl8168f_hw_phy_config(tp);
3700
3701         /* Improve 2-pair detection performance */
3702         rtl_writephy(tp, 0x1f, 0x0005);
3703         rtl_writephy(tp, 0x05, 0x8b85);
3704         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3705         rtl_writephy(tp, 0x1f, 0x0000);
3706
3707         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3708
3709         /* Modify green table for giga */
3710         rtl_writephy(tp, 0x1f, 0x0005);
3711         rtl_writephy(tp, 0x05, 0x8b54);
3712         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3713         rtl_writephy(tp, 0x05, 0x8b5d);
3714         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3715         rtl_writephy(tp, 0x05, 0x8a7c);
3716         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3717         rtl_writephy(tp, 0x05, 0x8a7f);
3718         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3719         rtl_writephy(tp, 0x05, 0x8a82);
3720         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3721         rtl_writephy(tp, 0x05, 0x8a85);
3722         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3723         rtl_writephy(tp, 0x05, 0x8a88);
3724         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3725         rtl_writephy(tp, 0x1f, 0x0000);
3726
3727         /* uc same-seed solution */
3728         rtl_writephy(tp, 0x1f, 0x0005);
3729         rtl_writephy(tp, 0x05, 0x8b85);
3730         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3731         rtl_writephy(tp, 0x1f, 0x0000);
3732
3733         /* eee setting */
3734         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3735         rtl_writephy(tp, 0x1f, 0x0005);
3736         rtl_writephy(tp, 0x05, 0x8b85);
3737         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3738         rtl_writephy(tp, 0x1f, 0x0004);
3739         rtl_writephy(tp, 0x1f, 0x0007);
3740         rtl_writephy(tp, 0x1e, 0x0020);
3741         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3742         rtl_writephy(tp, 0x1f, 0x0000);
3743         rtl_writephy(tp, 0x0d, 0x0007);
3744         rtl_writephy(tp, 0x0e, 0x003c);
3745         rtl_writephy(tp, 0x0d, 0x4007);
3746         rtl_writephy(tp, 0x0e, 0x0000);
3747         rtl_writephy(tp, 0x0d, 0x0000);
3748
3749         /* Green feature */
3750         rtl_writephy(tp, 0x1f, 0x0003);
3751         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3752         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3753         rtl_writephy(tp, 0x1f, 0x0000);
3754 }
3755
3756 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3757 {
3758         rtl_apply_firmware(tp);
3759
3760         rtl_writephy(tp, 0x1f, 0x0a46);
3761         if (rtl_readphy(tp, 0x10) & 0x0100) {
3762                 rtl_writephy(tp, 0x1f, 0x0bcc);
3763                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3764         } else {
3765                 rtl_writephy(tp, 0x1f, 0x0bcc);
3766                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3767         }
3768
3769         rtl_writephy(tp, 0x1f, 0x0a46);
3770         if (rtl_readphy(tp, 0x13) & 0x0100) {
3771                 rtl_writephy(tp, 0x1f, 0x0c41);
3772                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3773         } else {
3774                 rtl_writephy(tp, 0x1f, 0x0c41);
3775                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3776         }
3777
3778         /* Enable PHY auto speed down */
3779         rtl_writephy(tp, 0x1f, 0x0a44);
3780         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3781
3782         rtl_writephy(tp, 0x1f, 0x0bcc);
3783         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3784         rtl_writephy(tp, 0x1f, 0x0a44);
3785         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3786         rtl_writephy(tp, 0x1f, 0x0a43);
3787         rtl_writephy(tp, 0x13, 0x8084);
3788         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3789         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3790
3791         /* EEE auto-fallback function */
3792         rtl_writephy(tp, 0x1f, 0x0a4b);
3793         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3794
3795         /* Enable UC LPF tune function */
3796         rtl_writephy(tp, 0x1f, 0x0a43);
3797         rtl_writephy(tp, 0x13, 0x8012);
3798         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3799
3800         rtl_writephy(tp, 0x1f, 0x0c42);
3801         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3802
3803         /* Improve SWR Efficiency */
3804         rtl_writephy(tp, 0x1f, 0x0bcd);
3805         rtl_writephy(tp, 0x14, 0x5065);
3806         rtl_writephy(tp, 0x14, 0xd065);
3807         rtl_writephy(tp, 0x1f, 0x0bc8);
3808         rtl_writephy(tp, 0x11, 0x5655);
3809         rtl_writephy(tp, 0x1f, 0x0bcd);
3810         rtl_writephy(tp, 0x14, 0x1065);
3811         rtl_writephy(tp, 0x14, 0x9065);
3812         rtl_writephy(tp, 0x14, 0x1065);
3813
3814         /* Check ALDPS bit, disable it if enabled */
3815         rtl_writephy(tp, 0x1f, 0x0a43);
3816         if (rtl_readphy(tp, 0x10) & 0x0004)
3817                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3818
3819         rtl_writephy(tp, 0x1f, 0x0000);
3820 }
3821
3822 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3823 {
3824         rtl_apply_firmware(tp);
3825 }
3826
3827 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3828 {
3829         u16 dout_tapbin;
3830         u32 data;
3831
3832         rtl_apply_firmware(tp);
3833
3834         /* CHN EST parameters adjust - giga master */
3835         rtl_writephy(tp, 0x1f, 0x0a43);
3836         rtl_writephy(tp, 0x13, 0x809b);
3837         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3838         rtl_writephy(tp, 0x13, 0x80a2);
3839         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3840         rtl_writephy(tp, 0x13, 0x80a4);
3841         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3842         rtl_writephy(tp, 0x13, 0x809c);
3843         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3844         rtl_writephy(tp, 0x1f, 0x0000);
3845
3846         /* CHN EST parameters adjust - giga slave */
3847         rtl_writephy(tp, 0x1f, 0x0a43);
3848         rtl_writephy(tp, 0x13, 0x80ad);
3849         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3850         rtl_writephy(tp, 0x13, 0x80b4);
3851         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3852         rtl_writephy(tp, 0x13, 0x80ac);
3853         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3854         rtl_writephy(tp, 0x1f, 0x0000);
3855
3856         /* CHN EST parameters adjust - fnet */
3857         rtl_writephy(tp, 0x1f, 0x0a43);
3858         rtl_writephy(tp, 0x13, 0x808e);
3859         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3860         rtl_writephy(tp, 0x13, 0x8090);
3861         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3862         rtl_writephy(tp, 0x13, 0x8092);
3863         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3864         rtl_writephy(tp, 0x1f, 0x0000);
3865
3866         /* enable R-tune & PGA-retune function */
3867         dout_tapbin = 0;
3868         rtl_writephy(tp, 0x1f, 0x0a46);
3869         data = rtl_readphy(tp, 0x13);
3870         data &= 3;
3871         data <<= 2;
3872         dout_tapbin |= data;
3873         data = rtl_readphy(tp, 0x12);
3874         data &= 0xc000;
3875         data >>= 14;
3876         dout_tapbin |= data;
3877         dout_tapbin = ~(dout_tapbin^0x08);
3878         dout_tapbin <<= 12;
3879         dout_tapbin &= 0xf000;
3880         rtl_writephy(tp, 0x1f, 0x0a43);
3881         rtl_writephy(tp, 0x13, 0x827a);
3882         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3883         rtl_writephy(tp, 0x13, 0x827b);
3884         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3885         rtl_writephy(tp, 0x13, 0x827c);
3886         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3887         rtl_writephy(tp, 0x13, 0x827d);
3888         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3889
3890         rtl_writephy(tp, 0x1f, 0x0a43);
3891         rtl_writephy(tp, 0x13, 0x0811);
3892         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3893         rtl_writephy(tp, 0x1f, 0x0a42);
3894         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3895         rtl_writephy(tp, 0x1f, 0x0000);
3896
3897         /* enable GPHY 10M */
3898         rtl_writephy(tp, 0x1f, 0x0a44);
3899         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3900         rtl_writephy(tp, 0x1f, 0x0000);
3901
3902         /* SAR ADC performance */
3903         rtl_writephy(tp, 0x1f, 0x0bca);
3904         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3905         rtl_writephy(tp, 0x1f, 0x0000);
3906
3907         rtl_writephy(tp, 0x1f, 0x0a43);
3908         rtl_writephy(tp, 0x13, 0x803f);
3909         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3910         rtl_writephy(tp, 0x13, 0x8047);
3911         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3912         rtl_writephy(tp, 0x13, 0x804f);
3913         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3914         rtl_writephy(tp, 0x13, 0x8057);
3915         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3916         rtl_writephy(tp, 0x13, 0x805f);
3917         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3918         rtl_writephy(tp, 0x13, 0x8067);
3919         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3920         rtl_writephy(tp, 0x13, 0x806f);
3921         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3922         rtl_writephy(tp, 0x1f, 0x0000);
3923
3924         /* disable phy pfm mode */
3925         rtl_writephy(tp, 0x1f, 0x0a44);
3926         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3927         rtl_writephy(tp, 0x1f, 0x0000);
3928
3929         /* Check ALDPS bit, disable it if enabled */
3930         rtl_writephy(tp, 0x1f, 0x0a43);
3931         if (rtl_readphy(tp, 0x10) & 0x0004)
3932                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3933
3934         rtl_writephy(tp, 0x1f, 0x0000);
3935 }
3936
3937 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3938 {
3939         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3940         u16 rlen;
3941         u32 data;
3942
3943         rtl_apply_firmware(tp);
3944
3945         /* CHIN EST parameter update */
3946         rtl_writephy(tp, 0x1f, 0x0a43);
3947         rtl_writephy(tp, 0x13, 0x808a);
3948         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3949         rtl_writephy(tp, 0x1f, 0x0000);
3950
3951         /* enable R-tune & PGA-retune function */
3952         rtl_writephy(tp, 0x1f, 0x0a43);
3953         rtl_writephy(tp, 0x13, 0x0811);
3954         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3955         rtl_writephy(tp, 0x1f, 0x0a42);
3956         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3957         rtl_writephy(tp, 0x1f, 0x0000);
3958
3959         /* enable GPHY 10M */
3960         rtl_writephy(tp, 0x1f, 0x0a44);
3961         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3962         rtl_writephy(tp, 0x1f, 0x0000);
3963
3964         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3965         data = r8168_mac_ocp_read(tp, 0xdd02);
3966         ioffset_p3 = ((data & 0x80)>>7);
3967         ioffset_p3 <<= 3;
3968
3969         data = r8168_mac_ocp_read(tp, 0xdd00);
3970         ioffset_p3 |= ((data & (0xe000))>>13);
3971         ioffset_p2 = ((data & (0x1e00))>>9);
3972         ioffset_p1 = ((data & (0x01e0))>>5);
3973         ioffset_p0 = ((data & 0x0010)>>4);
3974         ioffset_p0 <<= 3;
3975         ioffset_p0 |= (data & (0x07));
3976         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3977
3978         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3979             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3980                 rtl_writephy(tp, 0x1f, 0x0bcf);
3981                 rtl_writephy(tp, 0x16, data);
3982                 rtl_writephy(tp, 0x1f, 0x0000);
3983         }
3984
3985         /* Modify rlen (TX LPF corner frequency) level */
3986         rtl_writephy(tp, 0x1f, 0x0bcd);
3987         data = rtl_readphy(tp, 0x16);
3988         data &= 0x000f;
3989         rlen = 0;
3990         if (data > 3)
3991                 rlen = data - 3;
3992         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3993         rtl_writephy(tp, 0x17, data);
3994         rtl_writephy(tp, 0x1f, 0x0bcd);
3995         rtl_writephy(tp, 0x1f, 0x0000);
3996
3997         /* disable phy pfm mode */
3998         rtl_writephy(tp, 0x1f, 0x0a44);
3999         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4000         rtl_writephy(tp, 0x1f, 0x0000);
4001
4002         /* Check ALDPS bit, disable it if enabled */
4003         rtl_writephy(tp, 0x1f, 0x0a43);
4004         if (rtl_readphy(tp, 0x10) & 0x0004)
4005                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4006
4007         rtl_writephy(tp, 0x1f, 0x0000);
4008 }
4009
4010 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4011 {
4012         /* Enable PHY auto speed down */
4013         rtl_writephy(tp, 0x1f, 0x0a44);
4014         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4015         rtl_writephy(tp, 0x1f, 0x0000);
4016
4017         /* patch 10M & ALDPS */
4018         rtl_writephy(tp, 0x1f, 0x0bcc);
4019         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4020         rtl_writephy(tp, 0x1f, 0x0a44);
4021         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4022         rtl_writephy(tp, 0x1f, 0x0a43);
4023         rtl_writephy(tp, 0x13, 0x8084);
4024         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4025         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4026         rtl_writephy(tp, 0x1f, 0x0000);
4027
4028         /* Enable EEE auto-fallback function */
4029         rtl_writephy(tp, 0x1f, 0x0a4b);
4030         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4031         rtl_writephy(tp, 0x1f, 0x0000);
4032
4033         /* Enable UC LPF tune function */
4034         rtl_writephy(tp, 0x1f, 0x0a43);
4035         rtl_writephy(tp, 0x13, 0x8012);
4036         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4037         rtl_writephy(tp, 0x1f, 0x0000);
4038
4039         /* set rg_sel_sdm_rate */
4040         rtl_writephy(tp, 0x1f, 0x0c42);
4041         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4042         rtl_writephy(tp, 0x1f, 0x0000);
4043
4044         /* Check ALDPS bit, disable it if enabled */
4045         rtl_writephy(tp, 0x1f, 0x0a43);
4046         if (rtl_readphy(tp, 0x10) & 0x0004)
4047                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4048
4049         rtl_writephy(tp, 0x1f, 0x0000);
4050 }
4051
4052 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4053 {
4054         /* patch 10M & ALDPS */
4055         rtl_writephy(tp, 0x1f, 0x0bcc);
4056         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4057         rtl_writephy(tp, 0x1f, 0x0a44);
4058         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4059         rtl_writephy(tp, 0x1f, 0x0a43);
4060         rtl_writephy(tp, 0x13, 0x8084);
4061         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4062         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4063         rtl_writephy(tp, 0x1f, 0x0000);
4064
4065         /* Enable UC LPF tune function */
4066         rtl_writephy(tp, 0x1f, 0x0a43);
4067         rtl_writephy(tp, 0x13, 0x8012);
4068         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4069         rtl_writephy(tp, 0x1f, 0x0000);
4070
4071         /* Set rg_sel_sdm_rate */
4072         rtl_writephy(tp, 0x1f, 0x0c42);
4073         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4074         rtl_writephy(tp, 0x1f, 0x0000);
4075
4076         /* Channel estimation parameters */
4077         rtl_writephy(tp, 0x1f, 0x0a43);
4078         rtl_writephy(tp, 0x13, 0x80f3);
4079         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4080         rtl_writephy(tp, 0x13, 0x80f0);
4081         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4082         rtl_writephy(tp, 0x13, 0x80ef);
4083         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4084         rtl_writephy(tp, 0x13, 0x80f6);
4085         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4086         rtl_writephy(tp, 0x13, 0x80ec);
4087         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4088         rtl_writephy(tp, 0x13, 0x80ed);
4089         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4090         rtl_writephy(tp, 0x13, 0x80f2);
4091         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4092         rtl_writephy(tp, 0x13, 0x80f4);
4093         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4094         rtl_writephy(tp, 0x1f, 0x0a43);
4095         rtl_writephy(tp, 0x13, 0x8110);
4096         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4097         rtl_writephy(tp, 0x13, 0x810f);
4098         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4099         rtl_writephy(tp, 0x13, 0x8111);
4100         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4101         rtl_writephy(tp, 0x13, 0x8113);
4102         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4103         rtl_writephy(tp, 0x13, 0x8115);
4104         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4105         rtl_writephy(tp, 0x13, 0x810e);
4106         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4107         rtl_writephy(tp, 0x13, 0x810c);
4108         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4109         rtl_writephy(tp, 0x13, 0x810b);
4110         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4111         rtl_writephy(tp, 0x1f, 0x0a43);
4112         rtl_writephy(tp, 0x13, 0x80d1);
4113         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4114         rtl_writephy(tp, 0x13, 0x80cd);
4115         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4116         rtl_writephy(tp, 0x13, 0x80d3);
4117         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4118         rtl_writephy(tp, 0x13, 0x80d5);
4119         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4120         rtl_writephy(tp, 0x13, 0x80d7);
4121         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4122
4123         /* Force PWM-mode */
4124         rtl_writephy(tp, 0x1f, 0x0bcd);
4125         rtl_writephy(tp, 0x14, 0x5065);
4126         rtl_writephy(tp, 0x14, 0xd065);
4127         rtl_writephy(tp, 0x1f, 0x0bc8);
4128         rtl_writephy(tp, 0x12, 0x00ed);
4129         rtl_writephy(tp, 0x1f, 0x0bcd);
4130         rtl_writephy(tp, 0x14, 0x1065);
4131         rtl_writephy(tp, 0x14, 0x9065);
4132         rtl_writephy(tp, 0x14, 0x1065);
4133         rtl_writephy(tp, 0x1f, 0x0000);
4134
4135         /* Check ALDPS bit, disable it if enabled */
4136         rtl_writephy(tp, 0x1f, 0x0a43);
4137         if (rtl_readphy(tp, 0x10) & 0x0004)
4138                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4139
4140         rtl_writephy(tp, 0x1f, 0x0000);
4141 }
4142
4143 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4144 {
4145         static const struct phy_reg phy_reg_init[] = {
4146                 { 0x1f, 0x0003 },
4147                 { 0x08, 0x441d },
4148                 { 0x01, 0x9100 },
4149                 { 0x1f, 0x0000 }
4150         };
4151
4152         rtl_writephy(tp, 0x1f, 0x0000);
4153         rtl_patchphy(tp, 0x11, 1 << 12);
4154         rtl_patchphy(tp, 0x19, 1 << 13);
4155         rtl_patchphy(tp, 0x10, 1 << 15);
4156
4157         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4158 }
4159
4160 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4161 {
4162         static const struct phy_reg phy_reg_init[] = {
4163                 { 0x1f, 0x0005 },
4164                 { 0x1a, 0x0000 },
4165                 { 0x1f, 0x0000 },
4166
4167                 { 0x1f, 0x0004 },
4168                 { 0x1c, 0x0000 },
4169                 { 0x1f, 0x0000 },
4170
4171                 { 0x1f, 0x0001 },
4172                 { 0x15, 0x7701 },
4173                 { 0x1f, 0x0000 }
4174         };
4175
4176         /* Disable ALDPS before ram code */
4177         rtl_writephy(tp, 0x1f, 0x0000);
4178         rtl_writephy(tp, 0x18, 0x0310);
4179         msleep(100);
4180
4181         rtl_apply_firmware(tp);
4182
4183         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4184 }
4185
4186 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4187 {
4188         /* Disable ALDPS before setting firmware */
4189         rtl_writephy(tp, 0x1f, 0x0000);
4190         rtl_writephy(tp, 0x18, 0x0310);
4191         msleep(20);
4192
4193         rtl_apply_firmware(tp);
4194
4195         /* EEE setting */
4196         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4197         rtl_writephy(tp, 0x1f, 0x0004);
4198         rtl_writephy(tp, 0x10, 0x401f);
4199         rtl_writephy(tp, 0x19, 0x7030);
4200         rtl_writephy(tp, 0x1f, 0x0000);
4201 }
4202
4203 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4204 {
4205         static const struct phy_reg phy_reg_init[] = {
4206                 { 0x1f, 0x0004 },
4207                 { 0x10, 0xc07f },
4208                 { 0x19, 0x7030 },
4209                 { 0x1f, 0x0000 }
4210         };
4211
4212         /* Disable ALDPS before ram code */
4213         rtl_writephy(tp, 0x1f, 0x0000);
4214         rtl_writephy(tp, 0x18, 0x0310);
4215         msleep(100);
4216
4217         rtl_apply_firmware(tp);
4218
4219         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4220         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4221
4222         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4223 }
4224
4225 static void rtl_hw_phy_config(struct net_device *dev)
4226 {
4227         struct rtl8169_private *tp = netdev_priv(dev);
4228
4229         rtl8169_print_mac_version(tp);
4230
4231         switch (tp->mac_version) {
4232         case RTL_GIGA_MAC_VER_01:
4233                 break;
4234         case RTL_GIGA_MAC_VER_02:
4235         case RTL_GIGA_MAC_VER_03:
4236                 rtl8169s_hw_phy_config(tp);
4237                 break;
4238         case RTL_GIGA_MAC_VER_04:
4239                 rtl8169sb_hw_phy_config(tp);
4240                 break;
4241         case RTL_GIGA_MAC_VER_05:
4242                 rtl8169scd_hw_phy_config(tp);
4243                 break;
4244         case RTL_GIGA_MAC_VER_06:
4245                 rtl8169sce_hw_phy_config(tp);
4246                 break;
4247         case RTL_GIGA_MAC_VER_07:
4248         case RTL_GIGA_MAC_VER_08:
4249         case RTL_GIGA_MAC_VER_09:
4250                 rtl8102e_hw_phy_config(tp);
4251                 break;
4252         case RTL_GIGA_MAC_VER_11:
4253                 rtl8168bb_hw_phy_config(tp);
4254                 break;
4255         case RTL_GIGA_MAC_VER_12:
4256                 rtl8168bef_hw_phy_config(tp);
4257                 break;
4258         case RTL_GIGA_MAC_VER_17:
4259                 rtl8168bef_hw_phy_config(tp);
4260                 break;
4261         case RTL_GIGA_MAC_VER_18:
4262                 rtl8168cp_1_hw_phy_config(tp);
4263                 break;
4264         case RTL_GIGA_MAC_VER_19:
4265                 rtl8168c_1_hw_phy_config(tp);
4266                 break;
4267         case RTL_GIGA_MAC_VER_20:
4268                 rtl8168c_2_hw_phy_config(tp);
4269                 break;
4270         case RTL_GIGA_MAC_VER_21:
4271                 rtl8168c_3_hw_phy_config(tp);
4272                 break;
4273         case RTL_GIGA_MAC_VER_22:
4274                 rtl8168c_4_hw_phy_config(tp);
4275                 break;
4276         case RTL_GIGA_MAC_VER_23:
4277         case RTL_GIGA_MAC_VER_24:
4278                 rtl8168cp_2_hw_phy_config(tp);
4279                 break;
4280         case RTL_GIGA_MAC_VER_25:
4281                 rtl8168d_1_hw_phy_config(tp);
4282                 break;
4283         case RTL_GIGA_MAC_VER_26:
4284                 rtl8168d_2_hw_phy_config(tp);
4285                 break;
4286         case RTL_GIGA_MAC_VER_27:
4287                 rtl8168d_3_hw_phy_config(tp);
4288                 break;
4289         case RTL_GIGA_MAC_VER_28:
4290                 rtl8168d_4_hw_phy_config(tp);
4291                 break;
4292         case RTL_GIGA_MAC_VER_29:
4293         case RTL_GIGA_MAC_VER_30:
4294                 rtl8105e_hw_phy_config(tp);
4295                 break;
4296         case RTL_GIGA_MAC_VER_31:
4297                 /* None. */
4298                 break;
4299         case RTL_GIGA_MAC_VER_32:
4300         case RTL_GIGA_MAC_VER_33:
4301                 rtl8168e_1_hw_phy_config(tp);
4302                 break;
4303         case RTL_GIGA_MAC_VER_34:
4304                 rtl8168e_2_hw_phy_config(tp);
4305                 break;
4306         case RTL_GIGA_MAC_VER_35:
4307                 rtl8168f_1_hw_phy_config(tp);
4308                 break;
4309         case RTL_GIGA_MAC_VER_36:
4310                 rtl8168f_2_hw_phy_config(tp);
4311                 break;
4312
4313         case RTL_GIGA_MAC_VER_37:
4314                 rtl8402_hw_phy_config(tp);
4315                 break;
4316
4317         case RTL_GIGA_MAC_VER_38:
4318                 rtl8411_hw_phy_config(tp);
4319                 break;
4320
4321         case RTL_GIGA_MAC_VER_39:
4322                 rtl8106e_hw_phy_config(tp);
4323                 break;
4324
4325         case RTL_GIGA_MAC_VER_40:
4326                 rtl8168g_1_hw_phy_config(tp);
4327                 break;
4328         case RTL_GIGA_MAC_VER_42:
4329         case RTL_GIGA_MAC_VER_43:
4330         case RTL_GIGA_MAC_VER_44:
4331                 rtl8168g_2_hw_phy_config(tp);
4332                 break;
4333         case RTL_GIGA_MAC_VER_45:
4334         case RTL_GIGA_MAC_VER_47:
4335                 rtl8168h_1_hw_phy_config(tp);
4336                 break;
4337         case RTL_GIGA_MAC_VER_46:
4338         case RTL_GIGA_MAC_VER_48:
4339                 rtl8168h_2_hw_phy_config(tp);
4340                 break;
4341
4342         case RTL_GIGA_MAC_VER_49:
4343                 rtl8168ep_1_hw_phy_config(tp);
4344                 break;
4345         case RTL_GIGA_MAC_VER_50:
4346         case RTL_GIGA_MAC_VER_51:
4347                 rtl8168ep_2_hw_phy_config(tp);
4348                 break;
4349
4350         case RTL_GIGA_MAC_VER_41:
4351         default:
4352                 break;
4353         }
4354 }
4355
4356 static void rtl_phy_work(struct rtl8169_private *tp)
4357 {
4358         struct timer_list *timer = &tp->timer;
4359         void __iomem *ioaddr = tp->mmio_addr;
4360         unsigned long timeout = RTL8169_PHY_TIMEOUT;
4361
4362         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4363
4364         if (tp->phy_reset_pending(tp)) {
4365                 /*
4366                  * A busy loop could burn quite a few cycles on nowadays CPU.
4367                  * Let's delay the execution of the timer for a few ticks.
4368                  */
4369                 timeout = HZ/10;
4370                 goto out_mod_timer;
4371         }
4372
4373         if (tp->link_ok(ioaddr))
4374                 return;
4375
4376         netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4377
4378         tp->phy_reset_enable(tp);
4379
4380 out_mod_timer:
4381         mod_timer(timer, jiffies + timeout);
4382 }
4383
4384 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4385 {
4386         if (!test_and_set_bit(flag, tp->wk.flags))
4387                 schedule_work(&tp->wk.work);
4388 }
4389
4390 static void rtl8169_phy_timer(unsigned long __opaque)
4391 {
4392         struct net_device *dev = (struct net_device *)__opaque;
4393         struct rtl8169_private *tp = netdev_priv(dev);
4394
4395         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4396 }
4397
4398 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4399                                   void __iomem *ioaddr)
4400 {
4401         iounmap(ioaddr);
4402         pci_release_regions(pdev);
4403         pci_clear_mwi(pdev);
4404         pci_disable_device(pdev);
4405         free_netdev(dev);
4406 }
4407
4408 DECLARE_RTL_COND(rtl_phy_reset_cond)
4409 {
4410         return tp->phy_reset_pending(tp);
4411 }
4412
4413 static void rtl8169_phy_reset(struct net_device *dev,
4414                               struct rtl8169_private *tp)
4415 {
4416         tp->phy_reset_enable(tp);
4417         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4418 }
4419
4420 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4421 {
4422         void __iomem *ioaddr = tp->mmio_addr;
4423
4424         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4425             (RTL_R8(PHYstatus) & TBI_Enable);
4426 }
4427
4428 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4429 {
4430         void __iomem *ioaddr = tp->mmio_addr;
4431
4432         rtl_hw_phy_config(dev);
4433
4434         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4435                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4436                 RTL_W8(0x82, 0x01);
4437         }
4438
4439         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4440
4441         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4442                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4443
4444         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4445                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4446                 RTL_W8(0x82, 0x01);
4447                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4448                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4449         }
4450
4451         rtl8169_phy_reset(dev, tp);
4452
4453         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4454                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4455                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4456                           (tp->mii.supports_gmii ?
4457                            ADVERTISED_1000baseT_Half |
4458                            ADVERTISED_1000baseT_Full : 0));
4459
4460         if (rtl_tbi_enabled(tp))
4461                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4462 }
4463
4464 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4465 {
4466         void __iomem *ioaddr = tp->mmio_addr;
4467
4468         rtl_lock_work(tp);
4469
4470         RTL_W8(Cfg9346, Cfg9346_Unlock);
4471
4472         RTL_W32(MAC4, addr[4] | addr[5] << 8);
4473         RTL_R32(MAC4);
4474
4475         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4476         RTL_R32(MAC0);
4477
4478         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4479                 rtl_rar_exgmac_set(tp, addr);
4480
4481         RTL_W8(Cfg9346, Cfg9346_Lock);
4482
4483         rtl_unlock_work(tp);
4484 }
4485
4486 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4487 {
4488         void __iomem *ioaddr = tp->mmio_addr;
4489
4490         switch (tp->mac_version) {
4491         case RTL_GIGA_MAC_VER_01:
4492         case RTL_GIGA_MAC_VER_02:
4493         case RTL_GIGA_MAC_VER_03:
4494         case RTL_GIGA_MAC_VER_04:
4495         case RTL_GIGA_MAC_VER_05:
4496         case RTL_GIGA_MAC_VER_06:
4497         case RTL_GIGA_MAC_VER_10:
4498         case RTL_GIGA_MAC_VER_11:
4499         case RTL_GIGA_MAC_VER_12:
4500         case RTL_GIGA_MAC_VER_13:
4501         case RTL_GIGA_MAC_VER_14:
4502         case RTL_GIGA_MAC_VER_15:
4503         case RTL_GIGA_MAC_VER_16:
4504         case RTL_GIGA_MAC_VER_17:
4505                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4506                 break;
4507         case RTL_GIGA_MAC_VER_18:
4508         case RTL_GIGA_MAC_VER_19:
4509         case RTL_GIGA_MAC_VER_20:
4510         case RTL_GIGA_MAC_VER_21:
4511         case RTL_GIGA_MAC_VER_22:
4512         case RTL_GIGA_MAC_VER_23:
4513         case RTL_GIGA_MAC_VER_24:
4514         case RTL_GIGA_MAC_VER_34:
4515         case RTL_GIGA_MAC_VER_35:
4516                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4517                 break;
4518         case RTL_GIGA_MAC_VER_40:
4519         case RTL_GIGA_MAC_VER_41:
4520         case RTL_GIGA_MAC_VER_42:
4521         case RTL_GIGA_MAC_VER_43:
4522         case RTL_GIGA_MAC_VER_44:
4523         case RTL_GIGA_MAC_VER_45:
4524         case RTL_GIGA_MAC_VER_46:
4525         case RTL_GIGA_MAC_VER_47:
4526         case RTL_GIGA_MAC_VER_48:
4527         case RTL_GIGA_MAC_VER_49:
4528         case RTL_GIGA_MAC_VER_50:
4529         case RTL_GIGA_MAC_VER_51:
4530                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4531                 break;
4532         default:
4533                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4534                 break;
4535         }
4536 }
4537
4538 static int rtl_set_mac_address(struct net_device *dev, void *p)
4539 {
4540         struct rtl8169_private *tp = netdev_priv(dev);
4541         struct device *d = &tp->pci_dev->dev;
4542         struct sockaddr *addr = p;
4543
4544         if (!is_valid_ether_addr(addr->sa_data))
4545                 return -EADDRNOTAVAIL;
4546
4547         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4548
4549         pm_runtime_get_noresume(d);
4550
4551         if (pm_runtime_active(d))
4552                 rtl_rar_set(tp, dev->dev_addr);
4553
4554         pm_runtime_put_noidle(d);
4555
4556         /* Reportedly at least Asus X453MA truncates packets otherwise */
4557         if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4558                 rtl_init_rxcfg(tp);
4559
4560         return 0;
4561 }
4562
4563 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4564 {
4565         struct rtl8169_private *tp = netdev_priv(dev);
4566         struct mii_ioctl_data *data = if_mii(ifr);
4567
4568         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4569 }
4570
4571 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4572                           struct mii_ioctl_data *data, int cmd)
4573 {
4574         switch (cmd) {
4575         case SIOCGMIIPHY:
4576                 data->phy_id = 32; /* Internal PHY */
4577                 return 0;
4578
4579         case SIOCGMIIREG:
4580                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4581                 return 0;
4582
4583         case SIOCSMIIREG:
4584                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4585                 return 0;
4586         }
4587         return -EOPNOTSUPP;
4588 }
4589
4590 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4591 {
4592         return -EOPNOTSUPP;
4593 }
4594
4595 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4596 {
4597         if (tp->features & RTL_FEATURE_MSI) {
4598                 pci_disable_msi(pdev);
4599                 tp->features &= ~RTL_FEATURE_MSI;
4600         }
4601 }
4602
4603 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4604 {
4605         struct mdio_ops *ops = &tp->mdio_ops;
4606
4607         switch (tp->mac_version) {
4608         case RTL_GIGA_MAC_VER_27:
4609                 ops->write      = r8168dp_1_mdio_write;
4610                 ops->read       = r8168dp_1_mdio_read;
4611                 break;
4612         case RTL_GIGA_MAC_VER_28:
4613         case RTL_GIGA_MAC_VER_31:
4614                 ops->write      = r8168dp_2_mdio_write;
4615                 ops->read       = r8168dp_2_mdio_read;
4616                 break;
4617         case RTL_GIGA_MAC_VER_40:
4618         case RTL_GIGA_MAC_VER_41:
4619         case RTL_GIGA_MAC_VER_42:
4620         case RTL_GIGA_MAC_VER_43:
4621         case RTL_GIGA_MAC_VER_44:
4622         case RTL_GIGA_MAC_VER_45:
4623         case RTL_GIGA_MAC_VER_46:
4624         case RTL_GIGA_MAC_VER_47:
4625         case RTL_GIGA_MAC_VER_48:
4626         case RTL_GIGA_MAC_VER_49:
4627         case RTL_GIGA_MAC_VER_50:
4628         case RTL_GIGA_MAC_VER_51:
4629                 ops->write      = r8168g_mdio_write;
4630                 ops->read       = r8168g_mdio_read;
4631                 break;
4632         default:
4633                 ops->write      = r8169_mdio_write;
4634                 ops->read       = r8169_mdio_read;
4635                 break;
4636         }
4637 }
4638
4639 static void rtl_speed_down(struct rtl8169_private *tp)
4640 {
4641         u32 adv;
4642         int lpa;
4643
4644         rtl_writephy(tp, 0x1f, 0x0000);
4645         lpa = rtl_readphy(tp, MII_LPA);
4646
4647         if (lpa & (LPA_10HALF | LPA_10FULL))
4648                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4649         else if (lpa & (LPA_100HALF | LPA_100FULL))
4650                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4651                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4652         else
4653                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4654                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4655                       (tp->mii.supports_gmii ?
4656                        ADVERTISED_1000baseT_Half |
4657                        ADVERTISED_1000baseT_Full : 0);
4658
4659         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4660                           adv);
4661 }
4662
4663 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4664 {
4665         void __iomem *ioaddr = tp->mmio_addr;
4666
4667         switch (tp->mac_version) {
4668         case RTL_GIGA_MAC_VER_25:
4669         case RTL_GIGA_MAC_VER_26:
4670         case RTL_GIGA_MAC_VER_29:
4671         case RTL_GIGA_MAC_VER_30:
4672         case RTL_GIGA_MAC_VER_32:
4673         case RTL_GIGA_MAC_VER_33:
4674         case RTL_GIGA_MAC_VER_34:
4675         case RTL_GIGA_MAC_VER_37:
4676         case RTL_GIGA_MAC_VER_38:
4677         case RTL_GIGA_MAC_VER_39:
4678         case RTL_GIGA_MAC_VER_40:
4679         case RTL_GIGA_MAC_VER_41:
4680         case RTL_GIGA_MAC_VER_42:
4681         case RTL_GIGA_MAC_VER_43:
4682         case RTL_GIGA_MAC_VER_44:
4683         case RTL_GIGA_MAC_VER_45:
4684         case RTL_GIGA_MAC_VER_46:
4685         case RTL_GIGA_MAC_VER_47:
4686         case RTL_GIGA_MAC_VER_48:
4687         case RTL_GIGA_MAC_VER_49:
4688         case RTL_GIGA_MAC_VER_50:
4689         case RTL_GIGA_MAC_VER_51:
4690                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4691                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4692                 break;
4693         default:
4694                 break;
4695         }
4696 }
4697
4698 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4699 {
4700         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4701                 return false;
4702
4703         rtl_speed_down(tp);
4704         rtl_wol_suspend_quirk(tp);
4705
4706         return true;
4707 }
4708
4709 static void r810x_phy_power_down(struct rtl8169_private *tp)
4710 {
4711         rtl_writephy(tp, 0x1f, 0x0000);
4712         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4713 }
4714
4715 static void r810x_phy_power_up(struct rtl8169_private *tp)
4716 {
4717         rtl_writephy(tp, 0x1f, 0x0000);
4718         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4719 }
4720
4721 static void r810x_pll_power_down(struct rtl8169_private *tp)
4722 {
4723         void __iomem *ioaddr = tp->mmio_addr;
4724
4725         if (rtl_wol_pll_power_down(tp))
4726                 return;
4727
4728         r810x_phy_power_down(tp);
4729
4730         switch (tp->mac_version) {
4731         case RTL_GIGA_MAC_VER_07:
4732         case RTL_GIGA_MAC_VER_08:
4733         case RTL_GIGA_MAC_VER_09:
4734         case RTL_GIGA_MAC_VER_10:
4735         case RTL_GIGA_MAC_VER_13:
4736         case RTL_GIGA_MAC_VER_16:
4737                 break;
4738         default:
4739                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4740                 break;
4741         }
4742 }
4743
4744 static void r810x_pll_power_up(struct rtl8169_private *tp)
4745 {
4746         void __iomem *ioaddr = tp->mmio_addr;
4747
4748         r810x_phy_power_up(tp);
4749
4750         switch (tp->mac_version) {
4751         case RTL_GIGA_MAC_VER_07:
4752         case RTL_GIGA_MAC_VER_08:
4753         case RTL_GIGA_MAC_VER_09:
4754         case RTL_GIGA_MAC_VER_10:
4755         case RTL_GIGA_MAC_VER_13:
4756         case RTL_GIGA_MAC_VER_16:
4757                 break;
4758         case RTL_GIGA_MAC_VER_47:
4759         case RTL_GIGA_MAC_VER_48:
4760                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4761                 break;
4762         default:
4763                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4764                 break;
4765         }
4766 }
4767
4768 static void r8168_phy_power_up(struct rtl8169_private *tp)
4769 {
4770         rtl_writephy(tp, 0x1f, 0x0000);
4771         switch (tp->mac_version) {
4772         case RTL_GIGA_MAC_VER_11:
4773         case RTL_GIGA_MAC_VER_12:
4774         case RTL_GIGA_MAC_VER_17:
4775         case RTL_GIGA_MAC_VER_18:
4776         case RTL_GIGA_MAC_VER_19:
4777         case RTL_GIGA_MAC_VER_20:
4778         case RTL_GIGA_MAC_VER_21:
4779         case RTL_GIGA_MAC_VER_22:
4780         case RTL_GIGA_MAC_VER_23:
4781         case RTL_GIGA_MAC_VER_24:
4782         case RTL_GIGA_MAC_VER_25:
4783         case RTL_GIGA_MAC_VER_26:
4784         case RTL_GIGA_MAC_VER_27:
4785         case RTL_GIGA_MAC_VER_28:
4786         case RTL_GIGA_MAC_VER_31:
4787                 rtl_writephy(tp, 0x0e, 0x0000);
4788                 break;
4789         default:
4790                 break;
4791         }
4792         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4793 }
4794
4795 static void r8168_phy_power_down(struct rtl8169_private *tp)
4796 {
4797         rtl_writephy(tp, 0x1f, 0x0000);
4798         switch (tp->mac_version) {
4799         case RTL_GIGA_MAC_VER_32:
4800         case RTL_GIGA_MAC_VER_33:
4801         case RTL_GIGA_MAC_VER_40:
4802         case RTL_GIGA_MAC_VER_41:
4803                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4804                 break;
4805
4806         case RTL_GIGA_MAC_VER_11:
4807         case RTL_GIGA_MAC_VER_12:
4808         case RTL_GIGA_MAC_VER_17:
4809         case RTL_GIGA_MAC_VER_18:
4810         case RTL_GIGA_MAC_VER_19:
4811         case RTL_GIGA_MAC_VER_20:
4812         case RTL_GIGA_MAC_VER_21:
4813         case RTL_GIGA_MAC_VER_22:
4814         case RTL_GIGA_MAC_VER_23:
4815         case RTL_GIGA_MAC_VER_24:
4816         case RTL_GIGA_MAC_VER_25:
4817         case RTL_GIGA_MAC_VER_26:
4818         case RTL_GIGA_MAC_VER_27:
4819         case RTL_GIGA_MAC_VER_28:
4820         case RTL_GIGA_MAC_VER_31:
4821                 rtl_writephy(tp, 0x0e, 0x0200);
4822         default:
4823                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4824                 break;
4825         }
4826 }
4827
4828 static void r8168_pll_power_down(struct rtl8169_private *tp)
4829 {
4830         void __iomem *ioaddr = tp->mmio_addr;
4831
4832         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4833              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4834              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4835              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4836              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4837              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4838             r8168_check_dash(tp)) {
4839                 return;
4840         }
4841
4842         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4843              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4844             (RTL_R16(CPlusCmd) & ASF)) {
4845                 return;
4846         }
4847
4848         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4849             tp->mac_version == RTL_GIGA_MAC_VER_33)
4850                 rtl_ephy_write(tp, 0x19, 0xff64);
4851
4852         if (rtl_wol_pll_power_down(tp))
4853                 return;
4854
4855         r8168_phy_power_down(tp);
4856
4857         switch (tp->mac_version) {
4858         case RTL_GIGA_MAC_VER_25:
4859         case RTL_GIGA_MAC_VER_26:
4860         case RTL_GIGA_MAC_VER_27:
4861         case RTL_GIGA_MAC_VER_28:
4862         case RTL_GIGA_MAC_VER_31:
4863         case RTL_GIGA_MAC_VER_32:
4864         case RTL_GIGA_MAC_VER_33:
4865         case RTL_GIGA_MAC_VER_44:
4866         case RTL_GIGA_MAC_VER_45:
4867         case RTL_GIGA_MAC_VER_46:
4868         case RTL_GIGA_MAC_VER_50:
4869         case RTL_GIGA_MAC_VER_51:
4870                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4871                 break;
4872         case RTL_GIGA_MAC_VER_40:
4873         case RTL_GIGA_MAC_VER_41:
4874         case RTL_GIGA_MAC_VER_49:
4875                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4876                              0xfc000000, ERIAR_EXGMAC);
4877                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4878                 break;
4879         }
4880 }
4881
4882 static void r8168_pll_power_up(struct rtl8169_private *tp)
4883 {
4884         void __iomem *ioaddr = tp->mmio_addr;
4885
4886         switch (tp->mac_version) {
4887         case RTL_GIGA_MAC_VER_25:
4888         case RTL_GIGA_MAC_VER_26:
4889         case RTL_GIGA_MAC_VER_27:
4890         case RTL_GIGA_MAC_VER_28:
4891         case RTL_GIGA_MAC_VER_31:
4892         case RTL_GIGA_MAC_VER_32:
4893         case RTL_GIGA_MAC_VER_33:
4894                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4895                 break;
4896         case RTL_GIGA_MAC_VER_44:
4897         case RTL_GIGA_MAC_VER_45:
4898         case RTL_GIGA_MAC_VER_46:
4899         case RTL_GIGA_MAC_VER_50:
4900         case RTL_GIGA_MAC_VER_51:
4901                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4902                 break;
4903         case RTL_GIGA_MAC_VER_40:
4904         case RTL_GIGA_MAC_VER_41:
4905         case RTL_GIGA_MAC_VER_49:
4906                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4907                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4908                              0x00000000, ERIAR_EXGMAC);
4909                 break;
4910         }
4911
4912         r8168_phy_power_up(tp);
4913 }
4914
4915 static void rtl_generic_op(struct rtl8169_private *tp,
4916                            void (*op)(struct rtl8169_private *))
4917 {
4918         if (op)
4919                 op(tp);
4920 }
4921
4922 static void rtl_pll_power_down(struct rtl8169_private *tp)
4923 {
4924         rtl_generic_op(tp, tp->pll_power_ops.down);
4925 }
4926
4927 static void rtl_pll_power_up(struct rtl8169_private *tp)
4928 {
4929         rtl_generic_op(tp, tp->pll_power_ops.up);
4930
4931         /* give MAC/PHY some time to resume */
4932         msleep(20);
4933 }
4934
4935 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4936 {
4937         struct pll_power_ops *ops = &tp->pll_power_ops;
4938
4939         switch (tp->mac_version) {
4940         case RTL_GIGA_MAC_VER_07:
4941         case RTL_GIGA_MAC_VER_08:
4942         case RTL_GIGA_MAC_VER_09:
4943         case RTL_GIGA_MAC_VER_10:
4944         case RTL_GIGA_MAC_VER_16:
4945         case RTL_GIGA_MAC_VER_29:
4946         case RTL_GIGA_MAC_VER_30:
4947         case RTL_GIGA_MAC_VER_37:
4948         case RTL_GIGA_MAC_VER_39:
4949         case RTL_GIGA_MAC_VER_43:
4950         case RTL_GIGA_MAC_VER_47:
4951         case RTL_GIGA_MAC_VER_48:
4952                 ops->down       = r810x_pll_power_down;
4953                 ops->up         = r810x_pll_power_up;
4954                 break;
4955
4956         case RTL_GIGA_MAC_VER_11:
4957         case RTL_GIGA_MAC_VER_12:
4958         case RTL_GIGA_MAC_VER_17:
4959         case RTL_GIGA_MAC_VER_18:
4960         case RTL_GIGA_MAC_VER_19:
4961         case RTL_GIGA_MAC_VER_20:
4962         case RTL_GIGA_MAC_VER_21:
4963         case RTL_GIGA_MAC_VER_22:
4964         case RTL_GIGA_MAC_VER_23:
4965         case RTL_GIGA_MAC_VER_24:
4966         case RTL_GIGA_MAC_VER_25:
4967         case RTL_GIGA_MAC_VER_26:
4968         case RTL_GIGA_MAC_VER_27:
4969         case RTL_GIGA_MAC_VER_28:
4970         case RTL_GIGA_MAC_VER_31:
4971         case RTL_GIGA_MAC_VER_32:
4972         case RTL_GIGA_MAC_VER_33:
4973         case RTL_GIGA_MAC_VER_34:
4974         case RTL_GIGA_MAC_VER_35:
4975         case RTL_GIGA_MAC_VER_36:
4976         case RTL_GIGA_MAC_VER_38:
4977         case RTL_GIGA_MAC_VER_40:
4978         case RTL_GIGA_MAC_VER_41:
4979         case RTL_GIGA_MAC_VER_42:
4980         case RTL_GIGA_MAC_VER_44:
4981         case RTL_GIGA_MAC_VER_45:
4982         case RTL_GIGA_MAC_VER_46:
4983         case RTL_GIGA_MAC_VER_49:
4984         case RTL_GIGA_MAC_VER_50:
4985         case RTL_GIGA_MAC_VER_51:
4986                 ops->down       = r8168_pll_power_down;
4987                 ops->up         = r8168_pll_power_up;
4988                 break;
4989
4990         default:
4991                 ops->down       = NULL;
4992                 ops->up         = NULL;
4993                 break;
4994         }
4995 }
4996
4997 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4998 {
4999         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
5000 }
5001
5002 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
5003 {
5004         void __iomem *ioaddr = tp->mmio_addr;
5005
5006         RTL_W8(Cfg9346, Cfg9346_Unlock);
5007         rtl_generic_op(tp, tp->jumbo_ops.enable);
5008         RTL_W8(Cfg9346, Cfg9346_Lock);
5009 }
5010
5011 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
5012 {
5013         void __iomem *ioaddr = tp->mmio_addr;
5014
5015         RTL_W8(Cfg9346, Cfg9346_Unlock);
5016         rtl_generic_op(tp, tp->jumbo_ops.disable);
5017         RTL_W8(Cfg9346, Cfg9346_Lock);
5018 }
5019
5020 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5021 {
5022         void __iomem *ioaddr = tp->mmio_addr;
5023
5024         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5025         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
5026         rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5027 }
5028
5029 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5030 {
5031         void __iomem *ioaddr = tp->mmio_addr;
5032
5033         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5034         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
5035         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5036 }
5037
5038 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5039 {
5040         void __iomem *ioaddr = tp->mmio_addr;
5041
5042         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5043 }
5044
5045 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5046 {
5047         void __iomem *ioaddr = tp->mmio_addr;
5048
5049         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5050 }
5051
5052 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5053 {
5054         void __iomem *ioaddr = tp->mmio_addr;
5055
5056         RTL_W8(MaxTxPacketSize, 0x3f);
5057         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5058         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
5059         rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5060 }
5061
5062 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5063 {
5064         void __iomem *ioaddr = tp->mmio_addr;
5065
5066         RTL_W8(MaxTxPacketSize, 0x0c);
5067         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5068         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
5069         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5070 }
5071
5072 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5073 {
5074         rtl_tx_performance_tweak(tp->pci_dev,
5075                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5076 }
5077
5078 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5079 {
5080         rtl_tx_performance_tweak(tp->pci_dev,
5081                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5082 }
5083
5084 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5085 {
5086         void __iomem *ioaddr = tp->mmio_addr;
5087
5088         r8168b_0_hw_jumbo_enable(tp);
5089
5090         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5091 }
5092
5093 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5094 {
5095         void __iomem *ioaddr = tp->mmio_addr;
5096
5097         r8168b_0_hw_jumbo_disable(tp);
5098
5099         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5100 }
5101
5102 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5103 {
5104         struct jumbo_ops *ops = &tp->jumbo_ops;
5105
5106         switch (tp->mac_version) {
5107         case RTL_GIGA_MAC_VER_11:
5108                 ops->disable    = r8168b_0_hw_jumbo_disable;
5109                 ops->enable     = r8168b_0_hw_jumbo_enable;
5110                 break;
5111         case RTL_GIGA_MAC_VER_12:
5112         case RTL_GIGA_MAC_VER_17:
5113                 ops->disable    = r8168b_1_hw_jumbo_disable;
5114                 ops->enable     = r8168b_1_hw_jumbo_enable;
5115                 break;
5116         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5117         case RTL_GIGA_MAC_VER_19:
5118         case RTL_GIGA_MAC_VER_20:
5119         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5120         case RTL_GIGA_MAC_VER_22:
5121         case RTL_GIGA_MAC_VER_23:
5122         case RTL_GIGA_MAC_VER_24:
5123         case RTL_GIGA_MAC_VER_25:
5124         case RTL_GIGA_MAC_VER_26:
5125                 ops->disable    = r8168c_hw_jumbo_disable;
5126                 ops->enable     = r8168c_hw_jumbo_enable;
5127                 break;
5128         case RTL_GIGA_MAC_VER_27:
5129         case RTL_GIGA_MAC_VER_28:
5130                 ops->disable    = r8168dp_hw_jumbo_disable;
5131                 ops->enable     = r8168dp_hw_jumbo_enable;
5132                 break;
5133         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5134         case RTL_GIGA_MAC_VER_32:
5135         case RTL_GIGA_MAC_VER_33:
5136         case RTL_GIGA_MAC_VER_34:
5137                 ops->disable    = r8168e_hw_jumbo_disable;
5138                 ops->enable     = r8168e_hw_jumbo_enable;
5139                 break;
5140
5141         /*
5142          * No action needed for jumbo frames with 8169.
5143          * No jumbo for 810x at all.
5144          */
5145         case RTL_GIGA_MAC_VER_40:
5146         case RTL_GIGA_MAC_VER_41:
5147         case RTL_GIGA_MAC_VER_42:
5148         case RTL_GIGA_MAC_VER_43:
5149         case RTL_GIGA_MAC_VER_44:
5150         case RTL_GIGA_MAC_VER_45:
5151         case RTL_GIGA_MAC_VER_46:
5152         case RTL_GIGA_MAC_VER_47:
5153         case RTL_GIGA_MAC_VER_48:
5154         case RTL_GIGA_MAC_VER_49:
5155         case RTL_GIGA_MAC_VER_50:
5156         case RTL_GIGA_MAC_VER_51:
5157         default:
5158                 ops->disable    = NULL;
5159                 ops->enable     = NULL;
5160                 break;
5161         }
5162 }
5163
5164 DECLARE_RTL_COND(rtl_chipcmd_cond)
5165 {
5166         void __iomem *ioaddr = tp->mmio_addr;
5167
5168         return RTL_R8(ChipCmd) & CmdReset;
5169 }
5170
5171 static void rtl_hw_reset(struct rtl8169_private *tp)
5172 {
5173         void __iomem *ioaddr = tp->mmio_addr;
5174
5175         RTL_W8(ChipCmd, CmdReset);
5176
5177         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5178 }
5179
5180 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5181 {
5182         struct rtl_fw *rtl_fw;
5183         const char *name;
5184         int rc = -ENOMEM;
5185
5186         name = rtl_lookup_firmware_name(tp);
5187         if (!name)
5188                 goto out_no_firmware;
5189
5190         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5191         if (!rtl_fw)
5192                 goto err_warn;
5193
5194         rc = reject_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5195         if (rc < 0)
5196                 goto err_free;
5197
5198         rc = rtl_check_firmware(tp, rtl_fw);
5199         if (rc < 0)
5200                 goto err_release_firmware;
5201
5202         tp->rtl_fw = rtl_fw;
5203 out:
5204         return;
5205
5206 err_release_firmware:
5207         release_firmware(rtl_fw->fw);
5208 err_free:
5209         kfree(rtl_fw);
5210 err_warn:
5211         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5212                    name, rc);
5213 out_no_firmware:
5214         tp->rtl_fw = NULL;
5215         goto out;
5216 }
5217
5218 static void rtl_request_firmware(struct rtl8169_private *tp)
5219 {
5220         if (IS_ERR(tp->rtl_fw))
5221                 rtl_request_uncached_firmware(tp);
5222 }
5223
5224 static void rtl_rx_close(struct rtl8169_private *tp)
5225 {
5226         void __iomem *ioaddr = tp->mmio_addr;
5227
5228         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5229 }
5230
5231 DECLARE_RTL_COND(rtl_npq_cond)
5232 {
5233         void __iomem *ioaddr = tp->mmio_addr;
5234
5235         return RTL_R8(TxPoll) & NPQ;
5236 }
5237
5238 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5239 {
5240         void __iomem *ioaddr = tp->mmio_addr;
5241
5242         return RTL_R32(TxConfig) & TXCFG_EMPTY;
5243 }
5244
5245 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5246 {
5247         void __iomem *ioaddr = tp->mmio_addr;
5248
5249         /* Disable interrupts */
5250         rtl8169_irq_mask_and_ack(tp);
5251
5252         rtl_rx_close(tp);
5253
5254         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5255             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5256             tp->mac_version == RTL_GIGA_MAC_VER_31) {
5257                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5258         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5259                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5260                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5261                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5262                    tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5263                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5264                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5265                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5266                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5267                    tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5268                    tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5269                    tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5270                    tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5271                    tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5272                    tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5273                    tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5274                    tp->mac_version == RTL_GIGA_MAC_VER_51) {
5275                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5276                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5277         } else {
5278                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5279                 udelay(100);
5280         }
5281
5282         rtl_hw_reset(tp);
5283 }
5284
5285 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5286 {
5287         void __iomem *ioaddr = tp->mmio_addr;
5288
5289         /* Set DMA burst size and Interframe Gap Time */
5290         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5291                 (InterFrameGap << TxInterFrameGapShift));
5292 }
5293
5294 static void rtl_hw_start(struct net_device *dev)
5295 {
5296         struct rtl8169_private *tp = netdev_priv(dev);
5297
5298         tp->hw_start(dev);
5299
5300         rtl_irq_enable_all(tp);
5301 }
5302
5303 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5304                                          void __iomem *ioaddr)
5305 {
5306         /*
5307          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5308          * register to be written before TxDescAddrLow to work.
5309          * Switching from MMIO to I/O access fixes the issue as well.
5310          */
5311         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5312         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5313         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5314         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5315 }
5316
5317 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5318 {
5319         u16 cmd;
5320
5321         cmd = RTL_R16(CPlusCmd);
5322         RTL_W16(CPlusCmd, cmd);
5323         return cmd;
5324 }
5325
5326 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5327 {
5328         /* Low hurts. Let's disable the filtering. */
5329         RTL_W16(RxMaxSize, rx_buf_sz + 1);
5330 }
5331
5332 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5333 {
5334         static const struct rtl_cfg2_info {
5335                 u32 mac_version;
5336                 u32 clk;
5337                 u32 val;
5338         } cfg2_info [] = {
5339                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5340                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5341                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5342                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5343         };
5344         const struct rtl_cfg2_info *p = cfg2_info;
5345         unsigned int i;
5346         u32 clk;
5347
5348         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5349         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5350                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5351                         RTL_W32(0x7c, p->val);
5352                         break;
5353                 }
5354         }
5355 }
5356
5357 static void rtl_set_rx_mode(struct net_device *dev)
5358 {
5359         struct rtl8169_private *tp = netdev_priv(dev);
5360         void __iomem *ioaddr = tp->mmio_addr;
5361         u32 mc_filter[2];       /* Multicast hash filter */
5362         int rx_mode;
5363         u32 tmp = 0;
5364
5365         if (dev->flags & IFF_PROMISC) {
5366                 /* Unconditionally log net taps. */
5367                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5368                 rx_mode =
5369                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5370                     AcceptAllPhys;
5371                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5372         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5373                    (dev->flags & IFF_ALLMULTI)) {
5374                 /* Too many to filter perfectly -- accept all multicasts. */
5375                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5376                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5377         } else {
5378                 struct netdev_hw_addr *ha;
5379
5380                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5381                 mc_filter[1] = mc_filter[0] = 0;
5382                 netdev_for_each_mc_addr(ha, dev) {
5383                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5384                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5385                         rx_mode |= AcceptMulticast;
5386                 }
5387         }
5388
5389         if (dev->features & NETIF_F_RXALL)
5390                 rx_mode |= (AcceptErr | AcceptRunt);
5391
5392         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5393
5394         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5395                 u32 data = mc_filter[0];
5396
5397                 mc_filter[0] = swab32(mc_filter[1]);
5398                 mc_filter[1] = swab32(data);
5399         }
5400
5401         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5402                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5403
5404         RTL_W32(MAR0 + 4, mc_filter[1]);
5405         RTL_W32(MAR0 + 0, mc_filter[0]);
5406
5407         RTL_W32(RxConfig, tmp);
5408 }
5409
5410 static void rtl_hw_start_8169(struct net_device *dev)
5411 {
5412         struct rtl8169_private *tp = netdev_priv(dev);
5413         void __iomem *ioaddr = tp->mmio_addr;
5414         struct pci_dev *pdev = tp->pci_dev;
5415
5416         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5417                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5418                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5419         }
5420
5421         RTL_W8(Cfg9346, Cfg9346_Unlock);
5422         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5423             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5424             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5425             tp->mac_version == RTL_GIGA_MAC_VER_04)
5426                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5427
5428         rtl_init_rxcfg(tp);
5429
5430         RTL_W8(EarlyTxThres, NoEarlyTx);
5431
5432         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5433
5434         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5435             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5436             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5437             tp->mac_version == RTL_GIGA_MAC_VER_04)
5438                 rtl_set_rx_tx_config_registers(tp);
5439
5440         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5441
5442         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5443             tp->mac_version == RTL_GIGA_MAC_VER_03) {
5444                 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5445                         "Bit-3 and bit-14 MUST be 1\n");
5446                 tp->cp_cmd |= (1 << 14);
5447         }
5448
5449         RTL_W16(CPlusCmd, tp->cp_cmd);
5450
5451         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5452
5453         /*
5454          * Undocumented corner. Supposedly:
5455          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5456          */
5457         RTL_W16(IntrMitigate, 0x0000);
5458
5459         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5460
5461         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5462             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5463             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5464             tp->mac_version != RTL_GIGA_MAC_VER_04) {
5465                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5466                 rtl_set_rx_tx_config_registers(tp);
5467         }
5468
5469         RTL_W8(Cfg9346, Cfg9346_Lock);
5470
5471         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5472         RTL_R8(IntrMask);
5473
5474         RTL_W32(RxMissed, 0);
5475
5476         rtl_set_rx_mode(dev);
5477
5478         /* no early-rx interrupts */
5479         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5480 }
5481
5482 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5483 {
5484         if (tp->csi_ops.write)
5485                 tp->csi_ops.write(tp, addr, value);
5486 }
5487
5488 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5489 {
5490         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5491 }
5492
5493 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5494 {
5495         u32 csi;
5496
5497         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5498         rtl_csi_write(tp, 0x070c, csi | bits);
5499 }
5500
5501 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5502 {
5503         rtl_csi_access_enable(tp, 0x17000000);
5504 }
5505
5506 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5507 {
5508         rtl_csi_access_enable(tp, 0x27000000);
5509 }
5510
5511 DECLARE_RTL_COND(rtl_csiar_cond)
5512 {
5513         void __iomem *ioaddr = tp->mmio_addr;
5514
5515         return RTL_R32(CSIAR) & CSIAR_FLAG;
5516 }
5517
5518 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5519 {
5520         void __iomem *ioaddr = tp->mmio_addr;
5521
5522         RTL_W32(CSIDR, value);
5523         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5524                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5525
5526         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5527 }
5528
5529 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5530 {
5531         void __iomem *ioaddr = tp->mmio_addr;
5532
5533         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5534                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5535
5536         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5537                 RTL_R32(CSIDR) : ~0;
5538 }
5539
5540 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5541 {
5542         void __iomem *ioaddr = tp->mmio_addr;
5543
5544         RTL_W32(CSIDR, value);
5545         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5546                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5547                 CSIAR_FUNC_NIC);
5548
5549         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5550 }
5551
5552 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5553 {
5554         void __iomem *ioaddr = tp->mmio_addr;
5555
5556         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5557                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5558
5559         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5560                 RTL_R32(CSIDR) : ~0;
5561 }
5562
5563 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5564 {
5565         void __iomem *ioaddr = tp->mmio_addr;
5566
5567         RTL_W32(CSIDR, value);
5568         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5569                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5570                 CSIAR_FUNC_NIC2);
5571
5572         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5573 }
5574
5575 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5576 {
5577         void __iomem *ioaddr = tp->mmio_addr;
5578
5579         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5580                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5581
5582         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5583                 RTL_R32(CSIDR) : ~0;
5584 }
5585
5586 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5587 {
5588         struct csi_ops *ops = &tp->csi_ops;
5589
5590         switch (tp->mac_version) {
5591         case RTL_GIGA_MAC_VER_01:
5592         case RTL_GIGA_MAC_VER_02:
5593         case RTL_GIGA_MAC_VER_03:
5594         case RTL_GIGA_MAC_VER_04:
5595         case RTL_GIGA_MAC_VER_05:
5596         case RTL_GIGA_MAC_VER_06:
5597         case RTL_GIGA_MAC_VER_10:
5598         case RTL_GIGA_MAC_VER_11:
5599         case RTL_GIGA_MAC_VER_12:
5600         case RTL_GIGA_MAC_VER_13:
5601         case RTL_GIGA_MAC_VER_14:
5602         case RTL_GIGA_MAC_VER_15:
5603         case RTL_GIGA_MAC_VER_16:
5604         case RTL_GIGA_MAC_VER_17:
5605                 ops->write      = NULL;
5606                 ops->read       = NULL;
5607                 break;
5608
5609         case RTL_GIGA_MAC_VER_37:
5610         case RTL_GIGA_MAC_VER_38:
5611                 ops->write      = r8402_csi_write;
5612                 ops->read       = r8402_csi_read;
5613                 break;
5614
5615         case RTL_GIGA_MAC_VER_44:
5616                 ops->write      = r8411_csi_write;
5617                 ops->read       = r8411_csi_read;
5618                 break;
5619
5620         default:
5621                 ops->write      = r8169_csi_write;
5622                 ops->read       = r8169_csi_read;
5623                 break;
5624         }
5625 }
5626
5627 struct ephy_info {
5628         unsigned int offset;
5629         u16 mask;
5630         u16 bits;
5631 };
5632
5633 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5634                           int len)
5635 {
5636         u16 w;
5637
5638         while (len-- > 0) {
5639                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5640                 rtl_ephy_write(tp, e->offset, w);
5641                 e++;
5642         }
5643 }
5644
5645 static void rtl_disable_clock_request(struct pci_dev *pdev)
5646 {
5647         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5648                                    PCI_EXP_LNKCTL_CLKREQ_EN);
5649 }
5650
5651 static void rtl_enable_clock_request(struct pci_dev *pdev)
5652 {
5653         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5654                                  PCI_EXP_LNKCTL_CLKREQ_EN);
5655 }
5656
5657 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5658 {
5659         void __iomem *ioaddr = tp->mmio_addr;
5660         u8 data;
5661
5662         data = RTL_R8(Config3);
5663
5664         if (enable)
5665                 data |= Rdy_to_L23;
5666         else
5667                 data &= ~Rdy_to_L23;
5668
5669         RTL_W8(Config3, data);
5670 }
5671
5672 #define R8168_CPCMD_QUIRK_MASK (\
5673         EnableBist | \
5674         Mac_dbgo_oe | \
5675         Force_half_dup | \
5676         Force_rxflow_en | \
5677         Force_txflow_en | \
5678         Cxpl_dbg_sel | \
5679         ASF | \
5680         PktCntrDisable | \
5681         Mac_dbgo_sel)
5682
5683 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5684 {
5685         void __iomem *ioaddr = tp->mmio_addr;
5686         struct pci_dev *pdev = tp->pci_dev;
5687
5688         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5689
5690         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5691
5692         if (tp->dev->mtu <= ETH_DATA_LEN) {
5693                 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5694                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5695         }
5696 }
5697
5698 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5699 {
5700         void __iomem *ioaddr = tp->mmio_addr;
5701
5702         rtl_hw_start_8168bb(tp);
5703
5704         RTL_W8(MaxTxPacketSize, TxPacketMax);
5705
5706         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5707 }
5708
5709 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5710 {
5711         void __iomem *ioaddr = tp->mmio_addr;
5712         struct pci_dev *pdev = tp->pci_dev;
5713
5714         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5715
5716         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5717
5718         if (tp->dev->mtu <= ETH_DATA_LEN)
5719                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5720
5721         rtl_disable_clock_request(pdev);
5722
5723         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5724 }
5725
5726 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5727 {
5728         static const struct ephy_info e_info_8168cp[] = {
5729                 { 0x01, 0,      0x0001 },
5730                 { 0x02, 0x0800, 0x1000 },
5731                 { 0x03, 0,      0x0042 },
5732                 { 0x06, 0x0080, 0x0000 },
5733                 { 0x07, 0,      0x2000 }
5734         };
5735
5736         rtl_csi_access_enable_2(tp);
5737
5738         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5739
5740         __rtl_hw_start_8168cp(tp);
5741 }
5742
5743 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5744 {
5745         void __iomem *ioaddr = tp->mmio_addr;
5746         struct pci_dev *pdev = tp->pci_dev;
5747
5748         rtl_csi_access_enable_2(tp);
5749
5750         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5751
5752         if (tp->dev->mtu <= ETH_DATA_LEN)
5753                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5754
5755         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5756 }
5757
5758 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5759 {
5760         void __iomem *ioaddr = tp->mmio_addr;
5761         struct pci_dev *pdev = tp->pci_dev;
5762
5763         rtl_csi_access_enable_2(tp);
5764
5765         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5766
5767         /* Magic. */
5768         RTL_W8(DBG_REG, 0x20);
5769
5770         RTL_W8(MaxTxPacketSize, TxPacketMax);
5771
5772         if (tp->dev->mtu <= ETH_DATA_LEN)
5773                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5774
5775         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5776 }
5777
5778 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5779 {
5780         void __iomem *ioaddr = tp->mmio_addr;
5781         static const struct ephy_info e_info_8168c_1[] = {
5782                 { 0x02, 0x0800, 0x1000 },
5783                 { 0x03, 0,      0x0002 },
5784                 { 0x06, 0x0080, 0x0000 }
5785         };
5786
5787         rtl_csi_access_enable_2(tp);
5788
5789         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5790
5791         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5792
5793         __rtl_hw_start_8168cp(tp);
5794 }
5795
5796 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5797 {
5798         static const struct ephy_info e_info_8168c_2[] = {
5799                 { 0x01, 0,      0x0001 },
5800                 { 0x03, 0x0400, 0x0220 }
5801         };
5802
5803         rtl_csi_access_enable_2(tp);
5804
5805         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5806
5807         __rtl_hw_start_8168cp(tp);
5808 }
5809
5810 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5811 {
5812         rtl_hw_start_8168c_2(tp);
5813 }
5814
5815 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5816 {
5817         rtl_csi_access_enable_2(tp);
5818
5819         __rtl_hw_start_8168cp(tp);
5820 }
5821
5822 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5823 {
5824         void __iomem *ioaddr = tp->mmio_addr;
5825         struct pci_dev *pdev = tp->pci_dev;
5826
5827         rtl_csi_access_enable_2(tp);
5828
5829         rtl_disable_clock_request(pdev);
5830
5831         RTL_W8(MaxTxPacketSize, TxPacketMax);
5832
5833         if (tp->dev->mtu <= ETH_DATA_LEN)
5834                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5835
5836         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5837 }
5838
5839 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5840 {
5841         void __iomem *ioaddr = tp->mmio_addr;
5842         struct pci_dev *pdev = tp->pci_dev;
5843
5844         rtl_csi_access_enable_1(tp);
5845
5846         if (tp->dev->mtu <= ETH_DATA_LEN)
5847                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5848
5849         RTL_W8(MaxTxPacketSize, TxPacketMax);
5850
5851         rtl_disable_clock_request(pdev);
5852 }
5853
5854 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5855 {
5856         void __iomem *ioaddr = tp->mmio_addr;
5857         struct pci_dev *pdev = tp->pci_dev;
5858         static const struct ephy_info e_info_8168d_4[] = {
5859                 { 0x0b, 0x0000, 0x0048 },
5860                 { 0x19, 0x0020, 0x0050 },
5861                 { 0x0c, 0x0100, 0x0020 }
5862         };
5863
5864         rtl_csi_access_enable_1(tp);
5865
5866         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5867
5868         RTL_W8(MaxTxPacketSize, TxPacketMax);
5869
5870         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5871
5872         rtl_enable_clock_request(pdev);
5873 }
5874
5875 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5876 {
5877         void __iomem *ioaddr = tp->mmio_addr;
5878         struct pci_dev *pdev = tp->pci_dev;
5879         static const struct ephy_info e_info_8168e_1[] = {
5880                 { 0x00, 0x0200, 0x0100 },
5881                 { 0x00, 0x0000, 0x0004 },
5882                 { 0x06, 0x0002, 0x0001 },
5883                 { 0x06, 0x0000, 0x0030 },
5884                 { 0x07, 0x0000, 0x2000 },
5885                 { 0x00, 0x0000, 0x0020 },
5886                 { 0x03, 0x5800, 0x2000 },
5887                 { 0x03, 0x0000, 0x0001 },
5888                 { 0x01, 0x0800, 0x1000 },
5889                 { 0x07, 0x0000, 0x4000 },
5890                 { 0x1e, 0x0000, 0x2000 },
5891                 { 0x19, 0xffff, 0xfe6c },
5892                 { 0x0a, 0x0000, 0x0040 }
5893         };
5894
5895         rtl_csi_access_enable_2(tp);
5896
5897         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5898
5899         if (tp->dev->mtu <= ETH_DATA_LEN)
5900                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5901
5902         RTL_W8(MaxTxPacketSize, TxPacketMax);
5903
5904         rtl_disable_clock_request(pdev);
5905
5906         /* Reset tx FIFO pointer */
5907         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5908         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5909
5910         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5911 }
5912
5913 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5914 {
5915         void __iomem *ioaddr = tp->mmio_addr;
5916         struct pci_dev *pdev = tp->pci_dev;
5917         static const struct ephy_info e_info_8168e_2[] = {
5918                 { 0x09, 0x0000, 0x0080 },
5919                 { 0x19, 0x0000, 0x0224 }
5920         };
5921
5922         rtl_csi_access_enable_1(tp);
5923
5924         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5925
5926         if (tp->dev->mtu <= ETH_DATA_LEN)
5927                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5928
5929         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5930         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5931         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5932         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5933         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5934         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5935         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5936         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5937
5938         RTL_W8(MaxTxPacketSize, EarlySize);
5939
5940         rtl_disable_clock_request(pdev);
5941
5942         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5943         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5944
5945         /* Adjust EEE LED frequency */
5946         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5947
5948         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5949         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5950         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5951 }
5952
5953 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5954 {
5955         void __iomem *ioaddr = tp->mmio_addr;
5956         struct pci_dev *pdev = tp->pci_dev;
5957
5958         rtl_csi_access_enable_2(tp);
5959
5960         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5961
5962         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5963         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5964         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5965         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5966         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5967         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5968         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5969         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5970         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5971         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5972
5973         RTL_W8(MaxTxPacketSize, EarlySize);
5974
5975         rtl_disable_clock_request(pdev);
5976
5977         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5978         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5979         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5980         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5981         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5982 }
5983
5984 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5985 {
5986         void __iomem *ioaddr = tp->mmio_addr;
5987         static const struct ephy_info e_info_8168f_1[] = {
5988                 { 0x06, 0x00c0, 0x0020 },
5989                 { 0x08, 0x0001, 0x0002 },
5990                 { 0x09, 0x0000, 0x0080 },
5991                 { 0x19, 0x0000, 0x0224 }
5992         };
5993
5994         rtl_hw_start_8168f(tp);
5995
5996         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5997
5998         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5999
6000         /* Adjust EEE LED frequency */
6001         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6002 }
6003
6004 static void rtl_hw_start_8411(struct rtl8169_private *tp)
6005 {
6006         static const struct ephy_info e_info_8168f_1[] = {
6007                 { 0x06, 0x00c0, 0x0020 },
6008                 { 0x0f, 0xffff, 0x5200 },
6009                 { 0x1e, 0x0000, 0x4000 },
6010                 { 0x19, 0x0000, 0x0224 }
6011         };
6012
6013         rtl_hw_start_8168f(tp);
6014         rtl_pcie_state_l2l3_enable(tp, false);
6015
6016         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6017
6018         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
6019 }
6020
6021 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
6022 {
6023         void __iomem *ioaddr = tp->mmio_addr;
6024         struct pci_dev *pdev = tp->pci_dev;
6025
6026         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6027
6028         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6029         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6030         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6031         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6032
6033         rtl_csi_access_enable_1(tp);
6034
6035         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6036
6037         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6038         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6039         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
6040
6041         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6042         RTL_W8(MaxTxPacketSize, EarlySize);
6043
6044         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6045         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6046
6047         /* Adjust EEE LED frequency */
6048         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6049
6050         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6051         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6052
6053         rtl_pcie_state_l2l3_enable(tp, false);
6054 }
6055
6056 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6057 {
6058         void __iomem *ioaddr = tp->mmio_addr;
6059         static const struct ephy_info e_info_8168g_1[] = {
6060                 { 0x00, 0x0000, 0x0008 },
6061                 { 0x0c, 0x37d0, 0x0820 },
6062                 { 0x1e, 0x0000, 0x0001 },
6063                 { 0x19, 0x8000, 0x0000 }
6064         };
6065
6066         rtl_hw_start_8168g(tp);
6067
6068         /* disable aspm and clock request before access ephy */
6069         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6070         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6071         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6072 }
6073
6074 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6075 {
6076         void __iomem *ioaddr = tp->mmio_addr;
6077         static const struct ephy_info e_info_8168g_2[] = {
6078                 { 0x00, 0x0000, 0x0008 },
6079                 { 0x0c, 0x3df0, 0x0200 },
6080                 { 0x19, 0xffff, 0xfc00 },
6081                 { 0x1e, 0xffff, 0x20eb }
6082         };
6083
6084         rtl_hw_start_8168g(tp);
6085
6086         /* disable aspm and clock request before access ephy */
6087         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6088         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6089         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6090 }
6091
6092 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6093 {
6094         void __iomem *ioaddr = tp->mmio_addr;
6095         static const struct ephy_info e_info_8411_2[] = {
6096                 { 0x00, 0x0000, 0x0008 },
6097                 { 0x0c, 0x3df0, 0x0200 },
6098                 { 0x0f, 0xffff, 0x5200 },
6099                 { 0x19, 0x0020, 0x0000 },
6100                 { 0x1e, 0x0000, 0x2000 }
6101         };
6102
6103         rtl_hw_start_8168g(tp);
6104
6105         /* disable aspm and clock request before access ephy */
6106         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6107         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6108         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6109 }
6110
6111 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6112 {
6113         void __iomem *ioaddr = tp->mmio_addr;
6114         struct pci_dev *pdev = tp->pci_dev;
6115         int rg_saw_cnt;
6116         u32 data;
6117         static const struct ephy_info e_info_8168h_1[] = {
6118                 { 0x1e, 0x0800, 0x0001 },
6119                 { 0x1d, 0x0000, 0x0800 },
6120                 { 0x05, 0xffff, 0x2089 },
6121                 { 0x06, 0xffff, 0x5881 },
6122                 { 0x04, 0xffff, 0x154a },
6123                 { 0x01, 0xffff, 0x068b }
6124         };
6125
6126         /* disable aspm and clock request before access ephy */
6127         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6128         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6129         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6130
6131         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6132
6133         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6134         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6135         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6136         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6137
6138         rtl_csi_access_enable_1(tp);
6139
6140         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6141
6142         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6143         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6144
6145         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6146
6147         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6148
6149         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6150
6151         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6152         RTL_W8(MaxTxPacketSize, EarlySize);
6153
6154         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6155         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6156
6157         /* Adjust EEE LED frequency */
6158         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6159
6160         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6161         RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6162
6163         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6164
6165         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6166
6167         rtl_pcie_state_l2l3_enable(tp, false);
6168
6169         rtl_writephy(tp, 0x1f, 0x0c42);
6170         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6171         rtl_writephy(tp, 0x1f, 0x0000);
6172         if (rg_saw_cnt > 0) {
6173                 u16 sw_cnt_1ms_ini;
6174
6175                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6176                 sw_cnt_1ms_ini &= 0x0fff;
6177                 data = r8168_mac_ocp_read(tp, 0xd412);
6178                 data &= ~0x0fff;
6179                 data |= sw_cnt_1ms_ini;
6180                 r8168_mac_ocp_write(tp, 0xd412, data);
6181         }
6182
6183         data = r8168_mac_ocp_read(tp, 0xe056);
6184         data &= ~0xf0;
6185         data |= 0x70;
6186         r8168_mac_ocp_write(tp, 0xe056, data);
6187
6188         data = r8168_mac_ocp_read(tp, 0xe052);
6189         data &= ~0x6000;
6190         data |= 0x8008;
6191         r8168_mac_ocp_write(tp, 0xe052, data);
6192
6193         data = r8168_mac_ocp_read(tp, 0xe0d6);
6194         data &= ~0x01ff;
6195         data |= 0x017f;
6196         r8168_mac_ocp_write(tp, 0xe0d6, data);
6197
6198         data = r8168_mac_ocp_read(tp, 0xd420);
6199         data &= ~0x0fff;
6200         data |= 0x047f;
6201         r8168_mac_ocp_write(tp, 0xd420, data);
6202
6203         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6204         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6205         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6206         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6207 }
6208
6209 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6210 {
6211         void __iomem *ioaddr = tp->mmio_addr;
6212         struct pci_dev *pdev = tp->pci_dev;
6213
6214         rtl8168ep_stop_cmac(tp);
6215
6216         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6217
6218         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6219         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6220         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6221         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6222
6223         rtl_csi_access_enable_1(tp);
6224
6225         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6226
6227         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6228         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6229
6230         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6231
6232         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6233
6234         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6235         RTL_W8(MaxTxPacketSize, EarlySize);
6236
6237         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6238         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6239
6240         /* Adjust EEE LED frequency */
6241         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6242
6243         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6244
6245         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6246
6247         rtl_pcie_state_l2l3_enable(tp, false);
6248 }
6249
6250 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6251 {
6252         void __iomem *ioaddr = tp->mmio_addr;
6253         static const struct ephy_info e_info_8168ep_1[] = {
6254                 { 0x00, 0xffff, 0x10ab },
6255                 { 0x06, 0xffff, 0xf030 },
6256                 { 0x08, 0xffff, 0x2006 },
6257                 { 0x0d, 0xffff, 0x1666 },
6258                 { 0x0c, 0x3ff0, 0x0000 }
6259         };
6260
6261         /* disable aspm and clock request before access ephy */
6262         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6263         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6264         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6265
6266         rtl_hw_start_8168ep(tp);
6267 }
6268
6269 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6270 {
6271         void __iomem *ioaddr = tp->mmio_addr;
6272         static const struct ephy_info e_info_8168ep_2[] = {
6273                 { 0x00, 0xffff, 0x10a3 },
6274                 { 0x19, 0xffff, 0xfc00 },
6275                 { 0x1e, 0xffff, 0x20ea }
6276         };
6277
6278         /* disable aspm and clock request before access ephy */
6279         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6280         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6281         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6282
6283         rtl_hw_start_8168ep(tp);
6284
6285         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6286         RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6287 }
6288
6289 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6290 {
6291         void __iomem *ioaddr = tp->mmio_addr;
6292         u32 data;
6293         static const struct ephy_info e_info_8168ep_3[] = {
6294                 { 0x00, 0xffff, 0x10a3 },
6295                 { 0x19, 0xffff, 0x7c00 },
6296                 { 0x1e, 0xffff, 0x20eb },
6297                 { 0x0d, 0xffff, 0x1666 }
6298         };
6299
6300         /* disable aspm and clock request before access ephy */
6301         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6302         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6303         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6304
6305         rtl_hw_start_8168ep(tp);
6306
6307         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6308         RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6309
6310         data = r8168_mac_ocp_read(tp, 0xd3e2);
6311         data &= 0xf000;
6312         data |= 0x0271;
6313         r8168_mac_ocp_write(tp, 0xd3e2, data);
6314
6315         data = r8168_mac_ocp_read(tp, 0xd3e4);
6316         data &= 0xff00;
6317         r8168_mac_ocp_write(tp, 0xd3e4, data);
6318
6319         data = r8168_mac_ocp_read(tp, 0xe860);
6320         data |= 0x0080;
6321         r8168_mac_ocp_write(tp, 0xe860, data);
6322 }
6323
6324 static void rtl_hw_start_8168(struct net_device *dev)
6325 {
6326         struct rtl8169_private *tp = netdev_priv(dev);
6327         void __iomem *ioaddr = tp->mmio_addr;
6328
6329         RTL_W8(Cfg9346, Cfg9346_Unlock);
6330
6331         RTL_W8(MaxTxPacketSize, TxPacketMax);
6332
6333         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6334
6335         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6336
6337         RTL_W16(CPlusCmd, tp->cp_cmd);
6338
6339         RTL_W16(IntrMitigate, 0x5151);
6340
6341         /* Work around for RxFIFO overflow. */
6342         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6343                 tp->event_slow |= RxFIFOOver | PCSTimeout;
6344                 tp->event_slow &= ~RxOverflow;
6345         }
6346
6347         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6348
6349         rtl_set_rx_tx_config_registers(tp);
6350
6351         RTL_R8(IntrMask);
6352
6353         switch (tp->mac_version) {
6354         case RTL_GIGA_MAC_VER_11:
6355                 rtl_hw_start_8168bb(tp);
6356                 break;
6357
6358         case RTL_GIGA_MAC_VER_12:
6359         case RTL_GIGA_MAC_VER_17:
6360                 rtl_hw_start_8168bef(tp);
6361                 break;
6362
6363         case RTL_GIGA_MAC_VER_18:
6364                 rtl_hw_start_8168cp_1(tp);
6365                 break;
6366
6367         case RTL_GIGA_MAC_VER_19:
6368                 rtl_hw_start_8168c_1(tp);
6369                 break;
6370
6371         case RTL_GIGA_MAC_VER_20:
6372                 rtl_hw_start_8168c_2(tp);
6373                 break;
6374
6375         case RTL_GIGA_MAC_VER_21:
6376                 rtl_hw_start_8168c_3(tp);
6377                 break;
6378
6379         case RTL_GIGA_MAC_VER_22:
6380                 rtl_hw_start_8168c_4(tp);
6381                 break;
6382
6383         case RTL_GIGA_MAC_VER_23:
6384                 rtl_hw_start_8168cp_2(tp);
6385                 break;
6386
6387         case RTL_GIGA_MAC_VER_24:
6388                 rtl_hw_start_8168cp_3(tp);
6389                 break;
6390
6391         case RTL_GIGA_MAC_VER_25:
6392         case RTL_GIGA_MAC_VER_26:
6393         case RTL_GIGA_MAC_VER_27:
6394                 rtl_hw_start_8168d(tp);
6395                 break;
6396
6397         case RTL_GIGA_MAC_VER_28:
6398                 rtl_hw_start_8168d_4(tp);
6399                 break;
6400
6401         case RTL_GIGA_MAC_VER_31:
6402                 rtl_hw_start_8168dp(tp);
6403                 break;
6404
6405         case RTL_GIGA_MAC_VER_32:
6406         case RTL_GIGA_MAC_VER_33:
6407                 rtl_hw_start_8168e_1(tp);
6408                 break;
6409         case RTL_GIGA_MAC_VER_34:
6410                 rtl_hw_start_8168e_2(tp);
6411                 break;
6412
6413         case RTL_GIGA_MAC_VER_35:
6414         case RTL_GIGA_MAC_VER_36:
6415                 rtl_hw_start_8168f_1(tp);
6416                 break;
6417
6418         case RTL_GIGA_MAC_VER_38:
6419                 rtl_hw_start_8411(tp);
6420                 break;
6421
6422         case RTL_GIGA_MAC_VER_40:
6423         case RTL_GIGA_MAC_VER_41:
6424                 rtl_hw_start_8168g_1(tp);
6425                 break;
6426         case RTL_GIGA_MAC_VER_42:
6427                 rtl_hw_start_8168g_2(tp);
6428                 break;
6429
6430         case RTL_GIGA_MAC_VER_44:
6431                 rtl_hw_start_8411_2(tp);
6432                 break;
6433
6434         case RTL_GIGA_MAC_VER_45:
6435         case RTL_GIGA_MAC_VER_46:
6436                 rtl_hw_start_8168h_1(tp);
6437                 break;
6438
6439         case RTL_GIGA_MAC_VER_49:
6440                 rtl_hw_start_8168ep_1(tp);
6441                 break;
6442
6443         case RTL_GIGA_MAC_VER_50:
6444                 rtl_hw_start_8168ep_2(tp);
6445                 break;
6446
6447         case RTL_GIGA_MAC_VER_51:
6448                 rtl_hw_start_8168ep_3(tp);
6449                 break;
6450
6451         default:
6452                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6453                         dev->name, tp->mac_version);
6454                 break;
6455         }
6456
6457         RTL_W8(Cfg9346, Cfg9346_Lock);
6458
6459         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6460
6461         rtl_set_rx_mode(dev);
6462
6463         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6464 }
6465
6466 #define R810X_CPCMD_QUIRK_MASK (\
6467         EnableBist | \
6468         Mac_dbgo_oe | \
6469         Force_half_dup | \
6470         Force_rxflow_en | \
6471         Force_txflow_en | \
6472         Cxpl_dbg_sel | \
6473         ASF | \
6474         PktCntrDisable | \
6475         Mac_dbgo_sel)
6476
6477 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6478 {
6479         void __iomem *ioaddr = tp->mmio_addr;
6480         struct pci_dev *pdev = tp->pci_dev;
6481         static const struct ephy_info e_info_8102e_1[] = {
6482                 { 0x01, 0, 0x6e65 },
6483                 { 0x02, 0, 0x091f },
6484                 { 0x03, 0, 0xc2f9 },
6485                 { 0x06, 0, 0xafb5 },
6486                 { 0x07, 0, 0x0e00 },
6487                 { 0x19, 0, 0xec80 },
6488                 { 0x01, 0, 0x2e65 },
6489                 { 0x01, 0, 0x6e65 }
6490         };
6491         u8 cfg1;
6492
6493         rtl_csi_access_enable_2(tp);
6494
6495         RTL_W8(DBG_REG, FIX_NAK_1);
6496
6497         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6498
6499         RTL_W8(Config1,
6500                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6501         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6502
6503         cfg1 = RTL_R8(Config1);
6504         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6505                 RTL_W8(Config1, cfg1 & ~LEDS0);
6506
6507         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6508 }
6509
6510 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6511 {
6512         void __iomem *ioaddr = tp->mmio_addr;
6513         struct pci_dev *pdev = tp->pci_dev;
6514
6515         rtl_csi_access_enable_2(tp);
6516
6517         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6518
6519         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6520         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6521 }
6522
6523 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6524 {
6525         rtl_hw_start_8102e_2(tp);
6526
6527         rtl_ephy_write(tp, 0x03, 0xc2f9);
6528 }
6529
6530 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6531 {
6532         void __iomem *ioaddr = tp->mmio_addr;
6533         static const struct ephy_info e_info_8105e_1[] = {
6534                 { 0x07, 0, 0x4000 },
6535                 { 0x19, 0, 0x0200 },
6536                 { 0x19, 0, 0x0020 },
6537                 { 0x1e, 0, 0x2000 },
6538                 { 0x03, 0, 0x0001 },
6539                 { 0x19, 0, 0x0100 },
6540                 { 0x19, 0, 0x0004 },
6541                 { 0x0a, 0, 0x0020 }
6542         };
6543
6544         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6545         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6546
6547         /* Disable Early Tally Counter */
6548         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6549
6550         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6551         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6552
6553         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6554
6555         rtl_pcie_state_l2l3_enable(tp, false);
6556 }
6557
6558 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6559 {
6560         rtl_hw_start_8105e_1(tp);
6561         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6562 }
6563
6564 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6565 {
6566         void __iomem *ioaddr = tp->mmio_addr;
6567         static const struct ephy_info e_info_8402[] = {
6568                 { 0x19, 0xffff, 0xff64 },
6569                 { 0x1e, 0, 0x4000 }
6570         };
6571
6572         rtl_csi_access_enable_2(tp);
6573
6574         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6575         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6576
6577         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6578         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6579
6580         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6581
6582         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6583
6584         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6585         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6586         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6587         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6588         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6589         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6590         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6591
6592         rtl_pcie_state_l2l3_enable(tp, false);
6593 }
6594
6595 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6596 {
6597         void __iomem *ioaddr = tp->mmio_addr;
6598
6599         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6600         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6601
6602         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6603         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6604         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6605
6606         rtl_pcie_state_l2l3_enable(tp, false);
6607 }
6608
6609 static void rtl_hw_start_8101(struct net_device *dev)
6610 {
6611         struct rtl8169_private *tp = netdev_priv(dev);
6612         void __iomem *ioaddr = tp->mmio_addr;
6613         struct pci_dev *pdev = tp->pci_dev;
6614
6615         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6616                 tp->event_slow &= ~RxFIFOOver;
6617
6618         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6619             tp->mac_version == RTL_GIGA_MAC_VER_16)
6620                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6621                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
6622
6623         RTL_W8(Cfg9346, Cfg9346_Unlock);
6624
6625         RTL_W8(MaxTxPacketSize, TxPacketMax);
6626
6627         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6628
6629         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6630         RTL_W16(CPlusCmd, tp->cp_cmd);
6631
6632         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6633
6634         rtl_set_rx_tx_config_registers(tp);
6635
6636         switch (tp->mac_version) {
6637         case RTL_GIGA_MAC_VER_07:
6638                 rtl_hw_start_8102e_1(tp);
6639                 break;
6640
6641         case RTL_GIGA_MAC_VER_08:
6642                 rtl_hw_start_8102e_3(tp);
6643                 break;
6644
6645         case RTL_GIGA_MAC_VER_09:
6646                 rtl_hw_start_8102e_2(tp);
6647                 break;
6648
6649         case RTL_GIGA_MAC_VER_29:
6650                 rtl_hw_start_8105e_1(tp);
6651                 break;
6652         case RTL_GIGA_MAC_VER_30:
6653                 rtl_hw_start_8105e_2(tp);
6654                 break;
6655
6656         case RTL_GIGA_MAC_VER_37:
6657                 rtl_hw_start_8402(tp);
6658                 break;
6659
6660         case RTL_GIGA_MAC_VER_39:
6661                 rtl_hw_start_8106(tp);
6662                 break;
6663         case RTL_GIGA_MAC_VER_43:
6664                 rtl_hw_start_8168g_2(tp);
6665                 break;
6666         case RTL_GIGA_MAC_VER_47:
6667         case RTL_GIGA_MAC_VER_48:
6668                 rtl_hw_start_8168h_1(tp);
6669                 break;
6670         }
6671
6672         RTL_W8(Cfg9346, Cfg9346_Lock);
6673
6674         RTL_W16(IntrMitigate, 0x0000);
6675
6676         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6677
6678         rtl_set_rx_mode(dev);
6679
6680         RTL_R8(IntrMask);
6681
6682         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6683 }
6684
6685 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6686 {
6687         struct rtl8169_private *tp = netdev_priv(dev);
6688
6689         if (new_mtu > ETH_DATA_LEN)
6690                 rtl_hw_jumbo_enable(tp);
6691         else
6692                 rtl_hw_jumbo_disable(tp);
6693
6694         dev->mtu = new_mtu;
6695         netdev_update_features(dev);
6696
6697         return 0;
6698 }
6699
6700 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6701 {
6702         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6703         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6704 }
6705
6706 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6707                                      void **data_buff, struct RxDesc *desc)
6708 {
6709         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6710                          DMA_FROM_DEVICE);
6711
6712         kfree(*data_buff);
6713         *data_buff = NULL;
6714         rtl8169_make_unusable_by_asic(desc);
6715 }
6716
6717 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6718 {
6719         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6720
6721         /* Force memory writes to complete before releasing descriptor */
6722         dma_wmb();
6723
6724         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6725 }
6726
6727 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6728                                        u32 rx_buf_sz)
6729 {
6730         desc->addr = cpu_to_le64(mapping);
6731         rtl8169_mark_to_asic(desc, rx_buf_sz);
6732 }
6733
6734 static inline void *rtl8169_align(void *data)
6735 {
6736         return (void *)ALIGN((long)data, 16);
6737 }
6738
6739 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6740                                              struct RxDesc *desc)
6741 {
6742         void *data;
6743         dma_addr_t mapping;
6744         struct device *d = &tp->pci_dev->dev;
6745         struct net_device *dev = tp->dev;
6746         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6747
6748         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6749         if (!data)
6750                 return NULL;
6751
6752         if (rtl8169_align(data) != data) {
6753                 kfree(data);
6754                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6755                 if (!data)
6756                         return NULL;
6757         }
6758
6759         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6760                                  DMA_FROM_DEVICE);
6761         if (unlikely(dma_mapping_error(d, mapping))) {
6762                 if (net_ratelimit())
6763                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6764                 goto err_out;
6765         }
6766
6767         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6768         return data;
6769
6770 err_out:
6771         kfree(data);
6772         return NULL;
6773 }
6774
6775 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6776 {
6777         unsigned int i;
6778
6779         for (i = 0; i < NUM_RX_DESC; i++) {
6780                 if (tp->Rx_databuff[i]) {
6781                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6782                                             tp->RxDescArray + i);
6783                 }
6784         }
6785 }
6786
6787 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6788 {
6789         desc->opts1 |= cpu_to_le32(RingEnd);
6790 }
6791
6792 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6793 {
6794         unsigned int i;
6795
6796         for (i = 0; i < NUM_RX_DESC; i++) {
6797                 void *data;
6798
6799                 if (tp->Rx_databuff[i])
6800                         continue;
6801
6802                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6803                 if (!data) {
6804                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6805                         goto err_out;
6806                 }
6807                 tp->Rx_databuff[i] = data;
6808         }
6809
6810         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6811         return 0;
6812
6813 err_out:
6814         rtl8169_rx_clear(tp);
6815         return -ENOMEM;
6816 }
6817
6818 static int rtl8169_init_ring(struct net_device *dev)
6819 {
6820         struct rtl8169_private *tp = netdev_priv(dev);
6821
6822         rtl8169_init_ring_indexes(tp);
6823
6824         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6825         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6826
6827         return rtl8169_rx_fill(tp);
6828 }
6829
6830 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6831                                  struct TxDesc *desc)
6832 {
6833         unsigned int len = tx_skb->len;
6834
6835         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6836
6837         desc->opts1 = 0x00;
6838         desc->opts2 = 0x00;
6839         desc->addr = 0x00;
6840         tx_skb->len = 0;
6841 }
6842
6843 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6844                                    unsigned int n)
6845 {
6846         unsigned int i;
6847
6848         for (i = 0; i < n; i++) {
6849                 unsigned int entry = (start + i) % NUM_TX_DESC;
6850                 struct ring_info *tx_skb = tp->tx_skb + entry;
6851                 unsigned int len = tx_skb->len;
6852
6853                 if (len) {
6854                         struct sk_buff *skb = tx_skb->skb;
6855
6856                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6857                                              tp->TxDescArray + entry);
6858                         if (skb) {
6859                                 dev_consume_skb_any(skb);
6860                                 tx_skb->skb = NULL;
6861                         }
6862                 }
6863         }
6864 }
6865
6866 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6867 {
6868         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6869         tp->cur_tx = tp->dirty_tx = 0;
6870 }
6871
6872 static void rtl_reset_work(struct rtl8169_private *tp)
6873 {
6874         struct net_device *dev = tp->dev;
6875         int i;
6876
6877         napi_disable(&tp->napi);
6878         netif_stop_queue(dev);
6879         synchronize_sched();
6880
6881         rtl8169_hw_reset(tp);
6882
6883         for (i = 0; i < NUM_RX_DESC; i++)
6884                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6885
6886         rtl8169_tx_clear(tp);
6887         rtl8169_init_ring_indexes(tp);
6888
6889         napi_enable(&tp->napi);
6890         rtl_hw_start(dev);
6891         netif_wake_queue(dev);
6892         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6893 }
6894
6895 static void rtl8169_tx_timeout(struct net_device *dev)
6896 {
6897         struct rtl8169_private *tp = netdev_priv(dev);
6898
6899         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6900 }
6901
6902 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6903                               u32 *opts)
6904 {
6905         struct skb_shared_info *info = skb_shinfo(skb);
6906         unsigned int cur_frag, entry;
6907         struct TxDesc *uninitialized_var(txd);
6908         struct device *d = &tp->pci_dev->dev;
6909
6910         entry = tp->cur_tx;
6911         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6912                 const skb_frag_t *frag = info->frags + cur_frag;
6913                 dma_addr_t mapping;
6914                 u32 status, len;
6915                 void *addr;
6916
6917                 entry = (entry + 1) % NUM_TX_DESC;
6918
6919                 txd = tp->TxDescArray + entry;
6920                 len = skb_frag_size(frag);
6921                 addr = skb_frag_address(frag);
6922                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6923                 if (unlikely(dma_mapping_error(d, mapping))) {
6924                         if (net_ratelimit())
6925                                 netif_err(tp, drv, tp->dev,
6926                                           "Failed to map TX fragments DMA!\n");
6927                         goto err_out;
6928                 }
6929
6930                 /* Anti gcc 2.95.3 bugware (sic) */
6931                 status = opts[0] | len |
6932                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
6933
6934                 txd->opts1 = cpu_to_le32(status);
6935                 txd->opts2 = cpu_to_le32(opts[1]);
6936                 txd->addr = cpu_to_le64(mapping);
6937
6938                 tp->tx_skb[entry].len = len;
6939         }
6940
6941         if (cur_frag) {
6942                 tp->tx_skb[entry].skb = skb;
6943                 txd->opts1 |= cpu_to_le32(LastFrag);
6944         }
6945
6946         return cur_frag;
6947
6948 err_out:
6949         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6950         return -EIO;
6951 }
6952
6953 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6954 {
6955         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6956 }
6957
6958 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6959                                       struct net_device *dev);
6960 /* r8169_csum_workaround()
6961  * The hw limites the value the transport offset. When the offset is out of the
6962  * range, calculate the checksum by sw.
6963  */
6964 static void r8169_csum_workaround(struct rtl8169_private *tp,
6965                                   struct sk_buff *skb)
6966 {
6967         if (skb_shinfo(skb)->gso_size) {
6968                 netdev_features_t features = tp->dev->features;
6969                 struct sk_buff *segs, *nskb;
6970
6971                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6972                 segs = skb_gso_segment(skb, features);
6973                 if (IS_ERR(segs) || !segs)
6974                         goto drop;
6975
6976                 do {
6977                         nskb = segs;
6978                         segs = segs->next;
6979                         nskb->next = NULL;
6980                         rtl8169_start_xmit(nskb, tp->dev);
6981                 } while (segs);
6982
6983                 dev_consume_skb_any(skb);
6984         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6985                 if (skb_checksum_help(skb) < 0)
6986                         goto drop;
6987
6988                 rtl8169_start_xmit(skb, tp->dev);
6989         } else {
6990                 struct net_device_stats *stats;
6991
6992 drop:
6993                 stats = &tp->dev->stats;
6994                 stats->tx_dropped++;
6995                 dev_kfree_skb_any(skb);
6996         }
6997 }
6998
6999 /* msdn_giant_send_check()
7000  * According to the document of microsoft, the TCP Pseudo Header excludes the
7001  * packet length for IPv6 TCP large packets.
7002  */
7003 static int msdn_giant_send_check(struct sk_buff *skb)
7004 {
7005         const struct ipv6hdr *ipv6h;
7006         struct tcphdr *th;
7007         int ret;
7008
7009         ret = skb_cow_head(skb, 0);
7010         if (ret)
7011                 return ret;
7012
7013         ipv6h = ipv6_hdr(skb);
7014         th = tcp_hdr(skb);
7015
7016         th->check = 0;
7017         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
7018
7019         return ret;
7020 }
7021
7022 static inline __be16 get_protocol(struct sk_buff *skb)
7023 {
7024         __be16 protocol;
7025
7026         if (skb->protocol == htons(ETH_P_8021Q))
7027                 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7028         else
7029                 protocol = skb->protocol;
7030
7031         return protocol;
7032 }
7033
7034 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7035                                 struct sk_buff *skb, u32 *opts)
7036 {
7037         u32 mss = skb_shinfo(skb)->gso_size;
7038
7039         if (mss) {
7040                 opts[0] |= TD_LSO;
7041                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7042         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7043                 const struct iphdr *ip = ip_hdr(skb);
7044
7045                 if (ip->protocol == IPPROTO_TCP)
7046                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7047                 else if (ip->protocol == IPPROTO_UDP)
7048                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7049                 else
7050                         WARN_ON_ONCE(1);
7051         }
7052
7053         return true;
7054 }
7055
7056 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7057                                 struct sk_buff *skb, u32 *opts)
7058 {
7059         u32 transport_offset = (u32)skb_transport_offset(skb);
7060         u32 mss = skb_shinfo(skb)->gso_size;
7061
7062         if (mss) {
7063                 if (transport_offset > GTTCPHO_MAX) {
7064                         netif_warn(tp, tx_err, tp->dev,
7065                                    "Invalid transport offset 0x%x for TSO\n",
7066                                    transport_offset);
7067                         return false;
7068                 }
7069
7070                 switch (get_protocol(skb)) {
7071                 case htons(ETH_P_IP):
7072                         opts[0] |= TD1_GTSENV4;
7073                         break;
7074
7075                 case htons(ETH_P_IPV6):
7076                         if (msdn_giant_send_check(skb))
7077                                 return false;
7078
7079                         opts[0] |= TD1_GTSENV6;
7080                         break;
7081
7082                 default:
7083                         WARN_ON_ONCE(1);
7084                         break;
7085                 }
7086
7087                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7088                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7089         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7090                 u8 ip_protocol;
7091
7092                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7093                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7094
7095                 if (transport_offset > TCPHO_MAX) {
7096                         netif_warn(tp, tx_err, tp->dev,
7097                                    "Invalid transport offset 0x%x\n",
7098                                    transport_offset);
7099                         return false;
7100                 }
7101
7102                 switch (get_protocol(skb)) {
7103                 case htons(ETH_P_IP):
7104                         opts[1] |= TD1_IPv4_CS;
7105                         ip_protocol = ip_hdr(skb)->protocol;
7106                         break;
7107
7108                 case htons(ETH_P_IPV6):
7109                         opts[1] |= TD1_IPv6_CS;
7110                         ip_protocol = ipv6_hdr(skb)->nexthdr;
7111                         break;
7112
7113                 default:
7114                         ip_protocol = IPPROTO_RAW;
7115                         break;
7116                 }
7117
7118                 if (ip_protocol == IPPROTO_TCP)
7119                         opts[1] |= TD1_TCP_CS;
7120                 else if (ip_protocol == IPPROTO_UDP)
7121                         opts[1] |= TD1_UDP_CS;
7122                 else
7123                         WARN_ON_ONCE(1);
7124
7125                 opts[1] |= transport_offset << TCPHO_SHIFT;
7126         } else {
7127                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7128                         /* eth_skb_pad would free the skb on error */
7129                         return !__skb_put_padto(skb, ETH_ZLEN, false);
7130         }
7131
7132         return true;
7133 }
7134
7135 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7136                                       struct net_device *dev)
7137 {
7138         struct rtl8169_private *tp = netdev_priv(dev);
7139         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7140         struct TxDesc *txd = tp->TxDescArray + entry;
7141         void __iomem *ioaddr = tp->mmio_addr;
7142         struct device *d = &tp->pci_dev->dev;
7143         dma_addr_t mapping;
7144         u32 status, len;
7145         u32 opts[2];
7146         int frags;
7147
7148         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7149                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7150                 goto err_stop_0;
7151         }
7152
7153         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7154                 goto err_stop_0;
7155
7156         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7157         opts[0] = DescOwn;
7158
7159         if (!tp->tso_csum(tp, skb, opts)) {
7160                 r8169_csum_workaround(tp, skb);
7161                 return NETDEV_TX_OK;
7162         }
7163
7164         len = skb_headlen(skb);
7165         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7166         if (unlikely(dma_mapping_error(d, mapping))) {
7167                 if (net_ratelimit())
7168                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7169                 goto err_dma_0;
7170         }
7171
7172         tp->tx_skb[entry].len = len;
7173         txd->addr = cpu_to_le64(mapping);
7174
7175         frags = rtl8169_xmit_frags(tp, skb, opts);
7176         if (frags < 0)
7177                 goto err_dma_1;
7178         else if (frags)
7179                 opts[0] |= FirstFrag;
7180         else {
7181                 opts[0] |= FirstFrag | LastFrag;
7182                 tp->tx_skb[entry].skb = skb;
7183         }
7184
7185         txd->opts2 = cpu_to_le32(opts[1]);
7186
7187         skb_tx_timestamp(skb);
7188
7189         /* Force memory writes to complete before releasing descriptor */
7190         dma_wmb();
7191
7192         /* Anti gcc 2.95.3 bugware (sic) */
7193         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7194         txd->opts1 = cpu_to_le32(status);
7195
7196         /* Force all memory writes to complete before notifying device */
7197         wmb();
7198
7199         tp->cur_tx += frags + 1;
7200
7201         RTL_W8(TxPoll, NPQ);
7202
7203         mmiowb();
7204
7205         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7206                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7207                  * not miss a ring update when it notices a stopped queue.
7208                  */
7209                 smp_wmb();
7210                 netif_stop_queue(dev);
7211                 /* Sync with rtl_tx:
7212                  * - publish queue status and cur_tx ring index (write barrier)
7213                  * - refresh dirty_tx ring index (read barrier).
7214                  * May the current thread have a pessimistic view of the ring
7215                  * status and forget to wake up queue, a racing rtl_tx thread
7216                  * can't.
7217                  */
7218                 smp_mb();
7219                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7220                         netif_wake_queue(dev);
7221         }
7222
7223         return NETDEV_TX_OK;
7224
7225 err_dma_1:
7226         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7227 err_dma_0:
7228         dev_kfree_skb_any(skb);
7229         dev->stats.tx_dropped++;
7230         return NETDEV_TX_OK;
7231
7232 err_stop_0:
7233         netif_stop_queue(dev);
7234         dev->stats.tx_dropped++;
7235         return NETDEV_TX_BUSY;
7236 }
7237
7238 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7239 {
7240         struct rtl8169_private *tp = netdev_priv(dev);
7241         struct pci_dev *pdev = tp->pci_dev;
7242         u16 pci_status, pci_cmd;
7243
7244         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7245         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7246
7247         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7248                   pci_cmd, pci_status);
7249
7250         /*
7251          * The recovery sequence below admits a very elaborated explanation:
7252          * - it seems to work;
7253          * - I did not see what else could be done;
7254          * - it makes iop3xx happy.
7255          *
7256          * Feel free to adjust to your needs.
7257          */
7258         if (pdev->broken_parity_status)
7259                 pci_cmd &= ~PCI_COMMAND_PARITY;
7260         else
7261                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7262
7263         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7264
7265         pci_write_config_word(pdev, PCI_STATUS,
7266                 pci_status & (PCI_STATUS_DETECTED_PARITY |
7267                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7268                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7269
7270         /* The infamous DAC f*ckup only happens at boot time */
7271         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7272                 void __iomem *ioaddr = tp->mmio_addr;
7273
7274                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7275                 tp->cp_cmd &= ~PCIDAC;
7276                 RTL_W16(CPlusCmd, tp->cp_cmd);
7277                 dev->features &= ~NETIF_F_HIGHDMA;
7278         }
7279
7280         rtl8169_hw_reset(tp);
7281
7282         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7283 }
7284
7285 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7286 {
7287         unsigned int dirty_tx, tx_left;
7288
7289         dirty_tx = tp->dirty_tx;
7290         smp_rmb();
7291         tx_left = tp->cur_tx - dirty_tx;
7292
7293         while (tx_left > 0) {
7294                 unsigned int entry = dirty_tx % NUM_TX_DESC;
7295                 struct ring_info *tx_skb = tp->tx_skb + entry;
7296                 u32 status;
7297
7298                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7299                 if (status & DescOwn)
7300                         break;
7301
7302                 /* This barrier is needed to keep us from reading
7303                  * any other fields out of the Tx descriptor until
7304                  * we know the status of DescOwn
7305                  */
7306                 dma_rmb();
7307
7308                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7309                                      tp->TxDescArray + entry);
7310                 if (status & LastFrag) {
7311                         u64_stats_update_begin(&tp->tx_stats.syncp);
7312                         tp->tx_stats.packets++;
7313                         tp->tx_stats.bytes += tx_skb->skb->len;
7314                         u64_stats_update_end(&tp->tx_stats.syncp);
7315                         dev_consume_skb_any(tx_skb->skb);
7316                         tx_skb->skb = NULL;
7317                 }
7318                 dirty_tx++;
7319                 tx_left--;
7320         }
7321
7322         if (tp->dirty_tx != dirty_tx) {
7323                 tp->dirty_tx = dirty_tx;
7324                 /* Sync with rtl8169_start_xmit:
7325                  * - publish dirty_tx ring index (write barrier)
7326                  * - refresh cur_tx ring index and queue status (read barrier)
7327                  * May the current thread miss the stopped queue condition,
7328                  * a racing xmit thread can only have a right view of the
7329                  * ring status.
7330                  */
7331                 smp_mb();
7332                 if (netif_queue_stopped(dev) &&
7333                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7334                         netif_wake_queue(dev);
7335                 }
7336                 /*
7337                  * 8168 hack: TxPoll requests are lost when the Tx packets are
7338                  * too close. Let's kick an extra TxPoll request when a burst
7339                  * of start_xmit activity is detected (if it is not detected,
7340                  * it is slow enough). -- FR
7341                  */
7342                 if (tp->cur_tx != dirty_tx) {
7343                         void __iomem *ioaddr = tp->mmio_addr;
7344
7345                         RTL_W8(TxPoll, NPQ);
7346                 }
7347         }
7348 }
7349
7350 static inline int rtl8169_fragmented_frame(u32 status)
7351 {
7352         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7353 }
7354
7355 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7356 {
7357         u32 status = opts1 & RxProtoMask;
7358
7359         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7360             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7361                 skb->ip_summed = CHECKSUM_UNNECESSARY;
7362         else
7363                 skb_checksum_none_assert(skb);
7364 }
7365
7366 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7367                                            struct rtl8169_private *tp,
7368                                            int pkt_size,
7369                                            dma_addr_t addr)
7370 {
7371         struct sk_buff *skb;
7372         struct device *d = &tp->pci_dev->dev;
7373
7374         data = rtl8169_align(data);
7375         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7376         prefetch(data);
7377         skb = napi_alloc_skb(&tp->napi, pkt_size);
7378         if (skb)
7379                 memcpy(skb->data, data, pkt_size);
7380         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7381
7382         return skb;
7383 }
7384
7385 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7386 {
7387         unsigned int cur_rx, rx_left;
7388         unsigned int count;
7389
7390         cur_rx = tp->cur_rx;
7391
7392         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7393                 unsigned int entry = cur_rx % NUM_RX_DESC;
7394                 struct RxDesc *desc = tp->RxDescArray + entry;
7395                 u32 status;
7396
7397                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7398                 if (status & DescOwn)
7399                         break;
7400
7401                 /* This barrier is needed to keep us from reading
7402                  * any other fields out of the Rx descriptor until
7403                  * we know the status of DescOwn
7404                  */
7405                 dma_rmb();
7406
7407                 if (unlikely(status & RxRES)) {
7408                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7409                                    status);
7410                         dev->stats.rx_errors++;
7411                         if (status & (RxRWT | RxRUNT))
7412                                 dev->stats.rx_length_errors++;
7413                         if (status & RxCRC)
7414                                 dev->stats.rx_crc_errors++;
7415                         if (status & RxFOVF) {
7416                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7417                                 dev->stats.rx_fifo_errors++;
7418                         }
7419                         if ((status & (RxRUNT | RxCRC)) &&
7420                             !(status & (RxRWT | RxFOVF)) &&
7421                             (dev->features & NETIF_F_RXALL))
7422                                 goto process_pkt;
7423                 } else {
7424                         struct sk_buff *skb;
7425                         dma_addr_t addr;
7426                         int pkt_size;
7427
7428 process_pkt:
7429                         addr = le64_to_cpu(desc->addr);
7430                         if (likely(!(dev->features & NETIF_F_RXFCS)))
7431                                 pkt_size = (status & 0x00003fff) - 4;
7432                         else
7433                                 pkt_size = status & 0x00003fff;
7434
7435                         /*
7436                          * The driver does not support incoming fragmented
7437                          * frames. They are seen as a symptom of over-mtu
7438                          * sized frames.
7439                          */
7440                         if (unlikely(rtl8169_fragmented_frame(status))) {
7441                                 dev->stats.rx_dropped++;
7442                                 dev->stats.rx_length_errors++;
7443                                 goto release_descriptor;
7444                         }
7445
7446                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7447                                                   tp, pkt_size, addr);
7448                         if (!skb) {
7449                                 dev->stats.rx_dropped++;
7450                                 goto release_descriptor;
7451                         }
7452
7453                         rtl8169_rx_csum(skb, status);
7454                         skb_put(skb, pkt_size);
7455                         skb->protocol = eth_type_trans(skb, dev);
7456
7457                         rtl8169_rx_vlan_tag(desc, skb);
7458
7459                         if (skb->pkt_type == PACKET_MULTICAST)
7460                                 dev->stats.multicast++;
7461
7462                         napi_gro_receive(&tp->napi, skb);
7463
7464                         u64_stats_update_begin(&tp->rx_stats.syncp);
7465                         tp->rx_stats.packets++;
7466                         tp->rx_stats.bytes += pkt_size;
7467                         u64_stats_update_end(&tp->rx_stats.syncp);
7468                 }
7469 release_descriptor:
7470                 desc->opts2 = 0;
7471                 rtl8169_mark_to_asic(desc, rx_buf_sz);
7472         }
7473
7474         count = cur_rx - tp->cur_rx;
7475         tp->cur_rx = cur_rx;
7476
7477         return count;
7478 }
7479
7480 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7481 {
7482         struct net_device *dev = dev_instance;
7483         struct rtl8169_private *tp = netdev_priv(dev);
7484         int handled = 0;
7485         u16 status;
7486
7487         status = rtl_get_events(tp);
7488         if (status && status != 0xffff) {
7489                 status &= RTL_EVENT_NAPI | tp->event_slow;
7490                 if (status) {
7491                         handled = 1;
7492
7493                         rtl_irq_disable(tp);
7494                         napi_schedule(&tp->napi);
7495                 }
7496         }
7497         return IRQ_RETVAL(handled);
7498 }
7499
7500 /*
7501  * Workqueue context.
7502  */
7503 static void rtl_slow_event_work(struct rtl8169_private *tp)
7504 {
7505         struct net_device *dev = tp->dev;
7506         u16 status;
7507
7508         status = rtl_get_events(tp) & tp->event_slow;
7509         rtl_ack_events(tp, status);
7510
7511         if (unlikely(status & RxFIFOOver)) {
7512                 switch (tp->mac_version) {
7513                 /* Work around for rx fifo overflow */
7514                 case RTL_GIGA_MAC_VER_11:
7515                         netif_stop_queue(dev);
7516                         /* XXX - Hack alert. See rtl_task(). */
7517                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7518                 default:
7519                         break;
7520                 }
7521         }
7522
7523         if (unlikely(status & SYSErr))
7524                 rtl8169_pcierr_interrupt(dev);
7525
7526         if (status & LinkChg)
7527                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
7528
7529         rtl_irq_enable_all(tp);
7530 }
7531
7532 static void rtl_task(struct work_struct *work)
7533 {
7534         static const struct {
7535                 int bitnr;
7536                 void (*action)(struct rtl8169_private *);
7537         } rtl_work[] = {
7538                 /* XXX - keep rtl_slow_event_work() as first element. */
7539                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
7540                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
7541                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
7542         };
7543         struct rtl8169_private *tp =
7544                 container_of(work, struct rtl8169_private, wk.work);
7545         struct net_device *dev = tp->dev;
7546         int i;
7547
7548         rtl_lock_work(tp);
7549
7550         if (!netif_running(dev) ||
7551             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7552                 goto out_unlock;
7553
7554         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7555                 bool pending;
7556
7557                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7558                 if (pending)
7559                         rtl_work[i].action(tp);
7560         }
7561
7562 out_unlock:
7563         rtl_unlock_work(tp);
7564 }
7565
7566 static int rtl8169_poll(struct napi_struct *napi, int budget)
7567 {
7568         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7569         struct net_device *dev = tp->dev;
7570         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7571         int work_done;
7572         u16 status;
7573
7574         status = rtl_get_events(tp);
7575         rtl_ack_events(tp, status & ~tp->event_slow);
7576
7577         work_done = rtl_rx(dev, tp, (u32) budget);
7578
7579         rtl_tx(dev, tp);
7580
7581         if (status & tp->event_slow) {
7582                 enable_mask &= ~tp->event_slow;
7583
7584                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7585         }
7586
7587         if (work_done < budget) {
7588                 napi_complete_done(napi, work_done);
7589
7590                 rtl_irq_enable(tp, enable_mask);
7591                 mmiowb();
7592         }
7593
7594         return work_done;
7595 }
7596
7597 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7598 {
7599         struct rtl8169_private *tp = netdev_priv(dev);
7600
7601         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7602                 return;
7603
7604         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7605         RTL_W32(RxMissed, 0);
7606 }
7607
7608 static void rtl8169_down(struct net_device *dev)
7609 {
7610         struct rtl8169_private *tp = netdev_priv(dev);
7611         void __iomem *ioaddr = tp->mmio_addr;
7612
7613         del_timer_sync(&tp->timer);
7614
7615         napi_disable(&tp->napi);
7616         netif_stop_queue(dev);
7617
7618         rtl8169_hw_reset(tp);
7619         /*
7620          * At this point device interrupts can not be enabled in any function,
7621          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7622          * and napi is disabled (rtl8169_poll).
7623          */
7624         rtl8169_rx_missed(dev, ioaddr);
7625
7626         /* Give a racing hard_start_xmit a few cycles to complete. */
7627         synchronize_sched();
7628
7629         rtl8169_tx_clear(tp);
7630
7631         rtl8169_rx_clear(tp);
7632
7633         rtl_pll_power_down(tp);
7634 }
7635
7636 static int rtl8169_close(struct net_device *dev)
7637 {
7638         struct rtl8169_private *tp = netdev_priv(dev);
7639         struct pci_dev *pdev = tp->pci_dev;
7640
7641         pm_runtime_get_sync(&pdev->dev);
7642
7643         /* Update counters before going down */
7644         rtl8169_update_counters(dev);
7645
7646         rtl_lock_work(tp);
7647         /* Clear all task flags */
7648         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
7649
7650         rtl8169_down(dev);
7651         rtl_unlock_work(tp);
7652
7653         cancel_work_sync(&tp->wk.work);
7654
7655         free_irq(pdev->irq, dev);
7656
7657         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7658                           tp->RxPhyAddr);
7659         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7660                           tp->TxPhyAddr);
7661         tp->TxDescArray = NULL;
7662         tp->RxDescArray = NULL;
7663
7664         pm_runtime_put_sync(&pdev->dev);
7665
7666         return 0;
7667 }
7668
7669 #ifdef CONFIG_NET_POLL_CONTROLLER
7670 static void rtl8169_netpoll(struct net_device *dev)
7671 {
7672         struct rtl8169_private *tp = netdev_priv(dev);
7673
7674         rtl8169_interrupt(tp->pci_dev->irq, dev);
7675 }
7676 #endif
7677
7678 static int rtl_open(struct net_device *dev)
7679 {
7680         struct rtl8169_private *tp = netdev_priv(dev);
7681         void __iomem *ioaddr = tp->mmio_addr;
7682         struct pci_dev *pdev = tp->pci_dev;
7683         int retval = -ENOMEM;
7684
7685         pm_runtime_get_sync(&pdev->dev);
7686
7687         /*
7688          * Rx and Tx descriptors needs 256 bytes alignment.
7689          * dma_alloc_coherent provides more.
7690          */
7691         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7692                                              &tp->TxPhyAddr, GFP_KERNEL);
7693         if (!tp->TxDescArray)
7694                 goto err_pm_runtime_put;
7695
7696         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7697                                              &tp->RxPhyAddr, GFP_KERNEL);
7698         if (!tp->RxDescArray)
7699                 goto err_free_tx_0;
7700
7701         retval = rtl8169_init_ring(dev);
7702         if (retval < 0)
7703                 goto err_free_rx_1;
7704
7705         INIT_WORK(&tp->wk.work, rtl_task);
7706
7707         smp_mb();
7708
7709         rtl_request_firmware(tp);
7710
7711         retval = request_irq(pdev->irq, rtl8169_interrupt,
7712                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7713                              dev->name, dev);
7714         if (retval < 0)
7715                 goto err_release_fw_2;
7716
7717         rtl_lock_work(tp);
7718
7719         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7720
7721         napi_enable(&tp->napi);
7722
7723         rtl8169_init_phy(dev, tp);
7724
7725         __rtl8169_set_features(dev, dev->features);
7726
7727         rtl_pll_power_up(tp);
7728
7729         rtl_hw_start(dev);
7730
7731         if (!rtl8169_init_counter_offsets(dev))
7732                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7733
7734         netif_start_queue(dev);
7735
7736         rtl_unlock_work(tp);
7737
7738         tp->saved_wolopts = 0;
7739         pm_runtime_put_noidle(&pdev->dev);
7740
7741         rtl8169_check_link_status(dev, tp, ioaddr);
7742 out:
7743         return retval;
7744
7745 err_release_fw_2:
7746         rtl_release_firmware(tp);
7747         rtl8169_rx_clear(tp);
7748 err_free_rx_1:
7749         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7750                           tp->RxPhyAddr);
7751         tp->RxDescArray = NULL;
7752 err_free_tx_0:
7753         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7754                           tp->TxPhyAddr);
7755         tp->TxDescArray = NULL;
7756 err_pm_runtime_put:
7757         pm_runtime_put_noidle(&pdev->dev);
7758         goto out;
7759 }
7760
7761 static void
7762 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7763 {
7764         struct rtl8169_private *tp = netdev_priv(dev);
7765         void __iomem *ioaddr = tp->mmio_addr;
7766         struct pci_dev *pdev = tp->pci_dev;
7767         struct rtl8169_counters *counters = tp->counters;
7768         unsigned int start;
7769
7770         pm_runtime_get_noresume(&pdev->dev);
7771
7772         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
7773                 rtl8169_rx_missed(dev, ioaddr);
7774
7775         do {
7776                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7777                 stats->rx_packets = tp->rx_stats.packets;
7778                 stats->rx_bytes = tp->rx_stats.bytes;
7779         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7780
7781         do {
7782                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7783                 stats->tx_packets = tp->tx_stats.packets;
7784                 stats->tx_bytes = tp->tx_stats.bytes;
7785         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7786
7787         stats->rx_dropped       = dev->stats.rx_dropped;
7788         stats->tx_dropped       = dev->stats.tx_dropped;
7789         stats->rx_length_errors = dev->stats.rx_length_errors;
7790         stats->rx_errors        = dev->stats.rx_errors;
7791         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
7792         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
7793         stats->rx_missed_errors = dev->stats.rx_missed_errors;
7794         stats->multicast        = dev->stats.multicast;
7795
7796         /*
7797          * Fetch additonal counter values missing in stats collected by driver
7798          * from tally counters.
7799          */
7800         if (pm_runtime_active(&pdev->dev))
7801                 rtl8169_update_counters(dev);
7802
7803         /*
7804          * Subtract values fetched during initalization.
7805          * See rtl8169_init_counter_offsets for a description why we do that.
7806          */
7807         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
7808                 le64_to_cpu(tp->tc_offset.tx_errors);
7809         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
7810                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
7811         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
7812                 le16_to_cpu(tp->tc_offset.tx_aborted);
7813
7814         pm_runtime_put_noidle(&pdev->dev);
7815 }
7816
7817 static void rtl8169_net_suspend(struct net_device *dev)
7818 {
7819         struct rtl8169_private *tp = netdev_priv(dev);
7820
7821         if (!netif_running(dev))
7822                 return;
7823
7824         netif_device_detach(dev);
7825         netif_stop_queue(dev);
7826
7827         rtl_lock_work(tp);
7828         napi_disable(&tp->napi);
7829         /* Clear all task flags */
7830         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
7831
7832         rtl_unlock_work(tp);
7833
7834         rtl_pll_power_down(tp);
7835 }
7836
7837 #ifdef CONFIG_PM
7838
7839 static int rtl8169_suspend(struct device *device)
7840 {
7841         struct pci_dev *pdev = to_pci_dev(device);
7842         struct net_device *dev = pci_get_drvdata(pdev);
7843
7844         rtl8169_net_suspend(dev);
7845
7846         return 0;
7847 }
7848
7849 static void __rtl8169_resume(struct net_device *dev)
7850 {
7851         struct rtl8169_private *tp = netdev_priv(dev);
7852
7853         netif_device_attach(dev);
7854
7855         rtl_pll_power_up(tp);
7856
7857         rtl_lock_work(tp);
7858         napi_enable(&tp->napi);
7859         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7860         rtl_unlock_work(tp);
7861
7862         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7863 }
7864
7865 static int rtl8169_resume(struct device *device)
7866 {
7867         struct pci_dev *pdev = to_pci_dev(device);
7868         struct net_device *dev = pci_get_drvdata(pdev);
7869         struct rtl8169_private *tp = netdev_priv(dev);
7870
7871         rtl8169_init_phy(dev, tp);
7872
7873         if (netif_running(dev))
7874                 __rtl8169_resume(dev);
7875
7876         return 0;
7877 }
7878
7879 static int rtl8169_runtime_suspend(struct device *device)
7880 {
7881         struct pci_dev *pdev = to_pci_dev(device);
7882         struct net_device *dev = pci_get_drvdata(pdev);
7883         struct rtl8169_private *tp = netdev_priv(dev);
7884
7885         if (!tp->TxDescArray)
7886                 return 0;
7887
7888         rtl_lock_work(tp);
7889         tp->saved_wolopts = __rtl8169_get_wol(tp);
7890         __rtl8169_set_wol(tp, WAKE_ANY);
7891         rtl_unlock_work(tp);
7892
7893         rtl8169_net_suspend(dev);
7894
7895         /* Update counters before going runtime suspend */
7896         rtl8169_rx_missed(dev, tp->mmio_addr);
7897         rtl8169_update_counters(dev);
7898
7899         return 0;
7900 }
7901
7902 static int rtl8169_runtime_resume(struct device *device)
7903 {
7904         struct pci_dev *pdev = to_pci_dev(device);
7905         struct net_device *dev = pci_get_drvdata(pdev);
7906         struct rtl8169_private *tp = netdev_priv(dev);
7907         rtl_rar_set(tp, dev->dev_addr);
7908
7909         if (!tp->TxDescArray)
7910                 return 0;
7911
7912         rtl_lock_work(tp);
7913         __rtl8169_set_wol(tp, tp->saved_wolopts);
7914         tp->saved_wolopts = 0;
7915         rtl_unlock_work(tp);
7916
7917         rtl8169_init_phy(dev, tp);
7918
7919         __rtl8169_resume(dev);
7920
7921         return 0;
7922 }
7923
7924 static int rtl8169_runtime_idle(struct device *device)
7925 {
7926         struct pci_dev *pdev = to_pci_dev(device);
7927         struct net_device *dev = pci_get_drvdata(pdev);
7928         struct rtl8169_private *tp = netdev_priv(dev);
7929
7930         return tp->TxDescArray ? -EBUSY : 0;
7931 }
7932
7933 static const struct dev_pm_ops rtl8169_pm_ops = {
7934         .suspend                = rtl8169_suspend,
7935         .resume                 = rtl8169_resume,
7936         .freeze                 = rtl8169_suspend,
7937         .thaw                   = rtl8169_resume,
7938         .poweroff               = rtl8169_suspend,
7939         .restore                = rtl8169_resume,
7940         .runtime_suspend        = rtl8169_runtime_suspend,
7941         .runtime_resume         = rtl8169_runtime_resume,
7942         .runtime_idle           = rtl8169_runtime_idle,
7943 };
7944
7945 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
7946
7947 #else /* !CONFIG_PM */
7948
7949 #define RTL8169_PM_OPS  NULL
7950
7951 #endif /* !CONFIG_PM */
7952
7953 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7954 {
7955         void __iomem *ioaddr = tp->mmio_addr;
7956
7957         /* WoL fails with 8168b when the receiver is disabled. */
7958         switch (tp->mac_version) {
7959         case RTL_GIGA_MAC_VER_11:
7960         case RTL_GIGA_MAC_VER_12:
7961         case RTL_GIGA_MAC_VER_17:
7962                 pci_clear_master(tp->pci_dev);
7963
7964                 RTL_W8(ChipCmd, CmdRxEnb);
7965                 /* PCI commit */
7966                 RTL_R8(ChipCmd);
7967                 break;
7968         default:
7969                 break;
7970         }
7971 }
7972
7973 static void rtl_shutdown(struct pci_dev *pdev)
7974 {
7975         struct net_device *dev = pci_get_drvdata(pdev);
7976         struct rtl8169_private *tp = netdev_priv(dev);
7977         struct device *d = &pdev->dev;
7978
7979         pm_runtime_get_sync(d);
7980
7981         rtl8169_net_suspend(dev);
7982
7983         /* Restore original MAC address */
7984         rtl_rar_set(tp, dev->perm_addr);
7985
7986         rtl8169_hw_reset(tp);
7987
7988         if (system_state == SYSTEM_POWER_OFF) {
7989                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7990                         rtl_wol_suspend_quirk(tp);
7991                         rtl_wol_shutdown_quirk(tp);
7992                 }
7993
7994                 pci_wake_from_d3(pdev, true);
7995                 pci_set_power_state(pdev, PCI_D3hot);
7996         }
7997
7998         pm_runtime_put_noidle(d);
7999 }
8000
8001 static void rtl_remove_one(struct pci_dev *pdev)
8002 {
8003         struct net_device *dev = pci_get_drvdata(pdev);
8004         struct rtl8169_private *tp = netdev_priv(dev);
8005
8006         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8007              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8008              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8009              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8010              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8011              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8012             r8168_check_dash(tp)) {
8013                 rtl8168_driver_stop(tp);
8014         }
8015
8016         netif_napi_del(&tp->napi);
8017
8018         unregister_netdev(dev);
8019
8020         dma_free_coherent(&tp->pci_dev->dev, sizeof(*tp->counters),
8021                           tp->counters, tp->counters_phys_addr);
8022
8023         rtl_release_firmware(tp);
8024
8025         if (pci_dev_run_wake(pdev))
8026                 pm_runtime_get_noresume(&pdev->dev);
8027
8028         /* restore original MAC address */
8029         rtl_rar_set(tp, dev->perm_addr);
8030
8031         rtl_disable_msi(pdev, tp);
8032         rtl8169_release_board(pdev, dev, tp->mmio_addr);
8033 }
8034
8035 static const struct net_device_ops rtl_netdev_ops = {
8036         .ndo_open               = rtl_open,
8037         .ndo_stop               = rtl8169_close,
8038         .ndo_get_stats64        = rtl8169_get_stats64,
8039         .ndo_start_xmit         = rtl8169_start_xmit,
8040         .ndo_tx_timeout         = rtl8169_tx_timeout,
8041         .ndo_validate_addr      = eth_validate_addr,
8042         .ndo_change_mtu         = rtl8169_change_mtu,
8043         .ndo_fix_features       = rtl8169_fix_features,
8044         .ndo_set_features       = rtl8169_set_features,
8045         .ndo_set_mac_address    = rtl_set_mac_address,
8046         .ndo_do_ioctl           = rtl8169_ioctl,
8047         .ndo_set_rx_mode        = rtl_set_rx_mode,
8048 #ifdef CONFIG_NET_POLL_CONTROLLER
8049         .ndo_poll_controller    = rtl8169_netpoll,
8050 #endif
8051
8052 };
8053
8054 static const struct rtl_cfg_info {
8055         void (*hw_start)(struct net_device *);
8056         unsigned int region;
8057         unsigned int align;
8058         u16 event_slow;
8059         unsigned features;
8060         u8 default_ver;
8061 } rtl_cfg_infos [] = {
8062         [RTL_CFG_0] = {
8063                 .hw_start       = rtl_hw_start_8169,
8064                 .region         = 1,
8065                 .align          = 0,
8066                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8067                 .features       = RTL_FEATURE_GMII,
8068                 .default_ver    = RTL_GIGA_MAC_VER_01,
8069         },
8070         [RTL_CFG_1] = {
8071                 .hw_start       = rtl_hw_start_8168,
8072                 .region         = 2,
8073                 .align          = 8,
8074                 .event_slow     = SYSErr | LinkChg | RxOverflow,
8075                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8076                 .default_ver    = RTL_GIGA_MAC_VER_11,
8077         },
8078         [RTL_CFG_2] = {
8079                 .hw_start       = rtl_hw_start_8101,
8080                 .region         = 2,
8081                 .align          = 8,
8082                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8083                                   PCSTimeout,
8084                 .features       = RTL_FEATURE_MSI,
8085                 .default_ver    = RTL_GIGA_MAC_VER_13,
8086         }
8087 };
8088
8089 /* Cfg9346_Unlock assumed. */
8090 static unsigned rtl_try_msi(struct rtl8169_private *tp,
8091                             const struct rtl_cfg_info *cfg)
8092 {
8093         void __iomem *ioaddr = tp->mmio_addr;
8094         unsigned msi = 0;
8095         u8 cfg2;
8096
8097         cfg2 = RTL_R8(Config2) & ~MSIEnable;
8098         if (cfg->features & RTL_FEATURE_MSI) {
8099                 if (pci_enable_msi(tp->pci_dev)) {
8100                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8101                 } else {
8102                         cfg2 |= MSIEnable;
8103                         msi = RTL_FEATURE_MSI;
8104                 }
8105         }
8106         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8107                 RTL_W8(Config2, cfg2);
8108         return msi;
8109 }
8110
8111 DECLARE_RTL_COND(rtl_link_list_ready_cond)
8112 {
8113         void __iomem *ioaddr = tp->mmio_addr;
8114
8115         return RTL_R8(MCU) & LINK_LIST_RDY;
8116 }
8117
8118 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8119 {
8120         void __iomem *ioaddr = tp->mmio_addr;
8121
8122         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8123 }
8124
8125 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8126 {
8127         void __iomem *ioaddr = tp->mmio_addr;
8128         u32 data;
8129
8130         tp->ocp_base = OCP_STD_PHY_BASE;
8131
8132         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8133
8134         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8135                 return;
8136
8137         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8138                 return;
8139
8140         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8141         msleep(1);
8142         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8143
8144         data = r8168_mac_ocp_read(tp, 0xe8de);
8145         data &= ~(1 << 14);
8146         r8168_mac_ocp_write(tp, 0xe8de, data);
8147
8148         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8149                 return;
8150
8151         data = r8168_mac_ocp_read(tp, 0xe8de);
8152         data |= (1 << 15);
8153         r8168_mac_ocp_write(tp, 0xe8de, data);
8154
8155         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8156                 return;
8157 }
8158
8159 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8160 {
8161         rtl8168ep_stop_cmac(tp);
8162         rtl_hw_init_8168g(tp);
8163 }
8164
8165 static void rtl_hw_initialize(struct rtl8169_private *tp)
8166 {
8167         switch (tp->mac_version) {
8168         case RTL_GIGA_MAC_VER_40:
8169         case RTL_GIGA_MAC_VER_41:
8170         case RTL_GIGA_MAC_VER_42:
8171         case RTL_GIGA_MAC_VER_43:
8172         case RTL_GIGA_MAC_VER_44:
8173         case RTL_GIGA_MAC_VER_45:
8174         case RTL_GIGA_MAC_VER_46:
8175         case RTL_GIGA_MAC_VER_47:
8176         case RTL_GIGA_MAC_VER_48:
8177                 rtl_hw_init_8168g(tp);
8178                 break;
8179         case RTL_GIGA_MAC_VER_49:
8180         case RTL_GIGA_MAC_VER_50:
8181         case RTL_GIGA_MAC_VER_51:
8182                 rtl_hw_init_8168ep(tp);
8183                 break;
8184         default:
8185                 break;
8186         }
8187 }
8188
8189 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8190 {
8191         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8192         const unsigned int region = cfg->region;
8193         struct rtl8169_private *tp;
8194         struct mii_if_info *mii;
8195         struct net_device *dev;
8196         void __iomem *ioaddr;
8197         int chipset, i;
8198         int rc;
8199
8200         if (netif_msg_drv(&debug)) {
8201                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8202                        MODULENAME, RTL8169_VERSION);
8203         }
8204
8205         dev = alloc_etherdev(sizeof (*tp));
8206         if (!dev) {
8207                 rc = -ENOMEM;
8208                 goto out;
8209         }
8210
8211         SET_NETDEV_DEV(dev, &pdev->dev);
8212         dev->netdev_ops = &rtl_netdev_ops;
8213         tp = netdev_priv(dev);
8214         tp->dev = dev;
8215         tp->pci_dev = pdev;
8216         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8217
8218         mii = &tp->mii;
8219         mii->dev = dev;
8220         mii->mdio_read = rtl_mdio_read;
8221         mii->mdio_write = rtl_mdio_write;
8222         mii->phy_id_mask = 0x1f;
8223         mii->reg_num_mask = 0x1f;
8224         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8225
8226         /* disable ASPM completely as that cause random device stop working
8227          * problems as well as full system hangs for some PCIe devices users */
8228         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8229                                      PCIE_LINK_STATE_CLKPM);
8230
8231         /* enable device (incl. PCI PM wakeup and hotplug setup) */
8232         rc = pci_enable_device(pdev);
8233         if (rc < 0) {
8234                 netif_err(tp, probe, dev, "enable failure\n");
8235                 goto err_out_free_dev_1;
8236         }
8237
8238         if (pci_set_mwi(pdev) < 0)
8239                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8240
8241         /* make sure PCI base addr 1 is MMIO */
8242         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8243                 netif_err(tp, probe, dev,
8244                           "region #%d not an MMIO resource, aborting\n",
8245                           region);
8246                 rc = -ENODEV;
8247                 goto err_out_mwi_2;
8248         }
8249
8250         /* check for weird/broken PCI region reporting */
8251         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8252                 netif_err(tp, probe, dev,
8253                           "Invalid PCI region size(s), aborting\n");
8254                 rc = -ENODEV;
8255                 goto err_out_mwi_2;
8256         }
8257
8258         rc = pci_request_regions(pdev, MODULENAME);
8259         if (rc < 0) {
8260                 netif_err(tp, probe, dev, "could not request regions\n");
8261                 goto err_out_mwi_2;
8262         }
8263
8264         /* ioremap MMIO region */
8265         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8266         if (!ioaddr) {
8267                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8268                 rc = -EIO;
8269                 goto err_out_free_res_3;
8270         }
8271         tp->mmio_addr = ioaddr;
8272
8273         if (!pci_is_pcie(pdev))
8274                 netif_info(tp, probe, dev, "not PCI Express\n");
8275
8276         /* Identify chip attached to board */
8277         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8278
8279         tp->cp_cmd = 0;
8280
8281         if ((sizeof(dma_addr_t) > 4) &&
8282             (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8283                               tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
8284             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
8285             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
8286
8287                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8288                 if (!pci_is_pcie(pdev))
8289                         tp->cp_cmd |= PCIDAC;
8290                 dev->features |= NETIF_F_HIGHDMA;
8291         } else {
8292                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8293                 if (rc < 0) {
8294                         netif_err(tp, probe, dev, "DMA configuration failed\n");
8295                         goto err_out_unmap_4;
8296                 }
8297         }
8298
8299         rtl_init_rxcfg(tp);
8300
8301         rtl_irq_disable(tp);
8302
8303         rtl_hw_initialize(tp);
8304
8305         rtl_hw_reset(tp);
8306
8307         rtl_ack_events(tp, 0xffff);
8308
8309         pci_set_master(pdev);
8310
8311         rtl_init_mdio_ops(tp);
8312         rtl_init_pll_power_ops(tp);
8313         rtl_init_jumbo_ops(tp);
8314         rtl_init_csi_ops(tp);
8315
8316         rtl8169_print_mac_version(tp);
8317
8318         chipset = tp->mac_version;
8319         tp->txd_version = rtl_chip_infos[chipset].txd_version;
8320
8321         RTL_W8(Cfg9346, Cfg9346_Unlock);
8322         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8323         RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8324         switch (tp->mac_version) {
8325         case RTL_GIGA_MAC_VER_34:
8326         case RTL_GIGA_MAC_VER_35:
8327         case RTL_GIGA_MAC_VER_36:
8328         case RTL_GIGA_MAC_VER_37:
8329         case RTL_GIGA_MAC_VER_38:
8330         case RTL_GIGA_MAC_VER_40:
8331         case RTL_GIGA_MAC_VER_41:
8332         case RTL_GIGA_MAC_VER_42:
8333         case RTL_GIGA_MAC_VER_43:
8334         case RTL_GIGA_MAC_VER_44:
8335         case RTL_GIGA_MAC_VER_45:
8336         case RTL_GIGA_MAC_VER_46:
8337         case RTL_GIGA_MAC_VER_47:
8338         case RTL_GIGA_MAC_VER_48:
8339         case RTL_GIGA_MAC_VER_49:
8340         case RTL_GIGA_MAC_VER_50:
8341         case RTL_GIGA_MAC_VER_51:
8342                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8343                         tp->features |= RTL_FEATURE_WOL;
8344                 if ((RTL_R8(Config3) & LinkUp) != 0)
8345                         tp->features |= RTL_FEATURE_WOL;
8346                 break;
8347         default:
8348                 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8349                         tp->features |= RTL_FEATURE_WOL;
8350                 break;
8351         }
8352         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8353                 tp->features |= RTL_FEATURE_WOL;
8354         tp->features |= rtl_try_msi(tp, cfg);
8355         RTL_W8(Cfg9346, Cfg9346_Lock);
8356
8357         if (rtl_tbi_enabled(tp)) {
8358                 tp->set_speed = rtl8169_set_speed_tbi;
8359                 tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi;
8360                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8361                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8362                 tp->link_ok = rtl8169_tbi_link_ok;
8363                 tp->do_ioctl = rtl_tbi_ioctl;
8364         } else {
8365                 tp->set_speed = rtl8169_set_speed_xmii;
8366                 tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii;
8367                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8368                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8369                 tp->link_ok = rtl8169_xmii_link_ok;
8370                 tp->do_ioctl = rtl_xmii_ioctl;
8371         }
8372
8373         mutex_init(&tp->wk.mutex);
8374         u64_stats_init(&tp->rx_stats.syncp);
8375         u64_stats_init(&tp->tx_stats.syncp);
8376
8377         /* Get MAC address */
8378         if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8379             tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8380             tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8381             tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8382             tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8383             tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8384             tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8385             tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8386             tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8387             tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8388             tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8389             tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8390             tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8391             tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8392             tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8393             tp->mac_version == RTL_GIGA_MAC_VER_51) {
8394                 u16 mac_addr[3];
8395
8396                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8397                 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8398
8399                 if (is_valid_ether_addr((u8 *)mac_addr))
8400                         rtl_rar_set(tp, (u8 *)mac_addr);
8401         }
8402         for (i = 0; i < ETH_ALEN; i++)
8403                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8404
8405         dev->ethtool_ops = &rtl8169_ethtool_ops;
8406         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8407
8408         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8409
8410         /* don't enable SG, IP_CSUM and TSO by default - it might not work
8411          * properly for all devices */
8412         dev->features |= NETIF_F_RXCSUM |
8413                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8414
8415         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8416                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8417                 NETIF_F_HW_VLAN_CTAG_RX;
8418         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8419                 NETIF_F_HIGHDMA;
8420
8421         tp->cp_cmd |= RxChkSum | RxVlan;
8422
8423         /*
8424          * Pretend we are using VLANs; This bypasses a nasty bug where
8425          * Interrupts stop flowing on high load on 8110SCd controllers.
8426          */
8427         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8428                 /* Disallow toggling */
8429                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8430
8431         if (tp->txd_version == RTL_TD_0)
8432                 tp->tso_csum = rtl8169_tso_csum_v1;
8433         else if (tp->txd_version == RTL_TD_1) {
8434                 tp->tso_csum = rtl8169_tso_csum_v2;
8435                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8436         } else
8437                 WARN_ON_ONCE(1);
8438
8439         dev->hw_features |= NETIF_F_RXALL;
8440         dev->hw_features |= NETIF_F_RXFCS;
8441
8442         /* MTU range: 60 - hw-specific max */
8443         dev->min_mtu = ETH_ZLEN;
8444         dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
8445
8446         tp->hw_start = cfg->hw_start;
8447         tp->event_slow = cfg->event_slow;
8448
8449         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8450                 ~(RxBOVF | RxFOVF) : ~0;
8451
8452         setup_timer(&tp->timer, rtl8169_phy_timer, (unsigned long)dev);
8453
8454         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8455
8456         tp->counters = dma_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8457                                            &tp->counters_phys_addr, GFP_KERNEL);
8458         if (!tp->counters) {
8459                 rc = -ENOMEM;
8460                 goto err_out_msi_5;
8461         }
8462
8463         pci_set_drvdata(pdev, dev);
8464
8465         rc = register_netdev(dev);
8466         if (rc < 0)
8467                 goto err_out_cnt_6;
8468
8469         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8470                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8471                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8472         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8473                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8474                            "tx checksumming: %s]\n",
8475                            rtl_chip_infos[chipset].jumbo_max,
8476                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8477         }
8478
8479         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8480              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8481              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8482              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8483              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8484              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8485             r8168_check_dash(tp)) {
8486                 rtl8168_driver_start(tp);
8487         }
8488
8489         if (pci_dev_run_wake(pdev))
8490                 pm_runtime_put_noidle(&pdev->dev);
8491
8492         netif_carrier_off(dev);
8493
8494 out:
8495         return rc;
8496
8497 err_out_cnt_6:
8498         dma_free_coherent(&pdev->dev, sizeof(*tp->counters), tp->counters,
8499                           tp->counters_phys_addr);
8500 err_out_msi_5:
8501         netif_napi_del(&tp->napi);
8502         rtl_disable_msi(pdev, tp);
8503 err_out_unmap_4:
8504         iounmap(ioaddr);
8505 err_out_free_res_3:
8506         pci_release_regions(pdev);
8507 err_out_mwi_2:
8508         pci_clear_mwi(pdev);
8509         pci_disable_device(pdev);
8510 err_out_free_dev_1:
8511         free_netdev(dev);
8512         goto out;
8513 }
8514
8515 static struct pci_driver rtl8169_pci_driver = {
8516         .name           = MODULENAME,
8517         .id_table       = rtl8169_pci_tbl,
8518         .probe          = rtl_init_one,
8519         .remove         = rtl_remove_one,
8520         .shutdown       = rtl_shutdown,
8521         .driver.pm      = RTL8169_PM_OPS,
8522 };
8523
8524 module_pci_driver(rtl8169_pci_driver);