2 * RDC R6040 Fast Ethernet MAC support
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Copyright (C) 2007-2012 Florian Fainelli <f.fainelli@gmail.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/string.h>
29 #include <linux/timer.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/interrupt.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/delay.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/crc32.h>
41 #include <linux/spinlock.h>
42 #include <linux/bitops.h>
44 #include <linux/irq.h>
45 #include <linux/uaccess.h>
46 #include <linux/phy.h>
48 #include <asm/processor.h>
50 #define DRV_NAME "r6040"
51 #define DRV_VERSION "0.29"
52 #define DRV_RELDATE "04Jul2016"
54 /* Time in jiffies before concluding the transmitter is hung. */
55 #define TX_TIMEOUT (6000 * HZ / 1000)
57 /* RDC MAC I/O Size */
58 #define R6040_IO_SIZE 256
64 #define MCR0 0x00 /* Control register 0 */
65 #define MCR0_RCVEN 0x0002 /* Receive enable */
66 #define MCR0_PROMISC 0x0020 /* Promiscuous mode */
67 #define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */
68 #define MCR0_XMTEN 0x1000 /* Transmission enable */
69 #define MCR0_FD 0x8000 /* Full/Half duplex */
70 #define MCR1 0x04 /* Control register 1 */
71 #define MAC_RST 0x0001 /* Reset the MAC */
72 #define MBCR 0x08 /* Bus control */
73 #define MT_ICR 0x0C /* TX interrupt control */
74 #define MR_ICR 0x10 /* RX interrupt control */
75 #define MTPR 0x14 /* TX poll command register */
76 #define TM2TX 0x0001 /* Trigger MAC to transmit */
77 #define MR_BSR 0x18 /* RX buffer size */
78 #define MR_DCR 0x1A /* RX descriptor control */
79 #define MLSR 0x1C /* Last status */
80 #define TX_FIFO_UNDR 0x0200 /* TX FIFO under-run */
81 #define TX_EXCEEDC 0x2000 /* Transmit exceed collision */
82 #define TX_LATEC 0x4000 /* Transmit late collision */
83 #define MMDIO 0x20 /* MDIO control register */
84 #define MDIO_WRITE 0x4000 /* MDIO write */
85 #define MDIO_READ 0x2000 /* MDIO read */
86 #define MMRD 0x24 /* MDIO read data register */
87 #define MMWD 0x28 /* MDIO write data register */
88 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
89 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
90 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
91 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
92 #define MISR 0x3C /* Status register */
93 #define MIER 0x40 /* INT enable register */
94 #define MSK_INT 0x0000 /* Mask off interrupts */
95 #define RX_FINISH 0x0001 /* RX finished */
96 #define RX_NO_DESC 0x0002 /* No RX descriptor available */
97 #define RX_FIFO_FULL 0x0004 /* RX FIFO full */
98 #define RX_EARLY 0x0008 /* RX early */
99 #define TX_FINISH 0x0010 /* TX finished */
100 #define TX_EARLY 0x0080 /* TX early */
101 #define EVENT_OVRFL 0x0100 /* Event counter overflow */
102 #define LINK_CHANGED 0x0200 /* PHY link changed */
103 #define ME_CISR 0x44 /* Event counter INT status */
104 #define ME_CIER 0x48 /* Event counter INT enable */
105 #define MR_CNT 0x50 /* Successfully received packet counter */
106 #define ME_CNT0 0x52 /* Event counter 0 */
107 #define ME_CNT1 0x54 /* Event counter 1 */
108 #define ME_CNT2 0x56 /* Event counter 2 */
109 #define ME_CNT3 0x58 /* Event counter 3 */
110 #define MT_CNT 0x5A /* Successfully transmit packet counter */
111 #define ME_CNT4 0x5C /* Event counter 4 */
112 #define MP_CNT 0x5E /* Pause frame counter register */
113 #define MAR0 0x60 /* Hash table 0 */
114 #define MAR1 0x62 /* Hash table 1 */
115 #define MAR2 0x64 /* Hash table 2 */
116 #define MAR3 0x66 /* Hash table 3 */
117 #define MID_0L 0x68 /* Multicast address MID0 Low */
118 #define MID_0M 0x6A /* Multicast address MID0 Medium */
119 #define MID_0H 0x6C /* Multicast address MID0 High */
120 #define MID_1L 0x70 /* MID1 Low */
121 #define MID_1M 0x72 /* MID1 Medium */
122 #define MID_1H 0x74 /* MID1 High */
123 #define MID_2L 0x78 /* MID2 Low */
124 #define MID_2M 0x7A /* MID2 Medium */
125 #define MID_2H 0x7C /* MID2 High */
126 #define MID_3L 0x80 /* MID3 Low */
127 #define MID_3M 0x82 /* MID3 Medium */
128 #define MID_3H 0x84 /* MID3 High */
129 #define PHY_CC 0x88 /* PHY status change configuration register */
130 #define SCEN 0x8000 /* PHY status change enable */
131 #define PHYAD_SHIFT 8 /* PHY address shift */
132 #define TMRDIV_SHIFT 0 /* Timer divider shift */
133 #define PHY_ST 0x8A /* PHY status register */
134 #define MAC_SM 0xAC /* MAC status machine */
135 #define MAC_SM_RST 0x0002 /* MAC status machine reset */
136 #define MD_CSC 0xb6 /* MDC speed control register */
137 #define MD_CSC_DEFAULT 0x0030
138 #define MAC_ID 0xBE /* Identifier register */
140 #define TX_DCNT 0x80 /* TX descriptor count */
141 #define RX_DCNT 0x80 /* RX descriptor count */
142 #define MAX_BUF_SIZE 0x600
143 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
144 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
145 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
146 #define MCAST_MAX 3 /* Max number multicast addresses to filter */
148 #define MAC_DEF_TIMEOUT 2048 /* Default MAC read/write operation timeout */
150 /* Descriptor status */
151 #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
152 #define DSC_RX_OK 0x4000 /* RX was successful */
153 #define DSC_RX_ERR 0x0800 /* RX PHY error */
154 #define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
155 #define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
156 #define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
157 #define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
158 #define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
159 #define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
160 #define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
161 #define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
162 #define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
163 #define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
165 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
166 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
167 "Florian Fainelli <f.fainelli@gmail.com>");
168 MODULE_LICENSE("GPL");
169 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
170 MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
172 /* RX and TX interrupts that we handle */
173 #define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
174 #define TX_INTS (TX_FINISH)
175 #define INT_MASK (RX_INTS | TX_INTS)
177 struct r6040_descriptor {
178 u16 status, len; /* 0-3 */
179 __le32 buf; /* 4-7 */
180 __le32 ndesc; /* 8-B */
182 char *vbufp; /* 10-13 */
183 struct r6040_descriptor *vndescp; /* 14-17 */
184 struct sk_buff *skb_ptr; /* 18-1B */
185 u32 rev2; /* 1C-1F */
188 struct r6040_private {
189 spinlock_t lock; /* driver lock */
190 struct pci_dev *pdev;
191 struct r6040_descriptor *rx_insert_ptr;
192 struct r6040_descriptor *rx_remove_ptr;
193 struct r6040_descriptor *tx_insert_ptr;
194 struct r6040_descriptor *tx_remove_ptr;
195 struct r6040_descriptor *rx_ring;
196 struct r6040_descriptor *tx_ring;
197 dma_addr_t rx_ring_dma;
198 dma_addr_t tx_ring_dma;
201 struct net_device *dev;
202 struct mii_bus *mii_bus;
203 struct napi_struct napi;
209 static char version[] = DRV_NAME
210 ": RDC R6040 NAPI net driver,"
211 "version "DRV_VERSION " (" DRV_RELDATE ")";
213 /* Read a word data from PHY Chip */
214 static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
216 int limit = MAC_DEF_TIMEOUT;
219 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
220 /* Wait for the read bit to be cleared */
222 cmd = ioread16(ioaddr + MMDIO);
223 if (!(cmd & MDIO_READ))
231 return ioread16(ioaddr + MMRD);
234 /* Write a word data from PHY Chip */
235 static int r6040_phy_write(void __iomem *ioaddr,
236 int phy_addr, int reg, u16 val)
238 int limit = MAC_DEF_TIMEOUT;
241 iowrite16(val, ioaddr + MMWD);
242 /* Write the command to the MDIO bus */
243 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
244 /* Wait for the write bit to be cleared */
246 cmd = ioread16(ioaddr + MMDIO);
247 if (!(cmd & MDIO_WRITE))
252 return (limit < 0) ? -ETIMEDOUT : 0;
255 static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg)
257 struct net_device *dev = bus->priv;
258 struct r6040_private *lp = netdev_priv(dev);
259 void __iomem *ioaddr = lp->base;
261 return r6040_phy_read(ioaddr, phy_addr, reg);
264 static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr,
267 struct net_device *dev = bus->priv;
268 struct r6040_private *lp = netdev_priv(dev);
269 void __iomem *ioaddr = lp->base;
271 return r6040_phy_write(ioaddr, phy_addr, reg, value);
274 static void r6040_free_txbufs(struct net_device *dev)
276 struct r6040_private *lp = netdev_priv(dev);
279 for (i = 0; i < TX_DCNT; i++) {
280 if (lp->tx_insert_ptr->skb_ptr) {
281 pci_unmap_single(lp->pdev,
282 le32_to_cpu(lp->tx_insert_ptr->buf),
283 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
284 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
285 lp->tx_insert_ptr->skb_ptr = NULL;
287 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
291 static void r6040_free_rxbufs(struct net_device *dev)
293 struct r6040_private *lp = netdev_priv(dev);
296 for (i = 0; i < RX_DCNT; i++) {
297 if (lp->rx_insert_ptr->skb_ptr) {
298 pci_unmap_single(lp->pdev,
299 le32_to_cpu(lp->rx_insert_ptr->buf),
300 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
301 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
302 lp->rx_insert_ptr->skb_ptr = NULL;
304 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
308 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
309 dma_addr_t desc_dma, int size)
311 struct r6040_descriptor *desc = desc_ring;
312 dma_addr_t mapping = desc_dma;
315 mapping += sizeof(*desc);
316 desc->ndesc = cpu_to_le32(mapping);
317 desc->vndescp = desc + 1;
321 desc->ndesc = cpu_to_le32(desc_dma);
322 desc->vndescp = desc_ring;
325 static void r6040_init_txbufs(struct net_device *dev)
327 struct r6040_private *lp = netdev_priv(dev);
329 lp->tx_free_desc = TX_DCNT;
331 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
332 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
335 static int r6040_alloc_rxbufs(struct net_device *dev)
337 struct r6040_private *lp = netdev_priv(dev);
338 struct r6040_descriptor *desc;
342 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
343 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
345 /* Allocate skbs for the rx descriptors */
348 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
354 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
356 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
357 desc->status = DSC_OWNER_MAC;
358 desc = desc->vndescp;
359 } while (desc != lp->rx_ring);
364 /* Deallocate all previously allocated skbs */
365 r6040_free_rxbufs(dev);
369 static void r6040_reset_mac(struct r6040_private *lp)
371 void __iomem *ioaddr = lp->base;
372 int limit = MAC_DEF_TIMEOUT;
375 md_csc = ioread16(ioaddr + MD_CSC);
376 iowrite16(MAC_RST, ioaddr + MCR1);
378 cmd = ioread16(ioaddr + MCR1);
383 /* Reset internal state machine */
384 iowrite16(MAC_SM_RST, ioaddr + MAC_SM);
385 iowrite16(0, ioaddr + MAC_SM);
388 /* Restore MDIO clock frequency */
389 if (md_csc != MD_CSC_DEFAULT)
390 iowrite16(md_csc, ioaddr + MD_CSC);
393 static void r6040_init_mac_regs(struct net_device *dev)
395 struct r6040_private *lp = netdev_priv(dev);
396 void __iomem *ioaddr = lp->base;
398 /* Mask Off Interrupt */
399 iowrite16(MSK_INT, ioaddr + MIER);
404 /* MAC Bus Control Register */
405 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
407 /* Buffer Size Register */
408 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
410 /* Write TX ring start address */
411 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
412 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
414 /* Write RX ring start address */
415 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
416 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
418 /* Set interrupt waiting time and packet numbers */
419 iowrite16(0, ioaddr + MT_ICR);
420 iowrite16(0, ioaddr + MR_ICR);
422 /* Enable interrupts */
423 iowrite16(INT_MASK, ioaddr + MIER);
425 /* Enable TX and RX */
426 iowrite16(lp->mcr0 | MCR0_RCVEN, ioaddr);
428 /* Let TX poll the descriptors
429 * we may got called by r6040_tx_timeout which has left
430 * some unsent tx buffers */
431 iowrite16(TM2TX, ioaddr + MTPR);
434 static void r6040_tx_timeout(struct net_device *dev)
436 struct r6040_private *priv = netdev_priv(dev);
437 void __iomem *ioaddr = priv->base;
439 netdev_warn(dev, "transmit timed out, int enable %4.4x "
441 ioread16(ioaddr + MIER),
442 ioread16(ioaddr + MISR));
444 dev->stats.tx_errors++;
446 /* Reset MAC and re-init all registers */
447 r6040_init_mac_regs(dev);
450 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
452 struct r6040_private *priv = netdev_priv(dev);
453 void __iomem *ioaddr = priv->base;
456 spin_lock_irqsave(&priv->lock, flags);
457 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
458 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
459 spin_unlock_irqrestore(&priv->lock, flags);
464 /* Stop RDC MAC and Free the allocated resource */
465 static void r6040_down(struct net_device *dev)
467 struct r6040_private *lp = netdev_priv(dev);
468 void __iomem *ioaddr = lp->base;
472 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
477 /* Restore MAC Address to MIDx */
478 adrp = (u16 *) dev->dev_addr;
479 iowrite16(adrp[0], ioaddr + MID_0L);
480 iowrite16(adrp[1], ioaddr + MID_0M);
481 iowrite16(adrp[2], ioaddr + MID_0H);
484 static int r6040_close(struct net_device *dev)
486 struct r6040_private *lp = netdev_priv(dev);
487 struct pci_dev *pdev = lp->pdev;
489 phy_stop(dev->phydev);
490 napi_disable(&lp->napi);
491 netif_stop_queue(dev);
493 spin_lock_irq(&lp->lock);
497 r6040_free_rxbufs(dev);
500 r6040_free_txbufs(dev);
502 spin_unlock_irq(&lp->lock);
504 free_irq(dev->irq, dev);
506 /* Free Descriptor memory */
508 pci_free_consistent(pdev,
509 RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
514 pci_free_consistent(pdev,
515 TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
522 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
527 return phy_mii_ioctl(dev->phydev, rq, cmd);
530 static int r6040_rx(struct net_device *dev, int limit)
532 struct r6040_private *priv = netdev_priv(dev);
533 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
534 struct sk_buff *skb_ptr, *new_skb;
538 /* Limit not reached and the descriptor belongs to the CPU */
539 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
540 /* Read the descriptor status */
541 err = descptr->status;
542 /* Global error status set */
543 if (err & DSC_RX_ERR) {
545 if (err & DSC_RX_ERR_DRI)
546 dev->stats.rx_frame_errors++;
547 /* Buffer length exceeded */
548 if (err & DSC_RX_ERR_BUF)
549 dev->stats.rx_length_errors++;
550 /* Packet too long */
551 if (err & DSC_RX_ERR_LONG)
552 dev->stats.rx_length_errors++;
553 /* Packet < 64 bytes */
554 if (err & DSC_RX_ERR_RUNT)
555 dev->stats.rx_length_errors++;
557 if (err & DSC_RX_ERR_CRC) {
558 spin_lock(&priv->lock);
559 dev->stats.rx_crc_errors++;
560 spin_unlock(&priv->lock);
565 /* Packet successfully received */
566 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
568 dev->stats.rx_dropped++;
571 skb_ptr = descptr->skb_ptr;
572 skb_ptr->dev = priv->dev;
574 /* Do not count the CRC */
575 skb_put(skb_ptr, descptr->len - 4);
576 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
577 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
578 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
580 /* Send to upper layer */
581 netif_receive_skb(skb_ptr);
582 dev->stats.rx_packets++;
583 dev->stats.rx_bytes += descptr->len - 4;
585 /* put new skb into descriptor */
586 descptr->skb_ptr = new_skb;
587 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
588 descptr->skb_ptr->data,
589 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
592 /* put the descriptor back to the MAC */
593 descptr->status = DSC_OWNER_MAC;
594 descptr = descptr->vndescp;
597 priv->rx_remove_ptr = descptr;
602 static void r6040_tx(struct net_device *dev)
604 struct r6040_private *priv = netdev_priv(dev);
605 struct r6040_descriptor *descptr;
606 void __iomem *ioaddr = priv->base;
607 struct sk_buff *skb_ptr;
610 spin_lock(&priv->lock);
611 descptr = priv->tx_remove_ptr;
612 while (priv->tx_free_desc < TX_DCNT) {
613 /* Check for errors */
614 err = ioread16(ioaddr + MLSR);
616 if (err & TX_FIFO_UNDR)
617 dev->stats.tx_fifo_errors++;
618 if (err & (TX_EXCEEDC | TX_LATEC))
619 dev->stats.tx_carrier_errors++;
621 if (descptr->status & DSC_OWNER_MAC)
622 break; /* Not complete */
623 skb_ptr = descptr->skb_ptr;
625 /* Statistic Counter */
626 dev->stats.tx_packets++;
627 dev->stats.tx_bytes += skb_ptr->len;
629 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
630 skb_ptr->len, PCI_DMA_TODEVICE);
632 dev_kfree_skb(skb_ptr);
633 descptr->skb_ptr = NULL;
634 /* To next descriptor */
635 descptr = descptr->vndescp;
636 priv->tx_free_desc++;
638 priv->tx_remove_ptr = descptr;
640 if (priv->tx_free_desc)
641 netif_wake_queue(dev);
642 spin_unlock(&priv->lock);
645 static int r6040_poll(struct napi_struct *napi, int budget)
647 struct r6040_private *priv =
648 container_of(napi, struct r6040_private, napi);
649 struct net_device *dev = priv->dev;
650 void __iomem *ioaddr = priv->base;
655 work_done = r6040_rx(dev, budget);
657 if (work_done < budget) {
658 napi_complete_done(napi, work_done);
659 /* Enable RX/TX interrupt */
660 iowrite16(ioread16(ioaddr + MIER) | RX_INTS | TX_INTS,
666 /* The RDC interrupt handler. */
667 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
669 struct net_device *dev = dev_id;
670 struct r6040_private *lp = netdev_priv(dev);
671 void __iomem *ioaddr = lp->base;
675 misr = ioread16(ioaddr + MIER);
676 /* Mask off RDC MAC interrupt */
677 iowrite16(MSK_INT, ioaddr + MIER);
678 /* Read MISR status and clear */
679 status = ioread16(ioaddr + MISR);
681 if (status == 0x0000 || status == 0xffff) {
682 /* Restore RDC MAC interrupt */
683 iowrite16(misr, ioaddr + MIER);
687 /* RX interrupt request */
688 if (status & (RX_INTS | TX_INTS)) {
689 if (status & RX_NO_DESC) {
690 /* RX descriptor unavailable */
691 dev->stats.rx_dropped++;
692 dev->stats.rx_missed_errors++;
694 if (status & RX_FIFO_FULL)
695 dev->stats.rx_fifo_errors++;
697 if (likely(napi_schedule_prep(&lp->napi))) {
698 /* Mask off RX interrupt */
699 misr &= ~(RX_INTS | TX_INTS);
700 __napi_schedule_irqoff(&lp->napi);
704 /* Restore RDC MAC interrupt */
705 iowrite16(misr, ioaddr + MIER);
710 #ifdef CONFIG_NET_POLL_CONTROLLER
711 static void r6040_poll_controller(struct net_device *dev)
713 disable_irq(dev->irq);
714 r6040_interrupt(dev->irq, dev);
715 enable_irq(dev->irq);
720 static int r6040_up(struct net_device *dev)
722 struct r6040_private *lp = netdev_priv(dev);
723 void __iomem *ioaddr = lp->base;
726 /* Initialise and alloc RX/TX buffers */
727 r6040_init_txbufs(dev);
728 ret = r6040_alloc_rxbufs(dev);
732 /* improve performance (by RDC guys) */
733 r6040_phy_write(ioaddr, 30, 17,
734 (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
735 r6040_phy_write(ioaddr, 30, 17,
736 ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
737 r6040_phy_write(ioaddr, 0, 19, 0x0000);
738 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
740 /* Initialize all MAC registers */
741 r6040_init_mac_regs(dev);
743 phy_start(dev->phydev);
749 /* Read/set MAC address routines */
750 static void r6040_mac_address(struct net_device *dev)
752 struct r6040_private *lp = netdev_priv(dev);
753 void __iomem *ioaddr = lp->base;
759 /* Restore MAC Address */
760 adrp = (u16 *) dev->dev_addr;
761 iowrite16(adrp[0], ioaddr + MID_0L);
762 iowrite16(adrp[1], ioaddr + MID_0M);
763 iowrite16(adrp[2], ioaddr + MID_0H);
766 static int r6040_open(struct net_device *dev)
768 struct r6040_private *lp = netdev_priv(dev);
771 /* Request IRQ and Register interrupt handler */
772 ret = request_irq(dev->irq, r6040_interrupt,
773 IRQF_SHARED, dev->name, dev);
777 /* Set MAC address */
778 r6040_mac_address(dev);
780 /* Allocate Descriptor memory */
782 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
789 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
792 goto err_free_rx_ring;
797 goto err_free_tx_ring;
799 napi_enable(&lp->napi);
800 netif_start_queue(dev);
805 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
808 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
811 free_irq(dev->irq, dev);
816 static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
817 struct net_device *dev)
819 struct r6040_private *lp = netdev_priv(dev);
820 struct r6040_descriptor *descptr;
821 void __iomem *ioaddr = lp->base;
824 if (skb_put_padto(skb, ETH_ZLEN) < 0)
827 /* Critical Section */
828 spin_lock_irqsave(&lp->lock, flags);
830 /* TX resource check */
831 if (!lp->tx_free_desc) {
832 spin_unlock_irqrestore(&lp->lock, flags);
833 netif_stop_queue(dev);
834 netdev_err(dev, ": no tx descriptor\n");
835 return NETDEV_TX_BUSY;
838 /* Set TX descriptor & Transmit it */
840 descptr = lp->tx_insert_ptr;
841 descptr->len = skb->len;
842 descptr->skb_ptr = skb;
843 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
844 skb->data, skb->len, PCI_DMA_TODEVICE));
845 descptr->status = DSC_OWNER_MAC;
847 skb_tx_timestamp(skb);
849 /* Trigger the MAC to check the TX descriptor */
850 if (!skb->xmit_more || netif_queue_stopped(dev))
851 iowrite16(TM2TX, ioaddr + MTPR);
852 lp->tx_insert_ptr = descptr->vndescp;
854 /* If no tx resource, stop */
855 if (!lp->tx_free_desc)
856 netif_stop_queue(dev);
858 spin_unlock_irqrestore(&lp->lock, flags);
863 static void r6040_multicast_list(struct net_device *dev)
865 struct r6040_private *lp = netdev_priv(dev);
866 void __iomem *ioaddr = lp->base;
868 struct netdev_hw_addr *ha;
871 u16 hash_table[4] = { 0 };
873 spin_lock_irqsave(&lp->lock, flags);
875 /* Keep our MAC Address */
876 adrp = (u16 *)dev->dev_addr;
877 iowrite16(adrp[0], ioaddr + MID_0L);
878 iowrite16(adrp[1], ioaddr + MID_0M);
879 iowrite16(adrp[2], ioaddr + MID_0H);
881 /* Clear AMCP & PROM bits */
882 lp->mcr0 = ioread16(ioaddr + MCR0) & ~(MCR0_PROMISC | MCR0_HASH_EN);
884 /* Promiscuous mode */
885 if (dev->flags & IFF_PROMISC)
886 lp->mcr0 |= MCR0_PROMISC;
888 /* Enable multicast hash table function to
889 * receive all multicast packets. */
890 else if (dev->flags & IFF_ALLMULTI) {
891 lp->mcr0 |= MCR0_HASH_EN;
893 for (i = 0; i < MCAST_MAX ; i++) {
894 iowrite16(0, ioaddr + MID_1L + 8 * i);
895 iowrite16(0, ioaddr + MID_1M + 8 * i);
896 iowrite16(0, ioaddr + MID_1H + 8 * i);
899 for (i = 0; i < 4; i++)
900 hash_table[i] = 0xffff;
902 /* Use internal multicast address registers if the number of
903 * multicast addresses is not greater than MCAST_MAX. */
904 else if (netdev_mc_count(dev) <= MCAST_MAX) {
906 netdev_for_each_mc_addr(ha, dev) {
907 u16 *adrp = (u16 *) ha->addr;
908 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
909 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
910 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
913 while (i < MCAST_MAX) {
914 iowrite16(0, ioaddr + MID_1L + 8 * i);
915 iowrite16(0, ioaddr + MID_1M + 8 * i);
916 iowrite16(0, ioaddr + MID_1H + 8 * i);
920 /* Otherwise, Enable multicast hash table function. */
924 lp->mcr0 |= MCR0_HASH_EN;
926 for (i = 0; i < MCAST_MAX ; i++) {
927 iowrite16(0, ioaddr + MID_1L + 8 * i);
928 iowrite16(0, ioaddr + MID_1M + 8 * i);
929 iowrite16(0, ioaddr + MID_1H + 8 * i);
932 /* Build multicast hash table */
933 netdev_for_each_mc_addr(ha, dev) {
934 u8 *addrs = ha->addr;
936 crc = ether_crc(ETH_ALEN, addrs);
938 hash_table[crc >> 4] |= 1 << (crc & 0xf);
942 iowrite16(lp->mcr0, ioaddr + MCR0);
944 /* Fill the MAC hash tables with their values */
945 if (lp->mcr0 & MCR0_HASH_EN) {
946 iowrite16(hash_table[0], ioaddr + MAR0);
947 iowrite16(hash_table[1], ioaddr + MAR1);
948 iowrite16(hash_table[2], ioaddr + MAR2);
949 iowrite16(hash_table[3], ioaddr + MAR3);
952 spin_unlock_irqrestore(&lp->lock, flags);
955 static void netdev_get_drvinfo(struct net_device *dev,
956 struct ethtool_drvinfo *info)
958 struct r6040_private *rp = netdev_priv(dev);
960 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
961 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
962 strlcpy(info->bus_info, pci_name(rp->pdev), sizeof(info->bus_info));
965 static const struct ethtool_ops netdev_ethtool_ops = {
966 .get_drvinfo = netdev_get_drvinfo,
967 .get_link = ethtool_op_get_link,
968 .get_ts_info = ethtool_op_get_ts_info,
969 .get_link_ksettings = phy_ethtool_get_link_ksettings,
970 .set_link_ksettings = phy_ethtool_set_link_ksettings,
973 static const struct net_device_ops r6040_netdev_ops = {
974 .ndo_open = r6040_open,
975 .ndo_stop = r6040_close,
976 .ndo_start_xmit = r6040_start_xmit,
977 .ndo_get_stats = r6040_get_stats,
978 .ndo_set_rx_mode = r6040_multicast_list,
979 .ndo_validate_addr = eth_validate_addr,
980 .ndo_set_mac_address = eth_mac_addr,
981 .ndo_do_ioctl = r6040_ioctl,
982 .ndo_tx_timeout = r6040_tx_timeout,
983 #ifdef CONFIG_NET_POLL_CONTROLLER
984 .ndo_poll_controller = r6040_poll_controller,
988 static void r6040_adjust_link(struct net_device *dev)
990 struct r6040_private *lp = netdev_priv(dev);
991 struct phy_device *phydev = dev->phydev;
992 int status_changed = 0;
993 void __iomem *ioaddr = lp->base;
997 if (lp->old_link != phydev->link) {
999 lp->old_link = phydev->link;
1002 /* reflect duplex change */
1003 if (phydev->link && (lp->old_duplex != phydev->duplex)) {
1004 lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? MCR0_FD : 0);
1005 iowrite16(lp->mcr0, ioaddr);
1008 lp->old_duplex = phydev->duplex;
1012 phy_print_status(phydev);
1015 static int r6040_mii_probe(struct net_device *dev)
1017 struct r6040_private *lp = netdev_priv(dev);
1018 struct phy_device *phydev = NULL;
1020 phydev = phy_find_first(lp->mii_bus);
1022 dev_err(&lp->pdev->dev, "no PHY found\n");
1026 phydev = phy_connect(dev, phydev_name(phydev), &r6040_adjust_link,
1027 PHY_INTERFACE_MODE_MII);
1029 if (IS_ERR(phydev)) {
1030 dev_err(&lp->pdev->dev, "could not attach to PHY\n");
1031 return PTR_ERR(phydev);
1034 /* mask with MAC supported features */
1035 phydev->supported &= (SUPPORTED_10baseT_Half
1036 | SUPPORTED_10baseT_Full
1037 | SUPPORTED_100baseT_Half
1038 | SUPPORTED_100baseT_Full
1043 phydev->advertising = phydev->supported;
1045 lp->old_duplex = -1;
1047 phy_attached_info(phydev);
1052 static int r6040_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1054 struct net_device *dev;
1055 struct r6040_private *lp;
1056 void __iomem *ioaddr;
1057 int err, io_size = R6040_IO_SIZE;
1058 static int card_idx = -1;
1062 pr_info("%s\n", version);
1064 err = pci_enable_device(pdev);
1068 /* this should always be supported */
1069 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1071 dev_err(&pdev->dev, "32-bit PCI DMA addresses not supported by the card\n");
1072 goto err_out_disable_dev;
1074 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1076 dev_err(&pdev->dev, "32-bit PCI DMA addresses not supported by the card\n");
1077 goto err_out_disable_dev;
1081 if (pci_resource_len(pdev, bar) < io_size) {
1082 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
1084 goto err_out_disable_dev;
1087 pci_set_master(pdev);
1089 dev = alloc_etherdev(sizeof(struct r6040_private));
1092 goto err_out_disable_dev;
1094 SET_NETDEV_DEV(dev, &pdev->dev);
1095 lp = netdev_priv(dev);
1097 err = pci_request_regions(pdev, DRV_NAME);
1100 dev_err(&pdev->dev, "Failed to request PCI regions\n");
1101 goto err_out_free_dev;
1104 ioaddr = pci_iomap(pdev, bar, io_size);
1106 dev_err(&pdev->dev, "ioremap failed for device\n");
1108 goto err_out_free_res;
1111 /* If PHY status change register is still set to zero it means the
1112 * bootloader didn't initialize it, so we set it to:
1113 * - enable phy status change
1114 * - enable all phy addresses
1115 * - set to lowest timer divider */
1116 if (ioread16(ioaddr + PHY_CC) == 0)
1117 iowrite16(SCEN | PHY_MAX_ADDR << PHYAD_SHIFT |
1118 7 << TMRDIV_SHIFT, ioaddr + PHY_CC);
1120 /* Init system & device */
1122 dev->irq = pdev->irq;
1124 spin_lock_init(&lp->lock);
1125 pci_set_drvdata(pdev, dev);
1127 /* Set MAC address */
1130 adrp = (u16 *)dev->dev_addr;
1131 adrp[0] = ioread16(ioaddr + MID_0L);
1132 adrp[1] = ioread16(ioaddr + MID_0M);
1133 adrp[2] = ioread16(ioaddr + MID_0H);
1135 /* Some bootloader/BIOSes do not initialize
1136 * MAC address, warn about that */
1137 if (!(adrp[0] || adrp[1] || adrp[2])) {
1138 netdev_warn(dev, "MAC address not initialized, "
1139 "generating random\n");
1140 eth_hw_addr_random(dev);
1143 /* Link new device into r6040_root_dev */
1147 /* Init RDC private data */
1148 lp->mcr0 = MCR0_XMTEN | MCR0_RCVEN;
1150 /* The RDC-specific entries in the device structure. */
1151 dev->netdev_ops = &r6040_netdev_ops;
1152 dev->ethtool_ops = &netdev_ethtool_ops;
1153 dev->watchdog_timeo = TX_TIMEOUT;
1155 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1157 lp->mii_bus = mdiobus_alloc();
1159 dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
1164 lp->mii_bus->priv = dev;
1165 lp->mii_bus->read = r6040_mdiobus_read;
1166 lp->mii_bus->write = r6040_mdiobus_write;
1167 lp->mii_bus->name = "r6040_eth_mii";
1168 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1169 dev_name(&pdev->dev), card_idx);
1171 err = mdiobus_register(lp->mii_bus);
1173 dev_err(&pdev->dev, "failed to register MII bus\n");
1177 err = r6040_mii_probe(dev);
1179 dev_err(&pdev->dev, "failed to probe MII bus\n");
1180 goto err_out_mdio_unregister;
1183 /* Register net device. After this dev->name assign */
1184 err = register_netdev(dev);
1186 dev_err(&pdev->dev, "Failed to register net device\n");
1187 goto err_out_mdio_unregister;
1191 err_out_mdio_unregister:
1192 mdiobus_unregister(lp->mii_bus);
1194 mdiobus_free(lp->mii_bus);
1196 netif_napi_del(&lp->napi);
1197 pci_iounmap(pdev, ioaddr);
1199 pci_release_regions(pdev);
1202 err_out_disable_dev:
1203 pci_disable_device(pdev);
1208 static void r6040_remove_one(struct pci_dev *pdev)
1210 struct net_device *dev = pci_get_drvdata(pdev);
1211 struct r6040_private *lp = netdev_priv(dev);
1213 unregister_netdev(dev);
1214 mdiobus_unregister(lp->mii_bus);
1215 mdiobus_free(lp->mii_bus);
1216 netif_napi_del(&lp->napi);
1217 pci_iounmap(pdev, lp->base);
1218 pci_release_regions(pdev);
1220 pci_disable_device(pdev);
1224 static const struct pci_device_id r6040_pci_tbl[] = {
1225 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1228 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1230 static struct pci_driver r6040_driver = {
1232 .id_table = r6040_pci_tbl,
1233 .probe = r6040_init_one,
1234 .remove = r6040_remove_one,
1237 module_pci_driver(r6040_driver);