2 * RDC R6040 Fast Ethernet MAC support
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Copyright (C) 2007-2012 Florian Fainelli <florian@openwrt.org>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/string.h>
29 #include <linux/timer.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/interrupt.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/delay.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/crc32.h>
41 #include <linux/spinlock.h>
42 #include <linux/bitops.h>
44 #include <linux/irq.h>
45 #include <linux/uaccess.h>
46 #include <linux/phy.h>
48 #include <asm/processor.h>
50 #define DRV_NAME "r6040"
51 #define DRV_VERSION "0.28"
52 #define DRV_RELDATE "07Oct2011"
54 /* Time in jiffies before concluding the transmitter is hung. */
55 #define TX_TIMEOUT (6000 * HZ / 1000)
57 /* RDC MAC I/O Size */
58 #define R6040_IO_SIZE 256
64 #define MCR0 0x00 /* Control register 0 */
65 #define MCR0_RCVEN 0x0002 /* Receive enable */
66 #define MCR0_PROMISC 0x0020 /* Promiscuous mode */
67 #define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */
68 #define MCR0_XMTEN 0x1000 /* Transmission enable */
69 #define MCR0_FD 0x8000 /* Full/Half duplex */
70 #define MCR1 0x04 /* Control register 1 */
71 #define MAC_RST 0x0001 /* Reset the MAC */
72 #define MBCR 0x08 /* Bus control */
73 #define MT_ICR 0x0C /* TX interrupt control */
74 #define MR_ICR 0x10 /* RX interrupt control */
75 #define MTPR 0x14 /* TX poll command register */
76 #define TM2TX 0x0001 /* Trigger MAC to transmit */
77 #define MR_BSR 0x18 /* RX buffer size */
78 #define MR_DCR 0x1A /* RX descriptor control */
79 #define MLSR 0x1C /* Last status */
80 #define TX_FIFO_UNDR 0x0200 /* TX FIFO under-run */
81 #define TX_EXCEEDC 0x2000 /* Transmit exceed collision */
82 #define TX_LATEC 0x4000 /* Transmit late collision */
83 #define MMDIO 0x20 /* MDIO control register */
84 #define MDIO_WRITE 0x4000 /* MDIO write */
85 #define MDIO_READ 0x2000 /* MDIO read */
86 #define MMRD 0x24 /* MDIO read data register */
87 #define MMWD 0x28 /* MDIO write data register */
88 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
89 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
90 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
91 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
92 #define MISR 0x3C /* Status register */
93 #define MIER 0x40 /* INT enable register */
94 #define MSK_INT 0x0000 /* Mask off interrupts */
95 #define RX_FINISH 0x0001 /* RX finished */
96 #define RX_NO_DESC 0x0002 /* No RX descriptor available */
97 #define RX_FIFO_FULL 0x0004 /* RX FIFO full */
98 #define RX_EARLY 0x0008 /* RX early */
99 #define TX_FINISH 0x0010 /* TX finished */
100 #define TX_EARLY 0x0080 /* TX early */
101 #define EVENT_OVRFL 0x0100 /* Event counter overflow */
102 #define LINK_CHANGED 0x0200 /* PHY link changed */
103 #define ME_CISR 0x44 /* Event counter INT status */
104 #define ME_CIER 0x48 /* Event counter INT enable */
105 #define MR_CNT 0x50 /* Successfully received packet counter */
106 #define ME_CNT0 0x52 /* Event counter 0 */
107 #define ME_CNT1 0x54 /* Event counter 1 */
108 #define ME_CNT2 0x56 /* Event counter 2 */
109 #define ME_CNT3 0x58 /* Event counter 3 */
110 #define MT_CNT 0x5A /* Successfully transmit packet counter */
111 #define ME_CNT4 0x5C /* Event counter 4 */
112 #define MP_CNT 0x5E /* Pause frame counter register */
113 #define MAR0 0x60 /* Hash table 0 */
114 #define MAR1 0x62 /* Hash table 1 */
115 #define MAR2 0x64 /* Hash table 2 */
116 #define MAR3 0x66 /* Hash table 3 */
117 #define MID_0L 0x68 /* Multicast address MID0 Low */
118 #define MID_0M 0x6A /* Multicast address MID0 Medium */
119 #define MID_0H 0x6C /* Multicast address MID0 High */
120 #define MID_1L 0x70 /* MID1 Low */
121 #define MID_1M 0x72 /* MID1 Medium */
122 #define MID_1H 0x74 /* MID1 High */
123 #define MID_2L 0x78 /* MID2 Low */
124 #define MID_2M 0x7A /* MID2 Medium */
125 #define MID_2H 0x7C /* MID2 High */
126 #define MID_3L 0x80 /* MID3 Low */
127 #define MID_3M 0x82 /* MID3 Medium */
128 #define MID_3H 0x84 /* MID3 High */
129 #define PHY_CC 0x88 /* PHY status change configuration register */
130 #define SCEN 0x8000 /* PHY status change enable */
131 #define PHYAD_SHIFT 8 /* PHY address shift */
132 #define TMRDIV_SHIFT 0 /* Timer divider shift */
133 #define PHY_ST 0x8A /* PHY status register */
134 #define MAC_SM 0xAC /* MAC status machine */
135 #define MAC_SM_RST 0x0002 /* MAC status machine reset */
136 #define MD_CSC 0xb6 /* MDC speed control register */
137 #define MD_CSC_DEFAULT 0x0030
138 #define MAC_ID 0xBE /* Identifier register */
140 #define TX_DCNT 0x80 /* TX descriptor count */
141 #define RX_DCNT 0x80 /* RX descriptor count */
142 #define MAX_BUF_SIZE 0x600
143 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
144 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
145 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
146 #define MCAST_MAX 3 /* Max number multicast addresses to filter */
148 #define MAC_DEF_TIMEOUT 2048 /* Default MAC read/write operation timeout */
150 /* Descriptor status */
151 #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
152 #define DSC_RX_OK 0x4000 /* RX was successful */
153 #define DSC_RX_ERR 0x0800 /* RX PHY error */
154 #define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
155 #define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
156 #define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
157 #define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
158 #define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
159 #define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
160 #define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
161 #define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
162 #define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
163 #define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
165 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
166 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
167 "Florian Fainelli <florian@openwrt.org>");
168 MODULE_LICENSE("GPL");
169 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
170 MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
172 /* RX and TX interrupts that we handle */
173 #define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
174 #define TX_INTS (TX_FINISH)
175 #define INT_MASK (RX_INTS | TX_INTS)
177 struct r6040_descriptor {
178 u16 status, len; /* 0-3 */
179 __le32 buf; /* 4-7 */
180 __le32 ndesc; /* 8-B */
182 char *vbufp; /* 10-13 */
183 struct r6040_descriptor *vndescp; /* 14-17 */
184 struct sk_buff *skb_ptr; /* 18-1B */
185 u32 rev2; /* 1C-1F */
188 struct r6040_private {
189 spinlock_t lock; /* driver lock */
190 struct pci_dev *pdev;
191 struct r6040_descriptor *rx_insert_ptr;
192 struct r6040_descriptor *rx_remove_ptr;
193 struct r6040_descriptor *tx_insert_ptr;
194 struct r6040_descriptor *tx_remove_ptr;
195 struct r6040_descriptor *rx_ring;
196 struct r6040_descriptor *tx_ring;
197 dma_addr_t rx_ring_dma;
198 dma_addr_t tx_ring_dma;
201 struct net_device *dev;
202 struct mii_bus *mii_bus;
203 struct napi_struct napi;
205 struct phy_device *phydev;
210 static char version[] = DRV_NAME
211 ": RDC R6040 NAPI net driver,"
212 "version "DRV_VERSION " (" DRV_RELDATE ")";
214 /* Read a word data from PHY Chip */
215 static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
217 int limit = MAC_DEF_TIMEOUT;
220 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
221 /* Wait for the read bit to be cleared */
223 cmd = ioread16(ioaddr + MMDIO);
224 if (!(cmd & MDIO_READ))
232 return ioread16(ioaddr + MMRD);
235 /* Write a word data from PHY Chip */
236 static int r6040_phy_write(void __iomem *ioaddr,
237 int phy_addr, int reg, u16 val)
239 int limit = MAC_DEF_TIMEOUT;
242 iowrite16(val, ioaddr + MMWD);
243 /* Write the command to the MDIO bus */
244 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
245 /* Wait for the write bit to be cleared */
247 cmd = ioread16(ioaddr + MMDIO);
248 if (!(cmd & MDIO_WRITE))
253 return (limit < 0) ? -ETIMEDOUT : 0;
256 static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg)
258 struct net_device *dev = bus->priv;
259 struct r6040_private *lp = netdev_priv(dev);
260 void __iomem *ioaddr = lp->base;
262 return r6040_phy_read(ioaddr, phy_addr, reg);
265 static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr,
268 struct net_device *dev = bus->priv;
269 struct r6040_private *lp = netdev_priv(dev);
270 void __iomem *ioaddr = lp->base;
272 return r6040_phy_write(ioaddr, phy_addr, reg, value);
275 static void r6040_free_txbufs(struct net_device *dev)
277 struct r6040_private *lp = netdev_priv(dev);
280 for (i = 0; i < TX_DCNT; i++) {
281 if (lp->tx_insert_ptr->skb_ptr) {
282 pci_unmap_single(lp->pdev,
283 le32_to_cpu(lp->tx_insert_ptr->buf),
284 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
285 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
286 lp->tx_insert_ptr->skb_ptr = NULL;
288 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
292 static void r6040_free_rxbufs(struct net_device *dev)
294 struct r6040_private *lp = netdev_priv(dev);
297 for (i = 0; i < RX_DCNT; i++) {
298 if (lp->rx_insert_ptr->skb_ptr) {
299 pci_unmap_single(lp->pdev,
300 le32_to_cpu(lp->rx_insert_ptr->buf),
301 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
302 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
303 lp->rx_insert_ptr->skb_ptr = NULL;
305 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
309 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
310 dma_addr_t desc_dma, int size)
312 struct r6040_descriptor *desc = desc_ring;
313 dma_addr_t mapping = desc_dma;
316 mapping += sizeof(*desc);
317 desc->ndesc = cpu_to_le32(mapping);
318 desc->vndescp = desc + 1;
322 desc->ndesc = cpu_to_le32(desc_dma);
323 desc->vndescp = desc_ring;
326 static void r6040_init_txbufs(struct net_device *dev)
328 struct r6040_private *lp = netdev_priv(dev);
330 lp->tx_free_desc = TX_DCNT;
332 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
333 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
336 static int r6040_alloc_rxbufs(struct net_device *dev)
338 struct r6040_private *lp = netdev_priv(dev);
339 struct r6040_descriptor *desc;
343 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
344 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
346 /* Allocate skbs for the rx descriptors */
349 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
355 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
357 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
358 desc->status = DSC_OWNER_MAC;
359 desc = desc->vndescp;
360 } while (desc != lp->rx_ring);
365 /* Deallocate all previously allocated skbs */
366 r6040_free_rxbufs(dev);
370 static void r6040_reset_mac(struct r6040_private *lp)
372 void __iomem *ioaddr = lp->base;
373 int limit = MAC_DEF_TIMEOUT;
376 md_csc = ioread16(ioaddr + MD_CSC);
377 iowrite16(MAC_RST, ioaddr + MCR1);
379 cmd = ioread16(ioaddr + MCR1);
384 /* Reset internal state machine */
385 iowrite16(MAC_SM_RST, ioaddr + MAC_SM);
386 iowrite16(0, ioaddr + MAC_SM);
389 /* Restore MDIO clock frequency */
390 if (md_csc != MD_CSC_DEFAULT)
391 iowrite16(md_csc, ioaddr + MD_CSC);
394 static void r6040_init_mac_regs(struct net_device *dev)
396 struct r6040_private *lp = netdev_priv(dev);
397 void __iomem *ioaddr = lp->base;
399 /* Mask Off Interrupt */
400 iowrite16(MSK_INT, ioaddr + MIER);
405 /* MAC Bus Control Register */
406 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
408 /* Buffer Size Register */
409 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
411 /* Write TX ring start address */
412 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
413 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
415 /* Write RX ring start address */
416 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
417 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
419 /* Set interrupt waiting time and packet numbers */
420 iowrite16(0, ioaddr + MT_ICR);
421 iowrite16(0, ioaddr + MR_ICR);
423 /* Enable interrupts */
424 iowrite16(INT_MASK, ioaddr + MIER);
426 /* Enable TX and RX */
427 iowrite16(lp->mcr0 | MCR0_RCVEN, ioaddr);
429 /* Let TX poll the descriptors
430 * we may got called by r6040_tx_timeout which has left
431 * some unsent tx buffers */
432 iowrite16(TM2TX, ioaddr + MTPR);
435 static void r6040_tx_timeout(struct net_device *dev)
437 struct r6040_private *priv = netdev_priv(dev);
438 void __iomem *ioaddr = priv->base;
440 netdev_warn(dev, "transmit timed out, int enable %4.4x "
442 ioread16(ioaddr + MIER),
443 ioread16(ioaddr + MISR));
445 dev->stats.tx_errors++;
447 /* Reset MAC and re-init all registers */
448 r6040_init_mac_regs(dev);
451 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
453 struct r6040_private *priv = netdev_priv(dev);
454 void __iomem *ioaddr = priv->base;
457 spin_lock_irqsave(&priv->lock, flags);
458 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
459 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
460 spin_unlock_irqrestore(&priv->lock, flags);
465 /* Stop RDC MAC and Free the allocated resource */
466 static void r6040_down(struct net_device *dev)
468 struct r6040_private *lp = netdev_priv(dev);
469 void __iomem *ioaddr = lp->base;
473 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
478 /* Restore MAC Address to MIDx */
479 adrp = (u16 *) dev->dev_addr;
480 iowrite16(adrp[0], ioaddr + MID_0L);
481 iowrite16(adrp[1], ioaddr + MID_0M);
482 iowrite16(adrp[2], ioaddr + MID_0H);
484 phy_stop(lp->phydev);
487 static int r6040_close(struct net_device *dev)
489 struct r6040_private *lp = netdev_priv(dev);
490 struct pci_dev *pdev = lp->pdev;
492 spin_lock_irq(&lp->lock);
493 napi_disable(&lp->napi);
494 netif_stop_queue(dev);
497 free_irq(dev->irq, dev);
500 r6040_free_rxbufs(dev);
503 r6040_free_txbufs(dev);
505 spin_unlock_irq(&lp->lock);
507 /* Free Descriptor memory */
509 pci_free_consistent(pdev,
510 RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
515 pci_free_consistent(pdev,
516 TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
523 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
525 struct r6040_private *lp = netdev_priv(dev);
530 return phy_mii_ioctl(lp->phydev, rq, cmd);
533 static int r6040_rx(struct net_device *dev, int limit)
535 struct r6040_private *priv = netdev_priv(dev);
536 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
537 struct sk_buff *skb_ptr, *new_skb;
541 /* Limit not reached and the descriptor belongs to the CPU */
542 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
543 /* Read the descriptor status */
544 err = descptr->status;
545 /* Global error status set */
546 if (err & DSC_RX_ERR) {
548 if (err & DSC_RX_ERR_DRI)
549 dev->stats.rx_frame_errors++;
550 /* Buffer length exceeded */
551 if (err & DSC_RX_ERR_BUF)
552 dev->stats.rx_length_errors++;
553 /* Packet too long */
554 if (err & DSC_RX_ERR_LONG)
555 dev->stats.rx_length_errors++;
556 /* Packet < 64 bytes */
557 if (err & DSC_RX_ERR_RUNT)
558 dev->stats.rx_length_errors++;
560 if (err & DSC_RX_ERR_CRC) {
561 spin_lock(&priv->lock);
562 dev->stats.rx_crc_errors++;
563 spin_unlock(&priv->lock);
568 /* Packet successfully received */
569 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
571 dev->stats.rx_dropped++;
574 skb_ptr = descptr->skb_ptr;
575 skb_ptr->dev = priv->dev;
577 /* Do not count the CRC */
578 skb_put(skb_ptr, descptr->len - 4);
579 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
580 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
581 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
583 /* Send to upper layer */
584 netif_receive_skb(skb_ptr);
585 dev->stats.rx_packets++;
586 dev->stats.rx_bytes += descptr->len - 4;
588 /* put new skb into descriptor */
589 descptr->skb_ptr = new_skb;
590 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
591 descptr->skb_ptr->data,
592 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
595 /* put the descriptor back to the MAC */
596 descptr->status = DSC_OWNER_MAC;
597 descptr = descptr->vndescp;
600 priv->rx_remove_ptr = descptr;
605 static void r6040_tx(struct net_device *dev)
607 struct r6040_private *priv = netdev_priv(dev);
608 struct r6040_descriptor *descptr;
609 void __iomem *ioaddr = priv->base;
610 struct sk_buff *skb_ptr;
613 spin_lock(&priv->lock);
614 descptr = priv->tx_remove_ptr;
615 while (priv->tx_free_desc < TX_DCNT) {
616 /* Check for errors */
617 err = ioread16(ioaddr + MLSR);
619 if (err & TX_FIFO_UNDR)
620 dev->stats.tx_fifo_errors++;
621 if (err & (TX_EXCEEDC | TX_LATEC))
622 dev->stats.tx_carrier_errors++;
624 if (descptr->status & DSC_OWNER_MAC)
625 break; /* Not complete */
626 skb_ptr = descptr->skb_ptr;
627 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
628 skb_ptr->len, PCI_DMA_TODEVICE);
630 dev_kfree_skb_irq(skb_ptr);
631 descptr->skb_ptr = NULL;
632 /* To next descriptor */
633 descptr = descptr->vndescp;
634 priv->tx_free_desc++;
636 priv->tx_remove_ptr = descptr;
638 if (priv->tx_free_desc)
639 netif_wake_queue(dev);
640 spin_unlock(&priv->lock);
643 static int r6040_poll(struct napi_struct *napi, int budget)
645 struct r6040_private *priv =
646 container_of(napi, struct r6040_private, napi);
647 struct net_device *dev = priv->dev;
648 void __iomem *ioaddr = priv->base;
651 work_done = r6040_rx(dev, budget);
653 if (work_done < budget) {
655 /* Enable RX interrupt */
656 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
661 /* The RDC interrupt handler. */
662 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
664 struct net_device *dev = dev_id;
665 struct r6040_private *lp = netdev_priv(dev);
666 void __iomem *ioaddr = lp->base;
670 misr = ioread16(ioaddr + MIER);
671 /* Mask off RDC MAC interrupt */
672 iowrite16(MSK_INT, ioaddr + MIER);
673 /* Read MISR status and clear */
674 status = ioread16(ioaddr + MISR);
676 if (status == 0x0000 || status == 0xffff) {
677 /* Restore RDC MAC interrupt */
678 iowrite16(misr, ioaddr + MIER);
682 /* RX interrupt request */
683 if (status & RX_INTS) {
684 if (status & RX_NO_DESC) {
685 /* RX descriptor unavailable */
686 dev->stats.rx_dropped++;
687 dev->stats.rx_missed_errors++;
689 if (status & RX_FIFO_FULL)
690 dev->stats.rx_fifo_errors++;
692 if (likely(napi_schedule_prep(&lp->napi))) {
693 /* Mask off RX interrupt */
695 __napi_schedule(&lp->napi);
699 /* TX interrupt request */
700 if (status & TX_INTS)
703 /* Restore RDC MAC interrupt */
704 iowrite16(misr, ioaddr + MIER);
709 #ifdef CONFIG_NET_POLL_CONTROLLER
710 static void r6040_poll_controller(struct net_device *dev)
712 disable_irq(dev->irq);
713 r6040_interrupt(dev->irq, dev);
714 enable_irq(dev->irq);
719 static int r6040_up(struct net_device *dev)
721 struct r6040_private *lp = netdev_priv(dev);
722 void __iomem *ioaddr = lp->base;
725 /* Initialise and alloc RX/TX buffers */
726 r6040_init_txbufs(dev);
727 ret = r6040_alloc_rxbufs(dev);
731 /* improve performance (by RDC guys) */
732 r6040_phy_write(ioaddr, 30, 17,
733 (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
734 r6040_phy_write(ioaddr, 30, 17,
735 ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
736 r6040_phy_write(ioaddr, 0, 19, 0x0000);
737 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
739 /* Initialize all MAC registers */
740 r6040_init_mac_regs(dev);
742 phy_start(lp->phydev);
748 /* Read/set MAC address routines */
749 static void r6040_mac_address(struct net_device *dev)
751 struct r6040_private *lp = netdev_priv(dev);
752 void __iomem *ioaddr = lp->base;
758 /* Restore MAC Address */
759 adrp = (u16 *) dev->dev_addr;
760 iowrite16(adrp[0], ioaddr + MID_0L);
761 iowrite16(adrp[1], ioaddr + MID_0M);
762 iowrite16(adrp[2], ioaddr + MID_0H);
765 static int r6040_open(struct net_device *dev)
767 struct r6040_private *lp = netdev_priv(dev);
770 /* Request IRQ and Register interrupt handler */
771 ret = request_irq(dev->irq, r6040_interrupt,
772 IRQF_SHARED, dev->name, dev);
776 /* Set MAC address */
777 r6040_mac_address(dev);
779 /* Allocate Descriptor memory */
781 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
788 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
791 goto err_free_rx_ring;
796 goto err_free_tx_ring;
798 napi_enable(&lp->napi);
799 netif_start_queue(dev);
804 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
807 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
810 free_irq(dev->irq, dev);
815 static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
816 struct net_device *dev)
818 struct r6040_private *lp = netdev_priv(dev);
819 struct r6040_descriptor *descptr;
820 void __iomem *ioaddr = lp->base;
823 /* Critical Section */
824 spin_lock_irqsave(&lp->lock, flags);
826 /* TX resource check */
827 if (!lp->tx_free_desc) {
828 spin_unlock_irqrestore(&lp->lock, flags);
829 netif_stop_queue(dev);
830 netdev_err(dev, ": no tx descriptor\n");
831 return NETDEV_TX_BUSY;
834 /* Statistic Counter */
835 dev->stats.tx_packets++;
836 dev->stats.tx_bytes += skb->len;
837 /* Set TX descriptor & Transmit it */
839 descptr = lp->tx_insert_ptr;
840 if (skb->len < ETH_ZLEN)
841 descptr->len = ETH_ZLEN;
843 descptr->len = skb->len;
845 descptr->skb_ptr = skb;
846 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
847 skb->data, skb->len, PCI_DMA_TODEVICE));
848 descptr->status = DSC_OWNER_MAC;
850 skb_tx_timestamp(skb);
852 /* Trigger the MAC to check the TX descriptor */
853 iowrite16(TM2TX, ioaddr + MTPR);
854 lp->tx_insert_ptr = descptr->vndescp;
856 /* If no tx resource, stop */
857 if (!lp->tx_free_desc)
858 netif_stop_queue(dev);
860 spin_unlock_irqrestore(&lp->lock, flags);
865 static void r6040_multicast_list(struct net_device *dev)
867 struct r6040_private *lp = netdev_priv(dev);
868 void __iomem *ioaddr = lp->base;
870 struct netdev_hw_addr *ha;
873 u16 hash_table[4] = { 0 };
875 spin_lock_irqsave(&lp->lock, flags);
877 /* Keep our MAC Address */
878 adrp = (u16 *)dev->dev_addr;
879 iowrite16(adrp[0], ioaddr + MID_0L);
880 iowrite16(adrp[1], ioaddr + MID_0M);
881 iowrite16(adrp[2], ioaddr + MID_0H);
883 /* Clear AMCP & PROM bits */
884 lp->mcr0 = ioread16(ioaddr + MCR0) & ~(MCR0_PROMISC | MCR0_HASH_EN);
886 /* Promiscuous mode */
887 if (dev->flags & IFF_PROMISC)
888 lp->mcr0 |= MCR0_PROMISC;
890 /* Enable multicast hash table function to
891 * receive all multicast packets. */
892 else if (dev->flags & IFF_ALLMULTI) {
893 lp->mcr0 |= MCR0_HASH_EN;
895 for (i = 0; i < MCAST_MAX ; i++) {
896 iowrite16(0, ioaddr + MID_1L + 8 * i);
897 iowrite16(0, ioaddr + MID_1M + 8 * i);
898 iowrite16(0, ioaddr + MID_1H + 8 * i);
901 for (i = 0; i < 4; i++)
902 hash_table[i] = 0xffff;
904 /* Use internal multicast address registers if the number of
905 * multicast addresses is not greater than MCAST_MAX. */
906 else if (netdev_mc_count(dev) <= MCAST_MAX) {
908 netdev_for_each_mc_addr(ha, dev) {
909 u16 *adrp = (u16 *) ha->addr;
910 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
911 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
912 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
915 while (i < MCAST_MAX) {
916 iowrite16(0, ioaddr + MID_1L + 8 * i);
917 iowrite16(0, ioaddr + MID_1M + 8 * i);
918 iowrite16(0, ioaddr + MID_1H + 8 * i);
922 /* Otherwise, Enable multicast hash table function. */
926 lp->mcr0 |= MCR0_HASH_EN;
928 for (i = 0; i < MCAST_MAX ; i++) {
929 iowrite16(0, ioaddr + MID_1L + 8 * i);
930 iowrite16(0, ioaddr + MID_1M + 8 * i);
931 iowrite16(0, ioaddr + MID_1H + 8 * i);
934 /* Build multicast hash table */
935 netdev_for_each_mc_addr(ha, dev) {
936 u8 *addrs = ha->addr;
938 crc = ether_crc(ETH_ALEN, addrs);
940 hash_table[crc >> 4] |= 1 << (crc & 0xf);
944 iowrite16(lp->mcr0, ioaddr + MCR0);
946 /* Fill the MAC hash tables with their values */
947 if (lp->mcr0 & MCR0_HASH_EN) {
948 iowrite16(hash_table[0], ioaddr + MAR0);
949 iowrite16(hash_table[1], ioaddr + MAR1);
950 iowrite16(hash_table[2], ioaddr + MAR2);
951 iowrite16(hash_table[3], ioaddr + MAR3);
954 spin_unlock_irqrestore(&lp->lock, flags);
957 static void netdev_get_drvinfo(struct net_device *dev,
958 struct ethtool_drvinfo *info)
960 struct r6040_private *rp = netdev_priv(dev);
962 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
963 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
964 strlcpy(info->bus_info, pci_name(rp->pdev), sizeof(info->bus_info));
967 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
969 struct r6040_private *rp = netdev_priv(dev);
971 return phy_ethtool_gset(rp->phydev, cmd);
974 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
976 struct r6040_private *rp = netdev_priv(dev);
978 return phy_ethtool_sset(rp->phydev, cmd);
981 static const struct ethtool_ops netdev_ethtool_ops = {
982 .get_drvinfo = netdev_get_drvinfo,
983 .get_settings = netdev_get_settings,
984 .set_settings = netdev_set_settings,
985 .get_link = ethtool_op_get_link,
986 .get_ts_info = ethtool_op_get_ts_info,
989 static const struct net_device_ops r6040_netdev_ops = {
990 .ndo_open = r6040_open,
991 .ndo_stop = r6040_close,
992 .ndo_start_xmit = r6040_start_xmit,
993 .ndo_get_stats = r6040_get_stats,
994 .ndo_set_rx_mode = r6040_multicast_list,
995 .ndo_change_mtu = eth_change_mtu,
996 .ndo_validate_addr = eth_validate_addr,
997 .ndo_set_mac_address = eth_mac_addr,
998 .ndo_do_ioctl = r6040_ioctl,
999 .ndo_tx_timeout = r6040_tx_timeout,
1000 #ifdef CONFIG_NET_POLL_CONTROLLER
1001 .ndo_poll_controller = r6040_poll_controller,
1005 static void r6040_adjust_link(struct net_device *dev)
1007 struct r6040_private *lp = netdev_priv(dev);
1008 struct phy_device *phydev = lp->phydev;
1009 int status_changed = 0;
1010 void __iomem *ioaddr = lp->base;
1014 if (lp->old_link != phydev->link) {
1016 lp->old_link = phydev->link;
1019 /* reflect duplex change */
1020 if (phydev->link && (lp->old_duplex != phydev->duplex)) {
1021 lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? MCR0_FD : 0);
1022 iowrite16(lp->mcr0, ioaddr);
1025 lp->old_duplex = phydev->duplex;
1028 if (status_changed) {
1029 pr_info("%s: link %s", dev->name, phydev->link ?
1032 pr_cont(" - %d/%s", phydev->speed,
1033 DUPLEX_FULL == phydev->duplex ? "full" : "half");
1038 static int r6040_mii_probe(struct net_device *dev)
1040 struct r6040_private *lp = netdev_priv(dev);
1041 struct phy_device *phydev = NULL;
1043 phydev = phy_find_first(lp->mii_bus);
1045 dev_err(&lp->pdev->dev, "no PHY found\n");
1049 phydev = phy_connect(dev, dev_name(&phydev->dev), &r6040_adjust_link,
1050 PHY_INTERFACE_MODE_MII);
1052 if (IS_ERR(phydev)) {
1053 dev_err(&lp->pdev->dev, "could not attach to PHY\n");
1054 return PTR_ERR(phydev);
1057 /* mask with MAC supported features */
1058 phydev->supported &= (SUPPORTED_10baseT_Half
1059 | SUPPORTED_10baseT_Full
1060 | SUPPORTED_100baseT_Half
1061 | SUPPORTED_100baseT_Full
1066 phydev->advertising = phydev->supported;
1067 lp->phydev = phydev;
1069 lp->old_duplex = -1;
1071 dev_info(&lp->pdev->dev, "attached PHY driver [%s] "
1072 "(mii_bus:phy_addr=%s)\n",
1073 phydev->drv->name, dev_name(&phydev->dev));
1078 static int r6040_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1080 struct net_device *dev;
1081 struct r6040_private *lp;
1082 void __iomem *ioaddr;
1083 int err, io_size = R6040_IO_SIZE;
1084 static int card_idx = -1;
1089 pr_info("%s\n", version);
1091 err = pci_enable_device(pdev);
1095 /* this should always be supported */
1096 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1098 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1099 "not supported by the card\n");
1100 goto err_out_disable_dev;
1102 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1104 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1105 "not supported by the card\n");
1106 goto err_out_disable_dev;
1110 if (pci_resource_len(pdev, bar) < io_size) {
1111 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
1113 goto err_out_disable_dev;
1116 pci_set_master(pdev);
1118 dev = alloc_etherdev(sizeof(struct r6040_private));
1121 goto err_out_disable_dev;
1123 SET_NETDEV_DEV(dev, &pdev->dev);
1124 lp = netdev_priv(dev);
1126 err = pci_request_regions(pdev, DRV_NAME);
1129 dev_err(&pdev->dev, "Failed to request PCI regions\n");
1130 goto err_out_free_dev;
1133 ioaddr = pci_iomap(pdev, bar, io_size);
1135 dev_err(&pdev->dev, "ioremap failed for device\n");
1137 goto err_out_free_res;
1140 /* If PHY status change register is still set to zero it means the
1141 * bootloader didn't initialize it, so we set it to:
1142 * - enable phy status change
1143 * - enable all phy addresses
1144 * - set to lowest timer divider */
1145 if (ioread16(ioaddr + PHY_CC) == 0)
1146 iowrite16(SCEN | PHY_MAX_ADDR << PHYAD_SHIFT |
1147 7 << TMRDIV_SHIFT, ioaddr + PHY_CC);
1149 /* Init system & device */
1151 dev->irq = pdev->irq;
1153 spin_lock_init(&lp->lock);
1154 pci_set_drvdata(pdev, dev);
1156 /* Set MAC address */
1159 adrp = (u16 *)dev->dev_addr;
1160 adrp[0] = ioread16(ioaddr + MID_0L);
1161 adrp[1] = ioread16(ioaddr + MID_0M);
1162 adrp[2] = ioread16(ioaddr + MID_0H);
1164 /* Some bootloader/BIOSes do not initialize
1165 * MAC address, warn about that */
1166 if (!(adrp[0] || adrp[1] || adrp[2])) {
1167 netdev_warn(dev, "MAC address not initialized, "
1168 "generating random\n");
1169 eth_hw_addr_random(dev);
1172 /* Link new device into r6040_root_dev */
1176 /* Init RDC private data */
1177 lp->mcr0 = MCR0_XMTEN | MCR0_RCVEN;
1179 /* The RDC-specific entries in the device structure. */
1180 dev->netdev_ops = &r6040_netdev_ops;
1181 dev->ethtool_ops = &netdev_ethtool_ops;
1182 dev->watchdog_timeo = TX_TIMEOUT;
1184 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1186 lp->mii_bus = mdiobus_alloc();
1188 dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
1193 lp->mii_bus->priv = dev;
1194 lp->mii_bus->read = r6040_mdiobus_read;
1195 lp->mii_bus->write = r6040_mdiobus_write;
1196 lp->mii_bus->name = "r6040_eth_mii";
1197 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1198 dev_name(&pdev->dev), card_idx);
1199 lp->mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
1200 if (!lp->mii_bus->irq) {
1205 for (i = 0; i < PHY_MAX_ADDR; i++)
1206 lp->mii_bus->irq[i] = PHY_POLL;
1208 err = mdiobus_register(lp->mii_bus);
1210 dev_err(&pdev->dev, "failed to register MII bus\n");
1211 goto err_out_mdio_irq;
1214 err = r6040_mii_probe(dev);
1216 dev_err(&pdev->dev, "failed to probe MII bus\n");
1217 goto err_out_mdio_unregister;
1220 /* Register net device. After this dev->name assign */
1221 err = register_netdev(dev);
1223 dev_err(&pdev->dev, "Failed to register net device\n");
1224 goto err_out_mdio_unregister;
1228 err_out_mdio_unregister:
1229 mdiobus_unregister(lp->mii_bus);
1231 kfree(lp->mii_bus->irq);
1233 mdiobus_free(lp->mii_bus);
1235 netif_napi_del(&lp->napi);
1236 pci_iounmap(pdev, ioaddr);
1238 pci_release_regions(pdev);
1241 err_out_disable_dev:
1242 pci_disable_device(pdev);
1247 static void r6040_remove_one(struct pci_dev *pdev)
1249 struct net_device *dev = pci_get_drvdata(pdev);
1250 struct r6040_private *lp = netdev_priv(dev);
1252 unregister_netdev(dev);
1253 mdiobus_unregister(lp->mii_bus);
1254 kfree(lp->mii_bus->irq);
1255 mdiobus_free(lp->mii_bus);
1256 netif_napi_del(&lp->napi);
1257 pci_iounmap(pdev, lp->base);
1258 pci_release_regions(pdev);
1260 pci_disable_device(pdev);
1264 static const struct pci_device_id r6040_pci_tbl[] = {
1265 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1268 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1270 static struct pci_driver r6040_driver = {
1272 .id_table = r6040_pci_tbl,
1273 .probe = r6040_init_one,
1274 .remove = r6040_remove_one,
1277 module_pci_driver(r6040_driver);