2 * QLogic qlge NIC HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 * See LICENSE.qlge for copyright and licensing details.
5 * Author: Linux qlge network device driver by
6 * Ron Mercer <ron.mercer@qlogic.com>
8 #include <linux/kernel.h>
9 #include <linux/bitops.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/pagemap.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
27 #include <linux/ipv6.h>
29 #include <linux/tcp.h>
30 #include <linux/udp.h>
31 #include <linux/if_arp.h>
32 #include <linux/if_ether.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/if_vlan.h>
37 #include <linux/skbuff.h>
38 #include <linux/delay.h>
40 #include <linux/vmalloc.h>
41 #include <linux/prefetch.h>
42 #include <net/ip6_checksum.h>
46 char qlge_driver_name[] = DRV_NAME;
47 const char qlge_driver_version[] = DRV_VERSION;
49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50 MODULE_DESCRIPTION(DRV_STRING " ");
51 MODULE_LICENSE("GPL");
52 MODULE_VERSION(DRV_VERSION);
54 static const u32 default_msg =
55 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
56 /* NETIF_MSG_TIMER | */
61 /* NETIF_MSG_TX_QUEUED | */
62 /* NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
63 /* NETIF_MSG_PKTDATA | */
64 NETIF_MSG_HW | NETIF_MSG_WOL | 0;
66 static int debug = -1; /* defaults above */
67 module_param(debug, int, 0664);
68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
73 static int qlge_irq_type = MSIX_IRQ;
74 module_param(qlge_irq_type, int, 0664);
75 MODULE_PARM_DESC(qlge_irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
77 static int qlge_mpi_coredump;
78 module_param(qlge_mpi_coredump, int, 0);
79 MODULE_PARM_DESC(qlge_mpi_coredump,
80 "Option to enable MPI firmware dump. "
81 "Default is OFF - Do Not allocate memory. ");
83 static int qlge_force_coredump;
84 module_param(qlge_force_coredump, int, 0);
85 MODULE_PARM_DESC(qlge_force_coredump,
86 "Option to allow force of firmware core dump. "
87 "Default is OFF - Do not allow.");
89 static const struct pci_device_id qlge_pci_tbl[] = {
90 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
91 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
92 /* required last entry */
96 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
98 static int ql_wol(struct ql_adapter *);
99 static void qlge_set_multicast_list(struct net_device *);
100 static int ql_adapter_down(struct ql_adapter *);
101 static int ql_adapter_up(struct ql_adapter *);
103 /* This hardware semaphore causes exclusive access to
104 * resources shared between the NIC driver, MPI firmware,
105 * FCOE firmware and the FC driver.
107 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
112 case SEM_XGMAC0_MASK:
113 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
115 case SEM_XGMAC1_MASK:
116 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
119 sem_bits = SEM_SET << SEM_ICB_SHIFT;
121 case SEM_MAC_ADDR_MASK:
122 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
125 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
128 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
130 case SEM_RT_IDX_MASK:
131 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
133 case SEM_PROC_REG_MASK:
134 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
137 netif_alert(qdev, probe, qdev->ndev, "bad Semaphore mask!.\n");
141 ql_write32(qdev, SEM, sem_bits | sem_mask);
142 return !(ql_read32(qdev, SEM) & sem_bits);
145 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
147 unsigned int wait_count = 30;
149 if (!ql_sem_trylock(qdev, sem_mask))
152 } while (--wait_count);
156 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
158 ql_write32(qdev, SEM, sem_mask);
159 ql_read32(qdev, SEM); /* flush */
162 /* This function waits for a specific bit to come ready
163 * in a given register. It is used mostly by the initialize
164 * process, but is also used in kernel thread API such as
165 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
167 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
170 int count = UDELAY_COUNT;
173 temp = ql_read32(qdev, reg);
175 /* check for errors */
176 if (temp & err_bit) {
177 netif_alert(qdev, probe, qdev->ndev,
178 "register 0x%.08x access error, value = 0x%.08x!.\n",
181 } else if (temp & bit)
183 udelay(UDELAY_DELAY);
186 netif_alert(qdev, probe, qdev->ndev,
187 "Timed out waiting for reg %x to come ready.\n", reg);
191 /* The CFG register is used to download TX and RX control blocks
192 * to the chip. This function waits for an operation to complete.
194 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
196 int count = UDELAY_COUNT;
200 temp = ql_read32(qdev, CFG);
205 udelay(UDELAY_DELAY);
212 /* Used to issue init control blocks to hw. Maps control block,
213 * sets address, triggers download, waits for completion.
215 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
225 (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
228 map = pci_map_single(qdev->pdev, ptr, size, direction);
229 if (pci_dma_mapping_error(qdev->pdev, map)) {
230 netif_err(qdev, ifup, qdev->ndev, "Couldn't map DMA area.\n");
234 status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
238 status = ql_wait_cfg(qdev, bit);
240 netif_err(qdev, ifup, qdev->ndev,
241 "Timed out waiting for CFG to come ready.\n");
245 ql_write32(qdev, ICB_L, (u32) map);
246 ql_write32(qdev, ICB_H, (u32) (map >> 32));
248 mask = CFG_Q_MASK | (bit << 16);
249 value = bit | (q_id << CFG_Q_SHIFT);
250 ql_write32(qdev, CFG, (mask | value));
253 * Wait for the bit to clear after signaling hw.
255 status = ql_wait_cfg(qdev, bit);
257 ql_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */
258 pci_unmap_single(qdev->pdev, map, size, direction);
262 /* Get a specific MAC address from the CAM. Used for debug and reg dump. */
263 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
270 case MAC_ADDR_TYPE_MULTI_MAC:
271 case MAC_ADDR_TYPE_CAM_MAC:
274 ql_wait_reg_rdy(qdev,
275 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
278 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
279 (index << MAC_ADDR_IDX_SHIFT) | /* index */
280 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
282 ql_wait_reg_rdy(qdev,
283 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
286 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
288 ql_wait_reg_rdy(qdev,
289 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
292 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
293 (index << MAC_ADDR_IDX_SHIFT) | /* index */
294 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
296 ql_wait_reg_rdy(qdev,
297 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
300 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
301 if (type == MAC_ADDR_TYPE_CAM_MAC) {
303 ql_wait_reg_rdy(qdev,
304 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
307 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
308 (index << MAC_ADDR_IDX_SHIFT) | /* index */
309 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
311 ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
315 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
319 case MAC_ADDR_TYPE_VLAN:
320 case MAC_ADDR_TYPE_MULTI_FLTR:
322 netif_crit(qdev, ifup, qdev->ndev,
323 "Address type %d not yet supported.\n", type);
330 /* Set up a MAC, multicast or VLAN address for the
331 * inbound frame matching.
333 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
340 case MAC_ADDR_TYPE_MULTI_MAC:
342 u32 upper = (addr[0] << 8) | addr[1];
343 u32 lower = (addr[2] << 24) | (addr[3] << 16) |
344 (addr[4] << 8) | (addr[5]);
347 ql_wait_reg_rdy(qdev,
348 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
351 ql_write32(qdev, MAC_ADDR_IDX, (offset++) |
352 (index << MAC_ADDR_IDX_SHIFT) |
354 ql_write32(qdev, MAC_ADDR_DATA, lower);
356 ql_wait_reg_rdy(qdev,
357 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
360 ql_write32(qdev, MAC_ADDR_IDX, (offset++) |
361 (index << MAC_ADDR_IDX_SHIFT) |
364 ql_write32(qdev, MAC_ADDR_DATA, upper);
366 ql_wait_reg_rdy(qdev,
367 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
372 case MAC_ADDR_TYPE_CAM_MAC:
375 u32 upper = (addr[0] << 8) | addr[1];
377 (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
380 ql_wait_reg_rdy(qdev,
381 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
384 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
385 (index << MAC_ADDR_IDX_SHIFT) | /* index */
387 ql_write32(qdev, MAC_ADDR_DATA, lower);
389 ql_wait_reg_rdy(qdev,
390 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
393 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
394 (index << MAC_ADDR_IDX_SHIFT) | /* index */
396 ql_write32(qdev, MAC_ADDR_DATA, upper);
398 ql_wait_reg_rdy(qdev,
399 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
402 ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */
403 (index << MAC_ADDR_IDX_SHIFT) | /* index */
405 /* This field should also include the queue id
406 and possibly the function id. Right now we hardcode
407 the route field to NIC core.
409 cam_output = (CAM_OUT_ROUTE_NIC |
411 func << CAM_OUT_FUNC_SHIFT) |
412 (0 << CAM_OUT_CQ_ID_SHIFT));
413 if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
414 cam_output |= CAM_OUT_RV;
415 /* route to NIC core */
416 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
419 case MAC_ADDR_TYPE_VLAN:
421 u32 enable_bit = *((u32 *) &addr[0]);
422 /* For VLAN, the addr actually holds a bit that
423 * either enables or disables the vlan id we are
424 * addressing. It's either MAC_ADDR_E on or off.
425 * That's bit-27 we're talking about.
428 ql_wait_reg_rdy(qdev,
429 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
432 ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
433 (index << MAC_ADDR_IDX_SHIFT) | /* index */
435 enable_bit); /* enable/disable */
438 case MAC_ADDR_TYPE_MULTI_FLTR:
440 netif_crit(qdev, ifup, qdev->ndev,
441 "Address type %d not yet supported.\n", type);
448 /* Set or clear MAC address in hardware. We sometimes
449 * have to clear it to prevent wrong frame routing
450 * especially in a bonding environment.
452 static int ql_set_mac_addr(struct ql_adapter *qdev, int set)
455 char zero_mac_addr[ETH_ALEN];
459 addr = &qdev->current_mac_addr[0];
460 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
461 "Set Mac addr %pM\n", addr);
463 eth_zero_addr(zero_mac_addr);
464 addr = &zero_mac_addr[0];
465 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
466 "Clearing MAC address\n");
468 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
471 status = ql_set_mac_addr_reg(qdev, (u8 *) addr,
472 MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
473 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
475 netif_err(qdev, ifup, qdev->ndev,
476 "Failed to init mac address.\n");
480 void ql_link_on(struct ql_adapter *qdev)
482 netif_err(qdev, link, qdev->ndev, "Link is up.\n");
483 netif_carrier_on(qdev->ndev);
484 ql_set_mac_addr(qdev, 1);
487 void ql_link_off(struct ql_adapter *qdev)
489 netif_err(qdev, link, qdev->ndev, "Link is down.\n");
490 netif_carrier_off(qdev->ndev);
491 ql_set_mac_addr(qdev, 0);
494 /* Get a specific frame routing value from the CAM.
495 * Used for debug and reg dump.
497 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
501 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
505 ql_write32(qdev, RT_IDX,
506 RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
507 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
510 *value = ql_read32(qdev, RT_DATA);
515 /* The NIC function for this chip has 16 routing indexes. Each one can be used
516 * to route different frame types to various inbound queues. We send broadcast/
517 * multicast/error frames to the default queue for slow handling,
518 * and CAM hit/RSS frames to the fast handling queues.
520 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
523 int status = -EINVAL; /* Return error if no mask match. */
529 value = RT_IDX_DST_CAM_Q | /* dest */
530 RT_IDX_TYPE_NICQ | /* type */
531 (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
534 case RT_IDX_VALID: /* Promiscuous Mode frames. */
536 value = RT_IDX_DST_DFLT_Q | /* dest */
537 RT_IDX_TYPE_NICQ | /* type */
538 (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
541 case RT_IDX_ERR: /* Pass up MAC,IP,TCP/UDP error frames. */
543 value = RT_IDX_DST_DFLT_Q | /* dest */
544 RT_IDX_TYPE_NICQ | /* type */
545 (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
548 case RT_IDX_IP_CSUM_ERR: /* Pass up IP CSUM error frames. */
550 value = RT_IDX_DST_DFLT_Q | /* dest */
551 RT_IDX_TYPE_NICQ | /* type */
552 (RT_IDX_IP_CSUM_ERR_SLOT <<
553 RT_IDX_IDX_SHIFT); /* index */
556 case RT_IDX_TU_CSUM_ERR: /* Pass up TCP/UDP CSUM error frames. */
558 value = RT_IDX_DST_DFLT_Q | /* dest */
559 RT_IDX_TYPE_NICQ | /* type */
560 (RT_IDX_TCP_UDP_CSUM_ERR_SLOT <<
561 RT_IDX_IDX_SHIFT); /* index */
564 case RT_IDX_BCAST: /* Pass up Broadcast frames to default Q. */
566 value = RT_IDX_DST_DFLT_Q | /* dest */
567 RT_IDX_TYPE_NICQ | /* type */
568 (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
571 case RT_IDX_MCAST: /* Pass up All Multicast frames. */
573 value = RT_IDX_DST_DFLT_Q | /* dest */
574 RT_IDX_TYPE_NICQ | /* type */
575 (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
578 case RT_IDX_MCAST_MATCH: /* Pass up matched Multicast frames. */
580 value = RT_IDX_DST_DFLT_Q | /* dest */
581 RT_IDX_TYPE_NICQ | /* type */
582 (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
585 case RT_IDX_RSS_MATCH: /* Pass up matched RSS frames. */
587 value = RT_IDX_DST_RSS | /* dest */
588 RT_IDX_TYPE_NICQ | /* type */
589 (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
592 case 0: /* Clear the E-bit on an entry. */
594 value = RT_IDX_DST_DFLT_Q | /* dest */
595 RT_IDX_TYPE_NICQ | /* type */
596 (index << RT_IDX_IDX_SHIFT);/* index */
600 netif_err(qdev, ifup, qdev->ndev,
601 "Mask type %d not yet supported.\n", mask);
607 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
610 value |= (enable ? RT_IDX_E : 0);
611 ql_write32(qdev, RT_IDX, value);
612 ql_write32(qdev, RT_DATA, enable ? mask : 0);
618 static void ql_enable_interrupts(struct ql_adapter *qdev)
620 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
623 static void ql_disable_interrupts(struct ql_adapter *qdev)
625 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
628 /* If we're running with multiple MSI-X vectors then we enable on the fly.
629 * Otherwise, we may have multiple outstanding workers and don't want to
630 * enable until the last one finishes. In this case, the irq_cnt gets
631 * incremented every time we queue a worker and decremented every time
632 * a worker finishes. Once it hits zero we enable the interrupt.
634 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
637 unsigned long hw_flags = 0;
638 struct intr_context *ctx = qdev->intr_context + intr;
640 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
641 /* Always enable if we're MSIX multi interrupts and
642 * it's not the default (zeroeth) interrupt.
644 ql_write32(qdev, INTR_EN,
646 var = ql_read32(qdev, STS);
650 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
651 if (atomic_dec_and_test(&ctx->irq_cnt)) {
652 ql_write32(qdev, INTR_EN,
654 var = ql_read32(qdev, STS);
656 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
660 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
663 struct intr_context *ctx;
665 /* HW disables for us if we're MSIX multi interrupts and
666 * it's not the default (zeroeth) interrupt.
668 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
671 ctx = qdev->intr_context + intr;
672 spin_lock(&qdev->hw_lock);
673 if (!atomic_read(&ctx->irq_cnt)) {
674 ql_write32(qdev, INTR_EN,
676 var = ql_read32(qdev, STS);
678 atomic_inc(&ctx->irq_cnt);
679 spin_unlock(&qdev->hw_lock);
683 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
686 for (i = 0; i < qdev->intr_count; i++) {
687 /* The enable call does a atomic_dec_and_test
688 * and enables only if the result is zero.
689 * So we precharge it here.
691 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
693 atomic_set(&qdev->intr_context[i].irq_cnt, 1);
694 ql_enable_completion_interrupt(qdev, i);
699 static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
703 __le16 *flash = (__le16 *)&qdev->flash;
705 status = strncmp((char *)&qdev->flash, str, 4);
707 netif_err(qdev, ifup, qdev->ndev, "Invalid flash signature.\n");
711 for (i = 0; i < size; i++)
712 csum += le16_to_cpu(*flash++);
715 netif_err(qdev, ifup, qdev->ndev,
716 "Invalid flash checksum, csum = 0x%.04x.\n", csum);
721 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
724 /* wait for reg to come ready */
725 status = ql_wait_reg_rdy(qdev,
726 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
729 /* set up for reg read */
730 ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
731 /* wait for reg to come ready */
732 status = ql_wait_reg_rdy(qdev,
733 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
736 /* This data is stored on flash as an array of
737 * __le32. Since ql_read32() returns cpu endian
738 * we need to swap it back.
740 *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
745 static int ql_get_8000_flash_params(struct ql_adapter *qdev)
749 __le32 *p = (__le32 *)&qdev->flash;
753 /* Get flash offset for function and adjust
757 offset = FUNC0_FLASH_OFFSET / sizeof(u32);
759 offset = FUNC1_FLASH_OFFSET / sizeof(u32);
761 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
764 size = sizeof(struct flash_params_8000) / sizeof(u32);
765 for (i = 0; i < size; i++, p++) {
766 status = ql_read_flash_word(qdev, i+offset, p);
768 netif_err(qdev, ifup, qdev->ndev,
769 "Error reading flash.\n");
774 status = ql_validate_flash(qdev,
775 sizeof(struct flash_params_8000) / sizeof(u16),
778 netif_err(qdev, ifup, qdev->ndev, "Invalid flash.\n");
783 /* Extract either manufacturer or BOFM modified
786 if (qdev->flash.flash_params_8000.data_type1 == 2)
788 qdev->flash.flash_params_8000.mac_addr1,
789 qdev->ndev->addr_len);
792 qdev->flash.flash_params_8000.mac_addr,
793 qdev->ndev->addr_len);
795 if (!is_valid_ether_addr(mac_addr)) {
796 netif_err(qdev, ifup, qdev->ndev, "Invalid MAC address.\n");
801 memcpy(qdev->ndev->dev_addr,
803 qdev->ndev->addr_len);
806 ql_sem_unlock(qdev, SEM_FLASH_MASK);
810 static int ql_get_8012_flash_params(struct ql_adapter *qdev)
814 __le32 *p = (__le32 *)&qdev->flash;
816 u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
818 /* Second function's parameters follow the first
824 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
827 for (i = 0; i < size; i++, p++) {
828 status = ql_read_flash_word(qdev, i+offset, p);
830 netif_err(qdev, ifup, qdev->ndev,
831 "Error reading flash.\n");
837 status = ql_validate_flash(qdev,
838 sizeof(struct flash_params_8012) / sizeof(u16),
841 netif_err(qdev, ifup, qdev->ndev, "Invalid flash.\n");
846 if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
851 memcpy(qdev->ndev->dev_addr,
852 qdev->flash.flash_params_8012.mac_addr,
853 qdev->ndev->addr_len);
856 ql_sem_unlock(qdev, SEM_FLASH_MASK);
860 /* xgmac register are located behind the xgmac_addr and xgmac_data
861 * register pair. Each read/write requires us to wait for the ready
862 * bit before reading/writing the data.
864 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
867 /* wait for reg to come ready */
868 status = ql_wait_reg_rdy(qdev,
869 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
872 /* write the data to the data reg */
873 ql_write32(qdev, XGMAC_DATA, data);
874 /* trigger the write */
875 ql_write32(qdev, XGMAC_ADDR, reg);
879 /* xgmac register are located behind the xgmac_addr and xgmac_data
880 * register pair. Each read/write requires us to wait for the ready
881 * bit before reading/writing the data.
883 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
886 /* wait for reg to come ready */
887 status = ql_wait_reg_rdy(qdev,
888 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
891 /* set up for reg read */
892 ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
893 /* wait for reg to come ready */
894 status = ql_wait_reg_rdy(qdev,
895 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
899 *data = ql_read32(qdev, XGMAC_DATA);
904 /* This is used for reading the 64-bit statistics regs. */
905 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
911 status = ql_read_xgmac_reg(qdev, reg, &lo);
915 status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
919 *data = (u64) lo | ((u64) hi << 32);
925 static int ql_8000_port_initialize(struct ql_adapter *qdev)
929 * Get MPI firmware version for driver banner
932 status = ql_mb_about_fw(qdev);
935 status = ql_mb_get_fw_state(qdev);
938 /* Wake up a worker to get/set the TX/RX frame sizes. */
939 queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0);
944 /* Take the MAC Core out of reset.
945 * Enable statistics counting.
946 * Take the transmitter/receiver out of reset.
947 * This functionality may be done in the MPI firmware at a
950 static int ql_8012_port_initialize(struct ql_adapter *qdev)
955 if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
956 /* Another function has the semaphore, so
957 * wait for the port init bit to come ready.
959 netif_info(qdev, link, qdev->ndev,
960 "Another function has the semaphore, so wait for the port init bit to come ready.\n");
961 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
963 netif_crit(qdev, link, qdev->ndev,
964 "Port initialize timed out.\n");
969 netif_info(qdev, link, qdev->ndev, "Got xgmac semaphore!.\n");
970 /* Set the core reset. */
971 status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
974 data |= GLOBAL_CFG_RESET;
975 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
979 /* Clear the core reset and turn on jumbo for receiver. */
980 data &= ~GLOBAL_CFG_RESET; /* Clear core reset. */
981 data |= GLOBAL_CFG_JUMBO; /* Turn on jumbo. */
982 data |= GLOBAL_CFG_TX_STAT_EN;
983 data |= GLOBAL_CFG_RX_STAT_EN;
984 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
988 /* Enable transmitter, and clear it's reset. */
989 status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
992 data &= ~TX_CFG_RESET; /* Clear the TX MAC reset. */
993 data |= TX_CFG_EN; /* Enable the transmitter. */
994 status = ql_write_xgmac_reg(qdev, TX_CFG, data);
998 /* Enable receiver and clear it's reset. */
999 status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
1002 data &= ~RX_CFG_RESET; /* Clear the RX MAC reset. */
1003 data |= RX_CFG_EN; /* Enable the receiver. */
1004 status = ql_write_xgmac_reg(qdev, RX_CFG, data);
1008 /* Turn on jumbo. */
1010 ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
1014 ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
1018 /* Signal to the world that the port is enabled. */
1019 ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
1021 ql_sem_unlock(qdev, qdev->xg_sem_mask);
1025 static inline unsigned int ql_lbq_block_size(struct ql_adapter *qdev)
1027 return PAGE_SIZE << qdev->lbq_buf_order;
1030 /* Get the next large buffer. */
1031 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
1033 struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
1034 rx_ring->lbq_curr_idx++;
1035 if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
1036 rx_ring->lbq_curr_idx = 0;
1037 rx_ring->lbq_free_cnt++;
1041 static struct bq_desc *ql_get_curr_lchunk(struct ql_adapter *qdev,
1042 struct rx_ring *rx_ring)
1044 struct bq_desc *lbq_desc = ql_get_curr_lbuf(rx_ring);
1046 pci_dma_sync_single_for_cpu(qdev->pdev,
1047 dma_unmap_addr(lbq_desc, mapaddr),
1048 rx_ring->lbq_buf_size,
1049 PCI_DMA_FROMDEVICE);
1051 /* If it's the last chunk of our master page then
1054 if ((lbq_desc->p.pg_chunk.offset + rx_ring->lbq_buf_size)
1055 == ql_lbq_block_size(qdev))
1056 pci_unmap_page(qdev->pdev,
1057 lbq_desc->p.pg_chunk.map,
1058 ql_lbq_block_size(qdev),
1059 PCI_DMA_FROMDEVICE);
1063 /* Get the next small buffer. */
1064 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
1066 struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
1067 rx_ring->sbq_curr_idx++;
1068 if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
1069 rx_ring->sbq_curr_idx = 0;
1070 rx_ring->sbq_free_cnt++;
1074 /* Update an rx ring index. */
1075 static void ql_update_cq(struct rx_ring *rx_ring)
1077 rx_ring->cnsmr_idx++;
1078 rx_ring->curr_entry++;
1079 if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
1080 rx_ring->cnsmr_idx = 0;
1081 rx_ring->curr_entry = rx_ring->cq_base;
1085 static void ql_write_cq_idx(struct rx_ring *rx_ring)
1087 ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
1090 static int ql_get_next_chunk(struct ql_adapter *qdev, struct rx_ring *rx_ring,
1091 struct bq_desc *lbq_desc)
1093 if (!rx_ring->pg_chunk.page) {
1095 rx_ring->pg_chunk.page = alloc_pages(__GFP_COLD | __GFP_COMP |
1097 qdev->lbq_buf_order);
1098 if (unlikely(!rx_ring->pg_chunk.page)) {
1099 netif_err(qdev, drv, qdev->ndev,
1100 "page allocation failed.\n");
1103 rx_ring->pg_chunk.offset = 0;
1104 map = pci_map_page(qdev->pdev, rx_ring->pg_chunk.page,
1105 0, ql_lbq_block_size(qdev),
1106 PCI_DMA_FROMDEVICE);
1107 if (pci_dma_mapping_error(qdev->pdev, map)) {
1108 __free_pages(rx_ring->pg_chunk.page,
1109 qdev->lbq_buf_order);
1110 rx_ring->pg_chunk.page = NULL;
1111 netif_err(qdev, drv, qdev->ndev,
1112 "PCI mapping failed.\n");
1115 rx_ring->pg_chunk.map = map;
1116 rx_ring->pg_chunk.va = page_address(rx_ring->pg_chunk.page);
1119 /* Copy the current master pg_chunk info
1120 * to the current descriptor.
1122 lbq_desc->p.pg_chunk = rx_ring->pg_chunk;
1124 /* Adjust the master page chunk for next
1127 rx_ring->pg_chunk.offset += rx_ring->lbq_buf_size;
1128 if (rx_ring->pg_chunk.offset == ql_lbq_block_size(qdev)) {
1129 rx_ring->pg_chunk.page = NULL;
1130 lbq_desc->p.pg_chunk.last_flag = 1;
1132 rx_ring->pg_chunk.va += rx_ring->lbq_buf_size;
1133 get_page(rx_ring->pg_chunk.page);
1134 lbq_desc->p.pg_chunk.last_flag = 0;
1138 /* Process (refill) a large buffer queue. */
1139 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1141 u32 clean_idx = rx_ring->lbq_clean_idx;
1142 u32 start_idx = clean_idx;
1143 struct bq_desc *lbq_desc;
1147 while (rx_ring->lbq_free_cnt > 32) {
1148 for (i = (rx_ring->lbq_clean_idx % 16); i < 16; i++) {
1149 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1150 "lbq: try cleaning clean_idx = %d.\n",
1152 lbq_desc = &rx_ring->lbq[clean_idx];
1153 if (ql_get_next_chunk(qdev, rx_ring, lbq_desc)) {
1154 rx_ring->lbq_clean_idx = clean_idx;
1155 netif_err(qdev, ifup, qdev->ndev,
1156 "Could not get a page chunk, i=%d, clean_idx =%d .\n",
1161 map = lbq_desc->p.pg_chunk.map +
1162 lbq_desc->p.pg_chunk.offset;
1163 dma_unmap_addr_set(lbq_desc, mapaddr, map);
1164 dma_unmap_len_set(lbq_desc, maplen,
1165 rx_ring->lbq_buf_size);
1166 *lbq_desc->addr = cpu_to_le64(map);
1168 pci_dma_sync_single_for_device(qdev->pdev, map,
1169 rx_ring->lbq_buf_size,
1170 PCI_DMA_FROMDEVICE);
1172 if (clean_idx == rx_ring->lbq_len)
1176 rx_ring->lbq_clean_idx = clean_idx;
1177 rx_ring->lbq_prod_idx += 16;
1178 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
1179 rx_ring->lbq_prod_idx = 0;
1180 rx_ring->lbq_free_cnt -= 16;
1183 if (start_idx != clean_idx) {
1184 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1185 "lbq: updating prod idx = %d.\n",
1186 rx_ring->lbq_prod_idx);
1187 ql_write_db_reg(rx_ring->lbq_prod_idx,
1188 rx_ring->lbq_prod_idx_db_reg);
1192 /* Process (refill) a small buffer queue. */
1193 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1195 u32 clean_idx = rx_ring->sbq_clean_idx;
1196 u32 start_idx = clean_idx;
1197 struct bq_desc *sbq_desc;
1201 while (rx_ring->sbq_free_cnt > 16) {
1202 for (i = (rx_ring->sbq_clean_idx % 16); i < 16; i++) {
1203 sbq_desc = &rx_ring->sbq[clean_idx];
1204 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1205 "sbq: try cleaning clean_idx = %d.\n",
1207 if (sbq_desc->p.skb == NULL) {
1208 netif_printk(qdev, rx_status, KERN_DEBUG,
1210 "sbq: getting new skb for index %d.\n",
1213 netdev_alloc_skb(qdev->ndev,
1215 if (sbq_desc->p.skb == NULL) {
1216 rx_ring->sbq_clean_idx = clean_idx;
1219 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
1220 map = pci_map_single(qdev->pdev,
1221 sbq_desc->p.skb->data,
1222 rx_ring->sbq_buf_size,
1223 PCI_DMA_FROMDEVICE);
1224 if (pci_dma_mapping_error(qdev->pdev, map)) {
1225 netif_err(qdev, ifup, qdev->ndev,
1226 "PCI mapping failed.\n");
1227 rx_ring->sbq_clean_idx = clean_idx;
1228 dev_kfree_skb_any(sbq_desc->p.skb);
1229 sbq_desc->p.skb = NULL;
1232 dma_unmap_addr_set(sbq_desc, mapaddr, map);
1233 dma_unmap_len_set(sbq_desc, maplen,
1234 rx_ring->sbq_buf_size);
1235 *sbq_desc->addr = cpu_to_le64(map);
1239 if (clean_idx == rx_ring->sbq_len)
1242 rx_ring->sbq_clean_idx = clean_idx;
1243 rx_ring->sbq_prod_idx += 16;
1244 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1245 rx_ring->sbq_prod_idx = 0;
1246 rx_ring->sbq_free_cnt -= 16;
1249 if (start_idx != clean_idx) {
1250 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1251 "sbq: updating prod idx = %d.\n",
1252 rx_ring->sbq_prod_idx);
1253 ql_write_db_reg(rx_ring->sbq_prod_idx,
1254 rx_ring->sbq_prod_idx_db_reg);
1258 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1259 struct rx_ring *rx_ring)
1261 ql_update_sbq(qdev, rx_ring);
1262 ql_update_lbq(qdev, rx_ring);
1265 /* Unmaps tx buffers. Can be called from send() if a pci mapping
1266 * fails at some stage, or from the interrupt when a tx completes.
1268 static void ql_unmap_send(struct ql_adapter *qdev,
1269 struct tx_ring_desc *tx_ring_desc, int mapped)
1272 for (i = 0; i < mapped; i++) {
1273 if (i == 0 || (i == 7 && mapped > 7)) {
1275 * Unmap the skb->data area, or the
1276 * external sglist (AKA the Outbound
1277 * Address List (OAL)).
1278 * If its the zeroeth element, then it's
1279 * the skb->data area. If it's the 7th
1280 * element and there is more than 6 frags,
1284 netif_printk(qdev, tx_done, KERN_DEBUG,
1286 "unmapping OAL area.\n");
1288 pci_unmap_single(qdev->pdev,
1289 dma_unmap_addr(&tx_ring_desc->map[i],
1291 dma_unmap_len(&tx_ring_desc->map[i],
1295 netif_printk(qdev, tx_done, KERN_DEBUG, qdev->ndev,
1296 "unmapping frag %d.\n", i);
1297 pci_unmap_page(qdev->pdev,
1298 dma_unmap_addr(&tx_ring_desc->map[i],
1300 dma_unmap_len(&tx_ring_desc->map[i],
1301 maplen), PCI_DMA_TODEVICE);
1307 /* Map the buffers for this transmit. This will return
1308 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1310 static int ql_map_send(struct ql_adapter *qdev,
1311 struct ob_mac_iocb_req *mac_iocb_ptr,
1312 struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1314 int len = skb_headlen(skb);
1316 int frag_idx, err, map_idx = 0;
1317 struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1318 int frag_cnt = skb_shinfo(skb)->nr_frags;
1321 netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev,
1322 "frag_cnt = %d.\n", frag_cnt);
1325 * Map the skb buffer first.
1327 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1329 err = pci_dma_mapping_error(qdev->pdev, map);
1331 netif_err(qdev, tx_queued, qdev->ndev,
1332 "PCI mapping failed with error: %d\n", err);
1334 return NETDEV_TX_BUSY;
1337 tbd->len = cpu_to_le32(len);
1338 tbd->addr = cpu_to_le64(map);
1339 dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1340 dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1344 * This loop fills the remainder of the 8 address descriptors
1345 * in the IOCB. If there are more than 7 fragments, then the
1346 * eighth address desc will point to an external list (OAL).
1347 * When this happens, the remainder of the frags will be stored
1350 for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1351 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1353 if (frag_idx == 6 && frag_cnt > 7) {
1354 /* Let's tack on an sglist.
1355 * Our control block will now
1357 * iocb->seg[0] = skb->data
1358 * iocb->seg[1] = frag[0]
1359 * iocb->seg[2] = frag[1]
1360 * iocb->seg[3] = frag[2]
1361 * iocb->seg[4] = frag[3]
1362 * iocb->seg[5] = frag[4]
1363 * iocb->seg[6] = frag[5]
1364 * iocb->seg[7] = ptr to OAL (external sglist)
1365 * oal->seg[0] = frag[6]
1366 * oal->seg[1] = frag[7]
1367 * oal->seg[2] = frag[8]
1368 * oal->seg[3] = frag[9]
1369 * oal->seg[4] = frag[10]
1372 /* Tack on the OAL in the eighth segment of IOCB. */
1373 map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1376 err = pci_dma_mapping_error(qdev->pdev, map);
1378 netif_err(qdev, tx_queued, qdev->ndev,
1379 "PCI mapping outbound address list with error: %d\n",
1384 tbd->addr = cpu_to_le64(map);
1386 * The length is the number of fragments
1387 * that remain to be mapped times the length
1388 * of our sglist (OAL).
1391 cpu_to_le32((sizeof(struct tx_buf_desc) *
1392 (frag_cnt - frag_idx)) | TX_DESC_C);
1393 dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1395 dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1396 sizeof(struct oal));
1397 tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1401 map = skb_frag_dma_map(&qdev->pdev->dev, frag, 0, skb_frag_size(frag),
1404 err = dma_mapping_error(&qdev->pdev->dev, map);
1406 netif_err(qdev, tx_queued, qdev->ndev,
1407 "PCI mapping frags failed with error: %d.\n",
1412 tbd->addr = cpu_to_le64(map);
1413 tbd->len = cpu_to_le32(skb_frag_size(frag));
1414 dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1415 dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1416 skb_frag_size(frag));
1419 /* Save the number of segments we've mapped. */
1420 tx_ring_desc->map_cnt = map_idx;
1421 /* Terminate the last segment. */
1422 tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1423 return NETDEV_TX_OK;
1427 * If the first frag mapping failed, then i will be zero.
1428 * This causes the unmap of the skb->data area. Otherwise
1429 * we pass in the number of frags that mapped successfully
1430 * so they can be umapped.
1432 ql_unmap_send(qdev, tx_ring_desc, map_idx);
1433 return NETDEV_TX_BUSY;
1436 /* Categorizing receive firmware frame errors */
1437 static void ql_categorize_rx_err(struct ql_adapter *qdev, u8 rx_err,
1438 struct rx_ring *rx_ring)
1440 struct nic_stats *stats = &qdev->nic_stats;
1442 stats->rx_err_count++;
1443 rx_ring->rx_errors++;
1445 switch (rx_err & IB_MAC_IOCB_RSP_ERR_MASK) {
1446 case IB_MAC_IOCB_RSP_ERR_CODE_ERR:
1447 stats->rx_code_err++;
1449 case IB_MAC_IOCB_RSP_ERR_OVERSIZE:
1450 stats->rx_oversize_err++;
1452 case IB_MAC_IOCB_RSP_ERR_UNDERSIZE:
1453 stats->rx_undersize_err++;
1455 case IB_MAC_IOCB_RSP_ERR_PREAMBLE:
1456 stats->rx_preamble_err++;
1458 case IB_MAC_IOCB_RSP_ERR_FRAME_LEN:
1459 stats->rx_frame_len_err++;
1461 case IB_MAC_IOCB_RSP_ERR_CRC:
1462 stats->rx_crc_err++;
1469 * ql_update_mac_hdr_len - helper routine to update the mac header length
1470 * based on vlan tags if present
1472 static void ql_update_mac_hdr_len(struct ql_adapter *qdev,
1473 struct ib_mac_iocb_rsp *ib_mac_rsp,
1474 void *page, size_t *len)
1478 if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
1480 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) {
1482 /* Look for stacked vlan tags in ethertype field */
1483 if (tags[6] == ETH_P_8021Q &&
1484 tags[8] == ETH_P_8021Q)
1485 *len += 2 * VLAN_HLEN;
1491 /* Process an inbound completion from an rx ring. */
1492 static void ql_process_mac_rx_gro_page(struct ql_adapter *qdev,
1493 struct rx_ring *rx_ring,
1494 struct ib_mac_iocb_rsp *ib_mac_rsp,
1498 struct sk_buff *skb;
1499 struct bq_desc *lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1500 struct napi_struct *napi = &rx_ring->napi;
1502 /* Frame error, so drop the packet. */
1503 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1504 ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring);
1505 put_page(lbq_desc->p.pg_chunk.page);
1508 napi->dev = qdev->ndev;
1510 skb = napi_get_frags(napi);
1512 netif_err(qdev, drv, qdev->ndev,
1513 "Couldn't get an skb, exiting.\n");
1514 rx_ring->rx_dropped++;
1515 put_page(lbq_desc->p.pg_chunk.page);
1518 prefetch(lbq_desc->p.pg_chunk.va);
1519 __skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1520 lbq_desc->p.pg_chunk.page,
1521 lbq_desc->p.pg_chunk.offset,
1525 skb->data_len += length;
1526 skb->truesize += length;
1527 skb_shinfo(skb)->nr_frags++;
1529 rx_ring->rx_packets++;
1530 rx_ring->rx_bytes += length;
1531 skb->ip_summed = CHECKSUM_UNNECESSARY;
1532 skb_record_rx_queue(skb, rx_ring->cq_id);
1533 if (vlan_id != 0xffff)
1534 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
1535 napi_gro_frags(napi);
1538 /* Process an inbound completion from an rx ring. */
1539 static void ql_process_mac_rx_page(struct ql_adapter *qdev,
1540 struct rx_ring *rx_ring,
1541 struct ib_mac_iocb_rsp *ib_mac_rsp,
1545 struct net_device *ndev = qdev->ndev;
1546 struct sk_buff *skb = NULL;
1548 struct bq_desc *lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1549 struct napi_struct *napi = &rx_ring->napi;
1550 size_t hlen = ETH_HLEN;
1552 skb = netdev_alloc_skb(ndev, length);
1554 rx_ring->rx_dropped++;
1555 put_page(lbq_desc->p.pg_chunk.page);
1559 addr = lbq_desc->p.pg_chunk.va;
1562 /* Frame error, so drop the packet. */
1563 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1564 ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring);
1568 /* Update the MAC header length*/
1569 ql_update_mac_hdr_len(qdev, ib_mac_rsp, addr, &hlen);
1571 /* The max framesize filter on this chip is set higher than
1572 * MTU since FCoE uses 2k frames.
1574 if (skb->len > ndev->mtu + hlen) {
1575 netif_err(qdev, drv, qdev->ndev,
1576 "Segment too small, dropping.\n");
1577 rx_ring->rx_dropped++;
1580 memcpy(skb_put(skb, hlen), addr, hlen);
1581 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1582 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n",
1584 skb_fill_page_desc(skb, 0, lbq_desc->p.pg_chunk.page,
1585 lbq_desc->p.pg_chunk.offset + hlen,
1587 skb->len += length - hlen;
1588 skb->data_len += length - hlen;
1589 skb->truesize += length - hlen;
1591 rx_ring->rx_packets++;
1592 rx_ring->rx_bytes += skb->len;
1593 skb->protocol = eth_type_trans(skb, ndev);
1594 skb_checksum_none_assert(skb);
1596 if ((ndev->features & NETIF_F_RXCSUM) &&
1597 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1599 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1600 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1601 "TCP checksum done!\n");
1602 skb->ip_summed = CHECKSUM_UNNECESSARY;
1603 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1604 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1605 /* Unfragmented ipv4 UDP frame. */
1607 (struct iphdr *)((u8 *)addr + hlen);
1608 if (!(iph->frag_off &
1609 htons(IP_MF|IP_OFFSET))) {
1610 skb->ip_summed = CHECKSUM_UNNECESSARY;
1611 netif_printk(qdev, rx_status, KERN_DEBUG,
1613 "UDP checksum done!\n");
1618 skb_record_rx_queue(skb, rx_ring->cq_id);
1619 if (vlan_id != 0xffff)
1620 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
1621 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
1622 napi_gro_receive(napi, skb);
1624 netif_receive_skb(skb);
1627 dev_kfree_skb_any(skb);
1628 put_page(lbq_desc->p.pg_chunk.page);
1631 /* Process an inbound completion from an rx ring. */
1632 static void ql_process_mac_rx_skb(struct ql_adapter *qdev,
1633 struct rx_ring *rx_ring,
1634 struct ib_mac_iocb_rsp *ib_mac_rsp,
1638 struct net_device *ndev = qdev->ndev;
1639 struct sk_buff *skb = NULL;
1640 struct sk_buff *new_skb = NULL;
1641 struct bq_desc *sbq_desc = ql_get_curr_sbuf(rx_ring);
1643 skb = sbq_desc->p.skb;
1644 /* Allocate new_skb and copy */
1645 new_skb = netdev_alloc_skb(qdev->ndev, length + NET_IP_ALIGN);
1646 if (new_skb == NULL) {
1647 rx_ring->rx_dropped++;
1650 skb_reserve(new_skb, NET_IP_ALIGN);
1652 pci_dma_sync_single_for_cpu(qdev->pdev,
1653 dma_unmap_addr(sbq_desc, mapaddr),
1654 dma_unmap_len(sbq_desc, maplen),
1655 PCI_DMA_FROMDEVICE);
1657 memcpy(skb_put(new_skb, length), skb->data, length);
1659 pci_dma_sync_single_for_device(qdev->pdev,
1660 dma_unmap_addr(sbq_desc, mapaddr),
1661 dma_unmap_len(sbq_desc, maplen),
1662 PCI_DMA_FROMDEVICE);
1665 /* Frame error, so drop the packet. */
1666 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1667 ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring);
1668 dev_kfree_skb_any(skb);
1672 /* loopback self test for ethtool */
1673 if (test_bit(QL_SELFTEST, &qdev->flags)) {
1674 ql_check_lb_frame(qdev, skb);
1675 dev_kfree_skb_any(skb);
1679 /* The max framesize filter on this chip is set higher than
1680 * MTU since FCoE uses 2k frames.
1682 if (skb->len > ndev->mtu + ETH_HLEN) {
1683 dev_kfree_skb_any(skb);
1684 rx_ring->rx_dropped++;
1688 prefetch(skb->data);
1689 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1690 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1692 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1693 IB_MAC_IOCB_RSP_M_HASH ? "Hash" :
1694 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1695 IB_MAC_IOCB_RSP_M_REG ? "Registered" :
1696 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1697 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1699 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P)
1700 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1701 "Promiscuous Packet.\n");
1703 rx_ring->rx_packets++;
1704 rx_ring->rx_bytes += skb->len;
1705 skb->protocol = eth_type_trans(skb, ndev);
1706 skb_checksum_none_assert(skb);
1708 /* If rx checksum is on, and there are no
1709 * csum or frame errors.
1711 if ((ndev->features & NETIF_F_RXCSUM) &&
1712 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1714 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1715 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1716 "TCP checksum done!\n");
1717 skb->ip_summed = CHECKSUM_UNNECESSARY;
1718 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1719 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1720 /* Unfragmented ipv4 UDP frame. */
1721 struct iphdr *iph = (struct iphdr *) skb->data;
1722 if (!(iph->frag_off &
1723 htons(IP_MF|IP_OFFSET))) {
1724 skb->ip_summed = CHECKSUM_UNNECESSARY;
1725 netif_printk(qdev, rx_status, KERN_DEBUG,
1727 "UDP checksum done!\n");
1732 skb_record_rx_queue(skb, rx_ring->cq_id);
1733 if (vlan_id != 0xffff)
1734 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
1735 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
1736 napi_gro_receive(&rx_ring->napi, skb);
1738 netif_receive_skb(skb);
1741 static void ql_realign_skb(struct sk_buff *skb, int len)
1743 void *temp_addr = skb->data;
1745 /* Undo the skb_reserve(skb,32) we did before
1746 * giving to hardware, and realign data on
1747 * a 2-byte boundary.
1749 skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1750 skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1751 skb_copy_to_linear_data(skb, temp_addr,
1756 * This function builds an skb for the given inbound
1757 * completion. It will be rewritten for readability in the near
1758 * future, but for not it works well.
1760 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1761 struct rx_ring *rx_ring,
1762 struct ib_mac_iocb_rsp *ib_mac_rsp)
1764 struct bq_desc *lbq_desc;
1765 struct bq_desc *sbq_desc;
1766 struct sk_buff *skb = NULL;
1767 u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1768 u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1769 size_t hlen = ETH_HLEN;
1772 * Handle the header buffer if present.
1774 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1775 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1776 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1777 "Header of %d bytes in small buffer.\n", hdr_len);
1779 * Headers fit nicely into a small buffer.
1781 sbq_desc = ql_get_curr_sbuf(rx_ring);
1782 pci_unmap_single(qdev->pdev,
1783 dma_unmap_addr(sbq_desc, mapaddr),
1784 dma_unmap_len(sbq_desc, maplen),
1785 PCI_DMA_FROMDEVICE);
1786 skb = sbq_desc->p.skb;
1787 ql_realign_skb(skb, hdr_len);
1788 skb_put(skb, hdr_len);
1789 sbq_desc->p.skb = NULL;
1793 * Handle the data buffer(s).
1795 if (unlikely(!length)) { /* Is there data too? */
1796 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1797 "No Data buffer in this packet.\n");
1801 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1802 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1803 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1804 "Headers in small, data of %d bytes in small, combine them.\n",
1807 * Data is less than small buffer size so it's
1808 * stuffed in a small buffer.
1809 * For this case we append the data
1810 * from the "data" small buffer to the "header" small
1813 sbq_desc = ql_get_curr_sbuf(rx_ring);
1814 pci_dma_sync_single_for_cpu(qdev->pdev,
1816 (sbq_desc, mapaddr),
1819 PCI_DMA_FROMDEVICE);
1820 memcpy(skb_put(skb, length),
1821 sbq_desc->p.skb->data, length);
1822 pci_dma_sync_single_for_device(qdev->pdev,
1829 PCI_DMA_FROMDEVICE);
1831 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1832 "%d bytes in a single small buffer.\n",
1834 sbq_desc = ql_get_curr_sbuf(rx_ring);
1835 skb = sbq_desc->p.skb;
1836 ql_realign_skb(skb, length);
1837 skb_put(skb, length);
1838 pci_unmap_single(qdev->pdev,
1839 dma_unmap_addr(sbq_desc,
1841 dma_unmap_len(sbq_desc,
1843 PCI_DMA_FROMDEVICE);
1844 sbq_desc->p.skb = NULL;
1846 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1847 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1848 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1849 "Header in small, %d bytes in large. Chain large to small!\n",
1852 * The data is in a single large buffer. We
1853 * chain it to the header buffer's skb and let
1856 lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1857 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1858 "Chaining page at offset = %d, for %d bytes to skb.\n",
1859 lbq_desc->p.pg_chunk.offset, length);
1860 skb_fill_page_desc(skb, 0, lbq_desc->p.pg_chunk.page,
1861 lbq_desc->p.pg_chunk.offset,
1864 skb->data_len += length;
1865 skb->truesize += length;
1868 * The headers and data are in a single large buffer. We
1869 * copy it to a new skb and let it go. This can happen with
1870 * jumbo mtu on a non-TCP/UDP frame.
1872 lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1873 skb = netdev_alloc_skb(qdev->ndev, length);
1875 netif_printk(qdev, probe, KERN_DEBUG, qdev->ndev,
1876 "No skb available, drop the packet.\n");
1879 pci_unmap_page(qdev->pdev,
1880 dma_unmap_addr(lbq_desc,
1882 dma_unmap_len(lbq_desc, maplen),
1883 PCI_DMA_FROMDEVICE);
1884 skb_reserve(skb, NET_IP_ALIGN);
1885 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1886 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n",
1888 skb_fill_page_desc(skb, 0,
1889 lbq_desc->p.pg_chunk.page,
1890 lbq_desc->p.pg_chunk.offset,
1893 skb->data_len += length;
1894 skb->truesize += length;
1896 ql_update_mac_hdr_len(qdev, ib_mac_rsp,
1897 lbq_desc->p.pg_chunk.va,
1899 __pskb_pull_tail(skb, hlen);
1903 * The data is in a chain of large buffers
1904 * pointed to by a small buffer. We loop
1905 * thru and chain them to the our small header
1907 * frags: There are 18 max frags and our small
1908 * buffer will hold 32 of them. The thing is,
1909 * we'll use 3 max for our 9000 byte jumbo
1910 * frames. If the MTU goes up we could
1911 * eventually be in trouble.
1914 sbq_desc = ql_get_curr_sbuf(rx_ring);
1915 pci_unmap_single(qdev->pdev,
1916 dma_unmap_addr(sbq_desc, mapaddr),
1917 dma_unmap_len(sbq_desc, maplen),
1918 PCI_DMA_FROMDEVICE);
1919 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1921 * This is an non TCP/UDP IP frame, so
1922 * the headers aren't split into a small
1923 * buffer. We have to use the small buffer
1924 * that contains our sg list as our skb to
1925 * send upstairs. Copy the sg list here to
1926 * a local buffer and use it to find the
1929 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1930 "%d bytes of headers & data in chain of large.\n",
1932 skb = sbq_desc->p.skb;
1933 sbq_desc->p.skb = NULL;
1934 skb_reserve(skb, NET_IP_ALIGN);
1937 lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
1938 size = (length < rx_ring->lbq_buf_size) ? length :
1939 rx_ring->lbq_buf_size;
1941 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1942 "Adding page %d to skb for %d bytes.\n",
1944 skb_fill_page_desc(skb, i,
1945 lbq_desc->p.pg_chunk.page,
1946 lbq_desc->p.pg_chunk.offset,
1949 skb->data_len += size;
1950 skb->truesize += size;
1953 } while (length > 0);
1954 ql_update_mac_hdr_len(qdev, ib_mac_rsp, lbq_desc->p.pg_chunk.va,
1956 __pskb_pull_tail(skb, hlen);
1961 /* Process an inbound completion from an rx ring. */
1962 static void ql_process_mac_split_rx_intr(struct ql_adapter *qdev,
1963 struct rx_ring *rx_ring,
1964 struct ib_mac_iocb_rsp *ib_mac_rsp,
1967 struct net_device *ndev = qdev->ndev;
1968 struct sk_buff *skb = NULL;
1970 QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1972 skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1973 if (unlikely(!skb)) {
1974 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
1975 "No skb available, drop packet.\n");
1976 rx_ring->rx_dropped++;
1980 /* Frame error, so drop the packet. */
1981 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1982 ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring);
1983 dev_kfree_skb_any(skb);
1987 /* The max framesize filter on this chip is set higher than
1988 * MTU since FCoE uses 2k frames.
1990 if (skb->len > ndev->mtu + ETH_HLEN) {
1991 dev_kfree_skb_any(skb);
1992 rx_ring->rx_dropped++;
1996 /* loopback self test for ethtool */
1997 if (test_bit(QL_SELFTEST, &qdev->flags)) {
1998 ql_check_lb_frame(qdev, skb);
1999 dev_kfree_skb_any(skb);
2003 prefetch(skb->data);
2004 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
2005 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, "%s Multicast.\n",
2006 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
2007 IB_MAC_IOCB_RSP_M_HASH ? "Hash" :
2008 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
2009 IB_MAC_IOCB_RSP_M_REG ? "Registered" :
2010 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
2011 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
2012 rx_ring->rx_multicast++;
2014 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
2015 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2016 "Promiscuous Packet.\n");
2019 skb->protocol = eth_type_trans(skb, ndev);
2020 skb_checksum_none_assert(skb);
2022 /* If rx checksum is on, and there are no
2023 * csum or frame errors.
2025 if ((ndev->features & NETIF_F_RXCSUM) &&
2026 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
2028 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
2029 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2030 "TCP checksum done!\n");
2031 skb->ip_summed = CHECKSUM_UNNECESSARY;
2032 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
2033 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
2034 /* Unfragmented ipv4 UDP frame. */
2035 struct iphdr *iph = (struct iphdr *) skb->data;
2036 if (!(iph->frag_off &
2037 htons(IP_MF|IP_OFFSET))) {
2038 skb->ip_summed = CHECKSUM_UNNECESSARY;
2039 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2040 "TCP checksum done!\n");
2045 rx_ring->rx_packets++;
2046 rx_ring->rx_bytes += skb->len;
2047 skb_record_rx_queue(skb, rx_ring->cq_id);
2048 if (vlan_id != 0xffff)
2049 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
2050 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
2051 napi_gro_receive(&rx_ring->napi, skb);
2053 netif_receive_skb(skb);
2056 /* Process an inbound completion from an rx ring. */
2057 static unsigned long ql_process_mac_rx_intr(struct ql_adapter *qdev,
2058 struct rx_ring *rx_ring,
2059 struct ib_mac_iocb_rsp *ib_mac_rsp)
2061 u32 length = le32_to_cpu(ib_mac_rsp->data_len);
2062 u16 vlan_id = ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
2063 (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)) ?
2064 ((le16_to_cpu(ib_mac_rsp->vlan_id) &
2065 IB_MAC_IOCB_RSP_VLAN_MASK)) : 0xffff;
2067 QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
2069 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV) {
2070 /* The data and headers are split into
2073 ql_process_mac_split_rx_intr(qdev, rx_ring, ib_mac_rsp,
2075 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
2076 /* The data fit in a single small buffer.
2077 * Allocate a new skb, copy the data and
2078 * return the buffer to the free pool.
2080 ql_process_mac_rx_skb(qdev, rx_ring, ib_mac_rsp,
2082 } else if ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) &&
2083 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK) &&
2084 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T)) {
2085 /* TCP packet in a page chunk that's been checksummed.
2086 * Tack it on to our GRO skb and let it go.
2088 ql_process_mac_rx_gro_page(qdev, rx_ring, ib_mac_rsp,
2090 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
2091 /* Non-TCP packet in a page chunk. Allocate an
2092 * skb, tack it on frags, and send it up.
2094 ql_process_mac_rx_page(qdev, rx_ring, ib_mac_rsp,
2097 /* Non-TCP/UDP large frames that span multiple buffers
2098 * can be processed corrrectly by the split frame logic.
2100 ql_process_mac_split_rx_intr(qdev, rx_ring, ib_mac_rsp,
2104 return (unsigned long)length;
2107 /* Process an outbound completion from an rx ring. */
2108 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
2109 struct ob_mac_iocb_rsp *mac_rsp)
2111 struct tx_ring *tx_ring;
2112 struct tx_ring_desc *tx_ring_desc;
2114 QL_DUMP_OB_MAC_RSP(mac_rsp);
2115 tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
2116 tx_ring_desc = &tx_ring->q[mac_rsp->tid];
2117 ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
2118 tx_ring->tx_bytes += (tx_ring_desc->skb)->len;
2119 tx_ring->tx_packets++;
2120 dev_kfree_skb(tx_ring_desc->skb);
2121 tx_ring_desc->skb = NULL;
2123 if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
2126 OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
2127 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
2128 netif_warn(qdev, tx_done, qdev->ndev,
2129 "Total descriptor length did not match transfer length.\n");
2131 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
2132 netif_warn(qdev, tx_done, qdev->ndev,
2133 "Frame too short to be valid, not sent.\n");
2135 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
2136 netif_warn(qdev, tx_done, qdev->ndev,
2137 "Frame too long, but sent anyway.\n");
2139 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
2140 netif_warn(qdev, tx_done, qdev->ndev,
2141 "PCI backplane error. Frame not sent.\n");
2144 atomic_inc(&tx_ring->tx_count);
2147 /* Fire up a handler to reset the MPI processor. */
2148 void ql_queue_fw_error(struct ql_adapter *qdev)
2151 queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
2154 void ql_queue_asic_error(struct ql_adapter *qdev)
2157 ql_disable_interrupts(qdev);
2158 /* Clear adapter up bit to signal the recovery
2159 * process that it shouldn't kill the reset worker
2162 clear_bit(QL_ADAPTER_UP, &qdev->flags);
2163 /* Set asic recovery bit to indicate reset process that we are
2164 * in fatal error recovery process rather than normal close
2166 set_bit(QL_ASIC_RECOVERY, &qdev->flags);
2167 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
2170 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
2171 struct ib_ae_iocb_rsp *ib_ae_rsp)
2173 switch (ib_ae_rsp->event) {
2174 case MGMT_ERR_EVENT:
2175 netif_err(qdev, rx_err, qdev->ndev,
2176 "Management Processor Fatal Error.\n");
2177 ql_queue_fw_error(qdev);
2180 case CAM_LOOKUP_ERR_EVENT:
2181 netdev_err(qdev->ndev, "Multiple CAM hits lookup occurred.\n");
2182 netdev_err(qdev->ndev, "This event shouldn't occur.\n");
2183 ql_queue_asic_error(qdev);
2186 case SOFT_ECC_ERROR_EVENT:
2187 netdev_err(qdev->ndev, "Soft ECC error detected.\n");
2188 ql_queue_asic_error(qdev);
2191 case PCI_ERR_ANON_BUF_RD:
2192 netdev_err(qdev->ndev, "PCI error occurred when reading "
2193 "anonymous buffers from rx_ring %d.\n",
2195 ql_queue_asic_error(qdev);
2199 netif_err(qdev, drv, qdev->ndev, "Unexpected event %d.\n",
2201 ql_queue_asic_error(qdev);
2206 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
2208 struct ql_adapter *qdev = rx_ring->qdev;
2209 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
2210 struct ob_mac_iocb_rsp *net_rsp = NULL;
2213 struct tx_ring *tx_ring;
2214 /* While there are entries in the completion queue. */
2215 while (prod != rx_ring->cnsmr_idx) {
2217 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2218 "cq_id = %d, prod = %d, cnsmr = %d.\n.",
2219 rx_ring->cq_id, prod, rx_ring->cnsmr_idx);
2221 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
2223 switch (net_rsp->opcode) {
2225 case OPCODE_OB_MAC_TSO_IOCB:
2226 case OPCODE_OB_MAC_IOCB:
2227 ql_process_mac_tx_intr(qdev, net_rsp);
2230 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2231 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
2235 ql_update_cq(rx_ring);
2236 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
2240 ql_write_cq_idx(rx_ring);
2241 tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
2242 if (__netif_subqueue_stopped(qdev->ndev, tx_ring->wq_id)) {
2243 if ((atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
2245 * The queue got stopped because the tx_ring was full.
2246 * Wake it up, because it's now at least 25% empty.
2248 netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
2254 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
2256 struct ql_adapter *qdev = rx_ring->qdev;
2257 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
2258 struct ql_net_rsp_iocb *net_rsp;
2261 /* While there are entries in the completion queue. */
2262 while (prod != rx_ring->cnsmr_idx) {
2264 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2265 "cq_id = %d, prod = %d, cnsmr = %d.\n.",
2266 rx_ring->cq_id, prod, rx_ring->cnsmr_idx);
2268 net_rsp = rx_ring->curr_entry;
2270 switch (net_rsp->opcode) {
2271 case OPCODE_IB_MAC_IOCB:
2272 ql_process_mac_rx_intr(qdev, rx_ring,
2273 (struct ib_mac_iocb_rsp *)
2277 case OPCODE_IB_AE_IOCB:
2278 ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
2282 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2283 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
2288 ql_update_cq(rx_ring);
2289 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
2290 if (count == budget)
2293 ql_update_buffer_queues(qdev, rx_ring);
2294 ql_write_cq_idx(rx_ring);
2298 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
2300 struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
2301 struct ql_adapter *qdev = rx_ring->qdev;
2302 struct rx_ring *trx_ring;
2303 int i, work_done = 0;
2304 struct intr_context *ctx = &qdev->intr_context[rx_ring->cq_id];
2306 netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
2307 "Enter, NAPI POLL cq_id = %d.\n", rx_ring->cq_id);
2309 /* Service the TX rings first. They start
2310 * right after the RSS rings. */
2311 for (i = qdev->rss_ring_count; i < qdev->rx_ring_count; i++) {
2312 trx_ring = &qdev->rx_ring[i];
2313 /* If this TX completion ring belongs to this vector and
2314 * it's not empty then service it.
2316 if ((ctx->irq_mask & (1 << trx_ring->cq_id)) &&
2317 (ql_read_sh_reg(trx_ring->prod_idx_sh_reg) !=
2318 trx_ring->cnsmr_idx)) {
2319 netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev,
2320 "%s: Servicing TX completion ring %d.\n",
2321 __func__, trx_ring->cq_id);
2322 ql_clean_outbound_rx_ring(trx_ring);
2327 * Now service the RSS ring if it's active.
2329 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
2330 rx_ring->cnsmr_idx) {
2331 netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev,
2332 "%s: Servicing RX completion ring %d.\n",
2333 __func__, rx_ring->cq_id);
2334 work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
2337 if (work_done < budget) {
2338 napi_complete(napi);
2339 ql_enable_completion_interrupt(qdev, rx_ring->irq);
2344 static void qlge_vlan_mode(struct net_device *ndev, netdev_features_t features)
2346 struct ql_adapter *qdev = netdev_priv(ndev);
2348 if (features & NETIF_F_HW_VLAN_CTAG_RX) {
2349 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
2350 NIC_RCV_CFG_VLAN_MATCH_AND_NON);
2352 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
2357 * qlge_update_hw_vlan_features - helper routine to reinitialize the adapter
2358 * based on the features to enable/disable hardware vlan accel
2360 static int qlge_update_hw_vlan_features(struct net_device *ndev,
2361 netdev_features_t features)
2363 struct ql_adapter *qdev = netdev_priv(ndev);
2365 bool need_restart = netif_running(ndev);
2368 status = ql_adapter_down(qdev);
2370 netif_err(qdev, link, qdev->ndev,
2371 "Failed to bring down the adapter\n");
2376 /* update the features with resent change */
2377 ndev->features = features;
2380 status = ql_adapter_up(qdev);
2382 netif_err(qdev, link, qdev->ndev,
2383 "Failed to bring up the adapter\n");
2391 static int qlge_set_features(struct net_device *ndev,
2392 netdev_features_t features)
2394 netdev_features_t changed = ndev->features ^ features;
2397 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2398 /* Update the behavior of vlan accel in the adapter */
2399 err = qlge_update_hw_vlan_features(ndev, features);
2403 qlge_vlan_mode(ndev, features);
2409 static int __qlge_vlan_rx_add_vid(struct ql_adapter *qdev, u16 vid)
2411 u32 enable_bit = MAC_ADDR_E;
2414 err = ql_set_mac_addr_reg(qdev, (u8 *) &enable_bit,
2415 MAC_ADDR_TYPE_VLAN, vid);
2417 netif_err(qdev, ifup, qdev->ndev,
2418 "Failed to init vlan address.\n");
2422 static int qlge_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
2424 struct ql_adapter *qdev = netdev_priv(ndev);
2428 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2432 err = __qlge_vlan_rx_add_vid(qdev, vid);
2433 set_bit(vid, qdev->active_vlans);
2435 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
2440 static int __qlge_vlan_rx_kill_vid(struct ql_adapter *qdev, u16 vid)
2445 err = ql_set_mac_addr_reg(qdev, (u8 *) &enable_bit,
2446 MAC_ADDR_TYPE_VLAN, vid);
2448 netif_err(qdev, ifup, qdev->ndev,
2449 "Failed to clear vlan address.\n");
2453 static int qlge_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
2455 struct ql_adapter *qdev = netdev_priv(ndev);
2459 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2463 err = __qlge_vlan_rx_kill_vid(qdev, vid);
2464 clear_bit(vid, qdev->active_vlans);
2466 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
2471 static void qlge_restore_vlan(struct ql_adapter *qdev)
2476 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2480 for_each_set_bit(vid, qdev->active_vlans, VLAN_N_VID)
2481 __qlge_vlan_rx_add_vid(qdev, vid);
2483 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
2486 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
2487 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
2489 struct rx_ring *rx_ring = dev_id;
2490 napi_schedule(&rx_ring->napi);
2494 /* This handles a fatal error, MPI activity, and the default
2495 * rx_ring in an MSI-X multiple vector environment.
2496 * In MSI/Legacy environment it also process the rest of
2499 static irqreturn_t qlge_isr(int irq, void *dev_id)
2501 struct rx_ring *rx_ring = dev_id;
2502 struct ql_adapter *qdev = rx_ring->qdev;
2503 struct intr_context *intr_context = &qdev->intr_context[0];
2507 spin_lock(&qdev->hw_lock);
2508 if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
2509 netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev,
2510 "Shared Interrupt, Not ours!\n");
2511 spin_unlock(&qdev->hw_lock);
2514 spin_unlock(&qdev->hw_lock);
2516 var = ql_disable_completion_interrupt(qdev, intr_context->intr);
2519 * Check for fatal error.
2522 ql_queue_asic_error(qdev);
2523 netdev_err(qdev->ndev, "Got fatal error, STS = %x.\n", var);
2524 var = ql_read32(qdev, ERR_STS);
2525 netdev_err(qdev->ndev, "Resetting chip. "
2526 "Error Status Register = 0x%x\n", var);
2531 * Check MPI processor activity.
2533 if ((var & STS_PI) &&
2534 (ql_read32(qdev, INTR_MASK) & INTR_MASK_PI)) {
2536 * We've got an async event or mailbox completion.
2537 * Handle it and clear the source of the interrupt.
2539 netif_err(qdev, intr, qdev->ndev,
2540 "Got MPI processor interrupt.\n");
2541 ql_disable_completion_interrupt(qdev, intr_context->intr);
2542 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
2543 queue_delayed_work_on(smp_processor_id(),
2544 qdev->workqueue, &qdev->mpi_work, 0);
2549 * Get the bit-mask that shows the active queues for this
2550 * pass. Compare it to the queues that this irq services
2551 * and call napi if there's a match.
2553 var = ql_read32(qdev, ISR1);
2554 if (var & intr_context->irq_mask) {
2555 netif_info(qdev, intr, qdev->ndev,
2556 "Waking handler for rx_ring[0].\n");
2557 ql_disable_completion_interrupt(qdev, intr_context->intr);
2558 napi_schedule(&rx_ring->napi);
2561 ql_enable_completion_interrupt(qdev, intr_context->intr);
2562 return work_done ? IRQ_HANDLED : IRQ_NONE;
2565 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2568 if (skb_is_gso(skb)) {
2570 __be16 l3_proto = vlan_get_protocol(skb);
2572 err = skb_cow_head(skb, 0);
2576 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2577 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
2578 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2579 mac_iocb_ptr->total_hdrs_len =
2580 cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
2581 mac_iocb_ptr->net_trans_offset =
2582 cpu_to_le16(skb_network_offset(skb) |
2583 skb_transport_offset(skb)
2584 << OB_MAC_TRANSPORT_HDR_SHIFT);
2585 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
2586 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
2587 if (likely(l3_proto == htons(ETH_P_IP))) {
2588 struct iphdr *iph = ip_hdr(skb);
2590 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2591 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2595 } else if (l3_proto == htons(ETH_P_IPV6)) {
2596 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
2597 tcp_hdr(skb)->check =
2598 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2599 &ipv6_hdr(skb)->daddr,
2607 static void ql_hw_csum_setup(struct sk_buff *skb,
2608 struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2611 struct iphdr *iph = ip_hdr(skb);
2613 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2614 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2615 mac_iocb_ptr->net_trans_offset =
2616 cpu_to_le16(skb_network_offset(skb) |
2617 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
2619 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2620 len = (ntohs(iph->tot_len) - (iph->ihl << 2));
2621 if (likely(iph->protocol == IPPROTO_TCP)) {
2622 check = &(tcp_hdr(skb)->check);
2623 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
2624 mac_iocb_ptr->total_hdrs_len =
2625 cpu_to_le16(skb_transport_offset(skb) +
2626 (tcp_hdr(skb)->doff << 2));
2628 check = &(udp_hdr(skb)->check);
2629 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
2630 mac_iocb_ptr->total_hdrs_len =
2631 cpu_to_le16(skb_transport_offset(skb) +
2632 sizeof(struct udphdr));
2634 *check = ~csum_tcpudp_magic(iph->saddr,
2635 iph->daddr, len, iph->protocol, 0);
2638 static netdev_tx_t qlge_send(struct sk_buff *skb, struct net_device *ndev)
2640 struct tx_ring_desc *tx_ring_desc;
2641 struct ob_mac_iocb_req *mac_iocb_ptr;
2642 struct ql_adapter *qdev = netdev_priv(ndev);
2644 struct tx_ring *tx_ring;
2645 u32 tx_ring_idx = (u32) skb->queue_mapping;
2647 tx_ring = &qdev->tx_ring[tx_ring_idx];
2649 if (skb_padto(skb, ETH_ZLEN))
2650 return NETDEV_TX_OK;
2652 if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2653 netif_info(qdev, tx_queued, qdev->ndev,
2654 "%s: BUG! shutting down tx queue %d due to lack of resources.\n",
2655 __func__, tx_ring_idx);
2656 netif_stop_subqueue(ndev, tx_ring->wq_id);
2657 tx_ring->tx_errors++;
2658 return NETDEV_TX_BUSY;
2660 tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
2661 mac_iocb_ptr = tx_ring_desc->queue_entry;
2662 memset((void *)mac_iocb_ptr, 0, sizeof(*mac_iocb_ptr));
2664 mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
2665 mac_iocb_ptr->tid = tx_ring_desc->index;
2666 /* We use the upper 32-bits to store the tx queue for this IO.
2667 * When we get the completion we can use it to establish the context.
2669 mac_iocb_ptr->txq_idx = tx_ring_idx;
2670 tx_ring_desc->skb = skb;
2672 mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
2674 if (skb_vlan_tag_present(skb)) {
2675 netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev,
2676 "Adding a vlan tag %d.\n", skb_vlan_tag_get(skb));
2677 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
2678 mac_iocb_ptr->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb));
2680 tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2682 dev_kfree_skb_any(skb);
2683 return NETDEV_TX_OK;
2684 } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2685 ql_hw_csum_setup(skb,
2686 (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2688 if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2690 netif_err(qdev, tx_queued, qdev->ndev,
2691 "Could not map the segments.\n");
2692 tx_ring->tx_errors++;
2693 return NETDEV_TX_BUSY;
2695 QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2696 tx_ring->prod_idx++;
2697 if (tx_ring->prod_idx == tx_ring->wq_len)
2698 tx_ring->prod_idx = 0;
2701 ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
2702 netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev,
2703 "tx queued, slot %d, len %d\n",
2704 tx_ring->prod_idx, skb->len);
2706 atomic_dec(&tx_ring->tx_count);
2708 if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2709 netif_stop_subqueue(ndev, tx_ring->wq_id);
2710 if ((atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
2712 * The queue got stopped because the tx_ring was full.
2713 * Wake it up, because it's now at least 25% empty.
2715 netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
2717 return NETDEV_TX_OK;
2721 static void ql_free_shadow_space(struct ql_adapter *qdev)
2723 if (qdev->rx_ring_shadow_reg_area) {
2724 pci_free_consistent(qdev->pdev,
2726 qdev->rx_ring_shadow_reg_area,
2727 qdev->rx_ring_shadow_reg_dma);
2728 qdev->rx_ring_shadow_reg_area = NULL;
2730 if (qdev->tx_ring_shadow_reg_area) {
2731 pci_free_consistent(qdev->pdev,
2733 qdev->tx_ring_shadow_reg_area,
2734 qdev->tx_ring_shadow_reg_dma);
2735 qdev->tx_ring_shadow_reg_area = NULL;
2739 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2741 qdev->rx_ring_shadow_reg_area =
2742 pci_zalloc_consistent(qdev->pdev, PAGE_SIZE,
2743 &qdev->rx_ring_shadow_reg_dma);
2744 if (qdev->rx_ring_shadow_reg_area == NULL) {
2745 netif_err(qdev, ifup, qdev->ndev,
2746 "Allocation of RX shadow space failed.\n");
2750 qdev->tx_ring_shadow_reg_area =
2751 pci_zalloc_consistent(qdev->pdev, PAGE_SIZE,
2752 &qdev->tx_ring_shadow_reg_dma);
2753 if (qdev->tx_ring_shadow_reg_area == NULL) {
2754 netif_err(qdev, ifup, qdev->ndev,
2755 "Allocation of TX shadow space failed.\n");
2756 goto err_wqp_sh_area;
2761 pci_free_consistent(qdev->pdev,
2763 qdev->rx_ring_shadow_reg_area,
2764 qdev->rx_ring_shadow_reg_dma);
2768 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2770 struct tx_ring_desc *tx_ring_desc;
2772 struct ob_mac_iocb_req *mac_iocb_ptr;
2774 mac_iocb_ptr = tx_ring->wq_base;
2775 tx_ring_desc = tx_ring->q;
2776 for (i = 0; i < tx_ring->wq_len; i++) {
2777 tx_ring_desc->index = i;
2778 tx_ring_desc->skb = NULL;
2779 tx_ring_desc->queue_entry = mac_iocb_ptr;
2783 atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2786 static void ql_free_tx_resources(struct ql_adapter *qdev,
2787 struct tx_ring *tx_ring)
2789 if (tx_ring->wq_base) {
2790 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2791 tx_ring->wq_base, tx_ring->wq_base_dma);
2792 tx_ring->wq_base = NULL;
2798 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2799 struct tx_ring *tx_ring)
2802 pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2803 &tx_ring->wq_base_dma);
2805 if ((tx_ring->wq_base == NULL) ||
2806 tx_ring->wq_base_dma & WQ_ADDR_ALIGN)
2810 kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2811 if (tx_ring->q == NULL)
2816 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2817 tx_ring->wq_base, tx_ring->wq_base_dma);
2818 tx_ring->wq_base = NULL;
2820 netif_err(qdev, ifup, qdev->ndev, "tx_ring alloc failed.\n");
2824 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2826 struct bq_desc *lbq_desc;
2828 uint32_t curr_idx, clean_idx;
2830 curr_idx = rx_ring->lbq_curr_idx;
2831 clean_idx = rx_ring->lbq_clean_idx;
2832 while (curr_idx != clean_idx) {
2833 lbq_desc = &rx_ring->lbq[curr_idx];
2835 if (lbq_desc->p.pg_chunk.last_flag) {
2836 pci_unmap_page(qdev->pdev,
2837 lbq_desc->p.pg_chunk.map,
2838 ql_lbq_block_size(qdev),
2839 PCI_DMA_FROMDEVICE);
2840 lbq_desc->p.pg_chunk.last_flag = 0;
2843 put_page(lbq_desc->p.pg_chunk.page);
2844 lbq_desc->p.pg_chunk.page = NULL;
2846 if (++curr_idx == rx_ring->lbq_len)
2850 if (rx_ring->pg_chunk.page) {
2851 pci_unmap_page(qdev->pdev, rx_ring->pg_chunk.map,
2852 ql_lbq_block_size(qdev), PCI_DMA_FROMDEVICE);
2853 put_page(rx_ring->pg_chunk.page);
2854 rx_ring->pg_chunk.page = NULL;
2858 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2861 struct bq_desc *sbq_desc;
2863 for (i = 0; i < rx_ring->sbq_len; i++) {
2864 sbq_desc = &rx_ring->sbq[i];
2865 if (sbq_desc == NULL) {
2866 netif_err(qdev, ifup, qdev->ndev,
2867 "sbq_desc %d is NULL.\n", i);
2870 if (sbq_desc->p.skb) {
2871 pci_unmap_single(qdev->pdev,
2872 dma_unmap_addr(sbq_desc, mapaddr),
2873 dma_unmap_len(sbq_desc, maplen),
2874 PCI_DMA_FROMDEVICE);
2875 dev_kfree_skb(sbq_desc->p.skb);
2876 sbq_desc->p.skb = NULL;
2881 /* Free all large and small rx buffers associated
2882 * with the completion queues for this device.
2884 static void ql_free_rx_buffers(struct ql_adapter *qdev)
2887 struct rx_ring *rx_ring;
2889 for (i = 0; i < qdev->rx_ring_count; i++) {
2890 rx_ring = &qdev->rx_ring[i];
2892 ql_free_lbq_buffers(qdev, rx_ring);
2894 ql_free_sbq_buffers(qdev, rx_ring);
2898 static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2900 struct rx_ring *rx_ring;
2903 for (i = 0; i < qdev->rx_ring_count; i++) {
2904 rx_ring = &qdev->rx_ring[i];
2905 if (rx_ring->type != TX_Q)
2906 ql_update_buffer_queues(qdev, rx_ring);
2910 static void ql_init_lbq_ring(struct ql_adapter *qdev,
2911 struct rx_ring *rx_ring)
2914 struct bq_desc *lbq_desc;
2915 __le64 *bq = rx_ring->lbq_base;
2917 memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2918 for (i = 0; i < rx_ring->lbq_len; i++) {
2919 lbq_desc = &rx_ring->lbq[i];
2920 memset(lbq_desc, 0, sizeof(*lbq_desc));
2921 lbq_desc->index = i;
2922 lbq_desc->addr = bq;
2927 static void ql_init_sbq_ring(struct ql_adapter *qdev,
2928 struct rx_ring *rx_ring)
2931 struct bq_desc *sbq_desc;
2932 __le64 *bq = rx_ring->sbq_base;
2934 memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
2935 for (i = 0; i < rx_ring->sbq_len; i++) {
2936 sbq_desc = &rx_ring->sbq[i];
2937 memset(sbq_desc, 0, sizeof(*sbq_desc));
2938 sbq_desc->index = i;
2939 sbq_desc->addr = bq;
2944 static void ql_free_rx_resources(struct ql_adapter *qdev,
2945 struct rx_ring *rx_ring)
2947 /* Free the small buffer queue. */
2948 if (rx_ring->sbq_base) {
2949 pci_free_consistent(qdev->pdev,
2951 rx_ring->sbq_base, rx_ring->sbq_base_dma);
2952 rx_ring->sbq_base = NULL;
2955 /* Free the small buffer queue control blocks. */
2956 kfree(rx_ring->sbq);
2957 rx_ring->sbq = NULL;
2959 /* Free the large buffer queue. */
2960 if (rx_ring->lbq_base) {
2961 pci_free_consistent(qdev->pdev,
2963 rx_ring->lbq_base, rx_ring->lbq_base_dma);
2964 rx_ring->lbq_base = NULL;
2967 /* Free the large buffer queue control blocks. */
2968 kfree(rx_ring->lbq);
2969 rx_ring->lbq = NULL;
2971 /* Free the rx queue. */
2972 if (rx_ring->cq_base) {
2973 pci_free_consistent(qdev->pdev,
2975 rx_ring->cq_base, rx_ring->cq_base_dma);
2976 rx_ring->cq_base = NULL;
2980 /* Allocate queues and buffers for this completions queue based
2981 * on the values in the parameter structure. */
2982 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2983 struct rx_ring *rx_ring)
2987 * Allocate the completion queue for this rx_ring.
2990 pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2991 &rx_ring->cq_base_dma);
2993 if (rx_ring->cq_base == NULL) {
2994 netif_err(qdev, ifup, qdev->ndev, "rx_ring alloc failed.\n");
2998 if (rx_ring->sbq_len) {
3000 * Allocate small buffer queue.
3003 pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
3004 &rx_ring->sbq_base_dma);
3006 if (rx_ring->sbq_base == NULL) {
3007 netif_err(qdev, ifup, qdev->ndev,
3008 "Small buffer queue allocation failed.\n");
3013 * Allocate small buffer queue control blocks.
3015 rx_ring->sbq = kmalloc_array(rx_ring->sbq_len,
3016 sizeof(struct bq_desc),
3018 if (rx_ring->sbq == NULL)
3021 ql_init_sbq_ring(qdev, rx_ring);
3024 if (rx_ring->lbq_len) {
3026 * Allocate large buffer queue.
3029 pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
3030 &rx_ring->lbq_base_dma);
3032 if (rx_ring->lbq_base == NULL) {
3033 netif_err(qdev, ifup, qdev->ndev,
3034 "Large buffer queue allocation failed.\n");
3038 * Allocate large buffer queue control blocks.
3040 rx_ring->lbq = kmalloc_array(rx_ring->lbq_len,
3041 sizeof(struct bq_desc),
3043 if (rx_ring->lbq == NULL)
3046 ql_init_lbq_ring(qdev, rx_ring);
3052 ql_free_rx_resources(qdev, rx_ring);
3056 static void ql_tx_ring_clean(struct ql_adapter *qdev)
3058 struct tx_ring *tx_ring;
3059 struct tx_ring_desc *tx_ring_desc;
3063 * Loop through all queues and free
3066 for (j = 0; j < qdev->tx_ring_count; j++) {
3067 tx_ring = &qdev->tx_ring[j];
3068 for (i = 0; i < tx_ring->wq_len; i++) {
3069 tx_ring_desc = &tx_ring->q[i];
3070 if (tx_ring_desc && tx_ring_desc->skb) {
3071 netif_err(qdev, ifdown, qdev->ndev,
3072 "Freeing lost SKB %p, from queue %d, index %d.\n",
3073 tx_ring_desc->skb, j,
3074 tx_ring_desc->index);
3075 ql_unmap_send(qdev, tx_ring_desc,
3076 tx_ring_desc->map_cnt);
3077 dev_kfree_skb(tx_ring_desc->skb);
3078 tx_ring_desc->skb = NULL;
3084 static void ql_free_mem_resources(struct ql_adapter *qdev)
3088 for (i = 0; i < qdev->tx_ring_count; i++)
3089 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
3090 for (i = 0; i < qdev->rx_ring_count; i++)
3091 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
3092 ql_free_shadow_space(qdev);
3095 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
3099 /* Allocate space for our shadow registers and such. */
3100 if (ql_alloc_shadow_space(qdev))
3103 for (i = 0; i < qdev->rx_ring_count; i++) {
3104 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
3105 netif_err(qdev, ifup, qdev->ndev,
3106 "RX resource allocation failed.\n");
3110 /* Allocate tx queue resources */
3111 for (i = 0; i < qdev->tx_ring_count; i++) {
3112 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
3113 netif_err(qdev, ifup, qdev->ndev,
3114 "TX resource allocation failed.\n");
3121 ql_free_mem_resources(qdev);
3125 /* Set up the rx ring control block and pass it to the chip.
3126 * The control block is defined as
3127 * "Completion Queue Initialization Control Block", or cqicb.
3129 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
3131 struct cqicb *cqicb = &rx_ring->cqicb;
3132 void *shadow_reg = qdev->rx_ring_shadow_reg_area +
3133 (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
3134 u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
3135 (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
3136 void __iomem *doorbell_area =
3137 qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
3141 __le64 *base_indirect_ptr;
3144 /* Set up the shadow registers for this ring. */
3145 rx_ring->prod_idx_sh_reg = shadow_reg;
3146 rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
3147 *rx_ring->prod_idx_sh_reg = 0;
3148 shadow_reg += sizeof(u64);
3149 shadow_reg_dma += sizeof(u64);
3150 rx_ring->lbq_base_indirect = shadow_reg;
3151 rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
3152 shadow_reg += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
3153 shadow_reg_dma += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
3154 rx_ring->sbq_base_indirect = shadow_reg;
3155 rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
3157 /* PCI doorbell mem area + 0x00 for consumer index register */
3158 rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
3159 rx_ring->cnsmr_idx = 0;
3160 rx_ring->curr_entry = rx_ring->cq_base;
3162 /* PCI doorbell mem area + 0x04 for valid register */
3163 rx_ring->valid_db_reg = doorbell_area + 0x04;
3165 /* PCI doorbell mem area + 0x18 for large buffer consumer */
3166 rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
3168 /* PCI doorbell mem area + 0x1c */
3169 rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
3171 memset((void *)cqicb, 0, sizeof(struct cqicb));
3172 cqicb->msix_vect = rx_ring->irq;
3174 bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
3175 cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
3177 cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
3179 cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
3182 * Set up the control block load flags.
3184 cqicb->flags = FLAGS_LC | /* Load queue base address */
3185 FLAGS_LV | /* Load MSI-X vector */
3186 FLAGS_LI; /* Load irq delay values */
3187 if (rx_ring->lbq_len) {
3188 cqicb->flags |= FLAGS_LL; /* Load lbq values */
3189 tmp = (u64)rx_ring->lbq_base_dma;
3190 base_indirect_ptr = rx_ring->lbq_base_indirect;
3193 *base_indirect_ptr = cpu_to_le64(tmp);
3194 tmp += DB_PAGE_SIZE;
3195 base_indirect_ptr++;
3197 } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
3199 cpu_to_le64(rx_ring->lbq_base_indirect_dma);
3200 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
3201 (u16) rx_ring->lbq_buf_size;
3202 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
3203 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
3204 (u16) rx_ring->lbq_len;
3205 cqicb->lbq_len = cpu_to_le16(bq_len);
3206 rx_ring->lbq_prod_idx = 0;
3207 rx_ring->lbq_curr_idx = 0;
3208 rx_ring->lbq_clean_idx = 0;
3209 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
3211 if (rx_ring->sbq_len) {
3212 cqicb->flags |= FLAGS_LS; /* Load sbq values */
3213 tmp = (u64)rx_ring->sbq_base_dma;
3214 base_indirect_ptr = rx_ring->sbq_base_indirect;
3217 *base_indirect_ptr = cpu_to_le64(tmp);
3218 tmp += DB_PAGE_SIZE;
3219 base_indirect_ptr++;
3221 } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->sbq_len));
3223 cpu_to_le64(rx_ring->sbq_base_indirect_dma);
3224 cqicb->sbq_buf_size =
3225 cpu_to_le16((u16)(rx_ring->sbq_buf_size));
3226 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
3227 (u16) rx_ring->sbq_len;
3228 cqicb->sbq_len = cpu_to_le16(bq_len);
3229 rx_ring->sbq_prod_idx = 0;
3230 rx_ring->sbq_curr_idx = 0;
3231 rx_ring->sbq_clean_idx = 0;
3232 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
3234 switch (rx_ring->type) {
3236 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
3237 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
3240 /* Inbound completion handling rx_rings run in
3241 * separate NAPI contexts.
3243 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
3245 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
3246 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
3249 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3250 "Invalid rx_ring->type = %d.\n", rx_ring->type);
3252 err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
3253 CFG_LCQ, rx_ring->cq_id);
3255 netif_err(qdev, ifup, qdev->ndev, "Failed to load CQICB.\n");
3261 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
3263 struct wqicb *wqicb = (struct wqicb *)tx_ring;
3264 void __iomem *doorbell_area =
3265 qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
3266 void *shadow_reg = qdev->tx_ring_shadow_reg_area +
3267 (tx_ring->wq_id * sizeof(u64));
3268 u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
3269 (tx_ring->wq_id * sizeof(u64));
3273 * Assign doorbell registers for this tx_ring.
3275 /* TX PCI doorbell mem area for tx producer index */
3276 tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
3277 tx_ring->prod_idx = 0;
3278 /* TX PCI doorbell mem area + 0x04 */
3279 tx_ring->valid_db_reg = doorbell_area + 0x04;
3282 * Assign shadow registers for this tx_ring.
3284 tx_ring->cnsmr_idx_sh_reg = shadow_reg;
3285 tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
3287 wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
3288 wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
3289 Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
3290 wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
3292 wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
3294 wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
3296 ql_init_tx_ring(qdev, tx_ring);
3298 err = ql_write_cfg(qdev, wqicb, sizeof(*wqicb), CFG_LRQ,
3299 (u16) tx_ring->wq_id);
3301 netif_err(qdev, ifup, qdev->ndev, "Failed to load tx_ring.\n");
3307 static void ql_disable_msix(struct ql_adapter *qdev)
3309 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
3310 pci_disable_msix(qdev->pdev);
3311 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
3312 kfree(qdev->msi_x_entry);
3313 qdev->msi_x_entry = NULL;
3314 } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3315 pci_disable_msi(qdev->pdev);
3316 clear_bit(QL_MSI_ENABLED, &qdev->flags);
3320 /* We start by trying to get the number of vectors
3321 * stored in qdev->intr_count. If we don't get that
3322 * many then we reduce the count and try again.
3324 static void ql_enable_msix(struct ql_adapter *qdev)
3328 /* Get the MSIX vectors. */
3329 if (qlge_irq_type == MSIX_IRQ) {
3330 /* Try to alloc space for the msix struct,
3331 * if it fails then go to MSI/legacy.
3333 qdev->msi_x_entry = kcalloc(qdev->intr_count,
3334 sizeof(struct msix_entry),
3336 if (!qdev->msi_x_entry) {
3337 qlge_irq_type = MSI_IRQ;
3341 for (i = 0; i < qdev->intr_count; i++)
3342 qdev->msi_x_entry[i].entry = i;
3344 err = pci_enable_msix_range(qdev->pdev, qdev->msi_x_entry,
3345 1, qdev->intr_count);
3347 kfree(qdev->msi_x_entry);
3348 qdev->msi_x_entry = NULL;
3349 netif_warn(qdev, ifup, qdev->ndev,
3350 "MSI-X Enable failed, trying MSI.\n");
3351 qlge_irq_type = MSI_IRQ;
3353 qdev->intr_count = err;
3354 set_bit(QL_MSIX_ENABLED, &qdev->flags);
3355 netif_info(qdev, ifup, qdev->ndev,
3356 "MSI-X Enabled, got %d vectors.\n",
3362 qdev->intr_count = 1;
3363 if (qlge_irq_type == MSI_IRQ) {
3364 if (!pci_enable_msi(qdev->pdev)) {
3365 set_bit(QL_MSI_ENABLED, &qdev->flags);
3366 netif_info(qdev, ifup, qdev->ndev,
3367 "Running with MSI interrupts.\n");
3371 qlge_irq_type = LEG_IRQ;
3372 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3373 "Running with legacy interrupts.\n");
3376 /* Each vector services 1 RSS ring and and 1 or more
3377 * TX completion rings. This function loops through
3378 * the TX completion rings and assigns the vector that
3379 * will service it. An example would be if there are
3380 * 2 vectors (so 2 RSS rings) and 8 TX completion rings.
3381 * This would mean that vector 0 would service RSS ring 0
3382 * and TX completion rings 0,1,2 and 3. Vector 1 would
3383 * service RSS ring 1 and TX completion rings 4,5,6 and 7.
3385 static void ql_set_tx_vect(struct ql_adapter *qdev)
3388 u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count;
3390 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
3391 /* Assign irq vectors to TX rx_rings.*/
3392 for (vect = 0, j = 0, i = qdev->rss_ring_count;
3393 i < qdev->rx_ring_count; i++) {
3394 if (j == tx_rings_per_vector) {
3398 qdev->rx_ring[i].irq = vect;
3402 /* For single vector all rings have an irq
3405 for (i = 0; i < qdev->rx_ring_count; i++)
3406 qdev->rx_ring[i].irq = 0;
3410 /* Set the interrupt mask for this vector. Each vector
3411 * will service 1 RSS ring and 1 or more TX completion
3412 * rings. This function sets up a bit mask per vector
3413 * that indicates which rings it services.
3415 static void ql_set_irq_mask(struct ql_adapter *qdev, struct intr_context *ctx)
3417 int j, vect = ctx->intr;
3418 u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count;
3420 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
3421 /* Add the RSS ring serviced by this vector
3424 ctx->irq_mask = (1 << qdev->rx_ring[vect].cq_id);
3425 /* Add the TX ring(s) serviced by this vector
3427 for (j = 0; j < tx_rings_per_vector; j++) {
3429 (1 << qdev->rx_ring[qdev->rss_ring_count +
3430 (vect * tx_rings_per_vector) + j].cq_id);
3433 /* For single vector we just shift each queue's
3436 for (j = 0; j < qdev->rx_ring_count; j++)
3437 ctx->irq_mask |= (1 << qdev->rx_ring[j].cq_id);
3442 * Here we build the intr_context structures based on
3443 * our rx_ring count and intr vector count.
3444 * The intr_context structure is used to hook each vector
3445 * to possibly different handlers.
3447 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
3450 struct intr_context *intr_context = &qdev->intr_context[0];
3452 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
3453 /* Each rx_ring has it's
3454 * own intr_context since we have separate
3455 * vectors for each queue.
3457 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
3458 qdev->rx_ring[i].irq = i;
3459 intr_context->intr = i;
3460 intr_context->qdev = qdev;
3461 /* Set up this vector's bit-mask that indicates
3462 * which queues it services.
3464 ql_set_irq_mask(qdev, intr_context);
3466 * We set up each vectors enable/disable/read bits so
3467 * there's no bit/mask calculations in the critical path.
3469 intr_context->intr_en_mask =
3470 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3471 INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
3473 intr_context->intr_dis_mask =
3474 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3475 INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
3477 intr_context->intr_read_mask =
3478 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3479 INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
3482 /* The first vector/queue handles
3483 * broadcast/multicast, fatal errors,
3484 * and firmware events. This in addition
3485 * to normal inbound NAPI processing.
3487 intr_context->handler = qlge_isr;
3488 sprintf(intr_context->name, "%s-rx-%d",
3489 qdev->ndev->name, i);
3492 * Inbound queues handle unicast frames only.
3494 intr_context->handler = qlge_msix_rx_isr;
3495 sprintf(intr_context->name, "%s-rx-%d",
3496 qdev->ndev->name, i);
3501 * All rx_rings use the same intr_context since
3502 * there is only one vector.
3504 intr_context->intr = 0;
3505 intr_context->qdev = qdev;
3507 * We set up each vectors enable/disable/read bits so
3508 * there's no bit/mask calculations in the critical path.
3510 intr_context->intr_en_mask =
3511 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
3512 intr_context->intr_dis_mask =
3513 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
3514 INTR_EN_TYPE_DISABLE;
3515 intr_context->intr_read_mask =
3516 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
3518 * Single interrupt means one handler for all rings.
3520 intr_context->handler = qlge_isr;
3521 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
3522 /* Set up this vector's bit-mask that indicates
3523 * which queues it services. In this case there is
3524 * a single vector so it will service all RSS and
3525 * TX completion rings.
3527 ql_set_irq_mask(qdev, intr_context);
3529 /* Tell the TX completion rings which MSIx vector
3530 * they will be using.
3532 ql_set_tx_vect(qdev);
3535 static void ql_free_irq(struct ql_adapter *qdev)
3538 struct intr_context *intr_context = &qdev->intr_context[0];
3540 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
3541 if (intr_context->hooked) {
3542 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
3543 free_irq(qdev->msi_x_entry[i].vector,
3546 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
3550 ql_disable_msix(qdev);
3553 static int ql_request_irq(struct ql_adapter *qdev)
3557 struct pci_dev *pdev = qdev->pdev;
3558 struct intr_context *intr_context = &qdev->intr_context[0];
3560 ql_resolve_queues_to_irqs(qdev);
3562 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
3563 atomic_set(&intr_context->irq_cnt, 0);
3564 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
3565 status = request_irq(qdev->msi_x_entry[i].vector,
3566 intr_context->handler,
3571 netif_err(qdev, ifup, qdev->ndev,
3572 "Failed request for MSIX interrupt %d.\n",
3577 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3578 "trying msi or legacy interrupts.\n");
3579 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3580 "%s: irq = %d.\n", __func__, pdev->irq);
3581 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3582 "%s: context->name = %s.\n", __func__,
3583 intr_context->name);
3584 netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
3585 "%s: dev_id = 0x%p.\n", __func__,
3588 request_irq(pdev->irq, qlge_isr,
3589 test_bit(QL_MSI_ENABLED,
3591 flags) ? 0 : IRQF_SHARED,
3592 intr_context->name, &qdev->rx_ring[0]);
3596 netif_err(qdev, ifup, qdev->ndev,
3597 "Hooked intr %d, queue type %s, with name %s.\n",
3599 qdev->rx_ring[0].type == DEFAULT_Q ?
3601 qdev->rx_ring[0].type == TX_Q ? "TX_Q" :
3602 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
3603 intr_context->name);
3605 intr_context->hooked = 1;
3609 netif_err(qdev, ifup, qdev->ndev, "Failed to get the interrupts!!!\n");
3614 static int ql_start_rss(struct ql_adapter *qdev)
3616 static const u8 init_hash_seed[] = {
3617 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2,
3618 0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0,
3619 0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4,
3620 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, 0xf2, 0x0c,
3621 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa
3623 struct ricb *ricb = &qdev->ricb;
3626 u8 *hash_id = (u8 *) ricb->hash_cq_id;
3628 memset((void *)ricb, 0, sizeof(*ricb));
3630 ricb->base_cq = RSS_L4K;
3632 (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RT4 | RSS_RT6);
3633 ricb->mask = cpu_to_le16((u16)(0x3ff));
3636 * Fill out the Indirection Table.
3638 for (i = 0; i < 1024; i++)
3639 hash_id[i] = (i & (qdev->rss_ring_count - 1));
3641 memcpy((void *)&ricb->ipv6_hash_key[0], init_hash_seed, 40);
3642 memcpy((void *)&ricb->ipv4_hash_key[0], init_hash_seed, 16);
3644 status = ql_write_cfg(qdev, ricb, sizeof(*ricb), CFG_LR, 0);
3646 netif_err(qdev, ifup, qdev->ndev, "Failed to load RICB.\n");
3652 static int ql_clear_routing_entries(struct ql_adapter *qdev)
3656 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3659 /* Clear all the entries in the routing table. */
3660 for (i = 0; i < 16; i++) {
3661 status = ql_set_routing_reg(qdev, i, 0, 0);
3663 netif_err(qdev, ifup, qdev->ndev,
3664 "Failed to init routing register for CAM packets.\n");
3668 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3672 /* Initialize the frame-to-queue routing. */
3673 static int ql_route_initialize(struct ql_adapter *qdev)
3677 /* Clear all the entries in the routing table. */
3678 status = ql_clear_routing_entries(qdev);
3682 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3686 status = ql_set_routing_reg(qdev, RT_IDX_IP_CSUM_ERR_SLOT,
3687 RT_IDX_IP_CSUM_ERR, 1);
3689 netif_err(qdev, ifup, qdev->ndev,
3690 "Failed to init routing register "
3691 "for IP CSUM error packets.\n");
3694 status = ql_set_routing_reg(qdev, RT_IDX_TCP_UDP_CSUM_ERR_SLOT,
3695 RT_IDX_TU_CSUM_ERR, 1);
3697 netif_err(qdev, ifup, qdev->ndev,
3698 "Failed to init routing register "
3699 "for TCP/UDP CSUM error packets.\n");
3702 status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
3704 netif_err(qdev, ifup, qdev->ndev,
3705 "Failed to init routing register for broadcast packets.\n");
3708 /* If we have more than one inbound queue, then turn on RSS in the
3711 if (qdev->rss_ring_count > 1) {
3712 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
3713 RT_IDX_RSS_MATCH, 1);
3715 netif_err(qdev, ifup, qdev->ndev,
3716 "Failed to init routing register for MATCH RSS packets.\n");
3721 status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
3724 netif_err(qdev, ifup, qdev->ndev,
3725 "Failed to init routing register for CAM packets.\n");
3727 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3731 int ql_cam_route_initialize(struct ql_adapter *qdev)
3735 /* If check if the link is up and use to
3736 * determine if we are setting or clearing
3737 * the MAC address in the CAM.
3739 set = ql_read32(qdev, STS);
3740 set &= qdev->port_link_up;
3741 status = ql_set_mac_addr(qdev, set);
3743 netif_err(qdev, ifup, qdev->ndev, "Failed to init mac address.\n");
3747 status = ql_route_initialize(qdev);
3749 netif_err(qdev, ifup, qdev->ndev, "Failed to init routing table.\n");
3754 static int ql_adapter_initialize(struct ql_adapter *qdev)
3761 * Set up the System register to halt on errors.
3763 value = SYS_EFE | SYS_FAE;
3765 ql_write32(qdev, SYS, mask | value);
3767 /* Set the default queue, and VLAN behavior. */
3768 value = NIC_RCV_CFG_DFQ;
3769 mask = NIC_RCV_CFG_DFQ_MASK;
3770 if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) {
3771 value |= NIC_RCV_CFG_RV;
3772 mask |= (NIC_RCV_CFG_RV << 16);
3774 ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3776 /* Set the MPI interrupt to enabled. */
3777 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3779 /* Enable the function, set pagesize, enable error checking. */
3780 value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3781 FSC_EC | FSC_VM_PAGE_4K;
3782 value |= SPLT_SETTING;
3784 /* Set/clear header splitting. */
3785 mask = FSC_VM_PAGESIZE_MASK |
3786 FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3787 ql_write32(qdev, FSC, mask | value);
3789 ql_write32(qdev, SPLT_HDR, SPLT_LEN);
3791 /* Set RX packet routing to use port/pci function on which the
3792 * packet arrived on in addition to usual frame routing.
3793 * This is helpful on bonding where both interfaces can have
3794 * the same MAC address.
3796 ql_write32(qdev, RST_FO, RST_FO_RR_MASK | RST_FO_RR_RCV_FUNC_CQ);
3797 /* Reroute all packets to our Interface.
3798 * They may have been routed to MPI firmware
3801 value = ql_read32(qdev, MGMT_RCV_CFG);
3802 value &= ~MGMT_RCV_CFG_RM;
3805 /* Sticky reg needs clearing due to WOL. */
3806 ql_write32(qdev, MGMT_RCV_CFG, mask);
3807 ql_write32(qdev, MGMT_RCV_CFG, mask | value);
3809 /* Default WOL is enable on Mezz cards */
3810 if (qdev->pdev->subsystem_device == 0x0068 ||
3811 qdev->pdev->subsystem_device == 0x0180)
3812 qdev->wol = WAKE_MAGIC;
3814 /* Start up the rx queues. */
3815 for (i = 0; i < qdev->rx_ring_count; i++) {
3816 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3818 netif_err(qdev, ifup, qdev->ndev,
3819 "Failed to start rx ring[%d].\n", i);
3824 /* If there is more than one inbound completion queue
3825 * then download a RICB to configure RSS.
3827 if (qdev->rss_ring_count > 1) {
3828 status = ql_start_rss(qdev);
3830 netif_err(qdev, ifup, qdev->ndev, "Failed to start RSS.\n");
3835 /* Start up the tx queues. */
3836 for (i = 0; i < qdev->tx_ring_count; i++) {
3837 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3839 netif_err(qdev, ifup, qdev->ndev,
3840 "Failed to start tx ring[%d].\n", i);
3845 /* Initialize the port and set the max framesize. */
3846 status = qdev->nic_ops->port_initialize(qdev);
3848 netif_err(qdev, ifup, qdev->ndev, "Failed to start port.\n");
3850 /* Set up the MAC address and frame routing filter. */
3851 status = ql_cam_route_initialize(qdev);
3853 netif_err(qdev, ifup, qdev->ndev,
3854 "Failed to init CAM/Routing tables.\n");
3858 /* Start NAPI for the RSS queues. */
3859 for (i = 0; i < qdev->rss_ring_count; i++)
3860 napi_enable(&qdev->rx_ring[i].napi);
3865 /* Issue soft reset to chip. */
3866 static int ql_adapter_reset(struct ql_adapter *qdev)
3870 unsigned long end_jiffies;
3872 /* Clear all the entries in the routing table. */
3873 status = ql_clear_routing_entries(qdev);
3875 netif_err(qdev, ifup, qdev->ndev, "Failed to clear routing bits.\n");
3879 /* Check if bit is set then skip the mailbox command and
3880 * clear the bit, else we are in normal reset process.
3882 if (!test_bit(QL_ASIC_RECOVERY, &qdev->flags)) {
3883 /* Stop management traffic. */
3884 ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_STOP);
3886 /* Wait for the NIC and MGMNT FIFOs to empty. */
3887 ql_wait_fifo_empty(qdev);
3889 clear_bit(QL_ASIC_RECOVERY, &qdev->flags);
3891 ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3893 end_jiffies = jiffies + usecs_to_jiffies(30);
3895 value = ql_read32(qdev, RST_FO);
3896 if ((value & RST_FO_FR) == 0)
3899 } while (time_before(jiffies, end_jiffies));
3901 if (value & RST_FO_FR) {
3902 netif_err(qdev, ifdown, qdev->ndev,
3903 "ETIMEDOUT!!! errored out of resetting the chip!\n");
3904 status = -ETIMEDOUT;
3907 /* Resume management traffic. */
3908 ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_RESUME);
3912 static void ql_display_dev_info(struct net_device *ndev)
3914 struct ql_adapter *qdev = netdev_priv(ndev);
3916 netif_info(qdev, probe, qdev->ndev,
3917 "Function #%d, Port %d, NIC Roll %d, NIC Rev = %d, "
3918 "XG Roll = %d, XG Rev = %d.\n",
3921 qdev->chip_rev_id & 0x0000000f,
3922 qdev->chip_rev_id >> 4 & 0x0000000f,
3923 qdev->chip_rev_id >> 8 & 0x0000000f,
3924 qdev->chip_rev_id >> 12 & 0x0000000f);
3925 netif_info(qdev, probe, qdev->ndev,
3926 "MAC address %pM\n", ndev->dev_addr);
3929 static int ql_wol(struct ql_adapter *qdev)
3932 u32 wol = MB_WOL_DISABLE;
3934 /* The CAM is still intact after a reset, but if we
3935 * are doing WOL, then we may need to program the
3936 * routing regs. We would also need to issue the mailbox
3937 * commands to instruct the MPI what to do per the ethtool
3941 if (qdev->wol & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_PHY | WAKE_UCAST |
3942 WAKE_MCAST | WAKE_BCAST)) {
3943 netif_err(qdev, ifdown, qdev->ndev,
3944 "Unsupported WOL parameter. qdev->wol = 0x%x.\n",
3949 if (qdev->wol & WAKE_MAGIC) {
3950 status = ql_mb_wol_set_magic(qdev, 1);
3952 netif_err(qdev, ifdown, qdev->ndev,
3953 "Failed to set magic packet on %s.\n",
3957 netif_info(qdev, drv, qdev->ndev,
3958 "Enabled magic packet successfully on %s.\n",
3961 wol |= MB_WOL_MAGIC_PKT;
3965 wol |= MB_WOL_MODE_ON;
3966 status = ql_mb_wol_mode(qdev, wol);
3967 netif_err(qdev, drv, qdev->ndev,
3968 "WOL %s (wol code 0x%x) on %s\n",
3969 (status == 0) ? "Successfully set" : "Failed",
3970 wol, qdev->ndev->name);
3976 static void ql_cancel_all_work_sync(struct ql_adapter *qdev)
3979 /* Don't kill the reset worker thread if we
3980 * are in the process of recovery.
3982 if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3983 cancel_delayed_work_sync(&qdev->asic_reset_work);
3984 cancel_delayed_work_sync(&qdev->mpi_reset_work);
3985 cancel_delayed_work_sync(&qdev->mpi_work);
3986 cancel_delayed_work_sync(&qdev->mpi_idc_work);
3987 cancel_delayed_work_sync(&qdev->mpi_core_to_log);
3988 cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
3991 static int ql_adapter_down(struct ql_adapter *qdev)
3997 ql_cancel_all_work_sync(qdev);
3999 for (i = 0; i < qdev->rss_ring_count; i++)
4000 napi_disable(&qdev->rx_ring[i].napi);
4002 clear_bit(QL_ADAPTER_UP, &qdev->flags);
4004 ql_disable_interrupts(qdev);
4006 ql_tx_ring_clean(qdev);
4008 /* Call netif_napi_del() from common point.
4010 for (i = 0; i < qdev->rss_ring_count; i++)
4011 netif_napi_del(&qdev->rx_ring[i].napi);
4013 status = ql_adapter_reset(qdev);
4015 netif_err(qdev, ifdown, qdev->ndev, "reset(func #%d) FAILED!\n",
4017 ql_free_rx_buffers(qdev);
4022 static int ql_adapter_up(struct ql_adapter *qdev)
4026 err = ql_adapter_initialize(qdev);
4028 netif_info(qdev, ifup, qdev->ndev, "Unable to initialize adapter.\n");
4031 set_bit(QL_ADAPTER_UP, &qdev->flags);
4032 ql_alloc_rx_buffers(qdev);
4033 /* If the port is initialized and the
4034 * link is up the turn on the carrier.
4036 if ((ql_read32(qdev, STS) & qdev->port_init) &&
4037 (ql_read32(qdev, STS) & qdev->port_link_up))
4039 /* Restore rx mode. */
4040 clear_bit(QL_ALLMULTI, &qdev->flags);
4041 clear_bit(QL_PROMISCUOUS, &qdev->flags);
4042 qlge_set_multicast_list(qdev->ndev);
4044 /* Restore vlan setting. */
4045 qlge_restore_vlan(qdev);
4047 ql_enable_interrupts(qdev);
4048 ql_enable_all_completion_interrupts(qdev);
4049 netif_tx_start_all_queues(qdev->ndev);
4053 ql_adapter_reset(qdev);
4057 static void ql_release_adapter_resources(struct ql_adapter *qdev)
4059 ql_free_mem_resources(qdev);
4063 static int ql_get_adapter_resources(struct ql_adapter *qdev)
4067 if (ql_alloc_mem_resources(qdev)) {
4068 netif_err(qdev, ifup, qdev->ndev, "Unable to allocate memory.\n");
4071 status = ql_request_irq(qdev);
4075 static int qlge_close(struct net_device *ndev)
4077 struct ql_adapter *qdev = netdev_priv(ndev);
4079 /* If we hit pci_channel_io_perm_failure
4080 * failure condition, then we already
4081 * brought the adapter down.
4083 if (test_bit(QL_EEH_FATAL, &qdev->flags)) {
4084 netif_err(qdev, drv, qdev->ndev, "EEH fatal did unload.\n");
4085 clear_bit(QL_EEH_FATAL, &qdev->flags);
4090 * Wait for device to recover from a reset.
4091 * (Rarely happens, but possible.)
4093 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
4095 ql_adapter_down(qdev);
4096 ql_release_adapter_resources(qdev);
4100 static int ql_configure_rings(struct ql_adapter *qdev)
4103 struct rx_ring *rx_ring;
4104 struct tx_ring *tx_ring;
4105 int cpu_cnt = min(MAX_CPUS, (int)num_online_cpus());
4106 unsigned int lbq_buf_len = (qdev->ndev->mtu > 1500) ?
4107 LARGE_BUFFER_MAX_SIZE : LARGE_BUFFER_MIN_SIZE;
4109 qdev->lbq_buf_order = get_order(lbq_buf_len);
4111 /* In a perfect world we have one RSS ring for each CPU
4112 * and each has it's own vector. To do that we ask for
4113 * cpu_cnt vectors. ql_enable_msix() will adjust the
4114 * vector count to what we actually get. We then
4115 * allocate an RSS ring for each.
4116 * Essentially, we are doing min(cpu_count, msix_vector_count).
4118 qdev->intr_count = cpu_cnt;
4119 ql_enable_msix(qdev);
4120 /* Adjust the RSS ring count to the actual vector count. */
4121 qdev->rss_ring_count = qdev->intr_count;
4122 qdev->tx_ring_count = cpu_cnt;
4123 qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count;
4125 for (i = 0; i < qdev->tx_ring_count; i++) {
4126 tx_ring = &qdev->tx_ring[i];
4127 memset((void *)tx_ring, 0, sizeof(*tx_ring));
4128 tx_ring->qdev = qdev;
4130 tx_ring->wq_len = qdev->tx_ring_size;
4132 tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
4135 * The completion queue ID for the tx rings start
4136 * immediately after the rss rings.
4138 tx_ring->cq_id = qdev->rss_ring_count + i;
4141 for (i = 0; i < qdev->rx_ring_count; i++) {
4142 rx_ring = &qdev->rx_ring[i];
4143 memset((void *)rx_ring, 0, sizeof(*rx_ring));
4144 rx_ring->qdev = qdev;
4146 rx_ring->cpu = i % cpu_cnt; /* CPU to run handler on. */
4147 if (i < qdev->rss_ring_count) {
4149 * Inbound (RSS) queues.
4151 rx_ring->cq_len = qdev->rx_ring_size;
4153 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
4154 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
4156 rx_ring->lbq_len * sizeof(__le64);
4157 rx_ring->lbq_buf_size = (u16)lbq_buf_len;
4158 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
4160 rx_ring->sbq_len * sizeof(__le64);
4161 rx_ring->sbq_buf_size = SMALL_BUF_MAP_SIZE;
4162 rx_ring->type = RX_Q;
4165 * Outbound queue handles outbound completions only.
4167 /* outbound cq is same size as tx_ring it services. */
4168 rx_ring->cq_len = qdev->tx_ring_size;
4170 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
4171 rx_ring->lbq_len = 0;
4172 rx_ring->lbq_size = 0;
4173 rx_ring->lbq_buf_size = 0;
4174 rx_ring->sbq_len = 0;
4175 rx_ring->sbq_size = 0;
4176 rx_ring->sbq_buf_size = 0;
4177 rx_ring->type = TX_Q;
4183 static int qlge_open(struct net_device *ndev)
4186 struct ql_adapter *qdev = netdev_priv(ndev);
4188 err = ql_adapter_reset(qdev);
4192 err = ql_configure_rings(qdev);
4196 err = ql_get_adapter_resources(qdev);
4200 err = ql_adapter_up(qdev);
4207 ql_release_adapter_resources(qdev);
4211 static int ql_change_rx_buffers(struct ql_adapter *qdev)
4213 struct rx_ring *rx_ring;
4217 /* Wait for an outstanding reset to complete. */
4218 if (!test_bit(QL_ADAPTER_UP, &qdev->flags)) {
4221 while (--i && !test_bit(QL_ADAPTER_UP, &qdev->flags)) {
4222 netif_err(qdev, ifup, qdev->ndev,
4223 "Waiting for adapter UP...\n");
4228 netif_err(qdev, ifup, qdev->ndev,
4229 "Timed out waiting for adapter UP\n");
4234 status = ql_adapter_down(qdev);
4238 /* Get the new rx buffer size. */
4239 lbq_buf_len = (qdev->ndev->mtu > 1500) ?
4240 LARGE_BUFFER_MAX_SIZE : LARGE_BUFFER_MIN_SIZE;
4241 qdev->lbq_buf_order = get_order(lbq_buf_len);
4243 for (i = 0; i < qdev->rss_ring_count; i++) {
4244 rx_ring = &qdev->rx_ring[i];
4245 /* Set the new size. */
4246 rx_ring->lbq_buf_size = lbq_buf_len;
4249 status = ql_adapter_up(qdev);
4255 netif_alert(qdev, ifup, qdev->ndev,
4256 "Driver up/down cycle failed, closing device.\n");
4257 set_bit(QL_ADAPTER_UP, &qdev->flags);
4258 dev_close(qdev->ndev);
4262 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
4264 struct ql_adapter *qdev = netdev_priv(ndev);
4267 if (ndev->mtu == 1500 && new_mtu == 9000) {
4268 netif_err(qdev, ifup, qdev->ndev, "Changing to jumbo MTU.\n");
4269 } else if (ndev->mtu == 9000 && new_mtu == 1500) {
4270 netif_err(qdev, ifup, qdev->ndev, "Changing to normal MTU.\n");
4274 queue_delayed_work(qdev->workqueue,
4275 &qdev->mpi_port_cfg_work, 3*HZ);
4277 ndev->mtu = new_mtu;
4279 if (!netif_running(qdev->ndev)) {
4283 status = ql_change_rx_buffers(qdev);
4285 netif_err(qdev, ifup, qdev->ndev,
4286 "Changing MTU failed.\n");
4292 static struct net_device_stats *qlge_get_stats(struct net_device
4295 struct ql_adapter *qdev = netdev_priv(ndev);
4296 struct rx_ring *rx_ring = &qdev->rx_ring[0];
4297 struct tx_ring *tx_ring = &qdev->tx_ring[0];
4298 unsigned long pkts, mcast, dropped, errors, bytes;
4302 pkts = mcast = dropped = errors = bytes = 0;
4303 for (i = 0; i < qdev->rss_ring_count; i++, rx_ring++) {
4304 pkts += rx_ring->rx_packets;
4305 bytes += rx_ring->rx_bytes;
4306 dropped += rx_ring->rx_dropped;
4307 errors += rx_ring->rx_errors;
4308 mcast += rx_ring->rx_multicast;
4310 ndev->stats.rx_packets = pkts;
4311 ndev->stats.rx_bytes = bytes;
4312 ndev->stats.rx_dropped = dropped;
4313 ndev->stats.rx_errors = errors;
4314 ndev->stats.multicast = mcast;
4317 pkts = errors = bytes = 0;
4318 for (i = 0; i < qdev->tx_ring_count; i++, tx_ring++) {
4319 pkts += tx_ring->tx_packets;
4320 bytes += tx_ring->tx_bytes;
4321 errors += tx_ring->tx_errors;
4323 ndev->stats.tx_packets = pkts;
4324 ndev->stats.tx_bytes = bytes;
4325 ndev->stats.tx_errors = errors;
4326 return &ndev->stats;
4329 static void qlge_set_multicast_list(struct net_device *ndev)
4331 struct ql_adapter *qdev = netdev_priv(ndev);
4332 struct netdev_hw_addr *ha;
4335 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
4339 * Set or clear promiscuous mode if a
4340 * transition is taking place.
4342 if (ndev->flags & IFF_PROMISC) {
4343 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
4344 if (ql_set_routing_reg
4345 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
4346 netif_err(qdev, hw, qdev->ndev,
4347 "Failed to set promiscuous mode.\n");
4349 set_bit(QL_PROMISCUOUS, &qdev->flags);
4353 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
4354 if (ql_set_routing_reg
4355 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
4356 netif_err(qdev, hw, qdev->ndev,
4357 "Failed to clear promiscuous mode.\n");
4359 clear_bit(QL_PROMISCUOUS, &qdev->flags);
4365 * Set or clear all multicast mode if a
4366 * transition is taking place.
4368 if ((ndev->flags & IFF_ALLMULTI) ||
4369 (netdev_mc_count(ndev) > MAX_MULTICAST_ENTRIES)) {
4370 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
4371 if (ql_set_routing_reg
4372 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
4373 netif_err(qdev, hw, qdev->ndev,
4374 "Failed to set all-multi mode.\n");
4376 set_bit(QL_ALLMULTI, &qdev->flags);
4380 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
4381 if (ql_set_routing_reg
4382 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
4383 netif_err(qdev, hw, qdev->ndev,
4384 "Failed to clear all-multi mode.\n");
4386 clear_bit(QL_ALLMULTI, &qdev->flags);
4391 if (!netdev_mc_empty(ndev)) {
4392 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
4396 netdev_for_each_mc_addr(ha, ndev) {
4397 if (ql_set_mac_addr_reg(qdev, (u8 *) ha->addr,
4398 MAC_ADDR_TYPE_MULTI_MAC, i)) {
4399 netif_err(qdev, hw, qdev->ndev,
4400 "Failed to loadmulticast address.\n");
4401 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
4406 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
4407 if (ql_set_routing_reg
4408 (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
4409 netif_err(qdev, hw, qdev->ndev,
4410 "Failed to set multicast match mode.\n");
4412 set_bit(QL_ALLMULTI, &qdev->flags);
4416 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
4419 static int qlge_set_mac_address(struct net_device *ndev, void *p)
4421 struct ql_adapter *qdev = netdev_priv(ndev);
4422 struct sockaddr *addr = p;
4425 if (!is_valid_ether_addr(addr->sa_data))
4426 return -EADDRNOTAVAIL;
4427 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
4428 /* Update local copy of current mac address. */
4429 memcpy(qdev->current_mac_addr, ndev->dev_addr, ndev->addr_len);
4431 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
4434 status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
4435 MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
4437 netif_err(qdev, hw, qdev->ndev, "Failed to load MAC address.\n");
4438 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
4442 static void qlge_tx_timeout(struct net_device *ndev)
4444 struct ql_adapter *qdev = netdev_priv(ndev);
4445 ql_queue_asic_error(qdev);
4448 static void ql_asic_reset_work(struct work_struct *work)
4450 struct ql_adapter *qdev =
4451 container_of(work, struct ql_adapter, asic_reset_work.work);
4454 status = ql_adapter_down(qdev);
4458 status = ql_adapter_up(qdev);
4462 /* Restore rx mode. */
4463 clear_bit(QL_ALLMULTI, &qdev->flags);
4464 clear_bit(QL_PROMISCUOUS, &qdev->flags);
4465 qlge_set_multicast_list(qdev->ndev);
4470 netif_alert(qdev, ifup, qdev->ndev,
4471 "Driver up/down cycle failed, closing device\n");
4473 set_bit(QL_ADAPTER_UP, &qdev->flags);
4474 dev_close(qdev->ndev);
4478 static const struct nic_operations qla8012_nic_ops = {
4479 .get_flash = ql_get_8012_flash_params,
4480 .port_initialize = ql_8012_port_initialize,
4483 static const struct nic_operations qla8000_nic_ops = {
4484 .get_flash = ql_get_8000_flash_params,
4485 .port_initialize = ql_8000_port_initialize,
4488 /* Find the pcie function number for the other NIC
4489 * on this chip. Since both NIC functions share a
4490 * common firmware we have the lowest enabled function
4491 * do any common work. Examples would be resetting
4492 * after a fatal firmware error, or doing a firmware
4495 static int ql_get_alt_pcie_func(struct ql_adapter *qdev)
4499 u32 nic_func1, nic_func2;
4501 status = ql_read_mpi_reg(qdev, MPI_TEST_FUNC_PORT_CFG,
4506 nic_func1 = ((temp >> MPI_TEST_NIC1_FUNC_SHIFT) &
4507 MPI_TEST_NIC_FUNC_MASK);
4508 nic_func2 = ((temp >> MPI_TEST_NIC2_FUNC_SHIFT) &
4509 MPI_TEST_NIC_FUNC_MASK);
4511 if (qdev->func == nic_func1)
4512 qdev->alt_func = nic_func2;
4513 else if (qdev->func == nic_func2)
4514 qdev->alt_func = nic_func1;
4521 static int ql_get_board_info(struct ql_adapter *qdev)
4525 (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
4529 status = ql_get_alt_pcie_func(qdev);
4533 qdev->port = (qdev->func < qdev->alt_func) ? 0 : 1;
4535 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
4536 qdev->port_link_up = STS_PL1;
4537 qdev->port_init = STS_PI1;
4538 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
4539 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
4541 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
4542 qdev->port_link_up = STS_PL0;
4543 qdev->port_init = STS_PI0;
4544 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
4545 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
4547 qdev->chip_rev_id = ql_read32(qdev, REV_ID);
4548 qdev->device_id = qdev->pdev->device;
4549 if (qdev->device_id == QLGE_DEVICE_ID_8012)
4550 qdev->nic_ops = &qla8012_nic_ops;
4551 else if (qdev->device_id == QLGE_DEVICE_ID_8000)
4552 qdev->nic_ops = &qla8000_nic_ops;
4556 static void ql_release_all(struct pci_dev *pdev)
4558 struct net_device *ndev = pci_get_drvdata(pdev);
4559 struct ql_adapter *qdev = netdev_priv(ndev);
4561 if (qdev->workqueue) {
4562 destroy_workqueue(qdev->workqueue);
4563 qdev->workqueue = NULL;
4567 iounmap(qdev->reg_base);
4568 if (qdev->doorbell_area)
4569 iounmap(qdev->doorbell_area);
4570 vfree(qdev->mpi_coredump);
4571 pci_release_regions(pdev);
4574 static int ql_init_device(struct pci_dev *pdev, struct net_device *ndev,
4577 struct ql_adapter *qdev = netdev_priv(ndev);
4580 memset((void *)qdev, 0, sizeof(*qdev));
4581 err = pci_enable_device(pdev);
4583 dev_err(&pdev->dev, "PCI device enable failed.\n");
4589 pci_set_drvdata(pdev, ndev);
4591 /* Set PCIe read request size */
4592 err = pcie_set_readrq(pdev, 4096);
4594 dev_err(&pdev->dev, "Set readrq failed.\n");
4598 err = pci_request_regions(pdev, DRV_NAME);
4600 dev_err(&pdev->dev, "PCI region request failed.\n");
4604 pci_set_master(pdev);
4605 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4606 set_bit(QL_DMA64, &qdev->flags);
4607 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4609 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4611 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4615 dev_err(&pdev->dev, "No usable DMA configuration.\n");
4619 /* Set PCIe reset type for EEH to fundamental. */
4620 pdev->needs_freset = 1;
4621 pci_save_state(pdev);
4623 ioremap_nocache(pci_resource_start(pdev, 1),
4624 pci_resource_len(pdev, 1));
4625 if (!qdev->reg_base) {
4626 dev_err(&pdev->dev, "Register mapping failed.\n");
4631 qdev->doorbell_area_size = pci_resource_len(pdev, 3);
4632 qdev->doorbell_area =
4633 ioremap_nocache(pci_resource_start(pdev, 3),
4634 pci_resource_len(pdev, 3));
4635 if (!qdev->doorbell_area) {
4636 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
4641 err = ql_get_board_info(qdev);
4643 dev_err(&pdev->dev, "Register access failed.\n");
4647 qdev->msg_enable = netif_msg_init(debug, default_msg);
4648 spin_lock_init(&qdev->hw_lock);
4649 spin_lock_init(&qdev->stats_lock);
4651 if (qlge_mpi_coredump) {
4652 qdev->mpi_coredump =
4653 vmalloc(sizeof(struct ql_mpi_coredump));
4654 if (qdev->mpi_coredump == NULL) {
4658 if (qlge_force_coredump)
4659 set_bit(QL_FRC_COREDUMP, &qdev->flags);
4661 /* make sure the EEPROM is good */
4662 err = qdev->nic_ops->get_flash(qdev);
4664 dev_err(&pdev->dev, "Invalid FLASH.\n");
4668 /* Keep local copy of current mac address. */
4669 memcpy(qdev->current_mac_addr, ndev->dev_addr, ndev->addr_len);
4671 /* Set up the default ring sizes. */
4672 qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
4673 qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
4675 /* Set up the coalescing parameters. */
4676 qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
4677 qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
4678 qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
4679 qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
4682 * Set up the operating parameters.
4684 qdev->workqueue = create_singlethread_workqueue(ndev->name);
4685 INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
4686 INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
4687 INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
4688 INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
4689 INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
4690 INIT_DELAYED_WORK(&qdev->mpi_core_to_log, ql_mpi_core_to_log);
4691 init_completion(&qdev->ide_completion);
4692 mutex_init(&qdev->mpi_mutex);
4695 dev_info(&pdev->dev, "%s\n", DRV_STRING);
4696 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
4697 DRV_NAME, DRV_VERSION);
4701 ql_release_all(pdev);
4703 pci_disable_device(pdev);
4707 static const struct net_device_ops qlge_netdev_ops = {
4708 .ndo_open = qlge_open,
4709 .ndo_stop = qlge_close,
4710 .ndo_start_xmit = qlge_send,
4711 .ndo_change_mtu = qlge_change_mtu,
4712 .ndo_get_stats = qlge_get_stats,
4713 .ndo_set_rx_mode = qlge_set_multicast_list,
4714 .ndo_set_mac_address = qlge_set_mac_address,
4715 .ndo_validate_addr = eth_validate_addr,
4716 .ndo_tx_timeout = qlge_tx_timeout,
4717 .ndo_set_features = qlge_set_features,
4718 .ndo_vlan_rx_add_vid = qlge_vlan_rx_add_vid,
4719 .ndo_vlan_rx_kill_vid = qlge_vlan_rx_kill_vid,
4722 static void ql_timer(unsigned long data)
4724 struct ql_adapter *qdev = (struct ql_adapter *)data;
4727 var = ql_read32(qdev, STS);
4728 if (pci_channel_offline(qdev->pdev)) {
4729 netif_err(qdev, ifup, qdev->ndev, "EEH STS = 0x%.08x.\n", var);
4733 mod_timer(&qdev->timer, jiffies + (5*HZ));
4736 static int qlge_probe(struct pci_dev *pdev,
4737 const struct pci_device_id *pci_entry)
4739 struct net_device *ndev = NULL;
4740 struct ql_adapter *qdev = NULL;
4741 static int cards_found = 0;
4744 ndev = alloc_etherdev_mq(sizeof(struct ql_adapter),
4745 min(MAX_CPUS, netif_get_num_default_rss_queues()));
4749 err = ql_init_device(pdev, ndev, cards_found);
4755 qdev = netdev_priv(ndev);
4756 SET_NETDEV_DEV(ndev, &pdev->dev);
4757 ndev->hw_features = NETIF_F_SG |
4761 NETIF_F_HW_VLAN_CTAG_TX |
4762 NETIF_F_HW_VLAN_CTAG_RX |
4763 NETIF_F_HW_VLAN_CTAG_FILTER |
4765 ndev->features = ndev->hw_features;
4766 ndev->vlan_features = ndev->hw_features;
4767 /* vlan gets same features (except vlan filter) */
4768 ndev->vlan_features &= ~(NETIF_F_HW_VLAN_CTAG_FILTER |
4769 NETIF_F_HW_VLAN_CTAG_TX |
4770 NETIF_F_HW_VLAN_CTAG_RX);
4772 if (test_bit(QL_DMA64, &qdev->flags))
4773 ndev->features |= NETIF_F_HIGHDMA;
4776 * Set up net_device structure.
4778 ndev->tx_queue_len = qdev->tx_ring_size;
4779 ndev->irq = pdev->irq;
4781 ndev->netdev_ops = &qlge_netdev_ops;
4782 ndev->ethtool_ops = &qlge_ethtool_ops;
4783 ndev->watchdog_timeo = 10 * HZ;
4785 err = register_netdev(ndev);
4787 dev_err(&pdev->dev, "net device registration failed.\n");
4788 ql_release_all(pdev);
4789 pci_disable_device(pdev);
4793 /* Start up the timer to trigger EEH if
4796 init_timer_deferrable(&qdev->timer);
4797 qdev->timer.data = (unsigned long)qdev;
4798 qdev->timer.function = ql_timer;
4799 qdev->timer.expires = jiffies + (5*HZ);
4800 add_timer(&qdev->timer);
4802 ql_display_dev_info(ndev);
4803 atomic_set(&qdev->lb_count, 0);
4808 netdev_tx_t ql_lb_send(struct sk_buff *skb, struct net_device *ndev)
4810 return qlge_send(skb, ndev);
4813 int ql_clean_lb_rx_ring(struct rx_ring *rx_ring, int budget)
4815 return ql_clean_inbound_rx_ring(rx_ring, budget);
4818 static void qlge_remove(struct pci_dev *pdev)
4820 struct net_device *ndev = pci_get_drvdata(pdev);
4821 struct ql_adapter *qdev = netdev_priv(ndev);
4822 del_timer_sync(&qdev->timer);
4823 ql_cancel_all_work_sync(qdev);
4824 unregister_netdev(ndev);
4825 ql_release_all(pdev);
4826 pci_disable_device(pdev);
4830 /* Clean up resources without touching hardware. */
4831 static void ql_eeh_close(struct net_device *ndev)
4834 struct ql_adapter *qdev = netdev_priv(ndev);
4836 if (netif_carrier_ok(ndev)) {
4837 netif_carrier_off(ndev);
4838 netif_stop_queue(ndev);
4841 /* Disabling the timer */
4842 del_timer_sync(&qdev->timer);
4843 ql_cancel_all_work_sync(qdev);
4845 for (i = 0; i < qdev->rss_ring_count; i++)
4846 netif_napi_del(&qdev->rx_ring[i].napi);
4848 clear_bit(QL_ADAPTER_UP, &qdev->flags);
4849 ql_tx_ring_clean(qdev);
4850 ql_free_rx_buffers(qdev);
4851 ql_release_adapter_resources(qdev);
4855 * This callback is called by the PCI subsystem whenever
4856 * a PCI bus error is detected.
4858 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
4859 enum pci_channel_state state)
4861 struct net_device *ndev = pci_get_drvdata(pdev);
4862 struct ql_adapter *qdev = netdev_priv(ndev);
4865 case pci_channel_io_normal:
4866 return PCI_ERS_RESULT_CAN_RECOVER;
4867 case pci_channel_io_frozen:
4868 netif_device_detach(ndev);
4869 if (netif_running(ndev))
4871 pci_disable_device(pdev);
4872 return PCI_ERS_RESULT_NEED_RESET;
4873 case pci_channel_io_perm_failure:
4875 "%s: pci_channel_io_perm_failure.\n", __func__);
4877 set_bit(QL_EEH_FATAL, &qdev->flags);
4878 return PCI_ERS_RESULT_DISCONNECT;
4881 /* Request a slot reset. */
4882 return PCI_ERS_RESULT_NEED_RESET;
4886 * This callback is called after the PCI buss has been reset.
4887 * Basically, this tries to restart the card from scratch.
4888 * This is a shortened version of the device probe/discovery code,
4889 * it resembles the first-half of the () routine.
4891 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
4893 struct net_device *ndev = pci_get_drvdata(pdev);
4894 struct ql_adapter *qdev = netdev_priv(ndev);
4896 pdev->error_state = pci_channel_io_normal;
4898 pci_restore_state(pdev);
4899 if (pci_enable_device(pdev)) {
4900 netif_err(qdev, ifup, qdev->ndev,
4901 "Cannot re-enable PCI device after reset.\n");
4902 return PCI_ERS_RESULT_DISCONNECT;
4904 pci_set_master(pdev);
4906 if (ql_adapter_reset(qdev)) {
4907 netif_err(qdev, drv, qdev->ndev, "reset FAILED!\n");
4908 set_bit(QL_EEH_FATAL, &qdev->flags);
4909 return PCI_ERS_RESULT_DISCONNECT;
4912 return PCI_ERS_RESULT_RECOVERED;
4915 static void qlge_io_resume(struct pci_dev *pdev)
4917 struct net_device *ndev = pci_get_drvdata(pdev);
4918 struct ql_adapter *qdev = netdev_priv(ndev);
4921 if (netif_running(ndev)) {
4922 err = qlge_open(ndev);
4924 netif_err(qdev, ifup, qdev->ndev,
4925 "Device initialization failed after reset.\n");
4929 netif_err(qdev, ifup, qdev->ndev,
4930 "Device was not running prior to EEH.\n");
4932 mod_timer(&qdev->timer, jiffies + (5*HZ));
4933 netif_device_attach(ndev);
4936 static const struct pci_error_handlers qlge_err_handler = {
4937 .error_detected = qlge_io_error_detected,
4938 .slot_reset = qlge_io_slot_reset,
4939 .resume = qlge_io_resume,
4942 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
4944 struct net_device *ndev = pci_get_drvdata(pdev);
4945 struct ql_adapter *qdev = netdev_priv(ndev);
4948 netif_device_detach(ndev);
4949 del_timer_sync(&qdev->timer);
4951 if (netif_running(ndev)) {
4952 err = ql_adapter_down(qdev);
4958 err = pci_save_state(pdev);
4962 pci_disable_device(pdev);
4964 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4970 static int qlge_resume(struct pci_dev *pdev)
4972 struct net_device *ndev = pci_get_drvdata(pdev);
4973 struct ql_adapter *qdev = netdev_priv(ndev);
4976 pci_set_power_state(pdev, PCI_D0);
4977 pci_restore_state(pdev);
4978 err = pci_enable_device(pdev);
4980 netif_err(qdev, ifup, qdev->ndev, "Cannot enable PCI device from suspend\n");
4983 pci_set_master(pdev);
4985 pci_enable_wake(pdev, PCI_D3hot, 0);
4986 pci_enable_wake(pdev, PCI_D3cold, 0);
4988 if (netif_running(ndev)) {
4989 err = ql_adapter_up(qdev);
4994 mod_timer(&qdev->timer, jiffies + (5*HZ));
4995 netif_device_attach(ndev);
4999 #endif /* CONFIG_PM */
5001 static void qlge_shutdown(struct pci_dev *pdev)
5003 qlge_suspend(pdev, PMSG_SUSPEND);
5006 static struct pci_driver qlge_driver = {
5008 .id_table = qlge_pci_tbl,
5009 .probe = qlge_probe,
5010 .remove = qlge_remove,
5012 .suspend = qlge_suspend,
5013 .resume = qlge_resume,
5015 .shutdown = qlge_shutdown,
5016 .err_handler = &qlge_err_handler
5019 module_pci_driver(qlge_driver);