2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
8 #include <linux/types.h>
10 #include "qlcnic_sriov.h"
12 #include "qlcnic_83xx_hw.h"
14 #define QLC_BC_COMMAND 0
15 #define QLC_BC_RESPONSE 1
17 #define QLC_MBOX_RESP_TIMEOUT (10 * HZ)
18 #define QLC_MBOX_CH_FREE_TIMEOUT (10 * HZ)
21 #define QLC_BC_CFREE 1
23 #define QLC_BC_HDR_SZ 16
24 #define QLC_BC_PAYLOAD_SZ (1024 - QLC_BC_HDR_SZ)
26 #define QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF 2048
27 #define QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF 512
29 #define QLC_83XX_VF_RESET_FAIL_THRESH 8
30 #define QLC_BC_CMD_MAX_RETRY_CNT 5
32 static void qlcnic_sriov_handle_async_issue_cmd(struct work_struct *work);
33 static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter *);
34 static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args *, u32);
35 static void qlcnic_sriov_vf_poll_dev_state(struct work_struct *);
36 static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter *);
37 static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans *);
38 static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter *,
39 struct qlcnic_cmd_args *);
40 static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter *, u8);
41 static void qlcnic_sriov_process_bc_cmd(struct work_struct *);
42 static int qlcnic_sriov_vf_shutdown(struct pci_dev *);
43 static int qlcnic_sriov_vf_resume(struct qlcnic_adapter *);
44 static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter *,
45 struct qlcnic_cmd_args *);
47 static struct qlcnic_hardware_ops qlcnic_sriov_vf_hw_ops = {
48 .read_crb = qlcnic_83xx_read_crb,
49 .write_crb = qlcnic_83xx_write_crb,
50 .read_reg = qlcnic_83xx_rd_reg_indirect,
51 .write_reg = qlcnic_83xx_wrt_reg_indirect,
52 .get_mac_address = qlcnic_83xx_get_mac_address,
53 .setup_intr = qlcnic_83xx_setup_intr,
54 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
55 .mbx_cmd = qlcnic_sriov_issue_cmd,
56 .get_func_no = qlcnic_83xx_get_func_no,
57 .api_lock = qlcnic_83xx_cam_lock,
58 .api_unlock = qlcnic_83xx_cam_unlock,
59 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
60 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
61 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
62 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
63 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
64 .setup_link_event = qlcnic_83xx_setup_link_event,
65 .get_nic_info = qlcnic_83xx_get_nic_info,
66 .get_pci_info = qlcnic_83xx_get_pci_info,
67 .set_nic_info = qlcnic_83xx_set_nic_info,
68 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
69 .napi_enable = qlcnic_83xx_napi_enable,
70 .napi_disable = qlcnic_83xx_napi_disable,
71 .config_intr_coal = qlcnic_83xx_config_intr_coal,
72 .config_rss = qlcnic_83xx_config_rss,
73 .config_hw_lro = qlcnic_83xx_config_hw_lro,
74 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
75 .change_l2_filter = qlcnic_83xx_change_l2_filter,
76 .get_board_info = qlcnic_83xx_get_port_info,
77 .free_mac_list = qlcnic_sriov_vf_free_mac_list,
78 .enable_sds_intr = qlcnic_83xx_enable_sds_intr,
79 .disable_sds_intr = qlcnic_83xx_disable_sds_intr,
80 .encap_rx_offload = qlcnic_83xx_encap_rx_offload,
81 .encap_tx_offload = qlcnic_83xx_encap_tx_offload,
84 static struct qlcnic_nic_template qlcnic_sriov_vf_ops = {
85 .config_bridged_mode = qlcnic_config_bridged_mode,
86 .config_led = qlcnic_config_led,
87 .cancel_idc_work = qlcnic_sriov_vf_cancel_fw_work,
88 .napi_add = qlcnic_83xx_napi_add,
89 .napi_del = qlcnic_83xx_napi_del,
90 .shutdown = qlcnic_sriov_vf_shutdown,
91 .resume = qlcnic_sriov_vf_resume,
92 .config_ipaddr = qlcnic_83xx_config_ipaddr,
93 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
96 static const struct qlcnic_mailbox_metadata qlcnic_sriov_bc_mbx_tbl[] = {
97 {QLCNIC_BC_CMD_CHANNEL_INIT, 2, 2},
98 {QLCNIC_BC_CMD_CHANNEL_TERM, 2, 2},
99 {QLCNIC_BC_CMD_GET_ACL, 3, 14},
100 {QLCNIC_BC_CMD_CFG_GUEST_VLAN, 2, 2},
103 static inline bool qlcnic_sriov_bc_msg_check(u32 val)
105 return (val & (1 << QLC_BC_MSG)) ? true : false;
108 static inline bool qlcnic_sriov_channel_free_check(u32 val)
110 return (val & (1 << QLC_BC_CFREE)) ? true : false;
113 static inline bool qlcnic_sriov_flr_check(u32 val)
115 return (val & (1 << QLC_BC_FLR)) ? true : false;
118 static inline u8 qlcnic_sriov_target_func_id(u32 val)
120 return (val >> 4) & 0xff;
123 static int qlcnic_sriov_virtid_fn(struct qlcnic_adapter *adapter, int vf_id)
125 struct pci_dev *dev = adapter->pdev;
129 if (qlcnic_sriov_vf_check(adapter))
132 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
135 pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &offset);
136 pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &stride);
138 return (dev->devfn + offset + stride * vf_id) & 0xff;
141 int qlcnic_sriov_init(struct qlcnic_adapter *adapter, int num_vfs)
143 struct qlcnic_sriov *sriov;
144 struct qlcnic_back_channel *bc;
145 struct workqueue_struct *wq;
146 struct qlcnic_vport *vp;
147 struct qlcnic_vf_info *vf;
150 if (!qlcnic_sriov_enable_check(adapter))
153 sriov = kzalloc(sizeof(struct qlcnic_sriov), GFP_KERNEL);
157 adapter->ahw->sriov = sriov;
158 sriov->num_vfs = num_vfs;
160 sriov->vf_info = kzalloc(sizeof(struct qlcnic_vf_info) *
161 num_vfs, GFP_KERNEL);
162 if (!sriov->vf_info) {
164 goto qlcnic_free_sriov;
167 wq = create_singlethread_workqueue("bc-trans");
170 dev_err(&adapter->pdev->dev,
171 "Cannot create bc-trans workqueue\n");
172 goto qlcnic_free_vf_info;
175 bc->bc_trans_wq = wq;
177 wq = create_singlethread_workqueue("async");
180 dev_err(&adapter->pdev->dev, "Cannot create async workqueue\n");
181 goto qlcnic_destroy_trans_wq;
184 bc->bc_async_wq = wq;
185 INIT_LIST_HEAD(&bc->async_cmd_list);
186 INIT_WORK(&bc->vf_async_work, qlcnic_sriov_handle_async_issue_cmd);
187 spin_lock_init(&bc->queue_lock);
188 bc->adapter = adapter;
190 for (i = 0; i < num_vfs; i++) {
191 vf = &sriov->vf_info[i];
192 vf->adapter = adapter;
193 vf->pci_func = qlcnic_sriov_virtid_fn(adapter, i);
194 mutex_init(&vf->send_cmd_lock);
195 spin_lock_init(&vf->vlan_list_lock);
196 INIT_LIST_HEAD(&vf->rcv_act.wait_list);
197 INIT_LIST_HEAD(&vf->rcv_pend.wait_list);
198 spin_lock_init(&vf->rcv_act.lock);
199 spin_lock_init(&vf->rcv_pend.lock);
200 init_completion(&vf->ch_free_cmpl);
202 INIT_WORK(&vf->trans_work, qlcnic_sriov_process_bc_cmd);
204 if (qlcnic_sriov_pf_check(adapter)) {
205 vp = kzalloc(sizeof(struct qlcnic_vport), GFP_KERNEL);
208 goto qlcnic_destroy_async_wq;
210 sriov->vf_info[i].vp = vp;
211 vp->vlan_mode = QLC_GUEST_VLAN_MODE;
212 vp->max_tx_bw = MAX_BW;
213 vp->min_tx_bw = MIN_BW;
214 vp->spoofchk = false;
215 random_ether_addr(vp->mac);
216 dev_info(&adapter->pdev->dev,
217 "MAC Address %pM is configured for VF %d\n",
224 qlcnic_destroy_async_wq:
225 destroy_workqueue(bc->bc_async_wq);
227 qlcnic_destroy_trans_wq:
228 destroy_workqueue(bc->bc_trans_wq);
231 kfree(sriov->vf_info);
234 kfree(adapter->ahw->sriov);
238 void qlcnic_sriov_cleanup_list(struct qlcnic_trans_list *t_list)
240 struct qlcnic_bc_trans *trans;
241 struct qlcnic_cmd_args cmd;
244 spin_lock_irqsave(&t_list->lock, flags);
246 while (!list_empty(&t_list->wait_list)) {
247 trans = list_first_entry(&t_list->wait_list,
248 struct qlcnic_bc_trans, list);
249 list_del(&trans->list);
251 cmd.req.arg = (u32 *)trans->req_pay;
252 cmd.rsp.arg = (u32 *)trans->rsp_pay;
253 qlcnic_free_mbx_args(&cmd);
254 qlcnic_sriov_cleanup_transaction(trans);
257 spin_unlock_irqrestore(&t_list->lock, flags);
260 void __qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter)
262 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
263 struct qlcnic_back_channel *bc = &sriov->bc;
264 struct qlcnic_vf_info *vf;
267 if (!qlcnic_sriov_enable_check(adapter))
270 qlcnic_sriov_cleanup_async_list(bc);
271 destroy_workqueue(bc->bc_async_wq);
273 for (i = 0; i < sriov->num_vfs; i++) {
274 vf = &sriov->vf_info[i];
275 qlcnic_sriov_cleanup_list(&vf->rcv_pend);
276 cancel_work_sync(&vf->trans_work);
277 qlcnic_sriov_cleanup_list(&vf->rcv_act);
280 destroy_workqueue(bc->bc_trans_wq);
282 for (i = 0; i < sriov->num_vfs; i++)
283 kfree(sriov->vf_info[i].vp);
285 kfree(sriov->vf_info);
286 kfree(adapter->ahw->sriov);
289 static void qlcnic_sriov_vf_cleanup(struct qlcnic_adapter *adapter)
291 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
292 qlcnic_sriov_cfg_bc_intr(adapter, 0);
293 __qlcnic_sriov_cleanup(adapter);
296 void qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter)
298 if (!test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state))
301 qlcnic_sriov_free_vlans(adapter);
303 if (qlcnic_sriov_pf_check(adapter))
304 qlcnic_sriov_pf_cleanup(adapter);
306 if (qlcnic_sriov_vf_check(adapter))
307 qlcnic_sriov_vf_cleanup(adapter);
310 static int qlcnic_sriov_post_bc_msg(struct qlcnic_adapter *adapter, u32 *hdr,
311 u32 *pay, u8 pci_func, u8 size)
313 struct qlcnic_hardware_context *ahw = adapter->ahw;
314 struct qlcnic_mailbox *mbx = ahw->mailbox;
315 struct qlcnic_cmd_args cmd;
316 unsigned long timeout;
319 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
323 cmd.func_num = pci_func;
324 cmd.op_type = QLC_83XX_MBX_POST_BC_OP;
325 cmd.cmd_op = ((struct qlcnic_bc_hdr *)hdr)->cmd_op;
327 err = mbx->ops->enqueue_cmd(adapter, &cmd, &timeout);
329 dev_err(&adapter->pdev->dev,
330 "%s: Mailbox not available, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
331 __func__, cmd.cmd_op, cmd.type, ahw->pci_func,
336 if (!wait_for_completion_timeout(&cmd.completion, timeout)) {
337 dev_err(&adapter->pdev->dev,
338 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
339 __func__, cmd.cmd_op, cmd.type, ahw->pci_func,
341 flush_workqueue(mbx->work_q);
344 return cmd.rsp_opcode;
347 static void qlcnic_sriov_vf_cfg_buff_desc(struct qlcnic_adapter *adapter)
349 adapter->num_rxd = QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF;
350 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
351 adapter->num_jumbo_rxd = QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF;
352 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
353 adapter->num_txd = MAX_CMD_DESCRIPTORS;
354 adapter->max_rds_rings = MAX_RDS_RINGS;
357 int qlcnic_sriov_get_vf_vport_info(struct qlcnic_adapter *adapter,
358 struct qlcnic_info *npar_info, u16 vport_id)
360 struct device *dev = &adapter->pdev->dev;
361 struct qlcnic_cmd_args cmd;
365 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
369 cmd.req.arg[1] = vport_id << 16 | 0x1;
370 err = qlcnic_issue_cmd(adapter, &cmd);
372 dev_err(&adapter->pdev->dev,
373 "Failed to get vport info, err=%d\n", err);
374 qlcnic_free_mbx_args(&cmd);
378 status = cmd.rsp.arg[2] & 0xffff;
380 npar_info->min_tx_bw = MSW(cmd.rsp.arg[2]);
382 npar_info->max_tx_bw = LSW(cmd.rsp.arg[3]);
384 npar_info->max_tx_ques = MSW(cmd.rsp.arg[3]);
386 npar_info->max_tx_mac_filters = LSW(cmd.rsp.arg[4]);
388 npar_info->max_rx_mcast_mac_filters = MSW(cmd.rsp.arg[4]);
390 npar_info->max_rx_ucast_mac_filters = LSW(cmd.rsp.arg[5]);
392 npar_info->max_rx_ip_addr = MSW(cmd.rsp.arg[5]);
394 npar_info->max_rx_lro_flow = LSW(cmd.rsp.arg[6]);
396 npar_info->max_rx_status_rings = MSW(cmd.rsp.arg[6]);
398 npar_info->max_rx_buf_rings = LSW(cmd.rsp.arg[7]);
400 npar_info->max_rx_ques = MSW(cmd.rsp.arg[7]);
401 npar_info->max_tx_vlan_keys = LSW(cmd.rsp.arg[8]);
402 npar_info->max_local_ipv6_addrs = MSW(cmd.rsp.arg[8]);
403 npar_info->max_remote_ipv6_addrs = LSW(cmd.rsp.arg[9]);
405 dev_info(dev, "\n\tmin_tx_bw: %d, max_tx_bw: %d max_tx_ques: %d,\n"
406 "\tmax_tx_mac_filters: %d max_rx_mcast_mac_filters: %d,\n"
407 "\tmax_rx_ucast_mac_filters: 0x%x, max_rx_ip_addr: %d,\n"
408 "\tmax_rx_lro_flow: %d max_rx_status_rings: %d,\n"
409 "\tmax_rx_buf_rings: %d, max_rx_ques: %d, max_tx_vlan_keys %d\n"
410 "\tlocal_ipv6_addr: %d, remote_ipv6_addr: %d\n",
411 npar_info->min_tx_bw, npar_info->max_tx_bw,
412 npar_info->max_tx_ques, npar_info->max_tx_mac_filters,
413 npar_info->max_rx_mcast_mac_filters,
414 npar_info->max_rx_ucast_mac_filters, npar_info->max_rx_ip_addr,
415 npar_info->max_rx_lro_flow, npar_info->max_rx_status_rings,
416 npar_info->max_rx_buf_rings, npar_info->max_rx_ques,
417 npar_info->max_tx_vlan_keys, npar_info->max_local_ipv6_addrs,
418 npar_info->max_remote_ipv6_addrs);
420 qlcnic_free_mbx_args(&cmd);
424 static int qlcnic_sriov_set_pvid_mode(struct qlcnic_adapter *adapter,
425 struct qlcnic_cmd_args *cmd)
427 adapter->rx_pvid = MSW(cmd->rsp.arg[1]) & 0xffff;
428 adapter->flags &= ~QLCNIC_TAGGING_ENABLED;
432 static int qlcnic_sriov_set_guest_vlan_mode(struct qlcnic_adapter *adapter,
433 struct qlcnic_cmd_args *cmd)
435 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
436 int i, num_vlans, ret;
439 if (sriov->allowed_vlans)
442 sriov->any_vlan = cmd->rsp.arg[2] & 0xf;
443 sriov->num_allowed_vlans = cmd->rsp.arg[2] >> 16;
444 dev_info(&adapter->pdev->dev, "Number of allowed Guest VLANs = %d\n",
445 sriov->num_allowed_vlans);
447 ret = qlcnic_sriov_alloc_vlans(adapter);
451 if (!sriov->any_vlan)
454 num_vlans = sriov->num_allowed_vlans;
455 sriov->allowed_vlans = kzalloc(sizeof(u16) * num_vlans, GFP_KERNEL);
456 if (!sriov->allowed_vlans)
459 vlans = (u16 *)&cmd->rsp.arg[3];
460 for (i = 0; i < num_vlans; i++)
461 sriov->allowed_vlans[i] = vlans[i];
466 static int qlcnic_sriov_get_vf_acl(struct qlcnic_adapter *adapter)
468 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
469 struct qlcnic_cmd_args cmd;
472 memset(&cmd, 0, sizeof(cmd));
473 ret = qlcnic_sriov_alloc_bc_mbx_args(&cmd, QLCNIC_BC_CMD_GET_ACL);
477 ret = qlcnic_issue_cmd(adapter, &cmd);
479 dev_err(&adapter->pdev->dev, "Failed to get ACL, err=%d\n",
482 sriov->vlan_mode = cmd.rsp.arg[1] & 0x3;
483 switch (sriov->vlan_mode) {
484 case QLC_GUEST_VLAN_MODE:
485 ret = qlcnic_sriov_set_guest_vlan_mode(adapter, &cmd);
488 ret = qlcnic_sriov_set_pvid_mode(adapter, &cmd);
493 qlcnic_free_mbx_args(&cmd);
497 static int qlcnic_sriov_vf_init_driver(struct qlcnic_adapter *adapter)
499 struct qlcnic_hardware_context *ahw = adapter->ahw;
500 struct qlcnic_info nic_info;
503 err = qlcnic_sriov_get_vf_vport_info(adapter, &nic_info, 0);
507 ahw->max_mc_count = nic_info.max_rx_mcast_mac_filters;
509 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
513 if (qlcnic_83xx_get_port_info(adapter))
516 qlcnic_sriov_vf_cfg_buff_desc(adapter);
517 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
518 dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
519 adapter->ahw->fw_hal_version);
521 ahw->physical_port = (u8) nic_info.phys_port;
522 ahw->switch_mode = nic_info.switch_mode;
523 ahw->max_mtu = nic_info.max_mtu;
524 ahw->op_mode = nic_info.op_mode;
525 ahw->capabilities = nic_info.capabilities;
529 static int qlcnic_sriov_setup_vf(struct qlcnic_adapter *adapter,
534 adapter->flags |= QLCNIC_VLAN_FILTERING;
535 adapter->ahw->total_nic_func = 1;
536 INIT_LIST_HEAD(&adapter->vf_mc_list);
537 if (!qlcnic_use_msi_x && !!qlcnic_use_msi)
538 dev_warn(&adapter->pdev->dev,
539 "Device does not support MSI interrupts\n");
541 /* compute and set default and max tx/sds rings */
542 qlcnic_set_tx_ring_count(adapter, QLCNIC_SINGLE_RING);
543 qlcnic_set_sds_ring_count(adapter, QLCNIC_SINGLE_RING);
545 err = qlcnic_setup_intr(adapter);
547 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n");
548 goto err_out_disable_msi;
551 err = qlcnic_83xx_setup_mbx_intr(adapter);
553 goto err_out_disable_msi;
555 err = qlcnic_sriov_init(adapter, 1);
557 goto err_out_disable_mbx_intr;
559 err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
561 goto err_out_cleanup_sriov;
563 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
565 goto err_out_disable_bc_intr;
567 err = qlcnic_sriov_vf_init_driver(adapter);
569 goto err_out_send_channel_term;
571 err = qlcnic_sriov_get_vf_acl(adapter);
573 goto err_out_send_channel_term;
575 err = qlcnic_setup_netdev(adapter, adapter->netdev, pci_using_dac);
577 goto err_out_send_channel_term;
579 pci_set_drvdata(adapter->pdev, adapter);
580 dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n",
581 adapter->netdev->name);
583 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
584 adapter->ahw->idc.delay);
587 err_out_send_channel_term:
588 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
590 err_out_disable_bc_intr:
591 qlcnic_sriov_cfg_bc_intr(adapter, 0);
593 err_out_cleanup_sriov:
594 __qlcnic_sriov_cleanup(adapter);
596 err_out_disable_mbx_intr:
597 qlcnic_83xx_free_mbx_intr(adapter);
600 qlcnic_teardown_intr(adapter);
604 static int qlcnic_sriov_check_dev_ready(struct qlcnic_adapter *adapter)
610 if (++adapter->fw_fail_cnt > QLC_BC_CMD_MAX_RETRY_CNT)
612 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
613 } while (state != QLC_83XX_IDC_DEV_READY);
618 int qlcnic_sriov_vf_init(struct qlcnic_adapter *adapter, int pci_using_dac)
620 struct qlcnic_hardware_context *ahw = adapter->ahw;
623 set_bit(QLC_83XX_MODULE_LOADED, &ahw->idc.status);
624 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
625 ahw->reset_context = 0;
626 adapter->fw_fail_cnt = 0;
627 ahw->msix_supported = 1;
628 adapter->need_fw_reset = 0;
629 adapter->flags |= QLCNIC_TX_INTR_SHARED;
631 err = qlcnic_sriov_check_dev_ready(adapter);
635 err = qlcnic_sriov_setup_vf(adapter, pci_using_dac);
639 if (qlcnic_read_mac_addr(adapter))
640 dev_warn(&adapter->pdev->dev, "failed to read mac addr\n");
642 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
644 clear_bit(__QLCNIC_RESETTING, &adapter->state);
648 void qlcnic_sriov_vf_set_ops(struct qlcnic_adapter *adapter)
650 struct qlcnic_hardware_context *ahw = adapter->ahw;
652 ahw->op_mode = QLCNIC_SRIOV_VF_FUNC;
653 dev_info(&adapter->pdev->dev,
654 "HAL Version: %d Non Privileged SRIOV function\n",
655 ahw->fw_hal_version);
656 adapter->nic_ops = &qlcnic_sriov_vf_ops;
657 set_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state);
661 void qlcnic_sriov_vf_register_map(struct qlcnic_hardware_context *ahw)
663 ahw->hw_ops = &qlcnic_sriov_vf_hw_ops;
664 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
665 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
668 static u32 qlcnic_sriov_get_bc_paysize(u32 real_pay_size, u8 curr_frag)
672 pay_size = real_pay_size / ((curr_frag + 1) * QLC_BC_PAYLOAD_SZ);
675 pay_size = QLC_BC_PAYLOAD_SZ;
677 pay_size = real_pay_size % QLC_BC_PAYLOAD_SZ;
682 int qlcnic_sriov_func_to_index(struct qlcnic_adapter *adapter, u8 pci_func)
684 struct qlcnic_vf_info *vf_info = adapter->ahw->sriov->vf_info;
687 if (qlcnic_sriov_vf_check(adapter))
690 for (i = 0; i < adapter->ahw->sriov->num_vfs; i++) {
691 if (vf_info[i].pci_func == pci_func)
698 static inline int qlcnic_sriov_alloc_bc_trans(struct qlcnic_bc_trans **trans)
700 *trans = kzalloc(sizeof(struct qlcnic_bc_trans), GFP_ATOMIC);
704 init_completion(&(*trans)->resp_cmpl);
708 static inline int qlcnic_sriov_alloc_bc_msg(struct qlcnic_bc_hdr **hdr,
711 *hdr = kzalloc(sizeof(struct qlcnic_bc_hdr) * size, GFP_ATOMIC);
718 static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args *mbx, u32 type)
720 const struct qlcnic_mailbox_metadata *mbx_tbl;
723 mbx_tbl = qlcnic_sriov_bc_mbx_tbl;
724 size = ARRAY_SIZE(qlcnic_sriov_bc_mbx_tbl);
726 for (i = 0; i < size; i++) {
727 if (type == mbx_tbl[i].cmd) {
728 mbx->op_type = QLC_BC_CMD;
729 mbx->req.num = mbx_tbl[i].in_args;
730 mbx->rsp.num = mbx_tbl[i].out_args;
731 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
735 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
742 mbx->req.arg[0] = (type | (mbx->req.num << 16) |
744 mbx->rsp.arg[0] = (type & 0xffff) | mbx->rsp.num << 16;
751 static int qlcnic_sriov_prepare_bc_hdr(struct qlcnic_bc_trans *trans,
752 struct qlcnic_cmd_args *cmd,
753 u16 seq, u8 msg_type)
755 struct qlcnic_bc_hdr *hdr;
757 u32 num_regs, bc_pay_sz;
759 u8 cmd_op, num_frags, t_num_frags;
761 bc_pay_sz = QLC_BC_PAYLOAD_SZ;
762 if (msg_type == QLC_BC_COMMAND) {
763 trans->req_pay = (struct qlcnic_bc_payload *)cmd->req.arg;
764 trans->rsp_pay = (struct qlcnic_bc_payload *)cmd->rsp.arg;
765 num_regs = cmd->req.num;
766 trans->req_pay_size = (num_regs * 4);
767 num_regs = cmd->rsp.num;
768 trans->rsp_pay_size = (num_regs * 4);
769 cmd_op = cmd->req.arg[0] & 0xff;
770 remainder = (trans->req_pay_size) % (bc_pay_sz);
771 num_frags = (trans->req_pay_size) / (bc_pay_sz);
774 t_num_frags = num_frags;
775 if (qlcnic_sriov_alloc_bc_msg(&trans->req_hdr, num_frags))
777 remainder = (trans->rsp_pay_size) % (bc_pay_sz);
778 num_frags = (trans->rsp_pay_size) / (bc_pay_sz);
781 if (qlcnic_sriov_alloc_bc_msg(&trans->rsp_hdr, num_frags))
783 num_frags = t_num_frags;
784 hdr = trans->req_hdr;
786 cmd->req.arg = (u32 *)trans->req_pay;
787 cmd->rsp.arg = (u32 *)trans->rsp_pay;
788 cmd_op = cmd->req.arg[0] & 0xff;
789 cmd->cmd_op = cmd_op;
790 remainder = (trans->rsp_pay_size) % (bc_pay_sz);
791 num_frags = (trans->rsp_pay_size) / (bc_pay_sz);
794 cmd->req.num = trans->req_pay_size / 4;
795 cmd->rsp.num = trans->rsp_pay_size / 4;
796 hdr = trans->rsp_hdr;
797 cmd->op_type = trans->req_hdr->op_type;
800 trans->trans_id = seq;
801 trans->cmd_id = cmd_op;
802 for (i = 0; i < num_frags; i++) {
804 hdr[i].msg_type = msg_type;
805 hdr[i].op_type = cmd->op_type;
807 hdr[i].num_frags = num_frags;
808 hdr[i].frag_num = i + 1;
809 hdr[i].cmd_op = cmd_op;
815 static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans *trans)
819 kfree(trans->req_hdr);
820 kfree(trans->rsp_hdr);
824 static int qlcnic_sriov_clear_trans(struct qlcnic_vf_info *vf,
825 struct qlcnic_bc_trans *trans, u8 type)
827 struct qlcnic_trans_list *t_list;
831 if (type == QLC_BC_RESPONSE) {
832 t_list = &vf->rcv_act;
833 spin_lock_irqsave(&t_list->lock, flags);
835 list_del(&trans->list);
836 if (t_list->count > 0)
838 spin_unlock_irqrestore(&t_list->lock, flags);
840 if (type == QLC_BC_COMMAND) {
841 while (test_and_set_bit(QLC_BC_VF_SEND, &vf->state))
844 clear_bit(QLC_BC_VF_SEND, &vf->state);
849 static void qlcnic_sriov_schedule_bc_cmd(struct qlcnic_sriov *sriov,
850 struct qlcnic_vf_info *vf,
853 if (test_bit(QLC_BC_VF_FLR, &vf->state) ||
854 vf->adapter->need_fw_reset)
857 queue_work(sriov->bc.bc_trans_wq, &vf->trans_work);
860 static inline void qlcnic_sriov_wait_for_resp(struct qlcnic_bc_trans *trans)
862 struct completion *cmpl = &trans->resp_cmpl;
864 if (wait_for_completion_timeout(cmpl, QLC_MBOX_RESP_TIMEOUT))
865 trans->trans_state = QLC_END;
867 trans->trans_state = QLC_ABORT;
872 static void qlcnic_sriov_handle_multi_frags(struct qlcnic_bc_trans *trans,
875 if (type == QLC_BC_RESPONSE) {
876 trans->curr_rsp_frag++;
877 if (trans->curr_rsp_frag < trans->rsp_hdr->num_frags)
878 trans->trans_state = QLC_INIT;
880 trans->trans_state = QLC_END;
882 trans->curr_req_frag++;
883 if (trans->curr_req_frag < trans->req_hdr->num_frags)
884 trans->trans_state = QLC_INIT;
886 trans->trans_state = QLC_WAIT_FOR_RESP;
890 static void qlcnic_sriov_wait_for_channel_free(struct qlcnic_bc_trans *trans,
893 struct qlcnic_vf_info *vf = trans->vf;
894 struct completion *cmpl = &vf->ch_free_cmpl;
896 if (!wait_for_completion_timeout(cmpl, QLC_MBOX_CH_FREE_TIMEOUT)) {
897 trans->trans_state = QLC_ABORT;
901 clear_bit(QLC_BC_VF_CHANNEL, &vf->state);
902 qlcnic_sriov_handle_multi_frags(trans, type);
905 static void qlcnic_sriov_pull_bc_msg(struct qlcnic_adapter *adapter,
906 u32 *hdr, u32 *pay, u32 size)
908 struct qlcnic_hardware_context *ahw = adapter->ahw;
910 u8 i, max = 2, hdr_size, j;
912 hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
913 max = (size / sizeof(u32)) + hdr_size;
915 fw_mbx = readl(QLCNIC_MBX_FW(ahw, 0));
916 for (i = 2, j = 0; j < hdr_size; i++, j++)
917 *(hdr++) = readl(QLCNIC_MBX_FW(ahw, i));
918 for (; j < max; i++, j++)
919 *(pay++) = readl(QLCNIC_MBX_FW(ahw, i));
922 static int __qlcnic_sriov_issue_bc_post(struct qlcnic_vf_info *vf)
928 if (!test_and_set_bit(QLC_BC_VF_CHANNEL, &vf->state)) {
938 static int qlcnic_sriov_issue_bc_post(struct qlcnic_bc_trans *trans, u8 type)
940 struct qlcnic_vf_info *vf = trans->vf;
941 u32 pay_size, hdr_size;
944 u8 pci_func = trans->func_id;
946 if (__qlcnic_sriov_issue_bc_post(vf))
949 if (type == QLC_BC_COMMAND) {
950 hdr = (u32 *)(trans->req_hdr + trans->curr_req_frag);
951 pay = (u32 *)(trans->req_pay + trans->curr_req_frag);
952 hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
953 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
954 trans->curr_req_frag);
955 pay_size = (pay_size / sizeof(u32));
957 hdr = (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag);
958 pay = (u32 *)(trans->rsp_pay + trans->curr_rsp_frag);
959 hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
960 pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size,
961 trans->curr_rsp_frag);
962 pay_size = (pay_size / sizeof(u32));
965 ret = qlcnic_sriov_post_bc_msg(vf->adapter, hdr, pay,
970 static int __qlcnic_sriov_send_bc_msg(struct qlcnic_bc_trans *trans,
971 struct qlcnic_vf_info *vf, u8 type)
977 if (test_bit(QLC_BC_VF_FLR, &vf->state) ||
978 vf->adapter->need_fw_reset)
979 trans->trans_state = QLC_ABORT;
981 switch (trans->trans_state) {
983 trans->trans_state = QLC_WAIT_FOR_CHANNEL_FREE;
984 if (qlcnic_sriov_issue_bc_post(trans, type))
985 trans->trans_state = QLC_ABORT;
987 case QLC_WAIT_FOR_CHANNEL_FREE:
988 qlcnic_sriov_wait_for_channel_free(trans, type);
990 case QLC_WAIT_FOR_RESP:
991 qlcnic_sriov_wait_for_resp(trans);
1000 clear_bit(QLC_BC_VF_CHANNEL, &vf->state);
1010 static int qlcnic_sriov_send_bc_cmd(struct qlcnic_adapter *adapter,
1011 struct qlcnic_bc_trans *trans, int pci_func)
1013 struct qlcnic_vf_info *vf;
1014 int err, index = qlcnic_sriov_func_to_index(adapter, pci_func);
1019 vf = &adapter->ahw->sriov->vf_info[index];
1021 trans->func_id = pci_func;
1023 if (!test_bit(QLC_BC_VF_STATE, &vf->state)) {
1024 if (qlcnic_sriov_pf_check(adapter))
1026 if (qlcnic_sriov_vf_check(adapter) &&
1027 trans->cmd_id != QLCNIC_BC_CMD_CHANNEL_INIT)
1031 mutex_lock(&vf->send_cmd_lock);
1032 vf->send_cmd = trans;
1033 err = __qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_COMMAND);
1034 qlcnic_sriov_clear_trans(vf, trans, QLC_BC_COMMAND);
1035 mutex_unlock(&vf->send_cmd_lock);
1039 static void __qlcnic_sriov_process_bc_cmd(struct qlcnic_adapter *adapter,
1040 struct qlcnic_bc_trans *trans,
1041 struct qlcnic_cmd_args *cmd)
1043 #ifdef CONFIG_QLCNIC_SRIOV
1044 if (qlcnic_sriov_pf_check(adapter)) {
1045 qlcnic_sriov_pf_process_bc_cmd(adapter, trans, cmd);
1049 cmd->rsp.arg[0] |= (0x9 << 25);
1053 static void qlcnic_sriov_process_bc_cmd(struct work_struct *work)
1055 struct qlcnic_vf_info *vf = container_of(work, struct qlcnic_vf_info,
1057 struct qlcnic_bc_trans *trans = NULL;
1058 struct qlcnic_adapter *adapter = vf->adapter;
1059 struct qlcnic_cmd_args cmd;
1062 if (adapter->need_fw_reset)
1065 if (test_bit(QLC_BC_VF_FLR, &vf->state))
1068 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
1069 trans = list_first_entry(&vf->rcv_act.wait_list,
1070 struct qlcnic_bc_trans, list);
1071 adapter = vf->adapter;
1073 if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, trans->req_hdr->seq_id,
1077 __qlcnic_sriov_process_bc_cmd(adapter, trans, &cmd);
1078 trans->trans_state = QLC_INIT;
1079 __qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_RESPONSE);
1082 qlcnic_free_mbx_args(&cmd);
1083 req = qlcnic_sriov_clear_trans(vf, trans, QLC_BC_RESPONSE);
1084 qlcnic_sriov_cleanup_transaction(trans);
1086 qlcnic_sriov_schedule_bc_cmd(adapter->ahw->sriov, vf,
1087 qlcnic_sriov_process_bc_cmd);
1090 static void qlcnic_sriov_handle_bc_resp(struct qlcnic_bc_hdr *hdr,
1091 struct qlcnic_vf_info *vf)
1093 struct qlcnic_bc_trans *trans;
1096 if (test_and_set_bit(QLC_BC_VF_SEND, &vf->state))
1099 trans = vf->send_cmd;
1104 if (trans->trans_id != hdr->seq_id)
1107 pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size,
1108 trans->curr_rsp_frag);
1109 qlcnic_sriov_pull_bc_msg(vf->adapter,
1110 (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag),
1111 (u32 *)(trans->rsp_pay + trans->curr_rsp_frag),
1113 if (++trans->curr_rsp_frag < trans->rsp_hdr->num_frags)
1116 complete(&trans->resp_cmpl);
1119 clear_bit(QLC_BC_VF_SEND, &vf->state);
1122 int __qlcnic_sriov_add_act_list(struct qlcnic_sriov *sriov,
1123 struct qlcnic_vf_info *vf,
1124 struct qlcnic_bc_trans *trans)
1126 struct qlcnic_trans_list *t_list = &vf->rcv_act;
1129 list_add_tail(&trans->list, &t_list->wait_list);
1130 if (t_list->count == 1)
1131 qlcnic_sriov_schedule_bc_cmd(sriov, vf,
1132 qlcnic_sriov_process_bc_cmd);
1136 static int qlcnic_sriov_add_act_list(struct qlcnic_sriov *sriov,
1137 struct qlcnic_vf_info *vf,
1138 struct qlcnic_bc_trans *trans)
1140 struct qlcnic_trans_list *t_list = &vf->rcv_act;
1142 spin_lock(&t_list->lock);
1144 __qlcnic_sriov_add_act_list(sriov, vf, trans);
1146 spin_unlock(&t_list->lock);
1150 static void qlcnic_sriov_handle_pending_trans(struct qlcnic_sriov *sriov,
1151 struct qlcnic_vf_info *vf,
1152 struct qlcnic_bc_hdr *hdr)
1154 struct qlcnic_bc_trans *trans = NULL;
1155 struct list_head *node;
1156 u32 pay_size, curr_frag;
1157 u8 found = 0, active = 0;
1159 spin_lock(&vf->rcv_pend.lock);
1160 if (vf->rcv_pend.count > 0) {
1161 list_for_each(node, &vf->rcv_pend.wait_list) {
1162 trans = list_entry(node, struct qlcnic_bc_trans, list);
1163 if (trans->trans_id == hdr->seq_id) {
1171 curr_frag = trans->curr_req_frag;
1172 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
1174 qlcnic_sriov_pull_bc_msg(vf->adapter,
1175 (u32 *)(trans->req_hdr + curr_frag),
1176 (u32 *)(trans->req_pay + curr_frag),
1178 trans->curr_req_frag++;
1179 if (trans->curr_req_frag >= hdr->num_frags) {
1180 vf->rcv_pend.count--;
1181 list_del(&trans->list);
1185 spin_unlock(&vf->rcv_pend.lock);
1188 if (qlcnic_sriov_add_act_list(sriov, vf, trans))
1189 qlcnic_sriov_cleanup_transaction(trans);
1194 static void qlcnic_sriov_handle_bc_cmd(struct qlcnic_sriov *sriov,
1195 struct qlcnic_bc_hdr *hdr,
1196 struct qlcnic_vf_info *vf)
1198 struct qlcnic_bc_trans *trans;
1199 struct qlcnic_adapter *adapter = vf->adapter;
1200 struct qlcnic_cmd_args cmd;
1205 if (adapter->need_fw_reset)
1208 if (!test_bit(QLC_BC_VF_STATE, &vf->state) &&
1209 hdr->op_type != QLC_BC_CMD &&
1210 hdr->cmd_op != QLCNIC_BC_CMD_CHANNEL_INIT)
1213 if (hdr->frag_num > 1) {
1214 qlcnic_sriov_handle_pending_trans(sriov, vf, hdr);
1218 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
1219 cmd_op = hdr->cmd_op;
1220 if (qlcnic_sriov_alloc_bc_trans(&trans))
1223 if (hdr->op_type == QLC_BC_CMD)
1224 err = qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op);
1226 err = qlcnic_alloc_mbx_args(&cmd, adapter, cmd_op);
1229 qlcnic_sriov_cleanup_transaction(trans);
1233 cmd.op_type = hdr->op_type;
1234 if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, hdr->seq_id,
1236 qlcnic_free_mbx_args(&cmd);
1237 qlcnic_sriov_cleanup_transaction(trans);
1241 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
1242 trans->curr_req_frag);
1243 qlcnic_sriov_pull_bc_msg(vf->adapter,
1244 (u32 *)(trans->req_hdr + trans->curr_req_frag),
1245 (u32 *)(trans->req_pay + trans->curr_req_frag),
1247 trans->func_id = vf->pci_func;
1249 trans->trans_id = hdr->seq_id;
1250 trans->curr_req_frag++;
1252 if (qlcnic_sriov_soft_flr_check(adapter, trans, vf))
1255 if (trans->curr_req_frag == trans->req_hdr->num_frags) {
1256 if (qlcnic_sriov_add_act_list(sriov, vf, trans)) {
1257 qlcnic_free_mbx_args(&cmd);
1258 qlcnic_sriov_cleanup_transaction(trans);
1261 spin_lock(&vf->rcv_pend.lock);
1262 list_add_tail(&trans->list, &vf->rcv_pend.wait_list);
1263 vf->rcv_pend.count++;
1264 spin_unlock(&vf->rcv_pend.lock);
1268 static void qlcnic_sriov_handle_msg_event(struct qlcnic_sriov *sriov,
1269 struct qlcnic_vf_info *vf)
1271 struct qlcnic_bc_hdr hdr;
1272 u32 *ptr = (u32 *)&hdr;
1275 for (i = 2; i < 6; i++)
1276 ptr[i - 2] = readl(QLCNIC_MBX_FW(vf->adapter->ahw, i));
1277 msg_type = hdr.msg_type;
1280 case QLC_BC_COMMAND:
1281 qlcnic_sriov_handle_bc_cmd(sriov, &hdr, vf);
1283 case QLC_BC_RESPONSE:
1284 qlcnic_sriov_handle_bc_resp(&hdr, vf);
1289 static void qlcnic_sriov_handle_flr_event(struct qlcnic_sriov *sriov,
1290 struct qlcnic_vf_info *vf)
1292 struct qlcnic_adapter *adapter = vf->adapter;
1294 if (qlcnic_sriov_pf_check(adapter))
1295 qlcnic_sriov_pf_handle_flr(sriov, vf);
1297 dev_err(&adapter->pdev->dev,
1298 "Invalid event to VF. VF should not get FLR event\n");
1301 void qlcnic_sriov_handle_bc_event(struct qlcnic_adapter *adapter, u32 event)
1303 struct qlcnic_vf_info *vf;
1304 struct qlcnic_sriov *sriov;
1308 sriov = adapter->ahw->sriov;
1309 pci_func = qlcnic_sriov_target_func_id(event);
1310 index = qlcnic_sriov_func_to_index(adapter, pci_func);
1315 vf = &sriov->vf_info[index];
1316 vf->pci_func = pci_func;
1318 if (qlcnic_sriov_channel_free_check(event))
1319 complete(&vf->ch_free_cmpl);
1321 if (qlcnic_sriov_flr_check(event)) {
1322 qlcnic_sriov_handle_flr_event(sriov, vf);
1326 if (qlcnic_sriov_bc_msg_check(event))
1327 qlcnic_sriov_handle_msg_event(sriov, vf);
1330 int qlcnic_sriov_cfg_bc_intr(struct qlcnic_adapter *adapter, u8 enable)
1332 struct qlcnic_cmd_args cmd;
1335 if (!test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state))
1338 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_BC_EVENT_SETUP))
1342 cmd.req.arg[1] = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7);
1344 err = qlcnic_83xx_issue_cmd(adapter, &cmd);
1346 if (err != QLCNIC_RCODE_SUCCESS) {
1347 dev_err(&adapter->pdev->dev,
1348 "Failed to %s bc events, err=%d\n",
1349 (enable ? "enable" : "disable"), err);
1352 qlcnic_free_mbx_args(&cmd);
1356 static int qlcnic_sriov_retry_bc_cmd(struct qlcnic_adapter *adapter,
1357 struct qlcnic_bc_trans *trans)
1359 u8 max = QLC_BC_CMD_MAX_RETRY_CNT;
1362 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1363 if (state == QLC_83XX_IDC_DEV_READY) {
1365 clear_bit(QLC_BC_VF_CHANNEL, &trans->vf->state);
1366 trans->trans_state = QLC_INIT;
1367 if (++adapter->fw_fail_cnt > max)
1376 static int __qlcnic_sriov_issue_cmd(struct qlcnic_adapter *adapter,
1377 struct qlcnic_cmd_args *cmd)
1379 struct qlcnic_hardware_context *ahw = adapter->ahw;
1380 struct qlcnic_mailbox *mbx = ahw->mailbox;
1381 struct device *dev = &adapter->pdev->dev;
1382 struct qlcnic_bc_trans *trans;
1384 u32 rsp_data, opcode, mbx_err_code, rsp;
1385 u16 seq = ++adapter->ahw->sriov->bc.trans_counter;
1386 u8 func = ahw->pci_func;
1388 rsp = qlcnic_sriov_alloc_bc_trans(&trans);
1392 rsp = qlcnic_sriov_prepare_bc_hdr(trans, cmd, seq, QLC_BC_COMMAND);
1394 goto cleanup_transaction;
1397 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
1399 QLCDB(adapter, DRV, "MBX not Ready!(cmd 0x%x) for VF 0x%x\n",
1400 QLCNIC_MBX_RSP(cmd->req.arg[0]), func);
1404 err = qlcnic_sriov_send_bc_cmd(adapter, trans, func);
1406 dev_err(dev, "MBX command 0x%x timed out for VF %d\n",
1407 (cmd->req.arg[0] & 0xffff), func);
1408 rsp = QLCNIC_RCODE_TIMEOUT;
1410 /* After adapter reset PF driver may take some time to
1411 * respond to VF's request. Retry request till maximum retries.
1413 if ((trans->req_hdr->cmd_op == QLCNIC_BC_CMD_CHANNEL_INIT) &&
1414 !qlcnic_sriov_retry_bc_cmd(adapter, trans))
1420 rsp_data = cmd->rsp.arg[0];
1421 mbx_err_code = QLCNIC_MBX_STATUS(rsp_data);
1422 opcode = QLCNIC_MBX_RSP(cmd->req.arg[0]);
1424 if ((mbx_err_code == QLCNIC_MBX_RSP_OK) ||
1425 (mbx_err_code == QLCNIC_MBX_PORT_RSP_OK)) {
1426 rsp = QLCNIC_RCODE_SUCCESS;
1428 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
1429 rsp = QLCNIC_RCODE_SUCCESS;
1436 "MBX command 0x%x failed with err:0x%x for VF %d\n",
1437 opcode, mbx_err_code, func);
1442 if (rsp == QLCNIC_RCODE_TIMEOUT) {
1443 ahw->reset_context = 1;
1444 adapter->need_fw_reset = 1;
1445 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1448 cleanup_transaction:
1449 qlcnic_sriov_cleanup_transaction(trans);
1452 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
1453 qlcnic_free_mbx_args(cmd);
1461 static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter *adapter,
1462 struct qlcnic_cmd_args *cmd)
1464 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT)
1465 return qlcnic_sriov_async_issue_cmd(adapter, cmd);
1467 return __qlcnic_sriov_issue_cmd(adapter, cmd);
1470 static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter *adapter, u8 cmd_op)
1472 struct qlcnic_cmd_args cmd;
1473 struct qlcnic_vf_info *vf = &adapter->ahw->sriov->vf_info[0];
1476 memset(&cmd, 0, sizeof(cmd));
1477 if (qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op))
1480 ret = qlcnic_issue_cmd(adapter, &cmd);
1482 dev_err(&adapter->pdev->dev,
1483 "Failed bc channel %s %d\n", cmd_op ? "term" : "init",
1488 cmd_op = (cmd.rsp.arg[0] & 0xff);
1489 if (cmd.rsp.arg[0] >> 25 == 2)
1491 if (cmd_op == QLCNIC_BC_CMD_CHANNEL_INIT)
1492 set_bit(QLC_BC_VF_STATE, &vf->state);
1494 clear_bit(QLC_BC_VF_STATE, &vf->state);
1497 qlcnic_free_mbx_args(&cmd);
1501 static void qlcnic_vf_add_mc_list(struct net_device *netdev, const u8 *mac,
1502 enum qlcnic_mac_type mac_type)
1504 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1505 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
1506 struct qlcnic_vf_info *vf;
1510 vf = &adapter->ahw->sriov->vf_info[0];
1512 if (!qlcnic_sriov_check_any_vlan(vf)) {
1513 qlcnic_nic_add_mac(adapter, mac, 0, mac_type);
1515 spin_lock(&vf->vlan_list_lock);
1516 for (i = 0; i < sriov->num_allowed_vlans; i++) {
1517 vlan_id = vf->sriov_vlans[i];
1519 qlcnic_nic_add_mac(adapter, mac, vlan_id,
1522 spin_unlock(&vf->vlan_list_lock);
1523 if (qlcnic_84xx_check(adapter))
1524 qlcnic_nic_add_mac(adapter, mac, 0, mac_type);
1528 void qlcnic_sriov_cleanup_async_list(struct qlcnic_back_channel *bc)
1530 struct list_head *head = &bc->async_cmd_list;
1531 struct qlcnic_async_cmd *entry;
1533 flush_workqueue(bc->bc_async_wq);
1534 cancel_work_sync(&bc->vf_async_work);
1536 spin_lock(&bc->queue_lock);
1537 while (!list_empty(head)) {
1538 entry = list_entry(head->next, struct qlcnic_async_cmd,
1540 list_del(&entry->list);
1544 spin_unlock(&bc->queue_lock);
1547 void qlcnic_sriov_vf_set_multi(struct net_device *netdev)
1549 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1550 struct qlcnic_hardware_context *ahw = adapter->ahw;
1551 static const u8 bcast_addr[ETH_ALEN] = {
1552 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
1554 struct netdev_hw_addr *ha;
1555 u32 mode = VPORT_MISS_MODE_DROP;
1557 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
1560 if (netdev->flags & IFF_PROMISC) {
1561 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
1562 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1563 } else if ((netdev->flags & IFF_ALLMULTI) ||
1564 (netdev_mc_count(netdev) > ahw->max_mc_count)) {
1565 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1567 qlcnic_vf_add_mc_list(netdev, bcast_addr, QLCNIC_BROADCAST_MAC);
1568 if (!netdev_mc_empty(netdev)) {
1569 qlcnic_flush_mcast_mac(adapter);
1570 netdev_for_each_mc_addr(ha, netdev)
1571 qlcnic_vf_add_mc_list(netdev, ha->addr,
1572 QLCNIC_MULTICAST_MAC);
1576 /* configure unicast MAC address, if there is not sufficient space
1577 * to store all the unicast addresses then enable promiscuous mode
1579 if (netdev_uc_count(netdev) > ahw->max_uc_count) {
1580 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1581 } else if (!netdev_uc_empty(netdev)) {
1582 netdev_for_each_uc_addr(ha, netdev)
1583 qlcnic_vf_add_mc_list(netdev, ha->addr,
1584 QLCNIC_UNICAST_MAC);
1587 if (adapter->pdev->is_virtfn) {
1588 if (mode == VPORT_MISS_MODE_ACCEPT_ALL &&
1589 !adapter->fdb_mac_learn) {
1590 qlcnic_alloc_lb_filters_mem(adapter);
1591 adapter->drv_mac_learn = 1;
1592 adapter->rx_mac_learn = true;
1594 adapter->drv_mac_learn = 0;
1595 adapter->rx_mac_learn = false;
1599 qlcnic_nic_set_promisc(adapter, mode);
1602 static void qlcnic_sriov_handle_async_issue_cmd(struct work_struct *work)
1604 struct qlcnic_async_cmd *entry, *tmp;
1605 struct qlcnic_back_channel *bc;
1606 struct qlcnic_cmd_args *cmd;
1607 struct list_head *head;
1608 LIST_HEAD(del_list);
1610 bc = container_of(work, struct qlcnic_back_channel, vf_async_work);
1611 head = &bc->async_cmd_list;
1613 spin_lock(&bc->queue_lock);
1614 list_splice_init(head, &del_list);
1615 spin_unlock(&bc->queue_lock);
1617 list_for_each_entry_safe(entry, tmp, &del_list, list) {
1618 list_del(&entry->list);
1620 __qlcnic_sriov_issue_cmd(bc->adapter, cmd);
1624 if (!list_empty(head))
1625 queue_work(bc->bc_async_wq, &bc->vf_async_work);
1630 static struct qlcnic_async_cmd *
1631 qlcnic_sriov_alloc_async_cmd(struct qlcnic_back_channel *bc,
1632 struct qlcnic_cmd_args *cmd)
1634 struct qlcnic_async_cmd *entry = NULL;
1636 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
1642 spin_lock(&bc->queue_lock);
1643 list_add_tail(&entry->list, &bc->async_cmd_list);
1644 spin_unlock(&bc->queue_lock);
1649 static void qlcnic_sriov_schedule_async_cmd(struct qlcnic_back_channel *bc,
1650 struct qlcnic_cmd_args *cmd)
1652 struct qlcnic_async_cmd *entry = NULL;
1654 entry = qlcnic_sriov_alloc_async_cmd(bc, cmd);
1656 qlcnic_free_mbx_args(cmd);
1661 queue_work(bc->bc_async_wq, &bc->vf_async_work);
1664 static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter *adapter,
1665 struct qlcnic_cmd_args *cmd)
1668 struct qlcnic_back_channel *bc = &adapter->ahw->sriov->bc;
1670 if (adapter->need_fw_reset)
1673 qlcnic_sriov_schedule_async_cmd(bc, cmd);
1678 static int qlcnic_sriov_vf_reinit_driver(struct qlcnic_adapter *adapter)
1682 adapter->need_fw_reset = 0;
1683 qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
1684 qlcnic_83xx_enable_mbx_interrupt(adapter);
1686 err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
1690 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
1692 goto err_out_cleanup_bc_intr;
1694 err = qlcnic_sriov_vf_init_driver(adapter);
1696 goto err_out_term_channel;
1700 err_out_term_channel:
1701 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
1703 err_out_cleanup_bc_intr:
1704 qlcnic_sriov_cfg_bc_intr(adapter, 0);
1708 static void qlcnic_sriov_vf_attach(struct qlcnic_adapter *adapter)
1710 struct net_device *netdev = adapter->netdev;
1712 if (netif_running(netdev)) {
1713 if (!qlcnic_up(adapter, netdev))
1714 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
1717 netif_device_attach(netdev);
1720 static void qlcnic_sriov_vf_detach(struct qlcnic_adapter *adapter)
1722 struct qlcnic_hardware_context *ahw = adapter->ahw;
1723 struct qlcnic_intrpt_config *intr_tbl = ahw->intr_tbl;
1724 struct net_device *netdev = adapter->netdev;
1725 u8 i, max_ints = ahw->num_msix - 1;
1727 netif_device_detach(netdev);
1728 qlcnic_83xx_detach_mailbox_work(adapter);
1729 qlcnic_83xx_disable_mbx_intr(adapter);
1731 if (netif_running(netdev))
1732 qlcnic_down(adapter, netdev);
1734 for (i = 0; i < max_ints; i++) {
1736 intr_tbl[i].enabled = 0;
1737 intr_tbl[i].src = 0;
1739 ahw->reset_context = 0;
1742 static int qlcnic_sriov_vf_handle_dev_ready(struct qlcnic_adapter *adapter)
1744 struct qlcnic_hardware_context *ahw = adapter->ahw;
1745 struct device *dev = &adapter->pdev->dev;
1746 struct qlc_83xx_idc *idc = &ahw->idc;
1747 u8 func = ahw->pci_func;
1750 if ((idc->prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
1751 (idc->prev_state == QLC_83XX_IDC_DEV_INIT)) {
1752 if (!qlcnic_sriov_vf_reinit_driver(adapter)) {
1753 qlcnic_sriov_vf_attach(adapter);
1754 adapter->fw_fail_cnt = 0;
1756 "%s: Reinitialization of VF 0x%x done after FW reset\n",
1760 "%s: Reinitialization of VF 0x%x failed after FW reset\n",
1762 state = QLCRDX(ahw, QLC_83XX_IDC_DEV_STATE);
1763 dev_info(dev, "Current state 0x%x after FW reset\n",
1771 static int qlcnic_sriov_vf_handle_context_reset(struct qlcnic_adapter *adapter)
1773 struct qlcnic_hardware_context *ahw = adapter->ahw;
1774 struct qlcnic_mailbox *mbx = ahw->mailbox;
1775 struct device *dev = &adapter->pdev->dev;
1776 struct qlc_83xx_idc *idc = &ahw->idc;
1777 u8 func = ahw->pci_func;
1780 adapter->reset_ctx_cnt++;
1782 /* Skip the context reset and check if FW is hung */
1783 if (adapter->reset_ctx_cnt < 3) {
1784 adapter->need_fw_reset = 1;
1785 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1787 "Resetting context, wait here to check if FW is in failed state\n");
1791 /* Check if number of resets exceed the threshold.
1792 * If it exceeds the threshold just fail the VF.
1794 if (adapter->reset_ctx_cnt > QLC_83XX_VF_RESET_FAIL_THRESH) {
1795 clear_bit(QLC_83XX_MODULE_LOADED, &idc->status);
1796 adapter->tx_timeo_cnt = 0;
1797 adapter->fw_fail_cnt = 0;
1798 adapter->reset_ctx_cnt = 0;
1799 qlcnic_sriov_vf_detach(adapter);
1801 "Device context resets have exceeded the threshold, device interface will be shutdown\n");
1805 dev_info(dev, "Resetting context of VF 0x%x\n", func);
1806 dev_info(dev, "%s: Context reset count %d for VF 0x%x\n",
1807 __func__, adapter->reset_ctx_cnt, func);
1808 set_bit(__QLCNIC_RESETTING, &adapter->state);
1809 adapter->need_fw_reset = 1;
1810 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1811 qlcnic_sriov_vf_detach(adapter);
1812 adapter->need_fw_reset = 0;
1814 if (!qlcnic_sriov_vf_reinit_driver(adapter)) {
1815 qlcnic_sriov_vf_attach(adapter);
1816 adapter->tx_timeo_cnt = 0;
1817 adapter->reset_ctx_cnt = 0;
1818 adapter->fw_fail_cnt = 0;
1819 dev_info(dev, "Done resetting context for VF 0x%x\n", func);
1821 dev_err(dev, "%s: Reinitialization of VF 0x%x failed\n",
1823 state = QLCRDX(ahw, QLC_83XX_IDC_DEV_STATE);
1824 dev_info(dev, "%s: Current state 0x%x\n", __func__, state);
1830 static int qlcnic_sriov_vf_idc_ready_state(struct qlcnic_adapter *adapter)
1832 struct qlcnic_hardware_context *ahw = adapter->ahw;
1835 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY)
1836 ret = qlcnic_sriov_vf_handle_dev_ready(adapter);
1837 else if (ahw->reset_context)
1838 ret = qlcnic_sriov_vf_handle_context_reset(adapter);
1840 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1844 static int qlcnic_sriov_vf_idc_failed_state(struct qlcnic_adapter *adapter)
1846 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1848 dev_err(&adapter->pdev->dev, "Device is in failed state\n");
1849 if (idc->prev_state == QLC_83XX_IDC_DEV_READY)
1850 qlcnic_sriov_vf_detach(adapter);
1852 clear_bit(QLC_83XX_MODULE_LOADED, &idc->status);
1853 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1858 qlcnic_sriov_vf_idc_need_quiescent_state(struct qlcnic_adapter *adapter)
1860 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
1861 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1863 dev_info(&adapter->pdev->dev, "Device is in quiescent state\n");
1864 if (idc->prev_state == QLC_83XX_IDC_DEV_READY) {
1865 set_bit(__QLCNIC_RESETTING, &adapter->state);
1866 adapter->tx_timeo_cnt = 0;
1867 adapter->reset_ctx_cnt = 0;
1868 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1869 qlcnic_sriov_vf_detach(adapter);
1875 static int qlcnic_sriov_vf_idc_init_reset_state(struct qlcnic_adapter *adapter)
1877 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
1878 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1879 u8 func = adapter->ahw->pci_func;
1881 if (idc->prev_state == QLC_83XX_IDC_DEV_READY) {
1882 dev_err(&adapter->pdev->dev,
1883 "Firmware hang detected by VF 0x%x\n", func);
1884 set_bit(__QLCNIC_RESETTING, &adapter->state);
1885 adapter->tx_timeo_cnt = 0;
1886 adapter->reset_ctx_cnt = 0;
1887 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1888 qlcnic_sriov_vf_detach(adapter);
1893 static int qlcnic_sriov_vf_idc_unknown_state(struct qlcnic_adapter *adapter)
1895 dev_err(&adapter->pdev->dev, "%s: Device in unknown state\n", __func__);
1899 static void qlcnic_sriov_vf_periodic_tasks(struct qlcnic_adapter *adapter)
1901 if (adapter->fhash.fnum)
1902 qlcnic_prune_lb_filters(adapter);
1905 static void qlcnic_sriov_vf_poll_dev_state(struct work_struct *work)
1907 struct qlcnic_adapter *adapter;
1908 struct qlc_83xx_idc *idc;
1911 adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1912 idc = &adapter->ahw->idc;
1913 idc->curr_state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1915 switch (idc->curr_state) {
1916 case QLC_83XX_IDC_DEV_READY:
1917 ret = qlcnic_sriov_vf_idc_ready_state(adapter);
1919 case QLC_83XX_IDC_DEV_NEED_RESET:
1920 case QLC_83XX_IDC_DEV_INIT:
1921 ret = qlcnic_sriov_vf_idc_init_reset_state(adapter);
1923 case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1924 ret = qlcnic_sriov_vf_idc_need_quiescent_state(adapter);
1926 case QLC_83XX_IDC_DEV_FAILED:
1927 ret = qlcnic_sriov_vf_idc_failed_state(adapter);
1929 case QLC_83XX_IDC_DEV_QUISCENT:
1932 ret = qlcnic_sriov_vf_idc_unknown_state(adapter);
1935 idc->prev_state = idc->curr_state;
1936 qlcnic_sriov_vf_periodic_tasks(adapter);
1938 if (!ret && test_bit(QLC_83XX_MODULE_LOADED, &idc->status))
1939 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
1943 static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter *adapter)
1945 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1948 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1949 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1950 cancel_delayed_work_sync(&adapter->fw_work);
1953 static int qlcnic_sriov_check_vlan_id(struct qlcnic_sriov *sriov,
1954 struct qlcnic_vf_info *vf, u16 vlan_id)
1956 int i, err = -EINVAL;
1958 if (!vf->sriov_vlans)
1961 spin_lock_bh(&vf->vlan_list_lock);
1963 for (i = 0; i < sriov->num_allowed_vlans; i++) {
1964 if (vf->sriov_vlans[i] == vlan_id) {
1970 spin_unlock_bh(&vf->vlan_list_lock);
1974 static int qlcnic_sriov_validate_num_vlans(struct qlcnic_sriov *sriov,
1975 struct qlcnic_vf_info *vf)
1979 spin_lock_bh(&vf->vlan_list_lock);
1981 if (vf->num_vlan >= sriov->num_allowed_vlans)
1984 spin_unlock_bh(&vf->vlan_list_lock);
1988 static int qlcnic_sriov_validate_vlan_cfg(struct qlcnic_adapter *adapter,
1991 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
1992 struct qlcnic_vf_info *vf;
1997 vf = &adapter->ahw->sriov->vf_info[0];
1998 vlan_exist = qlcnic_sriov_check_any_vlan(vf);
1999 if (sriov->vlan_mode != QLC_GUEST_VLAN_MODE)
2003 if (qlcnic_83xx_vf_check(adapter) && vlan_exist)
2006 if (qlcnic_sriov_validate_num_vlans(sriov, vf))
2009 if (sriov->any_vlan) {
2010 for (i = 0; i < sriov->num_allowed_vlans; i++) {
2011 if (sriov->allowed_vlans[i] == vid)
2019 if (!vlan_exist || qlcnic_sriov_check_vlan_id(sriov, vf, vid))
2026 static void qlcnic_sriov_vlan_operation(struct qlcnic_vf_info *vf, u16 vlan_id,
2027 enum qlcnic_vlan_operations opcode)
2029 struct qlcnic_adapter *adapter = vf->adapter;
2030 struct qlcnic_sriov *sriov;
2032 sriov = adapter->ahw->sriov;
2034 if (!vf->sriov_vlans)
2037 spin_lock_bh(&vf->vlan_list_lock);
2041 qlcnic_sriov_add_vlan_id(sriov, vf, vlan_id);
2043 case QLC_VLAN_DELETE:
2044 qlcnic_sriov_del_vlan_id(sriov, vf, vlan_id);
2047 netdev_err(adapter->netdev, "Invalid VLAN operation\n");
2050 spin_unlock_bh(&vf->vlan_list_lock);
2054 int qlcnic_sriov_cfg_vf_guest_vlan(struct qlcnic_adapter *adapter,
2057 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2058 struct net_device *netdev = adapter->netdev;
2059 struct qlcnic_vf_info *vf;
2060 struct qlcnic_cmd_args cmd;
2063 memset(&cmd, 0, sizeof(cmd));
2067 vf = &adapter->ahw->sriov->vf_info[0];
2068 ret = qlcnic_sriov_validate_vlan_cfg(adapter, vid, enable);
2072 ret = qlcnic_sriov_alloc_bc_mbx_args(&cmd,
2073 QLCNIC_BC_CMD_CFG_GUEST_VLAN);
2077 cmd.req.arg[1] = (enable & 1) | vid << 16;
2079 qlcnic_sriov_cleanup_async_list(&sriov->bc);
2080 ret = qlcnic_issue_cmd(adapter, &cmd);
2082 dev_err(&adapter->pdev->dev,
2083 "Failed to configure guest VLAN, err=%d\n", ret);
2085 netif_addr_lock_bh(netdev);
2086 qlcnic_free_mac_list(adapter);
2087 netif_addr_unlock_bh(netdev);
2090 qlcnic_sriov_vlan_operation(vf, vid, QLC_VLAN_ADD);
2092 qlcnic_sriov_vlan_operation(vf, vid, QLC_VLAN_DELETE);
2094 netif_addr_lock_bh(netdev);
2095 qlcnic_set_multi(netdev);
2096 netif_addr_unlock_bh(netdev);
2099 qlcnic_free_mbx_args(&cmd);
2103 static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter *adapter)
2105 struct list_head *head = &adapter->mac_list;
2106 struct qlcnic_mac_vlan_list *cur;
2108 while (!list_empty(head)) {
2109 cur = list_entry(head->next, struct qlcnic_mac_vlan_list, list);
2110 qlcnic_sre_macaddr_change(adapter, cur->mac_addr, cur->vlan_id,
2112 list_del(&cur->list);
2118 static int qlcnic_sriov_vf_shutdown(struct pci_dev *pdev)
2120 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
2121 struct net_device *netdev = adapter->netdev;
2124 netif_device_detach(netdev);
2125 qlcnic_cancel_idc_work(adapter);
2127 if (netif_running(netdev))
2128 qlcnic_down(adapter, netdev);
2130 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
2131 qlcnic_sriov_cfg_bc_intr(adapter, 0);
2132 qlcnic_83xx_disable_mbx_intr(adapter);
2133 cancel_delayed_work_sync(&adapter->idc_aen_work);
2135 retval = pci_save_state(pdev);
2142 static int qlcnic_sriov_vf_resume(struct qlcnic_adapter *adapter)
2144 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
2145 struct net_device *netdev = adapter->netdev;
2148 set_bit(QLC_83XX_MODULE_LOADED, &idc->status);
2149 qlcnic_83xx_enable_mbx_interrupt(adapter);
2150 err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
2154 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
2156 if (netif_running(netdev)) {
2157 err = qlcnic_up(adapter, netdev);
2159 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
2163 netif_device_attach(netdev);
2164 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
2169 int qlcnic_sriov_alloc_vlans(struct qlcnic_adapter *adapter)
2171 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2172 struct qlcnic_vf_info *vf;
2175 for (i = 0; i < sriov->num_vfs; i++) {
2176 vf = &sriov->vf_info[i];
2177 vf->sriov_vlans = kcalloc(sriov->num_allowed_vlans,
2178 sizeof(*vf->sriov_vlans), GFP_KERNEL);
2179 if (!vf->sriov_vlans)
2186 void qlcnic_sriov_free_vlans(struct qlcnic_adapter *adapter)
2188 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2189 struct qlcnic_vf_info *vf;
2192 for (i = 0; i < sriov->num_vfs; i++) {
2193 vf = &sriov->vf_info[i];
2194 kfree(vf->sriov_vlans);
2195 vf->sriov_vlans = NULL;
2199 void qlcnic_sriov_add_vlan_id(struct qlcnic_sriov *sriov,
2200 struct qlcnic_vf_info *vf, u16 vlan_id)
2204 for (i = 0; i < sriov->num_allowed_vlans; i++) {
2205 if (!vf->sriov_vlans[i]) {
2206 vf->sriov_vlans[i] = vlan_id;
2213 void qlcnic_sriov_del_vlan_id(struct qlcnic_sriov *sriov,
2214 struct qlcnic_vf_info *vf, u16 vlan_id)
2218 for (i = 0; i < sriov->num_allowed_vlans; i++) {
2219 if (vf->sriov_vlans[i] == vlan_id) {
2220 vf->sriov_vlans[i] = 0;
2227 bool qlcnic_sriov_check_any_vlan(struct qlcnic_vf_info *vf)
2231 spin_lock_bh(&vf->vlan_list_lock);
2236 spin_unlock_bh(&vf->vlan_list_lock);