drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include <linux/if_vlan.h>
   9 #include <linux/ipv6.h>
  10 #include <linux/ethtool.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/aer.h>
  13
  14 #include "qlcnic.h"
  15 #include "qlcnic_sriov.h"
  16
  17 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *);
  18 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);
  19 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,
  20                                       struct qlcnic_cmd_args *);
  21 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);
  22 static irqreturn_t qlcnic_83xx_handle_aen(int, void *);
  23 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *,
  24                                                       pci_channel_state_t);
  25 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);
  26 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *);
  27 static void qlcnic_83xx_io_resume(struct pci_dev *);
  28 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);
  29 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *);
  30 static int qlcnic_83xx_resume(struct qlcnic_adapter *);
  31 static int qlcnic_83xx_shutdown(struct pci_dev *);
  32 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *);
  33
  34 #define RSS_HASHTYPE_IP_TCP             0x3
  35 #define QLC_83XX_FW_MBX_CMD             0
  36 #define QLC_SKIP_INACTIVE_PCI_REGS      7
  37 #define QLC_MAX_LEGACY_FUNC_SUPP        8
  38
  39 /* 83xx Module type */
  40 #define QLC_83XX_MODULE_FIBRE_10GBASE_LRM       0x1 /* 10GBase-LRM */
  41 #define QLC_83XX_MODULE_FIBRE_10GBASE_LR        0x2 /* 10GBase-LR */
  42 #define QLC_83XX_MODULE_FIBRE_10GBASE_SR        0x3 /* 10GBase-SR */
  43 #define QLC_83XX_MODULE_DA_10GE_PASSIVE_CP      0x4 /* 10GE passive
  44                                                      * copper(compliant)
  45                                                      */
  46 #define QLC_83XX_MODULE_DA_10GE_ACTIVE_CP       0x5 /* 10GE active limiting
  47                                                      * copper(compliant)
  48                                                      */
  49 #define QLC_83XX_MODULE_DA_10GE_LEGACY_CP       0x6 /* 10GE passive copper
  50                                                      * (legacy, best effort)
  51                                                      */
  52 #define QLC_83XX_MODULE_FIBRE_1000BASE_SX       0x7 /* 1000Base-SX */
  53 #define QLC_83XX_MODULE_FIBRE_1000BASE_LX       0x8 /* 1000Base-LX */
  54 #define QLC_83XX_MODULE_FIBRE_1000BASE_CX       0x9 /* 1000Base-CX */
  55 #define QLC_83XX_MODULE_TP_1000BASE_T           0xa /* 1000Base-T*/
  56 #define QLC_83XX_MODULE_DA_1GE_PASSIVE_CP       0xb /* 1GE passive copper
  57                                                      * (legacy, best effort)
  58                                                      */
  59 #define QLC_83XX_MODULE_UNKNOWN                 0xf /* Unknown module type */
  60
  61 /* Port types */
  62 #define QLC_83XX_10_CAPABLE      BIT_8
  63 #define QLC_83XX_100_CAPABLE     BIT_9
  64 #define QLC_83XX_1G_CAPABLE      BIT_10
  65 #define QLC_83XX_10G_CAPABLE     BIT_11
  66 #define QLC_83XX_AUTONEG_ENABLE  BIT_15
  67
  68 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
  69         {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
  70         {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
  71         {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
  72         {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  73         {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
  74         {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
  75         {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
  76         {QLCNIC_CMD_INTRPT_TEST, 22, 12},
  77         {QLCNIC_CMD_SET_MTU, 3, 1},
  78         {QLCNIC_CMD_READ_PHY, 4, 2},
  79         {QLCNIC_CMD_WRITE_PHY, 5, 1},
  80         {QLCNIC_CMD_READ_HW_REG, 4, 1},
  81         {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  82         {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  83         {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  84         {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  85         {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  86         {QLCNIC_CMD_GET_PCI_INFO, 1, 129},
  87         {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
  88         {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
  89         {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  90         {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  91         {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  92         {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  93         {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  94         {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  95         {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
  96         {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  97         {QLCNIC_CMD_TEMP_SIZE, 1, 4},
  98         {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
  99         {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
 100         {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
 101         {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
 102         {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
 103         {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
 104         {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
 105         {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
 106         {QLCNIC_CMD_GET_STATISTICS, 2, 80},
 107         {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
 108         {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
 109         {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
 110         {QLCNIC_CMD_IDC_ACK, 5, 1},
 111         {QLCNIC_CMD_INIT_NIC_FUNC, 3, 1},
 112         {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
 113         {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
 114         {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
 115         {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
 116         {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
 117         {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
 118         {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
 119         {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
 120         {QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50},
 121         {QLCNIC_CMD_SET_INGRESS_ENCAP, 2, 1},
 122         {QLCNIC_CMD_83XX_EXTEND_ISCSI_DUMP_CAP, 4, 1},
 123 };
 124
 125 const u32 qlcnic_83xx_ext_reg_tbl[] = {
 126         0x38CC,         /* Global Reset */
 127         0x38F0,         /* Wildcard */
 128         0x38FC,         /* Informant */
 129         0x3038,         /* Host MBX ctrl */
 130         0x303C,         /* FW MBX ctrl */
 131         0x355C,         /* BOOT LOADER ADDRESS REG */
 132         0x3560,         /* BOOT LOADER SIZE REG */
 133         0x3564,         /* FW IMAGE ADDR REG */
 134         0x1000,         /* MBX intr enable */
 135         0x1200,         /* Default Intr mask */
 136         0x1204,         /* Default Interrupt ID */
 137         0x3780,         /* QLC_83XX_IDC_MAJ_VERSION */
 138         0x3784,         /* QLC_83XX_IDC_DEV_STATE */
 139         0x3788,         /* QLC_83XX_IDC_DRV_PRESENCE */
 140         0x378C,         /* QLC_83XX_IDC_DRV_ACK */
 141         0x3790,         /* QLC_83XX_IDC_CTRL */
 142         0x3794,         /* QLC_83XX_IDC_DRV_AUDIT */
 143         0x3798,         /* QLC_83XX_IDC_MIN_VERSION */
 144         0x379C,         /* QLC_83XX_RECOVER_DRV_LOCK */
 145         0x37A0,         /* QLC_83XX_IDC_PF_0 */
 146         0x37A4,         /* QLC_83XX_IDC_PF_1 */
 147         0x37A8,         /* QLC_83XX_IDC_PF_2 */
 148         0x37AC,         /* QLC_83XX_IDC_PF_3 */
 149         0x37B0,         /* QLC_83XX_IDC_PF_4 */
 150         0x37B4,         /* QLC_83XX_IDC_PF_5 */
 151         0x37B8,         /* QLC_83XX_IDC_PF_6 */
 152         0x37BC,         /* QLC_83XX_IDC_PF_7 */
 153         0x37C0,         /* QLC_83XX_IDC_PF_8 */
 154         0x37C4,         /* QLC_83XX_IDC_PF_9 */
 155         0x37C8,         /* QLC_83XX_IDC_PF_10 */
 156         0x37CC,         /* QLC_83XX_IDC_PF_11 */
 157         0x37D0,         /* QLC_83XX_IDC_PF_12 */
 158         0x37D4,         /* QLC_83XX_IDC_PF_13 */
 159         0x37D8,         /* QLC_83XX_IDC_PF_14 */
 160         0x37DC,         /* QLC_83XX_IDC_PF_15 */
 161         0x37E0,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
 162         0x37E4,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
 163         0x37F0,         /* QLC_83XX_DRV_OP_MODE */
 164         0x37F4,         /* QLC_83XX_VNIC_STATE */
 165         0x3868,         /* QLC_83XX_DRV_LOCK */
 166         0x386C,         /* QLC_83XX_DRV_UNLOCK */
 167         0x3504,         /* QLC_83XX_DRV_LOCK_ID */
 168         0x34A4,         /* QLC_83XX_ASIC_TEMP */
 169 };
 170
 171 const u32 qlcnic_83xx_reg_tbl[] = {
 172         0x34A8,         /* PEG_HALT_STAT1 */
 173         0x34AC,         /* PEG_HALT_STAT2 */
 174         0x34B0,         /* FW_HEARTBEAT */
 175         0x3500,         /* FLASH LOCK_ID */
 176         0x3528,         /* FW_CAPABILITIES */
 177         0x3538,         /* Driver active, DRV_REG0 */
 178         0x3540,         /* Device state, DRV_REG1 */
 179         0x3544,         /* Driver state, DRV_REG2 */
 180         0x3548,         /* Driver scratch, DRV_REG3 */
 181         0x354C,         /* Device partition info, DRV_REG4 */
 182         0x3524,         /* Driver IDC ver, DRV_REG5 */
 183         0x3550,         /* FW_VER_MAJOR */
 184         0x3554,         /* FW_VER_MINOR */
 185         0x3558,         /* FW_VER_SUB */
 186         0x359C,         /* NPAR STATE */
 187         0x35FC,         /* FW_IMG_VALID */
 188         0x3650,         /* CMD_PEG_STATE */
 189         0x373C,         /* RCV_PEG_STATE */
 190         0x37B4,         /* ASIC TEMP */
 191         0x356C,         /* FW API */
 192         0x3570,         /* DRV OP MODE */
 193         0x3850,         /* FLASH LOCK */
 194         0x3854,         /* FLASH UNLOCK */
 195 };
 196
 197 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
 198         .read_crb                       = qlcnic_83xx_read_crb,
 199         .write_crb                      = qlcnic_83xx_write_crb,
 200         .read_reg                       = qlcnic_83xx_rd_reg_indirect,
 201         .write_reg                      = qlcnic_83xx_wrt_reg_indirect,
 202         .get_mac_address                = qlcnic_83xx_get_mac_address,
 203         .setup_intr                     = qlcnic_83xx_setup_intr,
 204         .alloc_mbx_args                 = qlcnic_83xx_alloc_mbx_args,
 205         .mbx_cmd                        = qlcnic_83xx_issue_cmd,
 206         .get_func_no                    = qlcnic_83xx_get_func_no,
 207         .api_lock                       = qlcnic_83xx_cam_lock,
 208         .api_unlock                     = qlcnic_83xx_cam_unlock,
 209         .add_sysfs                      = qlcnic_83xx_add_sysfs,
 210         .remove_sysfs                   = qlcnic_83xx_remove_sysfs,
 211         .process_lb_rcv_ring_diag       = qlcnic_83xx_process_rcv_ring_diag,
 212         .create_rx_ctx                  = qlcnic_83xx_create_rx_ctx,
 213         .create_tx_ctx                  = qlcnic_83xx_create_tx_ctx,
 214         .del_rx_ctx                     = qlcnic_83xx_del_rx_ctx,
 215         .del_tx_ctx                     = qlcnic_83xx_del_tx_ctx,
 216         .setup_link_event               = qlcnic_83xx_setup_link_event,
 217         .get_nic_info                   = qlcnic_83xx_get_nic_info,
 218         .get_pci_info                   = qlcnic_83xx_get_pci_info,
 219         .set_nic_info                   = qlcnic_83xx_set_nic_info,
 220         .change_macvlan                 = qlcnic_83xx_sre_macaddr_change,
 221         .napi_enable                    = qlcnic_83xx_napi_enable,
 222         .napi_disable                   = qlcnic_83xx_napi_disable,
 223         .config_intr_coal               = qlcnic_83xx_config_intr_coal,
 224         .config_rss                     = qlcnic_83xx_config_rss,
 225         .config_hw_lro                  = qlcnic_83xx_config_hw_lro,
 226         .config_promisc_mode            = qlcnic_83xx_nic_set_promisc,
 227         .change_l2_filter               = qlcnic_83xx_change_l2_filter,
 228         .get_board_info                 = qlcnic_83xx_get_port_info,
 229         .set_mac_filter_count           = qlcnic_83xx_set_mac_filter_count,
 230         .free_mac_list                  = qlcnic_82xx_free_mac_list,
 231         .io_error_detected              = qlcnic_83xx_io_error_detected,
 232         .io_slot_reset                  = qlcnic_83xx_io_slot_reset,
 233         .io_resume                      = qlcnic_83xx_io_resume,
 234         .get_beacon_state               = qlcnic_83xx_get_beacon_state,
 235         .enable_sds_intr                = qlcnic_83xx_enable_sds_intr,
 236         .disable_sds_intr               = qlcnic_83xx_disable_sds_intr,
 237         .enable_tx_intr                 = qlcnic_83xx_enable_tx_intr,
 238         .disable_tx_intr                = qlcnic_83xx_disable_tx_intr,
 239         .get_saved_state                = qlcnic_83xx_get_saved_state,
 240         .set_saved_state                = qlcnic_83xx_set_saved_state,
 241         .cache_tmpl_hdr_values          = qlcnic_83xx_cache_tmpl_hdr_values,
 242         .get_cap_size                   = qlcnic_83xx_get_cap_size,
 243         .set_sys_info                   = qlcnic_83xx_set_sys_info,
 244         .store_cap_mask                 = qlcnic_83xx_store_cap_mask,
 245         .encap_rx_offload               = qlcnic_83xx_encap_rx_offload,
 246         .encap_tx_offload               = qlcnic_83xx_encap_tx_offload,
 247 };
 248
 249 static struct qlcnic_nic_template qlcnic_83xx_ops = {
 250         .config_bridged_mode    = qlcnic_config_bridged_mode,
 251         .config_led             = qlcnic_config_led,
 252         .request_reset          = qlcnic_83xx_idc_request_reset,
 253         .cancel_idc_work        = qlcnic_83xx_idc_exit,
 254         .napi_add               = qlcnic_83xx_napi_add,
 255         .napi_del               = qlcnic_83xx_napi_del,
 256         .config_ipaddr          = qlcnic_83xx_config_ipaddr,
 257         .clear_legacy_intr      = qlcnic_83xx_clear_legacy_intr,
 258         .shutdown               = qlcnic_83xx_shutdown,
 259         .resume                 = qlcnic_83xx_resume,
 260 };
 261
 262 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
 263 {
 264         ahw->hw_ops             = &qlcnic_83xx_hw_ops;
 265         ahw->reg_tbl            = (u32 *)qlcnic_83xx_reg_tbl;
 266         ahw->ext_reg_tbl        = (u32 *)qlcnic_83xx_ext_reg_tbl;
 267 }
 268
 269 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
 270 {
 271         u32 fw_major, fw_minor, fw_build;
 272         struct pci_dev *pdev = adapter->pdev;
 273
 274         fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
 275         fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
 276         fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
 277         adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
 278
 279         dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
 280                  QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
 281
 282         return adapter->fw_version;
 283 }
 284
 285 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
 286 {
 287         void __iomem *base;
 288         u32 val;
 289
 290         base = adapter->ahw->pci_base0 +
 291                QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
 292         writel(addr, base);
 293         val = readl(base);
 294         if (val != addr)
 295                 return -EIO;
 296
 297         return 0;
 298 }
 299
 300 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 301                                 int *err)
 302 {
 303         struct qlcnic_hardware_context *ahw = adapter->ahw;
 304
 305         *err = __qlcnic_set_win_base(adapter, (u32) addr);
 306         if (!*err) {
 307                 return QLCRDX(ahw, QLCNIC_WILDCARD);
 308         } else {
 309                 dev_err(&adapter->pdev->dev,
 310                         "%s failed, addr = 0x%lx\n", __func__, addr);
 311                 return -EIO;
 312         }
 313 }
 314
 315 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 316                                  u32 data)
 317 {
 318         int err;
 319         struct qlcnic_hardware_context *ahw = adapter->ahw;
 320
 321         err = __qlcnic_set_win_base(adapter, (u32) addr);
 322         if (!err) {
 323                 QLCWRX(ahw, QLCNIC_WILDCARD, data);
 324                 return 0;
 325         } else {
 326                 dev_err(&adapter->pdev->dev,
 327                         "%s failed, addr = 0x%x data = 0x%x\n",
 328                         __func__, (int)addr, data);
 329                 return err;
 330         }
 331 }
 332
 333 static void qlcnic_83xx_enable_legacy(struct qlcnic_adapter *adapter)
 334 {
 335         struct qlcnic_hardware_context *ahw = adapter->ahw;
 336
 337         /* MSI-X enablement failed, use legacy interrupt */
 338         adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
 339         adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
 340         adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
 341         adapter->msix_entries[0].vector = adapter->pdev->irq;
 342         dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
 343 }
 344
 345 static int qlcnic_83xx_calculate_msix_vector(struct qlcnic_adapter *adapter)
 346 {
 347         int num_msix;
 348
 349         num_msix = adapter->drv_sds_rings;
 350
 351         /* account for AEN interrupt MSI-X based interrupts */
 352         num_msix += 1;
 353
 354         if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
 355                 num_msix += adapter->drv_tx_rings;
 356
 357         return num_msix;
 358 }
 359
 360 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter)
 361 {
 362         struct qlcnic_hardware_context *ahw = adapter->ahw;
 363         int err, i, num_msix;
 364
 365         if (adapter->flags & QLCNIC_TSS_RSS) {
 366                 err = qlcnic_setup_tss_rss_intr(adapter);
 367                 if (err < 0)
 368                         return err;
 369                 num_msix = ahw->num_msix;
 370         } else {
 371                 num_msix = qlcnic_83xx_calculate_msix_vector(adapter);
 372
 373                 err = qlcnic_enable_msix(adapter, num_msix);
 374                 if (err == -ENOMEM)
 375                         return err;
 376
 377                 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
 378                         num_msix = ahw->num_msix;
 379                 } else {
 380                         if (qlcnic_sriov_vf_check(adapter))
 381                                 return -EINVAL;
 382                         num_msix = 1;
 383                         adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
 384                         adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
 385                 }
 386         }
 387
 388         /* setup interrupt mapping table for fw */
 389         ahw->intr_tbl =
 390                 vzalloc(array_size(num_msix,
 391                                    sizeof(struct qlcnic_intrpt_config)));
 392         if (!ahw->intr_tbl)
 393                 return -ENOMEM;
 394
 395         if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
 396                 if (adapter->ahw->pci_func >= QLC_MAX_LEGACY_FUNC_SUPP) {
 397                         dev_err(&adapter->pdev->dev, "PCI function number 8 and higher are not supported with legacy interrupt, func 0x%x\n",
 398                                 ahw->pci_func);
 399                         return -EOPNOTSUPP;
 400                 }
 401
 402                 qlcnic_83xx_enable_legacy(adapter);
 403         }
 404
 405         for (i = 0; i < num_msix; i++) {
 406                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
 407                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
 408                 else
 409                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
 410                 ahw->intr_tbl[i].id = i;
 411                 ahw->intr_tbl[i].src = 0;
 412         }
 413
 414         return 0;
 415 }
 416
 417 static inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
 418 {
 419         writel(0, adapter->tgt_mask_reg);
 420 }
 421
 422 static inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
 423 {
 424         if (adapter->tgt_mask_reg)
 425                 writel(1, adapter->tgt_mask_reg);
 426 }
 427
 428 static inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
 429                                                     *adapter)
 430 {
 431         u32 mask;
 432
 433         /* Mailbox in MSI-x mode and Legacy Interrupt share the same
 434          * source register. We could be here before contexts are created
 435          * and sds_ring->crb_intr_mask has not been initialized, calculate
 436          * BAR offset for Interrupt Source Register
 437          */
 438         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 439         writel(0, adapter->ahw->pci_base0 + mask);
 440 }
 441
 442 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
 443 {
 444         u32 mask;
 445
 446         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 447         writel(1, adapter->ahw->pci_base0 + mask);
 448         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
 449 }
 450
 451 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
 452                                      struct qlcnic_cmd_args *cmd)
 453 {
 454         int i;
 455
 456         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 457                 return;
 458
 459         for (i = 0; i < cmd->rsp.num; i++)
 460                 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
 461 }
 462
 463 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
 464 {
 465         u32 intr_val;
 466         struct qlcnic_hardware_context *ahw = adapter->ahw;
 467         int retries = 0;
 468
 469         intr_val = readl(adapter->tgt_status_reg);
 470
 471         if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
 472                 return IRQ_NONE;
 473
 474         if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
 475                 adapter->stats.spurious_intr++;
 476                 return IRQ_NONE;
 477         }
 478         /* The barrier is required to ensure writes to the registers */
 479         wmb();
 480
 481         /* clear the interrupt trigger control register */
 482         writel_relaxed(0, adapter->isr_int_vec);
 483         intr_val = readl(adapter->isr_int_vec);
 484         do {
 485                 intr_val = readl(adapter->tgt_status_reg);
 486                 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
 487                         break;
 488                 retries++;
 489         } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
 490                  (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
 491
 492         return IRQ_HANDLED;
 493 }
 494
 495 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
 496 {
 497         mbx->rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 498         complete(&mbx->completion);
 499 }
 500
 501 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
 502 {
 503         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 504         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 505         unsigned long flags;
 506
 507         spin_lock_irqsave(&mbx->aen_lock, flags);
 508         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
 509         if (!(resp & QLCNIC_SET_OWNER))
 510                 goto out;
 511
 512         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
 513         if (event &  QLCNIC_MBX_ASYNC_EVENT) {
 514                 __qlcnic_83xx_process_aen(adapter);
 515         } else {
 516                 if (mbx->rsp_status != rsp_status)
 517                         qlcnic_83xx_notify_mbx_response(mbx);
 518         }
 519 out:
 520         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 521         spin_unlock_irqrestore(&mbx->aen_lock, flags);
 522 }
 523
 524 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
 525 {
 526         struct qlcnic_adapter *adapter = data;
 527         struct qlcnic_host_sds_ring *sds_ring;
 528         struct qlcnic_hardware_context *ahw = adapter->ahw;
 529
 530         if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
 531                 return IRQ_NONE;
 532
 533         qlcnic_83xx_poll_process_aen(adapter);
 534
 535         if (ahw->diag_test) {
 536                 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST)
 537                         ahw->diag_cnt++;
 538                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 539                 return IRQ_HANDLED;
 540         }
 541
 542         if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
 543                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 544         } else {
 545                 sds_ring = &adapter->recv_ctx->sds_rings[0];
 546                 napi_schedule(&sds_ring->napi);
 547         }
 548
 549         return IRQ_HANDLED;
 550 }
 551
 552 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
 553 {
 554         struct qlcnic_host_sds_ring *sds_ring = data;
 555         struct qlcnic_adapter *adapter = sds_ring->adapter;
 556
 557         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 558                 goto done;
 559
 560         if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
 561                 return IRQ_NONE;
 562
 563 done:
 564         adapter->ahw->diag_cnt++;
 565         qlcnic_enable_sds_intr(adapter, sds_ring);
 566
 567         return IRQ_HANDLED;
 568 }
 569
 570 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
 571 {
 572         u32 num_msix;
 573
 574         if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
 575                 qlcnic_83xx_set_legacy_intr_mask(adapter);
 576
 577         qlcnic_83xx_disable_mbx_intr(adapter);
 578
 579         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 580                 num_msix = adapter->ahw->num_msix - 1;
 581         else
 582                 num_msix = 0;
 583
 584         msleep(20);
 585
 586         if (adapter->msix_entries) {
 587                 synchronize_irq(adapter->msix_entries[num_msix].vector);
 588                 free_irq(adapter->msix_entries[num_msix].vector, adapter);
 589         }
 590 }
 591
 592 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
 593 {
 594         irq_handler_t handler;
 595         u32 val;
 596         int err = 0;
 597         unsigned long flags = 0;
 598
 599         if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
 600             !(adapter->flags & QLCNIC_MSIX_ENABLED))
 601                 flags |= IRQF_SHARED;
 602
 603         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
 604                 handler = qlcnic_83xx_handle_aen;
 605                 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
 606                 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
 607                 if (err) {
 608                         dev_err(&adapter->pdev->dev,
 609                                 "failed to register MBX interrupt\n");
 610                         return err;
 611                 }
 612         } else {
 613                 handler = qlcnic_83xx_intr;
 614                 val = adapter->msix_entries[0].vector;
 615                 err = request_irq(val, handler, flags, "qlcnic", adapter);
 616                 if (err) {
 617                         dev_err(&adapter->pdev->dev,
 618                                 "failed to register INTx interrupt\n");
 619                         return err;
 620                 }
 621                 qlcnic_83xx_clear_legacy_intr_mask(adapter);
 622         }
 623
 624         /* Enable mailbox interrupt */
 625         qlcnic_83xx_enable_mbx_interrupt(adapter);
 626
 627         return err;
 628 }
 629
 630 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
 631 {
 632         u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
 633         adapter->ahw->pci_func = (val >> 24) & 0xff;
 634 }
 635
 636 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
 637 {
 638         void __iomem *addr;
 639         u32 val, limit = 0;
 640
 641         struct qlcnic_hardware_context *ahw = adapter->ahw;
 642
 643         addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
 644         do {
 645                 val = readl(addr);
 646                 if (val) {
 647                         /* write the function number to register */
 648                         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
 649                                             ahw->pci_func);
 650                         return 0;
 651                 }
 652                 usleep_range(1000, 2000);
 653         } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
 654
 655         return -EIO;
 656 }
 657
 658 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
 659 {
 660         void __iomem *addr;
 661         u32 val;
 662         struct qlcnic_hardware_context *ahw = adapter->ahw;
 663
 664         addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
 665         val = readl(addr);
 666 }
 667
 668 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
 669                           loff_t offset, size_t size)
 670 {
 671         int ret = 0;
 672         u32 data;
 673
 674         if (qlcnic_api_lock(adapter)) {
 675                 dev_err(&adapter->pdev->dev,
 676                         "%s: failed to acquire lock. addr offset 0x%x\n",
 677                         __func__, (u32)offset);
 678                 return;
 679         }
 680
 681         data = QLCRD32(adapter, (u32) offset, &ret);
 682         qlcnic_api_unlock(adapter);
 683
 684         if (ret == -EIO) {
 685                 dev_err(&adapter->pdev->dev,
 686                         "%s: failed. addr offset 0x%x\n",
 687                         __func__, (u32)offset);
 688                 return;
 689         }
 690         memcpy(buf, &data, size);
 691 }
 692
 693 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
 694                            loff_t offset, size_t size)
 695 {
 696         u32 data;
 697
 698         memcpy(&data, buf, size);
 699         qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
 700 }
 701
 702 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
 703 {
 704         struct qlcnic_hardware_context *ahw = adapter->ahw;
 705         int status;
 706
 707         status = qlcnic_83xx_get_port_config(adapter);
 708         if (status) {
 709                 dev_err(&adapter->pdev->dev,
 710                         "Get Port Info failed\n");
 711         } else {
 712
 713                 if (ahw->port_config & QLC_83XX_10G_CAPABLE) {
 714                         ahw->port_type = QLCNIC_XGBE;
 715                 } else if (ahw->port_config & QLC_83XX_10_CAPABLE ||
 716                            ahw->port_config & QLC_83XX_100_CAPABLE ||
 717                            ahw->port_config & QLC_83XX_1G_CAPABLE) {
 718                         ahw->port_type = QLCNIC_GBE;
 719                 } else {
 720                         ahw->port_type = QLCNIC_XGBE;
 721                 }
 722
 723                 if (QLC_83XX_AUTONEG(ahw->port_config))
 724                         ahw->link_autoneg = AUTONEG_ENABLE;
 725
 726         }
 727         return status;
 728 }
 729
 730 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
 731 {
 732         struct qlcnic_hardware_context *ahw = adapter->ahw;
 733         u16 act_pci_fn = ahw->total_nic_func;
 734         u16 count;
 735
 736         ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
 737         if (act_pci_fn <= 2)
 738                 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
 739                          act_pci_fn;
 740         else
 741                 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
 742                          act_pci_fn;
 743         ahw->max_uc_count = count;
 744 }
 745
 746 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
 747 {
 748         u32 val;
 749
 750         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 751                 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
 752         else
 753                 val = BIT_2;
 754
 755         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
 756         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 757 }
 758
 759 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
 760                           const struct pci_device_id *ent)
 761 {
 762         u32 op_mode, priv_level;
 763         struct qlcnic_hardware_context *ahw = adapter->ahw;
 764
 765         ahw->fw_hal_version = 2;
 766         qlcnic_get_func_no(adapter);
 767
 768         if (qlcnic_sriov_vf_check(adapter)) {
 769                 qlcnic_sriov_vf_set_ops(adapter);
 770                 return;
 771         }
 772
 773         /* Determine function privilege level */
 774         op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
 775         if (op_mode == QLC_83XX_DEFAULT_OPMODE)
 776                 priv_level = QLCNIC_MGMT_FUNC;
 777         else
 778                 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
 779                                                          ahw->pci_func);
 780
 781         if (priv_level == QLCNIC_NON_PRIV_FUNC) {
 782                 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
 783                 dev_info(&adapter->pdev->dev,
 784                          "HAL Version: %d Non Privileged function\n",
 785                          ahw->fw_hal_version);
 786                 adapter->nic_ops = &qlcnic_vf_ops;
 787         } else {
 788                 if (pci_find_ext_capability(adapter->pdev,
 789                                             PCI_EXT_CAP_ID_SRIOV))
 790                         set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
 791                 adapter->nic_ops = &qlcnic_83xx_ops;
 792         }
 793 }
 794
 795 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
 796                                         u32 data[]);
 797 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 798                                             u32 data[]);
 799
 800 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
 801                      struct qlcnic_cmd_args *cmd)
 802 {
 803         int i;
 804
 805         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 806                 return;
 807
 808         dev_info(&adapter->pdev->dev,
 809                  "Host MBX regs(%d)\n", cmd->req.num);
 810         for (i = 0; i < cmd->req.num; i++) {
 811                 if (i && !(i % 8))
 812                         pr_info("\n");
 813                 pr_info("%08x ", cmd->req.arg[i]);
 814         }
 815         pr_info("\n");
 816         dev_info(&adapter->pdev->dev,
 817                  "FW MBX regs(%d)\n", cmd->rsp.num);
 818         for (i = 0; i < cmd->rsp.num; i++) {
 819                 if (i && !(i % 8))
 820                         pr_info("\n");
 821                 pr_info("%08x ", cmd->rsp.arg[i]);
 822         }
 823         pr_info("\n");
 824 }
 825
 826 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
 827                                                 struct qlcnic_cmd_args *cmd)
 828 {
 829         struct qlcnic_hardware_context *ahw = adapter->ahw;
 830         int opcode = LSW(cmd->req.arg[0]);
 831         unsigned long max_loops;
 832
 833         max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
 834
 835         for (; max_loops; max_loops--) {
 836                 if (atomic_read(&cmd->rsp_status) ==
 837                     QLC_83XX_MBX_RESPONSE_ARRIVED)
 838                         return;
 839
 840                 udelay(1);
 841         }
 842
 843         dev_err(&adapter->pdev->dev,
 844                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 845                 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
 846         flush_workqueue(ahw->mailbox->work_q);
 847         return;
 848 }
 849
 850 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
 851                           struct qlcnic_cmd_args *cmd)
 852 {
 853         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 854         struct qlcnic_hardware_context *ahw = adapter->ahw;
 855         int cmd_type, err, opcode;
 856         unsigned long timeout;
 857
 858         if (!mbx)
 859                 return -EIO;
 860
 861         opcode = LSW(cmd->req.arg[0]);
 862         cmd_type = cmd->type;
 863         err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
 864         if (err) {
 865                 dev_err(&adapter->pdev->dev,
 866                         "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 867                         __func__, opcode, cmd->type, ahw->pci_func,
 868                         ahw->op_mode);
 869                 return err;
 870         }
 871
 872         switch (cmd_type) {
 873         case QLC_83XX_MBX_CMD_WAIT:
 874                 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
 875                         dev_err(&adapter->pdev->dev,
 876                                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 877                                 __func__, opcode, cmd_type, ahw->pci_func,
 878                                 ahw->op_mode);
 879                         flush_workqueue(mbx->work_q);
 880                 }
 881                 break;
 882         case QLC_83XX_MBX_CMD_NO_WAIT:
 883                 return 0;
 884         case QLC_83XX_MBX_CMD_BUSY_WAIT:
 885                 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
 886                 break;
 887         default:
 888                 dev_err(&adapter->pdev->dev,
 889                         "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 890                         __func__, opcode, cmd_type, ahw->pci_func,
 891                         ahw->op_mode);
 892                 qlcnic_83xx_detach_mailbox_work(adapter);
 893         }
 894
 895         return cmd->rsp_opcode;
 896 }
 897
 898 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
 899                                struct qlcnic_adapter *adapter, u32 type)
 900 {
 901         int i, size;
 902         u32 temp;
 903         const struct qlcnic_mailbox_metadata *mbx_tbl;
 904
 905         memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
 906         mbx_tbl = qlcnic_83xx_mbx_tbl;
 907         size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
 908         for (i = 0; i < size; i++) {
 909                 if (type == mbx_tbl[i].cmd) {
 910                         mbx->op_type = QLC_83XX_FW_MBX_CMD;
 911                         mbx->req.num = mbx_tbl[i].in_args;
 912                         mbx->rsp.num = mbx_tbl[i].out_args;
 913                         mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
 914                                                GFP_ATOMIC);
 915                         if (!mbx->req.arg)
 916                                 return -ENOMEM;
 917                         mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
 918                                                GFP_ATOMIC);
 919                         if (!mbx->rsp.arg) {
 920                                 kfree(mbx->req.arg);
 921                                 mbx->req.arg = NULL;
 922                                 return -ENOMEM;
 923                         }
 924                         temp = adapter->ahw->fw_hal_version << 29;
 925                         mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
 926                         mbx->cmd_op = type;
 927                         return 0;
 928                 }
 929         }
 930
 931         dev_err(&adapter->pdev->dev, "%s: Invalid mailbox command opcode 0x%x\n",
 932                 __func__, type);
 933         return -EINVAL;
 934 }
 935
 936 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
 937 {
 938         struct qlcnic_adapter *adapter;
 939         struct qlcnic_cmd_args cmd;
 940         int i, err = 0;
 941
 942         adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
 943         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
 944         if (err)
 945                 return;
 946
 947         for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
 948                 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
 949
 950         err = qlcnic_issue_cmd(adapter, &cmd);
 951         if (err)
 952                 dev_info(&adapter->pdev->dev,
 953                          "%s: Mailbox IDC ACK failed.\n", __func__);
 954         qlcnic_free_mbx_args(&cmd);
 955 }
 956
 957 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 958                                             u32 data[])
 959 {
 960         dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
 961                 QLCNIC_MBX_RSP(data[0]));
 962         clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
 963         return;
 964 }
 965
 966 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 967 {
 968         struct qlcnic_hardware_context *ahw = adapter->ahw;
 969         u32 event[QLC_83XX_MBX_AEN_CNT];
 970         int i;
 971
 972         for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 973                 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
 974
 975         switch (QLCNIC_MBX_RSP(event[0])) {
 976
 977         case QLCNIC_MBX_LINK_EVENT:
 978                 qlcnic_83xx_handle_link_aen(adapter, event);
 979                 break;
 980         case QLCNIC_MBX_COMP_EVENT:
 981                 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
 982                 break;
 983         case QLCNIC_MBX_REQUEST_EVENT:
 984                 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 985                         adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
 986                 queue_delayed_work(adapter->qlcnic_wq,
 987                                    &adapter->idc_aen_work, 0);
 988                 break;
 989         case QLCNIC_MBX_TIME_EXTEND_EVENT:
 990                 ahw->extend_lb_time = event[1] >> 8 & 0xf;
 991                 break;
 992         case QLCNIC_MBX_BC_EVENT:
 993                 qlcnic_sriov_handle_bc_event(adapter, event[1]);
 994                 break;
 995         case QLCNIC_MBX_SFP_INSERT_EVENT:
 996                 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
 997                          QLCNIC_MBX_RSP(event[0]));
 998                 break;
 999         case QLCNIC_MBX_SFP_REMOVE_EVENT:
1000                 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
1001                          QLCNIC_MBX_RSP(event[0]));
1002                 break;
1003         case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
1004                 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]);
1005                 break;
1006         default:
1007                 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
1008                         QLCNIC_MBX_RSP(event[0]));
1009                 break;
1010         }
1011
1012         QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
1013 }
1014
1015 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
1016 {
1017         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
1018         struct qlcnic_hardware_context *ahw = adapter->ahw;
1019         struct qlcnic_mailbox *mbx = ahw->mailbox;
1020         unsigned long flags;
1021
1022         spin_lock_irqsave(&mbx->aen_lock, flags);
1023         resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
1024         if (resp & QLCNIC_SET_OWNER) {
1025                 event = readl(QLCNIC_MBX_FW(ahw, 0));
1026                 if (event &  QLCNIC_MBX_ASYNC_EVENT) {
1027                         __qlcnic_83xx_process_aen(adapter);
1028                 } else {
1029                         if (mbx->rsp_status != rsp_status)
1030                                 qlcnic_83xx_notify_mbx_response(mbx);
1031                 }
1032         }
1033         spin_unlock_irqrestore(&mbx->aen_lock, flags);
1034 }
1035
1036 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
1037 {
1038         struct qlcnic_adapter *adapter;
1039
1040         adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
1041
1042         if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1043                 return;
1044
1045         qlcnic_83xx_process_aen(adapter);
1046         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
1047                            (HZ / 10));
1048 }
1049
1050 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
1051 {
1052         if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1053                 return;
1054
1055         INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
1056         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
1057 }
1058
1059 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
1060 {
1061         if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1062                 return;
1063         cancel_delayed_work_sync(&adapter->mbx_poll_work);
1064 }
1065
1066 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
1067 {
1068         int index, i, err, sds_mbx_size;
1069         u32 *buf, intrpt_id, intr_mask;
1070         u16 context_id;
1071         u8 num_sds;
1072         struct qlcnic_cmd_args cmd;
1073         struct qlcnic_host_sds_ring *sds;
1074         struct qlcnic_sds_mbx sds_mbx;
1075         struct qlcnic_add_rings_mbx_out *mbx_out;
1076         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1077         struct qlcnic_hardware_context *ahw = adapter->ahw;
1078
1079         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1080         context_id = recv_ctx->context_id;
1081         num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS;
1082         err = ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
1083                                         QLCNIC_CMD_ADD_RCV_RINGS);
1084         if (err) {
1085                 dev_err(&adapter->pdev->dev,
1086                         "Failed to alloc mbx args %d\n", err);
1087                 return err;
1088         }
1089
1090         cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
1091
1092         /* set up status rings, mbx 2-81 */
1093         index = 2;
1094         for (i = 8; i < adapter->drv_sds_rings; i++) {
1095                 memset(&sds_mbx, 0, sds_mbx_size);
1096                 sds = &recv_ctx->sds_rings[i];
1097                 sds->consumer = 0;
1098                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1099                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1100                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1101                 sds_mbx.sds_ring_size = sds->num_desc;
1102
1103                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1104                         intrpt_id = ahw->intr_tbl[i].id;
1105                 else
1106                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1107
1108                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1109                         sds_mbx.intrpt_id = intrpt_id;
1110                 else
1111                         sds_mbx.intrpt_id = 0xffff;
1112                 sds_mbx.intrpt_val = 0;
1113                 buf = &cmd.req.arg[index];
1114                 memcpy(buf, &sds_mbx, sds_mbx_size);
1115                 index += sds_mbx_size / sizeof(u32);
1116         }
1117
1118         /* send the mailbox command */
1119         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1120         if (err) {
1121                 dev_err(&adapter->pdev->dev,
1122                         "Failed to add rings %d\n", err);
1123                 goto out;
1124         }
1125
1126         mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1127         index = 0;
1128         /* status descriptor ring */
1129         for (i = 8; i < adapter->drv_sds_rings; i++) {
1130                 sds = &recv_ctx->sds_rings[i];
1131                 sds->crb_sts_consumer = ahw->pci_base0 +
1132                                         mbx_out->host_csmr[index];
1133                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1134                         intr_mask = ahw->intr_tbl[i].src;
1135                 else
1136                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1137
1138                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1139                 index++;
1140         }
1141 out:
1142         qlcnic_free_mbx_args(&cmd);
1143         return err;
1144 }
1145
1146 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1147 {
1148         int err;
1149         u32 temp = 0;
1150         struct qlcnic_cmd_args cmd;
1151         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1152
1153         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1154                 return;
1155
1156         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1157                 cmd.req.arg[0] |= (0x3 << 29);
1158
1159         if (qlcnic_sriov_pf_check(adapter))
1160                 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1161
1162         cmd.req.arg[1] = recv_ctx->context_id | temp;
1163         err = qlcnic_issue_cmd(adapter, &cmd);
1164         if (err)
1165                 dev_err(&adapter->pdev->dev,
1166                         "Failed to destroy rx ctx in firmware\n");
1167
1168         recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1169         qlcnic_free_mbx_args(&cmd);
1170 }
1171
1172 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1173 {
1174         int i, err, index, sds_mbx_size, rds_mbx_size;
1175         u8 num_sds, num_rds;
1176         u32 *buf, intrpt_id, intr_mask, cap = 0;
1177         struct qlcnic_host_sds_ring *sds;
1178         struct qlcnic_host_rds_ring *rds;
1179         struct qlcnic_sds_mbx sds_mbx;
1180         struct qlcnic_rds_mbx rds_mbx;
1181         struct qlcnic_cmd_args cmd;
1182         struct qlcnic_rcv_mbx_out *mbx_out;
1183         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1184         struct qlcnic_hardware_context *ahw = adapter->ahw;
1185         num_rds = adapter->max_rds_rings;
1186
1187         if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS)
1188                 num_sds = adapter->drv_sds_rings;
1189         else
1190                 num_sds = QLCNIC_MAX_SDS_RINGS;
1191
1192         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1193         rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1194         cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1195
1196         if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1197                 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1198
1199         /* set mailbox hdr and capabilities */
1200         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1201                                     QLCNIC_CMD_CREATE_RX_CTX);
1202         if (err)
1203                 return err;
1204
1205         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1206                 cmd.req.arg[0] |= (0x3 << 29);
1207
1208         cmd.req.arg[1] = cap;
1209         cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1210                          (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1211
1212         if (qlcnic_sriov_pf_check(adapter))
1213                 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1214                                                          &cmd.req.arg[6]);
1215         /* set up status rings, mbx 8-57/87 */
1216         index = QLC_83XX_HOST_SDS_MBX_IDX;
1217         for (i = 0; i < num_sds; i++) {
1218                 memset(&sds_mbx, 0, sds_mbx_size);
1219                 sds = &recv_ctx->sds_rings[i];
1220                 sds->consumer = 0;
1221                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1222                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1223                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1224                 sds_mbx.sds_ring_size = sds->num_desc;
1225                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1226                         intrpt_id = ahw->intr_tbl[i].id;
1227                 else
1228                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1229                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1230                         sds_mbx.intrpt_id = intrpt_id;
1231                 else
1232                         sds_mbx.intrpt_id = 0xffff;
1233                 sds_mbx.intrpt_val = 0;
1234                 buf = &cmd.req.arg[index];
1235                 memcpy(buf, &sds_mbx, sds_mbx_size);
1236                 index += sds_mbx_size / sizeof(u32);
1237         }
1238         /* set up receive rings, mbx 88-111/135 */
1239         index = QLCNIC_HOST_RDS_MBX_IDX;
1240         rds = &recv_ctx->rds_rings[0];
1241         rds->producer = 0;
1242         memset(&rds_mbx, 0, rds_mbx_size);
1243         rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1244         rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1245         rds_mbx.reg_ring_sz = rds->dma_size;
1246         rds_mbx.reg_ring_len = rds->num_desc;
1247         /* Jumbo ring */
1248         rds = &recv_ctx->rds_rings[1];
1249         rds->producer = 0;
1250         rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1251         rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1252         rds_mbx.jmb_ring_sz = rds->dma_size;
1253         rds_mbx.jmb_ring_len = rds->num_desc;
1254         buf = &cmd.req.arg[index];
1255         memcpy(buf, &rds_mbx, rds_mbx_size);
1256
1257         /* send the mailbox command */
1258         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1259         if (err) {
1260                 dev_err(&adapter->pdev->dev,
1261                         "Failed to create Rx ctx in firmware%d\n", err);
1262                 goto out;
1263         }
1264         mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1265         recv_ctx->context_id = mbx_out->ctx_id;
1266         recv_ctx->state = mbx_out->state;
1267         recv_ctx->virt_port = mbx_out->vport_id;
1268         dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1269                  recv_ctx->context_id, recv_ctx->state);
1270         /* Receive descriptor ring */
1271         /* Standard ring */
1272         rds = &recv_ctx->rds_rings[0];
1273         rds->crb_rcv_producer = ahw->pci_base0 +
1274                                 mbx_out->host_prod[0].reg_buf;
1275         /* Jumbo ring */
1276         rds = &recv_ctx->rds_rings[1];
1277         rds->crb_rcv_producer = ahw->pci_base0 +
1278                                 mbx_out->host_prod[0].jmb_buf;
1279         /* status descriptor ring */
1280         for (i = 0; i < num_sds; i++) {
1281                 sds = &recv_ctx->sds_rings[i];
1282                 sds->crb_sts_consumer = ahw->pci_base0 +
1283                                         mbx_out->host_csmr[i];
1284                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1285                         intr_mask = ahw->intr_tbl[i].src;
1286                 else
1287                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1288                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1289         }
1290
1291         if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS)
1292                 err = qlcnic_83xx_add_rings(adapter);
1293 out:
1294         qlcnic_free_mbx_args(&cmd);
1295         return err;
1296 }
1297
1298 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1299                             struct qlcnic_host_tx_ring *tx_ring)
1300 {
1301         struct qlcnic_cmd_args cmd;
1302         u32 temp = 0;
1303
1304         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1305                 return;
1306
1307         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1308                 cmd.req.arg[0] |= (0x3 << 29);
1309
1310         if (qlcnic_sriov_pf_check(adapter))
1311                 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1312
1313         cmd.req.arg[1] = tx_ring->ctx_id | temp;
1314         if (qlcnic_issue_cmd(adapter, &cmd))
1315                 dev_err(&adapter->pdev->dev,
1316                         "Failed to destroy tx ctx in firmware\n");
1317         qlcnic_free_mbx_args(&cmd);
1318 }
1319
1320 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1321                               struct qlcnic_host_tx_ring *tx, int ring)
1322 {
1323         int err;
1324         u16 msix_id;
1325         u32 *buf, intr_mask, temp = 0;
1326         struct qlcnic_cmd_args cmd;
1327         struct qlcnic_tx_mbx mbx;
1328         struct qlcnic_tx_mbx_out *mbx_out;
1329         struct qlcnic_hardware_context *ahw = adapter->ahw;
1330         u32 msix_vector;
1331
1332         /* Reset host resources */
1333         tx->producer = 0;
1334         tx->sw_consumer = 0;
1335         *(tx->hw_consumer) = 0;
1336
1337         memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1338
1339         /* setup mailbox inbox registerss */
1340         mbx.phys_addr_low = LSD(tx->phys_addr);
1341         mbx.phys_addr_high = MSD(tx->phys_addr);
1342         mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1343         mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1344         mbx.size = tx->num_desc;
1345         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1346                 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1347                         msix_vector = adapter->drv_sds_rings + ring;
1348                 else
1349                         msix_vector = adapter->drv_sds_rings - 1;
1350                 msix_id = ahw->intr_tbl[msix_vector].id;
1351         } else {
1352                 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1353         }
1354
1355         if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1356                 mbx.intr_id = msix_id;
1357         else
1358                 mbx.intr_id = 0xffff;
1359         mbx.src = 0;
1360
1361         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1362         if (err)
1363                 return err;
1364
1365         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1366                 cmd.req.arg[0] |= (0x3 << 29);
1367
1368         if (qlcnic_sriov_pf_check(adapter))
1369                 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1370
1371         cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1372         cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp;
1373
1374         buf = &cmd.req.arg[6];
1375         memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1376         /* send the mailbox command*/
1377         err = qlcnic_issue_cmd(adapter, &cmd);
1378         if (err) {
1379                 netdev_err(adapter->netdev,
1380                            "Failed to create Tx ctx in firmware 0x%x\n", err);
1381                 goto out;
1382         }
1383         mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1384         tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1385         tx->ctx_id = mbx_out->ctx_id;
1386         if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1387             !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1388                 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src;
1389                 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1390         }
1391         netdev_info(adapter->netdev,
1392                     "Tx Context[0x%x] Created, state:0x%x\n",
1393                     tx->ctx_id, mbx_out->state);
1394 out:
1395         qlcnic_free_mbx_args(&cmd);
1396         return err;
1397 }
1398
1399 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1400                                       u8 num_sds_ring)
1401 {
1402         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1403         struct qlcnic_host_sds_ring *sds_ring;
1404         struct qlcnic_host_rds_ring *rds_ring;
1405         u16 adapter_state = adapter->is_up;
1406         u8 ring;
1407         int ret;
1408
1409         netif_device_detach(netdev);
1410
1411         if (netif_running(netdev))
1412                 __qlcnic_down(adapter, netdev);
1413
1414         qlcnic_detach(adapter);
1415
1416         adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
1417         adapter->ahw->diag_test = test;
1418         adapter->ahw->linkup = 0;
1419
1420         ret = qlcnic_attach(adapter);
1421         if (ret) {
1422                 netif_device_attach(netdev);
1423                 return ret;
1424         }
1425
1426         ret = qlcnic_fw_create_ctx(adapter);
1427         if (ret) {
1428                 qlcnic_detach(adapter);
1429                 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1430                         adapter->drv_sds_rings = num_sds_ring;
1431                         qlcnic_attach(adapter);
1432                 }
1433                 netif_device_attach(netdev);
1434                 return ret;
1435         }
1436
1437         for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1438                 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1439                 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1440         }
1441
1442         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1443                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1444                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1445                         qlcnic_enable_sds_intr(adapter, sds_ring);
1446                 }
1447         }
1448
1449         if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1450                 adapter->ahw->loopback_state = 0;
1451                 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1452         }
1453
1454         set_bit(__QLCNIC_DEV_UP, &adapter->state);
1455         return 0;
1456 }
1457
1458 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1459                                       u8 drv_sds_rings)
1460 {
1461         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1462         struct qlcnic_host_sds_ring *sds_ring;
1463         int ring;
1464
1465         clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1466         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1467                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1468                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1469                         if (adapter->flags & QLCNIC_MSIX_ENABLED)
1470                                 qlcnic_disable_sds_intr(adapter, sds_ring);
1471                 }
1472         }
1473
1474         qlcnic_fw_destroy_ctx(adapter);
1475         qlcnic_detach(adapter);
1476
1477         adapter->ahw->diag_test = 0;
1478         adapter->drv_sds_rings = drv_sds_rings;
1479
1480         if (qlcnic_attach(adapter))
1481                 goto out;
1482
1483         if (netif_running(netdev))
1484                 __qlcnic_up(adapter, netdev);
1485
1486 out:
1487         netif_device_attach(netdev);
1488 }
1489
1490 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *adapter)
1491 {
1492         struct qlcnic_hardware_context *ahw = adapter->ahw;
1493         struct qlcnic_cmd_args cmd;
1494         u8 beacon_state;
1495         int err = 0;
1496
1497         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LED_CONFIG);
1498         if (!err) {
1499                 err = qlcnic_issue_cmd(adapter, &cmd);
1500                 if (!err) {
1501                         beacon_state = cmd.rsp.arg[4];
1502                         if (beacon_state == QLCNIC_BEACON_DISABLE)
1503                                 ahw->beacon_state = QLC_83XX_BEACON_OFF;
1504                         else if (beacon_state == QLC_83XX_ENABLE_BEACON)
1505                                 ahw->beacon_state = QLC_83XX_BEACON_ON;
1506                 }
1507         } else {
1508                 netdev_err(adapter->netdev, "Get beacon state failed, err=%d\n",
1509                            err);
1510         }
1511
1512         qlcnic_free_mbx_args(&cmd);
1513
1514         return;
1515 }
1516
1517 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1518                            u32 beacon)
1519 {
1520         struct qlcnic_cmd_args cmd;
1521         u32 mbx_in;
1522         int i, status = 0;
1523
1524         if (state) {
1525                 /* Get LED configuration */
1526                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1527                                                QLCNIC_CMD_GET_LED_CONFIG);
1528                 if (status)
1529                         return status;
1530
1531                 status = qlcnic_issue_cmd(adapter, &cmd);
1532                 if (status) {
1533                         dev_err(&adapter->pdev->dev,
1534                                 "Get led config failed.\n");
1535                         goto mbx_err;
1536                 } else {
1537                         for (i = 0; i < 4; i++)
1538                                 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1539                 }
1540                 qlcnic_free_mbx_args(&cmd);
1541                 /* Set LED Configuration */
1542                 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1543                           LSW(QLC_83XX_LED_CONFIG);
1544                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1545                                                QLCNIC_CMD_SET_LED_CONFIG);
1546                 if (status)
1547                         return status;
1548
1549                 cmd.req.arg[1] = mbx_in;
1550                 cmd.req.arg[2] = mbx_in;
1551                 cmd.req.arg[3] = mbx_in;
1552                 if (beacon)
1553                         cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1554                 status = qlcnic_issue_cmd(adapter, &cmd);
1555                 if (status) {
1556                         dev_err(&adapter->pdev->dev,
1557                                 "Set led config failed.\n");
1558                 }
1559 mbx_err:
1560                 qlcnic_free_mbx_args(&cmd);
1561                 return status;
1562
1563         } else {
1564                 /* Restoring default LED configuration */
1565                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1566                                                QLCNIC_CMD_SET_LED_CONFIG);
1567                 if (status)
1568                         return status;
1569
1570                 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1571                 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1572                 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1573                 if (beacon)
1574                         cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1575                 status = qlcnic_issue_cmd(adapter, &cmd);
1576                 if (status)
1577                         dev_err(&adapter->pdev->dev,
1578                                 "Restoring led config failed.\n");
1579                 qlcnic_free_mbx_args(&cmd);
1580                 return status;
1581         }
1582 }
1583
1584 int  qlcnic_83xx_set_led(struct net_device *netdev,
1585                          enum ethtool_phys_id_state state)
1586 {
1587         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1588         int err = -EIO, active = 1;
1589
1590         if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1591                 netdev_warn(netdev,
1592                             "LED test is not supported in non-privileged mode\n");
1593                 return -EOPNOTSUPP;
1594         }
1595
1596         switch (state) {
1597         case ETHTOOL_ID_ACTIVE:
1598                 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1599                         return -EBUSY;
1600
1601                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1602                         break;
1603
1604                 err = qlcnic_83xx_config_led(adapter, active, 0);
1605                 if (err)
1606                         netdev_err(netdev, "Failed to set LED blink state\n");
1607                 break;
1608         case ETHTOOL_ID_INACTIVE:
1609                 active = 0;
1610
1611                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1612                         break;
1613
1614                 err = qlcnic_83xx_config_led(adapter, active, 0);
1615                 if (err)
1616                         netdev_err(netdev, "Failed to reset LED blink state\n");
1617                 break;
1618
1619         default:
1620                 return -EINVAL;
1621         }
1622
1623         if (!active || err)
1624                 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1625
1626         return err;
1627 }
1628
1629 void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *adapter, int enable)
1630 {
1631         struct qlcnic_cmd_args cmd;
1632         int status;
1633
1634         if (qlcnic_sriov_vf_check(adapter))
1635                 return;
1636
1637         if (enable)
1638                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1639                                                QLCNIC_CMD_INIT_NIC_FUNC);
1640         else
1641                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1642                                                QLCNIC_CMD_STOP_NIC_FUNC);
1643
1644         if (status)
1645                 return;
1646
1647         cmd.req.arg[1] = QLC_REGISTER_LB_IDC | QLC_INIT_FW_RESOURCES;
1648
1649         if (adapter->dcb)
1650                 cmd.req.arg[1] |= QLC_REGISTER_DCB_AEN;
1651
1652         status = qlcnic_issue_cmd(adapter, &cmd);
1653         if (status)
1654                 dev_err(&adapter->pdev->dev,
1655                         "Failed to %s in NIC IDC function event.\n",
1656                         (enable ? "register" : "unregister"));
1657
1658         qlcnic_free_mbx_args(&cmd);
1659 }
1660
1661 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1662 {
1663         struct qlcnic_cmd_args cmd;
1664         int err;
1665
1666         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1667         if (err)
1668                 return err;
1669
1670         cmd.req.arg[1] = adapter->ahw->port_config;
1671         err = qlcnic_issue_cmd(adapter, &cmd);
1672         if (err)
1673                 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1674         qlcnic_free_mbx_args(&cmd);
1675         return err;
1676 }
1677
1678 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1679 {
1680         struct qlcnic_cmd_args cmd;
1681         int err;
1682
1683         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1684         if (err)
1685                 return err;
1686
1687         err = qlcnic_issue_cmd(adapter, &cmd);
1688         if (err)
1689                 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1690         else
1691                 adapter->ahw->port_config = cmd.rsp.arg[1];
1692         qlcnic_free_mbx_args(&cmd);
1693         return err;
1694 }
1695
1696 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1697 {
1698         int err;
1699         u32 temp;
1700         struct qlcnic_cmd_args cmd;
1701
1702         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1703         if (err)
1704                 return err;
1705
1706         temp = adapter->recv_ctx->context_id << 16;
1707         cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1708         err = qlcnic_issue_cmd(adapter, &cmd);
1709         if (err)
1710                 dev_info(&adapter->pdev->dev,
1711                          "Setup linkevent mailbox failed\n");
1712         qlcnic_free_mbx_args(&cmd);
1713         return err;
1714 }
1715
1716 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1717                                                  u32 *interface_id)
1718 {
1719         if (qlcnic_sriov_pf_check(adapter)) {
1720                 qlcnic_alloc_lb_filters_mem(adapter);
1721                 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1722                 adapter->rx_mac_learn = true;
1723         } else {
1724                 if (!qlcnic_sriov_vf_check(adapter))
1725                         *interface_id = adapter->recv_ctx->context_id << 16;
1726         }
1727 }
1728
1729 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1730 {
1731         struct qlcnic_cmd_args *cmd = NULL;
1732         u32 temp = 0;
1733         int err;
1734
1735         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1736                 return -EIO;
1737
1738         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1739         if (!cmd)
1740                 return -ENOMEM;
1741
1742         err = qlcnic_alloc_mbx_args(cmd, adapter,
1743                                     QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1744         if (err)
1745                 goto out;
1746
1747         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1748         qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1749
1750         if (qlcnic_84xx_check(adapter) && qlcnic_sriov_pf_check(adapter))
1751                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1752
1753         cmd->req.arg[1] = mode | temp;
1754         err = qlcnic_issue_cmd(adapter, cmd);
1755         if (!err)
1756                 return err;
1757
1758         qlcnic_free_mbx_args(cmd);
1759
1760 out:
1761         kfree(cmd);
1762         return err;
1763 }
1764
1765 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1766 {
1767         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1768         struct qlcnic_hardware_context *ahw = adapter->ahw;
1769         u8 drv_sds_rings = adapter->drv_sds_rings;
1770         u8 drv_tx_rings = adapter->drv_tx_rings;
1771         int ret = 0, loop = 0;
1772
1773         if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1774                 netdev_warn(netdev,
1775                             "Loopback test not supported in non privileged mode\n");
1776                 return -ENOTSUPP;
1777         }
1778
1779         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1780                 netdev_info(netdev, "Device is resetting\n");
1781                 return -EBUSY;
1782         }
1783
1784         if (qlcnic_get_diag_lock(adapter)) {
1785                 netdev_info(netdev, "Device is in diagnostics mode\n");
1786                 return -EBUSY;
1787         }
1788
1789         netdev_info(netdev, "%s loopback test in progress\n",
1790                     mode == QLCNIC_ILB_MODE ? "internal" : "external");
1791
1792         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1793                                          drv_sds_rings);
1794         if (ret)
1795                 goto fail_diag_alloc;
1796
1797         ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1798         if (ret)
1799                 goto free_diag_res;
1800
1801         /* Poll for link up event before running traffic */
1802         do {
1803                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1804
1805                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1806                         netdev_info(netdev,
1807                                     "Device is resetting, free LB test resources\n");
1808                         ret = -EBUSY;
1809                         goto free_diag_res;
1810                 }
1811                 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1812                         netdev_info(netdev,
1813                                     "Firmware didn't sent link up event to loopback request\n");
1814                         ret = -ETIMEDOUT;
1815                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1816                         goto free_diag_res;
1817                 }
1818         } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1819
1820         ret = qlcnic_do_lb_test(adapter, mode);
1821
1822         qlcnic_83xx_clear_lb_mode(adapter, mode);
1823
1824 free_diag_res:
1825         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
1826
1827 fail_diag_alloc:
1828         adapter->drv_sds_rings = drv_sds_rings;
1829         adapter->drv_tx_rings = drv_tx_rings;
1830         qlcnic_release_diag_lock(adapter);
1831         return ret;
1832 }
1833
1834 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1835                                              u32 *max_wait_count)
1836 {
1837         struct qlcnic_hardware_context *ahw = adapter->ahw;
1838         int temp;
1839
1840         netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n",
1841                     ahw->extend_lb_time);
1842         temp = ahw->extend_lb_time * 1000;
1843         *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1844         ahw->extend_lb_time = 0;
1845 }
1846
1847 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1848 {
1849         struct qlcnic_hardware_context *ahw = adapter->ahw;
1850         struct net_device *netdev = adapter->netdev;
1851         u32 config, max_wait_count;
1852         int status = 0, loop = 0;
1853
1854         ahw->extend_lb_time = 0;
1855         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1856         status = qlcnic_83xx_get_port_config(adapter);
1857         if (status)
1858                 return status;
1859
1860         config = ahw->port_config;
1861
1862         /* Check if port is already in loopback mode */
1863         if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1864             (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1865                 netdev_err(netdev,
1866                            "Port already in Loopback mode.\n");
1867                 return -EINPROGRESS;
1868         }
1869
1870         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1871
1872         if (mode == QLCNIC_ILB_MODE)
1873                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1874         if (mode == QLCNIC_ELB_MODE)
1875                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1876
1877         status = qlcnic_83xx_set_port_config(adapter);
1878         if (status) {
1879                 netdev_err(netdev,
1880                            "Failed to Set Loopback Mode = 0x%x.\n",
1881                            ahw->port_config);
1882                 ahw->port_config = config;
1883                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1884                 return status;
1885         }
1886
1887         /* Wait for Link and IDC Completion AEN */
1888         do {
1889                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1890
1891                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1892                         netdev_info(netdev,
1893                                     "Device is resetting, free LB test resources\n");
1894                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1895                         return -EBUSY;
1896                 }
1897
1898                 if (ahw->extend_lb_time)
1899                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1900                                                          &max_wait_count);
1901
1902                 if (loop++ > max_wait_count) {
1903                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1904                                    __func__);
1905                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1906                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1907                         return -ETIMEDOUT;
1908                 }
1909         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1910
1911         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1912                                   QLCNIC_MAC_ADD);
1913         return status;
1914 }
1915
1916 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1917 {
1918         struct qlcnic_hardware_context *ahw = adapter->ahw;
1919         u32 config = ahw->port_config, max_wait_count;
1920         struct net_device *netdev = adapter->netdev;
1921         int status = 0, loop = 0;
1922
1923         ahw->extend_lb_time = 0;
1924         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1925         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1926         if (mode == QLCNIC_ILB_MODE)
1927                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1928         if (mode == QLCNIC_ELB_MODE)
1929                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1930
1931         status = qlcnic_83xx_set_port_config(adapter);
1932         if (status) {
1933                 netdev_err(netdev,
1934                            "Failed to Clear Loopback Mode = 0x%x.\n",
1935                            ahw->port_config);
1936                 ahw->port_config = config;
1937                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1938                 return status;
1939         }
1940
1941         /* Wait for Link and IDC Completion AEN */
1942         do {
1943                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1944
1945                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1946                         netdev_info(netdev,
1947                                     "Device is resetting, free LB test resources\n");
1948                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1949                         return -EBUSY;
1950                 }
1951
1952                 if (ahw->extend_lb_time)
1953                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1954                                                          &max_wait_count);
1955
1956                 if (loop++ > max_wait_count) {
1957                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1958                                    __func__);
1959                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1960                         return -ETIMEDOUT;
1961                 }
1962         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1963
1964         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1965                                   QLCNIC_MAC_DEL);
1966         return status;
1967 }
1968
1969 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1970                                                 u32 *interface_id)
1971 {
1972         if (qlcnic_sriov_pf_check(adapter)) {
1973                 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1974         } else {
1975                 if (!qlcnic_sriov_vf_check(adapter))
1976                         *interface_id = adapter->recv_ctx->context_id << 16;
1977         }
1978 }
1979
1980 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1981                                int mode)
1982 {
1983         int err;
1984         u32 temp = 0, temp_ip;
1985         struct qlcnic_cmd_args cmd;
1986
1987         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1988                                     QLCNIC_CMD_CONFIGURE_IP_ADDR);
1989         if (err)
1990                 return;
1991
1992         qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1993
1994         if (mode == QLCNIC_IP_UP)
1995                 cmd.req.arg[1] = 1 | temp;
1996         else
1997                 cmd.req.arg[1] = 2 | temp;
1998
1999         /*
2000          * Adapter needs IP address in network byte order.
2001          * But hardware mailbox registers go through writel(), hence IP address
2002          * gets swapped on big endian architecture.
2003          * To negate swapping of writel() on big endian architecture
2004          * use swab32(value).
2005          */
2006
2007         temp_ip = swab32(ntohl(ip));
2008         memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
2009         err = qlcnic_issue_cmd(adapter, &cmd);
2010         if (err != QLCNIC_RCODE_SUCCESS)
2011                 dev_err(&adapter->netdev->dev,
2012                         "could not notify %s IP 0x%x request\n",
2013                         (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
2014
2015         qlcnic_free_mbx_args(&cmd);
2016 }
2017
2018 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
2019 {
2020         int err;
2021         u32 temp, arg1;
2022         struct qlcnic_cmd_args cmd;
2023         int lro_bit_mask;
2024
2025         lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
2026
2027         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2028                 return 0;
2029
2030         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
2031         if (err)
2032                 return err;
2033
2034         temp = adapter->recv_ctx->context_id << 16;
2035         arg1 = lro_bit_mask | temp;
2036         cmd.req.arg[1] = arg1;
2037
2038         err = qlcnic_issue_cmd(adapter, &cmd);
2039         if (err)
2040                 dev_info(&adapter->pdev->dev, "LRO config failed\n");
2041         qlcnic_free_mbx_args(&cmd);
2042
2043         return err;
2044 }
2045
2046 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
2047 {
2048         int err;
2049         u32 word;
2050         struct qlcnic_cmd_args cmd;
2051         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
2052                             0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
2053                             0x255b0ec26d5a56daULL };
2054
2055         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
2056         if (err)
2057                 return err;
2058         /*
2059          * RSS request:
2060          * bits 3-0: Rsvd
2061          *      5-4: hash_type_ipv4
2062          *      7-6: hash_type_ipv6
2063          *        8: enable
2064          *        9: use indirection table
2065          *    16-31: indirection table mask
2066          */
2067         word =  ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
2068                 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
2069                 ((u32)(enable & 0x1) << 8) |
2070                 ((0x7ULL) << 16);
2071         cmd.req.arg[1] = (adapter->recv_ctx->context_id);
2072         cmd.req.arg[2] = word;
2073         memcpy(&cmd.req.arg[4], key, sizeof(key));
2074
2075         err = qlcnic_issue_cmd(adapter, &cmd);
2076
2077         if (err)
2078                 dev_info(&adapter->pdev->dev, "RSS config failed\n");
2079         qlcnic_free_mbx_args(&cmd);
2080
2081         return err;
2082
2083 }
2084
2085 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
2086                                                  u32 *interface_id)
2087 {
2088         if (qlcnic_sriov_pf_check(adapter)) {
2089                 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
2090         } else {
2091                 if (!qlcnic_sriov_vf_check(adapter))
2092                         *interface_id = adapter->recv_ctx->context_id << 16;
2093         }
2094 }
2095
2096 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
2097                                    u16 vlan_id, u8 op)
2098 {
2099         struct qlcnic_cmd_args *cmd = NULL;
2100         struct qlcnic_macvlan_mbx mv;
2101         u32 *buf, temp = 0;
2102         int err;
2103
2104         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2105                 return -EIO;
2106
2107         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
2108         if (!cmd)
2109                 return -ENOMEM;
2110
2111         err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
2112         if (err)
2113                 goto out;
2114
2115         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
2116
2117         if (vlan_id)
2118                 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
2119                      QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
2120
2121         cmd->req.arg[1] = op | (1 << 8);
2122         qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
2123         cmd->req.arg[1] |= temp;
2124         mv.vlan = vlan_id;
2125         mv.mac_addr0 = addr[0];
2126         mv.mac_addr1 = addr[1];
2127         mv.mac_addr2 = addr[2];
2128         mv.mac_addr3 = addr[3];
2129         mv.mac_addr4 = addr[4];
2130         mv.mac_addr5 = addr[5];
2131         buf = &cmd->req.arg[2];
2132         memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
2133         err = qlcnic_issue_cmd(adapter, cmd);
2134         if (!err)
2135                 return err;
2136
2137         qlcnic_free_mbx_args(cmd);
2138 out:
2139         kfree(cmd);
2140         return err;
2141 }
2142
2143 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
2144                                   u16 vlan_id,
2145                                   struct qlcnic_host_tx_ring *tx_ring)
2146 {
2147         u8 mac[ETH_ALEN];
2148         memcpy(&mac, addr, ETH_ALEN);
2149         qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2150 }
2151
2152 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2153                                       u8 type, struct qlcnic_cmd_args *cmd)
2154 {
2155         switch (type) {
2156         case QLCNIC_SET_STATION_MAC:
2157         case QLCNIC_SET_FAC_DEF_MAC:
2158                 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2159                 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2160                 break;
2161         }
2162         cmd->req.arg[1] = type;
2163 }
2164
2165 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2166                                 u8 function)
2167 {
2168         int err, i;
2169         struct qlcnic_cmd_args cmd;
2170         u32 mac_low, mac_high;
2171
2172         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2173         if (err)
2174                 return err;
2175
2176         qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2177         err = qlcnic_issue_cmd(adapter, &cmd);
2178
2179         if (err == QLCNIC_RCODE_SUCCESS) {
2180                 mac_low = cmd.rsp.arg[1];
2181                 mac_high = cmd.rsp.arg[2];
2182
2183                 for (i = 0; i < 2; i++)
2184                         mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2185                 for (i = 2; i < 6; i++)
2186                         mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2187         } else {
2188                 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2189                         err);
2190                 err = -EIO;
2191         }
2192         qlcnic_free_mbx_args(&cmd);
2193         return err;
2194 }
2195
2196 static int qlcnic_83xx_set_rx_intr_coal(struct qlcnic_adapter *adapter)
2197 {
2198         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2199         struct qlcnic_cmd_args cmd;
2200         u16 temp;
2201         int err;
2202
2203         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2204         if (err)
2205                 return err;
2206
2207         temp = adapter->recv_ctx->context_id;
2208         cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2209         temp = coal->rx_time_us;
2210         cmd.req.arg[2] = coal->rx_packets | temp << 16;
2211         cmd.req.arg[3] = coal->flag;
2212
2213         err = qlcnic_issue_cmd(adapter, &cmd);
2214         if (err != QLCNIC_RCODE_SUCCESS)
2215                 netdev_err(adapter->netdev,
2216                            "failed to set interrupt coalescing parameters\n");
2217
2218         qlcnic_free_mbx_args(&cmd);
2219
2220         return err;
2221 }
2222
2223 static int qlcnic_83xx_set_tx_intr_coal(struct qlcnic_adapter *adapter)
2224 {
2225         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2226         struct qlcnic_cmd_args cmd;
2227         u16 temp;
2228         int err;
2229
2230         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2231         if (err)
2232                 return err;
2233
2234         temp = adapter->tx_ring->ctx_id;
2235         cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2236         temp = coal->tx_time_us;
2237         cmd.req.arg[2] = coal->tx_packets | temp << 16;
2238         cmd.req.arg[3] = coal->flag;
2239
2240         err = qlcnic_issue_cmd(adapter, &cmd);
2241         if (err != QLCNIC_RCODE_SUCCESS)
2242                 netdev_err(adapter->netdev,
2243                            "failed to set interrupt coalescing  parameters\n");
2244
2245         qlcnic_free_mbx_args(&cmd);
2246
2247         return err;
2248 }
2249
2250 int qlcnic_83xx_set_rx_tx_intr_coal(struct qlcnic_adapter *adapter)
2251 {
2252         int err = 0;
2253
2254         err = qlcnic_83xx_set_rx_intr_coal(adapter);
2255         if (err)
2256                 netdev_err(adapter->netdev,
2257                            "failed to set Rx coalescing parameters\n");
2258
2259         err = qlcnic_83xx_set_tx_intr_coal(adapter);
2260         if (err)
2261                 netdev_err(adapter->netdev,
2262                            "failed to set Tx coalescing parameters\n");
2263
2264         return err;
2265 }
2266
2267 int qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter,
2268                                  struct ethtool_coalesce *ethcoal)
2269 {
2270         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2271         u32 rx_coalesce_usecs, rx_max_frames;
2272         u32 tx_coalesce_usecs, tx_max_frames;
2273         int err;
2274
2275         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2276                 return -EIO;
2277
2278         tx_coalesce_usecs = ethcoal->tx_coalesce_usecs;
2279         tx_max_frames = ethcoal->tx_max_coalesced_frames;
2280         rx_coalesce_usecs = ethcoal->rx_coalesce_usecs;
2281         rx_max_frames = ethcoal->rx_max_coalesced_frames;
2282         coal->flag = QLCNIC_INTR_DEFAULT;
2283
2284         if ((coal->rx_time_us == rx_coalesce_usecs) &&
2285             (coal->rx_packets == rx_max_frames)) {
2286                 coal->type = QLCNIC_INTR_COAL_TYPE_TX;
2287                 coal->tx_time_us = tx_coalesce_usecs;
2288                 coal->tx_packets = tx_max_frames;
2289         } else if ((coal->tx_time_us == tx_coalesce_usecs) &&
2290                    (coal->tx_packets == tx_max_frames)) {
2291                 coal->type = QLCNIC_INTR_COAL_TYPE_RX;
2292                 coal->rx_time_us = rx_coalesce_usecs;
2293                 coal->rx_packets = rx_max_frames;
2294         } else {
2295                 coal->type = QLCNIC_INTR_COAL_TYPE_RX_TX;
2296                 coal->rx_time_us = rx_coalesce_usecs;
2297                 coal->rx_packets = rx_max_frames;
2298                 coal->tx_time_us = tx_coalesce_usecs;
2299                 coal->tx_packets = tx_max_frames;
2300         }
2301
2302         switch (coal->type) {
2303         case QLCNIC_INTR_COAL_TYPE_RX:
2304                 err = qlcnic_83xx_set_rx_intr_coal(adapter);
2305                 break;
2306         case QLCNIC_INTR_COAL_TYPE_TX:
2307                 err = qlcnic_83xx_set_tx_intr_coal(adapter);
2308                 break;
2309         case QLCNIC_INTR_COAL_TYPE_RX_TX:
2310                 err = qlcnic_83xx_set_rx_tx_intr_coal(adapter);
2311                 break;
2312         default:
2313                 err = -EINVAL;
2314                 netdev_err(adapter->netdev,
2315                            "Invalid Interrupt coalescing type\n");
2316                 break;
2317         }
2318
2319         return err;
2320 }
2321
2322 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2323                                         u32 data[])
2324 {
2325         struct qlcnic_hardware_context *ahw = adapter->ahw;
2326         u8 link_status, duplex;
2327         /* link speed */
2328         link_status = LSB(data[3]) & 1;
2329         if (link_status) {
2330                 ahw->link_speed = MSW(data[2]);
2331                 duplex = LSB(MSW(data[3]));
2332                 if (duplex)
2333                         ahw->link_duplex = DUPLEX_FULL;
2334                 else
2335                         ahw->link_duplex = DUPLEX_HALF;
2336         } else {
2337                 ahw->link_speed = SPEED_UNKNOWN;
2338                 ahw->link_duplex = DUPLEX_UNKNOWN;
2339         }
2340
2341         ahw->link_autoneg = MSB(MSW(data[3]));
2342         ahw->module_type = MSB(LSW(data[3]));
2343         ahw->has_link_events = 1;
2344         ahw->lb_mode = data[4] & QLCNIC_LB_MODE_MASK;
2345         qlcnic_advert_link_change(adapter, link_status);
2346 }
2347
2348 static irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2349 {
2350         u32 mask, resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
2351         struct qlcnic_adapter *adapter = data;
2352         struct qlcnic_mailbox *mbx;
2353         unsigned long flags;
2354
2355         mbx = adapter->ahw->mailbox;
2356         spin_lock_irqsave(&mbx->aen_lock, flags);
2357         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2358         if (!(resp & QLCNIC_SET_OWNER))
2359                 goto out;
2360
2361         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2362         if (event &  QLCNIC_MBX_ASYNC_EVENT) {
2363                 __qlcnic_83xx_process_aen(adapter);
2364         } else {
2365                 if (mbx->rsp_status != rsp_status)
2366                         qlcnic_83xx_notify_mbx_response(mbx);
2367                 else
2368                         adapter->stats.mbx_spurious_intr++;
2369         }
2370
2371 out:
2372         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2373         writel(0, adapter->ahw->pci_base0 + mask);
2374         spin_unlock_irqrestore(&mbx->aen_lock, flags);
2375         return IRQ_HANDLED;
2376 }
2377
2378 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2379                              struct qlcnic_info *nic)
2380 {
2381         int i, err = -EIO;
2382         struct qlcnic_cmd_args cmd;
2383
2384         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2385                 dev_err(&adapter->pdev->dev,
2386                         "%s: Error, invoked by non management func\n",
2387                         __func__);
2388                 return err;
2389         }
2390
2391         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2392         if (err)
2393                 return err;
2394
2395         cmd.req.arg[1] = (nic->pci_func << 16);
2396         cmd.req.arg[2] = 0x1 << 16;
2397         cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2398         cmd.req.arg[4] = nic->capabilities;
2399         cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2400         cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2401         cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2402         for (i = 8; i < 32; i++)
2403                 cmd.req.arg[i] = 0;
2404
2405         err = qlcnic_issue_cmd(adapter, &cmd);
2406
2407         if (err != QLCNIC_RCODE_SUCCESS) {
2408                 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2409                         err);
2410                 err = -EIO;
2411         }
2412
2413         qlcnic_free_mbx_args(&cmd);
2414
2415         return err;
2416 }
2417
2418 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2419                              struct qlcnic_info *npar_info, u8 func_id)
2420 {
2421         int err;
2422         u32 temp;
2423         u8 op = 0;
2424         struct qlcnic_cmd_args cmd;
2425         struct qlcnic_hardware_context *ahw = adapter->ahw;
2426
2427         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2428         if (err)
2429                 return err;
2430
2431         if (func_id != ahw->pci_func) {
2432                 temp = func_id << 16;
2433                 cmd.req.arg[1] = op | BIT_31 | temp;
2434         } else {
2435                 cmd.req.arg[1] = ahw->pci_func << 16;
2436         }
2437         err = qlcnic_issue_cmd(adapter, &cmd);
2438         if (err) {
2439                 dev_info(&adapter->pdev->dev,
2440                          "Failed to get nic info %d\n", err);
2441                 goto out;
2442         }
2443
2444         npar_info->op_type = cmd.rsp.arg[1];
2445         npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2446         npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2447         npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2448         npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2449         npar_info->capabilities = cmd.rsp.arg[4];
2450         npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2451         npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2452         npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2453         npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2454         npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2455         npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2456         if (cmd.rsp.arg[8] & 0x1)
2457                 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2458         if (cmd.rsp.arg[8] & 0x10000) {
2459                 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2460                 npar_info->max_linkspeed_reg_offset = temp;
2461         }
2462
2463         memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2464                sizeof(ahw->extra_capability));
2465
2466 out:
2467         qlcnic_free_mbx_args(&cmd);
2468         return err;
2469 }
2470
2471 int qlcnic_get_pci_func_type(struct qlcnic_adapter *adapter, u16 type,
2472                              u16 *nic, u16 *fcoe, u16 *iscsi)
2473 {
2474         struct device *dev = &adapter->pdev->dev;
2475         int err = 0;
2476
2477         switch (type) {
2478         case QLCNIC_TYPE_NIC:
2479                 (*nic)++;
2480                 break;
2481         case QLCNIC_TYPE_FCOE:
2482                 (*fcoe)++;
2483                 break;
2484         case QLCNIC_TYPE_ISCSI:
2485                 (*iscsi)++;
2486                 break;
2487         default:
2488                 dev_err(dev, "%s: Unknown PCI type[%x]\n",
2489                         __func__, type);
2490                 err = -EIO;
2491         }
2492
2493         return err;
2494 }
2495
2496 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2497                              struct qlcnic_pci_info *pci_info)
2498 {
2499         struct qlcnic_hardware_context *ahw = adapter->ahw;
2500         struct device *dev = &adapter->pdev->dev;
2501         u16 nic = 0, fcoe = 0, iscsi = 0;
2502         struct qlcnic_cmd_args cmd;
2503         int i, err = 0, j = 0;
2504         u32 temp;
2505
2506         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2507         if (err)
2508                 return err;
2509
2510         err = qlcnic_issue_cmd(adapter, &cmd);
2511
2512         ahw->total_nic_func = 0;
2513         if (err == QLCNIC_RCODE_SUCCESS) {
2514                 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2515                 for (i = 2, j = 0; j < ahw->max_vnic_func; j++, pci_info++) {
2516                         pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2517                         pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2518                         i++;
2519                         if (!pci_info->active) {
2520                                 i += QLC_SKIP_INACTIVE_PCI_REGS;
2521                                 continue;
2522                         }
2523                         pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2524                         err = qlcnic_get_pci_func_type(adapter, pci_info->type,
2525                                                        &nic, &fcoe, &iscsi);
2526                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2527                         pci_info->default_port = temp;
2528                         i++;
2529                         pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2530                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2531                         pci_info->tx_max_bw = temp;
2532                         i = i + 2;
2533                         memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2534                         i++;
2535                         memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2536                         i = i + 3;
2537                 }
2538         } else {
2539                 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2540                 err = -EIO;
2541         }
2542
2543         ahw->total_nic_func = nic;
2544         ahw->total_pci_func = nic + fcoe + iscsi;
2545         if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) {
2546                 dev_err(dev, "%s: Invalid function count: total nic func[%x], total pci func[%x]\n",
2547                         __func__, ahw->total_nic_func, ahw->total_pci_func);
2548                 err = -EIO;
2549         }
2550         qlcnic_free_mbx_args(&cmd);
2551
2552         return err;
2553 }
2554
2555 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2556 {
2557         int i, index, err;
2558         u8 max_ints;
2559         u32 val, temp, type;
2560         struct qlcnic_cmd_args cmd;
2561
2562         max_ints = adapter->ahw->num_msix - 1;
2563         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2564         if (err)
2565                 return err;
2566
2567         cmd.req.arg[1] = max_ints;
2568
2569         if (qlcnic_sriov_vf_check(adapter))
2570                 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2571
2572         for (i = 0, index = 2; i < max_ints; i++) {
2573                 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2574                 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2575                 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2576                         val |= (adapter->ahw->intr_tbl[i].id << 16);
2577                 cmd.req.arg[index++] = val;
2578         }
2579         err = qlcnic_issue_cmd(adapter, &cmd);
2580         if (err) {
2581                 dev_err(&adapter->pdev->dev,
2582                         "Failed to configure interrupts 0x%x\n", err);
2583                 goto out;
2584         }
2585
2586         max_ints = cmd.rsp.arg[1];
2587         for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2588                 val = cmd.rsp.arg[index];
2589                 if (LSB(val)) {
2590                         dev_info(&adapter->pdev->dev,
2591                                  "Can't configure interrupt %d\n",
2592                                  adapter->ahw->intr_tbl[i].id);
2593                         continue;
2594                 }
2595                 if (op_type) {
2596                         adapter->ahw->intr_tbl[i].id = MSW(val);
2597                         adapter->ahw->intr_tbl[i].enabled = 1;
2598                         temp = cmd.rsp.arg[index + 1];
2599                         adapter->ahw->intr_tbl[i].src = temp;
2600                 } else {
2601                         adapter->ahw->intr_tbl[i].id = i;
2602                         adapter->ahw->intr_tbl[i].enabled = 0;
2603                         adapter->ahw->intr_tbl[i].src = 0;
2604                 }
2605         }
2606 out:
2607         qlcnic_free_mbx_args(&cmd);
2608         return err;
2609 }
2610
2611 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2612 {
2613         int id, timeout = 0;
2614         u32 status = 0;
2615
2616         while (status == 0) {
2617                 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2618                 if (status)
2619                         break;
2620
2621                 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2622                         id = QLC_SHARED_REG_RD32(adapter,
2623                                                  QLCNIC_FLASH_LOCK_OWNER);
2624                         dev_err(&adapter->pdev->dev,
2625                                 "%s: failed, lock held by %d\n", __func__, id);
2626                         return -EIO;
2627                 }
2628                 usleep_range(1000, 2000);
2629         }
2630
2631         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2632         return 0;
2633 }
2634
2635 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2636 {
2637         QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2638         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2639 }
2640
2641 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2642                                       u32 flash_addr, u8 *p_data,
2643                                       int count)
2644 {
2645         u32 word, range, flash_offset, addr = flash_addr, ret;
2646         ulong indirect_add, direct_window;
2647         int i, err = 0;
2648
2649         flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2650         if (addr & 0x3) {
2651                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2652                 return -EIO;
2653         }
2654
2655         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2656                                      (addr & 0xFFFF0000));
2657
2658         range = flash_offset + (count * sizeof(u32));
2659         /* Check if data is spread across multiple sectors */
2660         if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2661
2662                 /* Multi sector read */
2663                 for (i = 0; i < count; i++) {
2664                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2665                         ret = QLCRD32(adapter, indirect_add, &err);
2666                         if (err == -EIO)
2667                                 return err;
2668
2669                         word = ret;
2670                         *(u32 *)p_data  = word;
2671                         p_data = p_data + 4;
2672                         addr = addr + 4;
2673                         flash_offset = flash_offset + 4;
2674
2675                         if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2676                                 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2677                                 /* This write is needed once for each sector */
2678                                 qlcnic_83xx_wrt_reg_indirect(adapter,
2679                                                              direct_window,
2680                                                              (addr));
2681                                 flash_offset = 0;
2682                         }
2683                 }
2684         } else {
2685                 /* Single sector read */
2686                 for (i = 0; i < count; i++) {
2687                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2688                         ret = QLCRD32(adapter, indirect_add, &err);
2689                         if (err == -EIO)
2690                                 return err;
2691
2692                         word = ret;
2693                         *(u32 *)p_data  = word;
2694                         p_data = p_data + 4;
2695                         addr = addr + 4;
2696                 }
2697         }
2698
2699         return 0;
2700 }
2701
2702 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2703 {
2704         u32 status;
2705         int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2706         int err = 0;
2707
2708         do {
2709                 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2710                 if (err == -EIO)
2711                         return err;
2712
2713                 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2714                     QLC_83XX_FLASH_STATUS_READY)
2715                         break;
2716
2717                 usleep_range(1000, 1100);
2718         } while (--retries);
2719
2720         if (!retries)
2721                 return -EIO;
2722
2723         return 0;
2724 }
2725
2726 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2727 {
2728         int ret;
2729         u32 cmd;
2730         cmd = adapter->ahw->fdt.write_statusreg_cmd;
2731         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2732                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2733         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2734                                      adapter->ahw->fdt.write_enable_bits);
2735         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2736                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2737         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2738         if (ret)
2739                 return -EIO;
2740
2741         return 0;
2742 }
2743
2744 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2745 {
2746         int ret;
2747
2748         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2749                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2750                                      adapter->ahw->fdt.write_statusreg_cmd));
2751         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2752                                      adapter->ahw->fdt.write_disable_bits);
2753         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2754                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2755         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2756         if (ret)
2757                 return -EIO;
2758
2759         return 0;
2760 }
2761
2762 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2763 {
2764         int ret, err = 0;
2765         u32 mfg_id;
2766
2767         if (qlcnic_83xx_lock_flash(adapter))
2768                 return -EIO;
2769
2770         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2771                                      QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2772         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2773                                      QLC_83XX_FLASH_READ_CTRL);
2774         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2775         if (ret) {
2776                 qlcnic_83xx_unlock_flash(adapter);
2777                 return -EIO;
2778         }
2779
2780         mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2781         if (err == -EIO) {
2782                 qlcnic_83xx_unlock_flash(adapter);
2783                 return err;
2784         }
2785
2786         adapter->flash_mfg_id = (mfg_id & 0xFF);
2787         qlcnic_83xx_unlock_flash(adapter);
2788
2789         return 0;
2790 }
2791
2792 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2793 {
2794         int count, fdt_size, ret = 0;
2795
2796         fdt_size = sizeof(struct qlcnic_fdt);
2797         count = fdt_size / sizeof(u32);
2798
2799         if (qlcnic_83xx_lock_flash(adapter))
2800                 return -EIO;
2801
2802         memset(&adapter->ahw->fdt, 0, fdt_size);
2803         ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2804                                                 (u8 *)&adapter->ahw->fdt,
2805                                                 count);
2806         qlcnic_swap32_buffer((u32 *)&adapter->ahw->fdt, count);
2807         qlcnic_83xx_unlock_flash(adapter);
2808         return ret;
2809 }
2810
2811 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2812                                    u32 sector_start_addr)
2813 {
2814         u32 reversed_addr, addr1, addr2, cmd;
2815         int ret = -EIO;
2816
2817         if (qlcnic_83xx_lock_flash(adapter) != 0)
2818                 return -EIO;
2819
2820         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2821                 ret = qlcnic_83xx_enable_flash_write(adapter);
2822                 if (ret) {
2823                         qlcnic_83xx_unlock_flash(adapter);
2824                         dev_err(&adapter->pdev->dev,
2825                                 "%s failed at %d\n",
2826                                 __func__, __LINE__);
2827                         return ret;
2828                 }
2829         }
2830
2831         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2832         if (ret) {
2833                 qlcnic_83xx_unlock_flash(adapter);
2834                 dev_err(&adapter->pdev->dev,
2835                         "%s: failed at %d\n", __func__, __LINE__);
2836                 return -EIO;
2837         }
2838
2839         addr1 = (sector_start_addr & 0xFF) << 16;
2840         addr2 = (sector_start_addr & 0xFF0000) >> 16;
2841         reversed_addr = addr1 | addr2 | (sector_start_addr & 0xFF00);
2842
2843         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2844                                      reversed_addr);
2845         cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2846         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2847                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2848         else
2849                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2850                                              QLC_83XX_FLASH_OEM_ERASE_SIG);
2851         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2852                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2853
2854         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2855         if (ret) {
2856                 qlcnic_83xx_unlock_flash(adapter);
2857                 dev_err(&adapter->pdev->dev,
2858                         "%s: failed at %d\n", __func__, __LINE__);
2859                 return -EIO;
2860         }
2861
2862         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2863                 ret = qlcnic_83xx_disable_flash_write(adapter);
2864                 if (ret) {
2865                         qlcnic_83xx_unlock_flash(adapter);
2866                         dev_err(&adapter->pdev->dev,
2867                                 "%s: failed at %d\n", __func__, __LINE__);
2868                         return ret;
2869                 }
2870         }
2871
2872         qlcnic_83xx_unlock_flash(adapter);
2873
2874         return 0;
2875 }
2876
2877 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2878                               u32 *p_data)
2879 {
2880         int ret = -EIO;
2881         u32 addr1 = 0x00800000 | (addr >> 2);
2882
2883         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2884         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2885         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2886                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2887         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2888         if (ret) {
2889                 dev_err(&adapter->pdev->dev,
2890                         "%s: failed at %d\n", __func__, __LINE__);
2891                 return -EIO;
2892         }
2893
2894         return 0;
2895 }
2896
2897 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2898                                  u32 *p_data, int count)
2899 {
2900         u32 temp;
2901         int ret = -EIO, err = 0;
2902
2903         if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2904             (count > QLC_83XX_FLASH_WRITE_MAX)) {
2905                 dev_err(&adapter->pdev->dev,
2906                         "%s: Invalid word count\n", __func__);
2907                 return -EIO;
2908         }
2909
2910         temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2911         if (err == -EIO)
2912                 return err;
2913
2914         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2915                                      (temp | QLC_83XX_FLASH_SPI_CTRL));
2916         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2917                                      QLC_83XX_FLASH_ADDR_TEMP_VAL);
2918
2919         /* First DWORD write */
2920         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2921         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2922                                      QLC_83XX_FLASH_FIRST_MS_PATTERN);
2923         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2924         if (ret) {
2925                 dev_err(&adapter->pdev->dev,
2926                         "%s: failed at %d\n", __func__, __LINE__);
2927                 return -EIO;
2928         }
2929
2930         count--;
2931         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2932                                      QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2933         /* Second to N-1 DWORD writes */
2934         while (count != 1) {
2935                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2936                                              *p_data++);
2937                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2938                                              QLC_83XX_FLASH_SECOND_MS_PATTERN);
2939                 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2940                 if (ret) {
2941                         dev_err(&adapter->pdev->dev,
2942                                 "%s: failed at %d\n", __func__, __LINE__);
2943                         return -EIO;
2944                 }
2945                 count--;
2946         }
2947
2948         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2949                                      QLC_83XX_FLASH_ADDR_TEMP_VAL |
2950                                      (addr >> 2));
2951         /* Last DWORD write */
2952         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2953         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2954                                      QLC_83XX_FLASH_LAST_MS_PATTERN);
2955         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2956         if (ret) {
2957                 dev_err(&adapter->pdev->dev,
2958                         "%s: failed at %d\n", __func__, __LINE__);
2959                 return -EIO;
2960         }
2961
2962         ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2963         if (err == -EIO)
2964                 return err;
2965
2966         if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2967                 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2968                         __func__, __LINE__);
2969                 /* Operation failed, clear error bit */
2970                 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2971                 if (err == -EIO)
2972                         return err;
2973
2974                 qlcnic_83xx_wrt_reg_indirect(adapter,
2975                                              QLC_83XX_FLASH_SPI_CONTROL,
2976                                              (temp | QLC_83XX_FLASH_SPI_CTRL));
2977         }
2978
2979         return 0;
2980 }
2981
2982 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2983 {
2984         u32 val, id;
2985
2986         val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2987
2988         /* Check if recovery need to be performed by the calling function */
2989         if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2990                 val = val & ~0x3F;
2991                 val = val | ((adapter->portnum << 2) |
2992                              QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2993                 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2994                 dev_info(&adapter->pdev->dev,
2995                          "%s: lock recovery initiated\n", __func__);
2996                 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2997                 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2998                 id = ((val >> 2) & 0xF);
2999                 if (id == adapter->portnum) {
3000                         val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
3001                         val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
3002                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
3003                         /* Force release the lock */
3004                         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
3005                         /* Clear recovery bits */
3006                         val = val & ~0x3F;
3007                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
3008                         dev_info(&adapter->pdev->dev,
3009                                  "%s: lock recovery completed\n", __func__);
3010                 } else {
3011                         dev_info(&adapter->pdev->dev,
3012                                  "%s: func %d to resume lock recovery process\n",
3013                                  __func__, id);
3014                 }
3015         } else {
3016                 dev_info(&adapter->pdev->dev,
3017                          "%s: lock recovery initiated by other functions\n",
3018                          __func__);
3019         }
3020 }
3021
3022 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
3023 {
3024         u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
3025         int max_attempt = 0;
3026
3027         while (status == 0) {
3028                 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
3029                 if (status)
3030                         break;
3031
3032                 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
3033                 i++;
3034
3035                 if (i == 1)
3036                         temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3037
3038                 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
3039                         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3040                         if (val == temp) {
3041                                 id = val & 0xFF;
3042                                 dev_info(&adapter->pdev->dev,
3043                                          "%s: lock to be recovered from %d\n",
3044                                          __func__, id);
3045                                 qlcnic_83xx_recover_driver_lock(adapter);
3046                                 i = 0;
3047                                 max_attempt++;
3048                         } else {
3049                                 dev_err(&adapter->pdev->dev,
3050                                         "%s: failed to get lock\n", __func__);
3051                                 return -EIO;
3052                         }
3053                 }
3054
3055                 /* Force exit from while loop after few attempts */
3056                 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
3057                         dev_err(&adapter->pdev->dev,
3058                                 "%s: failed to get lock\n", __func__);
3059                         return -EIO;
3060                 }
3061         }
3062
3063         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3064         lock_alive_counter = val >> 8;
3065         lock_alive_counter++;
3066         val = lock_alive_counter << 8 | adapter->portnum;
3067         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
3068
3069         return 0;
3070 }
3071
3072 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
3073 {
3074         u32 val, lock_alive_counter, id;
3075
3076         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3077         id = val & 0xFF;
3078         lock_alive_counter = val >> 8;
3079
3080         if (id != adapter->portnum)
3081                 dev_err(&adapter->pdev->dev,
3082                         "%s:Warning func %d is unlocking lock owned by %d\n",
3083                         __func__, adapter->portnum, id);
3084
3085         val = (lock_alive_counter << 8) | 0xFF;
3086         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
3087         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
3088 }
3089
3090 int qlcnic_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
3091                                 u32 *data, u32 count)
3092 {
3093         int i, j, ret = 0;
3094         u32 temp;
3095
3096         /* Check alignment */
3097         if (addr & 0xF)
3098                 return -EIO;
3099
3100         mutex_lock(&adapter->ahw->mem_lock);
3101         qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_HI, 0);
3102
3103         for (i = 0; i < count; i++, addr += 16) {
3104                 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
3105                                      QLCNIC_ADDR_QDR_NET_MAX)) ||
3106                       (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
3107                                      QLCNIC_ADDR_DDR_NET_MAX)))) {
3108                         mutex_unlock(&adapter->ahw->mem_lock);
3109                         return -EIO;
3110                 }
3111
3112                 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_LO, addr);
3113                 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_LO, *data++);
3114                 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_HI, *data++);
3115                 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_ULO, *data++);
3116                 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_UHI, *data++);
3117                 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_WRITE_ENABLE);
3118                 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_WRITE_START);
3119
3120                 for (j = 0; j < MAX_CTL_CHECK; j++) {
3121                         temp = qlcnic_ind_rd(adapter, QLCNIC_MS_CTRL);
3122
3123                         if ((temp & TA_CTL_BUSY) == 0)
3124                                 break;
3125                 }
3126
3127                 /* Status check failure */
3128                 if (j >= MAX_CTL_CHECK) {
3129                         printk_ratelimited(KERN_WARNING
3130                                            "MS memory write failed\n");
3131                         mutex_unlock(&adapter->ahw->mem_lock);
3132                         return -EIO;
3133                 }
3134         }
3135
3136         mutex_unlock(&adapter->ahw->mem_lock);
3137
3138         return ret;
3139 }
3140
3141 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
3142                              u8 *p_data, int count)
3143 {
3144         u32 word, addr = flash_addr, ret;
3145         ulong  indirect_addr;
3146         int i, err = 0;
3147
3148         if (qlcnic_83xx_lock_flash(adapter) != 0)
3149                 return -EIO;
3150
3151         if (addr & 0x3) {
3152                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
3153                 qlcnic_83xx_unlock_flash(adapter);
3154                 return -EIO;
3155         }
3156
3157         for (i = 0; i < count; i++) {
3158                 if (qlcnic_83xx_wrt_reg_indirect(adapter,
3159                                                  QLC_83XX_FLASH_DIRECT_WINDOW,
3160                                                  (addr))) {
3161                         qlcnic_83xx_unlock_flash(adapter);
3162                         return -EIO;
3163                 }
3164
3165                 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
3166                 ret = QLCRD32(adapter, indirect_addr, &err);
3167                 if (err == -EIO) {
3168                         qlcnic_83xx_unlock_flash(adapter);
3169                         return err;
3170                 }
3171
3172                 word = ret;
3173                 *(u32 *)p_data  = word;
3174                 p_data = p_data + 4;
3175                 addr = addr + 4;
3176         }
3177
3178         qlcnic_83xx_unlock_flash(adapter);
3179
3180         return 0;
3181 }
3182
3183 void qlcnic_83xx_get_port_type(struct qlcnic_adapter *adapter)
3184 {
3185         struct qlcnic_hardware_context *ahw = adapter->ahw;
3186         struct qlcnic_cmd_args cmd;
3187         u32 config;
3188         int err;
3189
3190         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3191         if (err)
3192                 return;
3193
3194         err = qlcnic_issue_cmd(adapter, &cmd);
3195         if (err) {
3196                 dev_info(&adapter->pdev->dev,
3197                          "Get Link Status Command failed: 0x%x\n", err);
3198                 goto out;
3199         } else {
3200                 config = cmd.rsp.arg[3];
3201
3202                 switch (QLC_83XX_SFP_MODULE_TYPE(config)) {
3203                 case QLC_83XX_MODULE_FIBRE_1000BASE_SX:
3204                 case QLC_83XX_MODULE_FIBRE_1000BASE_LX:
3205                 case QLC_83XX_MODULE_FIBRE_1000BASE_CX:
3206                 case QLC_83XX_MODULE_TP_1000BASE_T:
3207                         ahw->port_type = QLCNIC_GBE;
3208                         break;
3209                 default:
3210                         ahw->port_type = QLCNIC_XGBE;
3211                 }
3212         }
3213 out:
3214         qlcnic_free_mbx_args(&cmd);
3215 }
3216
3217 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
3218 {
3219         u8 pci_func;
3220         int err;
3221         u32 config = 0, state;
3222         struct qlcnic_cmd_args cmd;
3223         struct qlcnic_hardware_context *ahw = adapter->ahw;
3224
3225         if (qlcnic_sriov_vf_check(adapter))
3226                 pci_func = adapter->portnum;
3227         else
3228                 pci_func = ahw->pci_func;
3229
3230         state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
3231         if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
3232                 dev_info(&adapter->pdev->dev, "link state down\n");
3233                 return config;
3234         }
3235
3236         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3237         if (err)
3238                 return err;
3239
3240         err = qlcnic_issue_cmd(adapter, &cmd);
3241         if (err) {
3242                 dev_info(&adapter->pdev->dev,
3243                          "Get Link Status Command failed: 0x%x\n", err);
3244                 goto out;
3245         } else {
3246                 config = cmd.rsp.arg[1];
3247                 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
3248                 case QLC_83XX_10M_LINK:
3249                         ahw->link_speed = SPEED_10;
3250                         break;
3251                 case QLC_83XX_100M_LINK:
3252                         ahw->link_speed = SPEED_100;
3253                         break;
3254                 case QLC_83XX_1G_LINK:
3255                         ahw->link_speed = SPEED_1000;
3256                         break;
3257                 case QLC_83XX_10G_LINK:
3258                         ahw->link_speed = SPEED_10000;
3259                         break;
3260                 default:
3261                         ahw->link_speed = 0;
3262                         break;
3263                 }
3264                 config = cmd.rsp.arg[3];
3265                 switch (QLC_83XX_SFP_MODULE_TYPE(config)) {
3266                 case QLC_83XX_MODULE_FIBRE_10GBASE_LRM:
3267                 case QLC_83XX_MODULE_FIBRE_10GBASE_LR:
3268                 case QLC_83XX_MODULE_FIBRE_10GBASE_SR:
3269                         ahw->supported_type = PORT_FIBRE;
3270                         ahw->port_type = QLCNIC_XGBE;
3271                         break;
3272                 case QLC_83XX_MODULE_FIBRE_1000BASE_SX:
3273                 case QLC_83XX_MODULE_FIBRE_1000BASE_LX:
3274                 case QLC_83XX_MODULE_FIBRE_1000BASE_CX:
3275                         ahw->supported_type = PORT_FIBRE;
3276                         ahw->port_type = QLCNIC_GBE;
3277                         break;
3278                 case QLC_83XX_MODULE_TP_1000BASE_T:
3279                         ahw->supported_type = PORT_TP;
3280                         ahw->port_type = QLCNIC_GBE;
3281                         break;
3282                 case QLC_83XX_MODULE_DA_10GE_PASSIVE_CP:
3283                 case QLC_83XX_MODULE_DA_10GE_ACTIVE_CP:
3284                 case QLC_83XX_MODULE_DA_10GE_LEGACY_CP:
3285                 case QLC_83XX_MODULE_DA_1GE_PASSIVE_CP:
3286                         ahw->supported_type = PORT_DA;
3287                         ahw->port_type = QLCNIC_XGBE;
3288                         break;
3289                 default:
3290                         ahw->supported_type = PORT_OTHER;
3291                         ahw->port_type = QLCNIC_XGBE;
3292                 }
3293                 if (config & 1)
3294                         err = 1;
3295         }
3296 out:
3297         qlcnic_free_mbx_args(&cmd);
3298         return config;
3299 }
3300
3301 int qlcnic_83xx_get_link_ksettings(struct qlcnic_adapter *adapter,
3302                                    struct ethtool_link_ksettings *ecmd)
3303 {
3304         struct qlcnic_hardware_context *ahw = adapter->ahw;
3305         u32 config = 0;
3306         int status = 0;
3307         u32 supported, advertising;
3308
3309         if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
3310                 /* Get port configuration info */
3311                 status = qlcnic_83xx_get_port_info(adapter);
3312                 /* Get Link Status related info */
3313                 config = qlcnic_83xx_test_link(adapter);
3314                 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3315         }
3316
3317         /* hard code until there is a way to get it from flash */
3318         ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3319
3320         if (netif_running(adapter->netdev) && ahw->has_link_events) {
3321                 ecmd->base.speed = ahw->link_speed;
3322                 ecmd->base.duplex = ahw->link_duplex;
3323                 ecmd->base.autoneg = ahw->link_autoneg;
3324         } else {
3325                 ecmd->base.speed = SPEED_UNKNOWN;
3326                 ecmd->base.duplex = DUPLEX_UNKNOWN;
3327                 ecmd->base.autoneg = AUTONEG_DISABLE;
3328         }
3329
3330         supported = (SUPPORTED_10baseT_Full |
3331                            SUPPORTED_100baseT_Full |
3332                            SUPPORTED_1000baseT_Full |
3333                            SUPPORTED_10000baseT_Full |
3334                            SUPPORTED_Autoneg);
3335
3336         ethtool_convert_link_mode_to_legacy_u32(&advertising,
3337                                                 ecmd->link_modes.advertising);
3338
3339         if (ecmd->base.autoneg == AUTONEG_ENABLE) {
3340                 if (ahw->port_config & QLC_83XX_10_CAPABLE)
3341                         advertising |= SUPPORTED_10baseT_Full;
3342                 if (ahw->port_config & QLC_83XX_100_CAPABLE)
3343                         advertising |= SUPPORTED_100baseT_Full;
3344                 if (ahw->port_config & QLC_83XX_1G_CAPABLE)
3345                         advertising |= SUPPORTED_1000baseT_Full;
3346                 if (ahw->port_config & QLC_83XX_10G_CAPABLE)
3347                         advertising |= SUPPORTED_10000baseT_Full;
3348                 if (ahw->port_config & QLC_83XX_AUTONEG_ENABLE)
3349                         advertising |= ADVERTISED_Autoneg;
3350         } else {
3351                 switch (ahw->link_speed) {
3352                 case SPEED_10:
3353                         advertising = SUPPORTED_10baseT_Full;
3354                         break;
3355                 case SPEED_100:
3356                         advertising = SUPPORTED_100baseT_Full;
3357                         break;
3358                 case SPEED_1000:
3359                         advertising = SUPPORTED_1000baseT_Full;
3360                         break;
3361                 case SPEED_10000:
3362                         advertising = SUPPORTED_10000baseT_Full;
3363                         break;
3364                 default:
3365                         break;
3366                 }
3367
3368         }
3369
3370         switch (ahw->supported_type) {
3371         case PORT_FIBRE:
3372                 supported |= SUPPORTED_FIBRE;
3373                 advertising |= ADVERTISED_FIBRE;
3374                 ecmd->base.port = PORT_FIBRE;
3375                 break;
3376         case PORT_TP:
3377                 supported |= SUPPORTED_TP;
3378                 advertising |= ADVERTISED_TP;
3379                 ecmd->base.port = PORT_TP;
3380                 break;
3381         case PORT_DA:
3382                 supported |= SUPPORTED_FIBRE;
3383                 advertising |= ADVERTISED_FIBRE;
3384                 ecmd->base.port = PORT_DA;
3385                 break;
3386         default:
3387                 supported |= SUPPORTED_FIBRE;
3388                 advertising |= ADVERTISED_FIBRE;
3389                 ecmd->base.port = PORT_OTHER;
3390                 break;
3391         }
3392         ecmd->base.phy_address = ahw->physical_port;
3393
3394         ethtool_convert_legacy_u32_to_link_mode(ecmd->link_modes.supported,
3395                                                 supported);
3396         ethtool_convert_legacy_u32_to_link_mode(ecmd->link_modes.advertising,
3397                                                 advertising);
3398
3399         return status;
3400 }
3401
3402 int qlcnic_83xx_set_link_ksettings(struct qlcnic_adapter *adapter,
3403                                    const struct ethtool_link_ksettings *ecmd)
3404 {
3405         struct qlcnic_hardware_context *ahw = adapter->ahw;
3406         u32 config = adapter->ahw->port_config;
3407         int status = 0;
3408
3409         /* 83xx devices do not support Half duplex */
3410         if (ecmd->base.duplex == DUPLEX_HALF) {
3411                 netdev_info(adapter->netdev,
3412                             "Half duplex mode not supported\n");
3413                 return -EINVAL;
3414         }
3415
3416         if (ecmd->base.autoneg) {
3417                 ahw->port_config |= QLC_83XX_AUTONEG_ENABLE;
3418                 ahw->port_config |= (QLC_83XX_100_CAPABLE |
3419                                      QLC_83XX_1G_CAPABLE |
3420                                      QLC_83XX_10G_CAPABLE);
3421         } else { /* force speed */
3422                 ahw->port_config &= ~QLC_83XX_AUTONEG_ENABLE;
3423                 switch (ecmd->base.speed) {
3424                 case SPEED_10:
3425                         ahw->port_config &= ~(QLC_83XX_100_CAPABLE |
3426                                               QLC_83XX_1G_CAPABLE |
3427                                               QLC_83XX_10G_CAPABLE);
3428                         ahw->port_config |= QLC_83XX_10_CAPABLE;
3429                         break;
3430                 case SPEED_100:
3431                         ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3432                                               QLC_83XX_1G_CAPABLE |
3433                                               QLC_83XX_10G_CAPABLE);
3434                         ahw->port_config |= QLC_83XX_100_CAPABLE;
3435                         break;
3436                 case SPEED_1000:
3437                         ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3438                                               QLC_83XX_100_CAPABLE |
3439                                               QLC_83XX_10G_CAPABLE);
3440                         ahw->port_config |= QLC_83XX_1G_CAPABLE;
3441                         break;
3442                 case SPEED_10000:
3443                         ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3444                                               QLC_83XX_100_CAPABLE |
3445                                               QLC_83XX_1G_CAPABLE);
3446                         ahw->port_config |= QLC_83XX_10G_CAPABLE;
3447                         break;
3448                 default:
3449                         return -EINVAL;
3450                 }
3451         }
3452         status = qlcnic_83xx_set_port_config(adapter);
3453         if (status) {
3454                 netdev_info(adapter->netdev,
3455                             "Failed to Set Link Speed and autoneg.\n");
3456                 ahw->port_config = config;
3457         }
3458
3459         return status;
3460 }
3461
3462 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3463                                           u64 *data, int index)
3464 {
3465         u32 low, hi;
3466         u64 val;
3467
3468         low = cmd->rsp.arg[index];
3469         hi = cmd->rsp.arg[index + 1];
3470         val = (((u64) low) | (((u64) hi) << 32));
3471         *data++ = val;
3472         return data;
3473 }
3474
3475 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3476                                    struct qlcnic_cmd_args *cmd, u64 *data,
3477                                    int type, int *ret)
3478 {
3479         int err, k, total_regs;
3480
3481         *ret = 0;
3482         err = qlcnic_issue_cmd(adapter, cmd);
3483         if (err != QLCNIC_RCODE_SUCCESS) {
3484                 dev_info(&adapter->pdev->dev,
3485                          "Error in get statistics mailbox command\n");
3486                 *ret = -EIO;
3487                 return data;
3488         }
3489         total_regs = cmd->rsp.num;
3490         switch (type) {
3491         case QLC_83XX_STAT_MAC:
3492                 /* fill in MAC tx counters */
3493                 for (k = 2; k < 28; k += 2)
3494                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3495                 /* skip 24 bytes of reserved area */
3496                 /* fill in MAC rx counters */
3497                 for (k += 6; k < 60; k += 2)
3498                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3499                 /* skip 24 bytes of reserved area */
3500                 /* fill in MAC rx frame stats */
3501                 for (k += 6; k < 80; k += 2)
3502                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3503                 /* fill in eSwitch stats */
3504                 for (; k < total_regs; k += 2)
3505                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3506                 break;
3507         case QLC_83XX_STAT_RX:
3508                 for (k = 2; k < 8; k += 2)
3509                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3510                 /* skip 8 bytes of reserved data */
3511                 for (k += 2; k < 24; k += 2)
3512                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3513                 /* skip 8 bytes containing RE1FBQ error data */
3514                 for (k += 2; k < total_regs; k += 2)
3515                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3516                 break;
3517         case QLC_83XX_STAT_TX:
3518                 for (k = 2; k < 10; k += 2)
3519                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3520                 /* skip 8 bytes of reserved data */
3521                 for (k += 2; k < total_regs; k += 2)
3522                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3523                 break;
3524         default:
3525                 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3526                 *ret = -EIO;
3527         }
3528         return data;
3529 }
3530
3531 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3532 {
3533         struct qlcnic_cmd_args cmd;
3534         struct net_device *netdev = adapter->netdev;
3535         int ret = 0;
3536
3537         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3538         if (ret)
3539                 return;
3540         /* Get Tx stats */
3541         cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3542         cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3543         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3544                                       QLC_83XX_STAT_TX, &ret);
3545         if (ret) {
3546                 netdev_err(netdev, "Error getting Tx stats\n");
3547                 goto out;
3548         }
3549         /* Get MAC stats */
3550         cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3551         cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3552         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3553         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3554                                       QLC_83XX_STAT_MAC, &ret);
3555         if (ret) {
3556                 netdev_err(netdev, "Error getting MAC stats\n");
3557                 goto out;
3558         }
3559         /* Get Rx stats */
3560         cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3561         cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3562         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3563         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3564                                       QLC_83XX_STAT_RX, &ret);
3565         if (ret)
3566                 netdev_err(netdev, "Error getting Rx stats\n");
3567 out:
3568         qlcnic_free_mbx_args(&cmd);
3569 }
3570
3571 #define QLCNIC_83XX_ADD_PORT0           BIT_0
3572 #define QLCNIC_83XX_ADD_PORT1           BIT_1
3573 #define QLCNIC_83XX_EXTENDED_MEM_SIZE   13 /* In MB */
3574 int qlcnic_83xx_extend_md_capab(struct qlcnic_adapter *adapter)
3575 {
3576         struct qlcnic_cmd_args cmd;
3577         int err;
3578
3579         err = qlcnic_alloc_mbx_args(&cmd, adapter,
3580                                     QLCNIC_CMD_83XX_EXTEND_ISCSI_DUMP_CAP);
3581         if (err)
3582                 return err;
3583
3584         cmd.req.arg[1] = (QLCNIC_83XX_ADD_PORT0 | QLCNIC_83XX_ADD_PORT1);
3585         cmd.req.arg[2] = QLCNIC_83XX_EXTENDED_MEM_SIZE;
3586         cmd.req.arg[3] = QLCNIC_83XX_EXTENDED_MEM_SIZE;
3587
3588         err = qlcnic_issue_cmd(adapter, &cmd);
3589         if (err)
3590                 dev_err(&adapter->pdev->dev,
3591                         "failed to issue extend iSCSI minidump capability\n");
3592
3593         return err;
3594 }
3595
3596 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3597 {
3598         u32 major, minor, sub;
3599
3600         major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3601         minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3602         sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3603
3604         if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3605                 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3606                          __func__);
3607                 return 1;
3608         }
3609         return 0;
3610 }
3611
3612 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3613 {
3614         return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3615                 sizeof(*adapter->ahw->ext_reg_tbl)) +
3616                 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) *
3617                 sizeof(*adapter->ahw->reg_tbl));
3618 }
3619
3620 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3621 {
3622         int i, j = 0;
3623
3624         for (i = QLCNIC_DEV_INFO_SIZE + 1;
3625              j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3626                 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3627
3628         for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3629                 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3630         return i;
3631 }
3632
3633 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3634 {
3635         struct qlcnic_adapter *adapter = netdev_priv(netdev);
3636         struct qlcnic_hardware_context *ahw = adapter->ahw;
3637         struct qlcnic_cmd_args cmd;
3638         u8 val, drv_sds_rings = adapter->drv_sds_rings;
3639         u8 drv_tx_rings = adapter->drv_tx_rings;
3640         u32 data;
3641         u16 intrpt_id, id;
3642         int ret;
3643
3644         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3645                 netdev_info(netdev, "Device is resetting\n");
3646                 return -EBUSY;
3647         }
3648
3649         if (qlcnic_get_diag_lock(adapter)) {
3650                 netdev_info(netdev, "Device in diagnostics mode\n");
3651                 return -EBUSY;
3652         }
3653
3654         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3655                                          drv_sds_rings);
3656         if (ret)
3657                 goto fail_diag_irq;
3658
3659         ahw->diag_cnt = 0;
3660         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3661         if (ret)
3662                 goto fail_mbx_args;
3663
3664         if (adapter->flags & QLCNIC_MSIX_ENABLED)
3665                 intrpt_id = ahw->intr_tbl[0].id;
3666         else
3667                 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3668
3669         cmd.req.arg[1] = 1;
3670         cmd.req.arg[2] = intrpt_id;
3671         cmd.req.arg[3] = BIT_0;
3672
3673         ret = qlcnic_issue_cmd(adapter, &cmd);
3674         data = cmd.rsp.arg[2];
3675         id = LSW(data);
3676         val = LSB(MSW(data));
3677         if (id != intrpt_id)
3678                 dev_info(&adapter->pdev->dev,
3679                          "Interrupt generated: 0x%x, requested:0x%x\n",
3680                          id, intrpt_id);
3681         if (val)
3682                 dev_err(&adapter->pdev->dev,
3683                          "Interrupt test error: 0x%x\n", val);
3684         if (ret)
3685                 goto done;
3686
3687         msleep(20);
3688         ret = !ahw->diag_cnt;
3689
3690 done:
3691         qlcnic_free_mbx_args(&cmd);
3692
3693 fail_mbx_args:
3694         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
3695
3696 fail_diag_irq:
3697         adapter->drv_sds_rings = drv_sds_rings;
3698         adapter->drv_tx_rings = drv_tx_rings;
3699         qlcnic_release_diag_lock(adapter);
3700         return ret;
3701 }
3702
3703 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3704                                 struct ethtool_pauseparam *pause)
3705 {
3706         struct qlcnic_hardware_context *ahw = adapter->ahw;
3707         int status = 0;
3708         u32 config;
3709
3710         status = qlcnic_83xx_get_port_config(adapter);
3711         if (status) {
3712                 dev_err(&adapter->pdev->dev,
3713                         "%s: Get Pause Config failed\n", __func__);
3714                 return;
3715         }
3716         config = ahw->port_config;
3717         if (config & QLC_83XX_CFG_STD_PAUSE) {
3718                 switch (MSW(config)) {
3719                 case QLC_83XX_TX_PAUSE:
3720                         pause->tx_pause = 1;
3721                         break;
3722                 case QLC_83XX_RX_PAUSE:
3723                         pause->rx_pause = 1;
3724                         break;
3725                 case QLC_83XX_TX_RX_PAUSE:
3726                 default:
3727                         /* Backward compatibility for existing
3728                          * flash definitions
3729                          */
3730                         pause->tx_pause = 1;
3731                         pause->rx_pause = 1;
3732                 }
3733         }
3734
3735         if (QLC_83XX_AUTONEG(config))
3736                 pause->autoneg = 1;
3737 }
3738
3739 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3740                                struct ethtool_pauseparam *pause)
3741 {
3742         struct qlcnic_hardware_context *ahw = adapter->ahw;
3743         int status = 0;
3744         u32 config;
3745
3746         status = qlcnic_83xx_get_port_config(adapter);
3747         if (status) {
3748                 dev_err(&adapter->pdev->dev,
3749                         "%s: Get Pause Config failed.\n", __func__);
3750                 return status;
3751         }
3752         config = ahw->port_config;
3753
3754         if (ahw->port_type == QLCNIC_GBE) {
3755                 if (pause->autoneg)
3756                         ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3757                 if (!pause->autoneg)
3758                         ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3759         } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3760                 return -EOPNOTSUPP;
3761         }
3762
3763         if (!(config & QLC_83XX_CFG_STD_PAUSE))
3764                 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3765
3766         if (pause->rx_pause && pause->tx_pause) {
3767                 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3768         } else if (pause->rx_pause && !pause->tx_pause) {
3769                 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3770                 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3771         } else if (pause->tx_pause && !pause->rx_pause) {
3772                 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3773                 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3774         } else if (!pause->rx_pause && !pause->tx_pause) {
3775                 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE |
3776                                       QLC_83XX_CFG_STD_PAUSE);
3777         }
3778         status = qlcnic_83xx_set_port_config(adapter);
3779         if (status) {
3780                 dev_err(&adapter->pdev->dev,
3781                         "%s: Set Pause Config failed.\n", __func__);
3782                 ahw->port_config = config;
3783         }
3784         return status;
3785 }
3786
3787 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3788 {
3789         int ret, err = 0;
3790         u32 temp;
3791
3792         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3793                                      QLC_83XX_FLASH_OEM_READ_SIG);
3794         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3795                                      QLC_83XX_FLASH_READ_CTRL);
3796         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3797         if (ret)
3798                 return -EIO;
3799
3800         temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3801         if (err == -EIO)
3802                 return err;
3803
3804         return temp & 0xFF;
3805 }
3806
3807 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3808 {
3809         int status;
3810
3811         status = qlcnic_83xx_read_flash_status_reg(adapter);
3812         if (status == -EIO) {
3813                 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3814                          __func__);
3815                 return 1;
3816         }
3817         return 0;
3818 }
3819
3820 static int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3821 {
3822         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3823         struct net_device *netdev = adapter->netdev;
3824         int retval;
3825
3826         netif_device_detach(netdev);
3827         qlcnic_cancel_idc_work(adapter);
3828
3829         if (netif_running(netdev))
3830                 qlcnic_down(adapter, netdev);
3831
3832         qlcnic_83xx_disable_mbx_intr(adapter);
3833         cancel_delayed_work_sync(&adapter->idc_aen_work);
3834
3835         retval = pci_save_state(pdev);
3836         if (retval)
3837                 return retval;
3838
3839         return 0;
3840 }
3841
3842 static int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3843 {
3844         struct qlcnic_hardware_context *ahw = adapter->ahw;
3845         struct qlc_83xx_idc *idc = &ahw->idc;
3846         int err = 0;
3847
3848         err = qlcnic_83xx_idc_init(adapter);
3849         if (err)
3850                 return err;
3851
3852         if (ahw->nic_mode == QLCNIC_VNIC_MODE) {
3853                 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3854                         qlcnic_83xx_set_vnic_opmode(adapter);
3855                 } else {
3856                         err = qlcnic_83xx_check_vnic_state(adapter);
3857                         if (err)
3858                                 return err;
3859                 }
3860         }
3861
3862         err = qlcnic_83xx_idc_reattach_driver(adapter);
3863         if (err)
3864                 return err;
3865
3866         qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3867                              idc->delay);
3868         return err;
3869 }
3870
3871 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3872 {
3873         reinit_completion(&mbx->completion);
3874         set_bit(QLC_83XX_MBX_READY, &mbx->status);
3875 }
3876
3877 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3878 {
3879         if (!mbx)
3880                 return;
3881
3882         destroy_workqueue(mbx->work_q);
3883         kfree(mbx);
3884 }
3885
3886 static inline void
3887 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3888                                   struct qlcnic_cmd_args *cmd)
3889 {
3890         atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3891
3892         if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3893                 qlcnic_free_mbx_args(cmd);
3894                 kfree(cmd);
3895                 return;
3896         }
3897         complete(&cmd->completion);
3898 }
3899
3900 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3901 {
3902         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3903         struct list_head *head = &mbx->cmd_q;
3904         struct qlcnic_cmd_args *cmd = NULL;
3905
3906         spin_lock_bh(&mbx->queue_lock);
3907
3908         while (!list_empty(head)) {
3909                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3910                 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3911                          __func__, cmd->cmd_op);
3912                 list_del(&cmd->list);
3913                 mbx->num_cmds--;
3914                 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3915         }
3916
3917         spin_unlock_bh(&mbx->queue_lock);
3918 }
3919
3920 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3921 {
3922         struct qlcnic_hardware_context *ahw = adapter->ahw;
3923         struct qlcnic_mailbox *mbx = ahw->mailbox;
3924         u32 host_mbx_ctrl;
3925
3926         if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3927                 return -EBUSY;
3928
3929         host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3930         if (host_mbx_ctrl) {
3931                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3932                 ahw->idc.collect_dump = 1;
3933                 return -EIO;
3934         }
3935
3936         return 0;
3937 }
3938
3939 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3940                                               u8 issue_cmd)
3941 {
3942         if (issue_cmd)
3943                 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3944         else
3945                 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3946 }
3947
3948 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3949                                         struct qlcnic_cmd_args *cmd)
3950 {
3951         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3952
3953         spin_lock_bh(&mbx->queue_lock);
3954
3955         list_del(&cmd->list);
3956         mbx->num_cmds--;
3957
3958         spin_unlock_bh(&mbx->queue_lock);
3959
3960         qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3961 }
3962
3963 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3964                                        struct qlcnic_cmd_args *cmd)
3965 {
3966         u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3967         struct qlcnic_hardware_context *ahw = adapter->ahw;
3968         int i, j;
3969
3970         if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3971                 mbx_cmd = cmd->req.arg[0];
3972                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3973                 for (i = 1; i < cmd->req.num; i++)
3974                         writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3975         } else {
3976                 fw_hal_version = ahw->fw_hal_version;
3977                 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3978                 total_size = cmd->pay_size + hdr_size;
3979                 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3980                 mbx_cmd = tmp | fw_hal_version << 29;
3981                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3982
3983                 /* Back channel specific operations bits */
3984                 mbx_cmd = 0x1 | 1 << 4;
3985
3986                 if (qlcnic_sriov_pf_check(adapter))
3987                         mbx_cmd |= cmd->func_num << 5;
3988
3989                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3990
3991                 for (i = 2, j = 0; j < hdr_size; i++, j++)
3992                         writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3993                 for (j = 0; j < cmd->pay_size; j++, i++)
3994                         writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3995         }
3996 }
3997
3998 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3999 {
4000         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
4001
4002         if (!mbx)
4003                 return;
4004
4005         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
4006         complete(&mbx->completion);
4007         cancel_work_sync(&mbx->work);
4008         flush_workqueue(mbx->work_q);
4009         qlcnic_83xx_flush_mbx_queue(adapter);
4010 }
4011
4012 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
4013                                        struct qlcnic_cmd_args *cmd,
4014                                        unsigned long *timeout)
4015 {
4016         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
4017
4018         if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
4019                 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
4020                 init_completion(&cmd->completion);
4021                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
4022
4023                 spin_lock_bh(&mbx->queue_lock);
4024
4025                 list_add_tail(&cmd->list, &mbx->cmd_q);
4026                 mbx->num_cmds++;
4027                 cmd->total_cmds = mbx->num_cmds;
4028                 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
4029                 queue_work(mbx->work_q, &mbx->work);
4030
4031                 spin_unlock_bh(&mbx->queue_lock);
4032
4033                 return 0;
4034         }
4035
4036         return -EBUSY;
4037 }
4038
4039 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
4040                                        struct qlcnic_cmd_args *cmd)
4041 {
4042         u8 mac_cmd_rcode;
4043         u32 fw_data;
4044
4045         if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
4046                 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
4047                 mac_cmd_rcode = (u8)fw_data;
4048                 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
4049                     mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
4050                     mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
4051                         cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
4052                         return QLCNIC_RCODE_SUCCESS;
4053                 }
4054         }
4055
4056         return -EINVAL;
4057 }
4058
4059 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
4060                                        struct qlcnic_cmd_args *cmd)
4061 {
4062         struct qlcnic_hardware_context *ahw = adapter->ahw;
4063         struct device *dev = &adapter->pdev->dev;
4064         u8 mbx_err_code;
4065         u32 fw_data;
4066
4067         fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
4068         mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
4069         qlcnic_83xx_get_mbx_data(adapter, cmd);
4070
4071         switch (mbx_err_code) {
4072         case QLCNIC_MBX_RSP_OK:
4073         case QLCNIC_MBX_PORT_RSP_OK:
4074                 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
4075                 break;
4076         default:
4077                 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
4078                         break;
4079
4080                 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
4081                         __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
4082                         ahw->op_mode, mbx_err_code);
4083                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
4084                 qlcnic_dump_mbx(adapter, cmd);
4085         }
4086
4087         return;
4088 }
4089
4090 static inline void qlcnic_dump_mailbox_registers(struct qlcnic_adapter *adapter)
4091 {
4092         struct qlcnic_hardware_context *ahw = adapter->ahw;
4093         u32 offset;
4094
4095         offset = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
4096         dev_info(&adapter->pdev->dev, "Mbx interrupt mask=0x%x, Mbx interrupt enable=0x%x, Host mbx control=0x%x, Fw mbx control=0x%x",
4097                  readl(ahw->pci_base0 + offset),
4098                  QLCRDX(ahw, QLCNIC_MBX_INTR_ENBL),
4099                  QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL),
4100                  QLCRDX(ahw, QLCNIC_FW_MBX_CTRL));
4101 }
4102
4103 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
4104 {
4105         struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
4106                                                   work);
4107         struct qlcnic_adapter *adapter = mbx->adapter;
4108         const struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
4109         struct device *dev = &adapter->pdev->dev;
4110         struct list_head *head = &mbx->cmd_q;
4111         struct qlcnic_hardware_context *ahw;
4112         struct qlcnic_cmd_args *cmd = NULL;
4113         unsigned long flags;
4114
4115         ahw = adapter->ahw;
4116
4117         while (true) {
4118                 if (qlcnic_83xx_check_mbx_status(adapter)) {
4119                         qlcnic_83xx_flush_mbx_queue(adapter);
4120                         return;
4121                 }
4122
4123                 spin_lock_irqsave(&mbx->aen_lock, flags);
4124                 mbx->rsp_status = QLC_83XX_MBX_RESPONSE_WAIT;
4125                 spin_unlock_irqrestore(&mbx->aen_lock, flags);
4126
4127                 spin_lock_bh(&mbx->queue_lock);
4128
4129                 if (list_empty(head)) {
4130                         spin_unlock_bh(&mbx->queue_lock);
4131                         return;
4132                 }
4133                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
4134
4135                 spin_unlock_bh(&mbx->queue_lock);
4136
4137                 mbx_ops->encode_cmd(adapter, cmd);
4138                 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
4139
4140                 if (wait_for_completion_timeout(&mbx->completion,
4141                                                 QLC_83XX_MBX_TIMEOUT)) {
4142                         mbx_ops->decode_resp(adapter, cmd);
4143                         mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
4144                 } else {
4145                         dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
4146                                 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
4147                                 ahw->op_mode);
4148                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
4149                         qlcnic_dump_mailbox_registers(adapter);
4150                         qlcnic_83xx_get_mbx_data(adapter, cmd);
4151                         qlcnic_dump_mbx(adapter, cmd);
4152                         qlcnic_83xx_idc_request_reset(adapter,
4153                                                       QLCNIC_FORCE_FW_DUMP_KEY);
4154                         cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
4155                 }
4156                 mbx_ops->dequeue_cmd(adapter, cmd);
4157         }
4158 }
4159
4160 static const struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
4161         .enqueue_cmd    = qlcnic_83xx_enqueue_mbx_cmd,
4162         .dequeue_cmd    = qlcnic_83xx_dequeue_mbx_cmd,
4163         .decode_resp    = qlcnic_83xx_decode_mbx_rsp,
4164         .encode_cmd     = qlcnic_83xx_encode_mbx_cmd,
4165         .nofity_fw      = qlcnic_83xx_signal_mbx_cmd,
4166 };
4167
4168 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
4169 {
4170         struct qlcnic_hardware_context *ahw = adapter->ahw;
4171         struct qlcnic_mailbox *mbx;
4172
4173         ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
4174         if (!ahw->mailbox)
4175                 return -ENOMEM;
4176
4177         mbx = ahw->mailbox;
4178         mbx->ops = &qlcnic_83xx_mbx_ops;
4179         mbx->adapter = adapter;
4180
4181         spin_lock_init(&mbx->queue_lock);
4182         spin_lock_init(&mbx->aen_lock);
4183         INIT_LIST_HEAD(&mbx->cmd_q);
4184         init_completion(&mbx->completion);
4185
4186         mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
4187         if (mbx->work_q == NULL) {
4188                 kfree(mbx);
4189                 return -ENOMEM;
4190         }
4191
4192         INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
4193         set_bit(QLC_83XX_MBX_READY, &mbx->status);
4194         return 0;
4195 }
4196
4197 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev,
4198                                                       pci_channel_state_t state)
4199 {
4200         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4201
4202         if (state == pci_channel_io_perm_failure)
4203                 return PCI_ERS_RESULT_DISCONNECT;
4204
4205         if (state == pci_channel_io_normal)
4206                 return PCI_ERS_RESULT_RECOVERED;
4207
4208         set_bit(__QLCNIC_AER, &adapter->state);
4209         set_bit(__QLCNIC_RESETTING, &adapter->state);
4210
4211         qlcnic_83xx_aer_stop_poll_work(adapter);
4212
4213         pci_save_state(pdev);
4214         pci_disable_device(pdev);
4215
4216         return PCI_ERS_RESULT_NEED_RESET;
4217 }
4218
4219 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev)
4220 {
4221         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4222         int err = 0;
4223
4224         pdev->error_state = pci_channel_io_normal;
4225         err = pci_enable_device(pdev);
4226         if (err)
4227                 goto disconnect;
4228
4229         pci_set_power_state(pdev, PCI_D0);
4230         pci_set_master(pdev);
4231         pci_restore_state(pdev);
4232
4233         err = qlcnic_83xx_aer_reset(adapter);
4234         if (err == 0)
4235                 return PCI_ERS_RESULT_RECOVERED;
4236 disconnect:
4237         clear_bit(__QLCNIC_AER, &adapter->state);
4238         clear_bit(__QLCNIC_RESETTING, &adapter->state);
4239         return PCI_ERS_RESULT_DISCONNECT;
4240 }
4241
4242 static void qlcnic_83xx_io_resume(struct pci_dev *pdev)
4243 {
4244         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4245
4246         pci_cleanup_aer_uncorrect_error_status(pdev);
4247         if (test_and_clear_bit(__QLCNIC_AER, &adapter->state))
4248                 qlcnic_83xx_aer_start_poll_work(adapter);
4249 }