2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
8 #include <linux/if_vlan.h>
9 #include <linux/ipv6.h>
10 #include <linux/ethtool.h>
11 #include <linux/interrupt.h>
12 #include <linux/aer.h>
15 #include "qlcnic_sriov.h"
17 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *);
18 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);
19 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,
20 struct qlcnic_cmd_args *);
21 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);
22 static irqreturn_t qlcnic_83xx_handle_aen(int, void *);
23 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *,
25 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);
26 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *);
27 static void qlcnic_83xx_io_resume(struct pci_dev *);
28 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);
29 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *);
30 static int qlcnic_83xx_resume(struct qlcnic_adapter *);
31 static int qlcnic_83xx_shutdown(struct pci_dev *);
32 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *);
34 #define RSS_HASHTYPE_IP_TCP 0x3
35 #define QLC_83XX_FW_MBX_CMD 0
36 #define QLC_SKIP_INACTIVE_PCI_REGS 7
37 #define QLC_MAX_LEGACY_FUNC_SUPP 8
39 /* 83xx Module type */
40 #define QLC_83XX_MODULE_FIBRE_10GBASE_LRM 0x1 /* 10GBase-LRM */
41 #define QLC_83XX_MODULE_FIBRE_10GBASE_LR 0x2 /* 10GBase-LR */
42 #define QLC_83XX_MODULE_FIBRE_10GBASE_SR 0x3 /* 10GBase-SR */
43 #define QLC_83XX_MODULE_DA_10GE_PASSIVE_CP 0x4 /* 10GE passive
46 #define QLC_83XX_MODULE_DA_10GE_ACTIVE_CP 0x5 /* 10GE active limiting
49 #define QLC_83XX_MODULE_DA_10GE_LEGACY_CP 0x6 /* 10GE passive copper
50 * (legacy, best effort)
52 #define QLC_83XX_MODULE_FIBRE_1000BASE_SX 0x7 /* 1000Base-SX */
53 #define QLC_83XX_MODULE_FIBRE_1000BASE_LX 0x8 /* 1000Base-LX */
54 #define QLC_83XX_MODULE_FIBRE_1000BASE_CX 0x9 /* 1000Base-CX */
55 #define QLC_83XX_MODULE_TP_1000BASE_T 0xa /* 1000Base-T*/
56 #define QLC_83XX_MODULE_DA_1GE_PASSIVE_CP 0xb /* 1GE passive copper
57 * (legacy, best effort)
59 #define QLC_83XX_MODULE_UNKNOWN 0xf /* Unknown module type */
62 #define QLC_83XX_10_CAPABLE BIT_8
63 #define QLC_83XX_100_CAPABLE BIT_9
64 #define QLC_83XX_1G_CAPABLE BIT_10
65 #define QLC_83XX_10G_CAPABLE BIT_11
66 #define QLC_83XX_AUTONEG_ENABLE BIT_15
68 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
69 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
70 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
71 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
72 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
73 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
74 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
75 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
76 {QLCNIC_CMD_INTRPT_TEST, 22, 12},
77 {QLCNIC_CMD_SET_MTU, 3, 1},
78 {QLCNIC_CMD_READ_PHY, 4, 2},
79 {QLCNIC_CMD_WRITE_PHY, 5, 1},
80 {QLCNIC_CMD_READ_HW_REG, 4, 1},
81 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
82 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
83 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
84 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
85 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
86 {QLCNIC_CMD_GET_PCI_INFO, 1, 129},
87 {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
88 {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
89 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
90 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
91 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
92 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
93 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
94 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
95 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
96 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
97 {QLCNIC_CMD_TEMP_SIZE, 1, 4},
98 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
99 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
100 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
101 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
102 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
103 {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
104 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
105 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
106 {QLCNIC_CMD_GET_STATISTICS, 2, 80},
107 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
108 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
109 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
110 {QLCNIC_CMD_IDC_ACK, 5, 1},
111 {QLCNIC_CMD_INIT_NIC_FUNC, 3, 1},
112 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
113 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
114 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
115 {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
116 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
117 {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
118 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
119 {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
120 {QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50},
121 {QLCNIC_CMD_SET_INGRESS_ENCAP, 2, 1},
122 {QLCNIC_CMD_83XX_EXTEND_ISCSI_DUMP_CAP, 4, 1},
125 const u32 qlcnic_83xx_ext_reg_tbl[] = {
126 0x38CC, /* Global Reset */
127 0x38F0, /* Wildcard */
128 0x38FC, /* Informant */
129 0x3038, /* Host MBX ctrl */
130 0x303C, /* FW MBX ctrl */
131 0x355C, /* BOOT LOADER ADDRESS REG */
132 0x3560, /* BOOT LOADER SIZE REG */
133 0x3564, /* FW IMAGE ADDR REG */
134 0x1000, /* MBX intr enable */
135 0x1200, /* Default Intr mask */
136 0x1204, /* Default Interrupt ID */
137 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
138 0x3784, /* QLC_83XX_IDC_DEV_STATE */
139 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
140 0x378C, /* QLC_83XX_IDC_DRV_ACK */
141 0x3790, /* QLC_83XX_IDC_CTRL */
142 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
143 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
144 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
145 0x37A0, /* QLC_83XX_IDC_PF_0 */
146 0x37A4, /* QLC_83XX_IDC_PF_1 */
147 0x37A8, /* QLC_83XX_IDC_PF_2 */
148 0x37AC, /* QLC_83XX_IDC_PF_3 */
149 0x37B0, /* QLC_83XX_IDC_PF_4 */
150 0x37B4, /* QLC_83XX_IDC_PF_5 */
151 0x37B8, /* QLC_83XX_IDC_PF_6 */
152 0x37BC, /* QLC_83XX_IDC_PF_7 */
153 0x37C0, /* QLC_83XX_IDC_PF_8 */
154 0x37C4, /* QLC_83XX_IDC_PF_9 */
155 0x37C8, /* QLC_83XX_IDC_PF_10 */
156 0x37CC, /* QLC_83XX_IDC_PF_11 */
157 0x37D0, /* QLC_83XX_IDC_PF_12 */
158 0x37D4, /* QLC_83XX_IDC_PF_13 */
159 0x37D8, /* QLC_83XX_IDC_PF_14 */
160 0x37DC, /* QLC_83XX_IDC_PF_15 */
161 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
162 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
163 0x37F0, /* QLC_83XX_DRV_OP_MODE */
164 0x37F4, /* QLC_83XX_VNIC_STATE */
165 0x3868, /* QLC_83XX_DRV_LOCK */
166 0x386C, /* QLC_83XX_DRV_UNLOCK */
167 0x3504, /* QLC_83XX_DRV_LOCK_ID */
168 0x34A4, /* QLC_83XX_ASIC_TEMP */
171 const u32 qlcnic_83xx_reg_tbl[] = {
172 0x34A8, /* PEG_HALT_STAT1 */
173 0x34AC, /* PEG_HALT_STAT2 */
174 0x34B0, /* FW_HEARTBEAT */
175 0x3500, /* FLASH LOCK_ID */
176 0x3528, /* FW_CAPABILITIES */
177 0x3538, /* Driver active, DRV_REG0 */
178 0x3540, /* Device state, DRV_REG1 */
179 0x3544, /* Driver state, DRV_REG2 */
180 0x3548, /* Driver scratch, DRV_REG3 */
181 0x354C, /* Device partiton info, DRV_REG4 */
182 0x3524, /* Driver IDC ver, DRV_REG5 */
183 0x3550, /* FW_VER_MAJOR */
184 0x3554, /* FW_VER_MINOR */
185 0x3558, /* FW_VER_SUB */
186 0x359C, /* NPAR STATE */
187 0x35FC, /* FW_IMG_VALID */
188 0x3650, /* CMD_PEG_STATE */
189 0x373C, /* RCV_PEG_STATE */
190 0x37B4, /* ASIC TEMP */
192 0x3570, /* DRV OP MODE */
193 0x3850, /* FLASH LOCK */
194 0x3854, /* FLASH UNLOCK */
197 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
198 .read_crb = qlcnic_83xx_read_crb,
199 .write_crb = qlcnic_83xx_write_crb,
200 .read_reg = qlcnic_83xx_rd_reg_indirect,
201 .write_reg = qlcnic_83xx_wrt_reg_indirect,
202 .get_mac_address = qlcnic_83xx_get_mac_address,
203 .setup_intr = qlcnic_83xx_setup_intr,
204 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
205 .mbx_cmd = qlcnic_83xx_issue_cmd,
206 .get_func_no = qlcnic_83xx_get_func_no,
207 .api_lock = qlcnic_83xx_cam_lock,
208 .api_unlock = qlcnic_83xx_cam_unlock,
209 .add_sysfs = qlcnic_83xx_add_sysfs,
210 .remove_sysfs = qlcnic_83xx_remove_sysfs,
211 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
212 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
213 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
214 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
215 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
216 .setup_link_event = qlcnic_83xx_setup_link_event,
217 .get_nic_info = qlcnic_83xx_get_nic_info,
218 .get_pci_info = qlcnic_83xx_get_pci_info,
219 .set_nic_info = qlcnic_83xx_set_nic_info,
220 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
221 .napi_enable = qlcnic_83xx_napi_enable,
222 .napi_disable = qlcnic_83xx_napi_disable,
223 .config_intr_coal = qlcnic_83xx_config_intr_coal,
224 .config_rss = qlcnic_83xx_config_rss,
225 .config_hw_lro = qlcnic_83xx_config_hw_lro,
226 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
227 .change_l2_filter = qlcnic_83xx_change_l2_filter,
228 .get_board_info = qlcnic_83xx_get_port_info,
229 .set_mac_filter_count = qlcnic_83xx_set_mac_filter_count,
230 .free_mac_list = qlcnic_82xx_free_mac_list,
231 .io_error_detected = qlcnic_83xx_io_error_detected,
232 .io_slot_reset = qlcnic_83xx_io_slot_reset,
233 .io_resume = qlcnic_83xx_io_resume,
234 .get_beacon_state = qlcnic_83xx_get_beacon_state,
235 .enable_sds_intr = qlcnic_83xx_enable_sds_intr,
236 .disable_sds_intr = qlcnic_83xx_disable_sds_intr,
237 .enable_tx_intr = qlcnic_83xx_enable_tx_intr,
238 .disable_tx_intr = qlcnic_83xx_disable_tx_intr,
239 .get_saved_state = qlcnic_83xx_get_saved_state,
240 .set_saved_state = qlcnic_83xx_set_saved_state,
241 .cache_tmpl_hdr_values = qlcnic_83xx_cache_tmpl_hdr_values,
242 .get_cap_size = qlcnic_83xx_get_cap_size,
243 .set_sys_info = qlcnic_83xx_set_sys_info,
244 .store_cap_mask = qlcnic_83xx_store_cap_mask,
245 .encap_rx_offload = qlcnic_83xx_encap_rx_offload,
246 .encap_tx_offload = qlcnic_83xx_encap_tx_offload,
249 static struct qlcnic_nic_template qlcnic_83xx_ops = {
250 .config_bridged_mode = qlcnic_config_bridged_mode,
251 .config_led = qlcnic_config_led,
252 .request_reset = qlcnic_83xx_idc_request_reset,
253 .cancel_idc_work = qlcnic_83xx_idc_exit,
254 .napi_add = qlcnic_83xx_napi_add,
255 .napi_del = qlcnic_83xx_napi_del,
256 .config_ipaddr = qlcnic_83xx_config_ipaddr,
257 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
258 .shutdown = qlcnic_83xx_shutdown,
259 .resume = qlcnic_83xx_resume,
262 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
264 ahw->hw_ops = &qlcnic_83xx_hw_ops;
265 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
266 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
269 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
271 u32 fw_major, fw_minor, fw_build;
272 struct pci_dev *pdev = adapter->pdev;
274 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
275 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
276 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
277 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
279 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
280 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
282 return adapter->fw_version;
285 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
290 base = adapter->ahw->pci_base0 +
291 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
300 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
303 struct qlcnic_hardware_context *ahw = adapter->ahw;
305 *err = __qlcnic_set_win_base(adapter, (u32) addr);
307 return QLCRDX(ahw, QLCNIC_WILDCARD);
309 dev_err(&adapter->pdev->dev,
310 "%s failed, addr = 0x%lx\n", __func__, addr);
315 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
319 struct qlcnic_hardware_context *ahw = adapter->ahw;
321 err = __qlcnic_set_win_base(adapter, (u32) addr);
323 QLCWRX(ahw, QLCNIC_WILDCARD, data);
326 dev_err(&adapter->pdev->dev,
327 "%s failed, addr = 0x%x data = 0x%x\n",
328 __func__, (int)addr, data);
333 static void qlcnic_83xx_enable_legacy(struct qlcnic_adapter *adapter)
335 struct qlcnic_hardware_context *ahw = adapter->ahw;
337 /* MSI-X enablement failed, use legacy interrupt */
338 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
339 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
340 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
341 adapter->msix_entries[0].vector = adapter->pdev->irq;
342 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
345 static int qlcnic_83xx_calculate_msix_vector(struct qlcnic_adapter *adapter)
349 num_msix = adapter->drv_sds_rings;
351 /* account for AEN interrupt MSI-X based interrupts */
354 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
355 num_msix += adapter->drv_tx_rings;
360 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter)
362 struct qlcnic_hardware_context *ahw = adapter->ahw;
363 int err, i, num_msix;
365 if (adapter->flags & QLCNIC_TSS_RSS) {
366 err = qlcnic_setup_tss_rss_intr(adapter);
369 num_msix = ahw->num_msix;
371 num_msix = qlcnic_83xx_calculate_msix_vector(adapter);
373 err = qlcnic_enable_msix(adapter, num_msix);
377 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
378 num_msix = ahw->num_msix;
380 if (qlcnic_sriov_vf_check(adapter))
383 adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
384 adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
388 /* setup interrupt mapping table for fw */
389 ahw->intr_tbl = vzalloc(num_msix *
390 sizeof(struct qlcnic_intrpt_config));
394 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
395 if (adapter->ahw->pci_func >= QLC_MAX_LEGACY_FUNC_SUPP) {
396 dev_err(&adapter->pdev->dev, "PCI function number 8 and higher are not supported with legacy interrupt, func 0x%x\n",
401 qlcnic_83xx_enable_legacy(adapter);
404 for (i = 0; i < num_msix; i++) {
405 if (adapter->flags & QLCNIC_MSIX_ENABLED)
406 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
408 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
409 ahw->intr_tbl[i].id = i;
410 ahw->intr_tbl[i].src = 0;
416 static inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
418 writel(0, adapter->tgt_mask_reg);
421 static inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
423 if (adapter->tgt_mask_reg)
424 writel(1, adapter->tgt_mask_reg);
427 static inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
432 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
433 * source register. We could be here before contexts are created
434 * and sds_ring->crb_intr_mask has not been initialized, calculate
435 * BAR offset for Interrupt Source Register
437 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
438 writel(0, adapter->ahw->pci_base0 + mask);
441 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
445 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
446 writel(1, adapter->ahw->pci_base0 + mask);
447 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
450 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
451 struct qlcnic_cmd_args *cmd)
455 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
458 for (i = 0; i < cmd->rsp.num; i++)
459 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
462 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
465 struct qlcnic_hardware_context *ahw = adapter->ahw;
468 intr_val = readl(adapter->tgt_status_reg);
470 if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
473 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
474 adapter->stats.spurious_intr++;
477 /* The barrier is required to ensure writes to the registers */
480 /* clear the interrupt trigger control register */
481 writel(0, adapter->isr_int_vec);
482 intr_val = readl(adapter->isr_int_vec);
484 intr_val = readl(adapter->tgt_status_reg);
485 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
488 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
489 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
494 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
496 mbx->rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
497 complete(&mbx->completion);
500 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
502 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
503 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
506 spin_lock_irqsave(&mbx->aen_lock, flags);
507 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
508 if (!(resp & QLCNIC_SET_OWNER))
511 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
512 if (event & QLCNIC_MBX_ASYNC_EVENT) {
513 __qlcnic_83xx_process_aen(adapter);
515 if (mbx->rsp_status != rsp_status)
516 qlcnic_83xx_notify_mbx_response(mbx);
519 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
520 spin_unlock_irqrestore(&mbx->aen_lock, flags);
523 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
525 struct qlcnic_adapter *adapter = data;
526 struct qlcnic_host_sds_ring *sds_ring;
527 struct qlcnic_hardware_context *ahw = adapter->ahw;
529 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
532 qlcnic_83xx_poll_process_aen(adapter);
534 if (ahw->diag_test) {
535 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST)
537 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
541 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
542 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
544 sds_ring = &adapter->recv_ctx->sds_rings[0];
545 napi_schedule(&sds_ring->napi);
551 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
553 struct qlcnic_host_sds_ring *sds_ring = data;
554 struct qlcnic_adapter *adapter = sds_ring->adapter;
556 if (adapter->flags & QLCNIC_MSIX_ENABLED)
559 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
563 adapter->ahw->diag_cnt++;
564 qlcnic_enable_sds_intr(adapter, sds_ring);
569 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
573 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
574 qlcnic_83xx_set_legacy_intr_mask(adapter);
576 qlcnic_83xx_disable_mbx_intr(adapter);
578 if (adapter->flags & QLCNIC_MSIX_ENABLED)
579 num_msix = adapter->ahw->num_msix - 1;
585 if (adapter->msix_entries) {
586 synchronize_irq(adapter->msix_entries[num_msix].vector);
587 free_irq(adapter->msix_entries[num_msix].vector, adapter);
591 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
593 irq_handler_t handler;
596 unsigned long flags = 0;
598 if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
599 !(adapter->flags & QLCNIC_MSIX_ENABLED))
600 flags |= IRQF_SHARED;
602 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
603 handler = qlcnic_83xx_handle_aen;
604 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
605 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
607 dev_err(&adapter->pdev->dev,
608 "failed to register MBX interrupt\n");
612 handler = qlcnic_83xx_intr;
613 val = adapter->msix_entries[0].vector;
614 err = request_irq(val, handler, flags, "qlcnic", adapter);
616 dev_err(&adapter->pdev->dev,
617 "failed to register INTx interrupt\n");
620 qlcnic_83xx_clear_legacy_intr_mask(adapter);
623 /* Enable mailbox interrupt */
624 qlcnic_83xx_enable_mbx_interrupt(adapter);
629 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
631 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
632 adapter->ahw->pci_func = (val >> 24) & 0xff;
635 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
640 struct qlcnic_hardware_context *ahw = adapter->ahw;
642 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
646 /* write the function number to register */
647 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
651 usleep_range(1000, 2000);
652 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
657 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
661 struct qlcnic_hardware_context *ahw = adapter->ahw;
663 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
667 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
668 loff_t offset, size_t size)
673 if (qlcnic_api_lock(adapter)) {
674 dev_err(&adapter->pdev->dev,
675 "%s: failed to acquire lock. addr offset 0x%x\n",
676 __func__, (u32)offset);
680 data = QLCRD32(adapter, (u32) offset, &ret);
681 qlcnic_api_unlock(adapter);
684 dev_err(&adapter->pdev->dev,
685 "%s: failed. addr offset 0x%x\n",
686 __func__, (u32)offset);
689 memcpy(buf, &data, size);
692 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
693 loff_t offset, size_t size)
697 memcpy(&data, buf, size);
698 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
701 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
703 struct qlcnic_hardware_context *ahw = adapter->ahw;
706 status = qlcnic_83xx_get_port_config(adapter);
708 dev_err(&adapter->pdev->dev,
709 "Get Port Info failed\n");
712 if (ahw->port_config & QLC_83XX_10G_CAPABLE) {
713 ahw->port_type = QLCNIC_XGBE;
714 } else if (ahw->port_config & QLC_83XX_10_CAPABLE ||
715 ahw->port_config & QLC_83XX_100_CAPABLE ||
716 ahw->port_config & QLC_83XX_1G_CAPABLE) {
717 ahw->port_type = QLCNIC_GBE;
719 ahw->port_type = QLCNIC_XGBE;
722 if (QLC_83XX_AUTONEG(ahw->port_config))
723 ahw->link_autoneg = AUTONEG_ENABLE;
729 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
731 struct qlcnic_hardware_context *ahw = adapter->ahw;
732 u16 act_pci_fn = ahw->total_nic_func;
735 ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
737 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
740 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
742 ahw->max_uc_count = count;
745 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
749 if (adapter->flags & QLCNIC_MSIX_ENABLED)
750 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
754 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
755 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
758 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
759 const struct pci_device_id *ent)
761 u32 op_mode, priv_level;
762 struct qlcnic_hardware_context *ahw = adapter->ahw;
764 ahw->fw_hal_version = 2;
765 qlcnic_get_func_no(adapter);
767 if (qlcnic_sriov_vf_check(adapter)) {
768 qlcnic_sriov_vf_set_ops(adapter);
772 /* Determine function privilege level */
773 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
774 if (op_mode == QLC_83XX_DEFAULT_OPMODE)
775 priv_level = QLCNIC_MGMT_FUNC;
777 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
780 if (priv_level == QLCNIC_NON_PRIV_FUNC) {
781 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
782 dev_info(&adapter->pdev->dev,
783 "HAL Version: %d Non Privileged function\n",
784 ahw->fw_hal_version);
785 adapter->nic_ops = &qlcnic_vf_ops;
787 if (pci_find_ext_capability(adapter->pdev,
788 PCI_EXT_CAP_ID_SRIOV))
789 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
790 adapter->nic_ops = &qlcnic_83xx_ops;
794 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
796 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
799 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
800 struct qlcnic_cmd_args *cmd)
804 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
807 dev_info(&adapter->pdev->dev,
808 "Host MBX regs(%d)\n", cmd->req.num);
809 for (i = 0; i < cmd->req.num; i++) {
812 pr_info("%08x ", cmd->req.arg[i]);
815 dev_info(&adapter->pdev->dev,
816 "FW MBX regs(%d)\n", cmd->rsp.num);
817 for (i = 0; i < cmd->rsp.num; i++) {
820 pr_info("%08x ", cmd->rsp.arg[i]);
825 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
826 struct qlcnic_cmd_args *cmd)
828 struct qlcnic_hardware_context *ahw = adapter->ahw;
829 int opcode = LSW(cmd->req.arg[0]);
830 unsigned long max_loops;
832 max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
834 for (; max_loops; max_loops--) {
835 if (atomic_read(&cmd->rsp_status) ==
836 QLC_83XX_MBX_RESPONSE_ARRIVED)
842 dev_err(&adapter->pdev->dev,
843 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
844 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
845 flush_workqueue(ahw->mailbox->work_q);
849 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
850 struct qlcnic_cmd_args *cmd)
852 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
853 struct qlcnic_hardware_context *ahw = adapter->ahw;
854 int cmd_type, err, opcode;
855 unsigned long timeout;
860 opcode = LSW(cmd->req.arg[0]);
861 cmd_type = cmd->type;
862 err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
864 dev_err(&adapter->pdev->dev,
865 "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
866 __func__, opcode, cmd->type, ahw->pci_func,
872 case QLC_83XX_MBX_CMD_WAIT:
873 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
874 dev_err(&adapter->pdev->dev,
875 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
876 __func__, opcode, cmd_type, ahw->pci_func,
878 flush_workqueue(mbx->work_q);
881 case QLC_83XX_MBX_CMD_NO_WAIT:
883 case QLC_83XX_MBX_CMD_BUSY_WAIT:
884 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
887 dev_err(&adapter->pdev->dev,
888 "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
889 __func__, opcode, cmd_type, ahw->pci_func,
891 qlcnic_83xx_detach_mailbox_work(adapter);
894 return cmd->rsp_opcode;
897 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
898 struct qlcnic_adapter *adapter, u32 type)
902 const struct qlcnic_mailbox_metadata *mbx_tbl;
904 memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
905 mbx_tbl = qlcnic_83xx_mbx_tbl;
906 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
907 for (i = 0; i < size; i++) {
908 if (type == mbx_tbl[i].cmd) {
909 mbx->op_type = QLC_83XX_FW_MBX_CMD;
910 mbx->req.num = mbx_tbl[i].in_args;
911 mbx->rsp.num = mbx_tbl[i].out_args;
912 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
916 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
923 temp = adapter->ahw->fw_hal_version << 29;
924 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
930 dev_err(&adapter->pdev->dev, "%s: Invalid mailbox command opcode 0x%x\n",
935 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
937 struct qlcnic_adapter *adapter;
938 struct qlcnic_cmd_args cmd;
941 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
942 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
946 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
947 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
949 err = qlcnic_issue_cmd(adapter, &cmd);
951 dev_info(&adapter->pdev->dev,
952 "%s: Mailbox IDC ACK failed.\n", __func__);
953 qlcnic_free_mbx_args(&cmd);
956 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
959 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
960 QLCNIC_MBX_RSP(data[0]));
961 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
965 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
967 struct qlcnic_hardware_context *ahw = adapter->ahw;
968 u32 event[QLC_83XX_MBX_AEN_CNT];
971 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
972 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
974 switch (QLCNIC_MBX_RSP(event[0])) {
976 case QLCNIC_MBX_LINK_EVENT:
977 qlcnic_83xx_handle_link_aen(adapter, event);
979 case QLCNIC_MBX_COMP_EVENT:
980 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
982 case QLCNIC_MBX_REQUEST_EVENT:
983 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
984 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
985 queue_delayed_work(adapter->qlcnic_wq,
986 &adapter->idc_aen_work, 0);
988 case QLCNIC_MBX_TIME_EXTEND_EVENT:
989 ahw->extend_lb_time = event[1] >> 8 & 0xf;
991 case QLCNIC_MBX_BC_EVENT:
992 qlcnic_sriov_handle_bc_event(adapter, event[1]);
994 case QLCNIC_MBX_SFP_INSERT_EVENT:
995 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
996 QLCNIC_MBX_RSP(event[0]));
998 case QLCNIC_MBX_SFP_REMOVE_EVENT:
999 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
1000 QLCNIC_MBX_RSP(event[0]));
1002 case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
1003 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]);
1006 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
1007 QLCNIC_MBX_RSP(event[0]));
1011 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
1014 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
1016 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
1017 struct qlcnic_hardware_context *ahw = adapter->ahw;
1018 struct qlcnic_mailbox *mbx = ahw->mailbox;
1019 unsigned long flags;
1021 spin_lock_irqsave(&mbx->aen_lock, flags);
1022 resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
1023 if (resp & QLCNIC_SET_OWNER) {
1024 event = readl(QLCNIC_MBX_FW(ahw, 0));
1025 if (event & QLCNIC_MBX_ASYNC_EVENT) {
1026 __qlcnic_83xx_process_aen(adapter);
1028 if (mbx->rsp_status != rsp_status)
1029 qlcnic_83xx_notify_mbx_response(mbx);
1032 spin_unlock_irqrestore(&mbx->aen_lock, flags);
1035 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
1037 struct qlcnic_adapter *adapter;
1039 adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
1041 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1044 qlcnic_83xx_process_aen(adapter);
1045 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
1049 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
1051 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1054 INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
1055 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
1058 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
1060 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1062 cancel_delayed_work_sync(&adapter->mbx_poll_work);
1065 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
1067 int index, i, err, sds_mbx_size;
1068 u32 *buf, intrpt_id, intr_mask;
1071 struct qlcnic_cmd_args cmd;
1072 struct qlcnic_host_sds_ring *sds;
1073 struct qlcnic_sds_mbx sds_mbx;
1074 struct qlcnic_add_rings_mbx_out *mbx_out;
1075 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1076 struct qlcnic_hardware_context *ahw = adapter->ahw;
1078 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1079 context_id = recv_ctx->context_id;
1080 num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS;
1081 err = ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
1082 QLCNIC_CMD_ADD_RCV_RINGS);
1084 dev_err(&adapter->pdev->dev,
1085 "Failed to alloc mbx args %d\n", err);
1089 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
1091 /* set up status rings, mbx 2-81 */
1093 for (i = 8; i < adapter->drv_sds_rings; i++) {
1094 memset(&sds_mbx, 0, sds_mbx_size);
1095 sds = &recv_ctx->sds_rings[i];
1097 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1098 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1099 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1100 sds_mbx.sds_ring_size = sds->num_desc;
1102 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1103 intrpt_id = ahw->intr_tbl[i].id;
1105 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1107 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1108 sds_mbx.intrpt_id = intrpt_id;
1110 sds_mbx.intrpt_id = 0xffff;
1111 sds_mbx.intrpt_val = 0;
1112 buf = &cmd.req.arg[index];
1113 memcpy(buf, &sds_mbx, sds_mbx_size);
1114 index += sds_mbx_size / sizeof(u32);
1117 /* send the mailbox command */
1118 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1120 dev_err(&adapter->pdev->dev,
1121 "Failed to add rings %d\n", err);
1125 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1127 /* status descriptor ring */
1128 for (i = 8; i < adapter->drv_sds_rings; i++) {
1129 sds = &recv_ctx->sds_rings[i];
1130 sds->crb_sts_consumer = ahw->pci_base0 +
1131 mbx_out->host_csmr[index];
1132 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1133 intr_mask = ahw->intr_tbl[i].src;
1135 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1137 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1141 qlcnic_free_mbx_args(&cmd);
1145 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1149 struct qlcnic_cmd_args cmd;
1150 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1152 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1155 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1156 cmd.req.arg[0] |= (0x3 << 29);
1158 if (qlcnic_sriov_pf_check(adapter))
1159 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1161 cmd.req.arg[1] = recv_ctx->context_id | temp;
1162 err = qlcnic_issue_cmd(adapter, &cmd);
1164 dev_err(&adapter->pdev->dev,
1165 "Failed to destroy rx ctx in firmware\n");
1167 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1168 qlcnic_free_mbx_args(&cmd);
1171 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1173 int i, err, index, sds_mbx_size, rds_mbx_size;
1174 u8 num_sds, num_rds;
1175 u32 *buf, intrpt_id, intr_mask, cap = 0;
1176 struct qlcnic_host_sds_ring *sds;
1177 struct qlcnic_host_rds_ring *rds;
1178 struct qlcnic_sds_mbx sds_mbx;
1179 struct qlcnic_rds_mbx rds_mbx;
1180 struct qlcnic_cmd_args cmd;
1181 struct qlcnic_rcv_mbx_out *mbx_out;
1182 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1183 struct qlcnic_hardware_context *ahw = adapter->ahw;
1184 num_rds = adapter->max_rds_rings;
1186 if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS)
1187 num_sds = adapter->drv_sds_rings;
1189 num_sds = QLCNIC_MAX_SDS_RINGS;
1191 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1192 rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1193 cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1195 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1196 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1198 /* set mailbox hdr and capabilities */
1199 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1200 QLCNIC_CMD_CREATE_RX_CTX);
1204 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1205 cmd.req.arg[0] |= (0x3 << 29);
1207 cmd.req.arg[1] = cap;
1208 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1209 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1211 if (qlcnic_sriov_pf_check(adapter))
1212 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1214 /* set up status rings, mbx 8-57/87 */
1215 index = QLC_83XX_HOST_SDS_MBX_IDX;
1216 for (i = 0; i < num_sds; i++) {
1217 memset(&sds_mbx, 0, sds_mbx_size);
1218 sds = &recv_ctx->sds_rings[i];
1220 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1221 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1222 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1223 sds_mbx.sds_ring_size = sds->num_desc;
1224 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1225 intrpt_id = ahw->intr_tbl[i].id;
1227 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1228 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1229 sds_mbx.intrpt_id = intrpt_id;
1231 sds_mbx.intrpt_id = 0xffff;
1232 sds_mbx.intrpt_val = 0;
1233 buf = &cmd.req.arg[index];
1234 memcpy(buf, &sds_mbx, sds_mbx_size);
1235 index += sds_mbx_size / sizeof(u32);
1237 /* set up receive rings, mbx 88-111/135 */
1238 index = QLCNIC_HOST_RDS_MBX_IDX;
1239 rds = &recv_ctx->rds_rings[0];
1241 memset(&rds_mbx, 0, rds_mbx_size);
1242 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1243 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1244 rds_mbx.reg_ring_sz = rds->dma_size;
1245 rds_mbx.reg_ring_len = rds->num_desc;
1247 rds = &recv_ctx->rds_rings[1];
1249 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1250 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1251 rds_mbx.jmb_ring_sz = rds->dma_size;
1252 rds_mbx.jmb_ring_len = rds->num_desc;
1253 buf = &cmd.req.arg[index];
1254 memcpy(buf, &rds_mbx, rds_mbx_size);
1256 /* send the mailbox command */
1257 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1259 dev_err(&adapter->pdev->dev,
1260 "Failed to create Rx ctx in firmware%d\n", err);
1263 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1264 recv_ctx->context_id = mbx_out->ctx_id;
1265 recv_ctx->state = mbx_out->state;
1266 recv_ctx->virt_port = mbx_out->vport_id;
1267 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1268 recv_ctx->context_id, recv_ctx->state);
1269 /* Receive descriptor ring */
1271 rds = &recv_ctx->rds_rings[0];
1272 rds->crb_rcv_producer = ahw->pci_base0 +
1273 mbx_out->host_prod[0].reg_buf;
1275 rds = &recv_ctx->rds_rings[1];
1276 rds->crb_rcv_producer = ahw->pci_base0 +
1277 mbx_out->host_prod[0].jmb_buf;
1278 /* status descriptor ring */
1279 for (i = 0; i < num_sds; i++) {
1280 sds = &recv_ctx->sds_rings[i];
1281 sds->crb_sts_consumer = ahw->pci_base0 +
1282 mbx_out->host_csmr[i];
1283 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1284 intr_mask = ahw->intr_tbl[i].src;
1286 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1287 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1290 if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS)
1291 err = qlcnic_83xx_add_rings(adapter);
1293 qlcnic_free_mbx_args(&cmd);
1297 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1298 struct qlcnic_host_tx_ring *tx_ring)
1300 struct qlcnic_cmd_args cmd;
1303 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1306 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1307 cmd.req.arg[0] |= (0x3 << 29);
1309 if (qlcnic_sriov_pf_check(adapter))
1310 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1312 cmd.req.arg[1] = tx_ring->ctx_id | temp;
1313 if (qlcnic_issue_cmd(adapter, &cmd))
1314 dev_err(&adapter->pdev->dev,
1315 "Failed to destroy tx ctx in firmware\n");
1316 qlcnic_free_mbx_args(&cmd);
1319 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1320 struct qlcnic_host_tx_ring *tx, int ring)
1324 u32 *buf, intr_mask, temp = 0;
1325 struct qlcnic_cmd_args cmd;
1326 struct qlcnic_tx_mbx mbx;
1327 struct qlcnic_tx_mbx_out *mbx_out;
1328 struct qlcnic_hardware_context *ahw = adapter->ahw;
1331 /* Reset host resources */
1333 tx->sw_consumer = 0;
1334 *(tx->hw_consumer) = 0;
1336 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1338 /* setup mailbox inbox registerss */
1339 mbx.phys_addr_low = LSD(tx->phys_addr);
1340 mbx.phys_addr_high = MSD(tx->phys_addr);
1341 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1342 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1343 mbx.size = tx->num_desc;
1344 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1345 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1346 msix_vector = adapter->drv_sds_rings + ring;
1348 msix_vector = adapter->drv_sds_rings - 1;
1349 msix_id = ahw->intr_tbl[msix_vector].id;
1351 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1354 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1355 mbx.intr_id = msix_id;
1357 mbx.intr_id = 0xffff;
1360 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1364 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1365 cmd.req.arg[0] |= (0x3 << 29);
1367 if (qlcnic_sriov_pf_check(adapter))
1368 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1370 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1371 cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp;
1373 buf = &cmd.req.arg[6];
1374 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1375 /* send the mailbox command*/
1376 err = qlcnic_issue_cmd(adapter, &cmd);
1378 netdev_err(adapter->netdev,
1379 "Failed to create Tx ctx in firmware 0x%x\n", err);
1382 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1383 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1384 tx->ctx_id = mbx_out->ctx_id;
1385 if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1386 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1387 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src;
1388 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1390 netdev_info(adapter->netdev,
1391 "Tx Context[0x%x] Created, state:0x%x\n",
1392 tx->ctx_id, mbx_out->state);
1394 qlcnic_free_mbx_args(&cmd);
1398 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1401 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1402 struct qlcnic_host_sds_ring *sds_ring;
1403 struct qlcnic_host_rds_ring *rds_ring;
1404 u16 adapter_state = adapter->is_up;
1408 netif_device_detach(netdev);
1410 if (netif_running(netdev))
1411 __qlcnic_down(adapter, netdev);
1413 qlcnic_detach(adapter);
1415 adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
1416 adapter->ahw->diag_test = test;
1417 adapter->ahw->linkup = 0;
1419 ret = qlcnic_attach(adapter);
1421 netif_device_attach(netdev);
1425 ret = qlcnic_fw_create_ctx(adapter);
1427 qlcnic_detach(adapter);
1428 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1429 adapter->drv_sds_rings = num_sds_ring;
1430 qlcnic_attach(adapter);
1432 netif_device_attach(netdev);
1436 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1437 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1438 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1441 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1442 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1443 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1444 qlcnic_enable_sds_intr(adapter, sds_ring);
1448 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1449 adapter->ahw->loopback_state = 0;
1450 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1453 set_bit(__QLCNIC_DEV_UP, &adapter->state);
1457 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1460 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1461 struct qlcnic_host_sds_ring *sds_ring;
1464 clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1465 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1466 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1467 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1468 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1469 qlcnic_disable_sds_intr(adapter, sds_ring);
1473 qlcnic_fw_destroy_ctx(adapter);
1474 qlcnic_detach(adapter);
1476 adapter->ahw->diag_test = 0;
1477 adapter->drv_sds_rings = drv_sds_rings;
1479 if (qlcnic_attach(adapter))
1482 if (netif_running(netdev))
1483 __qlcnic_up(adapter, netdev);
1486 netif_device_attach(netdev);
1489 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *adapter)
1491 struct qlcnic_hardware_context *ahw = adapter->ahw;
1492 struct qlcnic_cmd_args cmd;
1496 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LED_CONFIG);
1498 err = qlcnic_issue_cmd(adapter, &cmd);
1500 beacon_state = cmd.rsp.arg[4];
1501 if (beacon_state == QLCNIC_BEACON_DISABLE)
1502 ahw->beacon_state = QLC_83XX_BEACON_OFF;
1503 else if (beacon_state == QLC_83XX_ENABLE_BEACON)
1504 ahw->beacon_state = QLC_83XX_BEACON_ON;
1507 netdev_err(adapter->netdev, "Get beacon state failed, err=%d\n",
1511 qlcnic_free_mbx_args(&cmd);
1516 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1519 struct qlcnic_cmd_args cmd;
1524 /* Get LED configuration */
1525 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1526 QLCNIC_CMD_GET_LED_CONFIG);
1530 status = qlcnic_issue_cmd(adapter, &cmd);
1532 dev_err(&adapter->pdev->dev,
1533 "Get led config failed.\n");
1536 for (i = 0; i < 4; i++)
1537 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1539 qlcnic_free_mbx_args(&cmd);
1540 /* Set LED Configuration */
1541 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1542 LSW(QLC_83XX_LED_CONFIG);
1543 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1544 QLCNIC_CMD_SET_LED_CONFIG);
1548 cmd.req.arg[1] = mbx_in;
1549 cmd.req.arg[2] = mbx_in;
1550 cmd.req.arg[3] = mbx_in;
1552 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1553 status = qlcnic_issue_cmd(adapter, &cmd);
1555 dev_err(&adapter->pdev->dev,
1556 "Set led config failed.\n");
1559 qlcnic_free_mbx_args(&cmd);
1563 /* Restoring default LED configuration */
1564 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1565 QLCNIC_CMD_SET_LED_CONFIG);
1569 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1570 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1571 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1573 cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1574 status = qlcnic_issue_cmd(adapter, &cmd);
1576 dev_err(&adapter->pdev->dev,
1577 "Restoring led config failed.\n");
1578 qlcnic_free_mbx_args(&cmd);
1583 int qlcnic_83xx_set_led(struct net_device *netdev,
1584 enum ethtool_phys_id_state state)
1586 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1587 int err = -EIO, active = 1;
1589 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1591 "LED test is not supported in non-privileged mode\n");
1596 case ETHTOOL_ID_ACTIVE:
1597 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1600 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1603 err = qlcnic_83xx_config_led(adapter, active, 0);
1605 netdev_err(netdev, "Failed to set LED blink state\n");
1607 case ETHTOOL_ID_INACTIVE:
1610 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1613 err = qlcnic_83xx_config_led(adapter, active, 0);
1615 netdev_err(netdev, "Failed to reset LED blink state\n");
1623 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1628 void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *adapter, int enable)
1630 struct qlcnic_cmd_args cmd;
1633 if (qlcnic_sriov_vf_check(adapter))
1637 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1638 QLCNIC_CMD_INIT_NIC_FUNC);
1640 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1641 QLCNIC_CMD_STOP_NIC_FUNC);
1646 cmd.req.arg[1] = QLC_REGISTER_LB_IDC | QLC_INIT_FW_RESOURCES;
1649 cmd.req.arg[1] |= QLC_REGISTER_DCB_AEN;
1651 status = qlcnic_issue_cmd(adapter, &cmd);
1653 dev_err(&adapter->pdev->dev,
1654 "Failed to %s in NIC IDC function event.\n",
1655 (enable ? "register" : "unregister"));
1657 qlcnic_free_mbx_args(&cmd);
1660 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1662 struct qlcnic_cmd_args cmd;
1665 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1669 cmd.req.arg[1] = adapter->ahw->port_config;
1670 err = qlcnic_issue_cmd(adapter, &cmd);
1672 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1673 qlcnic_free_mbx_args(&cmd);
1677 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1679 struct qlcnic_cmd_args cmd;
1682 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1686 err = qlcnic_issue_cmd(adapter, &cmd);
1688 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1690 adapter->ahw->port_config = cmd.rsp.arg[1];
1691 qlcnic_free_mbx_args(&cmd);
1695 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1699 struct qlcnic_cmd_args cmd;
1701 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1705 temp = adapter->recv_ctx->context_id << 16;
1706 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1707 err = qlcnic_issue_cmd(adapter, &cmd);
1709 dev_info(&adapter->pdev->dev,
1710 "Setup linkevent mailbox failed\n");
1711 qlcnic_free_mbx_args(&cmd);
1715 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1718 if (qlcnic_sriov_pf_check(adapter)) {
1719 qlcnic_alloc_lb_filters_mem(adapter);
1720 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1721 adapter->rx_mac_learn = true;
1723 if (!qlcnic_sriov_vf_check(adapter))
1724 *interface_id = adapter->recv_ctx->context_id << 16;
1728 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1730 struct qlcnic_cmd_args *cmd = NULL;
1734 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1737 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1741 err = qlcnic_alloc_mbx_args(cmd, adapter,
1742 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1746 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1747 qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1749 if (qlcnic_84xx_check(adapter) && qlcnic_sriov_pf_check(adapter))
1750 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1752 cmd->req.arg[1] = mode | temp;
1753 err = qlcnic_issue_cmd(adapter, cmd);
1757 qlcnic_free_mbx_args(cmd);
1764 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1766 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1767 struct qlcnic_hardware_context *ahw = adapter->ahw;
1768 u8 drv_sds_rings = adapter->drv_sds_rings;
1769 u8 drv_tx_rings = adapter->drv_tx_rings;
1770 int ret = 0, loop = 0;
1772 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1774 "Loopback test not supported in non privileged mode\n");
1778 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1779 netdev_info(netdev, "Device is resetting\n");
1783 if (qlcnic_get_diag_lock(adapter)) {
1784 netdev_info(netdev, "Device is in diagnostics mode\n");
1788 netdev_info(netdev, "%s loopback test in progress\n",
1789 mode == QLCNIC_ILB_MODE ? "internal" : "external");
1791 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1794 goto fail_diag_alloc;
1796 ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1800 /* Poll for link up event before running traffic */
1802 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1804 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1806 "Device is resetting, free LB test resources\n");
1810 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1812 "Firmware didn't sent link up event to loopback request\n");
1814 qlcnic_83xx_clear_lb_mode(adapter, mode);
1817 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1819 ret = qlcnic_do_lb_test(adapter, mode);
1821 qlcnic_83xx_clear_lb_mode(adapter, mode);
1824 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
1827 adapter->drv_sds_rings = drv_sds_rings;
1828 adapter->drv_tx_rings = drv_tx_rings;
1829 qlcnic_release_diag_lock(adapter);
1833 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1834 u32 *max_wait_count)
1836 struct qlcnic_hardware_context *ahw = adapter->ahw;
1839 netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n",
1840 ahw->extend_lb_time);
1841 temp = ahw->extend_lb_time * 1000;
1842 *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1843 ahw->extend_lb_time = 0;
1846 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1848 struct qlcnic_hardware_context *ahw = adapter->ahw;
1849 struct net_device *netdev = adapter->netdev;
1850 u32 config, max_wait_count;
1851 int status = 0, loop = 0;
1853 ahw->extend_lb_time = 0;
1854 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1855 status = qlcnic_83xx_get_port_config(adapter);
1859 config = ahw->port_config;
1861 /* Check if port is already in loopback mode */
1862 if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1863 (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1865 "Port already in Loopback mode.\n");
1866 return -EINPROGRESS;
1869 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1871 if (mode == QLCNIC_ILB_MODE)
1872 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1873 if (mode == QLCNIC_ELB_MODE)
1874 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1876 status = qlcnic_83xx_set_port_config(adapter);
1879 "Failed to Set Loopback Mode = 0x%x.\n",
1881 ahw->port_config = config;
1882 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1886 /* Wait for Link and IDC Completion AEN */
1888 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1890 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1892 "Device is resetting, free LB test resources\n");
1893 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1897 if (ahw->extend_lb_time)
1898 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1901 if (loop++ > max_wait_count) {
1902 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1904 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1905 qlcnic_83xx_clear_lb_mode(adapter, mode);
1908 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1910 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1915 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1917 struct qlcnic_hardware_context *ahw = adapter->ahw;
1918 u32 config = ahw->port_config, max_wait_count;
1919 struct net_device *netdev = adapter->netdev;
1920 int status = 0, loop = 0;
1922 ahw->extend_lb_time = 0;
1923 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1924 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1925 if (mode == QLCNIC_ILB_MODE)
1926 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1927 if (mode == QLCNIC_ELB_MODE)
1928 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1930 status = qlcnic_83xx_set_port_config(adapter);
1933 "Failed to Clear Loopback Mode = 0x%x.\n",
1935 ahw->port_config = config;
1936 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1940 /* Wait for Link and IDC Completion AEN */
1942 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1944 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1946 "Device is resetting, free LB test resources\n");
1947 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1951 if (ahw->extend_lb_time)
1952 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1955 if (loop++ > max_wait_count) {
1956 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1958 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1961 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1963 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1968 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1971 if (qlcnic_sriov_pf_check(adapter)) {
1972 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1974 if (!qlcnic_sriov_vf_check(adapter))
1975 *interface_id = adapter->recv_ctx->context_id << 16;
1979 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1983 u32 temp = 0, temp_ip;
1984 struct qlcnic_cmd_args cmd;
1986 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1987 QLCNIC_CMD_CONFIGURE_IP_ADDR);
1991 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1993 if (mode == QLCNIC_IP_UP)
1994 cmd.req.arg[1] = 1 | temp;
1996 cmd.req.arg[1] = 2 | temp;
1999 * Adapter needs IP address in network byte order.
2000 * But hardware mailbox registers go through writel(), hence IP address
2001 * gets swapped on big endian architecture.
2002 * To negate swapping of writel() on big endian architecture
2003 * use swab32(value).
2006 temp_ip = swab32(ntohl(ip));
2007 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
2008 err = qlcnic_issue_cmd(adapter, &cmd);
2009 if (err != QLCNIC_RCODE_SUCCESS)
2010 dev_err(&adapter->netdev->dev,
2011 "could not notify %s IP 0x%x request\n",
2012 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
2014 qlcnic_free_mbx_args(&cmd);
2017 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
2021 struct qlcnic_cmd_args cmd;
2024 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
2026 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2029 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
2033 temp = adapter->recv_ctx->context_id << 16;
2034 arg1 = lro_bit_mask | temp;
2035 cmd.req.arg[1] = arg1;
2037 err = qlcnic_issue_cmd(adapter, &cmd);
2039 dev_info(&adapter->pdev->dev, "LRO config failed\n");
2040 qlcnic_free_mbx_args(&cmd);
2045 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
2049 struct qlcnic_cmd_args cmd;
2050 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
2051 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
2052 0x255b0ec26d5a56daULL };
2054 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
2060 * 5-4: hash_type_ipv4
2061 * 7-6: hash_type_ipv6
2063 * 9: use indirection table
2064 * 16-31: indirection table mask
2066 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
2067 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
2068 ((u32)(enable & 0x1) << 8) |
2070 cmd.req.arg[1] = (adapter->recv_ctx->context_id);
2071 cmd.req.arg[2] = word;
2072 memcpy(&cmd.req.arg[4], key, sizeof(key));
2074 err = qlcnic_issue_cmd(adapter, &cmd);
2077 dev_info(&adapter->pdev->dev, "RSS config failed\n");
2078 qlcnic_free_mbx_args(&cmd);
2084 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
2087 if (qlcnic_sriov_pf_check(adapter)) {
2088 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
2090 if (!qlcnic_sriov_vf_check(adapter))
2091 *interface_id = adapter->recv_ctx->context_id << 16;
2095 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
2098 struct qlcnic_cmd_args *cmd = NULL;
2099 struct qlcnic_macvlan_mbx mv;
2103 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2106 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
2110 err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
2114 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
2117 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
2118 QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
2120 cmd->req.arg[1] = op | (1 << 8);
2121 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
2122 cmd->req.arg[1] |= temp;
2124 mv.mac_addr0 = addr[0];
2125 mv.mac_addr1 = addr[1];
2126 mv.mac_addr2 = addr[2];
2127 mv.mac_addr3 = addr[3];
2128 mv.mac_addr4 = addr[4];
2129 mv.mac_addr5 = addr[5];
2130 buf = &cmd->req.arg[2];
2131 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
2132 err = qlcnic_issue_cmd(adapter, cmd);
2136 qlcnic_free_mbx_args(cmd);
2142 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
2144 struct qlcnic_host_tx_ring *tx_ring)
2147 memcpy(&mac, addr, ETH_ALEN);
2148 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2151 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2152 u8 type, struct qlcnic_cmd_args *cmd)
2155 case QLCNIC_SET_STATION_MAC:
2156 case QLCNIC_SET_FAC_DEF_MAC:
2157 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2158 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2161 cmd->req.arg[1] = type;
2164 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2168 struct qlcnic_cmd_args cmd;
2169 u32 mac_low, mac_high;
2171 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2175 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2176 err = qlcnic_issue_cmd(adapter, &cmd);
2178 if (err == QLCNIC_RCODE_SUCCESS) {
2179 mac_low = cmd.rsp.arg[1];
2180 mac_high = cmd.rsp.arg[2];
2182 for (i = 0; i < 2; i++)
2183 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2184 for (i = 2; i < 6; i++)
2185 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2187 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2191 qlcnic_free_mbx_args(&cmd);
2195 static int qlcnic_83xx_set_rx_intr_coal(struct qlcnic_adapter *adapter)
2197 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2198 struct qlcnic_cmd_args cmd;
2202 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2206 temp = adapter->recv_ctx->context_id;
2207 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2208 temp = coal->rx_time_us;
2209 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2210 cmd.req.arg[3] = coal->flag;
2212 err = qlcnic_issue_cmd(adapter, &cmd);
2213 if (err != QLCNIC_RCODE_SUCCESS)
2214 netdev_err(adapter->netdev,
2215 "failed to set interrupt coalescing parameters\n");
2217 qlcnic_free_mbx_args(&cmd);
2222 static int qlcnic_83xx_set_tx_intr_coal(struct qlcnic_adapter *adapter)
2224 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2225 struct qlcnic_cmd_args cmd;
2229 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2233 temp = adapter->tx_ring->ctx_id;
2234 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2235 temp = coal->tx_time_us;
2236 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2237 cmd.req.arg[3] = coal->flag;
2239 err = qlcnic_issue_cmd(adapter, &cmd);
2240 if (err != QLCNIC_RCODE_SUCCESS)
2241 netdev_err(adapter->netdev,
2242 "failed to set interrupt coalescing parameters\n");
2244 qlcnic_free_mbx_args(&cmd);
2249 int qlcnic_83xx_set_rx_tx_intr_coal(struct qlcnic_adapter *adapter)
2253 err = qlcnic_83xx_set_rx_intr_coal(adapter);
2255 netdev_err(adapter->netdev,
2256 "failed to set Rx coalescing parameters\n");
2258 err = qlcnic_83xx_set_tx_intr_coal(adapter);
2260 netdev_err(adapter->netdev,
2261 "failed to set Tx coalescing parameters\n");
2266 int qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter,
2267 struct ethtool_coalesce *ethcoal)
2269 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2270 u32 rx_coalesce_usecs, rx_max_frames;
2271 u32 tx_coalesce_usecs, tx_max_frames;
2274 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2277 tx_coalesce_usecs = ethcoal->tx_coalesce_usecs;
2278 tx_max_frames = ethcoal->tx_max_coalesced_frames;
2279 rx_coalesce_usecs = ethcoal->rx_coalesce_usecs;
2280 rx_max_frames = ethcoal->rx_max_coalesced_frames;
2281 coal->flag = QLCNIC_INTR_DEFAULT;
2283 if ((coal->rx_time_us == rx_coalesce_usecs) &&
2284 (coal->rx_packets == rx_max_frames)) {
2285 coal->type = QLCNIC_INTR_COAL_TYPE_TX;
2286 coal->tx_time_us = tx_coalesce_usecs;
2287 coal->tx_packets = tx_max_frames;
2288 } else if ((coal->tx_time_us == tx_coalesce_usecs) &&
2289 (coal->tx_packets == tx_max_frames)) {
2290 coal->type = QLCNIC_INTR_COAL_TYPE_RX;
2291 coal->rx_time_us = rx_coalesce_usecs;
2292 coal->rx_packets = rx_max_frames;
2294 coal->type = QLCNIC_INTR_COAL_TYPE_RX_TX;
2295 coal->rx_time_us = rx_coalesce_usecs;
2296 coal->rx_packets = rx_max_frames;
2297 coal->tx_time_us = tx_coalesce_usecs;
2298 coal->tx_packets = tx_max_frames;
2301 switch (coal->type) {
2302 case QLCNIC_INTR_COAL_TYPE_RX:
2303 err = qlcnic_83xx_set_rx_intr_coal(adapter);
2305 case QLCNIC_INTR_COAL_TYPE_TX:
2306 err = qlcnic_83xx_set_tx_intr_coal(adapter);
2308 case QLCNIC_INTR_COAL_TYPE_RX_TX:
2309 err = qlcnic_83xx_set_rx_tx_intr_coal(adapter);
2313 netdev_err(adapter->netdev,
2314 "Invalid Interrupt coalescing type\n");
2321 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2324 struct qlcnic_hardware_context *ahw = adapter->ahw;
2325 u8 link_status, duplex;
2327 link_status = LSB(data[3]) & 1;
2329 ahw->link_speed = MSW(data[2]);
2330 duplex = LSB(MSW(data[3]));
2332 ahw->link_duplex = DUPLEX_FULL;
2334 ahw->link_duplex = DUPLEX_HALF;
2336 ahw->link_speed = SPEED_UNKNOWN;
2337 ahw->link_duplex = DUPLEX_UNKNOWN;
2340 ahw->link_autoneg = MSB(MSW(data[3]));
2341 ahw->module_type = MSB(LSW(data[3]));
2342 ahw->has_link_events = 1;
2343 ahw->lb_mode = data[4] & QLCNIC_LB_MODE_MASK;
2344 qlcnic_advert_link_change(adapter, link_status);
2347 static irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2349 u32 mask, resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
2350 struct qlcnic_adapter *adapter = data;
2351 struct qlcnic_mailbox *mbx;
2352 unsigned long flags;
2354 mbx = adapter->ahw->mailbox;
2355 spin_lock_irqsave(&mbx->aen_lock, flags);
2356 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2357 if (!(resp & QLCNIC_SET_OWNER))
2360 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2361 if (event & QLCNIC_MBX_ASYNC_EVENT) {
2362 __qlcnic_83xx_process_aen(adapter);
2364 if (mbx->rsp_status != rsp_status)
2365 qlcnic_83xx_notify_mbx_response(mbx);
2367 adapter->stats.mbx_spurious_intr++;
2371 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2372 writel(0, adapter->ahw->pci_base0 + mask);
2373 spin_unlock_irqrestore(&mbx->aen_lock, flags);
2377 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2378 struct qlcnic_info *nic)
2381 struct qlcnic_cmd_args cmd;
2383 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2384 dev_err(&adapter->pdev->dev,
2385 "%s: Error, invoked by non management func\n",
2390 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2394 cmd.req.arg[1] = (nic->pci_func << 16);
2395 cmd.req.arg[2] = 0x1 << 16;
2396 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2397 cmd.req.arg[4] = nic->capabilities;
2398 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2399 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2400 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2401 for (i = 8; i < 32; i++)
2404 err = qlcnic_issue_cmd(adapter, &cmd);
2406 if (err != QLCNIC_RCODE_SUCCESS) {
2407 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2412 qlcnic_free_mbx_args(&cmd);
2417 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2418 struct qlcnic_info *npar_info, u8 func_id)
2423 struct qlcnic_cmd_args cmd;
2424 struct qlcnic_hardware_context *ahw = adapter->ahw;
2426 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2430 if (func_id != ahw->pci_func) {
2431 temp = func_id << 16;
2432 cmd.req.arg[1] = op | BIT_31 | temp;
2434 cmd.req.arg[1] = ahw->pci_func << 16;
2436 err = qlcnic_issue_cmd(adapter, &cmd);
2438 dev_info(&adapter->pdev->dev,
2439 "Failed to get nic info %d\n", err);
2443 npar_info->op_type = cmd.rsp.arg[1];
2444 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2445 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2446 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2447 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2448 npar_info->capabilities = cmd.rsp.arg[4];
2449 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2450 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2451 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2452 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2453 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2454 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2455 if (cmd.rsp.arg[8] & 0x1)
2456 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2457 if (cmd.rsp.arg[8] & 0x10000) {
2458 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2459 npar_info->max_linkspeed_reg_offset = temp;
2462 memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2463 sizeof(ahw->extra_capability));
2466 qlcnic_free_mbx_args(&cmd);
2470 int qlcnic_get_pci_func_type(struct qlcnic_adapter *adapter, u16 type,
2471 u16 *nic, u16 *fcoe, u16 *iscsi)
2473 struct device *dev = &adapter->pdev->dev;
2477 case QLCNIC_TYPE_NIC:
2480 case QLCNIC_TYPE_FCOE:
2483 case QLCNIC_TYPE_ISCSI:
2487 dev_err(dev, "%s: Unknown PCI type[%x]\n",
2495 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2496 struct qlcnic_pci_info *pci_info)
2498 struct qlcnic_hardware_context *ahw = adapter->ahw;
2499 struct device *dev = &adapter->pdev->dev;
2500 u16 nic = 0, fcoe = 0, iscsi = 0;
2501 struct qlcnic_cmd_args cmd;
2502 int i, err = 0, j = 0;
2505 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2509 err = qlcnic_issue_cmd(adapter, &cmd);
2511 ahw->total_nic_func = 0;
2512 if (err == QLCNIC_RCODE_SUCCESS) {
2513 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2514 for (i = 2, j = 0; j < ahw->max_vnic_func; j++, pci_info++) {
2515 pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2516 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2518 if (!pci_info->active) {
2519 i += QLC_SKIP_INACTIVE_PCI_REGS;
2522 pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2523 err = qlcnic_get_pci_func_type(adapter, pci_info->type,
2524 &nic, &fcoe, &iscsi);
2525 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2526 pci_info->default_port = temp;
2528 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2529 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2530 pci_info->tx_max_bw = temp;
2532 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2534 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2538 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2542 ahw->total_nic_func = nic;
2543 ahw->total_pci_func = nic + fcoe + iscsi;
2544 if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) {
2545 dev_err(dev, "%s: Invalid function count: total nic func[%x], total pci func[%x]\n",
2546 __func__, ahw->total_nic_func, ahw->total_pci_func);
2549 qlcnic_free_mbx_args(&cmd);
2554 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2558 u32 val, temp, type;
2559 struct qlcnic_cmd_args cmd;
2561 max_ints = adapter->ahw->num_msix - 1;
2562 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2566 cmd.req.arg[1] = max_ints;
2568 if (qlcnic_sriov_vf_check(adapter))
2569 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2571 for (i = 0, index = 2; i < max_ints; i++) {
2572 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2573 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2574 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2575 val |= (adapter->ahw->intr_tbl[i].id << 16);
2576 cmd.req.arg[index++] = val;
2578 err = qlcnic_issue_cmd(adapter, &cmd);
2580 dev_err(&adapter->pdev->dev,
2581 "Failed to configure interrupts 0x%x\n", err);
2585 max_ints = cmd.rsp.arg[1];
2586 for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2587 val = cmd.rsp.arg[index];
2589 dev_info(&adapter->pdev->dev,
2590 "Can't configure interrupt %d\n",
2591 adapter->ahw->intr_tbl[i].id);
2595 adapter->ahw->intr_tbl[i].id = MSW(val);
2596 adapter->ahw->intr_tbl[i].enabled = 1;
2597 temp = cmd.rsp.arg[index + 1];
2598 adapter->ahw->intr_tbl[i].src = temp;
2600 adapter->ahw->intr_tbl[i].id = i;
2601 adapter->ahw->intr_tbl[i].enabled = 0;
2602 adapter->ahw->intr_tbl[i].src = 0;
2606 qlcnic_free_mbx_args(&cmd);
2610 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2612 int id, timeout = 0;
2615 while (status == 0) {
2616 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2620 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2621 id = QLC_SHARED_REG_RD32(adapter,
2622 QLCNIC_FLASH_LOCK_OWNER);
2623 dev_err(&adapter->pdev->dev,
2624 "%s: failed, lock held by %d\n", __func__, id);
2627 usleep_range(1000, 2000);
2630 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2634 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2636 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2637 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2640 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2641 u32 flash_addr, u8 *p_data,
2644 u32 word, range, flash_offset, addr = flash_addr, ret;
2645 ulong indirect_add, direct_window;
2648 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2650 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2654 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2655 (addr & 0xFFFF0000));
2657 range = flash_offset + (count * sizeof(u32));
2658 /* Check if data is spread across multiple sectors */
2659 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2661 /* Multi sector read */
2662 for (i = 0; i < count; i++) {
2663 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2664 ret = QLCRD32(adapter, indirect_add, &err);
2669 *(u32 *)p_data = word;
2670 p_data = p_data + 4;
2672 flash_offset = flash_offset + 4;
2674 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2675 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2676 /* This write is needed once for each sector */
2677 qlcnic_83xx_wrt_reg_indirect(adapter,
2684 /* Single sector read */
2685 for (i = 0; i < count; i++) {
2686 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2687 ret = QLCRD32(adapter, indirect_add, &err);
2692 *(u32 *)p_data = word;
2693 p_data = p_data + 4;
2701 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2704 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2708 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2712 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2713 QLC_83XX_FLASH_STATUS_READY)
2716 usleep_range(1000, 1100);
2717 } while (--retries);
2725 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2729 cmd = adapter->ahw->fdt.write_statusreg_cmd;
2730 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2731 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2732 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2733 adapter->ahw->fdt.write_enable_bits);
2734 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2735 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2736 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2743 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2747 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2748 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2749 adapter->ahw->fdt.write_statusreg_cmd));
2750 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2751 adapter->ahw->fdt.write_disable_bits);
2752 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2753 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2754 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2761 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2766 if (qlcnic_83xx_lock_flash(adapter))
2769 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2770 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2771 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2772 QLC_83XX_FLASH_READ_CTRL);
2773 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2775 qlcnic_83xx_unlock_flash(adapter);
2779 mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2781 qlcnic_83xx_unlock_flash(adapter);
2785 adapter->flash_mfg_id = (mfg_id & 0xFF);
2786 qlcnic_83xx_unlock_flash(adapter);
2791 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2793 int count, fdt_size, ret = 0;
2795 fdt_size = sizeof(struct qlcnic_fdt);
2796 count = fdt_size / sizeof(u32);
2798 if (qlcnic_83xx_lock_flash(adapter))
2801 memset(&adapter->ahw->fdt, 0, fdt_size);
2802 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2803 (u8 *)&adapter->ahw->fdt,
2805 qlcnic_swap32_buffer((u32 *)&adapter->ahw->fdt, count);
2806 qlcnic_83xx_unlock_flash(adapter);
2810 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2811 u32 sector_start_addr)
2813 u32 reversed_addr, addr1, addr2, cmd;
2816 if (qlcnic_83xx_lock_flash(adapter) != 0)
2819 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2820 ret = qlcnic_83xx_enable_flash_write(adapter);
2822 qlcnic_83xx_unlock_flash(adapter);
2823 dev_err(&adapter->pdev->dev,
2824 "%s failed at %d\n",
2825 __func__, __LINE__);
2830 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2832 qlcnic_83xx_unlock_flash(adapter);
2833 dev_err(&adapter->pdev->dev,
2834 "%s: failed at %d\n", __func__, __LINE__);
2838 addr1 = (sector_start_addr & 0xFF) << 16;
2839 addr2 = (sector_start_addr & 0xFF0000) >> 16;
2840 reversed_addr = addr1 | addr2 | (sector_start_addr & 0xFF00);
2842 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2844 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2845 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2846 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2848 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2849 QLC_83XX_FLASH_OEM_ERASE_SIG);
2850 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2851 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2853 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2855 qlcnic_83xx_unlock_flash(adapter);
2856 dev_err(&adapter->pdev->dev,
2857 "%s: failed at %d\n", __func__, __LINE__);
2861 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2862 ret = qlcnic_83xx_disable_flash_write(adapter);
2864 qlcnic_83xx_unlock_flash(adapter);
2865 dev_err(&adapter->pdev->dev,
2866 "%s: failed at %d\n", __func__, __LINE__);
2871 qlcnic_83xx_unlock_flash(adapter);
2876 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2880 u32 addr1 = 0x00800000 | (addr >> 2);
2882 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2883 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2884 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2885 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2886 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2888 dev_err(&adapter->pdev->dev,
2889 "%s: failed at %d\n", __func__, __LINE__);
2896 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2897 u32 *p_data, int count)
2900 int ret = -EIO, err = 0;
2902 if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2903 (count > QLC_83XX_FLASH_WRITE_MAX)) {
2904 dev_err(&adapter->pdev->dev,
2905 "%s: Invalid word count\n", __func__);
2909 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2913 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2914 (temp | QLC_83XX_FLASH_SPI_CTRL));
2915 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2916 QLC_83XX_FLASH_ADDR_TEMP_VAL);
2918 /* First DWORD write */
2919 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2920 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2921 QLC_83XX_FLASH_FIRST_MS_PATTERN);
2922 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2924 dev_err(&adapter->pdev->dev,
2925 "%s: failed at %d\n", __func__, __LINE__);
2930 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2931 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2932 /* Second to N-1 DWORD writes */
2933 while (count != 1) {
2934 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2936 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2937 QLC_83XX_FLASH_SECOND_MS_PATTERN);
2938 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2940 dev_err(&adapter->pdev->dev,
2941 "%s: failed at %d\n", __func__, __LINE__);
2947 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2948 QLC_83XX_FLASH_ADDR_TEMP_VAL |
2950 /* Last DWORD write */
2951 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2952 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2953 QLC_83XX_FLASH_LAST_MS_PATTERN);
2954 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2956 dev_err(&adapter->pdev->dev,
2957 "%s: failed at %d\n", __func__, __LINE__);
2961 ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2965 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2966 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2967 __func__, __LINE__);
2968 /* Operation failed, clear error bit */
2969 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2973 qlcnic_83xx_wrt_reg_indirect(adapter,
2974 QLC_83XX_FLASH_SPI_CONTROL,
2975 (temp | QLC_83XX_FLASH_SPI_CTRL));
2981 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2985 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2987 /* Check if recovery need to be performed by the calling function */
2988 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2990 val = val | ((adapter->portnum << 2) |
2991 QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2992 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2993 dev_info(&adapter->pdev->dev,
2994 "%s: lock recovery initiated\n", __func__);
2995 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2996 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2997 id = ((val >> 2) & 0xF);
2998 if (id == adapter->portnum) {
2999 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
3000 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
3001 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
3002 /* Force release the lock */
3003 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
3004 /* Clear recovery bits */
3006 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
3007 dev_info(&adapter->pdev->dev,
3008 "%s: lock recovery completed\n", __func__);
3010 dev_info(&adapter->pdev->dev,
3011 "%s: func %d to resume lock recovery process\n",
3015 dev_info(&adapter->pdev->dev,
3016 "%s: lock recovery initiated by other functions\n",
3021 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
3023 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
3024 int max_attempt = 0;
3026 while (status == 0) {
3027 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
3031 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
3035 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3037 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
3038 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3041 dev_info(&adapter->pdev->dev,
3042 "%s: lock to be recovered from %d\n",
3044 qlcnic_83xx_recover_driver_lock(adapter);
3048 dev_err(&adapter->pdev->dev,
3049 "%s: failed to get lock\n", __func__);
3054 /* Force exit from while loop after few attempts */
3055 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
3056 dev_err(&adapter->pdev->dev,
3057 "%s: failed to get lock\n", __func__);
3062 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3063 lock_alive_counter = val >> 8;
3064 lock_alive_counter++;
3065 val = lock_alive_counter << 8 | adapter->portnum;
3066 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
3071 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
3073 u32 val, lock_alive_counter, id;
3075 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3077 lock_alive_counter = val >> 8;
3079 if (id != adapter->portnum)
3080 dev_err(&adapter->pdev->dev,
3081 "%s:Warning func %d is unlocking lock owned by %d\n",
3082 __func__, adapter->portnum, id);
3084 val = (lock_alive_counter << 8) | 0xFF;
3085 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
3086 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
3089 int qlcnic_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
3090 u32 *data, u32 count)
3095 /* Check alignment */
3099 mutex_lock(&adapter->ahw->mem_lock);
3100 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_HI, 0);
3102 for (i = 0; i < count; i++, addr += 16) {
3103 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
3104 QLCNIC_ADDR_QDR_NET_MAX)) ||
3105 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
3106 QLCNIC_ADDR_DDR_NET_MAX)))) {
3107 mutex_unlock(&adapter->ahw->mem_lock);
3111 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_LO, addr);
3112 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_LO, *data++);
3113 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_HI, *data++);
3114 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_ULO, *data++);
3115 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_UHI, *data++);
3116 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_WRITE_ENABLE);
3117 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_WRITE_START);
3119 for (j = 0; j < MAX_CTL_CHECK; j++) {
3120 temp = qlcnic_ind_rd(adapter, QLCNIC_MS_CTRL);
3122 if ((temp & TA_CTL_BUSY) == 0)
3126 /* Status check failure */
3127 if (j >= MAX_CTL_CHECK) {
3128 printk_ratelimited(KERN_WARNING
3129 "MS memory write failed\n");
3130 mutex_unlock(&adapter->ahw->mem_lock);
3135 mutex_unlock(&adapter->ahw->mem_lock);
3140 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
3141 u8 *p_data, int count)
3143 u32 word, addr = flash_addr, ret;
3144 ulong indirect_addr;
3147 if (qlcnic_83xx_lock_flash(adapter) != 0)
3151 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
3152 qlcnic_83xx_unlock_flash(adapter);
3156 for (i = 0; i < count; i++) {
3157 if (qlcnic_83xx_wrt_reg_indirect(adapter,
3158 QLC_83XX_FLASH_DIRECT_WINDOW,
3160 qlcnic_83xx_unlock_flash(adapter);
3164 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
3165 ret = QLCRD32(adapter, indirect_addr, &err);
3167 qlcnic_83xx_unlock_flash(adapter);
3172 *(u32 *)p_data = word;
3173 p_data = p_data + 4;
3177 qlcnic_83xx_unlock_flash(adapter);
3182 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
3186 u32 config = 0, state;
3187 struct qlcnic_cmd_args cmd;
3188 struct qlcnic_hardware_context *ahw = adapter->ahw;
3190 if (qlcnic_sriov_vf_check(adapter))
3191 pci_func = adapter->portnum;
3193 pci_func = ahw->pci_func;
3195 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
3196 if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
3197 dev_info(&adapter->pdev->dev, "link state down\n");
3201 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3205 err = qlcnic_issue_cmd(adapter, &cmd);
3207 dev_info(&adapter->pdev->dev,
3208 "Get Link Status Command failed: 0x%x\n", err);
3211 config = cmd.rsp.arg[1];
3212 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
3213 case QLC_83XX_10M_LINK:
3214 ahw->link_speed = SPEED_10;
3216 case QLC_83XX_100M_LINK:
3217 ahw->link_speed = SPEED_100;
3219 case QLC_83XX_1G_LINK:
3220 ahw->link_speed = SPEED_1000;
3222 case QLC_83XX_10G_LINK:
3223 ahw->link_speed = SPEED_10000;
3226 ahw->link_speed = 0;
3229 config = cmd.rsp.arg[3];
3230 switch (QLC_83XX_SFP_MODULE_TYPE(config)) {
3231 case QLC_83XX_MODULE_FIBRE_10GBASE_LRM:
3232 case QLC_83XX_MODULE_FIBRE_10GBASE_LR:
3233 case QLC_83XX_MODULE_FIBRE_10GBASE_SR:
3234 ahw->supported_type = PORT_FIBRE;
3235 ahw->port_type = QLCNIC_XGBE;
3237 case QLC_83XX_MODULE_FIBRE_1000BASE_SX:
3238 case QLC_83XX_MODULE_FIBRE_1000BASE_LX:
3239 case QLC_83XX_MODULE_FIBRE_1000BASE_CX:
3240 ahw->supported_type = PORT_FIBRE;
3241 ahw->port_type = QLCNIC_GBE;
3243 case QLC_83XX_MODULE_TP_1000BASE_T:
3244 ahw->supported_type = PORT_TP;
3245 ahw->port_type = QLCNIC_GBE;
3247 case QLC_83XX_MODULE_DA_10GE_PASSIVE_CP:
3248 case QLC_83XX_MODULE_DA_10GE_ACTIVE_CP:
3249 case QLC_83XX_MODULE_DA_10GE_LEGACY_CP:
3250 case QLC_83XX_MODULE_DA_1GE_PASSIVE_CP:
3251 ahw->supported_type = PORT_DA;
3252 ahw->port_type = QLCNIC_XGBE;
3255 ahw->supported_type = PORT_OTHER;
3256 ahw->port_type = QLCNIC_XGBE;
3262 qlcnic_free_mbx_args(&cmd);
3266 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
3267 struct ethtool_cmd *ecmd)
3269 struct qlcnic_hardware_context *ahw = adapter->ahw;
3273 if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
3274 /* Get port configuration info */
3275 status = qlcnic_83xx_get_port_info(adapter);
3276 /* Get Link Status related info */
3277 config = qlcnic_83xx_test_link(adapter);
3278 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3281 /* hard code until there is a way to get it from flash */
3282 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3284 if (netif_running(adapter->netdev) && ahw->has_link_events) {
3285 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3286 ecmd->duplex = ahw->link_duplex;
3287 ecmd->autoneg = ahw->link_autoneg;
3289 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3290 ecmd->duplex = DUPLEX_UNKNOWN;
3291 ecmd->autoneg = AUTONEG_DISABLE;
3294 ecmd->supported = (SUPPORTED_10baseT_Full |
3295 SUPPORTED_100baseT_Full |
3296 SUPPORTED_1000baseT_Full |
3297 SUPPORTED_10000baseT_Full |
3300 if (ecmd->autoneg == AUTONEG_ENABLE) {
3301 if (ahw->port_config & QLC_83XX_10_CAPABLE)
3302 ecmd->advertising |= SUPPORTED_10baseT_Full;
3303 if (ahw->port_config & QLC_83XX_100_CAPABLE)
3304 ecmd->advertising |= SUPPORTED_100baseT_Full;
3305 if (ahw->port_config & QLC_83XX_1G_CAPABLE)
3306 ecmd->advertising |= SUPPORTED_1000baseT_Full;
3307 if (ahw->port_config & QLC_83XX_10G_CAPABLE)
3308 ecmd->advertising |= SUPPORTED_10000baseT_Full;
3309 if (ahw->port_config & QLC_83XX_AUTONEG_ENABLE)
3310 ecmd->advertising |= ADVERTISED_Autoneg;
3312 switch (ahw->link_speed) {
3314 ecmd->advertising = SUPPORTED_10baseT_Full;
3317 ecmd->advertising = SUPPORTED_100baseT_Full;
3320 ecmd->advertising = SUPPORTED_1000baseT_Full;
3323 ecmd->advertising = SUPPORTED_10000baseT_Full;
3331 switch (ahw->supported_type) {
3333 ecmd->supported |= SUPPORTED_FIBRE;
3334 ecmd->advertising |= ADVERTISED_FIBRE;
3335 ecmd->port = PORT_FIBRE;
3336 ecmd->transceiver = XCVR_EXTERNAL;
3339 ecmd->supported |= SUPPORTED_TP;
3340 ecmd->advertising |= ADVERTISED_TP;
3341 ecmd->port = PORT_TP;
3342 ecmd->transceiver = XCVR_INTERNAL;
3345 ecmd->supported |= SUPPORTED_FIBRE;
3346 ecmd->advertising |= ADVERTISED_FIBRE;
3347 ecmd->port = PORT_DA;
3348 ecmd->transceiver = XCVR_EXTERNAL;
3351 ecmd->supported |= SUPPORTED_FIBRE;
3352 ecmd->advertising |= ADVERTISED_FIBRE;
3353 ecmd->port = PORT_OTHER;
3354 ecmd->transceiver = XCVR_EXTERNAL;
3357 ecmd->phy_address = ahw->physical_port;
3361 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3362 struct ethtool_cmd *ecmd)
3364 struct qlcnic_hardware_context *ahw = adapter->ahw;
3365 u32 config = adapter->ahw->port_config;
3368 /* 83xx devices do not support Half duplex */
3369 if (ecmd->duplex == DUPLEX_HALF) {
3370 netdev_info(adapter->netdev,
3371 "Half duplex mode not supported\n");
3375 if (ecmd->autoneg) {
3376 ahw->port_config |= QLC_83XX_AUTONEG_ENABLE;
3377 ahw->port_config |= (QLC_83XX_100_CAPABLE |
3378 QLC_83XX_1G_CAPABLE |
3379 QLC_83XX_10G_CAPABLE);
3380 } else { /* force speed */
3381 ahw->port_config &= ~QLC_83XX_AUTONEG_ENABLE;
3382 switch (ethtool_cmd_speed(ecmd)) {
3384 ahw->port_config &= ~(QLC_83XX_100_CAPABLE |
3385 QLC_83XX_1G_CAPABLE |
3386 QLC_83XX_10G_CAPABLE);
3387 ahw->port_config |= QLC_83XX_10_CAPABLE;
3390 ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3391 QLC_83XX_1G_CAPABLE |
3392 QLC_83XX_10G_CAPABLE);
3393 ahw->port_config |= QLC_83XX_100_CAPABLE;
3396 ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3397 QLC_83XX_100_CAPABLE |
3398 QLC_83XX_10G_CAPABLE);
3399 ahw->port_config |= QLC_83XX_1G_CAPABLE;
3402 ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3403 QLC_83XX_100_CAPABLE |
3404 QLC_83XX_1G_CAPABLE);
3405 ahw->port_config |= QLC_83XX_10G_CAPABLE;
3411 status = qlcnic_83xx_set_port_config(adapter);
3413 netdev_info(adapter->netdev,
3414 "Failed to Set Link Speed and autoneg.\n");
3415 ahw->port_config = config;
3421 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3422 u64 *data, int index)
3427 low = cmd->rsp.arg[index];
3428 hi = cmd->rsp.arg[index + 1];
3429 val = (((u64) low) | (((u64) hi) << 32));
3434 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3435 struct qlcnic_cmd_args *cmd, u64 *data,
3438 int err, k, total_regs;
3441 err = qlcnic_issue_cmd(adapter, cmd);
3442 if (err != QLCNIC_RCODE_SUCCESS) {
3443 dev_info(&adapter->pdev->dev,
3444 "Error in get statistics mailbox command\n");
3448 total_regs = cmd->rsp.num;
3450 case QLC_83XX_STAT_MAC:
3451 /* fill in MAC tx counters */
3452 for (k = 2; k < 28; k += 2)
3453 data = qlcnic_83xx_copy_stats(cmd, data, k);
3454 /* skip 24 bytes of reserved area */
3455 /* fill in MAC rx counters */
3456 for (k += 6; k < 60; k += 2)
3457 data = qlcnic_83xx_copy_stats(cmd, data, k);
3458 /* skip 24 bytes of reserved area */
3459 /* fill in MAC rx frame stats */
3460 for (k += 6; k < 80; k += 2)
3461 data = qlcnic_83xx_copy_stats(cmd, data, k);
3462 /* fill in eSwitch stats */
3463 for (; k < total_regs; k += 2)
3464 data = qlcnic_83xx_copy_stats(cmd, data, k);
3466 case QLC_83XX_STAT_RX:
3467 for (k = 2; k < 8; k += 2)
3468 data = qlcnic_83xx_copy_stats(cmd, data, k);
3469 /* skip 8 bytes of reserved data */
3470 for (k += 2; k < 24; k += 2)
3471 data = qlcnic_83xx_copy_stats(cmd, data, k);
3472 /* skip 8 bytes containing RE1FBQ error data */
3473 for (k += 2; k < total_regs; k += 2)
3474 data = qlcnic_83xx_copy_stats(cmd, data, k);
3476 case QLC_83XX_STAT_TX:
3477 for (k = 2; k < 10; k += 2)
3478 data = qlcnic_83xx_copy_stats(cmd, data, k);
3479 /* skip 8 bytes of reserved data */
3480 for (k += 2; k < total_regs; k += 2)
3481 data = qlcnic_83xx_copy_stats(cmd, data, k);
3484 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3490 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3492 struct qlcnic_cmd_args cmd;
3493 struct net_device *netdev = adapter->netdev;
3496 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3500 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3501 cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3502 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3503 QLC_83XX_STAT_TX, &ret);
3505 netdev_err(netdev, "Error getting Tx stats\n");
3509 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3510 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3511 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3512 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3513 QLC_83XX_STAT_MAC, &ret);
3515 netdev_err(netdev, "Error getting MAC stats\n");
3519 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3520 cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3521 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3522 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3523 QLC_83XX_STAT_RX, &ret);
3525 netdev_err(netdev, "Error getting Rx stats\n");
3527 qlcnic_free_mbx_args(&cmd);
3530 #define QLCNIC_83XX_ADD_PORT0 BIT_0
3531 #define QLCNIC_83XX_ADD_PORT1 BIT_1
3532 #define QLCNIC_83XX_EXTENDED_MEM_SIZE 13 /* In MB */
3533 int qlcnic_83xx_extend_md_capab(struct qlcnic_adapter *adapter)
3535 struct qlcnic_cmd_args cmd;
3538 err = qlcnic_alloc_mbx_args(&cmd, adapter,
3539 QLCNIC_CMD_83XX_EXTEND_ISCSI_DUMP_CAP);
3543 cmd.req.arg[1] = (QLCNIC_83XX_ADD_PORT0 | QLCNIC_83XX_ADD_PORT1);
3544 cmd.req.arg[2] = QLCNIC_83XX_EXTENDED_MEM_SIZE;
3545 cmd.req.arg[3] = QLCNIC_83XX_EXTENDED_MEM_SIZE;
3547 err = qlcnic_issue_cmd(adapter, &cmd);
3549 dev_err(&adapter->pdev->dev,
3550 "failed to issue extend iSCSI minidump capability\n");
3555 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3557 u32 major, minor, sub;
3559 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3560 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3561 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3563 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3564 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3571 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3573 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3574 sizeof(*adapter->ahw->ext_reg_tbl)) +
3575 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) *
3576 sizeof(*adapter->ahw->reg_tbl));
3579 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3583 for (i = QLCNIC_DEV_INFO_SIZE + 1;
3584 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3585 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3587 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3588 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3592 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3594 struct qlcnic_adapter *adapter = netdev_priv(netdev);
3595 struct qlcnic_hardware_context *ahw = adapter->ahw;
3596 struct qlcnic_cmd_args cmd;
3597 u8 val, drv_sds_rings = adapter->drv_sds_rings;
3598 u8 drv_tx_rings = adapter->drv_tx_rings;
3603 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3604 netdev_info(netdev, "Device is resetting\n");
3608 if (qlcnic_get_diag_lock(adapter)) {
3609 netdev_info(netdev, "Device in diagnostics mode\n");
3613 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3619 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3623 if (adapter->flags & QLCNIC_MSIX_ENABLED)
3624 intrpt_id = ahw->intr_tbl[0].id;
3626 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3629 cmd.req.arg[2] = intrpt_id;
3630 cmd.req.arg[3] = BIT_0;
3632 ret = qlcnic_issue_cmd(adapter, &cmd);
3633 data = cmd.rsp.arg[2];
3635 val = LSB(MSW(data));
3636 if (id != intrpt_id)
3637 dev_info(&adapter->pdev->dev,
3638 "Interrupt generated: 0x%x, requested:0x%x\n",
3641 dev_err(&adapter->pdev->dev,
3642 "Interrupt test error: 0x%x\n", val);
3647 ret = !ahw->diag_cnt;
3650 qlcnic_free_mbx_args(&cmd);
3653 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
3656 adapter->drv_sds_rings = drv_sds_rings;
3657 adapter->drv_tx_rings = drv_tx_rings;
3658 qlcnic_release_diag_lock(adapter);
3662 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3663 struct ethtool_pauseparam *pause)
3665 struct qlcnic_hardware_context *ahw = adapter->ahw;
3669 status = qlcnic_83xx_get_port_config(adapter);
3671 dev_err(&adapter->pdev->dev,
3672 "%s: Get Pause Config failed\n", __func__);
3675 config = ahw->port_config;
3676 if (config & QLC_83XX_CFG_STD_PAUSE) {
3677 switch (MSW(config)) {
3678 case QLC_83XX_TX_PAUSE:
3679 pause->tx_pause = 1;
3681 case QLC_83XX_RX_PAUSE:
3682 pause->rx_pause = 1;
3684 case QLC_83XX_TX_RX_PAUSE:
3686 /* Backward compatibility for existing
3689 pause->tx_pause = 1;
3690 pause->rx_pause = 1;
3694 if (QLC_83XX_AUTONEG(config))
3698 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3699 struct ethtool_pauseparam *pause)
3701 struct qlcnic_hardware_context *ahw = adapter->ahw;
3705 status = qlcnic_83xx_get_port_config(adapter);
3707 dev_err(&adapter->pdev->dev,
3708 "%s: Get Pause Config failed.\n", __func__);
3711 config = ahw->port_config;
3713 if (ahw->port_type == QLCNIC_GBE) {
3715 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3716 if (!pause->autoneg)
3717 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3718 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3722 if (!(config & QLC_83XX_CFG_STD_PAUSE))
3723 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3725 if (pause->rx_pause && pause->tx_pause) {
3726 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3727 } else if (pause->rx_pause && !pause->tx_pause) {
3728 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3729 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3730 } else if (pause->tx_pause && !pause->rx_pause) {
3731 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3732 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3733 } else if (!pause->rx_pause && !pause->tx_pause) {
3734 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE |
3735 QLC_83XX_CFG_STD_PAUSE);
3737 status = qlcnic_83xx_set_port_config(adapter);
3739 dev_err(&adapter->pdev->dev,
3740 "%s: Set Pause Config failed.\n", __func__);
3741 ahw->port_config = config;
3746 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3751 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3752 QLC_83XX_FLASH_OEM_READ_SIG);
3753 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3754 QLC_83XX_FLASH_READ_CTRL);
3755 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3759 temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3766 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3770 status = qlcnic_83xx_read_flash_status_reg(adapter);
3771 if (status == -EIO) {
3772 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3779 static int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3781 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3782 struct net_device *netdev = adapter->netdev;
3785 netif_device_detach(netdev);
3786 qlcnic_cancel_idc_work(adapter);
3788 if (netif_running(netdev))
3789 qlcnic_down(adapter, netdev);
3791 qlcnic_83xx_disable_mbx_intr(adapter);
3792 cancel_delayed_work_sync(&adapter->idc_aen_work);
3794 retval = pci_save_state(pdev);
3801 static int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3803 struct qlcnic_hardware_context *ahw = adapter->ahw;
3804 struct qlc_83xx_idc *idc = &ahw->idc;
3807 err = qlcnic_83xx_idc_init(adapter);
3811 if (ahw->nic_mode == QLCNIC_VNIC_MODE) {
3812 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3813 qlcnic_83xx_set_vnic_opmode(adapter);
3815 err = qlcnic_83xx_check_vnic_state(adapter);
3821 err = qlcnic_83xx_idc_reattach_driver(adapter);
3825 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3830 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3832 reinit_completion(&mbx->completion);
3833 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3836 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3841 destroy_workqueue(mbx->work_q);
3846 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3847 struct qlcnic_cmd_args *cmd)
3849 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3851 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3852 qlcnic_free_mbx_args(cmd);
3856 complete(&cmd->completion);
3859 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3861 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3862 struct list_head *head = &mbx->cmd_q;
3863 struct qlcnic_cmd_args *cmd = NULL;
3865 spin_lock_bh(&mbx->queue_lock);
3867 while (!list_empty(head)) {
3868 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3869 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3870 __func__, cmd->cmd_op);
3871 list_del(&cmd->list);
3873 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3876 spin_unlock_bh(&mbx->queue_lock);
3879 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3881 struct qlcnic_hardware_context *ahw = adapter->ahw;
3882 struct qlcnic_mailbox *mbx = ahw->mailbox;
3885 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3888 host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3889 if (host_mbx_ctrl) {
3890 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3891 ahw->idc.collect_dump = 1;
3898 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3902 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3904 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3907 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3908 struct qlcnic_cmd_args *cmd)
3910 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3912 spin_lock_bh(&mbx->queue_lock);
3914 list_del(&cmd->list);
3917 spin_unlock_bh(&mbx->queue_lock);
3919 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3922 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3923 struct qlcnic_cmd_args *cmd)
3925 u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3926 struct qlcnic_hardware_context *ahw = adapter->ahw;
3929 if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3930 mbx_cmd = cmd->req.arg[0];
3931 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3932 for (i = 1; i < cmd->req.num; i++)
3933 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3935 fw_hal_version = ahw->fw_hal_version;
3936 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3937 total_size = cmd->pay_size + hdr_size;
3938 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3939 mbx_cmd = tmp | fw_hal_version << 29;
3940 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3942 /* Back channel specific operations bits */
3943 mbx_cmd = 0x1 | 1 << 4;
3945 if (qlcnic_sriov_pf_check(adapter))
3946 mbx_cmd |= cmd->func_num << 5;
3948 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3950 for (i = 2, j = 0; j < hdr_size; i++, j++)
3951 writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3952 for (j = 0; j < cmd->pay_size; j++, i++)
3953 writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3957 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3959 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3964 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3965 complete(&mbx->completion);
3966 cancel_work_sync(&mbx->work);
3967 flush_workqueue(mbx->work_q);
3968 qlcnic_83xx_flush_mbx_queue(adapter);
3971 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3972 struct qlcnic_cmd_args *cmd,
3973 unsigned long *timeout)
3975 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3977 if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3978 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3979 init_completion(&cmd->completion);
3980 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3982 spin_lock_bh(&mbx->queue_lock);
3984 list_add_tail(&cmd->list, &mbx->cmd_q);
3986 cmd->total_cmds = mbx->num_cmds;
3987 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3988 queue_work(mbx->work_q, &mbx->work);
3990 spin_unlock_bh(&mbx->queue_lock);
3998 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3999 struct qlcnic_cmd_args *cmd)
4004 if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
4005 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
4006 mac_cmd_rcode = (u8)fw_data;
4007 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
4008 mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
4009 mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
4010 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
4011 return QLCNIC_RCODE_SUCCESS;
4018 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
4019 struct qlcnic_cmd_args *cmd)
4021 struct qlcnic_hardware_context *ahw = adapter->ahw;
4022 struct device *dev = &adapter->pdev->dev;
4026 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
4027 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
4028 qlcnic_83xx_get_mbx_data(adapter, cmd);
4030 switch (mbx_err_code) {
4031 case QLCNIC_MBX_RSP_OK:
4032 case QLCNIC_MBX_PORT_RSP_OK:
4033 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
4036 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
4039 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
4040 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
4041 ahw->op_mode, mbx_err_code);
4042 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
4043 qlcnic_dump_mbx(adapter, cmd);
4049 static inline void qlcnic_dump_mailbox_registers(struct qlcnic_adapter *adapter)
4051 struct qlcnic_hardware_context *ahw = adapter->ahw;
4054 offset = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
4055 dev_info(&adapter->pdev->dev, "Mbx interrupt mask=0x%x, Mbx interrupt enable=0x%x, Host mbx control=0x%x, Fw mbx control=0x%x",
4056 readl(ahw->pci_base0 + offset),
4057 QLCRDX(ahw, QLCNIC_MBX_INTR_ENBL),
4058 QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL),
4059 QLCRDX(ahw, QLCNIC_FW_MBX_CTRL));
4062 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
4064 struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
4066 struct qlcnic_adapter *adapter = mbx->adapter;
4067 const struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
4068 struct device *dev = &adapter->pdev->dev;
4069 struct list_head *head = &mbx->cmd_q;
4070 struct qlcnic_hardware_context *ahw;
4071 struct qlcnic_cmd_args *cmd = NULL;
4072 unsigned long flags;
4077 if (qlcnic_83xx_check_mbx_status(adapter)) {
4078 qlcnic_83xx_flush_mbx_queue(adapter);
4082 spin_lock_irqsave(&mbx->aen_lock, flags);
4083 mbx->rsp_status = QLC_83XX_MBX_RESPONSE_WAIT;
4084 spin_unlock_irqrestore(&mbx->aen_lock, flags);
4086 spin_lock_bh(&mbx->queue_lock);
4088 if (list_empty(head)) {
4089 spin_unlock_bh(&mbx->queue_lock);
4092 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
4094 spin_unlock_bh(&mbx->queue_lock);
4096 mbx_ops->encode_cmd(adapter, cmd);
4097 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
4099 if (wait_for_completion_timeout(&mbx->completion,
4100 QLC_83XX_MBX_TIMEOUT)) {
4101 mbx_ops->decode_resp(adapter, cmd);
4102 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
4104 dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
4105 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
4107 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
4108 qlcnic_dump_mailbox_registers(adapter);
4109 qlcnic_83xx_get_mbx_data(adapter, cmd);
4110 qlcnic_dump_mbx(adapter, cmd);
4111 qlcnic_83xx_idc_request_reset(adapter,
4112 QLCNIC_FORCE_FW_DUMP_KEY);
4113 cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
4115 mbx_ops->dequeue_cmd(adapter, cmd);
4119 static const struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
4120 .enqueue_cmd = qlcnic_83xx_enqueue_mbx_cmd,
4121 .dequeue_cmd = qlcnic_83xx_dequeue_mbx_cmd,
4122 .decode_resp = qlcnic_83xx_decode_mbx_rsp,
4123 .encode_cmd = qlcnic_83xx_encode_mbx_cmd,
4124 .nofity_fw = qlcnic_83xx_signal_mbx_cmd,
4127 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
4129 struct qlcnic_hardware_context *ahw = adapter->ahw;
4130 struct qlcnic_mailbox *mbx;
4132 ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
4137 mbx->ops = &qlcnic_83xx_mbx_ops;
4138 mbx->adapter = adapter;
4140 spin_lock_init(&mbx->queue_lock);
4141 spin_lock_init(&mbx->aen_lock);
4142 INIT_LIST_HEAD(&mbx->cmd_q);
4143 init_completion(&mbx->completion);
4145 mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
4146 if (mbx->work_q == NULL) {
4151 INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
4152 set_bit(QLC_83XX_MBX_READY, &mbx->status);
4156 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev,
4157 pci_channel_state_t state)
4159 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4161 if (state == pci_channel_io_perm_failure)
4162 return PCI_ERS_RESULT_DISCONNECT;
4164 if (state == pci_channel_io_normal)
4165 return PCI_ERS_RESULT_RECOVERED;
4167 set_bit(__QLCNIC_AER, &adapter->state);
4168 set_bit(__QLCNIC_RESETTING, &adapter->state);
4170 qlcnic_83xx_aer_stop_poll_work(adapter);
4172 pci_save_state(pdev);
4173 pci_disable_device(pdev);
4175 return PCI_ERS_RESULT_NEED_RESET;
4178 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev)
4180 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4183 pdev->error_state = pci_channel_io_normal;
4184 err = pci_enable_device(pdev);
4188 pci_set_power_state(pdev, PCI_D0);
4189 pci_set_master(pdev);
4190 pci_restore_state(pdev);
4192 err = qlcnic_83xx_aer_reset(adapter);
4194 return PCI_ERS_RESULT_RECOVERED;
4196 clear_bit(__QLCNIC_AER, &adapter->state);
4197 clear_bit(__QLCNIC_RESETTING, &adapter->state);
4198 return PCI_ERS_RESULT_DISCONNECT;
4201 static void qlcnic_83xx_io_resume(struct pci_dev *pdev)
4203 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4205 pci_cleanup_aer_uncorrect_error_status(pdev);
4206 if (test_and_clear_bit(__QLCNIC_AER, &adapter->state))
4207 qlcnic_83xx_aer_start_poll_work(adapter);