drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include <linux/if_vlan.h>
   9 #include <linux/ipv6.h>
  10 #include <linux/ethtool.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/aer.h>
  13
  14 #include "qlcnic.h"
  15 #include "qlcnic_sriov.h"
  16
  17 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *);
  18 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);
  19 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,
  20                                       struct qlcnic_cmd_args *);
  21 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);
  22 static irqreturn_t qlcnic_83xx_handle_aen(int, void *);
  23 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *,
  24                                                       pci_channel_state_t);
  25 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);
  26 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *);
  27 static void qlcnic_83xx_io_resume(struct pci_dev *);
  28 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);
  29 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *);
  30 static int qlcnic_83xx_resume(struct qlcnic_adapter *);
  31 static int qlcnic_83xx_shutdown(struct pci_dev *);
  32 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *);
  33
  34 #define RSS_HASHTYPE_IP_TCP             0x3
  35 #define QLC_83XX_FW_MBX_CMD             0
  36 #define QLC_SKIP_INACTIVE_PCI_REGS      7
  37 #define QLC_MAX_LEGACY_FUNC_SUPP        8
  38
  39 /* 83xx Module type */
  40 #define QLC_83XX_MODULE_FIBRE_10GBASE_LRM       0x1 /* 10GBase-LRM */
  41 #define QLC_83XX_MODULE_FIBRE_10GBASE_LR        0x2 /* 10GBase-LR */
  42 #define QLC_83XX_MODULE_FIBRE_10GBASE_SR        0x3 /* 10GBase-SR */
  43 #define QLC_83XX_MODULE_DA_10GE_PASSIVE_CP      0x4 /* 10GE passive
  44                                                      * copper(compliant)
  45                                                      */
  46 #define QLC_83XX_MODULE_DA_10GE_ACTIVE_CP       0x5 /* 10GE active limiting
  47                                                      * copper(compliant)
  48                                                      */
  49 #define QLC_83XX_MODULE_DA_10GE_LEGACY_CP       0x6 /* 10GE passive copper
  50                                                      * (legacy, best effort)
  51                                                      */
  52 #define QLC_83XX_MODULE_FIBRE_1000BASE_SX       0x7 /* 1000Base-SX */
  53 #define QLC_83XX_MODULE_FIBRE_1000BASE_LX       0x8 /* 1000Base-LX */
  54 #define QLC_83XX_MODULE_FIBRE_1000BASE_CX       0x9 /* 1000Base-CX */
  55 #define QLC_83XX_MODULE_TP_1000BASE_T           0xa /* 1000Base-T*/
  56 #define QLC_83XX_MODULE_DA_1GE_PASSIVE_CP       0xb /* 1GE passive copper
  57                                                      * (legacy, best effort)
  58                                                      */
  59 #define QLC_83XX_MODULE_UNKNOWN                 0xf /* Unknown module type */
  60
  61 /* Port types */
  62 #define QLC_83XX_10_CAPABLE      BIT_8
  63 #define QLC_83XX_100_CAPABLE     BIT_9
  64 #define QLC_83XX_1G_CAPABLE      BIT_10
  65 #define QLC_83XX_10G_CAPABLE     BIT_11
  66 #define QLC_83XX_AUTONEG_ENABLE  BIT_15
  67
  68 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
  69         {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
  70         {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
  71         {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
  72         {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  73         {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
  74         {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
  75         {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
  76         {QLCNIC_CMD_INTRPT_TEST, 22, 12},
  77         {QLCNIC_CMD_SET_MTU, 3, 1},
  78         {QLCNIC_CMD_READ_PHY, 4, 2},
  79         {QLCNIC_CMD_WRITE_PHY, 5, 1},
  80         {QLCNIC_CMD_READ_HW_REG, 4, 1},
  81         {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  82         {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  83         {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  84         {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  85         {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  86         {QLCNIC_CMD_GET_PCI_INFO, 1, 129},
  87         {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
  88         {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
  89         {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  90         {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  91         {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  92         {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  93         {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  94         {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  95         {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
  96         {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  97         {QLCNIC_CMD_TEMP_SIZE, 1, 4},
  98         {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
  99         {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
 100         {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
 101         {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
 102         {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
 103         {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
 104         {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
 105         {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
 106         {QLCNIC_CMD_GET_STATISTICS, 2, 80},
 107         {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
 108         {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
 109         {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
 110         {QLCNIC_CMD_IDC_ACK, 5, 1},
 111         {QLCNIC_CMD_INIT_NIC_FUNC, 3, 1},
 112         {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
 113         {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
 114         {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
 115         {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
 116         {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
 117         {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
 118         {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
 119         {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
 120         {QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50},
 121         {QLCNIC_CMD_SET_INGRESS_ENCAP, 2, 1},
 122         {QLCNIC_CMD_83XX_EXTEND_ISCSI_DUMP_CAP, 4, 1},
 123 };
 124
 125 const u32 qlcnic_83xx_ext_reg_tbl[] = {
 126         0x38CC,         /* Global Reset */
 127         0x38F0,         /* Wildcard */
 128         0x38FC,         /* Informant */
 129         0x3038,         /* Host MBX ctrl */
 130         0x303C,         /* FW MBX ctrl */
 131         0x355C,         /* BOOT LOADER ADDRESS REG */
 132         0x3560,         /* BOOT LOADER SIZE REG */
 133         0x3564,         /* FW IMAGE ADDR REG */
 134         0x1000,         /* MBX intr enable */
 135         0x1200,         /* Default Intr mask */
 136         0x1204,         /* Default Interrupt ID */
 137         0x3780,         /* QLC_83XX_IDC_MAJ_VERSION */
 138         0x3784,         /* QLC_83XX_IDC_DEV_STATE */
 139         0x3788,         /* QLC_83XX_IDC_DRV_PRESENCE */
 140         0x378C,         /* QLC_83XX_IDC_DRV_ACK */
 141         0x3790,         /* QLC_83XX_IDC_CTRL */
 142         0x3794,         /* QLC_83XX_IDC_DRV_AUDIT */
 143         0x3798,         /* QLC_83XX_IDC_MIN_VERSION */
 144         0x379C,         /* QLC_83XX_RECOVER_DRV_LOCK */
 145         0x37A0,         /* QLC_83XX_IDC_PF_0 */
 146         0x37A4,         /* QLC_83XX_IDC_PF_1 */
 147         0x37A8,         /* QLC_83XX_IDC_PF_2 */
 148         0x37AC,         /* QLC_83XX_IDC_PF_3 */
 149         0x37B0,         /* QLC_83XX_IDC_PF_4 */
 150         0x37B4,         /* QLC_83XX_IDC_PF_5 */
 151         0x37B8,         /* QLC_83XX_IDC_PF_6 */
 152         0x37BC,         /* QLC_83XX_IDC_PF_7 */
 153         0x37C0,         /* QLC_83XX_IDC_PF_8 */
 154         0x37C4,         /* QLC_83XX_IDC_PF_9 */
 155         0x37C8,         /* QLC_83XX_IDC_PF_10 */
 156         0x37CC,         /* QLC_83XX_IDC_PF_11 */
 157         0x37D0,         /* QLC_83XX_IDC_PF_12 */
 158         0x37D4,         /* QLC_83XX_IDC_PF_13 */
 159         0x37D8,         /* QLC_83XX_IDC_PF_14 */
 160         0x37DC,         /* QLC_83XX_IDC_PF_15 */
 161         0x37E0,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
 162         0x37E4,         /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
 163         0x37F0,         /* QLC_83XX_DRV_OP_MODE */
 164         0x37F4,         /* QLC_83XX_VNIC_STATE */
 165         0x3868,         /* QLC_83XX_DRV_LOCK */
 166         0x386C,         /* QLC_83XX_DRV_UNLOCK */
 167         0x3504,         /* QLC_83XX_DRV_LOCK_ID */
 168         0x34A4,         /* QLC_83XX_ASIC_TEMP */
 169 };
 170
 171 const u32 qlcnic_83xx_reg_tbl[] = {
 172         0x34A8,         /* PEG_HALT_STAT1 */
 173         0x34AC,         /* PEG_HALT_STAT2 */
 174         0x34B0,         /* FW_HEARTBEAT */
 175         0x3500,         /* FLASH LOCK_ID */
 176         0x3528,         /* FW_CAPABILITIES */
 177         0x3538,         /* Driver active, DRV_REG0 */
 178         0x3540,         /* Device state, DRV_REG1 */
 179         0x3544,         /* Driver state, DRV_REG2 */
 180         0x3548,         /* Driver scratch, DRV_REG3 */
 181         0x354C,         /* Device partition info, DRV_REG4 */
 182         0x3524,         /* Driver IDC ver, DRV_REG5 */
 183         0x3550,         /* FW_VER_MAJOR */
 184         0x3554,         /* FW_VER_MINOR */
 185         0x3558,         /* FW_VER_SUB */
 186         0x359C,         /* NPAR STATE */
 187         0x35FC,         /* FW_IMG_VALID */
 188         0x3650,         /* CMD_PEG_STATE */
 189         0x373C,         /* RCV_PEG_STATE */
 190         0x37B4,         /* ASIC TEMP */
 191         0x356C,         /* FW API */
 192         0x3570,         /* DRV OP MODE */
 193         0x3850,         /* FLASH LOCK */
 194         0x3854,         /* FLASH UNLOCK */
 195 };
 196
 197 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
 198         .read_crb                       = qlcnic_83xx_read_crb,
 199         .write_crb                      = qlcnic_83xx_write_crb,
 200         .read_reg                       = qlcnic_83xx_rd_reg_indirect,
 201         .write_reg                      = qlcnic_83xx_wrt_reg_indirect,
 202         .get_mac_address                = qlcnic_83xx_get_mac_address,
 203         .setup_intr                     = qlcnic_83xx_setup_intr,
 204         .alloc_mbx_args                 = qlcnic_83xx_alloc_mbx_args,
 205         .mbx_cmd                        = qlcnic_83xx_issue_cmd,
 206         .get_func_no                    = qlcnic_83xx_get_func_no,
 207         .api_lock                       = qlcnic_83xx_cam_lock,
 208         .api_unlock                     = qlcnic_83xx_cam_unlock,
 209         .add_sysfs                      = qlcnic_83xx_add_sysfs,
 210         .remove_sysfs                   = qlcnic_83xx_remove_sysfs,
 211         .process_lb_rcv_ring_diag       = qlcnic_83xx_process_rcv_ring_diag,
 212         .create_rx_ctx                  = qlcnic_83xx_create_rx_ctx,
 213         .create_tx_ctx                  = qlcnic_83xx_create_tx_ctx,
 214         .del_rx_ctx                     = qlcnic_83xx_del_rx_ctx,
 215         .del_tx_ctx                     = qlcnic_83xx_del_tx_ctx,
 216         .setup_link_event               = qlcnic_83xx_setup_link_event,
 217         .get_nic_info                   = qlcnic_83xx_get_nic_info,
 218         .get_pci_info                   = qlcnic_83xx_get_pci_info,
 219         .set_nic_info                   = qlcnic_83xx_set_nic_info,
 220         .change_macvlan                 = qlcnic_83xx_sre_macaddr_change,
 221         .napi_enable                    = qlcnic_83xx_napi_enable,
 222         .napi_disable                   = qlcnic_83xx_napi_disable,
 223         .config_intr_coal               = qlcnic_83xx_config_intr_coal,
 224         .config_rss                     = qlcnic_83xx_config_rss,
 225         .config_hw_lro                  = qlcnic_83xx_config_hw_lro,
 226         .config_promisc_mode            = qlcnic_83xx_nic_set_promisc,
 227         .change_l2_filter               = qlcnic_83xx_change_l2_filter,
 228         .get_board_info                 = qlcnic_83xx_get_port_info,
 229         .set_mac_filter_count           = qlcnic_83xx_set_mac_filter_count,
 230         .free_mac_list                  = qlcnic_82xx_free_mac_list,
 231         .io_error_detected              = qlcnic_83xx_io_error_detected,
 232         .io_slot_reset                  = qlcnic_83xx_io_slot_reset,
 233         .io_resume                      = qlcnic_83xx_io_resume,
 234         .get_beacon_state               = qlcnic_83xx_get_beacon_state,
 235         .enable_sds_intr                = qlcnic_83xx_enable_sds_intr,
 236         .disable_sds_intr               = qlcnic_83xx_disable_sds_intr,
 237         .enable_tx_intr                 = qlcnic_83xx_enable_tx_intr,
 238         .disable_tx_intr                = qlcnic_83xx_disable_tx_intr,
 239         .get_saved_state                = qlcnic_83xx_get_saved_state,
 240         .set_saved_state                = qlcnic_83xx_set_saved_state,
 241         .cache_tmpl_hdr_values          = qlcnic_83xx_cache_tmpl_hdr_values,
 242         .get_cap_size                   = qlcnic_83xx_get_cap_size,
 243         .set_sys_info                   = qlcnic_83xx_set_sys_info,
 244         .store_cap_mask                 = qlcnic_83xx_store_cap_mask,
 245         .encap_rx_offload               = qlcnic_83xx_encap_rx_offload,
 246         .encap_tx_offload               = qlcnic_83xx_encap_tx_offload,
 247 };
 248
 249 static struct qlcnic_nic_template qlcnic_83xx_ops = {
 250         .config_bridged_mode    = qlcnic_config_bridged_mode,
 251         .config_led             = qlcnic_config_led,
 252         .request_reset          = qlcnic_83xx_idc_request_reset,
 253         .cancel_idc_work        = qlcnic_83xx_idc_exit,
 254         .napi_add               = qlcnic_83xx_napi_add,
 255         .napi_del               = qlcnic_83xx_napi_del,
 256         .config_ipaddr          = qlcnic_83xx_config_ipaddr,
 257         .clear_legacy_intr      = qlcnic_83xx_clear_legacy_intr,
 258         .shutdown               = qlcnic_83xx_shutdown,
 259         .resume                 = qlcnic_83xx_resume,
 260 };
 261
 262 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
 263 {
 264         ahw->hw_ops             = &qlcnic_83xx_hw_ops;
 265         ahw->reg_tbl            = (u32 *)qlcnic_83xx_reg_tbl;
 266         ahw->ext_reg_tbl        = (u32 *)qlcnic_83xx_ext_reg_tbl;
 267 }
 268
 269 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
 270 {
 271         u32 fw_major, fw_minor, fw_build;
 272         struct pci_dev *pdev = adapter->pdev;
 273
 274         fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
 275         fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
 276         fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
 277         adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
 278
 279         dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
 280                  QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
 281
 282         return adapter->fw_version;
 283 }
 284
 285 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
 286 {
 287         void __iomem *base;
 288         u32 val;
 289
 290         base = adapter->ahw->pci_base0 +
 291                QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
 292         writel(addr, base);
 293         val = readl(base);
 294         if (val != addr)
 295                 return -EIO;
 296
 297         return 0;
 298 }
 299
 300 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 301                                 int *err)
 302 {
 303         struct qlcnic_hardware_context *ahw = adapter->ahw;
 304
 305         *err = __qlcnic_set_win_base(adapter, (u32) addr);
 306         if (!*err) {
 307                 return QLCRDX(ahw, QLCNIC_WILDCARD);
 308         } else {
 309                 dev_err(&adapter->pdev->dev,
 310                         "%s failed, addr = 0x%lx\n", __func__, addr);
 311                 return -EIO;
 312         }
 313 }
 314
 315 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
 316                                  u32 data)
 317 {
 318         int err;
 319         struct qlcnic_hardware_context *ahw = adapter->ahw;
 320
 321         err = __qlcnic_set_win_base(adapter, (u32) addr);
 322         if (!err) {
 323                 QLCWRX(ahw, QLCNIC_WILDCARD, data);
 324                 return 0;
 325         } else {
 326                 dev_err(&adapter->pdev->dev,
 327                         "%s failed, addr = 0x%x data = 0x%x\n",
 328                         __func__, (int)addr, data);
 329                 return err;
 330         }
 331 }
 332
 333 static void qlcnic_83xx_enable_legacy(struct qlcnic_adapter *adapter)
 334 {
 335         struct qlcnic_hardware_context *ahw = adapter->ahw;
 336
 337         /* MSI-X enablement failed, use legacy interrupt */
 338         adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
 339         adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
 340         adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
 341         adapter->msix_entries[0].vector = adapter->pdev->irq;
 342         dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
 343 }
 344
 345 static int qlcnic_83xx_calculate_msix_vector(struct qlcnic_adapter *adapter)
 346 {
 347         int num_msix;
 348
 349         num_msix = adapter->drv_sds_rings;
 350
 351         /* account for AEN interrupt MSI-X based interrupts */
 352         num_msix += 1;
 353
 354         if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
 355                 num_msix += adapter->drv_tx_rings;
 356
 357         return num_msix;
 358 }
 359
 360 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter)
 361 {
 362         struct qlcnic_hardware_context *ahw = adapter->ahw;
 363         int err, i, num_msix;
 364
 365         if (adapter->flags & QLCNIC_TSS_RSS) {
 366                 err = qlcnic_setup_tss_rss_intr(adapter);
 367                 if (err < 0)
 368                         return err;
 369                 num_msix = ahw->num_msix;
 370         } else {
 371                 num_msix = qlcnic_83xx_calculate_msix_vector(adapter);
 372
 373                 err = qlcnic_enable_msix(adapter, num_msix);
 374                 if (err == -ENOMEM)
 375                         return err;
 376
 377                 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
 378                         num_msix = ahw->num_msix;
 379                 } else {
 380                         if (qlcnic_sriov_vf_check(adapter))
 381                                 return -EINVAL;
 382                         num_msix = 1;
 383                         adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
 384                         adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
 385                 }
 386         }
 387
 388         /* setup interrupt mapping table for fw */
 389         ahw->intr_tbl = vzalloc(num_msix *
 390                                 sizeof(struct qlcnic_intrpt_config));
 391         if (!ahw->intr_tbl)
 392                 return -ENOMEM;
 393
 394         if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
 395                 if (adapter->ahw->pci_func >= QLC_MAX_LEGACY_FUNC_SUPP) {
 396                         dev_err(&adapter->pdev->dev, "PCI function number 8 and higher are not supported with legacy interrupt, func 0x%x\n",
 397                                 ahw->pci_func);
 398                         return -EOPNOTSUPP;
 399                 }
 400
 401                 qlcnic_83xx_enable_legacy(adapter);
 402         }
 403
 404         for (i = 0; i < num_msix; i++) {
 405                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
 406                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
 407                 else
 408                         ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
 409                 ahw->intr_tbl[i].id = i;
 410                 ahw->intr_tbl[i].src = 0;
 411         }
 412
 413         return 0;
 414 }
 415
 416 static inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
 417 {
 418         writel(0, adapter->tgt_mask_reg);
 419 }
 420
 421 static inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
 422 {
 423         if (adapter->tgt_mask_reg)
 424                 writel(1, adapter->tgt_mask_reg);
 425 }
 426
 427 static inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
 428                                                     *adapter)
 429 {
 430         u32 mask;
 431
 432         /* Mailbox in MSI-x mode and Legacy Interrupt share the same
 433          * source register. We could be here before contexts are created
 434          * and sds_ring->crb_intr_mask has not been initialized, calculate
 435          * BAR offset for Interrupt Source Register
 436          */
 437         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 438         writel(0, adapter->ahw->pci_base0 + mask);
 439 }
 440
 441 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
 442 {
 443         u32 mask;
 444
 445         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
 446         writel(1, adapter->ahw->pci_base0 + mask);
 447         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
 448 }
 449
 450 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
 451                                      struct qlcnic_cmd_args *cmd)
 452 {
 453         int i;
 454
 455         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 456                 return;
 457
 458         for (i = 0; i < cmd->rsp.num; i++)
 459                 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
 460 }
 461
 462 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
 463 {
 464         u32 intr_val;
 465         struct qlcnic_hardware_context *ahw = adapter->ahw;
 466         int retries = 0;
 467
 468         intr_val = readl(adapter->tgt_status_reg);
 469
 470         if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
 471                 return IRQ_NONE;
 472
 473         if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
 474                 adapter->stats.spurious_intr++;
 475                 return IRQ_NONE;
 476         }
 477         /* The barrier is required to ensure writes to the registers */
 478         wmb();
 479
 480         /* clear the interrupt trigger control register */
 481         writel(0, adapter->isr_int_vec);
 482         intr_val = readl(adapter->isr_int_vec);
 483         do {
 484                 intr_val = readl(adapter->tgt_status_reg);
 485                 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
 486                         break;
 487                 retries++;
 488         } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
 489                  (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
 490
 491         return IRQ_HANDLED;
 492 }
 493
 494 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
 495 {
 496         mbx->rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 497         complete(&mbx->completion);
 498 }
 499
 500 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
 501 {
 502         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
 503         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 504         unsigned long flags;
 505
 506         spin_lock_irqsave(&mbx->aen_lock, flags);
 507         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
 508         if (!(resp & QLCNIC_SET_OWNER))
 509                 goto out;
 510
 511         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
 512         if (event &  QLCNIC_MBX_ASYNC_EVENT) {
 513                 __qlcnic_83xx_process_aen(adapter);
 514         } else {
 515                 if (mbx->rsp_status != rsp_status)
 516                         qlcnic_83xx_notify_mbx_response(mbx);
 517         }
 518 out:
 519         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 520         spin_unlock_irqrestore(&mbx->aen_lock, flags);
 521 }
 522
 523 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
 524 {
 525         struct qlcnic_adapter *adapter = data;
 526         struct qlcnic_host_sds_ring *sds_ring;
 527         struct qlcnic_hardware_context *ahw = adapter->ahw;
 528
 529         if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
 530                 return IRQ_NONE;
 531
 532         qlcnic_83xx_poll_process_aen(adapter);
 533
 534         if (ahw->diag_test) {
 535                 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST)
 536                         ahw->diag_cnt++;
 537                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 538                 return IRQ_HANDLED;
 539         }
 540
 541         if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
 542                 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 543         } else {
 544                 sds_ring = &adapter->recv_ctx->sds_rings[0];
 545                 napi_schedule(&sds_ring->napi);
 546         }
 547
 548         return IRQ_HANDLED;
 549 }
 550
 551 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
 552 {
 553         struct qlcnic_host_sds_ring *sds_ring = data;
 554         struct qlcnic_adapter *adapter = sds_ring->adapter;
 555
 556         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 557                 goto done;
 558
 559         if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
 560                 return IRQ_NONE;
 561
 562 done:
 563         adapter->ahw->diag_cnt++;
 564         qlcnic_enable_sds_intr(adapter, sds_ring);
 565
 566         return IRQ_HANDLED;
 567 }
 568
 569 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
 570 {
 571         u32 num_msix;
 572
 573         if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
 574                 qlcnic_83xx_set_legacy_intr_mask(adapter);
 575
 576         qlcnic_83xx_disable_mbx_intr(adapter);
 577
 578         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 579                 num_msix = adapter->ahw->num_msix - 1;
 580         else
 581                 num_msix = 0;
 582
 583         msleep(20);
 584
 585         if (adapter->msix_entries) {
 586                 synchronize_irq(adapter->msix_entries[num_msix].vector);
 587                 free_irq(adapter->msix_entries[num_msix].vector, adapter);
 588         }
 589 }
 590
 591 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
 592 {
 593         irq_handler_t handler;
 594         u32 val;
 595         int err = 0;
 596         unsigned long flags = 0;
 597
 598         if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
 599             !(adapter->flags & QLCNIC_MSIX_ENABLED))
 600                 flags |= IRQF_SHARED;
 601
 602         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
 603                 handler = qlcnic_83xx_handle_aen;
 604                 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
 605                 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
 606                 if (err) {
 607                         dev_err(&adapter->pdev->dev,
 608                                 "failed to register MBX interrupt\n");
 609                         return err;
 610                 }
 611         } else {
 612                 handler = qlcnic_83xx_intr;
 613                 val = adapter->msix_entries[0].vector;
 614                 err = request_irq(val, handler, flags, "qlcnic", adapter);
 615                 if (err) {
 616                         dev_err(&adapter->pdev->dev,
 617                                 "failed to register INTx interrupt\n");
 618                         return err;
 619                 }
 620                 qlcnic_83xx_clear_legacy_intr_mask(adapter);
 621         }
 622
 623         /* Enable mailbox interrupt */
 624         qlcnic_83xx_enable_mbx_interrupt(adapter);
 625
 626         return err;
 627 }
 628
 629 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
 630 {
 631         u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
 632         adapter->ahw->pci_func = (val >> 24) & 0xff;
 633 }
 634
 635 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
 636 {
 637         void __iomem *addr;
 638         u32 val, limit = 0;
 639
 640         struct qlcnic_hardware_context *ahw = adapter->ahw;
 641
 642         addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
 643         do {
 644                 val = readl(addr);
 645                 if (val) {
 646                         /* write the function number to register */
 647                         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
 648                                             ahw->pci_func);
 649                         return 0;
 650                 }
 651                 usleep_range(1000, 2000);
 652         } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
 653
 654         return -EIO;
 655 }
 656
 657 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
 658 {
 659         void __iomem *addr;
 660         u32 val;
 661         struct qlcnic_hardware_context *ahw = adapter->ahw;
 662
 663         addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
 664         val = readl(addr);
 665 }
 666
 667 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
 668                           loff_t offset, size_t size)
 669 {
 670         int ret = 0;
 671         u32 data;
 672
 673         if (qlcnic_api_lock(adapter)) {
 674                 dev_err(&adapter->pdev->dev,
 675                         "%s: failed to acquire lock. addr offset 0x%x\n",
 676                         __func__, (u32)offset);
 677                 return;
 678         }
 679
 680         data = QLCRD32(adapter, (u32) offset, &ret);
 681         qlcnic_api_unlock(adapter);
 682
 683         if (ret == -EIO) {
 684                 dev_err(&adapter->pdev->dev,
 685                         "%s: failed. addr offset 0x%x\n",
 686                         __func__, (u32)offset);
 687                 return;
 688         }
 689         memcpy(buf, &data, size);
 690 }
 691
 692 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
 693                            loff_t offset, size_t size)
 694 {
 695         u32 data;
 696
 697         memcpy(&data, buf, size);
 698         qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
 699 }
 700
 701 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
 702 {
 703         struct qlcnic_hardware_context *ahw = adapter->ahw;
 704         int status;
 705
 706         status = qlcnic_83xx_get_port_config(adapter);
 707         if (status) {
 708                 dev_err(&adapter->pdev->dev,
 709                         "Get Port Info failed\n");
 710         } else {
 711
 712                 if (ahw->port_config & QLC_83XX_10G_CAPABLE) {
 713                         ahw->port_type = QLCNIC_XGBE;
 714                 } else if (ahw->port_config & QLC_83XX_10_CAPABLE ||
 715                            ahw->port_config & QLC_83XX_100_CAPABLE ||
 716                            ahw->port_config & QLC_83XX_1G_CAPABLE) {
 717                         ahw->port_type = QLCNIC_GBE;
 718                 } else {
 719                         ahw->port_type = QLCNIC_XGBE;
 720                 }
 721
 722                 if (QLC_83XX_AUTONEG(ahw->port_config))
 723                         ahw->link_autoneg = AUTONEG_ENABLE;
 724
 725         }
 726         return status;
 727 }
 728
 729 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
 730 {
 731         struct qlcnic_hardware_context *ahw = adapter->ahw;
 732         u16 act_pci_fn = ahw->total_nic_func;
 733         u16 count;
 734
 735         ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
 736         if (act_pci_fn <= 2)
 737                 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
 738                          act_pci_fn;
 739         else
 740                 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
 741                          act_pci_fn;
 742         ahw->max_uc_count = count;
 743 }
 744
 745 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
 746 {
 747         u32 val;
 748
 749         if (adapter->flags & QLCNIC_MSIX_ENABLED)
 750                 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
 751         else
 752                 val = BIT_2;
 753
 754         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
 755         qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
 756 }
 757
 758 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
 759                           const struct pci_device_id *ent)
 760 {
 761         u32 op_mode, priv_level;
 762         struct qlcnic_hardware_context *ahw = adapter->ahw;
 763
 764         ahw->fw_hal_version = 2;
 765         qlcnic_get_func_no(adapter);
 766
 767         if (qlcnic_sriov_vf_check(adapter)) {
 768                 qlcnic_sriov_vf_set_ops(adapter);
 769                 return;
 770         }
 771
 772         /* Determine function privilege level */
 773         op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
 774         if (op_mode == QLC_83XX_DEFAULT_OPMODE)
 775                 priv_level = QLCNIC_MGMT_FUNC;
 776         else
 777                 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
 778                                                          ahw->pci_func);
 779
 780         if (priv_level == QLCNIC_NON_PRIV_FUNC) {
 781                 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
 782                 dev_info(&adapter->pdev->dev,
 783                          "HAL Version: %d Non Privileged function\n",
 784                          ahw->fw_hal_version);
 785                 adapter->nic_ops = &qlcnic_vf_ops;
 786         } else {
 787                 if (pci_find_ext_capability(adapter->pdev,
 788                                             PCI_EXT_CAP_ID_SRIOV))
 789                         set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
 790                 adapter->nic_ops = &qlcnic_83xx_ops;
 791         }
 792 }
 793
 794 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
 795                                         u32 data[]);
 796 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 797                                             u32 data[]);
 798
 799 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
 800                      struct qlcnic_cmd_args *cmd)
 801 {
 802         int i;
 803
 804         if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
 805                 return;
 806
 807         dev_info(&adapter->pdev->dev,
 808                  "Host MBX regs(%d)\n", cmd->req.num);
 809         for (i = 0; i < cmd->req.num; i++) {
 810                 if (i && !(i % 8))
 811                         pr_info("\n");
 812                 pr_info("%08x ", cmd->req.arg[i]);
 813         }
 814         pr_info("\n");
 815         dev_info(&adapter->pdev->dev,
 816                  "FW MBX regs(%d)\n", cmd->rsp.num);
 817         for (i = 0; i < cmd->rsp.num; i++) {
 818                 if (i && !(i % 8))
 819                         pr_info("\n");
 820                 pr_info("%08x ", cmd->rsp.arg[i]);
 821         }
 822         pr_info("\n");
 823 }
 824
 825 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
 826                                                 struct qlcnic_cmd_args *cmd)
 827 {
 828         struct qlcnic_hardware_context *ahw = adapter->ahw;
 829         int opcode = LSW(cmd->req.arg[0]);
 830         unsigned long max_loops;
 831
 832         max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
 833
 834         for (; max_loops; max_loops--) {
 835                 if (atomic_read(&cmd->rsp_status) ==
 836                     QLC_83XX_MBX_RESPONSE_ARRIVED)
 837                         return;
 838
 839                 udelay(1);
 840         }
 841
 842         dev_err(&adapter->pdev->dev,
 843                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 844                 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
 845         flush_workqueue(ahw->mailbox->work_q);
 846         return;
 847 }
 848
 849 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
 850                           struct qlcnic_cmd_args *cmd)
 851 {
 852         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 853         struct qlcnic_hardware_context *ahw = adapter->ahw;
 854         int cmd_type, err, opcode;
 855         unsigned long timeout;
 856
 857         if (!mbx)
 858                 return -EIO;
 859
 860         opcode = LSW(cmd->req.arg[0]);
 861         cmd_type = cmd->type;
 862         err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
 863         if (err) {
 864                 dev_err(&adapter->pdev->dev,
 865                         "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 866                         __func__, opcode, cmd->type, ahw->pci_func,
 867                         ahw->op_mode);
 868                 return err;
 869         }
 870
 871         switch (cmd_type) {
 872         case QLC_83XX_MBX_CMD_WAIT:
 873                 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
 874                         dev_err(&adapter->pdev->dev,
 875                                 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 876                                 __func__, opcode, cmd_type, ahw->pci_func,
 877                                 ahw->op_mode);
 878                         flush_workqueue(mbx->work_q);
 879                 }
 880                 break;
 881         case QLC_83XX_MBX_CMD_NO_WAIT:
 882                 return 0;
 883         case QLC_83XX_MBX_CMD_BUSY_WAIT:
 884                 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
 885                 break;
 886         default:
 887                 dev_err(&adapter->pdev->dev,
 888                         "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
 889                         __func__, opcode, cmd_type, ahw->pci_func,
 890                         ahw->op_mode);
 891                 qlcnic_83xx_detach_mailbox_work(adapter);
 892         }
 893
 894         return cmd->rsp_opcode;
 895 }
 896
 897 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
 898                                struct qlcnic_adapter *adapter, u32 type)
 899 {
 900         int i, size;
 901         u32 temp;
 902         const struct qlcnic_mailbox_metadata *mbx_tbl;
 903
 904         memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
 905         mbx_tbl = qlcnic_83xx_mbx_tbl;
 906         size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
 907         for (i = 0; i < size; i++) {
 908                 if (type == mbx_tbl[i].cmd) {
 909                         mbx->op_type = QLC_83XX_FW_MBX_CMD;
 910                         mbx->req.num = mbx_tbl[i].in_args;
 911                         mbx->rsp.num = mbx_tbl[i].out_args;
 912                         mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
 913                                                GFP_ATOMIC);
 914                         if (!mbx->req.arg)
 915                                 return -ENOMEM;
 916                         mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
 917                                                GFP_ATOMIC);
 918                         if (!mbx->rsp.arg) {
 919                                 kfree(mbx->req.arg);
 920                                 mbx->req.arg = NULL;
 921                                 return -ENOMEM;
 922                         }
 923                         temp = adapter->ahw->fw_hal_version << 29;
 924                         mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
 925                         mbx->cmd_op = type;
 926                         return 0;
 927                 }
 928         }
 929
 930         dev_err(&adapter->pdev->dev, "%s: Invalid mailbox command opcode 0x%x\n",
 931                 __func__, type);
 932         return -EINVAL;
 933 }
 934
 935 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
 936 {
 937         struct qlcnic_adapter *adapter;
 938         struct qlcnic_cmd_args cmd;
 939         int i, err = 0;
 940
 941         adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
 942         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
 943         if (err)
 944                 return;
 945
 946         for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
 947                 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
 948
 949         err = qlcnic_issue_cmd(adapter, &cmd);
 950         if (err)
 951                 dev_info(&adapter->pdev->dev,
 952                          "%s: Mailbox IDC ACK failed.\n", __func__);
 953         qlcnic_free_mbx_args(&cmd);
 954 }
 955
 956 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
 957                                             u32 data[])
 958 {
 959         dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
 960                 QLCNIC_MBX_RSP(data[0]));
 961         clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
 962         return;
 963 }
 964
 965 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
 966 {
 967         struct qlcnic_hardware_context *ahw = adapter->ahw;
 968         u32 event[QLC_83XX_MBX_AEN_CNT];
 969         int i;
 970
 971         for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 972                 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
 973
 974         switch (QLCNIC_MBX_RSP(event[0])) {
 975
 976         case QLCNIC_MBX_LINK_EVENT:
 977                 qlcnic_83xx_handle_link_aen(adapter, event);
 978                 break;
 979         case QLCNIC_MBX_COMP_EVENT:
 980                 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
 981                 break;
 982         case QLCNIC_MBX_REQUEST_EVENT:
 983                 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
 984                         adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
 985                 queue_delayed_work(adapter->qlcnic_wq,
 986                                    &adapter->idc_aen_work, 0);
 987                 break;
 988         case QLCNIC_MBX_TIME_EXTEND_EVENT:
 989                 ahw->extend_lb_time = event[1] >> 8 & 0xf;
 990                 break;
 991         case QLCNIC_MBX_BC_EVENT:
 992                 qlcnic_sriov_handle_bc_event(adapter, event[1]);
 993                 break;
 994         case QLCNIC_MBX_SFP_INSERT_EVENT:
 995                 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
 996                          QLCNIC_MBX_RSP(event[0]));
 997                 break;
 998         case QLCNIC_MBX_SFP_REMOVE_EVENT:
 999                 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
1000                          QLCNIC_MBX_RSP(event[0]));
1001                 break;
1002         case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
1003                 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]);
1004                 break;
1005         default:
1006                 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
1007                         QLCNIC_MBX_RSP(event[0]));
1008                 break;
1009         }
1010
1011         QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
1012 }
1013
1014 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
1015 {
1016         u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
1017         struct qlcnic_hardware_context *ahw = adapter->ahw;
1018         struct qlcnic_mailbox *mbx = ahw->mailbox;
1019         unsigned long flags;
1020
1021         spin_lock_irqsave(&mbx->aen_lock, flags);
1022         resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
1023         if (resp & QLCNIC_SET_OWNER) {
1024                 event = readl(QLCNIC_MBX_FW(ahw, 0));
1025                 if (event &  QLCNIC_MBX_ASYNC_EVENT) {
1026                         __qlcnic_83xx_process_aen(adapter);
1027                 } else {
1028                         if (mbx->rsp_status != rsp_status)
1029                                 qlcnic_83xx_notify_mbx_response(mbx);
1030                 }
1031         }
1032         spin_unlock_irqrestore(&mbx->aen_lock, flags);
1033 }
1034
1035 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
1036 {
1037         struct qlcnic_adapter *adapter;
1038
1039         adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
1040
1041         if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1042                 return;
1043
1044         qlcnic_83xx_process_aen(adapter);
1045         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
1046                            (HZ / 10));
1047 }
1048
1049 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
1050 {
1051         if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1052                 return;
1053
1054         INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
1055         queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
1056 }
1057
1058 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
1059 {
1060         if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1061                 return;
1062         cancel_delayed_work_sync(&adapter->mbx_poll_work);
1063 }
1064
1065 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
1066 {
1067         int index, i, err, sds_mbx_size;
1068         u32 *buf, intrpt_id, intr_mask;
1069         u16 context_id;
1070         u8 num_sds;
1071         struct qlcnic_cmd_args cmd;
1072         struct qlcnic_host_sds_ring *sds;
1073         struct qlcnic_sds_mbx sds_mbx;
1074         struct qlcnic_add_rings_mbx_out *mbx_out;
1075         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1076         struct qlcnic_hardware_context *ahw = adapter->ahw;
1077
1078         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1079         context_id = recv_ctx->context_id;
1080         num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS;
1081         err = ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
1082                                         QLCNIC_CMD_ADD_RCV_RINGS);
1083         if (err) {
1084                 dev_err(&adapter->pdev->dev,
1085                         "Failed to alloc mbx args %d\n", err);
1086                 return err;
1087         }
1088
1089         cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
1090
1091         /* set up status rings, mbx 2-81 */
1092         index = 2;
1093         for (i = 8; i < adapter->drv_sds_rings; i++) {
1094                 memset(&sds_mbx, 0, sds_mbx_size);
1095                 sds = &recv_ctx->sds_rings[i];
1096                 sds->consumer = 0;
1097                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1098                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1099                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1100                 sds_mbx.sds_ring_size = sds->num_desc;
1101
1102                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1103                         intrpt_id = ahw->intr_tbl[i].id;
1104                 else
1105                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1106
1107                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1108                         sds_mbx.intrpt_id = intrpt_id;
1109                 else
1110                         sds_mbx.intrpt_id = 0xffff;
1111                 sds_mbx.intrpt_val = 0;
1112                 buf = &cmd.req.arg[index];
1113                 memcpy(buf, &sds_mbx, sds_mbx_size);
1114                 index += sds_mbx_size / sizeof(u32);
1115         }
1116
1117         /* send the mailbox command */
1118         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1119         if (err) {
1120                 dev_err(&adapter->pdev->dev,
1121                         "Failed to add rings %d\n", err);
1122                 goto out;
1123         }
1124
1125         mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1126         index = 0;
1127         /* status descriptor ring */
1128         for (i = 8; i < adapter->drv_sds_rings; i++) {
1129                 sds = &recv_ctx->sds_rings[i];
1130                 sds->crb_sts_consumer = ahw->pci_base0 +
1131                                         mbx_out->host_csmr[index];
1132                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1133                         intr_mask = ahw->intr_tbl[i].src;
1134                 else
1135                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1136
1137                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1138                 index++;
1139         }
1140 out:
1141         qlcnic_free_mbx_args(&cmd);
1142         return err;
1143 }
1144
1145 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1146 {
1147         int err;
1148         u32 temp = 0;
1149         struct qlcnic_cmd_args cmd;
1150         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1151
1152         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1153                 return;
1154
1155         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1156                 cmd.req.arg[0] |= (0x3 << 29);
1157
1158         if (qlcnic_sriov_pf_check(adapter))
1159                 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1160
1161         cmd.req.arg[1] = recv_ctx->context_id | temp;
1162         err = qlcnic_issue_cmd(adapter, &cmd);
1163         if (err)
1164                 dev_err(&adapter->pdev->dev,
1165                         "Failed to destroy rx ctx in firmware\n");
1166
1167         recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1168         qlcnic_free_mbx_args(&cmd);
1169 }
1170
1171 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1172 {
1173         int i, err, index, sds_mbx_size, rds_mbx_size;
1174         u8 num_sds, num_rds;
1175         u32 *buf, intrpt_id, intr_mask, cap = 0;
1176         struct qlcnic_host_sds_ring *sds;
1177         struct qlcnic_host_rds_ring *rds;
1178         struct qlcnic_sds_mbx sds_mbx;
1179         struct qlcnic_rds_mbx rds_mbx;
1180         struct qlcnic_cmd_args cmd;
1181         struct qlcnic_rcv_mbx_out *mbx_out;
1182         struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1183         struct qlcnic_hardware_context *ahw = adapter->ahw;
1184         num_rds = adapter->max_rds_rings;
1185
1186         if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS)
1187                 num_sds = adapter->drv_sds_rings;
1188         else
1189                 num_sds = QLCNIC_MAX_SDS_RINGS;
1190
1191         sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1192         rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1193         cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1194
1195         if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1196                 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1197
1198         /* set mailbox hdr and capabilities */
1199         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1200                                     QLCNIC_CMD_CREATE_RX_CTX);
1201         if (err)
1202                 return err;
1203
1204         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1205                 cmd.req.arg[0] |= (0x3 << 29);
1206
1207         cmd.req.arg[1] = cap;
1208         cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1209                          (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1210
1211         if (qlcnic_sriov_pf_check(adapter))
1212                 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1213                                                          &cmd.req.arg[6]);
1214         /* set up status rings, mbx 8-57/87 */
1215         index = QLC_83XX_HOST_SDS_MBX_IDX;
1216         for (i = 0; i < num_sds; i++) {
1217                 memset(&sds_mbx, 0, sds_mbx_size);
1218                 sds = &recv_ctx->sds_rings[i];
1219                 sds->consumer = 0;
1220                 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1221                 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1222                 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1223                 sds_mbx.sds_ring_size = sds->num_desc;
1224                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1225                         intrpt_id = ahw->intr_tbl[i].id;
1226                 else
1227                         intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1228                 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1229                         sds_mbx.intrpt_id = intrpt_id;
1230                 else
1231                         sds_mbx.intrpt_id = 0xffff;
1232                 sds_mbx.intrpt_val = 0;
1233                 buf = &cmd.req.arg[index];
1234                 memcpy(buf, &sds_mbx, sds_mbx_size);
1235                 index += sds_mbx_size / sizeof(u32);
1236         }
1237         /* set up receive rings, mbx 88-111/135 */
1238         index = QLCNIC_HOST_RDS_MBX_IDX;
1239         rds = &recv_ctx->rds_rings[0];
1240         rds->producer = 0;
1241         memset(&rds_mbx, 0, rds_mbx_size);
1242         rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1243         rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1244         rds_mbx.reg_ring_sz = rds->dma_size;
1245         rds_mbx.reg_ring_len = rds->num_desc;
1246         /* Jumbo ring */
1247         rds = &recv_ctx->rds_rings[1];
1248         rds->producer = 0;
1249         rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1250         rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1251         rds_mbx.jmb_ring_sz = rds->dma_size;
1252         rds_mbx.jmb_ring_len = rds->num_desc;
1253         buf = &cmd.req.arg[index];
1254         memcpy(buf, &rds_mbx, rds_mbx_size);
1255
1256         /* send the mailbox command */
1257         err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1258         if (err) {
1259                 dev_err(&adapter->pdev->dev,
1260                         "Failed to create Rx ctx in firmware%d\n", err);
1261                 goto out;
1262         }
1263         mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1264         recv_ctx->context_id = mbx_out->ctx_id;
1265         recv_ctx->state = mbx_out->state;
1266         recv_ctx->virt_port = mbx_out->vport_id;
1267         dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1268                  recv_ctx->context_id, recv_ctx->state);
1269         /* Receive descriptor ring */
1270         /* Standard ring */
1271         rds = &recv_ctx->rds_rings[0];
1272         rds->crb_rcv_producer = ahw->pci_base0 +
1273                                 mbx_out->host_prod[0].reg_buf;
1274         /* Jumbo ring */
1275         rds = &recv_ctx->rds_rings[1];
1276         rds->crb_rcv_producer = ahw->pci_base0 +
1277                                 mbx_out->host_prod[0].jmb_buf;
1278         /* status descriptor ring */
1279         for (i = 0; i < num_sds; i++) {
1280                 sds = &recv_ctx->sds_rings[i];
1281                 sds->crb_sts_consumer = ahw->pci_base0 +
1282                                         mbx_out->host_csmr[i];
1283                 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1284                         intr_mask = ahw->intr_tbl[i].src;
1285                 else
1286                         intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1287                 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1288         }
1289
1290         if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS)
1291                 err = qlcnic_83xx_add_rings(adapter);
1292 out:
1293         qlcnic_free_mbx_args(&cmd);
1294         return err;
1295 }
1296
1297 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1298                             struct qlcnic_host_tx_ring *tx_ring)
1299 {
1300         struct qlcnic_cmd_args cmd;
1301         u32 temp = 0;
1302
1303         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1304                 return;
1305
1306         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1307                 cmd.req.arg[0] |= (0x3 << 29);
1308
1309         if (qlcnic_sriov_pf_check(adapter))
1310                 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1311
1312         cmd.req.arg[1] = tx_ring->ctx_id | temp;
1313         if (qlcnic_issue_cmd(adapter, &cmd))
1314                 dev_err(&adapter->pdev->dev,
1315                         "Failed to destroy tx ctx in firmware\n");
1316         qlcnic_free_mbx_args(&cmd);
1317 }
1318
1319 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1320                               struct qlcnic_host_tx_ring *tx, int ring)
1321 {
1322         int err;
1323         u16 msix_id;
1324         u32 *buf, intr_mask, temp = 0;
1325         struct qlcnic_cmd_args cmd;
1326         struct qlcnic_tx_mbx mbx;
1327         struct qlcnic_tx_mbx_out *mbx_out;
1328         struct qlcnic_hardware_context *ahw = adapter->ahw;
1329         u32 msix_vector;
1330
1331         /* Reset host resources */
1332         tx->producer = 0;
1333         tx->sw_consumer = 0;
1334         *(tx->hw_consumer) = 0;
1335
1336         memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1337
1338         /* setup mailbox inbox registerss */
1339         mbx.phys_addr_low = LSD(tx->phys_addr);
1340         mbx.phys_addr_high = MSD(tx->phys_addr);
1341         mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1342         mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1343         mbx.size = tx->num_desc;
1344         if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1345                 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1346                         msix_vector = adapter->drv_sds_rings + ring;
1347                 else
1348                         msix_vector = adapter->drv_sds_rings - 1;
1349                 msix_id = ahw->intr_tbl[msix_vector].id;
1350         } else {
1351                 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1352         }
1353
1354         if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1355                 mbx.intr_id = msix_id;
1356         else
1357                 mbx.intr_id = 0xffff;
1358         mbx.src = 0;
1359
1360         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1361         if (err)
1362                 return err;
1363
1364         if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1365                 cmd.req.arg[0] |= (0x3 << 29);
1366
1367         if (qlcnic_sriov_pf_check(adapter))
1368                 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1369
1370         cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1371         cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp;
1372
1373         buf = &cmd.req.arg[6];
1374         memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1375         /* send the mailbox command*/
1376         err = qlcnic_issue_cmd(adapter, &cmd);
1377         if (err) {
1378                 netdev_err(adapter->netdev,
1379                            "Failed to create Tx ctx in firmware 0x%x\n", err);
1380                 goto out;
1381         }
1382         mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1383         tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1384         tx->ctx_id = mbx_out->ctx_id;
1385         if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1386             !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1387                 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src;
1388                 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1389         }
1390         netdev_info(adapter->netdev,
1391                     "Tx Context[0x%x] Created, state:0x%x\n",
1392                     tx->ctx_id, mbx_out->state);
1393 out:
1394         qlcnic_free_mbx_args(&cmd);
1395         return err;
1396 }
1397
1398 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1399                                       u8 num_sds_ring)
1400 {
1401         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1402         struct qlcnic_host_sds_ring *sds_ring;
1403         struct qlcnic_host_rds_ring *rds_ring;
1404         u16 adapter_state = adapter->is_up;
1405         u8 ring;
1406         int ret;
1407
1408         netif_device_detach(netdev);
1409
1410         if (netif_running(netdev))
1411                 __qlcnic_down(adapter, netdev);
1412
1413         qlcnic_detach(adapter);
1414
1415         adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
1416         adapter->ahw->diag_test = test;
1417         adapter->ahw->linkup = 0;
1418
1419         ret = qlcnic_attach(adapter);
1420         if (ret) {
1421                 netif_device_attach(netdev);
1422                 return ret;
1423         }
1424
1425         ret = qlcnic_fw_create_ctx(adapter);
1426         if (ret) {
1427                 qlcnic_detach(adapter);
1428                 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1429                         adapter->drv_sds_rings = num_sds_ring;
1430                         qlcnic_attach(adapter);
1431                 }
1432                 netif_device_attach(netdev);
1433                 return ret;
1434         }
1435
1436         for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1437                 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1438                 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1439         }
1440
1441         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1442                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1443                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1444                         qlcnic_enable_sds_intr(adapter, sds_ring);
1445                 }
1446         }
1447
1448         if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1449                 adapter->ahw->loopback_state = 0;
1450                 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1451         }
1452
1453         set_bit(__QLCNIC_DEV_UP, &adapter->state);
1454         return 0;
1455 }
1456
1457 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1458                                       u8 drv_sds_rings)
1459 {
1460         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1461         struct qlcnic_host_sds_ring *sds_ring;
1462         int ring;
1463
1464         clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1465         if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1466                 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1467                         sds_ring = &adapter->recv_ctx->sds_rings[ring];
1468                         if (adapter->flags & QLCNIC_MSIX_ENABLED)
1469                                 qlcnic_disable_sds_intr(adapter, sds_ring);
1470                 }
1471         }
1472
1473         qlcnic_fw_destroy_ctx(adapter);
1474         qlcnic_detach(adapter);
1475
1476         adapter->ahw->diag_test = 0;
1477         adapter->drv_sds_rings = drv_sds_rings;
1478
1479         if (qlcnic_attach(adapter))
1480                 goto out;
1481
1482         if (netif_running(netdev))
1483                 __qlcnic_up(adapter, netdev);
1484
1485 out:
1486         netif_device_attach(netdev);
1487 }
1488
1489 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *adapter)
1490 {
1491         struct qlcnic_hardware_context *ahw = adapter->ahw;
1492         struct qlcnic_cmd_args cmd;
1493         u8 beacon_state;
1494         int err = 0;
1495
1496         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LED_CONFIG);
1497         if (!err) {
1498                 err = qlcnic_issue_cmd(adapter, &cmd);
1499                 if (!err) {
1500                         beacon_state = cmd.rsp.arg[4];
1501                         if (beacon_state == QLCNIC_BEACON_DISABLE)
1502                                 ahw->beacon_state = QLC_83XX_BEACON_OFF;
1503                         else if (beacon_state == QLC_83XX_ENABLE_BEACON)
1504                                 ahw->beacon_state = QLC_83XX_BEACON_ON;
1505                 }
1506         } else {
1507                 netdev_err(adapter->netdev, "Get beacon state failed, err=%d\n",
1508                            err);
1509         }
1510
1511         qlcnic_free_mbx_args(&cmd);
1512
1513         return;
1514 }
1515
1516 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1517                            u32 beacon)
1518 {
1519         struct qlcnic_cmd_args cmd;
1520         u32 mbx_in;
1521         int i, status = 0;
1522
1523         if (state) {
1524                 /* Get LED configuration */
1525                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1526                                                QLCNIC_CMD_GET_LED_CONFIG);
1527                 if (status)
1528                         return status;
1529
1530                 status = qlcnic_issue_cmd(adapter, &cmd);
1531                 if (status) {
1532                         dev_err(&adapter->pdev->dev,
1533                                 "Get led config failed.\n");
1534                         goto mbx_err;
1535                 } else {
1536                         for (i = 0; i < 4; i++)
1537                                 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1538                 }
1539                 qlcnic_free_mbx_args(&cmd);
1540                 /* Set LED Configuration */
1541                 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1542                           LSW(QLC_83XX_LED_CONFIG);
1543                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1544                                                QLCNIC_CMD_SET_LED_CONFIG);
1545                 if (status)
1546                         return status;
1547
1548                 cmd.req.arg[1] = mbx_in;
1549                 cmd.req.arg[2] = mbx_in;
1550                 cmd.req.arg[3] = mbx_in;
1551                 if (beacon)
1552                         cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1553                 status = qlcnic_issue_cmd(adapter, &cmd);
1554                 if (status) {
1555                         dev_err(&adapter->pdev->dev,
1556                                 "Set led config failed.\n");
1557                 }
1558 mbx_err:
1559                 qlcnic_free_mbx_args(&cmd);
1560                 return status;
1561
1562         } else {
1563                 /* Restoring default LED configuration */
1564                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1565                                                QLCNIC_CMD_SET_LED_CONFIG);
1566                 if (status)
1567                         return status;
1568
1569                 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1570                 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1571                 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1572                 if (beacon)
1573                         cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1574                 status = qlcnic_issue_cmd(adapter, &cmd);
1575                 if (status)
1576                         dev_err(&adapter->pdev->dev,
1577                                 "Restoring led config failed.\n");
1578                 qlcnic_free_mbx_args(&cmd);
1579                 return status;
1580         }
1581 }
1582
1583 int  qlcnic_83xx_set_led(struct net_device *netdev,
1584                          enum ethtool_phys_id_state state)
1585 {
1586         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1587         int err = -EIO, active = 1;
1588
1589         if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1590                 netdev_warn(netdev,
1591                             "LED test is not supported in non-privileged mode\n");
1592                 return -EOPNOTSUPP;
1593         }
1594
1595         switch (state) {
1596         case ETHTOOL_ID_ACTIVE:
1597                 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1598                         return -EBUSY;
1599
1600                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1601                         break;
1602
1603                 err = qlcnic_83xx_config_led(adapter, active, 0);
1604                 if (err)
1605                         netdev_err(netdev, "Failed to set LED blink state\n");
1606                 break;
1607         case ETHTOOL_ID_INACTIVE:
1608                 active = 0;
1609
1610                 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1611                         break;
1612
1613                 err = qlcnic_83xx_config_led(adapter, active, 0);
1614                 if (err)
1615                         netdev_err(netdev, "Failed to reset LED blink state\n");
1616                 break;
1617
1618         default:
1619                 return -EINVAL;
1620         }
1621
1622         if (!active || err)
1623                 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1624
1625         return err;
1626 }
1627
1628 void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *adapter, int enable)
1629 {
1630         struct qlcnic_cmd_args cmd;
1631         int status;
1632
1633         if (qlcnic_sriov_vf_check(adapter))
1634                 return;
1635
1636         if (enable)
1637                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1638                                                QLCNIC_CMD_INIT_NIC_FUNC);
1639         else
1640                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1641                                                QLCNIC_CMD_STOP_NIC_FUNC);
1642
1643         if (status)
1644                 return;
1645
1646         cmd.req.arg[1] = QLC_REGISTER_LB_IDC | QLC_INIT_FW_RESOURCES;
1647
1648         if (adapter->dcb)
1649                 cmd.req.arg[1] |= QLC_REGISTER_DCB_AEN;
1650
1651         status = qlcnic_issue_cmd(adapter, &cmd);
1652         if (status)
1653                 dev_err(&adapter->pdev->dev,
1654                         "Failed to %s in NIC IDC function event.\n",
1655                         (enable ? "register" : "unregister"));
1656
1657         qlcnic_free_mbx_args(&cmd);
1658 }
1659
1660 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1661 {
1662         struct qlcnic_cmd_args cmd;
1663         int err;
1664
1665         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1666         if (err)
1667                 return err;
1668
1669         cmd.req.arg[1] = adapter->ahw->port_config;
1670         err = qlcnic_issue_cmd(adapter, &cmd);
1671         if (err)
1672                 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1673         qlcnic_free_mbx_args(&cmd);
1674         return err;
1675 }
1676
1677 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1678 {
1679         struct qlcnic_cmd_args cmd;
1680         int err;
1681
1682         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1683         if (err)
1684                 return err;
1685
1686         err = qlcnic_issue_cmd(adapter, &cmd);
1687         if (err)
1688                 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1689         else
1690                 adapter->ahw->port_config = cmd.rsp.arg[1];
1691         qlcnic_free_mbx_args(&cmd);
1692         return err;
1693 }
1694
1695 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1696 {
1697         int err;
1698         u32 temp;
1699         struct qlcnic_cmd_args cmd;
1700
1701         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1702         if (err)
1703                 return err;
1704
1705         temp = adapter->recv_ctx->context_id << 16;
1706         cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1707         err = qlcnic_issue_cmd(adapter, &cmd);
1708         if (err)
1709                 dev_info(&adapter->pdev->dev,
1710                          "Setup linkevent mailbox failed\n");
1711         qlcnic_free_mbx_args(&cmd);
1712         return err;
1713 }
1714
1715 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1716                                                  u32 *interface_id)
1717 {
1718         if (qlcnic_sriov_pf_check(adapter)) {
1719                 qlcnic_alloc_lb_filters_mem(adapter);
1720                 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1721                 adapter->rx_mac_learn = true;
1722         } else {
1723                 if (!qlcnic_sriov_vf_check(adapter))
1724                         *interface_id = adapter->recv_ctx->context_id << 16;
1725         }
1726 }
1727
1728 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1729 {
1730         struct qlcnic_cmd_args *cmd = NULL;
1731         u32 temp = 0;
1732         int err;
1733
1734         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1735                 return -EIO;
1736
1737         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1738         if (!cmd)
1739                 return -ENOMEM;
1740
1741         err = qlcnic_alloc_mbx_args(cmd, adapter,
1742                                     QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1743         if (err)
1744                 goto out;
1745
1746         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1747         qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1748
1749         if (qlcnic_84xx_check(adapter) && qlcnic_sriov_pf_check(adapter))
1750                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1751
1752         cmd->req.arg[1] = mode | temp;
1753         err = qlcnic_issue_cmd(adapter, cmd);
1754         if (!err)
1755                 return err;
1756
1757         qlcnic_free_mbx_args(cmd);
1758
1759 out:
1760         kfree(cmd);
1761         return err;
1762 }
1763
1764 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1765 {
1766         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1767         struct qlcnic_hardware_context *ahw = adapter->ahw;
1768         u8 drv_sds_rings = adapter->drv_sds_rings;
1769         u8 drv_tx_rings = adapter->drv_tx_rings;
1770         int ret = 0, loop = 0;
1771
1772         if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1773                 netdev_warn(netdev,
1774                             "Loopback test not supported in non privileged mode\n");
1775                 return -ENOTSUPP;
1776         }
1777
1778         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1779                 netdev_info(netdev, "Device is resetting\n");
1780                 return -EBUSY;
1781         }
1782
1783         if (qlcnic_get_diag_lock(adapter)) {
1784                 netdev_info(netdev, "Device is in diagnostics mode\n");
1785                 return -EBUSY;
1786         }
1787
1788         netdev_info(netdev, "%s loopback test in progress\n",
1789                     mode == QLCNIC_ILB_MODE ? "internal" : "external");
1790
1791         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1792                                          drv_sds_rings);
1793         if (ret)
1794                 goto fail_diag_alloc;
1795
1796         ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1797         if (ret)
1798                 goto free_diag_res;
1799
1800         /* Poll for link up event before running traffic */
1801         do {
1802                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1803
1804                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1805                         netdev_info(netdev,
1806                                     "Device is resetting, free LB test resources\n");
1807                         ret = -EBUSY;
1808                         goto free_diag_res;
1809                 }
1810                 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1811                         netdev_info(netdev,
1812                                     "Firmware didn't sent link up event to loopback request\n");
1813                         ret = -ETIMEDOUT;
1814                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1815                         goto free_diag_res;
1816                 }
1817         } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1818
1819         ret = qlcnic_do_lb_test(adapter, mode);
1820
1821         qlcnic_83xx_clear_lb_mode(adapter, mode);
1822
1823 free_diag_res:
1824         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
1825
1826 fail_diag_alloc:
1827         adapter->drv_sds_rings = drv_sds_rings;
1828         adapter->drv_tx_rings = drv_tx_rings;
1829         qlcnic_release_diag_lock(adapter);
1830         return ret;
1831 }
1832
1833 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1834                                              u32 *max_wait_count)
1835 {
1836         struct qlcnic_hardware_context *ahw = adapter->ahw;
1837         int temp;
1838
1839         netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n",
1840                     ahw->extend_lb_time);
1841         temp = ahw->extend_lb_time * 1000;
1842         *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1843         ahw->extend_lb_time = 0;
1844 }
1845
1846 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1847 {
1848         struct qlcnic_hardware_context *ahw = adapter->ahw;
1849         struct net_device *netdev = adapter->netdev;
1850         u32 config, max_wait_count;
1851         int status = 0, loop = 0;
1852
1853         ahw->extend_lb_time = 0;
1854         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1855         status = qlcnic_83xx_get_port_config(adapter);
1856         if (status)
1857                 return status;
1858
1859         config = ahw->port_config;
1860
1861         /* Check if port is already in loopback mode */
1862         if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1863             (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1864                 netdev_err(netdev,
1865                            "Port already in Loopback mode.\n");
1866                 return -EINPROGRESS;
1867         }
1868
1869         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1870
1871         if (mode == QLCNIC_ILB_MODE)
1872                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1873         if (mode == QLCNIC_ELB_MODE)
1874                 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1875
1876         status = qlcnic_83xx_set_port_config(adapter);
1877         if (status) {
1878                 netdev_err(netdev,
1879                            "Failed to Set Loopback Mode = 0x%x.\n",
1880                            ahw->port_config);
1881                 ahw->port_config = config;
1882                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1883                 return status;
1884         }
1885
1886         /* Wait for Link and IDC Completion AEN */
1887         do {
1888                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1889
1890                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1891                         netdev_info(netdev,
1892                                     "Device is resetting, free LB test resources\n");
1893                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1894                         return -EBUSY;
1895                 }
1896
1897                 if (ahw->extend_lb_time)
1898                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1899                                                          &max_wait_count);
1900
1901                 if (loop++ > max_wait_count) {
1902                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1903                                    __func__);
1904                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1905                         qlcnic_83xx_clear_lb_mode(adapter, mode);
1906                         return -ETIMEDOUT;
1907                 }
1908         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1909
1910         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1911                                   QLCNIC_MAC_ADD);
1912         return status;
1913 }
1914
1915 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1916 {
1917         struct qlcnic_hardware_context *ahw = adapter->ahw;
1918         u32 config = ahw->port_config, max_wait_count;
1919         struct net_device *netdev = adapter->netdev;
1920         int status = 0, loop = 0;
1921
1922         ahw->extend_lb_time = 0;
1923         max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1924         set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1925         if (mode == QLCNIC_ILB_MODE)
1926                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1927         if (mode == QLCNIC_ELB_MODE)
1928                 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1929
1930         status = qlcnic_83xx_set_port_config(adapter);
1931         if (status) {
1932                 netdev_err(netdev,
1933                            "Failed to Clear Loopback Mode = 0x%x.\n",
1934                            ahw->port_config);
1935                 ahw->port_config = config;
1936                 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1937                 return status;
1938         }
1939
1940         /* Wait for Link and IDC Completion AEN */
1941         do {
1942                 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1943
1944                 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1945                         netdev_info(netdev,
1946                                     "Device is resetting, free LB test resources\n");
1947                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1948                         return -EBUSY;
1949                 }
1950
1951                 if (ahw->extend_lb_time)
1952                         qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1953                                                          &max_wait_count);
1954
1955                 if (loop++ > max_wait_count) {
1956                         netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1957                                    __func__);
1958                         clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1959                         return -ETIMEDOUT;
1960                 }
1961         } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1962
1963         qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1964                                   QLCNIC_MAC_DEL);
1965         return status;
1966 }
1967
1968 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1969                                                 u32 *interface_id)
1970 {
1971         if (qlcnic_sriov_pf_check(adapter)) {
1972                 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1973         } else {
1974                 if (!qlcnic_sriov_vf_check(adapter))
1975                         *interface_id = adapter->recv_ctx->context_id << 16;
1976         }
1977 }
1978
1979 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1980                                int mode)
1981 {
1982         int err;
1983         u32 temp = 0, temp_ip;
1984         struct qlcnic_cmd_args cmd;
1985
1986         err = qlcnic_alloc_mbx_args(&cmd, adapter,
1987                                     QLCNIC_CMD_CONFIGURE_IP_ADDR);
1988         if (err)
1989                 return;
1990
1991         qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1992
1993         if (mode == QLCNIC_IP_UP)
1994                 cmd.req.arg[1] = 1 | temp;
1995         else
1996                 cmd.req.arg[1] = 2 | temp;
1997
1998         /*
1999          * Adapter needs IP address in network byte order.
2000          * But hardware mailbox registers go through writel(), hence IP address
2001          * gets swapped on big endian architecture.
2002          * To negate swapping of writel() on big endian architecture
2003          * use swab32(value).
2004          */
2005
2006         temp_ip = swab32(ntohl(ip));
2007         memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
2008         err = qlcnic_issue_cmd(adapter, &cmd);
2009         if (err != QLCNIC_RCODE_SUCCESS)
2010                 dev_err(&adapter->netdev->dev,
2011                         "could not notify %s IP 0x%x request\n",
2012                         (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
2013
2014         qlcnic_free_mbx_args(&cmd);
2015 }
2016
2017 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
2018 {
2019         int err;
2020         u32 temp, arg1;
2021         struct qlcnic_cmd_args cmd;
2022         int lro_bit_mask;
2023
2024         lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
2025
2026         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2027                 return 0;
2028
2029         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
2030         if (err)
2031                 return err;
2032
2033         temp = adapter->recv_ctx->context_id << 16;
2034         arg1 = lro_bit_mask | temp;
2035         cmd.req.arg[1] = arg1;
2036
2037         err = qlcnic_issue_cmd(adapter, &cmd);
2038         if (err)
2039                 dev_info(&adapter->pdev->dev, "LRO config failed\n");
2040         qlcnic_free_mbx_args(&cmd);
2041
2042         return err;
2043 }
2044
2045 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
2046 {
2047         int err;
2048         u32 word;
2049         struct qlcnic_cmd_args cmd;
2050         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
2051                             0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
2052                             0x255b0ec26d5a56daULL };
2053
2054         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
2055         if (err)
2056                 return err;
2057         /*
2058          * RSS request:
2059          * bits 3-0: Rsvd
2060          *      5-4: hash_type_ipv4
2061          *      7-6: hash_type_ipv6
2062          *        8: enable
2063          *        9: use indirection table
2064          *    16-31: indirection table mask
2065          */
2066         word =  ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
2067                 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
2068                 ((u32)(enable & 0x1) << 8) |
2069                 ((0x7ULL) << 16);
2070         cmd.req.arg[1] = (adapter->recv_ctx->context_id);
2071         cmd.req.arg[2] = word;
2072         memcpy(&cmd.req.arg[4], key, sizeof(key));
2073
2074         err = qlcnic_issue_cmd(adapter, &cmd);
2075
2076         if (err)
2077                 dev_info(&adapter->pdev->dev, "RSS config failed\n");
2078         qlcnic_free_mbx_args(&cmd);
2079
2080         return err;
2081
2082 }
2083
2084 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
2085                                                  u32 *interface_id)
2086 {
2087         if (qlcnic_sriov_pf_check(adapter)) {
2088                 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
2089         } else {
2090                 if (!qlcnic_sriov_vf_check(adapter))
2091                         *interface_id = adapter->recv_ctx->context_id << 16;
2092         }
2093 }
2094
2095 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
2096                                    u16 vlan_id, u8 op)
2097 {
2098         struct qlcnic_cmd_args *cmd = NULL;
2099         struct qlcnic_macvlan_mbx mv;
2100         u32 *buf, temp = 0;
2101         int err;
2102
2103         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2104                 return -EIO;
2105
2106         cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
2107         if (!cmd)
2108                 return -ENOMEM;
2109
2110         err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
2111         if (err)
2112                 goto out;
2113
2114         cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
2115
2116         if (vlan_id)
2117                 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
2118                      QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
2119
2120         cmd->req.arg[1] = op | (1 << 8);
2121         qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
2122         cmd->req.arg[1] |= temp;
2123         mv.vlan = vlan_id;
2124         mv.mac_addr0 = addr[0];
2125         mv.mac_addr1 = addr[1];
2126         mv.mac_addr2 = addr[2];
2127         mv.mac_addr3 = addr[3];
2128         mv.mac_addr4 = addr[4];
2129         mv.mac_addr5 = addr[5];
2130         buf = &cmd->req.arg[2];
2131         memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
2132         err = qlcnic_issue_cmd(adapter, cmd);
2133         if (!err)
2134                 return err;
2135
2136         qlcnic_free_mbx_args(cmd);
2137 out:
2138         kfree(cmd);
2139         return err;
2140 }
2141
2142 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
2143                                   u16 vlan_id,
2144                                   struct qlcnic_host_tx_ring *tx_ring)
2145 {
2146         u8 mac[ETH_ALEN];
2147         memcpy(&mac, addr, ETH_ALEN);
2148         qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2149 }
2150
2151 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2152                                       u8 type, struct qlcnic_cmd_args *cmd)
2153 {
2154         switch (type) {
2155         case QLCNIC_SET_STATION_MAC:
2156         case QLCNIC_SET_FAC_DEF_MAC:
2157                 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2158                 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2159                 break;
2160         }
2161         cmd->req.arg[1] = type;
2162 }
2163
2164 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2165                                 u8 function)
2166 {
2167         int err, i;
2168         struct qlcnic_cmd_args cmd;
2169         u32 mac_low, mac_high;
2170
2171         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2172         if (err)
2173                 return err;
2174
2175         qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2176         err = qlcnic_issue_cmd(adapter, &cmd);
2177
2178         if (err == QLCNIC_RCODE_SUCCESS) {
2179                 mac_low = cmd.rsp.arg[1];
2180                 mac_high = cmd.rsp.arg[2];
2181
2182                 for (i = 0; i < 2; i++)
2183                         mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2184                 for (i = 2; i < 6; i++)
2185                         mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2186         } else {
2187                 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2188                         err);
2189                 err = -EIO;
2190         }
2191         qlcnic_free_mbx_args(&cmd);
2192         return err;
2193 }
2194
2195 static int qlcnic_83xx_set_rx_intr_coal(struct qlcnic_adapter *adapter)
2196 {
2197         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2198         struct qlcnic_cmd_args cmd;
2199         u16 temp;
2200         int err;
2201
2202         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2203         if (err)
2204                 return err;
2205
2206         temp = adapter->recv_ctx->context_id;
2207         cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2208         temp = coal->rx_time_us;
2209         cmd.req.arg[2] = coal->rx_packets | temp << 16;
2210         cmd.req.arg[3] = coal->flag;
2211
2212         err = qlcnic_issue_cmd(adapter, &cmd);
2213         if (err != QLCNIC_RCODE_SUCCESS)
2214                 netdev_err(adapter->netdev,
2215                            "failed to set interrupt coalescing parameters\n");
2216
2217         qlcnic_free_mbx_args(&cmd);
2218
2219         return err;
2220 }
2221
2222 static int qlcnic_83xx_set_tx_intr_coal(struct qlcnic_adapter *adapter)
2223 {
2224         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2225         struct qlcnic_cmd_args cmd;
2226         u16 temp;
2227         int err;
2228
2229         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2230         if (err)
2231                 return err;
2232
2233         temp = adapter->tx_ring->ctx_id;
2234         cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2235         temp = coal->tx_time_us;
2236         cmd.req.arg[2] = coal->tx_packets | temp << 16;
2237         cmd.req.arg[3] = coal->flag;
2238
2239         err = qlcnic_issue_cmd(adapter, &cmd);
2240         if (err != QLCNIC_RCODE_SUCCESS)
2241                 netdev_err(adapter->netdev,
2242                            "failed to set interrupt coalescing  parameters\n");
2243
2244         qlcnic_free_mbx_args(&cmd);
2245
2246         return err;
2247 }
2248
2249 int qlcnic_83xx_set_rx_tx_intr_coal(struct qlcnic_adapter *adapter)
2250 {
2251         int err = 0;
2252
2253         err = qlcnic_83xx_set_rx_intr_coal(adapter);
2254         if (err)
2255                 netdev_err(adapter->netdev,
2256                            "failed to set Rx coalescing parameters\n");
2257
2258         err = qlcnic_83xx_set_tx_intr_coal(adapter);
2259         if (err)
2260                 netdev_err(adapter->netdev,
2261                            "failed to set Tx coalescing parameters\n");
2262
2263         return err;
2264 }
2265
2266 int qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter,
2267                                  struct ethtool_coalesce *ethcoal)
2268 {
2269         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2270         u32 rx_coalesce_usecs, rx_max_frames;
2271         u32 tx_coalesce_usecs, tx_max_frames;
2272         int err;
2273
2274         if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2275                 return -EIO;
2276
2277         tx_coalesce_usecs = ethcoal->tx_coalesce_usecs;
2278         tx_max_frames = ethcoal->tx_max_coalesced_frames;
2279         rx_coalesce_usecs = ethcoal->rx_coalesce_usecs;
2280         rx_max_frames = ethcoal->rx_max_coalesced_frames;
2281         coal->flag = QLCNIC_INTR_DEFAULT;
2282
2283         if ((coal->rx_time_us == rx_coalesce_usecs) &&
2284             (coal->rx_packets == rx_max_frames)) {
2285                 coal->type = QLCNIC_INTR_COAL_TYPE_TX;
2286                 coal->tx_time_us = tx_coalesce_usecs;
2287                 coal->tx_packets = tx_max_frames;
2288         } else if ((coal->tx_time_us == tx_coalesce_usecs) &&
2289                    (coal->tx_packets == tx_max_frames)) {
2290                 coal->type = QLCNIC_INTR_COAL_TYPE_RX;
2291                 coal->rx_time_us = rx_coalesce_usecs;
2292                 coal->rx_packets = rx_max_frames;
2293         } else {
2294                 coal->type = QLCNIC_INTR_COAL_TYPE_RX_TX;
2295                 coal->rx_time_us = rx_coalesce_usecs;
2296                 coal->rx_packets = rx_max_frames;
2297                 coal->tx_time_us = tx_coalesce_usecs;
2298                 coal->tx_packets = tx_max_frames;
2299         }
2300
2301         switch (coal->type) {
2302         case QLCNIC_INTR_COAL_TYPE_RX:
2303                 err = qlcnic_83xx_set_rx_intr_coal(adapter);
2304                 break;
2305         case QLCNIC_INTR_COAL_TYPE_TX:
2306                 err = qlcnic_83xx_set_tx_intr_coal(adapter);
2307                 break;
2308         case QLCNIC_INTR_COAL_TYPE_RX_TX:
2309                 err = qlcnic_83xx_set_rx_tx_intr_coal(adapter);
2310                 break;
2311         default:
2312                 err = -EINVAL;
2313                 netdev_err(adapter->netdev,
2314                            "Invalid Interrupt coalescing type\n");
2315                 break;
2316         }
2317
2318         return err;
2319 }
2320
2321 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2322                                         u32 data[])
2323 {
2324         struct qlcnic_hardware_context *ahw = adapter->ahw;
2325         u8 link_status, duplex;
2326         /* link speed */
2327         link_status = LSB(data[3]) & 1;
2328         if (link_status) {
2329                 ahw->link_speed = MSW(data[2]);
2330                 duplex = LSB(MSW(data[3]));
2331                 if (duplex)
2332                         ahw->link_duplex = DUPLEX_FULL;
2333                 else
2334                         ahw->link_duplex = DUPLEX_HALF;
2335         } else {
2336                 ahw->link_speed = SPEED_UNKNOWN;
2337                 ahw->link_duplex = DUPLEX_UNKNOWN;
2338         }
2339
2340         ahw->link_autoneg = MSB(MSW(data[3]));
2341         ahw->module_type = MSB(LSW(data[3]));
2342         ahw->has_link_events = 1;
2343         ahw->lb_mode = data[4] & QLCNIC_LB_MODE_MASK;
2344         qlcnic_advert_link_change(adapter, link_status);
2345 }
2346
2347 static irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2348 {
2349         u32 mask, resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
2350         struct qlcnic_adapter *adapter = data;
2351         struct qlcnic_mailbox *mbx;
2352         unsigned long flags;
2353
2354         mbx = adapter->ahw->mailbox;
2355         spin_lock_irqsave(&mbx->aen_lock, flags);
2356         resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2357         if (!(resp & QLCNIC_SET_OWNER))
2358                 goto out;
2359
2360         event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2361         if (event &  QLCNIC_MBX_ASYNC_EVENT) {
2362                 __qlcnic_83xx_process_aen(adapter);
2363         } else {
2364                 if (mbx->rsp_status != rsp_status)
2365                         qlcnic_83xx_notify_mbx_response(mbx);
2366                 else
2367                         adapter->stats.mbx_spurious_intr++;
2368         }
2369
2370 out:
2371         mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2372         writel(0, adapter->ahw->pci_base0 + mask);
2373         spin_unlock_irqrestore(&mbx->aen_lock, flags);
2374         return IRQ_HANDLED;
2375 }
2376
2377 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2378                              struct qlcnic_info *nic)
2379 {
2380         int i, err = -EIO;
2381         struct qlcnic_cmd_args cmd;
2382
2383         if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2384                 dev_err(&adapter->pdev->dev,
2385                         "%s: Error, invoked by non management func\n",
2386                         __func__);
2387                 return err;
2388         }
2389
2390         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2391         if (err)
2392                 return err;
2393
2394         cmd.req.arg[1] = (nic->pci_func << 16);
2395         cmd.req.arg[2] = 0x1 << 16;
2396         cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2397         cmd.req.arg[4] = nic->capabilities;
2398         cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2399         cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2400         cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2401         for (i = 8; i < 32; i++)
2402                 cmd.req.arg[i] = 0;
2403
2404         err = qlcnic_issue_cmd(adapter, &cmd);
2405
2406         if (err != QLCNIC_RCODE_SUCCESS) {
2407                 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2408                         err);
2409                 err = -EIO;
2410         }
2411
2412         qlcnic_free_mbx_args(&cmd);
2413
2414         return err;
2415 }
2416
2417 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2418                              struct qlcnic_info *npar_info, u8 func_id)
2419 {
2420         int err;
2421         u32 temp;
2422         u8 op = 0;
2423         struct qlcnic_cmd_args cmd;
2424         struct qlcnic_hardware_context *ahw = adapter->ahw;
2425
2426         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2427         if (err)
2428                 return err;
2429
2430         if (func_id != ahw->pci_func) {
2431                 temp = func_id << 16;
2432                 cmd.req.arg[1] = op | BIT_31 | temp;
2433         } else {
2434                 cmd.req.arg[1] = ahw->pci_func << 16;
2435         }
2436         err = qlcnic_issue_cmd(adapter, &cmd);
2437         if (err) {
2438                 dev_info(&adapter->pdev->dev,
2439                          "Failed to get nic info %d\n", err);
2440                 goto out;
2441         }
2442
2443         npar_info->op_type = cmd.rsp.arg[1];
2444         npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2445         npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2446         npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2447         npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2448         npar_info->capabilities = cmd.rsp.arg[4];
2449         npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2450         npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2451         npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2452         npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2453         npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2454         npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2455         if (cmd.rsp.arg[8] & 0x1)
2456                 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2457         if (cmd.rsp.arg[8] & 0x10000) {
2458                 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2459                 npar_info->max_linkspeed_reg_offset = temp;
2460         }
2461
2462         memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2463                sizeof(ahw->extra_capability));
2464
2465 out:
2466         qlcnic_free_mbx_args(&cmd);
2467         return err;
2468 }
2469
2470 int qlcnic_get_pci_func_type(struct qlcnic_adapter *adapter, u16 type,
2471                              u16 *nic, u16 *fcoe, u16 *iscsi)
2472 {
2473         struct device *dev = &adapter->pdev->dev;
2474         int err = 0;
2475
2476         switch (type) {
2477         case QLCNIC_TYPE_NIC:
2478                 (*nic)++;
2479                 break;
2480         case QLCNIC_TYPE_FCOE:
2481                 (*fcoe)++;
2482                 break;
2483         case QLCNIC_TYPE_ISCSI:
2484                 (*iscsi)++;
2485                 break;
2486         default:
2487                 dev_err(dev, "%s: Unknown PCI type[%x]\n",
2488                         __func__, type);
2489                 err = -EIO;
2490         }
2491
2492         return err;
2493 }
2494
2495 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2496                              struct qlcnic_pci_info *pci_info)
2497 {
2498         struct qlcnic_hardware_context *ahw = adapter->ahw;
2499         struct device *dev = &adapter->pdev->dev;
2500         u16 nic = 0, fcoe = 0, iscsi = 0;
2501         struct qlcnic_cmd_args cmd;
2502         int i, err = 0, j = 0;
2503         u32 temp;
2504
2505         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2506         if (err)
2507                 return err;
2508
2509         err = qlcnic_issue_cmd(adapter, &cmd);
2510
2511         ahw->total_nic_func = 0;
2512         if (err == QLCNIC_RCODE_SUCCESS) {
2513                 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2514                 for (i = 2, j = 0; j < ahw->max_vnic_func; j++, pci_info++) {
2515                         pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2516                         pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2517                         i++;
2518                         if (!pci_info->active) {
2519                                 i += QLC_SKIP_INACTIVE_PCI_REGS;
2520                                 continue;
2521                         }
2522                         pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2523                         err = qlcnic_get_pci_func_type(adapter, pci_info->type,
2524                                                        &nic, &fcoe, &iscsi);
2525                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2526                         pci_info->default_port = temp;
2527                         i++;
2528                         pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2529                         temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2530                         pci_info->tx_max_bw = temp;
2531                         i = i + 2;
2532                         memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2533                         i++;
2534                         memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2535                         i = i + 3;
2536                 }
2537         } else {
2538                 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2539                 err = -EIO;
2540         }
2541
2542         ahw->total_nic_func = nic;
2543         ahw->total_pci_func = nic + fcoe + iscsi;
2544         if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) {
2545                 dev_err(dev, "%s: Invalid function count: total nic func[%x], total pci func[%x]\n",
2546                         __func__, ahw->total_nic_func, ahw->total_pci_func);
2547                 err = -EIO;
2548         }
2549         qlcnic_free_mbx_args(&cmd);
2550
2551         return err;
2552 }
2553
2554 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2555 {
2556         int i, index, err;
2557         u8 max_ints;
2558         u32 val, temp, type;
2559         struct qlcnic_cmd_args cmd;
2560
2561         max_ints = adapter->ahw->num_msix - 1;
2562         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2563         if (err)
2564                 return err;
2565
2566         cmd.req.arg[1] = max_ints;
2567
2568         if (qlcnic_sriov_vf_check(adapter))
2569                 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2570
2571         for (i = 0, index = 2; i < max_ints; i++) {
2572                 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2573                 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2574                 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2575                         val |= (adapter->ahw->intr_tbl[i].id << 16);
2576                 cmd.req.arg[index++] = val;
2577         }
2578         err = qlcnic_issue_cmd(adapter, &cmd);
2579         if (err) {
2580                 dev_err(&adapter->pdev->dev,
2581                         "Failed to configure interrupts 0x%x\n", err);
2582                 goto out;
2583         }
2584
2585         max_ints = cmd.rsp.arg[1];
2586         for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2587                 val = cmd.rsp.arg[index];
2588                 if (LSB(val)) {
2589                         dev_info(&adapter->pdev->dev,
2590                                  "Can't configure interrupt %d\n",
2591                                  adapter->ahw->intr_tbl[i].id);
2592                         continue;
2593                 }
2594                 if (op_type) {
2595                         adapter->ahw->intr_tbl[i].id = MSW(val);
2596                         adapter->ahw->intr_tbl[i].enabled = 1;
2597                         temp = cmd.rsp.arg[index + 1];
2598                         adapter->ahw->intr_tbl[i].src = temp;
2599                 } else {
2600                         adapter->ahw->intr_tbl[i].id = i;
2601                         adapter->ahw->intr_tbl[i].enabled = 0;
2602                         adapter->ahw->intr_tbl[i].src = 0;
2603                 }
2604         }
2605 out:
2606         qlcnic_free_mbx_args(&cmd);
2607         return err;
2608 }
2609
2610 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2611 {
2612         int id, timeout = 0;
2613         u32 status = 0;
2614
2615         while (status == 0) {
2616                 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2617                 if (status)
2618                         break;
2619
2620                 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2621                         id = QLC_SHARED_REG_RD32(adapter,
2622                                                  QLCNIC_FLASH_LOCK_OWNER);
2623                         dev_err(&adapter->pdev->dev,
2624                                 "%s: failed, lock held by %d\n", __func__, id);
2625                         return -EIO;
2626                 }
2627                 usleep_range(1000, 2000);
2628         }
2629
2630         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2631         return 0;
2632 }
2633
2634 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2635 {
2636         QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2637         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2638 }
2639
2640 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2641                                       u32 flash_addr, u8 *p_data,
2642                                       int count)
2643 {
2644         u32 word, range, flash_offset, addr = flash_addr, ret;
2645         ulong indirect_add, direct_window;
2646         int i, err = 0;
2647
2648         flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2649         if (addr & 0x3) {
2650                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2651                 return -EIO;
2652         }
2653
2654         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2655                                      (addr & 0xFFFF0000));
2656
2657         range = flash_offset + (count * sizeof(u32));
2658         /* Check if data is spread across multiple sectors */
2659         if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2660
2661                 /* Multi sector read */
2662                 for (i = 0; i < count; i++) {
2663                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2664                         ret = QLCRD32(adapter, indirect_add, &err);
2665                         if (err == -EIO)
2666                                 return err;
2667
2668                         word = ret;
2669                         *(u32 *)p_data  = word;
2670                         p_data = p_data + 4;
2671                         addr = addr + 4;
2672                         flash_offset = flash_offset + 4;
2673
2674                         if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2675                                 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2676                                 /* This write is needed once for each sector */
2677                                 qlcnic_83xx_wrt_reg_indirect(adapter,
2678                                                              direct_window,
2679                                                              (addr));
2680                                 flash_offset = 0;
2681                         }
2682                 }
2683         } else {
2684                 /* Single sector read */
2685                 for (i = 0; i < count; i++) {
2686                         indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2687                         ret = QLCRD32(adapter, indirect_add, &err);
2688                         if (err == -EIO)
2689                                 return err;
2690
2691                         word = ret;
2692                         *(u32 *)p_data  = word;
2693                         p_data = p_data + 4;
2694                         addr = addr + 4;
2695                 }
2696         }
2697
2698         return 0;
2699 }
2700
2701 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2702 {
2703         u32 status;
2704         int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2705         int err = 0;
2706
2707         do {
2708                 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2709                 if (err == -EIO)
2710                         return err;
2711
2712                 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2713                     QLC_83XX_FLASH_STATUS_READY)
2714                         break;
2715
2716                 usleep_range(1000, 1100);
2717         } while (--retries);
2718
2719         if (!retries)
2720                 return -EIO;
2721
2722         return 0;
2723 }
2724
2725 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2726 {
2727         int ret;
2728         u32 cmd;
2729         cmd = adapter->ahw->fdt.write_statusreg_cmd;
2730         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2731                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2732         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2733                                      adapter->ahw->fdt.write_enable_bits);
2734         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2735                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2736         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2737         if (ret)
2738                 return -EIO;
2739
2740         return 0;
2741 }
2742
2743 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2744 {
2745         int ret;
2746
2747         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2748                                      (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2749                                      adapter->ahw->fdt.write_statusreg_cmd));
2750         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2751                                      adapter->ahw->fdt.write_disable_bits);
2752         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2753                                      QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2754         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2755         if (ret)
2756                 return -EIO;
2757
2758         return 0;
2759 }
2760
2761 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2762 {
2763         int ret, err = 0;
2764         u32 mfg_id;
2765
2766         if (qlcnic_83xx_lock_flash(adapter))
2767                 return -EIO;
2768
2769         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2770                                      QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2771         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2772                                      QLC_83XX_FLASH_READ_CTRL);
2773         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2774         if (ret) {
2775                 qlcnic_83xx_unlock_flash(adapter);
2776                 return -EIO;
2777         }
2778
2779         mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2780         if (err == -EIO) {
2781                 qlcnic_83xx_unlock_flash(adapter);
2782                 return err;
2783         }
2784
2785         adapter->flash_mfg_id = (mfg_id & 0xFF);
2786         qlcnic_83xx_unlock_flash(adapter);
2787
2788         return 0;
2789 }
2790
2791 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2792 {
2793         int count, fdt_size, ret = 0;
2794
2795         fdt_size = sizeof(struct qlcnic_fdt);
2796         count = fdt_size / sizeof(u32);
2797
2798         if (qlcnic_83xx_lock_flash(adapter))
2799                 return -EIO;
2800
2801         memset(&adapter->ahw->fdt, 0, fdt_size);
2802         ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2803                                                 (u8 *)&adapter->ahw->fdt,
2804                                                 count);
2805         qlcnic_swap32_buffer((u32 *)&adapter->ahw->fdt, count);
2806         qlcnic_83xx_unlock_flash(adapter);
2807         return ret;
2808 }
2809
2810 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2811                                    u32 sector_start_addr)
2812 {
2813         u32 reversed_addr, addr1, addr2, cmd;
2814         int ret = -EIO;
2815
2816         if (qlcnic_83xx_lock_flash(adapter) != 0)
2817                 return -EIO;
2818
2819         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2820                 ret = qlcnic_83xx_enable_flash_write(adapter);
2821                 if (ret) {
2822                         qlcnic_83xx_unlock_flash(adapter);
2823                         dev_err(&adapter->pdev->dev,
2824                                 "%s failed at %d\n",
2825                                 __func__, __LINE__);
2826                         return ret;
2827                 }
2828         }
2829
2830         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2831         if (ret) {
2832                 qlcnic_83xx_unlock_flash(adapter);
2833                 dev_err(&adapter->pdev->dev,
2834                         "%s: failed at %d\n", __func__, __LINE__);
2835                 return -EIO;
2836         }
2837
2838         addr1 = (sector_start_addr & 0xFF) << 16;
2839         addr2 = (sector_start_addr & 0xFF0000) >> 16;
2840         reversed_addr = addr1 | addr2 | (sector_start_addr & 0xFF00);
2841
2842         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2843                                      reversed_addr);
2844         cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2845         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2846                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2847         else
2848                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2849                                              QLC_83XX_FLASH_OEM_ERASE_SIG);
2850         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2851                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2852
2853         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2854         if (ret) {
2855                 qlcnic_83xx_unlock_flash(adapter);
2856                 dev_err(&adapter->pdev->dev,
2857                         "%s: failed at %d\n", __func__, __LINE__);
2858                 return -EIO;
2859         }
2860
2861         if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2862                 ret = qlcnic_83xx_disable_flash_write(adapter);
2863                 if (ret) {
2864                         qlcnic_83xx_unlock_flash(adapter);
2865                         dev_err(&adapter->pdev->dev,
2866                                 "%s: failed at %d\n", __func__, __LINE__);
2867                         return ret;
2868                 }
2869         }
2870
2871         qlcnic_83xx_unlock_flash(adapter);
2872
2873         return 0;
2874 }
2875
2876 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2877                               u32 *p_data)
2878 {
2879         int ret = -EIO;
2880         u32 addr1 = 0x00800000 | (addr >> 2);
2881
2882         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2883         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2884         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2885                                      QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2886         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2887         if (ret) {
2888                 dev_err(&adapter->pdev->dev,
2889                         "%s: failed at %d\n", __func__, __LINE__);
2890                 return -EIO;
2891         }
2892
2893         return 0;
2894 }
2895
2896 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2897                                  u32 *p_data, int count)
2898 {
2899         u32 temp;
2900         int ret = -EIO, err = 0;
2901
2902         if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2903             (count > QLC_83XX_FLASH_WRITE_MAX)) {
2904                 dev_err(&adapter->pdev->dev,
2905                         "%s: Invalid word count\n", __func__);
2906                 return -EIO;
2907         }
2908
2909         temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2910         if (err == -EIO)
2911                 return err;
2912
2913         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2914                                      (temp | QLC_83XX_FLASH_SPI_CTRL));
2915         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2916                                      QLC_83XX_FLASH_ADDR_TEMP_VAL);
2917
2918         /* First DWORD write */
2919         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2920         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2921                                      QLC_83XX_FLASH_FIRST_MS_PATTERN);
2922         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2923         if (ret) {
2924                 dev_err(&adapter->pdev->dev,
2925                         "%s: failed at %d\n", __func__, __LINE__);
2926                 return -EIO;
2927         }
2928
2929         count--;
2930         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2931                                      QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2932         /* Second to N-1 DWORD writes */
2933         while (count != 1) {
2934                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2935                                              *p_data++);
2936                 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2937                                              QLC_83XX_FLASH_SECOND_MS_PATTERN);
2938                 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2939                 if (ret) {
2940                         dev_err(&adapter->pdev->dev,
2941                                 "%s: failed at %d\n", __func__, __LINE__);
2942                         return -EIO;
2943                 }
2944                 count--;
2945         }
2946
2947         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2948                                      QLC_83XX_FLASH_ADDR_TEMP_VAL |
2949                                      (addr >> 2));
2950         /* Last DWORD write */
2951         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2952         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2953                                      QLC_83XX_FLASH_LAST_MS_PATTERN);
2954         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2955         if (ret) {
2956                 dev_err(&adapter->pdev->dev,
2957                         "%s: failed at %d\n", __func__, __LINE__);
2958                 return -EIO;
2959         }
2960
2961         ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2962         if (err == -EIO)
2963                 return err;
2964
2965         if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2966                 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2967                         __func__, __LINE__);
2968                 /* Operation failed, clear error bit */
2969                 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2970                 if (err == -EIO)
2971                         return err;
2972
2973                 qlcnic_83xx_wrt_reg_indirect(adapter,
2974                                              QLC_83XX_FLASH_SPI_CONTROL,
2975                                              (temp | QLC_83XX_FLASH_SPI_CTRL));
2976         }
2977
2978         return 0;
2979 }
2980
2981 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2982 {
2983         u32 val, id;
2984
2985         val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2986
2987         /* Check if recovery need to be performed by the calling function */
2988         if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2989                 val = val & ~0x3F;
2990                 val = val | ((adapter->portnum << 2) |
2991                              QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2992                 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2993                 dev_info(&adapter->pdev->dev,
2994                          "%s: lock recovery initiated\n", __func__);
2995                 mdelay(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2996                 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2997                 id = ((val >> 2) & 0xF);
2998                 if (id == adapter->portnum) {
2999                         val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
3000                         val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
3001                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
3002                         /* Force release the lock */
3003                         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
3004                         /* Clear recovery bits */
3005                         val = val & ~0x3F;
3006                         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
3007                         dev_info(&adapter->pdev->dev,
3008                                  "%s: lock recovery completed\n", __func__);
3009                 } else {
3010                         dev_info(&adapter->pdev->dev,
3011                                  "%s: func %d to resume lock recovery process\n",
3012                                  __func__, id);
3013                 }
3014         } else {
3015                 dev_info(&adapter->pdev->dev,
3016                          "%s: lock recovery initiated by other functions\n",
3017                          __func__);
3018         }
3019 }
3020
3021 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
3022 {
3023         u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
3024         int max_attempt = 0;
3025
3026         while (status == 0) {
3027                 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
3028                 if (status)
3029                         break;
3030
3031                 mdelay(QLC_83XX_DRV_LOCK_WAIT_DELAY);
3032                 i++;
3033
3034                 if (i == 1)
3035                         temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3036
3037                 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
3038                         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3039                         if (val == temp) {
3040                                 id = val & 0xFF;
3041                                 dev_info(&adapter->pdev->dev,
3042                                          "%s: lock to be recovered from %d\n",
3043                                          __func__, id);
3044                                 qlcnic_83xx_recover_driver_lock(adapter);
3045                                 i = 0;
3046                                 max_attempt++;
3047                         } else {
3048                                 dev_err(&adapter->pdev->dev,
3049                                         "%s: failed to get lock\n", __func__);
3050                                 return -EIO;
3051                         }
3052                 }
3053
3054                 /* Force exit from while loop after few attempts */
3055                 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
3056                         dev_err(&adapter->pdev->dev,
3057                                 "%s: failed to get lock\n", __func__);
3058                         return -EIO;
3059                 }
3060         }
3061
3062         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3063         lock_alive_counter = val >> 8;
3064         lock_alive_counter++;
3065         val = lock_alive_counter << 8 | adapter->portnum;
3066         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
3067
3068         return 0;
3069 }
3070
3071 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
3072 {
3073         u32 val, lock_alive_counter, id;
3074
3075         val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3076         id = val & 0xFF;
3077         lock_alive_counter = val >> 8;
3078
3079         if (id != adapter->portnum)
3080                 dev_err(&adapter->pdev->dev,
3081                         "%s:Warning func %d is unlocking lock owned by %d\n",
3082                         __func__, adapter->portnum, id);
3083
3084         val = (lock_alive_counter << 8) | 0xFF;
3085         QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
3086         QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
3087 }
3088
3089 int qlcnic_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
3090                                 u32 *data, u32 count)
3091 {
3092         int i, j, ret = 0;
3093         u32 temp;
3094
3095         /* Check alignment */
3096         if (addr & 0xF)
3097                 return -EIO;
3098
3099         mutex_lock(&adapter->ahw->mem_lock);
3100         qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_HI, 0);
3101
3102         for (i = 0; i < count; i++, addr += 16) {
3103                 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
3104                                      QLCNIC_ADDR_QDR_NET_MAX)) ||
3105                       (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
3106                                      QLCNIC_ADDR_DDR_NET_MAX)))) {
3107                         mutex_unlock(&adapter->ahw->mem_lock);
3108                         return -EIO;
3109                 }
3110
3111                 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_LO, addr);
3112                 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_LO, *data++);
3113                 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_HI, *data++);
3114                 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_ULO, *data++);
3115                 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_UHI, *data++);
3116                 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_WRITE_ENABLE);
3117                 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_WRITE_START);
3118
3119                 for (j = 0; j < MAX_CTL_CHECK; j++) {
3120                         temp = qlcnic_ind_rd(adapter, QLCNIC_MS_CTRL);
3121
3122                         if ((temp & TA_CTL_BUSY) == 0)
3123                                 break;
3124                 }
3125
3126                 /* Status check failure */
3127                 if (j >= MAX_CTL_CHECK) {
3128                         printk_ratelimited(KERN_WARNING
3129                                            "MS memory write failed\n");
3130                         mutex_unlock(&adapter->ahw->mem_lock);
3131                         return -EIO;
3132                 }
3133         }
3134
3135         mutex_unlock(&adapter->ahw->mem_lock);
3136
3137         return ret;
3138 }
3139
3140 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
3141                              u8 *p_data, int count)
3142 {
3143         u32 word, addr = flash_addr, ret;
3144         ulong  indirect_addr;
3145         int i, err = 0;
3146
3147         if (qlcnic_83xx_lock_flash(adapter) != 0)
3148                 return -EIO;
3149
3150         if (addr & 0x3) {
3151                 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
3152                 qlcnic_83xx_unlock_flash(adapter);
3153                 return -EIO;
3154         }
3155
3156         for (i = 0; i < count; i++) {
3157                 if (qlcnic_83xx_wrt_reg_indirect(adapter,
3158                                                  QLC_83XX_FLASH_DIRECT_WINDOW,
3159                                                  (addr))) {
3160                         qlcnic_83xx_unlock_flash(adapter);
3161                         return -EIO;
3162                 }
3163
3164                 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
3165                 ret = QLCRD32(adapter, indirect_addr, &err);
3166                 if (err == -EIO) {
3167                         qlcnic_83xx_unlock_flash(adapter);
3168                         return err;
3169                 }
3170
3171                 word = ret;
3172                 *(u32 *)p_data  = word;
3173                 p_data = p_data + 4;
3174                 addr = addr + 4;
3175         }
3176
3177         qlcnic_83xx_unlock_flash(adapter);
3178
3179         return 0;
3180 }
3181
3182 void qlcnic_83xx_get_port_type(struct qlcnic_adapter *adapter)
3183 {
3184         struct qlcnic_hardware_context *ahw = adapter->ahw;
3185         struct qlcnic_cmd_args cmd;
3186         u32 config;
3187         int err;
3188
3189         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3190         if (err)
3191                 return;
3192
3193         err = qlcnic_issue_cmd(adapter, &cmd);
3194         if (err) {
3195                 dev_info(&adapter->pdev->dev,
3196                          "Get Link Status Command failed: 0x%x\n", err);
3197                 goto out;
3198         } else {
3199                 config = cmd.rsp.arg[3];
3200
3201                 switch (QLC_83XX_SFP_MODULE_TYPE(config)) {
3202                 case QLC_83XX_MODULE_FIBRE_1000BASE_SX:
3203                 case QLC_83XX_MODULE_FIBRE_1000BASE_LX:
3204                 case QLC_83XX_MODULE_FIBRE_1000BASE_CX:
3205                 case QLC_83XX_MODULE_TP_1000BASE_T:
3206                         ahw->port_type = QLCNIC_GBE;
3207                         break;
3208                 default:
3209                         ahw->port_type = QLCNIC_XGBE;
3210                 }
3211         }
3212 out:
3213         qlcnic_free_mbx_args(&cmd);
3214 }
3215
3216 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
3217 {
3218         u8 pci_func;
3219         int err;
3220         u32 config = 0, state;
3221         struct qlcnic_cmd_args cmd;
3222         struct qlcnic_hardware_context *ahw = adapter->ahw;
3223
3224         if (qlcnic_sriov_vf_check(adapter))
3225                 pci_func = adapter->portnum;
3226         else
3227                 pci_func = ahw->pci_func;
3228
3229         state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
3230         if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
3231                 dev_info(&adapter->pdev->dev, "link state down\n");
3232                 return config;
3233         }
3234
3235         err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3236         if (err)
3237                 return err;
3238
3239         err = qlcnic_issue_cmd(adapter, &cmd);
3240         if (err) {
3241                 dev_info(&adapter->pdev->dev,
3242                          "Get Link Status Command failed: 0x%x\n", err);
3243                 goto out;
3244         } else {
3245                 config = cmd.rsp.arg[1];
3246                 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
3247                 case QLC_83XX_10M_LINK:
3248                         ahw->link_speed = SPEED_10;
3249                         break;
3250                 case QLC_83XX_100M_LINK:
3251                         ahw->link_speed = SPEED_100;
3252                         break;
3253                 case QLC_83XX_1G_LINK:
3254                         ahw->link_speed = SPEED_1000;
3255                         break;
3256                 case QLC_83XX_10G_LINK:
3257                         ahw->link_speed = SPEED_10000;
3258                         break;
3259                 default:
3260                         ahw->link_speed = 0;
3261                         break;
3262                 }
3263                 config = cmd.rsp.arg[3];
3264                 switch (QLC_83XX_SFP_MODULE_TYPE(config)) {
3265                 case QLC_83XX_MODULE_FIBRE_10GBASE_LRM:
3266                 case QLC_83XX_MODULE_FIBRE_10GBASE_LR:
3267                 case QLC_83XX_MODULE_FIBRE_10GBASE_SR:
3268                         ahw->supported_type = PORT_FIBRE;
3269                         ahw->port_type = QLCNIC_XGBE;
3270                         break;
3271                 case QLC_83XX_MODULE_FIBRE_1000BASE_SX:
3272                 case QLC_83XX_MODULE_FIBRE_1000BASE_LX:
3273                 case QLC_83XX_MODULE_FIBRE_1000BASE_CX:
3274                         ahw->supported_type = PORT_FIBRE;
3275                         ahw->port_type = QLCNIC_GBE;
3276                         break;
3277                 case QLC_83XX_MODULE_TP_1000BASE_T:
3278                         ahw->supported_type = PORT_TP;
3279                         ahw->port_type = QLCNIC_GBE;
3280                         break;
3281                 case QLC_83XX_MODULE_DA_10GE_PASSIVE_CP:
3282                 case QLC_83XX_MODULE_DA_10GE_ACTIVE_CP:
3283                 case QLC_83XX_MODULE_DA_10GE_LEGACY_CP:
3284                 case QLC_83XX_MODULE_DA_1GE_PASSIVE_CP:
3285                         ahw->supported_type = PORT_DA;
3286                         ahw->port_type = QLCNIC_XGBE;
3287                         break;
3288                 default:
3289                         ahw->supported_type = PORT_OTHER;
3290                         ahw->port_type = QLCNIC_XGBE;
3291                 }
3292                 if (config & 1)
3293                         err = 1;
3294         }
3295 out:
3296         qlcnic_free_mbx_args(&cmd);
3297         return config;
3298 }
3299
3300 int qlcnic_83xx_get_link_ksettings(struct qlcnic_adapter *adapter,
3301                                    struct ethtool_link_ksettings *ecmd)
3302 {
3303         struct qlcnic_hardware_context *ahw = adapter->ahw;
3304         u32 config = 0;
3305         int status = 0;
3306         u32 supported, advertising;
3307
3308         if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
3309                 /* Get port configuration info */
3310                 status = qlcnic_83xx_get_port_info(adapter);
3311                 /* Get Link Status related info */
3312                 config = qlcnic_83xx_test_link(adapter);
3313                 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3314         }
3315
3316         /* hard code until there is a way to get it from flash */
3317         ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3318
3319         if (netif_running(adapter->netdev) && ahw->has_link_events) {
3320                 ecmd->base.speed = ahw->link_speed;
3321                 ecmd->base.duplex = ahw->link_duplex;
3322                 ecmd->base.autoneg = ahw->link_autoneg;
3323         } else {
3324                 ecmd->base.speed = SPEED_UNKNOWN;
3325                 ecmd->base.duplex = DUPLEX_UNKNOWN;
3326                 ecmd->base.autoneg = AUTONEG_DISABLE;
3327         }
3328
3329         supported = (SUPPORTED_10baseT_Full |
3330                            SUPPORTED_100baseT_Full |
3331                            SUPPORTED_1000baseT_Full |
3332                            SUPPORTED_10000baseT_Full |
3333                            SUPPORTED_Autoneg);
3334
3335         ethtool_convert_link_mode_to_legacy_u32(&advertising,
3336                                                 ecmd->link_modes.advertising);
3337
3338         if (ecmd->base.autoneg == AUTONEG_ENABLE) {
3339                 if (ahw->port_config & QLC_83XX_10_CAPABLE)
3340                         advertising |= SUPPORTED_10baseT_Full;
3341                 if (ahw->port_config & QLC_83XX_100_CAPABLE)
3342                         advertising |= SUPPORTED_100baseT_Full;
3343                 if (ahw->port_config & QLC_83XX_1G_CAPABLE)
3344                         advertising |= SUPPORTED_1000baseT_Full;
3345                 if (ahw->port_config & QLC_83XX_10G_CAPABLE)
3346                         advertising |= SUPPORTED_10000baseT_Full;
3347                 if (ahw->port_config & QLC_83XX_AUTONEG_ENABLE)
3348                         advertising |= ADVERTISED_Autoneg;
3349         } else {
3350                 switch (ahw->link_speed) {
3351                 case SPEED_10:
3352                         advertising = SUPPORTED_10baseT_Full;
3353                         break;
3354                 case SPEED_100:
3355                         advertising = SUPPORTED_100baseT_Full;
3356                         break;
3357                 case SPEED_1000:
3358                         advertising = SUPPORTED_1000baseT_Full;
3359                         break;
3360                 case SPEED_10000:
3361                         advertising = SUPPORTED_10000baseT_Full;
3362                         break;
3363                 default:
3364                         break;
3365                 }
3366
3367         }
3368
3369         switch (ahw->supported_type) {
3370         case PORT_FIBRE:
3371                 supported |= SUPPORTED_FIBRE;
3372                 advertising |= ADVERTISED_FIBRE;
3373                 ecmd->base.port = PORT_FIBRE;
3374                 break;
3375         case PORT_TP:
3376                 supported |= SUPPORTED_TP;
3377                 advertising |= ADVERTISED_TP;
3378                 ecmd->base.port = PORT_TP;
3379                 break;
3380         case PORT_DA:
3381                 supported |= SUPPORTED_FIBRE;
3382                 advertising |= ADVERTISED_FIBRE;
3383                 ecmd->base.port = PORT_DA;
3384                 break;
3385         default:
3386                 supported |= SUPPORTED_FIBRE;
3387                 advertising |= ADVERTISED_FIBRE;
3388                 ecmd->base.port = PORT_OTHER;
3389                 break;
3390         }
3391         ecmd->base.phy_address = ahw->physical_port;
3392
3393         ethtool_convert_legacy_u32_to_link_mode(ecmd->link_modes.supported,
3394                                                 supported);
3395         ethtool_convert_legacy_u32_to_link_mode(ecmd->link_modes.advertising,
3396                                                 advertising);
3397
3398         return status;
3399 }
3400
3401 int qlcnic_83xx_set_link_ksettings(struct qlcnic_adapter *adapter,
3402                                    const struct ethtool_link_ksettings *ecmd)
3403 {
3404         struct qlcnic_hardware_context *ahw = adapter->ahw;
3405         u32 config = adapter->ahw->port_config;
3406         int status = 0;
3407
3408         /* 83xx devices do not support Half duplex */
3409         if (ecmd->base.duplex == DUPLEX_HALF) {
3410                 netdev_info(adapter->netdev,
3411                             "Half duplex mode not supported\n");
3412                 return -EINVAL;
3413         }
3414
3415         if (ecmd->base.autoneg) {
3416                 ahw->port_config |= QLC_83XX_AUTONEG_ENABLE;
3417                 ahw->port_config |= (QLC_83XX_100_CAPABLE |
3418                                      QLC_83XX_1G_CAPABLE |
3419                                      QLC_83XX_10G_CAPABLE);
3420         } else { /* force speed */
3421                 ahw->port_config &= ~QLC_83XX_AUTONEG_ENABLE;
3422                 switch (ecmd->base.speed) {
3423                 case SPEED_10:
3424                         ahw->port_config &= ~(QLC_83XX_100_CAPABLE |
3425                                               QLC_83XX_1G_CAPABLE |
3426                                               QLC_83XX_10G_CAPABLE);
3427                         ahw->port_config |= QLC_83XX_10_CAPABLE;
3428                         break;
3429                 case SPEED_100:
3430                         ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3431                                               QLC_83XX_1G_CAPABLE |
3432                                               QLC_83XX_10G_CAPABLE);
3433                         ahw->port_config |= QLC_83XX_100_CAPABLE;
3434                         break;
3435                 case SPEED_1000:
3436                         ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3437                                               QLC_83XX_100_CAPABLE |
3438                                               QLC_83XX_10G_CAPABLE);
3439                         ahw->port_config |= QLC_83XX_1G_CAPABLE;
3440                         break;
3441                 case SPEED_10000:
3442                         ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
3443                                               QLC_83XX_100_CAPABLE |
3444                                               QLC_83XX_1G_CAPABLE);
3445                         ahw->port_config |= QLC_83XX_10G_CAPABLE;
3446                         break;
3447                 default:
3448                         return -EINVAL;
3449                 }
3450         }
3451         status = qlcnic_83xx_set_port_config(adapter);
3452         if (status) {
3453                 netdev_info(adapter->netdev,
3454                             "Failed to Set Link Speed and autoneg.\n");
3455                 ahw->port_config = config;
3456         }
3457
3458         return status;
3459 }
3460
3461 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3462                                           u64 *data, int index)
3463 {
3464         u32 low, hi;
3465         u64 val;
3466
3467         low = cmd->rsp.arg[index];
3468         hi = cmd->rsp.arg[index + 1];
3469         val = (((u64) low) | (((u64) hi) << 32));
3470         *data++ = val;
3471         return data;
3472 }
3473
3474 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3475                                    struct qlcnic_cmd_args *cmd, u64 *data,
3476                                    int type, int *ret)
3477 {
3478         int err, k, total_regs;
3479
3480         *ret = 0;
3481         err = qlcnic_issue_cmd(adapter, cmd);
3482         if (err != QLCNIC_RCODE_SUCCESS) {
3483                 dev_info(&adapter->pdev->dev,
3484                          "Error in get statistics mailbox command\n");
3485                 *ret = -EIO;
3486                 return data;
3487         }
3488         total_regs = cmd->rsp.num;
3489         switch (type) {
3490         case QLC_83XX_STAT_MAC:
3491                 /* fill in MAC tx counters */
3492                 for (k = 2; k < 28; k += 2)
3493                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3494                 /* skip 24 bytes of reserved area */
3495                 /* fill in MAC rx counters */
3496                 for (k += 6; k < 60; k += 2)
3497                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3498                 /* skip 24 bytes of reserved area */
3499                 /* fill in MAC rx frame stats */
3500                 for (k += 6; k < 80; k += 2)
3501                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3502                 /* fill in eSwitch stats */
3503                 for (; k < total_regs; k += 2)
3504                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3505                 break;
3506         case QLC_83XX_STAT_RX:
3507                 for (k = 2; k < 8; k += 2)
3508                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3509                 /* skip 8 bytes of reserved data */
3510                 for (k += 2; k < 24; k += 2)
3511                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3512                 /* skip 8 bytes containing RE1FBQ error data */
3513                 for (k += 2; k < total_regs; k += 2)
3514                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3515                 break;
3516         case QLC_83XX_STAT_TX:
3517                 for (k = 2; k < 10; k += 2)
3518                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3519                 /* skip 8 bytes of reserved data */
3520                 for (k += 2; k < total_regs; k += 2)
3521                         data = qlcnic_83xx_copy_stats(cmd, data, k);
3522                 break;
3523         default:
3524                 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3525                 *ret = -EIO;
3526         }
3527         return data;
3528 }
3529
3530 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3531 {
3532         struct qlcnic_cmd_args cmd;
3533         struct net_device *netdev = adapter->netdev;
3534         int ret = 0;
3535
3536         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3537         if (ret)
3538                 return;
3539         /* Get Tx stats */
3540         cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3541         cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3542         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3543                                       QLC_83XX_STAT_TX, &ret);
3544         if (ret) {
3545                 netdev_err(netdev, "Error getting Tx stats\n");
3546                 goto out;
3547         }
3548         /* Get MAC stats */
3549         cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3550         cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3551         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3552         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3553                                       QLC_83XX_STAT_MAC, &ret);
3554         if (ret) {
3555                 netdev_err(netdev, "Error getting MAC stats\n");
3556                 goto out;
3557         }
3558         /* Get Rx stats */
3559         cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3560         cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3561         memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3562         data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3563                                       QLC_83XX_STAT_RX, &ret);
3564         if (ret)
3565                 netdev_err(netdev, "Error getting Rx stats\n");
3566 out:
3567         qlcnic_free_mbx_args(&cmd);
3568 }
3569
3570 #define QLCNIC_83XX_ADD_PORT0           BIT_0
3571 #define QLCNIC_83XX_ADD_PORT1           BIT_1
3572 #define QLCNIC_83XX_EXTENDED_MEM_SIZE   13 /* In MB */
3573 int qlcnic_83xx_extend_md_capab(struct qlcnic_adapter *adapter)
3574 {
3575         struct qlcnic_cmd_args cmd;
3576         int err;
3577
3578         err = qlcnic_alloc_mbx_args(&cmd, adapter,
3579                                     QLCNIC_CMD_83XX_EXTEND_ISCSI_DUMP_CAP);
3580         if (err)
3581                 return err;
3582
3583         cmd.req.arg[1] = (QLCNIC_83XX_ADD_PORT0 | QLCNIC_83XX_ADD_PORT1);
3584         cmd.req.arg[2] = QLCNIC_83XX_EXTENDED_MEM_SIZE;
3585         cmd.req.arg[3] = QLCNIC_83XX_EXTENDED_MEM_SIZE;
3586
3587         err = qlcnic_issue_cmd(adapter, &cmd);
3588         if (err)
3589                 dev_err(&adapter->pdev->dev,
3590                         "failed to issue extend iSCSI minidump capability\n");
3591
3592         return err;
3593 }
3594
3595 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3596 {
3597         u32 major, minor, sub;
3598
3599         major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3600         minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3601         sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3602
3603         if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3604                 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3605                          __func__);
3606                 return 1;
3607         }
3608         return 0;
3609 }
3610
3611 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3612 {
3613         return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3614                 sizeof(*adapter->ahw->ext_reg_tbl)) +
3615                 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) *
3616                 sizeof(*adapter->ahw->reg_tbl));
3617 }
3618
3619 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3620 {
3621         int i, j = 0;
3622
3623         for (i = QLCNIC_DEV_INFO_SIZE + 1;
3624              j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3625                 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3626
3627         for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3628                 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3629         return i;
3630 }
3631
3632 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3633 {
3634         struct qlcnic_adapter *adapter = netdev_priv(netdev);
3635         struct qlcnic_hardware_context *ahw = adapter->ahw;
3636         struct qlcnic_cmd_args cmd;
3637         u8 val, drv_sds_rings = adapter->drv_sds_rings;
3638         u8 drv_tx_rings = adapter->drv_tx_rings;
3639         u32 data;
3640         u16 intrpt_id, id;
3641         int ret;
3642
3643         if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3644                 netdev_info(netdev, "Device is resetting\n");
3645                 return -EBUSY;
3646         }
3647
3648         if (qlcnic_get_diag_lock(adapter)) {
3649                 netdev_info(netdev, "Device in diagnostics mode\n");
3650                 return -EBUSY;
3651         }
3652
3653         ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3654                                          drv_sds_rings);
3655         if (ret)
3656                 goto fail_diag_irq;
3657
3658         ahw->diag_cnt = 0;
3659         ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3660         if (ret)
3661                 goto fail_mbx_args;
3662
3663         if (adapter->flags & QLCNIC_MSIX_ENABLED)
3664                 intrpt_id = ahw->intr_tbl[0].id;
3665         else
3666                 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3667
3668         cmd.req.arg[1] = 1;
3669         cmd.req.arg[2] = intrpt_id;
3670         cmd.req.arg[3] = BIT_0;
3671
3672         ret = qlcnic_issue_cmd(adapter, &cmd);
3673         data = cmd.rsp.arg[2];
3674         id = LSW(data);
3675         val = LSB(MSW(data));
3676         if (id != intrpt_id)
3677                 dev_info(&adapter->pdev->dev,
3678                          "Interrupt generated: 0x%x, requested:0x%x\n",
3679                          id, intrpt_id);
3680         if (val)
3681                 dev_err(&adapter->pdev->dev,
3682                          "Interrupt test error: 0x%x\n", val);
3683         if (ret)
3684                 goto done;
3685
3686         msleep(20);
3687         ret = !ahw->diag_cnt;
3688
3689 done:
3690         qlcnic_free_mbx_args(&cmd);
3691
3692 fail_mbx_args:
3693         qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
3694
3695 fail_diag_irq:
3696         adapter->drv_sds_rings = drv_sds_rings;
3697         adapter->drv_tx_rings = drv_tx_rings;
3698         qlcnic_release_diag_lock(adapter);
3699         return ret;
3700 }
3701
3702 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3703                                 struct ethtool_pauseparam *pause)
3704 {
3705         struct qlcnic_hardware_context *ahw = adapter->ahw;
3706         int status = 0;
3707         u32 config;
3708
3709         status = qlcnic_83xx_get_port_config(adapter);
3710         if (status) {
3711                 dev_err(&adapter->pdev->dev,
3712                         "%s: Get Pause Config failed\n", __func__);
3713                 return;
3714         }
3715         config = ahw->port_config;
3716         if (config & QLC_83XX_CFG_STD_PAUSE) {
3717                 switch (MSW(config)) {
3718                 case QLC_83XX_TX_PAUSE:
3719                         pause->tx_pause = 1;
3720                         break;
3721                 case QLC_83XX_RX_PAUSE:
3722                         pause->rx_pause = 1;
3723                         break;
3724                 case QLC_83XX_TX_RX_PAUSE:
3725                 default:
3726                         /* Backward compatibility for existing
3727                          * flash definitions
3728                          */
3729                         pause->tx_pause = 1;
3730                         pause->rx_pause = 1;
3731                 }
3732         }
3733
3734         if (QLC_83XX_AUTONEG(config))
3735                 pause->autoneg = 1;
3736 }
3737
3738 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3739                                struct ethtool_pauseparam *pause)
3740 {
3741         struct qlcnic_hardware_context *ahw = adapter->ahw;
3742         int status = 0;
3743         u32 config;
3744
3745         status = qlcnic_83xx_get_port_config(adapter);
3746         if (status) {
3747                 dev_err(&adapter->pdev->dev,
3748                         "%s: Get Pause Config failed.\n", __func__);
3749                 return status;
3750         }
3751         config = ahw->port_config;
3752
3753         if (ahw->port_type == QLCNIC_GBE) {
3754                 if (pause->autoneg)
3755                         ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3756                 if (!pause->autoneg)
3757                         ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3758         } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3759                 return -EOPNOTSUPP;
3760         }
3761
3762         if (!(config & QLC_83XX_CFG_STD_PAUSE))
3763                 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3764
3765         if (pause->rx_pause && pause->tx_pause) {
3766                 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3767         } else if (pause->rx_pause && !pause->tx_pause) {
3768                 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3769                 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3770         } else if (pause->tx_pause && !pause->rx_pause) {
3771                 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3772                 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3773         } else if (!pause->rx_pause && !pause->tx_pause) {
3774                 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE |
3775                                       QLC_83XX_CFG_STD_PAUSE);
3776         }
3777         status = qlcnic_83xx_set_port_config(adapter);
3778         if (status) {
3779                 dev_err(&adapter->pdev->dev,
3780                         "%s: Set Pause Config failed.\n", __func__);
3781                 ahw->port_config = config;
3782         }
3783         return status;
3784 }
3785
3786 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3787 {
3788         int ret, err = 0;
3789         u32 temp;
3790
3791         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3792                                      QLC_83XX_FLASH_OEM_READ_SIG);
3793         qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3794                                      QLC_83XX_FLASH_READ_CTRL);
3795         ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3796         if (ret)
3797                 return -EIO;
3798
3799         temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3800         if (err == -EIO)
3801                 return err;
3802
3803         return temp & 0xFF;
3804 }
3805
3806 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3807 {
3808         int status;
3809
3810         status = qlcnic_83xx_read_flash_status_reg(adapter);
3811         if (status == -EIO) {
3812                 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3813                          __func__);
3814                 return 1;
3815         }
3816         return 0;
3817 }
3818
3819 static int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3820 {
3821         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3822         struct net_device *netdev = adapter->netdev;
3823         int retval;
3824
3825         netif_device_detach(netdev);
3826         qlcnic_cancel_idc_work(adapter);
3827
3828         if (netif_running(netdev))
3829                 qlcnic_down(adapter, netdev);
3830
3831         qlcnic_83xx_disable_mbx_intr(adapter);
3832         cancel_delayed_work_sync(&adapter->idc_aen_work);
3833
3834         retval = pci_save_state(pdev);
3835         if (retval)
3836                 return retval;
3837
3838         return 0;
3839 }
3840
3841 static int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3842 {
3843         struct qlcnic_hardware_context *ahw = adapter->ahw;
3844         struct qlc_83xx_idc *idc = &ahw->idc;
3845         int err = 0;
3846
3847         err = qlcnic_83xx_idc_init(adapter);
3848         if (err)
3849                 return err;
3850
3851         if (ahw->nic_mode == QLCNIC_VNIC_MODE) {
3852                 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3853                         qlcnic_83xx_set_vnic_opmode(adapter);
3854                 } else {
3855                         err = qlcnic_83xx_check_vnic_state(adapter);
3856                         if (err)
3857                                 return err;
3858                 }
3859         }
3860
3861         err = qlcnic_83xx_idc_reattach_driver(adapter);
3862         if (err)
3863                 return err;
3864
3865         qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3866                              idc->delay);
3867         return err;
3868 }
3869
3870 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3871 {
3872         reinit_completion(&mbx->completion);
3873         set_bit(QLC_83XX_MBX_READY, &mbx->status);
3874 }
3875
3876 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3877 {
3878         if (!mbx)
3879                 return;
3880
3881         destroy_workqueue(mbx->work_q);
3882         kfree(mbx);
3883 }
3884
3885 static inline void
3886 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3887                                   struct qlcnic_cmd_args *cmd)
3888 {
3889         atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3890
3891         if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3892                 qlcnic_free_mbx_args(cmd);
3893                 kfree(cmd);
3894                 return;
3895         }
3896         complete(&cmd->completion);
3897 }
3898
3899 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3900 {
3901         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3902         struct list_head *head = &mbx->cmd_q;
3903         struct qlcnic_cmd_args *cmd = NULL;
3904
3905         spin_lock_bh(&mbx->queue_lock);
3906
3907         while (!list_empty(head)) {
3908                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3909                 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3910                          __func__, cmd->cmd_op);
3911                 list_del(&cmd->list);
3912                 mbx->num_cmds--;
3913                 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3914         }
3915
3916         spin_unlock_bh(&mbx->queue_lock);
3917 }
3918
3919 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3920 {
3921         struct qlcnic_hardware_context *ahw = adapter->ahw;
3922         struct qlcnic_mailbox *mbx = ahw->mailbox;
3923         u32 host_mbx_ctrl;
3924
3925         if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3926                 return -EBUSY;
3927
3928         host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3929         if (host_mbx_ctrl) {
3930                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3931                 ahw->idc.collect_dump = 1;
3932                 return -EIO;
3933         }
3934
3935         return 0;
3936 }
3937
3938 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3939                                               u8 issue_cmd)
3940 {
3941         if (issue_cmd)
3942                 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3943         else
3944                 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3945 }
3946
3947 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3948                                         struct qlcnic_cmd_args *cmd)
3949 {
3950         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3951
3952         spin_lock_bh(&mbx->queue_lock);
3953
3954         list_del(&cmd->list);
3955         mbx->num_cmds--;
3956
3957         spin_unlock_bh(&mbx->queue_lock);
3958
3959         qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3960 }
3961
3962 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3963                                        struct qlcnic_cmd_args *cmd)
3964 {
3965         u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3966         struct qlcnic_hardware_context *ahw = adapter->ahw;
3967         int i, j;
3968
3969         if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3970                 mbx_cmd = cmd->req.arg[0];
3971                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3972                 for (i = 1; i < cmd->req.num; i++)
3973                         writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3974         } else {
3975                 fw_hal_version = ahw->fw_hal_version;
3976                 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3977                 total_size = cmd->pay_size + hdr_size;
3978                 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3979                 mbx_cmd = tmp | fw_hal_version << 29;
3980                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3981
3982                 /* Back channel specific operations bits */
3983                 mbx_cmd = 0x1 | 1 << 4;
3984
3985                 if (qlcnic_sriov_pf_check(adapter))
3986                         mbx_cmd |= cmd->func_num << 5;
3987
3988                 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3989
3990                 for (i = 2, j = 0; j < hdr_size; i++, j++)
3991                         writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3992                 for (j = 0; j < cmd->pay_size; j++, i++)
3993                         writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3994         }
3995 }
3996
3997 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3998 {
3999         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
4000
4001         if (!mbx)
4002                 return;
4003
4004         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
4005         complete(&mbx->completion);
4006         cancel_work_sync(&mbx->work);
4007         flush_workqueue(mbx->work_q);
4008         qlcnic_83xx_flush_mbx_queue(adapter);
4009 }
4010
4011 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
4012                                        struct qlcnic_cmd_args *cmd,
4013                                        unsigned long *timeout)
4014 {
4015         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
4016
4017         if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
4018                 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
4019                 init_completion(&cmd->completion);
4020                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
4021
4022                 spin_lock_bh(&mbx->queue_lock);
4023
4024                 list_add_tail(&cmd->list, &mbx->cmd_q);
4025                 mbx->num_cmds++;
4026                 cmd->total_cmds = mbx->num_cmds;
4027                 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
4028                 queue_work(mbx->work_q, &mbx->work);
4029
4030                 spin_unlock_bh(&mbx->queue_lock);
4031
4032                 return 0;
4033         }
4034
4035         return -EBUSY;
4036 }
4037
4038 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
4039                                        struct qlcnic_cmd_args *cmd)
4040 {
4041         u8 mac_cmd_rcode;
4042         u32 fw_data;
4043
4044         if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
4045                 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
4046                 mac_cmd_rcode = (u8)fw_data;
4047                 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
4048                     mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
4049                     mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
4050                         cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
4051                         return QLCNIC_RCODE_SUCCESS;
4052                 }
4053         }
4054
4055         return -EINVAL;
4056 }
4057
4058 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
4059                                        struct qlcnic_cmd_args *cmd)
4060 {
4061         struct qlcnic_hardware_context *ahw = adapter->ahw;
4062         struct device *dev = &adapter->pdev->dev;
4063         u8 mbx_err_code;
4064         u32 fw_data;
4065
4066         fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
4067         mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
4068         qlcnic_83xx_get_mbx_data(adapter, cmd);
4069
4070         switch (mbx_err_code) {
4071         case QLCNIC_MBX_RSP_OK:
4072         case QLCNIC_MBX_PORT_RSP_OK:
4073                 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
4074                 break;
4075         default:
4076                 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
4077                         break;
4078
4079                 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
4080                         __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
4081                         ahw->op_mode, mbx_err_code);
4082                 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
4083                 qlcnic_dump_mbx(adapter, cmd);
4084         }
4085
4086         return;
4087 }
4088
4089 static inline void qlcnic_dump_mailbox_registers(struct qlcnic_adapter *adapter)
4090 {
4091         struct qlcnic_hardware_context *ahw = adapter->ahw;
4092         u32 offset;
4093
4094         offset = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
4095         dev_info(&adapter->pdev->dev, "Mbx interrupt mask=0x%x, Mbx interrupt enable=0x%x, Host mbx control=0x%x, Fw mbx control=0x%x",
4096                  readl(ahw->pci_base0 + offset),
4097                  QLCRDX(ahw, QLCNIC_MBX_INTR_ENBL),
4098                  QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL),
4099                  QLCRDX(ahw, QLCNIC_FW_MBX_CTRL));
4100 }
4101
4102 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
4103 {
4104         struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
4105                                                   work);
4106         struct qlcnic_adapter *adapter = mbx->adapter;
4107         const struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
4108         struct device *dev = &adapter->pdev->dev;
4109         struct list_head *head = &mbx->cmd_q;
4110         struct qlcnic_hardware_context *ahw;
4111         struct qlcnic_cmd_args *cmd = NULL;
4112         unsigned long flags;
4113
4114         ahw = adapter->ahw;
4115
4116         while (true) {
4117                 if (qlcnic_83xx_check_mbx_status(adapter)) {
4118                         qlcnic_83xx_flush_mbx_queue(adapter);
4119                         return;
4120                 }
4121
4122                 spin_lock_irqsave(&mbx->aen_lock, flags);
4123                 mbx->rsp_status = QLC_83XX_MBX_RESPONSE_WAIT;
4124                 spin_unlock_irqrestore(&mbx->aen_lock, flags);
4125
4126                 spin_lock_bh(&mbx->queue_lock);
4127
4128                 if (list_empty(head)) {
4129                         spin_unlock_bh(&mbx->queue_lock);
4130                         return;
4131                 }
4132                 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
4133
4134                 spin_unlock_bh(&mbx->queue_lock);
4135
4136                 mbx_ops->encode_cmd(adapter, cmd);
4137                 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
4138
4139                 if (wait_for_completion_timeout(&mbx->completion,
4140                                                 QLC_83XX_MBX_TIMEOUT)) {
4141                         mbx_ops->decode_resp(adapter, cmd);
4142                         mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
4143                 } else {
4144                         dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
4145                                 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
4146                                 ahw->op_mode);
4147                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
4148                         qlcnic_dump_mailbox_registers(adapter);
4149                         qlcnic_83xx_get_mbx_data(adapter, cmd);
4150                         qlcnic_dump_mbx(adapter, cmd);
4151                         qlcnic_83xx_idc_request_reset(adapter,
4152                                                       QLCNIC_FORCE_FW_DUMP_KEY);
4153                         cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
4154                 }
4155                 mbx_ops->dequeue_cmd(adapter, cmd);
4156         }
4157 }
4158
4159 static const struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
4160         .enqueue_cmd    = qlcnic_83xx_enqueue_mbx_cmd,
4161         .dequeue_cmd    = qlcnic_83xx_dequeue_mbx_cmd,
4162         .decode_resp    = qlcnic_83xx_decode_mbx_rsp,
4163         .encode_cmd     = qlcnic_83xx_encode_mbx_cmd,
4164         .nofity_fw      = qlcnic_83xx_signal_mbx_cmd,
4165 };
4166
4167 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
4168 {
4169         struct qlcnic_hardware_context *ahw = adapter->ahw;
4170         struct qlcnic_mailbox *mbx;
4171
4172         ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
4173         if (!ahw->mailbox)
4174                 return -ENOMEM;
4175
4176         mbx = ahw->mailbox;
4177         mbx->ops = &qlcnic_83xx_mbx_ops;
4178         mbx->adapter = adapter;
4179
4180         spin_lock_init(&mbx->queue_lock);
4181         spin_lock_init(&mbx->aen_lock);
4182         INIT_LIST_HEAD(&mbx->cmd_q);
4183         init_completion(&mbx->completion);
4184
4185         mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
4186         if (mbx->work_q == NULL) {
4187                 kfree(mbx);
4188                 return -ENOMEM;
4189         }
4190
4191         INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
4192         set_bit(QLC_83XX_MBX_READY, &mbx->status);
4193         return 0;
4194 }
4195
4196 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev,
4197                                                       pci_channel_state_t state)
4198 {
4199         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4200
4201         if (state == pci_channel_io_perm_failure)
4202                 return PCI_ERS_RESULT_DISCONNECT;
4203
4204         if (state == pci_channel_io_normal)
4205                 return PCI_ERS_RESULT_RECOVERED;
4206
4207         set_bit(__QLCNIC_AER, &adapter->state);
4208         set_bit(__QLCNIC_RESETTING, &adapter->state);
4209
4210         qlcnic_83xx_aer_stop_poll_work(adapter);
4211
4212         pci_save_state(pdev);
4213         pci_disable_device(pdev);
4214
4215         return PCI_ERS_RESULT_NEED_RESET;
4216 }
4217
4218 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev)
4219 {
4220         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4221         int err = 0;
4222
4223         pdev->error_state = pci_channel_io_normal;
4224         err = pci_enable_device(pdev);
4225         if (err)
4226                 goto disconnect;
4227
4228         pci_set_power_state(pdev, PCI_D0);
4229         pci_set_master(pdev);
4230         pci_restore_state(pdev);
4231
4232         err = qlcnic_83xx_aer_reset(adapter);
4233         if (err == 0)
4234                 return PCI_ERS_RESULT_RECOVERED;
4235 disconnect:
4236         clear_bit(__QLCNIC_AER, &adapter->state);
4237         clear_bit(__QLCNIC_RESETTING, &adapter->state);
4238         return PCI_ERS_RESULT_DISCONNECT;
4239 }
4240
4241 static void qlcnic_83xx_io_resume(struct pci_dev *pdev)
4242 {
4243         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4244
4245         pci_cleanup_aer_uncorrect_error_status(pdev);
4246         if (test_and_clear_bit(__QLCNIC_AER, &adapter->state))
4247                 qlcnic_83xx_aer_start_poll_work(adapter);
4248 }