drivers/net/ethernet/qlogic/qed/qed_sp_commands.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #include <linux/types.h>
  10 #include <asm/byteorder.h>
  11 #include <linux/bitops.h>
  12 #include <linux/errno.h>
  13 #include <linux/kernel.h>
  14 #include <linux/string.h>
  15 #include "qed.h"
  16 #include <linux/qed/qed_chain.h>
  17 #include "qed_cxt.h"
  18 #include "qed_dcbx.h"
  19 #include "qed_hsi.h"
  20 #include "qed_hw.h"
  21 #include "qed_int.h"
  22 #include "qed_reg_addr.h"
  23 #include "qed_sp.h"
  24 #include "qed_sriov.h"
  25
  26 int qed_sp_init_request(struct qed_hwfn *p_hwfn,
  27                         struct qed_spq_entry **pp_ent,
  28                         u8 cmd, u8 protocol, struct qed_sp_init_data *p_data)
  29 {
  30         u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid;
  31         struct qed_spq_entry *p_ent = NULL;
  32         int rc;
  33
  34         if (!pp_ent)
  35                 return -ENOMEM;
  36
  37         rc = qed_spq_get_entry(p_hwfn, pp_ent);
  38
  39         if (rc)
  40                 return rc;
  41
  42         p_ent = *pp_ent;
  43
  44         p_ent->elem.hdr.cid             = cpu_to_le32(opaque_cid);
  45         p_ent->elem.hdr.cmd_id          = cmd;
  46         p_ent->elem.hdr.protocol_id     = protocol;
  47
  48         p_ent->priority         = QED_SPQ_PRIORITY_NORMAL;
  49         p_ent->comp_mode        = p_data->comp_mode;
  50         p_ent->comp_done.done   = 0;
  51
  52         switch (p_ent->comp_mode) {
  53         case QED_SPQ_MODE_EBLOCK:
  54                 p_ent->comp_cb.cookie = &p_ent->comp_done;
  55                 break;
  56
  57         case QED_SPQ_MODE_BLOCK:
  58                 if (!p_data->p_comp_data)
  59                         goto err;
  60
  61                 p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
  62                 break;
  63
  64         case QED_SPQ_MODE_CB:
  65                 if (!p_data->p_comp_data)
  66                         p_ent->comp_cb.function = NULL;
  67                 else
  68                         p_ent->comp_cb = *p_data->p_comp_data;
  69                 break;
  70
  71         default:
  72                 DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n",
  73                           p_ent->comp_mode);
  74                 goto err;
  75         }
  76
  77         DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
  78                    "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
  79                    opaque_cid, cmd, protocol,
  80                    (unsigned long)&p_ent->ramrod,
  81                    D_TRINE(p_ent->comp_mode, QED_SPQ_MODE_EBLOCK,
  82                            QED_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
  83                            "MODE_CB"));
  84
  85         memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));
  86
  87         return 0;
  88
  89 err:
  90         /* qed_spq_get_entry() can either get an entry from the free_pool,
  91          * or, if no entries are left, allocate a new entry and add it to
  92          * the unlimited_pending list.
  93          */
  94         if (p_ent->queue == &p_hwfn->p_spq->unlimited_pending)
  95                 kfree(p_ent);
  96         else
  97                 qed_spq_return_entry(p_hwfn, p_ent);
  98
  99         return -EINVAL;
 100 }
 101
 102 static enum tunnel_clss qed_tunn_get_clss_type(u8 type)
 103 {
 104         switch (type) {
 105         case QED_TUNN_CLSS_MAC_VLAN:
 106                 return TUNNEL_CLSS_MAC_VLAN;
 107         case QED_TUNN_CLSS_MAC_VNI:
 108                 return TUNNEL_CLSS_MAC_VNI;
 109         case QED_TUNN_CLSS_INNER_MAC_VLAN:
 110                 return TUNNEL_CLSS_INNER_MAC_VLAN;
 111         case QED_TUNN_CLSS_INNER_MAC_VNI:
 112                 return TUNNEL_CLSS_INNER_MAC_VNI;
 113         default:
 114                 return TUNNEL_CLSS_MAC_VLAN;
 115         }
 116 }
 117
 118 static void
 119 qed_tunn_set_pf_fix_tunn_mode(struct qed_hwfn *p_hwfn,
 120                               struct qed_tunn_update_params *p_src,
 121                               struct pf_update_tunnel_config *p_tunn_cfg)
 122 {
 123         unsigned long cached_tunn_mode = p_hwfn->cdev->tunn_mode;
 124         unsigned long update_mask = p_src->tunn_mode_update_mask;
 125         unsigned long tunn_mode = p_src->tunn_mode;
 126         unsigned long new_tunn_mode = 0;
 127
 128         if (test_bit(QED_MODE_L2GRE_TUNN, &update_mask)) {
 129                 if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
 130                         __set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode);
 131         } else {
 132                 if (test_bit(QED_MODE_L2GRE_TUNN, &cached_tunn_mode))
 133                         __set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode);
 134         }
 135
 136         if (test_bit(QED_MODE_IPGRE_TUNN, &update_mask)) {
 137                 if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
 138                         __set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode);
 139         } else {
 140                 if (test_bit(QED_MODE_IPGRE_TUNN, &cached_tunn_mode))
 141                         __set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode);
 142         }
 143
 144         if (test_bit(QED_MODE_VXLAN_TUNN, &update_mask)) {
 145                 if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
 146                         __set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode);
 147         } else {
 148                 if (test_bit(QED_MODE_VXLAN_TUNN, &cached_tunn_mode))
 149                         __set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode);
 150         }
 151
 152         if (p_src->update_geneve_udp_port) {
 153                 p_tunn_cfg->set_geneve_udp_port_flg = 1;
 154                 p_tunn_cfg->geneve_udp_port =
 155                                 cpu_to_le16(p_src->geneve_udp_port);
 156         }
 157
 158         if (test_bit(QED_MODE_L2GENEVE_TUNN, &update_mask)) {
 159                 if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
 160                         __set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode);
 161         } else {
 162                 if (test_bit(QED_MODE_L2GENEVE_TUNN, &cached_tunn_mode))
 163                         __set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode);
 164         }
 165
 166         if (test_bit(QED_MODE_IPGENEVE_TUNN, &update_mask)) {
 167                 if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
 168                         __set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode);
 169         } else {
 170                 if (test_bit(QED_MODE_IPGENEVE_TUNN, &cached_tunn_mode))
 171                         __set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode);
 172         }
 173
 174         p_src->tunn_mode = new_tunn_mode;
 175 }
 176
 177 static void
 178 qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn,
 179                               struct qed_tunn_update_params *p_src,
 180                               struct pf_update_tunnel_config *p_tunn_cfg)
 181 {
 182         unsigned long tunn_mode = p_src->tunn_mode;
 183         enum tunnel_clss type;
 184
 185         qed_tunn_set_pf_fix_tunn_mode(p_hwfn, p_src, p_tunn_cfg);
 186         p_tunn_cfg->update_rx_pf_clss = p_src->update_rx_pf_clss;
 187         p_tunn_cfg->update_tx_pf_clss = p_src->update_tx_pf_clss;
 188
 189         type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan);
 190         p_tunn_cfg->tunnel_clss_vxlan  = type;
 191
 192         type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre);
 193         p_tunn_cfg->tunnel_clss_l2gre = type;
 194
 195         type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre);
 196         p_tunn_cfg->tunnel_clss_ipgre = type;
 197
 198         if (p_src->update_vxlan_udp_port) {
 199                 p_tunn_cfg->set_vxlan_udp_port_flg = 1;
 200                 p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port);
 201         }
 202
 203         if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
 204                 p_tunn_cfg->tx_enable_l2gre = 1;
 205
 206         if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
 207                 p_tunn_cfg->tx_enable_ipgre = 1;
 208
 209         if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
 210                 p_tunn_cfg->tx_enable_vxlan = 1;
 211
 212         if (p_src->update_geneve_udp_port) {
 213                 p_tunn_cfg->set_geneve_udp_port_flg = 1;
 214                 p_tunn_cfg->geneve_udp_port =
 215                                 cpu_to_le16(p_src->geneve_udp_port);
 216         }
 217
 218         if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
 219                 p_tunn_cfg->tx_enable_l2geneve = 1;
 220
 221         if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
 222                 p_tunn_cfg->tx_enable_ipgeneve = 1;
 223
 224         type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve);
 225         p_tunn_cfg->tunnel_clss_l2geneve = type;
 226
 227         type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);
 228         p_tunn_cfg->tunnel_clss_ipgeneve = type;
 229 }
 230
 231 static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn,
 232                                  struct qed_ptt *p_ptt,
 233                                  unsigned long tunn_mode)
 234 {
 235         u8 l2gre_enable = 0, ipgre_enable = 0, vxlan_enable = 0;
 236         u8 l2geneve_enable = 0, ipgeneve_enable = 0;
 237
 238         if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
 239                 l2gre_enable = 1;
 240
 241         if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
 242                 ipgre_enable = 1;
 243
 244         if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
 245                 vxlan_enable = 1;
 246
 247         qed_set_gre_enable(p_hwfn, p_ptt, l2gre_enable, ipgre_enable);
 248         qed_set_vxlan_enable(p_hwfn, p_ptt, vxlan_enable);
 249
 250         if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
 251                 l2geneve_enable = 1;
 252
 253         if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
 254                 ipgeneve_enable = 1;
 255
 256         qed_set_geneve_enable(p_hwfn, p_ptt, l2geneve_enable,
 257                               ipgeneve_enable);
 258 }
 259
 260 static void
 261 qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn,
 262                              struct qed_tunn_start_params *p_src,
 263                              struct pf_start_tunnel_config *p_tunn_cfg)
 264 {
 265         unsigned long tunn_mode;
 266         enum tunnel_clss type;
 267
 268         if (!p_src)
 269                 return;
 270
 271         tunn_mode = p_src->tunn_mode;
 272         type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan);
 273         p_tunn_cfg->tunnel_clss_vxlan = type;
 274         type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre);
 275         p_tunn_cfg->tunnel_clss_l2gre = type;
 276         type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre);
 277         p_tunn_cfg->tunnel_clss_ipgre = type;
 278
 279         if (p_src->update_vxlan_udp_port) {
 280                 p_tunn_cfg->set_vxlan_udp_port_flg = 1;
 281                 p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port);
 282         }
 283
 284         if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
 285                 p_tunn_cfg->tx_enable_l2gre = 1;
 286
 287         if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
 288                 p_tunn_cfg->tx_enable_ipgre = 1;
 289
 290         if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
 291                 p_tunn_cfg->tx_enable_vxlan = 1;
 292
 293         if (p_src->update_geneve_udp_port) {
 294                 p_tunn_cfg->set_geneve_udp_port_flg = 1;
 295                 p_tunn_cfg->geneve_udp_port =
 296                                 cpu_to_le16(p_src->geneve_udp_port);
 297         }
 298
 299         if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
 300                 p_tunn_cfg->tx_enable_l2geneve = 1;
 301
 302         if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
 303                 p_tunn_cfg->tx_enable_ipgeneve = 1;
 304
 305         type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve);
 306         p_tunn_cfg->tunnel_clss_l2geneve = type;
 307         type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);
 308         p_tunn_cfg->tunnel_clss_ipgeneve = type;
 309 }
 310
 311 int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
 312                     struct qed_tunn_start_params *p_tunn,
 313                     enum qed_mf_mode mode, bool allow_npar_tx_switch)
 314 {
 315         struct pf_start_ramrod_data *p_ramrod = NULL;
 316         u16 sb = qed_int_get_sp_sb_id(p_hwfn);
 317         u8 sb_index = p_hwfn->p_eq->eq_sb_index;
 318         struct qed_spq_entry *p_ent = NULL;
 319         struct qed_sp_init_data init_data;
 320         int rc = -EINVAL;
 321         u8 page_cnt;
 322
 323         /* update initial eq producer */
 324         qed_eq_prod_update(p_hwfn,
 325                            qed_chain_get_prod_idx(&p_hwfn->p_eq->chain));
 326
 327         memset(&init_data, 0, sizeof(init_data));
 328         init_data.cid = qed_spq_get_cid(p_hwfn);
 329         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 330         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
 331
 332         rc = qed_sp_init_request(p_hwfn, &p_ent,
 333                                  COMMON_RAMROD_PF_START,
 334                                  PROTOCOLID_COMMON, &init_data);
 335         if (rc)
 336                 return rc;
 337
 338         p_ramrod = &p_ent->ramrod.pf_start;
 339
 340         p_ramrod->event_ring_sb_id      = cpu_to_le16(sb);
 341         p_ramrod->event_ring_sb_index   = sb_index;
 342         p_ramrod->path_id               = QED_PATH_ID(p_hwfn);
 343         p_ramrod->dont_log_ramrods      = 0;
 344         p_ramrod->log_type_mask         = cpu_to_le16(0xf);
 345
 346         switch (mode) {
 347         case QED_MF_DEFAULT:
 348         case QED_MF_NPAR:
 349                 p_ramrod->mf_mode = MF_NPAR;
 350                 break;
 351         case QED_MF_OVLAN:
 352                 p_ramrod->mf_mode = MF_OVLAN;
 353                 break;
 354         default:
 355                 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
 356                 p_ramrod->mf_mode = MF_NPAR;
 357         }
 358         p_ramrod->outer_tag = p_hwfn->hw_info.ovlan;
 359
 360         /* Place EQ address in RAMROD */
 361         DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
 362                        p_hwfn->p_eq->chain.pbl.p_phys_table);
 363         page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain);
 364         p_ramrod->event_ring_num_pages = page_cnt;
 365         DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
 366                        p_hwfn->p_consq->chain.pbl.p_phys_table);
 367
 368         qed_tunn_set_pf_start_params(p_hwfn, p_tunn, &p_ramrod->tunnel_config);
 369
 370         if (IS_MF_SI(p_hwfn))
 371                 p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
 372
 373         switch (p_hwfn->hw_info.personality) {
 374         case QED_PCI_ETH:
 375                 p_ramrod->personality = PERSONALITY_ETH;
 376                 break;
 377         case QED_PCI_ISCSI:
 378                 p_ramrod->personality = PERSONALITY_ISCSI;
 379                 break;
 380         case QED_PCI_ETH_ROCE:
 381                 p_ramrod->personality = PERSONALITY_RDMA_AND_ETH;
 382                 break;
 383         default:
 384                 DP_NOTICE(p_hwfn, "Unkown personality %d\n",
 385                           p_hwfn->hw_info.personality);
 386                 p_ramrod->personality = PERSONALITY_ETH;
 387         }
 388
 389         if (p_hwfn->cdev->p_iov_info) {
 390                 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
 391
 392                 p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf;
 393                 p_ramrod->num_vfs = (u8) p_iov->total_vfs;
 394         }
 395         p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
 396         p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;
 397
 398         DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
 399                    "Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n",
 400                    sb, sb_index, p_ramrod->outer_tag);
 401
 402         rc = qed_spq_post(p_hwfn, p_ent, NULL);
 403
 404         if (p_tunn) {
 405                 qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt,
 406                                      p_tunn->tunn_mode);
 407                 p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode;
 408         }
 409
 410         return rc;
 411 }
 412
 413 int qed_sp_pf_update(struct qed_hwfn *p_hwfn)
 414 {
 415         struct qed_spq_entry *p_ent = NULL;
 416         struct qed_sp_init_data init_data;
 417         int rc = -EINVAL;
 418
 419         /* Get SPQ entry */
 420         memset(&init_data, 0, sizeof(init_data));
 421         init_data.cid = qed_spq_get_cid(p_hwfn);
 422         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 423         init_data.comp_mode = QED_SPQ_MODE_CB;
 424
 425         rc = qed_sp_init_request(p_hwfn, &p_ent,
 426                                  COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
 427                                  &init_data);
 428         if (rc)
 429                 return rc;
 430
 431         qed_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,
 432                                       &p_ent->ramrod.pf_update);
 433
 434         return qed_spq_post(p_hwfn, p_ent, NULL);
 435 }
 436
 437 /* Set pf update ramrod command params */
 438 int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn,
 439                               struct qed_tunn_update_params *p_tunn,
 440                               enum spq_mode comp_mode,
 441                               struct qed_spq_comp_cb *p_comp_data)
 442 {
 443         struct qed_spq_entry *p_ent = NULL;
 444         struct qed_sp_init_data init_data;
 445         int rc = -EINVAL;
 446
 447         /* Get SPQ entry */
 448         memset(&init_data, 0, sizeof(init_data));
 449         init_data.cid = qed_spq_get_cid(p_hwfn);
 450         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 451         init_data.comp_mode = comp_mode;
 452         init_data.p_comp_data = p_comp_data;
 453
 454         rc = qed_sp_init_request(p_hwfn, &p_ent,
 455                                  COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
 456                                  &init_data);
 457         if (rc)
 458                 return rc;
 459
 460         qed_tunn_set_pf_update_params(p_hwfn, p_tunn,
 461                                       &p_ent->ramrod.pf_update.tunnel_config);
 462
 463         rc = qed_spq_post(p_hwfn, p_ent, NULL);
 464         if (rc)
 465                 return rc;
 466
 467         if (p_tunn->update_vxlan_udp_port)
 468                 qed_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt,
 469                                         p_tunn->vxlan_udp_port);
 470         if (p_tunn->update_geneve_udp_port)
 471                 qed_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt,
 472                                          p_tunn->geneve_udp_port);
 473
 474         qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt, p_tunn->tunn_mode);
 475         p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode;
 476
 477         return rc;
 478 }
 479
 480 int qed_sp_pf_stop(struct qed_hwfn *p_hwfn)
 481 {
 482         struct qed_spq_entry *p_ent = NULL;
 483         struct qed_sp_init_data init_data;
 484         int rc = -EINVAL;
 485
 486         /* Get SPQ entry */
 487         memset(&init_data, 0, sizeof(init_data));
 488         init_data.cid = qed_spq_get_cid(p_hwfn);
 489         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 490         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
 491
 492         rc = qed_sp_init_request(p_hwfn, &p_ent,
 493                                  COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
 494                                  &init_data);
 495         if (rc)
 496                 return rc;
 497
 498         return qed_spq_post(p_hwfn, p_ent, NULL);
 499 }
 500
 501 int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn)
 502 {
 503         struct qed_spq_entry *p_ent = NULL;
 504         struct qed_sp_init_data init_data;
 505         int rc;
 506
 507         /* Get SPQ entry */
 508         memset(&init_data, 0, sizeof(init_data));
 509         init_data.cid = qed_spq_get_cid(p_hwfn);
 510         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 511         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
 512
 513         rc = qed_sp_init_request(p_hwfn, &p_ent,
 514                                  COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
 515                                  &init_data);
 516         if (rc)
 517                 return rc;
 518
 519         return qed_spq_post(p_hwfn, p_ent, NULL);
 520 }