1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
12 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
15 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \
18 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
21 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \
24 #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
27 #define CDU_REG_CID_ADDR_PARAMS_NCIB ( \
30 #define CDU_REG_SEGMENT0_PARAMS \
32 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \
34 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \
36 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \
38 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \
40 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \
42 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \
44 #define CDU_REG_SEGMENT1_PARAMS \
46 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \
48 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \
50 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \
52 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \
54 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \
56 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \
59 #define XSDM_REG_OPERATION_GEN \
61 #define NIG_REG_RX_BRB_OUT_EN \
63 #define NIG_REG_STORM_OUT_EN \
65 #define PSWRQ2_REG_L2P_VALIDATE_VFID \
67 #define PGLUE_B_REG_USE_CLIENTID_IN_TAG \
69 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
71 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
73 #define PSWHST_REG_ZONE_PERMISSION_TABLE \
75 #define BAR0_MAP_REG_MSDM_RAM \
77 #define BAR0_MAP_REG_USDM_RAM \
79 #define BAR0_MAP_REG_PSDM_RAM \
81 #define BAR0_MAP_REG_TSDM_RAM \
83 #define BAR0_MAP_REG_XSDM_RAM \
85 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
87 #define PRS_REG_SEARCH_TCP \
89 #define PRS_REG_SEARCH_UDP \
91 #define PRS_REG_SEARCH_FCOE \
93 #define PRS_REG_SEARCH_ROCE \
95 #define PRS_REG_SEARCH_OPENFLOW \
97 #define TM_REG_PF_ENABLE_CONN \
99 #define TM_REG_PF_ENABLE_TASK \
101 #define TM_REG_PF_SCAN_ACTIVE_CONN \
103 #define TM_REG_PF_SCAN_ACTIVE_TASK \
105 #define IGU_REG_LEADING_EDGE_LATCH \
107 #define IGU_REG_TRAILING_EDGE_LATCH \
109 #define QM_REG_USG_CNT_PF_TX \
111 #define QM_REG_USG_CNT_PF_OTHER \
113 #define DORQ_REG_PF_DB_ENABLE \
115 #define DORQ_REG_VF_USAGE_CNT \
117 #define QM_REG_PF_EN \
119 #define TCFC_REG_WEAK_ENABLE_VF \
121 #define TCFC_REG_STRONG_ENABLE_PF \
123 #define TCFC_REG_STRONG_ENABLE_VF \
125 #define CCFC_REG_WEAK_ENABLE_VF \
127 #define CCFC_REG_STRONG_ENABLE_PF \
129 #define PGLUE_B_REG_PGL_ADDR_88_F0 \
131 #define PGLUE_B_REG_PGL_ADDR_8C_F0 \
133 #define PGLUE_B_REG_PGL_ADDR_90_F0 \
135 #define PGLUE_B_REG_PGL_ADDR_94_F0 \
137 #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
139 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
141 #define MISC_REG_GEN_PURP_CR0 \
143 #define MCP_REG_SCRATCH \
145 #define CNIG_REG_NW_PORT_MODE_BB_B0 \
147 #define MISCS_REG_CHIP_NUM \
149 #define MISCS_REG_CHIP_REV \
151 #define MISCS_REG_CMT_ENABLED_FOR_PAIR \
153 #define MISCS_REG_CHIP_TEST_REG \
155 #define MISCS_REG_CHIP_METAL \
157 #define MISCS_REG_FUNCTION_HIDE \
159 #define BRB_REG_HEADER_SIZE \
161 #define BTB_REG_HEADER_SIZE \
163 #define CAU_REG_LONG_TIMEOUT_THRESHOLD \
165 #define CCFC_REG_ACTIVITY_COUNTER \
167 #define CCFC_REG_STRONG_ENABLE_VF \
169 #define CDU_REG_CID_ADDR_PARAMS \
171 #define DBG_REG_CLIENT_ENABLE \
173 #define DMAE_REG_INIT \
175 #define DORQ_REG_IFEN \
177 #define DORQ_REG_DB_DROP_REASON \
179 #define DORQ_REG_DB_DROP_DETAILS \
181 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \
183 #define GRC_REG_TIMEOUT_EN \
185 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \
187 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \
189 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \
191 #define IGU_REG_BLOCK_CONFIGURATION \
193 #define MCM_REG_INIT \
195 #define MCP2_REG_DBG_DWORD_ENABLE \
197 #define MISC_REG_PORT_MODE \
199 #define MISCS_REG_CLK_100G_MODE \
201 #define MSDM_REG_ENABLE_IN1 \
203 #define MSEM_REG_ENABLE_IN \
205 #define NIG_REG_CM_HDR \
207 #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \
209 #define NIG_REG_LLH_CLS_TYPE_DUALMODE \
211 #define NIG_REG_LLH_FUNC_FILTER_VALUE \
213 #define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE \
215 #define NIG_REG_LLH_FUNC_FILTER_EN \
217 #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE \
219 #define NIG_REG_LLH_FUNC_FILTER_MODE \
221 #define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE \
223 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE \
225 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE \
227 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL \
229 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE \
231 #define NCSI_REG_CONFIG \
233 #define PBF_REG_INIT \
235 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \
237 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \
239 #define PTU_REG_ATC_INIT_ARRAY \
241 #define PCM_REG_INIT \
243 #define PGLUE_B_REG_ADMIN_PER_PF_REGION \
245 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \
247 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \
249 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \
251 #define PGLUE_B_REG_TX_ERR_WR_DETAILS \
253 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \
255 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \
257 #define PGLUE_B_REG_TX_ERR_RD_DETAILS \
259 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \
261 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \
263 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \
265 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \
267 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \
269 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \
271 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \
273 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \
275 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \
277 #define PGLUE_B_REG_LATCHED_ERRORS_CLR \
279 #define PRM_REG_DISABLE_PRM \
281 #define PRS_REG_SOFT_RST \
283 #define PRS_REG_MSG_INFO \
285 #define PRS_REG_ROCE_DEST_QP_MAX_PF \
287 #define PRS_REG_USE_LIGHT_L2 \
289 #define PSDM_REG_ENABLE_IN1 \
291 #define PSEM_REG_ENABLE_IN \
293 #define PSWRQ_REG_DBG_SELECT \
295 #define PSWRQ2_REG_CDUT_P_SIZE \
297 #define PSWRQ2_REG_ILT_MEMORY \
299 #define PSWHST_REG_DISCARD_INTERNAL_WRITES \
301 #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
303 #define PSWHST_REG_INCORRECT_ACCESS_VALID \
305 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \
307 #define PSWHST_REG_INCORRECT_ACCESS_DATA \
309 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \
311 #define PSWRD_REG_DBG_SELECT \
313 #define PSWRD2_REG_CONF11 \
315 #define PSWWR_REG_USDM_FULL_TH \
317 #define PSWWR2_REG_CDU_FULL_TH2 \
319 #define QM_REG_MAXPQSIZE_0 \
321 #define RSS_REG_RSS_INIT_EN \
323 #define RDIF_REG_STOP_ON_ERROR \
325 #define SRC_REG_SOFT_RST \
327 #define TCFC_REG_ACTIVITY_COUNTER \
329 #define TCM_REG_INIT \
331 #define TM_REG_PXP_READ_DATA_FIFO_INIT \
333 #define TSDM_REG_ENABLE_IN1 \
335 #define TSEM_REG_ENABLE_IN \
337 #define TDIF_REG_STOP_ON_ERROR \
339 #define UCM_REG_INIT \
341 #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
343 #define USDM_REG_ENABLE_IN1 \
345 #define USEM_REG_ENABLE_IN \
347 #define XCM_REG_INIT \
349 #define XSDM_REG_ENABLE_IN1 \
351 #define XSEM_REG_ENABLE_IN \
353 #define YCM_REG_INIT \
355 #define YSDM_REG_ENABLE_IN1 \
357 #define YSEM_REG_ENABLE_IN \
359 #define XYLD_REG_SCBD_STRICT_PRIO \
361 #define TMLD_REG_SCBD_STRICT_PRIO \
363 #define MULD_REG_SCBD_STRICT_PRIO \
365 #define YULD_REG_SCBD_STRICT_PRIO \
367 #define MISC_REG_SHARED_MEM_ADDR \
369 #define DMAE_REG_GO_C0 \
371 #define DMAE_REG_GO_C1 \
373 #define DMAE_REG_GO_C2 \
375 #define DMAE_REG_GO_C3 \
377 #define DMAE_REG_GO_C4 \
379 #define DMAE_REG_GO_C5 \
381 #define DMAE_REG_GO_C6 \
383 #define DMAE_REG_GO_C7 \
385 #define DMAE_REG_GO_C8 \
387 #define DMAE_REG_GO_C9 \
389 #define DMAE_REG_GO_C10 \
391 #define DMAE_REG_GO_C11 \
393 #define DMAE_REG_GO_C12 \
395 #define DMAE_REG_GO_C13 \
397 #define DMAE_REG_GO_C14 \
399 #define DMAE_REG_GO_C15 \
401 #define DMAE_REG_GO_C16 \
403 #define DMAE_REG_GO_C17 \
405 #define DMAE_REG_GO_C18 \
407 #define DMAE_REG_GO_C19 \
409 #define DMAE_REG_GO_C20 \
411 #define DMAE_REG_GO_C21 \
413 #define DMAE_REG_GO_C22 \
415 #define DMAE_REG_GO_C23 \
417 #define DMAE_REG_GO_C24 \
419 #define DMAE_REG_GO_C25 \
421 #define DMAE_REG_GO_C26 \
423 #define DMAE_REG_GO_C27 \
425 #define DMAE_REG_GO_C28 \
427 #define DMAE_REG_GO_C29 \
429 #define DMAE_REG_GO_C30 \
431 #define DMAE_REG_GO_C31 \
433 #define DMAE_REG_CMD_MEM \
435 #define QM_REG_MAXPQSIZETXSEL_0 \
437 #define QM_REG_SDMCMDREADY \
439 #define QM_REG_SDMCMDADDR \
441 #define QM_REG_SDMCMDDATALSB \
443 #define QM_REG_SDMCMDDATAMSB \
445 #define QM_REG_SDMCMDGO \
447 #define QM_REG_RLPFCRD \
449 #define QM_REG_RLPFINCVAL \
451 #define QM_REG_RLGLBLCRD \
453 #define QM_REG_RLGLBLINCVAL \
455 #define IGU_REG_ATTENTION_ENABLE \
457 #define IGU_REG_ATTN_MSG_ADDR_L \
459 #define IGU_REG_ATTN_MSG_ADDR_H \
461 #define MISC_REG_AEU_GENERAL_ATTN_0 \
463 #define CAU_REG_SB_ADDR_MEMORY \
465 #define CAU_REG_SB_VAR_MEMORY \
467 #define CAU_REG_PI_MEMORY \
469 #define IGU_REG_PF_CONFIGURATION \
471 #define IGU_REG_VF_CONFIGURATION \
473 #define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
475 #define MISC_REG_AEU_AFTER_INVERT_1_IGU \
477 #define MISC_REG_AEU_MASK_ATTN_IGU \
479 #define IGU_REG_CLEANUP_STATUS_0 \
481 #define IGU_REG_CLEANUP_STATUS_1 \
483 #define IGU_REG_CLEANUP_STATUS_2 \
485 #define IGU_REG_CLEANUP_STATUS_3 \
487 #define IGU_REG_CLEANUP_STATUS_4 \
489 #define IGU_REG_COMMAND_REG_32LSB_DATA \
491 #define IGU_REG_COMMAND_REG_CTRL \
493 #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \
495 #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \
497 #define IGU_REG_MAPPING_MEMORY \
499 #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \
501 #define IGU_REG_WRITE_DONE_PENDING \
503 #define MISCS_REG_GENERIC_POR_0 \
505 #define MCP_REG_NVM_CFG4 \
507 #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \
509 #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
511 #define MCP_REG_CPU_STATE \
513 #define MCP_REG_CPU_STATE_SOFT_HALTED (0x1UL << 10)
514 #define MCP_REG_CPU_EVENT_MASK \
516 #define PGLUE_B_REG_PF_BAR0_SIZE \
518 #define PGLUE_B_REG_PF_BAR1_SIZE \
520 #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
521 #define PRS_REG_GRE_PROTOCOL 0x1f0734UL
522 #define PRS_REG_VXLAN_PORT 0x1f0738UL
523 #define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
524 #define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
526 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0)
527 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0
528 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1)
529 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1
530 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2)
531 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2
533 #define NIG_REG_VXLAN_CTRL 0x50105cUL
534 #define PBF_REG_VXLAN_PORT 0xd80518UL
535 #define PBF_REG_NGE_PORT 0xd8051cUL
536 #define PRS_REG_NGE_PORT 0x1f086cUL
537 #define NIG_REG_NGE_PORT 0x508b38UL
539 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
540 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
541 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
542 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL
543 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL
545 #define NIG_REG_NGE_IP_ENABLE 0x508b28UL
546 #define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL
547 #define NIG_REG_NGE_COMP_VER 0x508b30UL
548 #define PBF_REG_NGE_COMP_VER 0xd80524UL
549 #define PRS_REG_NGE_COMP_VER 0x1f0878UL
551 #define QM_REG_WFQPFWEIGHT 0x2f4e80UL
552 #define QM_REG_WFQVPWEIGHT 0x2fa000UL
554 #define PGLCS_REG_DBG_SELECT \
556 #define PGLCS_REG_DBG_DWORD_ENABLE \
558 #define PGLCS_REG_DBG_SHIFT \
560 #define PGLCS_REG_DBG_FORCE_VALID \
562 #define PGLCS_REG_DBG_FORCE_FRAME \
564 #define MISC_REG_RESET_PL_PDA_VMAIN_1 \
566 #define MISC_REG_RESET_PL_PDA_VMAIN_2 \
568 #define MISC_REG_RESET_PL_PDA_VAUX \
570 #define MISCS_REG_RESET_PL_UA \
572 #define MISCS_REG_RESET_PL_HV \
574 #define MISCS_REG_RESET_PL_HV_2 \
576 #define DMAE_REG_DBG_SELECT \
578 #define DMAE_REG_DBG_DWORD_ENABLE \
580 #define DMAE_REG_DBG_SHIFT \
582 #define DMAE_REG_DBG_FORCE_VALID \
584 #define DMAE_REG_DBG_FORCE_FRAME \
586 #define NCSI_REG_DBG_SELECT \
588 #define NCSI_REG_DBG_DWORD_ENABLE \
590 #define NCSI_REG_DBG_SHIFT \
592 #define NCSI_REG_DBG_FORCE_VALID \
594 #define NCSI_REG_DBG_FORCE_FRAME \
596 #define GRC_REG_DBG_SELECT \
598 #define GRC_REG_DBG_DWORD_ENABLE \
600 #define GRC_REG_DBG_SHIFT \
602 #define GRC_REG_DBG_FORCE_VALID \
604 #define GRC_REG_DBG_FORCE_FRAME \
606 #define UMAC_REG_DBG_SELECT \
608 #define UMAC_REG_DBG_DWORD_ENABLE \
610 #define UMAC_REG_DBG_SHIFT \
612 #define UMAC_REG_DBG_FORCE_VALID \
614 #define UMAC_REG_DBG_FORCE_FRAME \
616 #define MCP2_REG_DBG_SELECT \
618 #define MCP2_REG_DBG_DWORD_ENABLE \
620 #define MCP2_REG_DBG_SHIFT \
622 #define MCP2_REG_DBG_FORCE_VALID \
624 #define MCP2_REG_DBG_FORCE_FRAME \
626 #define PCIE_REG_DBG_SELECT \
628 #define PCIE_REG_DBG_DWORD_ENABLE \
630 #define PCIE_REG_DBG_SHIFT \
632 #define PCIE_REG_DBG_FORCE_VALID \
634 #define PCIE_REG_DBG_FORCE_FRAME \
636 #define DORQ_REG_DBG_SELECT \
638 #define DORQ_REG_DBG_DWORD_ENABLE \
640 #define DORQ_REG_DBG_SHIFT \
642 #define DORQ_REG_DBG_FORCE_VALID \
644 #define DORQ_REG_DBG_FORCE_FRAME \
646 #define IGU_REG_DBG_SELECT \
648 #define IGU_REG_DBG_DWORD_ENABLE \
650 #define IGU_REG_DBG_SHIFT \
652 #define IGU_REG_DBG_FORCE_VALID \
654 #define IGU_REG_DBG_FORCE_FRAME \
656 #define CAU_REG_DBG_SELECT \
658 #define CAU_REG_DBG_DWORD_ENABLE \
660 #define CAU_REG_DBG_SHIFT \
662 #define CAU_REG_DBG_FORCE_VALID \
664 #define CAU_REG_DBG_FORCE_FRAME \
666 #define PRS_REG_DBG_SELECT \
668 #define PRS_REG_DBG_DWORD_ENABLE \
670 #define PRS_REG_DBG_SHIFT \
672 #define PRS_REG_DBG_FORCE_VALID \
674 #define PRS_REG_DBG_FORCE_FRAME \
676 #define CNIG_REG_DBG_SELECT_K2 \
678 #define CNIG_REG_DBG_DWORD_ENABLE_K2 \
680 #define CNIG_REG_DBG_SHIFT_K2 \
682 #define CNIG_REG_DBG_FORCE_VALID_K2 \
684 #define CNIG_REG_DBG_FORCE_FRAME_K2 \
686 #define PRM_REG_DBG_SELECT \
688 #define PRM_REG_DBG_DWORD_ENABLE \
690 #define PRM_REG_DBG_SHIFT \
692 #define PRM_REG_DBG_FORCE_VALID \
694 #define PRM_REG_DBG_FORCE_FRAME \
696 #define SRC_REG_DBG_SELECT \
698 #define SRC_REG_DBG_DWORD_ENABLE \
700 #define SRC_REG_DBG_SHIFT \
702 #define SRC_REG_DBG_FORCE_VALID \
704 #define SRC_REG_DBG_FORCE_FRAME \
706 #define RSS_REG_DBG_SELECT \
708 #define RSS_REG_DBG_DWORD_ENABLE \
710 #define RSS_REG_DBG_SHIFT \
712 #define RSS_REG_DBG_FORCE_VALID \
714 #define RSS_REG_DBG_FORCE_FRAME \
716 #define RPB_REG_DBG_SELECT \
718 #define RPB_REG_DBG_DWORD_ENABLE \
720 #define RPB_REG_DBG_SHIFT \
722 #define RPB_REG_DBG_FORCE_VALID \
724 #define RPB_REG_DBG_FORCE_FRAME \
726 #define PSWRQ2_REG_DBG_SELECT \
728 #define PSWRQ2_REG_DBG_DWORD_ENABLE \
730 #define PSWRQ2_REG_DBG_SHIFT \
732 #define PSWRQ2_REG_DBG_FORCE_VALID \
734 #define PSWRQ2_REG_DBG_FORCE_FRAME \
736 #define PSWRQ_REG_DBG_SELECT \
738 #define PSWRQ_REG_DBG_DWORD_ENABLE \
740 #define PSWRQ_REG_DBG_SHIFT \
742 #define PSWRQ_REG_DBG_FORCE_VALID \
744 #define PSWRQ_REG_DBG_FORCE_FRAME \
746 #define PSWWR_REG_DBG_SELECT \
748 #define PSWWR_REG_DBG_DWORD_ENABLE \
750 #define PSWWR_REG_DBG_SHIFT \
752 #define PSWWR_REG_DBG_FORCE_VALID \
754 #define PSWWR_REG_DBG_FORCE_FRAME \
756 #define PSWRD_REG_DBG_SELECT \
758 #define PSWRD_REG_DBG_DWORD_ENABLE \
760 #define PSWRD_REG_DBG_SHIFT \
762 #define PSWRD_REG_DBG_FORCE_VALID \
764 #define PSWRD_REG_DBG_FORCE_FRAME \
766 #define PSWRD2_REG_DBG_SELECT \
768 #define PSWRD2_REG_DBG_DWORD_ENABLE \
770 #define PSWRD2_REG_DBG_SHIFT \
772 #define PSWRD2_REG_DBG_FORCE_VALID \
774 #define PSWRD2_REG_DBG_FORCE_FRAME \
776 #define PSWHST2_REG_DBG_SELECT \
778 #define PSWHST2_REG_DBG_DWORD_ENABLE \
780 #define PSWHST2_REG_DBG_SHIFT \
782 #define PSWHST2_REG_DBG_FORCE_VALID \
784 #define PSWHST2_REG_DBG_FORCE_FRAME \
786 #define PSWHST_REG_DBG_SELECT \
788 #define PSWHST_REG_DBG_DWORD_ENABLE \
790 #define PSWHST_REG_DBG_SHIFT \
792 #define PSWHST_REG_DBG_FORCE_VALID \
794 #define PSWHST_REG_DBG_FORCE_FRAME \
796 #define PGLUE_B_REG_DBG_SELECT \
798 #define PGLUE_B_REG_DBG_DWORD_ENABLE \
800 #define PGLUE_B_REG_DBG_SHIFT \
802 #define PGLUE_B_REG_DBG_FORCE_VALID \
804 #define PGLUE_B_REG_DBG_FORCE_FRAME \
806 #define TM_REG_DBG_SELECT \
808 #define TM_REG_DBG_DWORD_ENABLE \
810 #define TM_REG_DBG_SHIFT \
812 #define TM_REG_DBG_FORCE_VALID \
814 #define TM_REG_DBG_FORCE_FRAME \
816 #define TCFC_REG_DBG_SELECT \
818 #define TCFC_REG_DBG_DWORD_ENABLE \
820 #define TCFC_REG_DBG_SHIFT \
822 #define TCFC_REG_DBG_FORCE_VALID \
824 #define TCFC_REG_DBG_FORCE_FRAME \
826 #define CCFC_REG_DBG_SELECT \
828 #define CCFC_REG_DBG_DWORD_ENABLE \
830 #define CCFC_REG_DBG_SHIFT \
832 #define CCFC_REG_DBG_FORCE_VALID \
834 #define CCFC_REG_DBG_FORCE_FRAME \
836 #define QM_REG_DBG_SELECT \
838 #define QM_REG_DBG_DWORD_ENABLE \
840 #define QM_REG_DBG_SHIFT \
842 #define QM_REG_DBG_FORCE_VALID \
844 #define QM_REG_DBG_FORCE_FRAME \
846 #define RDIF_REG_DBG_SELECT \
848 #define RDIF_REG_DBG_DWORD_ENABLE \
850 #define RDIF_REG_DBG_SHIFT \
852 #define RDIF_REG_DBG_FORCE_VALID \
854 #define RDIF_REG_DBG_FORCE_FRAME \
856 #define TDIF_REG_DBG_SELECT \
858 #define TDIF_REG_DBG_DWORD_ENABLE \
860 #define TDIF_REG_DBG_SHIFT \
862 #define TDIF_REG_DBG_FORCE_VALID \
864 #define TDIF_REG_DBG_FORCE_FRAME \
866 #define BRB_REG_DBG_SELECT \
868 #define BRB_REG_DBG_DWORD_ENABLE \
870 #define BRB_REG_DBG_SHIFT \
872 #define BRB_REG_DBG_FORCE_VALID \
874 #define BRB_REG_DBG_FORCE_FRAME \
876 #define XYLD_REG_DBG_SELECT \
878 #define XYLD_REG_DBG_DWORD_ENABLE \
880 #define XYLD_REG_DBG_SHIFT \
882 #define XYLD_REG_DBG_FORCE_VALID \
884 #define XYLD_REG_DBG_FORCE_FRAME \
886 #define YULD_REG_DBG_SELECT \
888 #define YULD_REG_DBG_DWORD_ENABLE \
890 #define YULD_REG_DBG_SHIFT \
892 #define YULD_REG_DBG_FORCE_VALID \
894 #define YULD_REG_DBG_FORCE_FRAME \
896 #define TMLD_REG_DBG_SELECT \
898 #define TMLD_REG_DBG_DWORD_ENABLE \
900 #define TMLD_REG_DBG_SHIFT \
902 #define TMLD_REG_DBG_FORCE_VALID \
904 #define TMLD_REG_DBG_FORCE_FRAME \
906 #define MULD_REG_DBG_SELECT \
908 #define MULD_REG_DBG_DWORD_ENABLE \
910 #define MULD_REG_DBG_SHIFT \
912 #define MULD_REG_DBG_FORCE_VALID \
914 #define MULD_REG_DBG_FORCE_FRAME \
916 #define NIG_REG_DBG_SELECT \
918 #define NIG_REG_DBG_DWORD_ENABLE \
920 #define NIG_REG_DBG_SHIFT \
922 #define NIG_REG_DBG_FORCE_VALID \
924 #define NIG_REG_DBG_FORCE_FRAME \
926 #define BMB_REG_DBG_SELECT \
928 #define BMB_REG_DBG_DWORD_ENABLE \
930 #define BMB_REG_DBG_SHIFT \
932 #define BMB_REG_DBG_FORCE_VALID \
934 #define BMB_REG_DBG_FORCE_FRAME \
936 #define PTU_REG_DBG_SELECT \
938 #define PTU_REG_DBG_DWORD_ENABLE \
940 #define PTU_REG_DBG_SHIFT \
942 #define PTU_REG_DBG_FORCE_VALID \
944 #define PTU_REG_DBG_FORCE_FRAME \
946 #define CDU_REG_DBG_SELECT \
948 #define CDU_REG_DBG_DWORD_ENABLE \
950 #define CDU_REG_DBG_SHIFT \
952 #define CDU_REG_DBG_FORCE_VALID \
954 #define CDU_REG_DBG_FORCE_FRAME \
956 #define WOL_REG_DBG_SELECT \
958 #define WOL_REG_DBG_DWORD_ENABLE \
960 #define WOL_REG_DBG_SHIFT \
962 #define WOL_REG_DBG_FORCE_VALID \
964 #define WOL_REG_DBG_FORCE_FRAME \
966 #define BMBN_REG_DBG_SELECT \
968 #define BMBN_REG_DBG_DWORD_ENABLE \
970 #define BMBN_REG_DBG_SHIFT \
972 #define BMBN_REG_DBG_FORCE_VALID \
974 #define BMBN_REG_DBG_FORCE_FRAME \
976 #define NWM_REG_DBG_SELECT \
978 #define NWM_REG_DBG_DWORD_ENABLE \
980 #define NWM_REG_DBG_SHIFT \
982 #define NWM_REG_DBG_FORCE_VALID \
984 #define NWM_REG_DBG_FORCE_FRAME \
986 #define PBF_REG_DBG_SELECT \
988 #define PBF_REG_DBG_DWORD_ENABLE \
990 #define PBF_REG_DBG_SHIFT \
992 #define PBF_REG_DBG_FORCE_VALID \
994 #define PBF_REG_DBG_FORCE_FRAME \
996 #define PBF_PB1_REG_DBG_SELECT \
998 #define PBF_PB1_REG_DBG_DWORD_ENABLE \
1000 #define PBF_PB1_REG_DBG_SHIFT \
1002 #define PBF_PB1_REG_DBG_FORCE_VALID \
1004 #define PBF_PB1_REG_DBG_FORCE_FRAME \
1006 #define PBF_PB2_REG_DBG_SELECT \
1008 #define PBF_PB2_REG_DBG_DWORD_ENABLE \
1010 #define PBF_PB2_REG_DBG_SHIFT \
1012 #define PBF_PB2_REG_DBG_FORCE_VALID \
1014 #define PBF_PB2_REG_DBG_FORCE_FRAME \
1016 #define BTB_REG_DBG_SELECT \
1018 #define BTB_REG_DBG_DWORD_ENABLE \
1020 #define BTB_REG_DBG_SHIFT \
1022 #define BTB_REG_DBG_FORCE_VALID \
1024 #define BTB_REG_DBG_FORCE_FRAME \
1026 #define XSDM_REG_DBG_SELECT \
1028 #define XSDM_REG_DBG_DWORD_ENABLE \
1030 #define XSDM_REG_DBG_SHIFT \
1032 #define XSDM_REG_DBG_FORCE_VALID \
1034 #define XSDM_REG_DBG_FORCE_FRAME \
1036 #define YSDM_REG_DBG_SELECT \
1038 #define YSDM_REG_DBG_DWORD_ENABLE \
1040 #define YSDM_REG_DBG_SHIFT \
1042 #define YSDM_REG_DBG_FORCE_VALID \
1044 #define YSDM_REG_DBG_FORCE_FRAME \
1046 #define PSDM_REG_DBG_SELECT \
1048 #define PSDM_REG_DBG_DWORD_ENABLE \
1050 #define PSDM_REG_DBG_SHIFT \
1052 #define PSDM_REG_DBG_FORCE_VALID \
1054 #define PSDM_REG_DBG_FORCE_FRAME \
1056 #define TSDM_REG_DBG_SELECT \
1058 #define TSDM_REG_DBG_DWORD_ENABLE \
1060 #define TSDM_REG_DBG_SHIFT \
1062 #define TSDM_REG_DBG_FORCE_VALID \
1064 #define TSDM_REG_DBG_FORCE_FRAME \
1066 #define MSDM_REG_DBG_SELECT \
1068 #define MSDM_REG_DBG_DWORD_ENABLE \
1070 #define MSDM_REG_DBG_SHIFT \
1072 #define MSDM_REG_DBG_FORCE_VALID \
1074 #define MSDM_REG_DBG_FORCE_FRAME \
1076 #define USDM_REG_DBG_SELECT \
1078 #define USDM_REG_DBG_DWORD_ENABLE \
1080 #define USDM_REG_DBG_SHIFT \
1082 #define USDM_REG_DBG_FORCE_VALID \
1084 #define USDM_REG_DBG_FORCE_FRAME \
1086 #define XCM_REG_DBG_SELECT \
1088 #define XCM_REG_DBG_DWORD_ENABLE \
1090 #define XCM_REG_DBG_SHIFT \
1092 #define XCM_REG_DBG_FORCE_VALID \
1094 #define XCM_REG_DBG_FORCE_FRAME \
1096 #define YCM_REG_DBG_SELECT \
1098 #define YCM_REG_DBG_DWORD_ENABLE \
1100 #define YCM_REG_DBG_SHIFT \
1102 #define YCM_REG_DBG_FORCE_VALID \
1104 #define YCM_REG_DBG_FORCE_FRAME \
1106 #define PCM_REG_DBG_SELECT \
1108 #define PCM_REG_DBG_DWORD_ENABLE \
1110 #define PCM_REG_DBG_SHIFT \
1112 #define PCM_REG_DBG_FORCE_VALID \
1114 #define PCM_REG_DBG_FORCE_FRAME \
1116 #define TCM_REG_DBG_SELECT \
1118 #define TCM_REG_DBG_DWORD_ENABLE \
1120 #define TCM_REG_DBG_SHIFT \
1122 #define TCM_REG_DBG_FORCE_VALID \
1124 #define TCM_REG_DBG_FORCE_FRAME \
1126 #define MCM_REG_DBG_SELECT \
1128 #define MCM_REG_DBG_DWORD_ENABLE \
1130 #define MCM_REG_DBG_SHIFT \
1132 #define MCM_REG_DBG_FORCE_VALID \
1134 #define MCM_REG_DBG_FORCE_FRAME \
1136 #define UCM_REG_DBG_SELECT \
1138 #define UCM_REG_DBG_DWORD_ENABLE \
1140 #define UCM_REG_DBG_SHIFT \
1142 #define UCM_REG_DBG_FORCE_VALID \
1144 #define UCM_REG_DBG_FORCE_FRAME \
1146 #define XSEM_REG_DBG_SELECT \
1148 #define XSEM_REG_DBG_DWORD_ENABLE \
1150 #define XSEM_REG_DBG_SHIFT \
1152 #define XSEM_REG_DBG_FORCE_VALID \
1154 #define XSEM_REG_DBG_FORCE_FRAME \
1156 #define YSEM_REG_DBG_SELECT \
1158 #define YSEM_REG_DBG_DWORD_ENABLE \
1160 #define YSEM_REG_DBG_SHIFT \
1162 #define YSEM_REG_DBG_FORCE_VALID \
1164 #define YSEM_REG_DBG_FORCE_FRAME \
1166 #define PSEM_REG_DBG_SELECT \
1168 #define PSEM_REG_DBG_DWORD_ENABLE \
1170 #define PSEM_REG_DBG_SHIFT \
1172 #define PSEM_REG_DBG_FORCE_VALID \
1174 #define PSEM_REG_DBG_FORCE_FRAME \
1176 #define TSEM_REG_DBG_SELECT \
1178 #define TSEM_REG_DBG_DWORD_ENABLE \
1180 #define TSEM_REG_DBG_SHIFT \
1182 #define TSEM_REG_DBG_FORCE_VALID \
1184 #define TSEM_REG_DBG_FORCE_FRAME \
1186 #define MSEM_REG_DBG_SELECT \
1188 #define MSEM_REG_DBG_DWORD_ENABLE \
1190 #define MSEM_REG_DBG_SHIFT \
1192 #define MSEM_REG_DBG_FORCE_VALID \
1194 #define MSEM_REG_DBG_FORCE_FRAME \
1196 #define USEM_REG_DBG_SELECT \
1198 #define USEM_REG_DBG_DWORD_ENABLE \
1200 #define USEM_REG_DBG_SHIFT \
1202 #define USEM_REG_DBG_FORCE_VALID \
1204 #define USEM_REG_DBG_FORCE_FRAME \
1206 #define PCIE_REG_DBG_COMMON_SELECT \
1208 #define PCIE_REG_DBG_COMMON_DWORD_ENABLE \
1210 #define PCIE_REG_DBG_COMMON_SHIFT \
1212 #define PCIE_REG_DBG_COMMON_FORCE_VALID \
1214 #define PCIE_REG_DBG_COMMON_FORCE_FRAME \
1216 #define MISC_REG_RESET_PL_UA \
1218 #define MISC_REG_RESET_PL_HV \
1220 #define XCM_REG_CTX_RBC_ACCS \
1222 #define XCM_REG_AGG_CON_CTX \
1224 #define XCM_REG_SM_CON_CTX \
1226 #define YCM_REG_CTX_RBC_ACCS \
1228 #define YCM_REG_AGG_CON_CTX \
1230 #define YCM_REG_AGG_TASK_CTX \
1232 #define YCM_REG_SM_CON_CTX \
1234 #define YCM_REG_SM_TASK_CTX \
1236 #define PCM_REG_CTX_RBC_ACCS \
1238 #define PCM_REG_SM_CON_CTX \
1240 #define TCM_REG_CTX_RBC_ACCS \
1242 #define TCM_REG_AGG_CON_CTX \
1244 #define TCM_REG_AGG_TASK_CTX \
1246 #define TCM_REG_SM_CON_CTX \
1248 #define TCM_REG_SM_TASK_CTX \
1250 #define MCM_REG_CTX_RBC_ACCS \
1252 #define MCM_REG_AGG_CON_CTX \
1254 #define MCM_REG_AGG_TASK_CTX \
1256 #define MCM_REG_SM_CON_CTX \
1258 #define MCM_REG_SM_TASK_CTX \
1260 #define UCM_REG_CTX_RBC_ACCS \
1262 #define UCM_REG_AGG_CON_CTX \
1264 #define UCM_REG_AGG_TASK_CTX \
1266 #define UCM_REG_SM_CON_CTX \
1268 #define UCM_REG_SM_TASK_CTX \
1270 #define XSEM_REG_SLOW_DBG_EMPTY \
1272 #define XSEM_REG_SYNC_DBG_EMPTY \
1274 #define XSEM_REG_SLOW_DBG_ACTIVE \
1276 #define XSEM_REG_SLOW_DBG_MODE \
1278 #define XSEM_REG_DBG_FRAME_MODE \
1280 #define XSEM_REG_DBG_MODE1_CFG \
1282 #define XSEM_REG_FAST_MEMORY \
1284 #define YSEM_REG_SYNC_DBG_EMPTY \
1286 #define YSEM_REG_SLOW_DBG_ACTIVE \
1288 #define YSEM_REG_SLOW_DBG_MODE \
1290 #define YSEM_REG_DBG_FRAME_MODE \
1292 #define YSEM_REG_DBG_MODE1_CFG \
1294 #define YSEM_REG_FAST_MEMORY \
1296 #define PSEM_REG_SLOW_DBG_EMPTY \
1298 #define PSEM_REG_SYNC_DBG_EMPTY \
1300 #define PSEM_REG_SLOW_DBG_ACTIVE \
1302 #define PSEM_REG_SLOW_DBG_MODE \
1304 #define PSEM_REG_DBG_FRAME_MODE \
1306 #define PSEM_REG_DBG_MODE1_CFG \
1308 #define PSEM_REG_FAST_MEMORY \
1310 #define TSEM_REG_SLOW_DBG_EMPTY \
1312 #define TSEM_REG_SYNC_DBG_EMPTY \
1314 #define TSEM_REG_SLOW_DBG_ACTIVE \
1316 #define TSEM_REG_SLOW_DBG_MODE \
1318 #define TSEM_REG_DBG_FRAME_MODE \
1320 #define TSEM_REG_DBG_MODE1_CFG \
1322 #define TSEM_REG_FAST_MEMORY \
1324 #define MSEM_REG_SLOW_DBG_EMPTY \
1326 #define MSEM_REG_SYNC_DBG_EMPTY \
1328 #define MSEM_REG_SLOW_DBG_ACTIVE \
1330 #define MSEM_REG_SLOW_DBG_MODE \
1332 #define MSEM_REG_DBG_FRAME_MODE \
1334 #define MSEM_REG_DBG_MODE1_CFG \
1336 #define MSEM_REG_FAST_MEMORY \
1338 #define USEM_REG_SLOW_DBG_EMPTY \
1340 #define USEM_REG_SYNC_DBG_EMPTY \
1342 #define USEM_REG_SLOW_DBG_ACTIVE \
1344 #define USEM_REG_SLOW_DBG_MODE \
1346 #define USEM_REG_DBG_FRAME_MODE \
1348 #define USEM_REG_DBG_MODE1_CFG \
1350 #define USEM_REG_FAST_MEMORY \
1352 #define SEM_FAST_REG_INT_RAM \
1354 #define SEM_FAST_REG_INT_RAM_SIZE \
1356 #define GRC_REG_TRACE_FIFO_VALID_DATA \
1358 #define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \
1360 #define GRC_REG_PROTECTION_OVERRIDE_WINDOW \
1362 #define IGU_REG_ERROR_HANDLING_MEMORY \
1364 #define MCP_REG_CPU_MODE \
1366 #define MCP_REG_CPU_MODE_SOFT_HALT \
1368 #define BRB_REG_BIG_RAM_ADDRESS \
1370 #define BRB_REG_BIG_RAM_DATA \
1372 #define SEM_FAST_REG_STALL_0 \
1374 #define SEM_FAST_REG_STALLED \
1376 #define BTB_REG_BIG_RAM_ADDRESS \
1378 #define BTB_REG_BIG_RAM_DATA \
1380 #define BMB_REG_BIG_RAM_ADDRESS \
1382 #define BMB_REG_BIG_RAM_DATA \
1384 #define SEM_FAST_REG_STORM_REG_FILE \
1386 #define RSS_REG_RSS_RAM_ADDR \
1388 #define MISCS_REG_BLOCK_256B_EN \
1390 #define MCP_REG_SCRATCH_SIZE \
1392 #define MCP_REG_CPU_REG_FILE \
1394 #define MCP_REG_CPU_REG_FILE_SIZE \
1396 #define DBG_REG_DEBUG_TARGET \
1398 #define DBG_REG_FULL_MODE \
1400 #define DBG_REG_CALENDAR_OUT_DATA \
1402 #define GRC_REG_TRACE_FIFO \
1404 #define IGU_REG_ERROR_HANDLING_DATA_VALID \
1406 #define DBG_REG_DBG_BLOCK_ON \
1408 #define DBG_REG_FRAMING_MODE \
1410 #define SEM_FAST_REG_VFC_DATA_WR \
1412 #define SEM_FAST_REG_VFC_ADDR \
1414 #define SEM_FAST_REG_VFC_DATA_RD \
1416 #define RSS_REG_RSS_RAM_DATA \
1418 #define MISC_REG_BLOCK_256B_EN \
1420 #define NWS_REG_NWS_CMU \
1422 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0 \
1424 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8 \
1426 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0 \
1428 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8 \
1430 #define MS_REG_MS_CMU \
1432 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130 \
1434 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132 \
1436 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131 \
1438 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133 \
1440 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130 \
1442 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131 \
1444 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132 \
1446 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133 \
1448 #define PHY_PCIE_REG_PHY0 \
1450 #define PHY_PCIE_REG_PHY1 \
1452 #define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL
1453 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL
1454 #define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL
1455 #define DORQ_REG_PF_DPM_ENABLE 0x100510UL
1456 #define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL
1457 #define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL
1458 #define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL