drivers/net/ethernet/qlogic/qed/qed_mcp.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #include <linux/types.h>
  10 #include <asm/byteorder.h>
  11 #include <linux/delay.h>
  12 #include <linux/errno.h>
  13 #include <linux/kernel.h>
  14 #include <linux/slab.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/string.h>
  17 #include "qed.h"
  18 #include "qed_dcbx.h"
  19 #include "qed_hsi.h"
  20 #include "qed_hw.h"
  21 #include "qed_mcp.h"
  22 #include "qed_reg_addr.h"
  23 #include "qed_sriov.h"
  24
  25 #define CHIP_MCP_RESP_ITER_US 10
  26
  27 #define QED_DRV_MB_MAX_RETRIES  (500 * 1000)    /* Account for 5 sec */
  28 #define QED_MCP_RESET_RETRIES   (50 * 1000)     /* Account for 500 msec */
  29
  30 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val)           \
  31         qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  32                _val)
  33
  34 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  35         qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  36
  37 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val)  \
  38         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  39                      offsetof(struct public_drv_mb, _field), _val)
  40
  41 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field)         \
  42         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  43                      offsetof(struct public_drv_mb, _field))
  44
  45 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  46                   DRV_ID_PDA_COMP_VER_SHIFT)
  47
  48 #define MCP_BYTES_PER_MBIT_SHIFT 17
  49
  50 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn)
  51 {
  52         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  53                 return false;
  54         return true;
  55 }
  56
  57 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
  58 {
  59         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  60                                         PUBLIC_PORT);
  61         u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr);
  62
  63         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  64                                                    MFW_PORT(p_hwfn));
  65         DP_VERBOSE(p_hwfn, QED_MSG_SP,
  66                    "port_addr = 0x%x, port_id 0x%02x\n",
  67                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  68 }
  69
  70 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
  71 {
  72         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  73         u32 tmp, i;
  74
  75         if (!p_hwfn->mcp_info->public_base)
  76                 return;
  77
  78         for (i = 0; i < length; i++) {
  79                 tmp = qed_rd(p_hwfn, p_ptt,
  80                              p_hwfn->mcp_info->mfw_mb_addr +
  81                              (i << 2) + sizeof(u32));
  82
  83                 /* The MB data is actually BE; Need to force it to cpu */
  84                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  85                         be32_to_cpu((__force __be32)tmp);
  86         }
  87 }
  88
  89 int qed_mcp_free(struct qed_hwfn *p_hwfn)
  90 {
  91         if (p_hwfn->mcp_info) {
  92                 kfree(p_hwfn->mcp_info->mfw_mb_cur);
  93                 kfree(p_hwfn->mcp_info->mfw_mb_shadow);
  94         }
  95         kfree(p_hwfn->mcp_info);
  96
  97         return 0;
  98 }
  99
 100 /* Maximum of 1 sec to wait for the SHMEM ready indication */
 101 #define QED_MCP_SHMEM_RDY_MAX_RETRIES   20
 102 #define QED_MCP_SHMEM_RDY_ITER_MS       50
 103
 104 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 105 {
 106         struct qed_mcp_info *p_info = p_hwfn->mcp_info;
 107         u8 cnt = QED_MCP_SHMEM_RDY_MAX_RETRIES;
 108         u8 msec = QED_MCP_SHMEM_RDY_ITER_MS;
 109         u32 drv_mb_offsize, mfw_mb_offsize;
 110         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 111
 112         p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 113         if (!p_info->public_base) {
 114                 DP_NOTICE(p_hwfn,
 115                           "The address of the MCP scratch-pad is not configured\n");
 116                 return -EINVAL;
 117         }
 118
 119         p_info->public_base |= GRCBASE_MCP;
 120
 121         /* Get the MFW MB address and number of supported messages */
 122         mfw_mb_offsize = qed_rd(p_hwfn, p_ptt,
 123                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 124                                                      PUBLIC_MFW_MB));
 125         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 126         p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt,
 127                                             p_info->mfw_mb_addr +
 128                                             offsetof(struct public_mfw_mb,
 129                                                      sup_msgs));
 130
 131         /* The driver can notify that there was an MCP reset, and might read the
 132          * SHMEM values before the MFW has completed initializing them.
 133          * To avoid this, the "sup_msgs" field in the MFW mailbox is used as a
 134          * data ready indication.
 135          */
 136         while (!p_info->mfw_mb_length && --cnt) {
 137                 msleep(msec);
 138                 p_info->mfw_mb_length =
 139                         (u16)qed_rd(p_hwfn, p_ptt,
 140                                     p_info->mfw_mb_addr +
 141                                     offsetof(struct public_mfw_mb, sup_msgs));
 142         }
 143
 144         if (!cnt) {
 145                 DP_NOTICE(p_hwfn,
 146                           "Failed to get the SHMEM ready notification after %d msec\n",
 147                           QED_MCP_SHMEM_RDY_MAX_RETRIES * msec);
 148                 return -EBUSY;
 149         }
 150
 151         /* Calculate the driver and MFW mailbox address */
 152         drv_mb_offsize = qed_rd(p_hwfn, p_ptt,
 153                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 154                                                      PUBLIC_DRV_MB));
 155         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 156         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 157                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n",
 158                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 159
 160         /* Get the current driver mailbox sequence before sending
 161          * the first command
 162          */
 163         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 164                              DRV_MSG_SEQ_NUMBER_MASK;
 165
 166         /* Get current FW pulse sequence */
 167         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 168                                 DRV_PULSE_SEQ_MASK;
 169
 170         p_info->mcp_hist = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 171
 172         return 0;
 173 }
 174
 175 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 176 {
 177         struct qed_mcp_info *p_info;
 178         u32 size;
 179
 180         /* Allocate mcp_info structure */
 181         p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL);
 182         if (!p_hwfn->mcp_info)
 183                 goto err;
 184         p_info = p_hwfn->mcp_info;
 185
 186         if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) {
 187                 DP_NOTICE(p_hwfn, "MCP is not initialized\n");
 188                 /* Do not free mcp_info here, since public_base indicate that
 189                  * the MCP is not initialized
 190                  */
 191                 return 0;
 192         }
 193
 194         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 195         p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL);
 196         p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL);
 197         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 198                 goto err;
 199
 200         /* Initialize the MFW spinlock */
 201         spin_lock_init(&p_info->lock);
 202
 203         return 0;
 204
 205 err:
 206         qed_mcp_free(p_hwfn);
 207         return -ENOMEM;
 208 }
 209
 210 /* Locks the MFW mailbox of a PF to ensure a single access.
 211  * The lock is achieved in most cases by holding a spinlock, causing other
 212  * threads to wait till a previous access is done.
 213  * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single
 214  * access is achieved by setting a blocking flag, which will fail other
 215  * competing contexts to send their mailboxes.
 216  */
 217 static int qed_mcp_mb_lock(struct qed_hwfn *p_hwfn, u32 cmd)
 218 {
 219         spin_lock_bh(&p_hwfn->mcp_info->lock);
 220
 221         /* The spinlock shouldn't be acquired when the mailbox command is
 222          * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel
 223          * pending [UN]LOAD_REQ command of another PF together with a spinlock
 224          * (i.e. interrupts are disabled) - can lead to a deadlock.
 225          * It is assumed that for a single PF, no other mailbox commands can be
 226          * sent from another context while sending LOAD_REQ, and that any
 227          * parallel commands to UNLOAD_REQ can be cancelled.
 228          */
 229         if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
 230                 p_hwfn->mcp_info->block_mb_sending = false;
 231
 232         if (p_hwfn->mcp_info->block_mb_sending) {
 233                 DP_NOTICE(p_hwfn,
 234                           "Trying to send a MFW mailbox command [0x%x] in parallel to [UN]LOAD_REQ. Aborting.\n",
 235                           cmd);
 236                 spin_unlock_bh(&p_hwfn->mcp_info->lock);
 237                 return -EBUSY;
 238         }
 239
 240         if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 241                 p_hwfn->mcp_info->block_mb_sending = true;
 242                 spin_unlock_bh(&p_hwfn->mcp_info->lock);
 243         }
 244
 245         return 0;
 246 }
 247
 248 static void qed_mcp_mb_unlock(struct qed_hwfn *p_hwfn, u32 cmd)
 249 {
 250         if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ)
 251                 spin_unlock_bh(&p_hwfn->mcp_info->lock);
 252 }
 253
 254 int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 255 {
 256         u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
 257         u8 delay = CHIP_MCP_RESP_ITER_US;
 258         u32 org_mcp_reset_seq, cnt = 0;
 259         int rc = 0;
 260
 261         /* Ensure that only a single thread is accessing the mailbox at a
 262          * certain time.
 263          */
 264         rc = qed_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 265         if (rc != 0)
 266                 return rc;
 267
 268         /* Set drv command along with the updated sequence */
 269         org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 270         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header,
 271                   (DRV_MSG_CODE_MCP_RESET | seq));
 272
 273         do {
 274                 /* Wait for MFW response */
 275                 udelay(delay);
 276                 /* Give the FW up to 500 second (50*1000*10usec) */
 277         } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt,
 278                                               MISCS_REG_GENERIC_POR_0)) &&
 279                  (cnt++ < QED_MCP_RESET_RETRIES));
 280
 281         if (org_mcp_reset_seq !=
 282             qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 283                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 284                            "MCP was reset after %d usec\n", cnt * delay);
 285         } else {
 286                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 287                 rc = -EAGAIN;
 288         }
 289
 290         qed_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 291
 292         return rc;
 293 }
 294
 295 static int qed_do_mcp_cmd(struct qed_hwfn *p_hwfn,
 296                           struct qed_ptt *p_ptt,
 297                           u32 cmd,
 298                           u32 param,
 299                           u32 *o_mcp_resp,
 300                           u32 *o_mcp_param)
 301 {
 302         u8 delay = CHIP_MCP_RESP_ITER_US;
 303         u32 seq, cnt = 1, actual_mb_seq;
 304         int rc = 0;
 305
 306         /* Get actual driver mailbox sequence */
 307         actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 308                         DRV_MSG_SEQ_NUMBER_MASK;
 309
 310         /* Use MCP history register to check if MCP reset occurred between
 311          * init time and now.
 312          */
 313         if (p_hwfn->mcp_info->mcp_hist !=
 314             qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 315                 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Rereading MCP offsets\n");
 316                 qed_load_mcp_offsets(p_hwfn, p_ptt);
 317                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
 318         }
 319         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 320
 321         /* Set drv param */
 322         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
 323
 324         /* Set drv command along with the updated sequence */
 325         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
 326
 327         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 328                    "wrote command (%x) to MFW MB param 0x%08x\n",
 329                    (cmd | seq), param);
 330
 331         do {
 332                 /* Wait for MFW response */
 333                 udelay(delay);
 334                 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 335
 336                 /* Give the FW up to 5 second (500*10ms) */
 337         } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
 338                  (cnt++ < QED_DRV_MB_MAX_RETRIES));
 339
 340         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 341                    "[after %d ms] read (%x) seq is (%x) from FW MB\n",
 342                    cnt * delay, *o_mcp_resp, seq);
 343
 344         /* Is this a reply to our command? */
 345         if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
 346                 *o_mcp_resp &= FW_MSG_CODE_MASK;
 347                 /* Get the MCP param */
 348                 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 349         } else {
 350                 /* FW BUG! */
 351                 DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n",
 352                        cmd, param);
 353                 *o_mcp_resp = 0;
 354                 rc = -EAGAIN;
 355         }
 356         return rc;
 357 }
 358
 359 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 360                                  struct qed_ptt *p_ptt,
 361                                  struct qed_mcp_mb_params *p_mb_params)
 362 {
 363         u32 union_data_addr;
 364         int rc;
 365
 366         /* MCP not initialized */
 367         if (!qed_mcp_is_init(p_hwfn)) {
 368                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
 369                 return -EBUSY;
 370         }
 371
 372         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 373                           offsetof(struct public_drv_mb, union_data);
 374
 375         /* Ensure that only a single thread is accessing the mailbox at a
 376          * certain time.
 377          */
 378         rc = qed_mcp_mb_lock(p_hwfn, p_mb_params->cmd);
 379         if (rc)
 380                 return rc;
 381
 382         if (p_mb_params->p_data_src != NULL)
 383                 qed_memcpy_to(p_hwfn, p_ptt, union_data_addr,
 384                               p_mb_params->p_data_src,
 385                               sizeof(*p_mb_params->p_data_src));
 386
 387         rc = qed_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd,
 388                             p_mb_params->param, &p_mb_params->mcp_resp,
 389                             &p_mb_params->mcp_param);
 390
 391         if (p_mb_params->p_data_dst != NULL)
 392                 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 393                                 union_data_addr,
 394                                 sizeof(*p_mb_params->p_data_dst));
 395
 396         qed_mcp_mb_unlock(p_hwfn, p_mb_params->cmd);
 397
 398         return rc;
 399 }
 400
 401 int qed_mcp_cmd(struct qed_hwfn *p_hwfn,
 402                 struct qed_ptt *p_ptt,
 403                 u32 cmd,
 404                 u32 param,
 405                 u32 *o_mcp_resp,
 406                 u32 *o_mcp_param)
 407 {
 408         struct qed_mcp_mb_params mb_params;
 409         int rc;
 410
 411         memset(&mb_params, 0, sizeof(mb_params));
 412         mb_params.cmd = cmd;
 413         mb_params.param = param;
 414         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 415         if (rc)
 416                 return rc;
 417
 418         *o_mcp_resp = mb_params.mcp_resp;
 419         *o_mcp_param = mb_params.mcp_param;
 420
 421         return 0;
 422 }
 423
 424 int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn,
 425                        struct qed_ptt *p_ptt,
 426                        u32 cmd,
 427                        u32 param,
 428                        u32 *o_mcp_resp,
 429                        u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf)
 430 {
 431         struct qed_mcp_mb_params mb_params;
 432         union drv_union_data union_data;
 433         int rc;
 434
 435         memset(&mb_params, 0, sizeof(mb_params));
 436         mb_params.cmd = cmd;
 437         mb_params.param = param;
 438         mb_params.p_data_dst = &union_data;
 439         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 440         if (rc)
 441                 return rc;
 442
 443         *o_mcp_resp = mb_params.mcp_resp;
 444         *o_mcp_param = mb_params.mcp_param;
 445
 446         *o_txn_size = *o_mcp_param;
 447         memcpy(o_buf, &union_data.raw_data, *o_txn_size);
 448
 449         return 0;
 450 }
 451
 452 int qed_mcp_load_req(struct qed_hwfn *p_hwfn,
 453                      struct qed_ptt *p_ptt, u32 *p_load_code)
 454 {
 455         struct qed_dev *cdev = p_hwfn->cdev;
 456         struct qed_mcp_mb_params mb_params;
 457         union drv_union_data union_data;
 458         int rc;
 459
 460         memset(&mb_params, 0, sizeof(mb_params));
 461         /* Load Request */
 462         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 463         mb_params.param = PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT |
 464                           cdev->drv_type;
 465         memcpy(&union_data.ver_str, cdev->ver_str, MCP_DRV_VER_STR_SIZE);
 466         mb_params.p_data_src = &union_data;
 467         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 468
 469         /* if mcp fails to respond we must abort */
 470         if (rc) {
 471                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 472                 return rc;
 473         }
 474
 475         *p_load_code = mb_params.mcp_resp;
 476
 477         /* If MFW refused (e.g. other port is in diagnostic mode) we
 478          * must abort. This can happen in the following cases:
 479          * - Other port is in diagnostic mode
 480          * - Previously loaded function on the engine is not compliant with
 481          *   the requester.
 482          * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION.
 483          *      -
 484          */
 485         if (!(*p_load_code) ||
 486             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) ||
 487             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) ||
 488             ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) {
 489                 DP_ERR(p_hwfn, "MCP refused load request, aborting\n");
 490                 return -EBUSY;
 491         }
 492
 493         return 0;
 494 }
 495
 496 static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn,
 497                                   struct qed_ptt *p_ptt)
 498 {
 499         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 500                                         PUBLIC_PATH);
 501         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
 502         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
 503                                      QED_PATH_ID(p_hwfn));
 504         u32 disabled_vfs[VF_MAX_STATIC / 32];
 505         int i;
 506
 507         DP_VERBOSE(p_hwfn,
 508                    QED_MSG_SP,
 509                    "Reading Disabled VF information from [offset %08x], path_addr %08x\n",
 510                    mfw_path_offsize, path_addr);
 511
 512         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
 513                 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt,
 514                                          path_addr +
 515                                          offsetof(struct public_path,
 516                                                   mcp_vf_disabled) +
 517                                          sizeof(u32) * i);
 518                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
 519                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
 520                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
 521         }
 522
 523         if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs))
 524                 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
 525 }
 526
 527 int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn,
 528                        struct qed_ptt *p_ptt, u32 *vfs_to_ack)
 529 {
 530         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 531                                         PUBLIC_FUNC);
 532         u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr);
 533         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
 534                                      MCP_PF_ID(p_hwfn));
 535         struct qed_mcp_mb_params mb_params;
 536         union drv_union_data union_data;
 537         int rc;
 538         int i;
 539
 540         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
 541                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
 542                            "Acking VFs [%08x,...,%08x] - %08x\n",
 543                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
 544
 545         memset(&mb_params, 0, sizeof(mb_params));
 546         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
 547         memcpy(&union_data.ack_vf_disabled, vfs_to_ack, VF_MAX_STATIC / 8);
 548         mb_params.p_data_src = &union_data;
 549         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 550         if (rc) {
 551                 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n");
 552                 return -EBUSY;
 553         }
 554
 555         /* Clear the ACK bits */
 556         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
 557                 qed_wr(p_hwfn, p_ptt,
 558                        func_addr +
 559                        offsetof(struct public_func, drv_ack_vf_disabled) +
 560                        i * sizeof(u32), 0);
 561
 562         return rc;
 563 }
 564
 565 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn,
 566                                               struct qed_ptt *p_ptt)
 567 {
 568         u32 transceiver_state;
 569
 570         transceiver_state = qed_rd(p_hwfn, p_ptt,
 571                                    p_hwfn->mcp_info->port_addr +
 572                                    offsetof(struct public_port,
 573                                             transceiver_data));
 574
 575         DP_VERBOSE(p_hwfn,
 576                    (NETIF_MSG_HW | QED_MSG_SP),
 577                    "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n",
 578                    transceiver_state,
 579                    (u32)(p_hwfn->mcp_info->port_addr +
 580                           offsetof(struct public_port, transceiver_data)));
 581
 582         transceiver_state = GET_FIELD(transceiver_state,
 583                                       ETH_TRANSCEIVER_STATE);
 584
 585         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
 586                 DP_NOTICE(p_hwfn, "Transceiver is present.\n");
 587         else
 588                 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n");
 589 }
 590
 591 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn,
 592                                        struct qed_ptt *p_ptt, bool b_reset)
 593 {
 594         struct qed_mcp_link_state *p_link;
 595         u8 max_bw, min_bw;
 596         u32 status = 0;
 597
 598         p_link = &p_hwfn->mcp_info->link_output;
 599         memset(p_link, 0, sizeof(*p_link));
 600         if (!b_reset) {
 601                 status = qed_rd(p_hwfn, p_ptt,
 602                                 p_hwfn->mcp_info->port_addr +
 603                                 offsetof(struct public_port, link_status));
 604                 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP),
 605                            "Received link update [0x%08x] from mfw [Addr 0x%x]\n",
 606                            status,
 607                            (u32)(p_hwfn->mcp_info->port_addr +
 608                                  offsetof(struct public_port, link_status)));
 609         } else {
 610                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
 611                            "Resetting link indications\n");
 612                 return;
 613         }
 614
 615         if (p_hwfn->b_drv_link_init)
 616                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
 617         else
 618                 p_link->link_up = false;
 619
 620         p_link->full_duplex = true;
 621         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
 622         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
 623                 p_link->speed = 100000;
 624                 break;
 625         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
 626                 p_link->speed = 50000;
 627                 break;
 628         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
 629                 p_link->speed = 40000;
 630                 break;
 631         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
 632                 p_link->speed = 25000;
 633                 break;
 634         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
 635                 p_link->speed = 20000;
 636                 break;
 637         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
 638                 p_link->speed = 10000;
 639                 break;
 640         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
 641                 p_link->full_duplex = false;
 642         /* Fall-through */
 643         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
 644                 p_link->speed = 1000;
 645                 break;
 646         default:
 647                 p_link->speed = 0;
 648                 p_link->link_up = 0;
 649         }
 650
 651         if (p_link->link_up && p_link->speed)
 652                 p_link->line_speed = p_link->speed;
 653         else
 654                 p_link->line_speed = 0;
 655
 656         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
 657         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
 658
 659         /* Max bandwidth configuration */
 660         __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw);
 661
 662         /* Min bandwidth configuration */
 663         __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw);
 664         qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt,
 665                                             p_link->min_pf_rate);
 666
 667         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
 668         p_link->an_complete = !!(status &
 669                                  LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
 670         p_link->parallel_detection = !!(status &
 671                                         LINK_STATUS_PARALLEL_DETECTION_USED);
 672         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
 673
 674         p_link->partner_adv_speed |=
 675                 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
 676                 QED_LINK_PARTNER_SPEED_1G_FD : 0;
 677         p_link->partner_adv_speed |=
 678                 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
 679                 QED_LINK_PARTNER_SPEED_1G_HD : 0;
 680         p_link->partner_adv_speed |=
 681                 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
 682                 QED_LINK_PARTNER_SPEED_10G : 0;
 683         p_link->partner_adv_speed |=
 684                 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
 685                 QED_LINK_PARTNER_SPEED_20G : 0;
 686         p_link->partner_adv_speed |=
 687                 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
 688                 QED_LINK_PARTNER_SPEED_25G : 0;
 689         p_link->partner_adv_speed |=
 690                 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
 691                 QED_LINK_PARTNER_SPEED_40G : 0;
 692         p_link->partner_adv_speed |=
 693                 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
 694                 QED_LINK_PARTNER_SPEED_50G : 0;
 695         p_link->partner_adv_speed |=
 696                 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
 697                 QED_LINK_PARTNER_SPEED_100G : 0;
 698
 699         p_link->partner_tx_flow_ctrl_en =
 700                 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
 701         p_link->partner_rx_flow_ctrl_en =
 702                 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
 703
 704         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
 705         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
 706                 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE;
 707                 break;
 708         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
 709                 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE;
 710                 break;
 711         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
 712                 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE;
 713                 break;
 714         default:
 715                 p_link->partner_adv_pause = 0;
 716         }
 717
 718         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
 719
 720         qed_link_update(p_hwfn);
 721 }
 722
 723 int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up)
 724 {
 725         struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
 726         struct qed_mcp_mb_params mb_params;
 727         union drv_union_data union_data;
 728         struct eth_phy_cfg *phy_cfg;
 729         int rc = 0;
 730         u32 cmd;
 731
 732         /* Set the shmem configuration according to params */
 733         phy_cfg = &union_data.drv_phy_cfg;
 734         memset(phy_cfg, 0, sizeof(*phy_cfg));
 735         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
 736         if (!params->speed.autoneg)
 737                 phy_cfg->speed = params->speed.forced_speed;
 738         phy_cfg->pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
 739         phy_cfg->pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
 740         phy_cfg->pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
 741         phy_cfg->adv_speed = params->speed.advertised_speeds;
 742         phy_cfg->loopback_mode = params->loopback_mode;
 743
 744         p_hwfn->b_drv_link_init = b_up;
 745
 746         if (b_up) {
 747                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
 748                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n",
 749                            phy_cfg->speed,
 750                            phy_cfg->pause,
 751                            phy_cfg->adv_speed,
 752                            phy_cfg->loopback_mode,
 753                            phy_cfg->feature_config_flags);
 754         } else {
 755                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
 756                            "Resetting link\n");
 757         }
 758
 759         memset(&mb_params, 0, sizeof(mb_params));
 760         mb_params.cmd = cmd;
 761         mb_params.p_data_src = &union_data;
 762         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 763
 764         /* if mcp fails to respond we must abort */
 765         if (rc) {
 766                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
 767                 return rc;
 768         }
 769
 770         /* Reset the link status if needed */
 771         if (!b_up)
 772                 qed_mcp_handle_link_change(p_hwfn, p_ptt, true);
 773
 774         return 0;
 775 }
 776
 777 static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn,
 778                                         struct qed_ptt *p_ptt,
 779                                         enum MFW_DRV_MSG_TYPE type)
 780 {
 781         enum qed_mcp_protocol_type stats_type;
 782         union qed_mcp_protocol_stats stats;
 783         struct qed_mcp_mb_params mb_params;
 784         union drv_union_data union_data;
 785         u32 hsi_param;
 786
 787         switch (type) {
 788         case MFW_DRV_MSG_GET_LAN_STATS:
 789                 stats_type = QED_MCP_LAN_STATS;
 790                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
 791                 break;
 792         case MFW_DRV_MSG_GET_FCOE_STATS:
 793                 stats_type = QED_MCP_FCOE_STATS;
 794                 hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE;
 795                 break;
 796         case MFW_DRV_MSG_GET_ISCSI_STATS:
 797                 stats_type = QED_MCP_ISCSI_STATS;
 798                 hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI;
 799                 break;
 800         case MFW_DRV_MSG_GET_RDMA_STATS:
 801                 stats_type = QED_MCP_RDMA_STATS;
 802                 hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA;
 803                 break;
 804         default:
 805                 DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type);
 806                 return;
 807         }
 808
 809         qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats);
 810
 811         memset(&mb_params, 0, sizeof(mb_params));
 812         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
 813         mb_params.param = hsi_param;
 814         memcpy(&union_data, &stats, sizeof(stats));
 815         mb_params.p_data_src = &union_data;
 816         qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 817 }
 818
 819 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn,
 820                                   struct public_func *p_shmem_info)
 821 {
 822         struct qed_mcp_function_info *p_info;
 823
 824         p_info = &p_hwfn->mcp_info->func_info;
 825
 826         p_info->bandwidth_min = (p_shmem_info->config &
 827                                  FUNC_MF_CFG_MIN_BW_MASK) >>
 828                                         FUNC_MF_CFG_MIN_BW_SHIFT;
 829         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
 830                 DP_INFO(p_hwfn,
 831                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
 832                         p_info->bandwidth_min);
 833                 p_info->bandwidth_min = 1;
 834         }
 835
 836         p_info->bandwidth_max = (p_shmem_info->config &
 837                                  FUNC_MF_CFG_MAX_BW_MASK) >>
 838                                         FUNC_MF_CFG_MAX_BW_SHIFT;
 839         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
 840                 DP_INFO(p_hwfn,
 841                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
 842                         p_info->bandwidth_max);
 843                 p_info->bandwidth_max = 100;
 844         }
 845 }
 846
 847 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn,
 848                                   struct qed_ptt *p_ptt,
 849                                   struct public_func *p_data, int pfid)
 850 {
 851         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 852                                         PUBLIC_FUNC);
 853         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
 854         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
 855         u32 i, size;
 856
 857         memset(p_data, 0, sizeof(*p_data));
 858
 859         size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize));
 860         for (i = 0; i < size / sizeof(u32); i++)
 861                 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt,
 862                                             func_addr + (i << 2));
 863         return size;
 864 }
 865
 866 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 867 {
 868         struct qed_mcp_function_info *p_info;
 869         struct public_func shmem_info;
 870         u32 resp = 0, param = 0;
 871
 872         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
 873
 874         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
 875
 876         p_info = &p_hwfn->mcp_info->func_info;
 877
 878         qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min);
 879         qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max);
 880
 881         /* Acknowledge the MFW */
 882         qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
 883                     &param);
 884 }
 885
 886 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn,
 887                           struct qed_ptt *p_ptt)
 888 {
 889         struct qed_mcp_info *info = p_hwfn->mcp_info;
 890         int rc = 0;
 891         bool found = false;
 892         u16 i;
 893
 894         DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n");
 895
 896         /* Read Messages from MFW */
 897         qed_mcp_read_mb(p_hwfn, p_ptt);
 898
 899         /* Compare current messages to old ones */
 900         for (i = 0; i < info->mfw_mb_length; i++) {
 901                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
 902                         continue;
 903
 904                 found = true;
 905
 906                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
 907                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
 908                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
 909
 910                 switch (i) {
 911                 case MFW_DRV_MSG_LINK_CHANGE:
 912                         qed_mcp_handle_link_change(p_hwfn, p_ptt, false);
 913                         break;
 914                 case MFW_DRV_MSG_VF_DISABLED:
 915                         qed_mcp_handle_vf_flr(p_hwfn, p_ptt);
 916                         break;
 917                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
 918                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
 919                                                   QED_DCBX_REMOTE_LLDP_MIB);
 920                         break;
 921                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
 922                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
 923                                                   QED_DCBX_REMOTE_MIB);
 924                         break;
 925                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
 926                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
 927                                                   QED_DCBX_OPERATIONAL_MIB);
 928                         break;
 929                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
 930                         qed_mcp_handle_transceiver_change(p_hwfn, p_ptt);
 931                         break;
 932                 case MFW_DRV_MSG_GET_LAN_STATS:
 933                 case MFW_DRV_MSG_GET_FCOE_STATS:
 934                 case MFW_DRV_MSG_GET_ISCSI_STATS:
 935                 case MFW_DRV_MSG_GET_RDMA_STATS:
 936                         qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
 937                         break;
 938                 case MFW_DRV_MSG_BW_UPDATE:
 939                         qed_mcp_update_bw(p_hwfn, p_ptt);
 940                         break;
 941                 default:
 942                         DP_NOTICE(p_hwfn, "Unimplemented MFW message %d\n", i);
 943                         rc = -EINVAL;
 944                 }
 945         }
 946
 947         /* ACK everything */
 948         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
 949                 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]);
 950
 951                 /* MFW expect answer in BE, so we force write in that format */
 952                 qed_wr(p_hwfn, p_ptt,
 953                        info->mfw_mb_addr + sizeof(u32) +
 954                        MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
 955                        sizeof(u32) + i * sizeof(u32),
 956                        (__force u32)val);
 957         }
 958
 959         if (!found) {
 960                 DP_NOTICE(p_hwfn,
 961                           "Received an MFW message indication but no new message!\n");
 962                 rc = -EINVAL;
 963         }
 964
 965         /* Copy the new mfw messages into the shadow */
 966         memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
 967
 968         return rc;
 969 }
 970
 971 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn,
 972                         struct qed_ptt *p_ptt,
 973                         u32 *p_mfw_ver, u32 *p_running_bundle_id)
 974 {
 975         u32 global_offsize;
 976
 977         if (IS_VF(p_hwfn->cdev)) {
 978                 if (p_hwfn->vf_iov_info) {
 979                         struct pfvf_acquire_resp_tlv *p_resp;
 980
 981                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
 982                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
 983                         return 0;
 984                 } else {
 985                         DP_VERBOSE(p_hwfn,
 986                                    QED_MSG_IOV,
 987                                    "VF requested MFW version prior to ACQUIRE\n");
 988                         return -EINVAL;
 989                 }
 990         }
 991
 992         global_offsize = qed_rd(p_hwfn, p_ptt,
 993                                 SECTION_OFFSIZE_ADDR(p_hwfn->
 994                                                      mcp_info->public_base,
 995                                                      PUBLIC_GLOBAL));
 996         *p_mfw_ver =
 997             qed_rd(p_hwfn, p_ptt,
 998                    SECTION_ADDR(global_offsize,
 999                                 0) + offsetof(struct public_global, mfw_ver));
1000
1001         if (p_running_bundle_id != NULL) {
1002                 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt,
1003                                               SECTION_ADDR(global_offsize, 0) +
1004                                               offsetof(struct public_global,
1005                                                        running_bundle_id));
1006         }
1007
1008         return 0;
1009 }
1010
1011 int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type)
1012 {
1013         struct qed_hwfn *p_hwfn = &cdev->hwfns[0];
1014         struct qed_ptt  *p_ptt;
1015
1016         if (IS_VF(cdev))
1017                 return -EINVAL;
1018
1019         if (!qed_mcp_is_init(p_hwfn)) {
1020                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
1021                 return -EBUSY;
1022         }
1023
1024         *p_media_type = MEDIA_UNSPECIFIED;
1025
1026         p_ptt = qed_ptt_acquire(p_hwfn);
1027         if (!p_ptt)
1028                 return -EBUSY;
1029
1030         *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1031                                offsetof(struct public_port, media_type));
1032
1033         qed_ptt_release(p_hwfn, p_ptt);
1034
1035         return 0;
1036 }
1037
1038 static int
1039 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
1040                         struct public_func *p_info,
1041                         enum qed_pci_personality *p_proto)
1042 {
1043         int rc = 0;
1044
1045         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1046         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1047                 if (test_bit(QED_DEV_CAP_ROCE,
1048                              &p_hwfn->hw_info.device_capabilities))
1049                         *p_proto = QED_PCI_ETH_ROCE;
1050                 else
1051                         *p_proto = QED_PCI_ETH;
1052                 break;
1053         case FUNC_MF_CFG_PROTOCOL_ISCSI:
1054                 *p_proto = QED_PCI_ISCSI;
1055                 break;
1056         case FUNC_MF_CFG_PROTOCOL_ROCE:
1057                 DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n");
1058                 rc = -EINVAL;
1059                 break;
1060         default:
1061                 rc = -EINVAL;
1062         }
1063
1064         return rc;
1065 }
1066
1067 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn,
1068                                  struct qed_ptt *p_ptt)
1069 {
1070         struct qed_mcp_function_info *info;
1071         struct public_func shmem_info;
1072
1073         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1074         info = &p_hwfn->mcp_info->func_info;
1075
1076         info->pause_on_host = (shmem_info.config &
1077                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1078
1079         if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, &info->protocol)) {
1080                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1081                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1082                 return -EINVAL;
1083         }
1084
1085         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1086
1087         if (shmem_info.mac_upper || shmem_info.mac_lower) {
1088                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1089                 info->mac[1] = (u8)(shmem_info.mac_upper);
1090                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1091                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1092                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1093                 info->mac[5] = (u8)(shmem_info.mac_lower);
1094         } else {
1095                 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n");
1096         }
1097
1098         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
1099                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
1100         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
1101                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
1102
1103         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1104
1105         DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP),
1106                    "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x\n",
1107                 info->pause_on_host, info->protocol,
1108                 info->bandwidth_min, info->bandwidth_max,
1109                 info->mac[0], info->mac[1], info->mac[2],
1110                 info->mac[3], info->mac[4], info->mac[5],
1111                 info->wwn_port, info->wwn_node, info->ovlan);
1112
1113         return 0;
1114 }
1115
1116 struct qed_mcp_link_params
1117 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn)
1118 {
1119         if (!p_hwfn || !p_hwfn->mcp_info)
1120                 return NULL;
1121         return &p_hwfn->mcp_info->link_input;
1122 }
1123
1124 struct qed_mcp_link_state
1125 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn)
1126 {
1127         if (!p_hwfn || !p_hwfn->mcp_info)
1128                 return NULL;
1129         return &p_hwfn->mcp_info->link_output;
1130 }
1131
1132 struct qed_mcp_link_capabilities
1133 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn)
1134 {
1135         if (!p_hwfn || !p_hwfn->mcp_info)
1136                 return NULL;
1137         return &p_hwfn->mcp_info->link_capabilities;
1138 }
1139
1140 int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1141 {
1142         u32 resp = 0, param = 0;
1143         int rc;
1144
1145         rc = qed_mcp_cmd(p_hwfn, p_ptt,
1146                          DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
1147
1148         /* Wait for the drain to complete before returning */
1149         msleep(1020);
1150
1151         return rc;
1152 }
1153
1154 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn,
1155                            struct qed_ptt *p_ptt, u32 *p_flash_size)
1156 {
1157         u32 flash_size;
1158
1159         if (IS_VF(p_hwfn->cdev))
1160                 return -EINVAL;
1161
1162         flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
1163         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
1164                       MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
1165         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
1166
1167         *p_flash_size = flash_size;
1168
1169         return 0;
1170 }
1171
1172 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn,
1173                            struct qed_ptt *p_ptt, u8 vf_id, u8 num)
1174 {
1175         u32 resp = 0, param = 0, rc_param = 0;
1176         int rc;
1177
1178         /* Only Leader can configure MSIX, and need to take CMT into account */
1179         if (!IS_LEAD_HWFN(p_hwfn))
1180                 return 0;
1181         num *= p_hwfn->cdev->num_hwfns;
1182
1183         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
1184                  DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
1185         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
1186                  DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
1187
1188         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
1189                          &resp, &rc_param);
1190
1191         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
1192                 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id);
1193                 rc = -EINVAL;
1194         } else {
1195                 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1196                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
1197                            num, vf_id);
1198         }
1199
1200         return rc;
1201 }
1202
1203 int
1204 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn,
1205                          struct qed_ptt *p_ptt,
1206                          struct qed_mcp_drv_version *p_ver)
1207 {
1208         struct drv_version_stc *p_drv_version;
1209         struct qed_mcp_mb_params mb_params;
1210         union drv_union_data union_data;
1211         __be32 val;
1212         u32 i;
1213         int rc;
1214
1215         p_drv_version = &union_data.drv_version;
1216         p_drv_version->version = p_ver->version;
1217
1218         for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) {
1219                 val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)]));
1220                 *(__be32 *)&p_drv_version->name[i * sizeof(u32)] = val;
1221         }
1222
1223         memset(&mb_params, 0, sizeof(mb_params));
1224         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
1225         mb_params.p_data_src = &union_data;
1226         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1227         if (rc)
1228                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1229
1230         return rc;
1231 }
1232
1233 /* A maximal 100 msec waiting time for the MCP to halt */
1234 #define QED_MCP_HALT_SLEEP_MS           10
1235 #define QED_MCP_HALT_MAX_RETRIES        10
1236
1237 int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1238 {
1239         u32 resp = 0, param = 0, cpu_state, cnt = 0;
1240         int rc;
1241
1242         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
1243                          &param);
1244         if (rc) {
1245                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1246                 return rc;
1247         }
1248
1249         do {
1250                 msleep(QED_MCP_HALT_SLEEP_MS);
1251                 cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
1252                 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED)
1253                         break;
1254         } while (++cnt < QED_MCP_HALT_MAX_RETRIES);
1255
1256         if (cnt == QED_MCP_HALT_MAX_RETRIES) {
1257                 DP_NOTICE(p_hwfn,
1258                           "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
1259                           qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state);
1260                 return -EBUSY;
1261         }
1262
1263         return 0;
1264 }
1265
1266 #define QED_MCP_RESUME_SLEEP_MS 10
1267
1268 int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1269 {
1270         u32 cpu_mode, cpu_state;
1271
1272         qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
1273
1274         cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1275         cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT;
1276         qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode);
1277         msleep(QED_MCP_RESUME_SLEEP_MS);
1278         cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
1279
1280         if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) {
1281                 DP_NOTICE(p_hwfn,
1282                           "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
1283                           cpu_mode, cpu_state);
1284                 return -EBUSY;
1285         }
1286
1287         return 0;
1288 }
1289
1290 int qed_mcp_set_led(struct qed_hwfn *p_hwfn,
1291                     struct qed_ptt *p_ptt, enum qed_led_mode mode)
1292 {
1293         u32 resp = 0, param = 0, drv_mb_param;
1294         int rc;
1295
1296         switch (mode) {
1297         case QED_LED_MODE_ON:
1298                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
1299                 break;
1300         case QED_LED_MODE_OFF:
1301                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
1302                 break;
1303         case QED_LED_MODE_RESTORE:
1304                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
1305                 break;
1306         default:
1307                 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode);
1308                 return -EINVAL;
1309         }
1310
1311         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
1312                          drv_mb_param, &resp, &param);
1313
1314         return rc;
1315 }
1316
1317 int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn,
1318                           struct qed_ptt *p_ptt, u32 mask_parities)
1319 {
1320         u32 resp = 0, param = 0;
1321         int rc;
1322
1323         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
1324                          mask_parities, &resp, &param);
1325
1326         if (rc) {
1327                 DP_ERR(p_hwfn,
1328                        "MCP response failure for mask parities, aborting\n");
1329         } else if (resp != FW_MSG_CODE_OK) {
1330                 DP_ERR(p_hwfn,
1331                        "MCP did not acknowledge mask parity request. Old MFW?\n");
1332                 rc = -EINVAL;
1333         }
1334
1335         return rc;
1336 }
1337
1338 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1339 {
1340         u32 drv_mb_param = 0, rsp, param;
1341         int rc = 0;
1342
1343         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
1344                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
1345
1346         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
1347                          drv_mb_param, &rsp, &param);
1348
1349         if (rc)
1350                 return rc;
1351
1352         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
1353             (param != DRV_MB_PARAM_BIST_RC_PASSED))
1354                 rc = -EAGAIN;
1355
1356         return rc;
1357 }
1358
1359 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1360 {
1361         u32 drv_mb_param, rsp, param;
1362         int rc = 0;
1363
1364         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
1365                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
1366
1367         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
1368                          drv_mb_param, &rsp, &param);
1369
1370         if (rc)
1371                 return rc;
1372
1373         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
1374             (param != DRV_MB_PARAM_BIST_RC_PASSED))
1375                 rc = -EAGAIN;
1376
1377         return rc;
1378 }