drivers/net/ethernet/qlogic/qed/qed_main.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/stddef.h>
  34 #include <linux/pci.h>
  35 #include <linux/kernel.h>
  36 #include <linux/slab.h>
  37 #include <linux/delay.h>
  38 #include <asm/byteorder.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/string.h>
  41 #include <linux/module.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/workqueue.h>
  44 #include <linux/ethtool.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/vmalloc.h>
  47 #include <linux/crash_dump.h>
  48 #include <linux/crc32.h>
  49 #include <linux/qed/qed_if.h>
  50 #include <linux/qed/qed_ll2_if.h>
  51
  52 #include "qed.h"
  53 #include "qed_sriov.h"
  54 #include "qed_sp.h"
  55 #include "qed_dev_api.h"
  56 #include "qed_ll2.h"
  57 #include "qed_fcoe.h"
  58 #include "qed_iscsi.h"
  59
  60 #include "qed_mcp.h"
  61 #include "qed_hw.h"
  62 #include "qed_selftest.h"
  63 #include "qed_debug.h"
  64
  65 #define QED_ROCE_QPS                    (8192)
  66 #define QED_ROCE_DPIS                   (8)
  67 #define QED_RDMA_SRQS                   QED_ROCE_QPS
  68
  69 static char version[] =
  70         "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n";
  71
  72 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module");
  73 MODULE_LICENSE("GPL");
  74 MODULE_VERSION(DRV_MODULE_VERSION);
  75
  76 #define FW_FILE_VERSION                         \
  77         __stringify(FW_MAJOR_VERSION) "."       \
  78         __stringify(FW_MINOR_VERSION) "."       \
  79         __stringify(FW_REVISION_VERSION) "."    \
  80         __stringify(FW_ENGINEERING_VERSION)
  81
  82 #define QED_FW_FILE_NAME        \
  83         "/*(DEBLOBBED)*/"
  84
  85 /*(DEBLOBBED)*/
  86
  87 static int __init qed_init(void)
  88 {
  89         pr_info("%s", version);
  90
  91         return 0;
  92 }
  93
  94 static void __exit qed_cleanup(void)
  95 {
  96         pr_notice("qed_cleanup called\n");
  97 }
  98
  99 module_init(qed_init);
 100 module_exit(qed_cleanup);
 101
 102 /* Check if the DMA controller on the machine can properly handle the DMA
 103  * addressing required by the device.
 104 */
 105 static int qed_set_coherency_mask(struct qed_dev *cdev)
 106 {
 107         struct device *dev = &cdev->pdev->dev;
 108
 109         if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
 110                 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
 111                         DP_NOTICE(cdev,
 112                                   "Can't request 64-bit consistent allocations\n");
 113                         return -EIO;
 114                 }
 115         } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
 116                 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n");
 117                 return -EIO;
 118         }
 119
 120         return 0;
 121 }
 122
 123 static void qed_free_pci(struct qed_dev *cdev)
 124 {
 125         struct pci_dev *pdev = cdev->pdev;
 126
 127         if (cdev->doorbells && cdev->db_size)
 128                 iounmap(cdev->doorbells);
 129         if (cdev->regview)
 130                 iounmap(cdev->regview);
 131         if (atomic_read(&pdev->enable_cnt) == 1)
 132                 pci_release_regions(pdev);
 133
 134         pci_disable_device(pdev);
 135 }
 136
 137 #define PCI_REVISION_ID_ERROR_VAL       0xff
 138
 139 /* Performs PCI initializations as well as initializing PCI-related parameters
 140  * in the device structrue. Returns 0 in case of success.
 141  */
 142 static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev)
 143 {
 144         u8 rev_id;
 145         int rc;
 146
 147         cdev->pdev = pdev;
 148
 149         rc = pci_enable_device(pdev);
 150         if (rc) {
 151                 DP_NOTICE(cdev, "Cannot enable PCI device\n");
 152                 goto err0;
 153         }
 154
 155         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
 156                 DP_NOTICE(cdev, "No memory region found in bar #0\n");
 157                 rc = -EIO;
 158                 goto err1;
 159         }
 160
 161         if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
 162                 DP_NOTICE(cdev, "No memory region found in bar #2\n");
 163                 rc = -EIO;
 164                 goto err1;
 165         }
 166
 167         if (atomic_read(&pdev->enable_cnt) == 1) {
 168                 rc = pci_request_regions(pdev, "qed");
 169                 if (rc) {
 170                         DP_NOTICE(cdev,
 171                                   "Failed to request PCI memory resources\n");
 172                         goto err1;
 173                 }
 174                 pci_set_master(pdev);
 175                 pci_save_state(pdev);
 176         }
 177
 178         pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
 179         if (rev_id == PCI_REVISION_ID_ERROR_VAL) {
 180                 DP_NOTICE(cdev,
 181                           "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n",
 182                           rev_id);
 183                 rc = -ENODEV;
 184                 goto err2;
 185         }
 186         if (!pci_is_pcie(pdev)) {
 187                 DP_NOTICE(cdev, "The bus is not PCI Express\n");
 188                 rc = -EIO;
 189                 goto err2;
 190         }
 191
 192         cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
 193         if (IS_PF(cdev) && !cdev->pci_params.pm_cap)
 194                 DP_NOTICE(cdev, "Cannot find power management capability\n");
 195
 196         rc = qed_set_coherency_mask(cdev);
 197         if (rc)
 198                 goto err2;
 199
 200         cdev->pci_params.mem_start = pci_resource_start(pdev, 0);
 201         cdev->pci_params.mem_end = pci_resource_end(pdev, 0);
 202         cdev->pci_params.irq = pdev->irq;
 203
 204         cdev->regview = pci_ioremap_bar(pdev, 0);
 205         if (!cdev->regview) {
 206                 DP_NOTICE(cdev, "Cannot map register space, aborting\n");
 207                 rc = -ENOMEM;
 208                 goto err2;
 209         }
 210
 211         cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2);
 212         cdev->db_size = pci_resource_len(cdev->pdev, 2);
 213         if (!cdev->db_size) {
 214                 if (IS_PF(cdev)) {
 215                         DP_NOTICE(cdev, "No Doorbell bar available\n");
 216                         return -EINVAL;
 217                 } else {
 218                         return 0;
 219                 }
 220         }
 221
 222         cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size);
 223
 224         if (!cdev->doorbells) {
 225                 DP_NOTICE(cdev, "Cannot map doorbell space\n");
 226                 return -ENOMEM;
 227         }
 228
 229         return 0;
 230
 231 err2:
 232         pci_release_regions(pdev);
 233 err1:
 234         pci_disable_device(pdev);
 235 err0:
 236         return rc;
 237 }
 238
 239 int qed_fill_dev_info(struct qed_dev *cdev,
 240                       struct qed_dev_info *dev_info)
 241 {
 242         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
 243         struct qed_hw_info *hw_info = &p_hwfn->hw_info;
 244         struct qed_tunnel_info *tun = &cdev->tunnel;
 245         struct qed_ptt  *ptt;
 246
 247         memset(dev_info, 0, sizeof(struct qed_dev_info));
 248
 249         if (tun->vxlan.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
 250             tun->vxlan.b_mode_enabled)
 251                 dev_info->vxlan_enable = true;
 252
 253         if (tun->l2_gre.b_mode_enabled && tun->ip_gre.b_mode_enabled &&
 254             tun->l2_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
 255             tun->ip_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN)
 256                 dev_info->gre_enable = true;
 257
 258         if (tun->l2_geneve.b_mode_enabled && tun->ip_geneve.b_mode_enabled &&
 259             tun->l2_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
 260             tun->ip_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN)
 261                 dev_info->geneve_enable = true;
 262
 263         dev_info->num_hwfns = cdev->num_hwfns;
 264         dev_info->pci_mem_start = cdev->pci_params.mem_start;
 265         dev_info->pci_mem_end = cdev->pci_params.mem_end;
 266         dev_info->pci_irq = cdev->pci_params.irq;
 267         dev_info->rdma_supported = QED_IS_RDMA_PERSONALITY(p_hwfn);
 268         dev_info->dev_type = cdev->type;
 269         ether_addr_copy(dev_info->hw_mac, hw_info->hw_mac_addr);
 270
 271         if (IS_PF(cdev)) {
 272                 dev_info->fw_major = FW_MAJOR_VERSION;
 273                 dev_info->fw_minor = FW_MINOR_VERSION;
 274                 dev_info->fw_rev = FW_REVISION_VERSION;
 275                 dev_info->fw_eng = FW_ENGINEERING_VERSION;
 276                 dev_info->b_inter_pf_switch = test_bit(QED_MF_INTER_PF_SWITCH,
 277                                                        &cdev->mf_bits);
 278                 dev_info->tx_switching = true;
 279
 280                 if (hw_info->b_wol_support == QED_WOL_SUPPORT_PME)
 281                         dev_info->wol_support = true;
 282
 283                 dev_info->abs_pf_id = QED_LEADING_HWFN(cdev)->abs_pf_id;
 284         } else {
 285                 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major,
 286                                       &dev_info->fw_minor, &dev_info->fw_rev,
 287                                       &dev_info->fw_eng);
 288         }
 289
 290         if (IS_PF(cdev)) {
 291                 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
 292                 if (ptt) {
 293                         qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt,
 294                                             &dev_info->mfw_rev, NULL);
 295
 296                         qed_mcp_get_mbi_ver(QED_LEADING_HWFN(cdev), ptt,
 297                                             &dev_info->mbi_version);
 298
 299                         qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt,
 300                                                &dev_info->flash_size);
 301
 302                         qed_ptt_release(QED_LEADING_HWFN(cdev), ptt);
 303                 }
 304         } else {
 305                 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL,
 306                                     &dev_info->mfw_rev, NULL);
 307         }
 308
 309         dev_info->mtu = hw_info->mtu;
 310
 311         return 0;
 312 }
 313
 314 static void qed_free_cdev(struct qed_dev *cdev)
 315 {
 316         kfree((void *)cdev);
 317 }
 318
 319 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev)
 320 {
 321         struct qed_dev *cdev;
 322
 323         cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
 324         if (!cdev)
 325                 return cdev;
 326
 327         qed_init_struct(cdev);
 328
 329         return cdev;
 330 }
 331
 332 /* Sets the requested power state */
 333 static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state)
 334 {
 335         if (!cdev)
 336                 return -ENODEV;
 337
 338         DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n");
 339         return 0;
 340 }
 341
 342 /* probing */
 343 static struct qed_dev *qed_probe(struct pci_dev *pdev,
 344                                  struct qed_probe_params *params)
 345 {
 346         struct qed_dev *cdev;
 347         int rc;
 348
 349         cdev = qed_alloc_cdev(pdev);
 350         if (!cdev)
 351                 goto err0;
 352
 353         cdev->drv_type = DRV_ID_DRV_TYPE_LINUX;
 354         cdev->protocol = params->protocol;
 355
 356         if (params->is_vf)
 357                 cdev->b_is_vf = true;
 358
 359         qed_init_dp(cdev, params->dp_module, params->dp_level);
 360
 361         rc = qed_init_pci(cdev, pdev);
 362         if (rc) {
 363                 DP_ERR(cdev, "init pci failed\n");
 364                 goto err1;
 365         }
 366         DP_INFO(cdev, "PCI init completed successfully\n");
 367
 368         rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT);
 369         if (rc) {
 370                 DP_ERR(cdev, "hw prepare failed\n");
 371                 goto err2;
 372         }
 373
 374         DP_INFO(cdev, "qed_probe completed successfully\n");
 375
 376         return cdev;
 377
 378 err2:
 379         qed_free_pci(cdev);
 380 err1:
 381         qed_free_cdev(cdev);
 382 err0:
 383         return NULL;
 384 }
 385
 386 static void qed_remove(struct qed_dev *cdev)
 387 {
 388         if (!cdev)
 389                 return;
 390
 391         qed_hw_remove(cdev);
 392
 393         qed_free_pci(cdev);
 394
 395         qed_set_power_state(cdev, PCI_D3hot);
 396
 397         qed_free_cdev(cdev);
 398 }
 399
 400 static void qed_disable_msix(struct qed_dev *cdev)
 401 {
 402         if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
 403                 pci_disable_msix(cdev->pdev);
 404                 kfree(cdev->int_params.msix_table);
 405         } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) {
 406                 pci_disable_msi(cdev->pdev);
 407         }
 408
 409         memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param));
 410 }
 411
 412 static int qed_enable_msix(struct qed_dev *cdev,
 413                            struct qed_int_params *int_params)
 414 {
 415         int i, rc, cnt;
 416
 417         cnt = int_params->in.num_vectors;
 418
 419         for (i = 0; i < cnt; i++)
 420                 int_params->msix_table[i].entry = i;
 421
 422         rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table,
 423                                    int_params->in.min_msix_cnt, cnt);
 424         if (rc < cnt && rc >= int_params->in.min_msix_cnt &&
 425             (rc % cdev->num_hwfns)) {
 426                 pci_disable_msix(cdev->pdev);
 427
 428                 /* If fastpath is initialized, we need at least one interrupt
 429                  * per hwfn [and the slow path interrupts]. New requested number
 430                  * should be a multiple of the number of hwfns.
 431                  */
 432                 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns;
 433                 DP_NOTICE(cdev,
 434                           "Trying to enable MSI-X with less vectors (%d out of %d)\n",
 435                           cnt, int_params->in.num_vectors);
 436                 rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table,
 437                                            cnt);
 438                 if (!rc)
 439                         rc = cnt;
 440         }
 441
 442         /* For VFs, we should return with an error in case we didn't get the
 443          * exact number of msix vectors as we requested.
 444          * Not doing that will lead to a crash when starting queues for
 445          * this VF.
 446          */
 447         if ((IS_PF(cdev) && rc > 0) || (IS_VF(cdev) && rc == cnt)) {
 448                 /* MSI-x configuration was achieved */
 449                 int_params->out.int_mode = QED_INT_MODE_MSIX;
 450                 int_params->out.num_vectors = rc;
 451                 rc = 0;
 452         } else {
 453                 DP_NOTICE(cdev,
 454                           "Failed to enable MSI-X [Requested %d vectors][rc %d]\n",
 455                           cnt, rc);
 456         }
 457
 458         return rc;
 459 }
 460
 461 /* This function outputs the int mode and the number of enabled msix vector */
 462 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode)
 463 {
 464         struct qed_int_params *int_params = &cdev->int_params;
 465         struct msix_entry *tbl;
 466         int rc = 0, cnt;
 467
 468         switch (int_params->in.int_mode) {
 469         case QED_INT_MODE_MSIX:
 470                 /* Allocate MSIX table */
 471                 cnt = int_params->in.num_vectors;
 472                 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL);
 473                 if (!int_params->msix_table) {
 474                         rc = -ENOMEM;
 475                         goto out;
 476                 }
 477
 478                 /* Enable MSIX */
 479                 rc = qed_enable_msix(cdev, int_params);
 480                 if (!rc)
 481                         goto out;
 482
 483                 DP_NOTICE(cdev, "Failed to enable MSI-X\n");
 484                 kfree(int_params->msix_table);
 485                 if (force_mode)
 486                         goto out;
 487                 /* Fallthrough */
 488
 489         case QED_INT_MODE_MSI:
 490                 if (cdev->num_hwfns == 1) {
 491                         rc = pci_enable_msi(cdev->pdev);
 492                         if (!rc) {
 493                                 int_params->out.int_mode = QED_INT_MODE_MSI;
 494                                 goto out;
 495                         }
 496
 497                         DP_NOTICE(cdev, "Failed to enable MSI\n");
 498                         if (force_mode)
 499                                 goto out;
 500                 }
 501                 /* Fallthrough */
 502
 503         case QED_INT_MODE_INTA:
 504                         int_params->out.int_mode = QED_INT_MODE_INTA;
 505                         rc = 0;
 506                         goto out;
 507         default:
 508                 DP_NOTICE(cdev, "Unknown int_mode value %d\n",
 509                           int_params->in.int_mode);
 510                 rc = -EINVAL;
 511         }
 512
 513 out:
 514         if (!rc)
 515                 DP_INFO(cdev, "Using %s interrupts\n",
 516                         int_params->out.int_mode == QED_INT_MODE_INTA ?
 517                         "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ?
 518                         "MSI" : "MSIX");
 519         cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE;
 520
 521         return rc;
 522 }
 523
 524 static void qed_simd_handler_config(struct qed_dev *cdev, void *token,
 525                                     int index, void(*handler)(void *))
 526 {
 527         struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
 528         int relative_idx = index / cdev->num_hwfns;
 529
 530         hwfn->simd_proto_handler[relative_idx].func = handler;
 531         hwfn->simd_proto_handler[relative_idx].token = token;
 532 }
 533
 534 static void qed_simd_handler_clean(struct qed_dev *cdev, int index)
 535 {
 536         struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
 537         int relative_idx = index / cdev->num_hwfns;
 538
 539         memset(&hwfn->simd_proto_handler[relative_idx], 0,
 540                sizeof(struct qed_simd_fp_handler));
 541 }
 542
 543 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet)
 544 {
 545         tasklet_schedule((struct tasklet_struct *)tasklet);
 546         return IRQ_HANDLED;
 547 }
 548
 549 static irqreturn_t qed_single_int(int irq, void *dev_instance)
 550 {
 551         struct qed_dev *cdev = (struct qed_dev *)dev_instance;
 552         struct qed_hwfn *hwfn;
 553         irqreturn_t rc = IRQ_NONE;
 554         u64 status;
 555         int i, j;
 556
 557         for (i = 0; i < cdev->num_hwfns; i++) {
 558                 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]);
 559
 560                 if (!status)
 561                         continue;
 562
 563                 hwfn = &cdev->hwfns[i];
 564
 565                 /* Slowpath interrupt */
 566                 if (unlikely(status & 0x1)) {
 567                         tasklet_schedule(hwfn->sp_dpc);
 568                         status &= ~0x1;
 569                         rc = IRQ_HANDLED;
 570                 }
 571
 572                 /* Fastpath interrupts */
 573                 for (j = 0; j < 64; j++) {
 574                         if ((0x2ULL << j) & status) {
 575                                 struct qed_simd_fp_handler *p_handler =
 576                                         &hwfn->simd_proto_handler[j];
 577
 578                                 if (p_handler->func)
 579                                         p_handler->func(p_handler->token);
 580                                 else
 581                                         DP_NOTICE(hwfn,
 582                                                   "Not calling fastpath handler as it is NULL [handler #%d, status 0x%llx]\n",
 583                                                   j, status);
 584
 585                                 status &= ~(0x2ULL << j);
 586                                 rc = IRQ_HANDLED;
 587                         }
 588                 }
 589
 590                 if (unlikely(status))
 591                         DP_VERBOSE(hwfn, NETIF_MSG_INTR,
 592                                    "got an unknown interrupt status 0x%llx\n",
 593                                    status);
 594         }
 595
 596         return rc;
 597 }
 598
 599 int qed_slowpath_irq_req(struct qed_hwfn *hwfn)
 600 {
 601         struct qed_dev *cdev = hwfn->cdev;
 602         u32 int_mode;
 603         int rc = 0;
 604         u8 id;
 605
 606         int_mode = cdev->int_params.out.int_mode;
 607         if (int_mode == QED_INT_MODE_MSIX) {
 608                 id = hwfn->my_id;
 609                 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x",
 610                          id, cdev->pdev->bus->number,
 611                          PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
 612                 rc = request_irq(cdev->int_params.msix_table[id].vector,
 613                                  qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc);
 614         } else {
 615                 unsigned long flags = 0;
 616
 617                 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x",
 618                          cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn),
 619                          PCI_FUNC(cdev->pdev->devfn));
 620
 621                 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA)
 622                         flags |= IRQF_SHARED;
 623
 624                 rc = request_irq(cdev->pdev->irq, qed_single_int,
 625                                  flags, cdev->name, cdev);
 626         }
 627
 628         if (rc)
 629                 DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc);
 630         else
 631                 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP),
 632                            "Requested slowpath %s\n",
 633                            (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ");
 634
 635         return rc;
 636 }
 637
 638 static void qed_slowpath_tasklet_flush(struct qed_hwfn *p_hwfn)
 639 {
 640         /* Calling the disable function will make sure that any
 641          * currently-running function is completed. The following call to the
 642          * enable function makes this sequence a flush-like operation.
 643          */
 644         if (p_hwfn->b_sp_dpc_enabled) {
 645                 tasklet_disable(p_hwfn->sp_dpc);
 646                 tasklet_enable(p_hwfn->sp_dpc);
 647         }
 648 }
 649
 650 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn)
 651 {
 652         struct qed_dev *cdev = p_hwfn->cdev;
 653         u8 id = p_hwfn->my_id;
 654         u32 int_mode;
 655
 656         int_mode = cdev->int_params.out.int_mode;
 657         if (int_mode == QED_INT_MODE_MSIX)
 658                 synchronize_irq(cdev->int_params.msix_table[id].vector);
 659         else
 660                 synchronize_irq(cdev->pdev->irq);
 661
 662         qed_slowpath_tasklet_flush(p_hwfn);
 663 }
 664
 665 static void qed_slowpath_irq_free(struct qed_dev *cdev)
 666 {
 667         int i;
 668
 669         if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
 670                 for_each_hwfn(cdev, i) {
 671                         if (!cdev->hwfns[i].b_int_requested)
 672                                 break;
 673                         synchronize_irq(cdev->int_params.msix_table[i].vector);
 674                         free_irq(cdev->int_params.msix_table[i].vector,
 675                                  cdev->hwfns[i].sp_dpc);
 676                 }
 677         } else {
 678                 if (QED_LEADING_HWFN(cdev)->b_int_requested)
 679                         free_irq(cdev->pdev->irq, cdev);
 680         }
 681         qed_int_disable_post_isr_release(cdev);
 682 }
 683
 684 static int qed_nic_stop(struct qed_dev *cdev)
 685 {
 686         int i, rc;
 687
 688         rc = qed_hw_stop(cdev);
 689
 690         for (i = 0; i < cdev->num_hwfns; i++) {
 691                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 692
 693                 if (p_hwfn->b_sp_dpc_enabled) {
 694                         tasklet_disable(p_hwfn->sp_dpc);
 695                         p_hwfn->b_sp_dpc_enabled = false;
 696                         DP_VERBOSE(cdev, NETIF_MSG_IFDOWN,
 697                                    "Disabled sp tasklet [hwfn %d] at %p\n",
 698                                    i, p_hwfn->sp_dpc);
 699                 }
 700         }
 701
 702         qed_dbg_pf_exit(cdev);
 703
 704         return rc;
 705 }
 706
 707 static int qed_nic_setup(struct qed_dev *cdev)
 708 {
 709         int rc, i;
 710
 711         /* Determine if interface is going to require LL2 */
 712         if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) {
 713                 for (i = 0; i < cdev->num_hwfns; i++) {
 714                         struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 715
 716                         p_hwfn->using_ll2 = true;
 717                 }
 718         }
 719
 720         rc = qed_resc_alloc(cdev);
 721         if (rc)
 722                 return rc;
 723
 724         DP_INFO(cdev, "Allocated qed resources\n");
 725
 726         qed_resc_setup(cdev);
 727
 728         return rc;
 729 }
 730
 731 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt)
 732 {
 733         int limit = 0;
 734
 735         /* Mark the fastpath as free/used */
 736         cdev->int_params.fp_initialized = cnt ? true : false;
 737
 738         if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX)
 739                 limit = cdev->num_hwfns * 63;
 740         else if (cdev->int_params.fp_msix_cnt)
 741                 limit = cdev->int_params.fp_msix_cnt;
 742
 743         if (!limit)
 744                 return -ENOMEM;
 745
 746         return min_t(int, cnt, limit);
 747 }
 748
 749 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info)
 750 {
 751         memset(info, 0, sizeof(struct qed_int_info));
 752
 753         if (!cdev->int_params.fp_initialized) {
 754                 DP_INFO(cdev,
 755                         "Protocol driver requested interrupt information, but its support is not yet configured\n");
 756                 return -EINVAL;
 757         }
 758
 759         /* Need to expose only MSI-X information; Single IRQ is handled solely
 760          * by qed.
 761          */
 762         if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
 763                 int msix_base = cdev->int_params.fp_msix_base;
 764
 765                 info->msix_cnt = cdev->int_params.fp_msix_cnt;
 766                 info->msix = &cdev->int_params.msix_table[msix_base];
 767         }
 768
 769         return 0;
 770 }
 771
 772 static int qed_slowpath_setup_int(struct qed_dev *cdev,
 773                                   enum qed_int_mode int_mode)
 774 {
 775         struct qed_sb_cnt_info sb_cnt_info;
 776         int num_l2_queues = 0;
 777         int rc;
 778         int i;
 779
 780         if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
 781                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
 782                 return -EINVAL;
 783         }
 784
 785         memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
 786         cdev->int_params.in.int_mode = int_mode;
 787         for_each_hwfn(cdev, i) {
 788                 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
 789                 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info);
 790                 cdev->int_params.in.num_vectors += sb_cnt_info.cnt;
 791                 cdev->int_params.in.num_vectors++; /* slowpath */
 792         }
 793
 794         /* We want a minimum of one slowpath and one fastpath vector per hwfn */
 795         cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2;
 796
 797         if (is_kdump_kernel()) {
 798                 DP_INFO(cdev,
 799                         "Kdump kernel: Limit the max number of requested MSI-X vectors to %hd\n",
 800                         cdev->int_params.in.min_msix_cnt);
 801                 cdev->int_params.in.num_vectors =
 802                         cdev->int_params.in.min_msix_cnt;
 803         }
 804
 805         rc = qed_set_int_mode(cdev, false);
 806         if (rc)  {
 807                 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n");
 808                 return rc;
 809         }
 810
 811         cdev->int_params.fp_msix_base = cdev->num_hwfns;
 812         cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors -
 813                                        cdev->num_hwfns;
 814
 815         if (!IS_ENABLED(CONFIG_QED_RDMA) ||
 816             !QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev)))
 817                 return 0;
 818
 819         for_each_hwfn(cdev, i)
 820                 num_l2_queues += FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE);
 821
 822         DP_VERBOSE(cdev, QED_MSG_RDMA,
 823                    "cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n",
 824                    cdev->int_params.fp_msix_cnt, num_l2_queues);
 825
 826         if (cdev->int_params.fp_msix_cnt > num_l2_queues) {
 827                 cdev->int_params.rdma_msix_cnt =
 828                         (cdev->int_params.fp_msix_cnt - num_l2_queues)
 829                         / cdev->num_hwfns;
 830                 cdev->int_params.rdma_msix_base =
 831                         cdev->int_params.fp_msix_base + num_l2_queues;
 832                 cdev->int_params.fp_msix_cnt = num_l2_queues;
 833         } else {
 834                 cdev->int_params.rdma_msix_cnt = 0;
 835         }
 836
 837         DP_VERBOSE(cdev, QED_MSG_RDMA, "roce_msix_cnt=%d roce_msix_base=%d\n",
 838                    cdev->int_params.rdma_msix_cnt,
 839                    cdev->int_params.rdma_msix_base);
 840
 841         return 0;
 842 }
 843
 844 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev)
 845 {
 846         int rc;
 847
 848         memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
 849         cdev->int_params.in.int_mode = QED_INT_MODE_MSIX;
 850
 851         qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev),
 852                             &cdev->int_params.in.num_vectors);
 853         if (cdev->num_hwfns > 1) {
 854                 u8 vectors = 0;
 855
 856                 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors);
 857                 cdev->int_params.in.num_vectors += vectors;
 858         }
 859
 860         /* We want a minimum of one fastpath vector per vf hwfn */
 861         cdev->int_params.in.min_msix_cnt = cdev->num_hwfns;
 862
 863         rc = qed_set_int_mode(cdev, true);
 864         if (rc)
 865                 return rc;
 866
 867         cdev->int_params.fp_msix_base = 0;
 868         cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors;
 869
 870         return 0;
 871 }
 872
 873 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len,
 874                    u8 *input_buf, u32 max_size, u8 *unzip_buf)
 875 {
 876         int rc;
 877
 878         p_hwfn->stream->next_in = input_buf;
 879         p_hwfn->stream->avail_in = input_len;
 880         p_hwfn->stream->next_out = unzip_buf;
 881         p_hwfn->stream->avail_out = max_size;
 882
 883         rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS);
 884
 885         if (rc != Z_OK) {
 886                 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n",
 887                            rc);
 888                 return 0;
 889         }
 890
 891         rc = zlib_inflate(p_hwfn->stream, Z_FINISH);
 892         zlib_inflateEnd(p_hwfn->stream);
 893
 894         if (rc != Z_OK && rc != Z_STREAM_END) {
 895                 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n",
 896                            p_hwfn->stream->msg, rc);
 897                 return 0;
 898         }
 899
 900         return p_hwfn->stream->total_out / 4;
 901 }
 902
 903 static int qed_alloc_stream_mem(struct qed_dev *cdev)
 904 {
 905         int i;
 906         void *workspace;
 907
 908         for_each_hwfn(cdev, i) {
 909                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 910
 911                 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL);
 912                 if (!p_hwfn->stream)
 913                         return -ENOMEM;
 914
 915                 workspace = vzalloc(zlib_inflate_workspacesize());
 916                 if (!workspace)
 917                         return -ENOMEM;
 918                 p_hwfn->stream->workspace = workspace;
 919         }
 920
 921         return 0;
 922 }
 923
 924 static void qed_free_stream_mem(struct qed_dev *cdev)
 925 {
 926         int i;
 927
 928         for_each_hwfn(cdev, i) {
 929                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 930
 931                 if (!p_hwfn->stream)
 932                         return;
 933
 934                 vfree(p_hwfn->stream->workspace);
 935                 kfree(p_hwfn->stream);
 936         }
 937 }
 938
 939 static void qed_update_pf_params(struct qed_dev *cdev,
 940                                  struct qed_pf_params *params)
 941 {
 942         int i;
 943
 944         if (IS_ENABLED(CONFIG_QED_RDMA)) {
 945                 params->rdma_pf_params.num_qps = QED_ROCE_QPS;
 946                 params->rdma_pf_params.min_dpis = QED_ROCE_DPIS;
 947                 params->rdma_pf_params.num_srqs = QED_RDMA_SRQS;
 948                 /* divide by 3 the MRs to avoid MF ILT overflow */
 949                 params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX;
 950         }
 951
 952         if (cdev->num_hwfns > 1 || IS_VF(cdev))
 953                 params->eth_pf_params.num_arfs_filters = 0;
 954
 955         /* In case we might support RDMA, don't allow qede to be greedy
 956          * with the L2 contexts. Allow for 64 queues [rx, tx cos, xdp]
 957          * per hwfn.
 958          */
 959         if (QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) {
 960                 u16 *num_cons;
 961
 962                 num_cons = &params->eth_pf_params.num_cons;
 963                 *num_cons = min_t(u16, *num_cons, QED_MAX_L2_CONS);
 964         }
 965
 966         for (i = 0; i < cdev->num_hwfns; i++) {
 967                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 968
 969                 p_hwfn->pf_params = *params;
 970         }
 971 }
 972
 973 static void qed_slowpath_wq_stop(struct qed_dev *cdev)
 974 {
 975         int i;
 976
 977         if (IS_VF(cdev))
 978                 return;
 979
 980         for_each_hwfn(cdev, i) {
 981                 if (!cdev->hwfns[i].slowpath_wq)
 982                         continue;
 983
 984                 flush_workqueue(cdev->hwfns[i].slowpath_wq);
 985                 destroy_workqueue(cdev->hwfns[i].slowpath_wq);
 986         }
 987 }
 988
 989 static void qed_slowpath_task(struct work_struct *work)
 990 {
 991         struct qed_hwfn *hwfn = container_of(work, struct qed_hwfn,
 992                                              slowpath_task.work);
 993         struct qed_ptt *ptt = qed_ptt_acquire(hwfn);
 994
 995         if (!ptt) {
 996                 queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, 0);
 997                 return;
 998         }
 999
1000         if (test_and_clear_bit(QED_SLOWPATH_MFW_TLV_REQ,
1001                                &hwfn->slowpath_task_flags))
1002                 qed_mfw_process_tlv_req(hwfn, ptt);
1003
1004         qed_ptt_release(hwfn, ptt);
1005 }
1006
1007 static int qed_slowpath_wq_start(struct qed_dev *cdev)
1008 {
1009         struct qed_hwfn *hwfn;
1010         char name[NAME_SIZE];
1011         int i;
1012
1013         if (IS_VF(cdev))
1014                 return 0;
1015
1016         for_each_hwfn(cdev, i) {
1017                 hwfn = &cdev->hwfns[i];
1018
1019                 snprintf(name, NAME_SIZE, "slowpath-%02x:%02x.%02x",
1020                          cdev->pdev->bus->number,
1021                          PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
1022
1023                 hwfn->slowpath_wq = alloc_workqueue(name, 0, 0);
1024                 if (!hwfn->slowpath_wq) {
1025                         DP_NOTICE(hwfn, "Cannot create slowpath workqueue\n");
1026                         return -ENOMEM;
1027                 }
1028
1029                 INIT_DELAYED_WORK(&hwfn->slowpath_task, qed_slowpath_task);
1030         }
1031
1032         return 0;
1033 }
1034
1035 static int qed_slowpath_start(struct qed_dev *cdev,
1036                               struct qed_slowpath_params *params)
1037 {
1038         struct qed_drv_load_params drv_load_params;
1039         struct qed_hw_init_params hw_init_params;
1040         struct qed_mcp_drv_version drv_version;
1041         struct qed_tunnel_info tunn_info;
1042         const u8 *data = NULL;
1043         struct qed_hwfn *hwfn;
1044         struct qed_ptt *p_ptt;
1045         int rc = -EINVAL;
1046
1047         if (qed_iov_wq_start(cdev))
1048                 goto err;
1049
1050         if (qed_slowpath_wq_start(cdev))
1051                 goto err;
1052
1053         if (IS_PF(cdev)) {
1054                 rc = reject_firmware(&cdev->firmware, QED_FW_FILE_NAME,
1055                                       &cdev->pdev->dev);
1056                 if (rc) {
1057                         DP_NOTICE(cdev,
1058                                   "Failed to find fw file - /lib/firmware/%s\n",
1059                                   QED_FW_FILE_NAME);
1060                         goto err;
1061                 }
1062
1063                 if (cdev->num_hwfns == 1) {
1064                         p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
1065                         if (p_ptt) {
1066                                 QED_LEADING_HWFN(cdev)->p_arfs_ptt = p_ptt;
1067                         } else {
1068                                 DP_NOTICE(cdev,
1069                                           "Failed to acquire PTT for aRFS\n");
1070                                 goto err;
1071                         }
1072                 }
1073         }
1074
1075         cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS;
1076         rc = qed_nic_setup(cdev);
1077         if (rc)
1078                 goto err;
1079
1080         if (IS_PF(cdev))
1081                 rc = qed_slowpath_setup_int(cdev, params->int_mode);
1082         else
1083                 rc = qed_slowpath_vf_setup_int(cdev);
1084         if (rc)
1085                 goto err1;
1086
1087         if (IS_PF(cdev)) {
1088                 /* Allocate stream for unzipping */
1089                 rc = qed_alloc_stream_mem(cdev);
1090                 if (rc)
1091                         goto err2;
1092
1093                 /* First Dword used to differentiate between various sources */
1094                 data = cdev->firmware->data + sizeof(u32);
1095
1096                 qed_dbg_pf_init(cdev);
1097         }
1098
1099         /* Start the slowpath */
1100         memset(&hw_init_params, 0, sizeof(hw_init_params));
1101         memset(&tunn_info, 0, sizeof(tunn_info));
1102         tunn_info.vxlan.b_mode_enabled = true;
1103         tunn_info.l2_gre.b_mode_enabled = true;
1104         tunn_info.ip_gre.b_mode_enabled = true;
1105         tunn_info.l2_geneve.b_mode_enabled = true;
1106         tunn_info.ip_geneve.b_mode_enabled = true;
1107         tunn_info.vxlan.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1108         tunn_info.l2_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1109         tunn_info.ip_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1110         tunn_info.l2_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1111         tunn_info.ip_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1112         hw_init_params.p_tunn = &tunn_info;
1113         hw_init_params.b_hw_start = true;
1114         hw_init_params.int_mode = cdev->int_params.out.int_mode;
1115         hw_init_params.allow_npar_tx_switch = true;
1116         hw_init_params.bin_fw_data = data;
1117
1118         memset(&drv_load_params, 0, sizeof(drv_load_params));
1119         drv_load_params.is_crash_kernel = is_kdump_kernel();
1120         drv_load_params.mfw_timeout_val = QED_LOAD_REQ_LOCK_TO_DEFAULT;
1121         drv_load_params.avoid_eng_reset = false;
1122         drv_load_params.override_force_load = QED_OVERRIDE_FORCE_LOAD_NONE;
1123         hw_init_params.p_drv_load_params = &drv_load_params;
1124
1125         rc = qed_hw_init(cdev, &hw_init_params);
1126         if (rc)
1127                 goto err2;
1128
1129         DP_INFO(cdev,
1130                 "HW initialization and function start completed successfully\n");
1131
1132         if (IS_PF(cdev)) {
1133                 cdev->tunn_feature_mask = (BIT(QED_MODE_VXLAN_TUNN) |
1134                                            BIT(QED_MODE_L2GENEVE_TUNN) |
1135                                            BIT(QED_MODE_IPGENEVE_TUNN) |
1136                                            BIT(QED_MODE_L2GRE_TUNN) |
1137                                            BIT(QED_MODE_IPGRE_TUNN));
1138         }
1139
1140         /* Allocate LL2 interface if needed */
1141         if (QED_LEADING_HWFN(cdev)->using_ll2) {
1142                 rc = qed_ll2_alloc_if(cdev);
1143                 if (rc)
1144                         goto err3;
1145         }
1146         if (IS_PF(cdev)) {
1147                 hwfn = QED_LEADING_HWFN(cdev);
1148                 drv_version.version = (params->drv_major << 24) |
1149                                       (params->drv_minor << 16) |
1150                                       (params->drv_rev << 8) |
1151                                       (params->drv_eng);
1152                 strlcpy(drv_version.name, params->name,
1153                         MCP_DRV_VER_STR_SIZE - 4);
1154                 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
1155                                               &drv_version);
1156                 if (rc) {
1157                         DP_NOTICE(cdev, "Failed sending drv version command\n");
1158                         goto err4;
1159                 }
1160         }
1161
1162         qed_reset_vport_stats(cdev);
1163
1164         return 0;
1165
1166 err4:
1167         qed_ll2_dealloc_if(cdev);
1168 err3:
1169         qed_hw_stop(cdev);
1170 err2:
1171         qed_hw_timers_stop_all(cdev);
1172         if (IS_PF(cdev))
1173                 qed_slowpath_irq_free(cdev);
1174         qed_free_stream_mem(cdev);
1175         qed_disable_msix(cdev);
1176 err1:
1177         qed_resc_free(cdev);
1178 err:
1179         if (IS_PF(cdev))
1180                 release_firmware(cdev->firmware);
1181
1182         if (IS_PF(cdev) && (cdev->num_hwfns == 1) &&
1183             QED_LEADING_HWFN(cdev)->p_arfs_ptt)
1184                 qed_ptt_release(QED_LEADING_HWFN(cdev),
1185                                 QED_LEADING_HWFN(cdev)->p_arfs_ptt);
1186
1187         qed_iov_wq_stop(cdev, false);
1188
1189         qed_slowpath_wq_stop(cdev);
1190
1191         return rc;
1192 }
1193
1194 static int qed_slowpath_stop(struct qed_dev *cdev)
1195 {
1196         if (!cdev)
1197                 return -ENODEV;
1198
1199         qed_slowpath_wq_stop(cdev);
1200
1201         qed_ll2_dealloc_if(cdev);
1202
1203         if (IS_PF(cdev)) {
1204                 if (cdev->num_hwfns == 1)
1205                         qed_ptt_release(QED_LEADING_HWFN(cdev),
1206                                         QED_LEADING_HWFN(cdev)->p_arfs_ptt);
1207                 qed_free_stream_mem(cdev);
1208                 if (IS_QED_ETH_IF(cdev))
1209                         qed_sriov_disable(cdev, true);
1210         }
1211
1212         qed_nic_stop(cdev);
1213
1214         if (IS_PF(cdev))
1215                 qed_slowpath_irq_free(cdev);
1216
1217         qed_disable_msix(cdev);
1218
1219         qed_resc_free(cdev);
1220
1221         qed_iov_wq_stop(cdev, true);
1222
1223         if (IS_PF(cdev))
1224                 release_firmware(cdev->firmware);
1225
1226         return 0;
1227 }
1228
1229 static void qed_set_name(struct qed_dev *cdev, char name[NAME_SIZE])
1230 {
1231         int i;
1232
1233         memcpy(cdev->name, name, NAME_SIZE);
1234         for_each_hwfn(cdev, i)
1235                 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
1236 }
1237
1238 static u32 qed_sb_init(struct qed_dev *cdev,
1239                        struct qed_sb_info *sb_info,
1240                        void *sb_virt_addr,
1241                        dma_addr_t sb_phy_addr, u16 sb_id,
1242                        enum qed_sb_type type)
1243 {
1244         struct qed_hwfn *p_hwfn;
1245         struct qed_ptt *p_ptt;
1246         int hwfn_index;
1247         u16 rel_sb_id;
1248         u8 n_hwfns;
1249         u32 rc;
1250
1251         /* RoCE uses single engine and CMT uses two engines. When using both
1252          * we force only a single engine. Storage uses only engine 0 too.
1253          */
1254         if (type == QED_SB_TYPE_L2_QUEUE)
1255                 n_hwfns = cdev->num_hwfns;
1256         else
1257                 n_hwfns = 1;
1258
1259         hwfn_index = sb_id % n_hwfns;
1260         p_hwfn = &cdev->hwfns[hwfn_index];
1261         rel_sb_id = sb_id / n_hwfns;
1262
1263         DP_VERBOSE(cdev, NETIF_MSG_INTR,
1264                    "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1265                    hwfn_index, rel_sb_id, sb_id);
1266
1267         if (IS_PF(p_hwfn->cdev)) {
1268                 p_ptt = qed_ptt_acquire(p_hwfn);
1269                 if (!p_ptt)
1270                         return -EBUSY;
1271
1272                 rc = qed_int_sb_init(p_hwfn, p_ptt, sb_info, sb_virt_addr,
1273                                      sb_phy_addr, rel_sb_id);
1274                 qed_ptt_release(p_hwfn, p_ptt);
1275         } else {
1276                 rc = qed_int_sb_init(p_hwfn, NULL, sb_info, sb_virt_addr,
1277                                      sb_phy_addr, rel_sb_id);
1278         }
1279
1280         return rc;
1281 }
1282
1283 static u32 qed_sb_release(struct qed_dev *cdev,
1284                           struct qed_sb_info *sb_info, u16 sb_id)
1285 {
1286         struct qed_hwfn *p_hwfn;
1287         int hwfn_index;
1288         u16 rel_sb_id;
1289         u32 rc;
1290
1291         hwfn_index = sb_id % cdev->num_hwfns;
1292         p_hwfn = &cdev->hwfns[hwfn_index];
1293         rel_sb_id = sb_id / cdev->num_hwfns;
1294
1295         DP_VERBOSE(cdev, NETIF_MSG_INTR,
1296                    "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1297                    hwfn_index, rel_sb_id, sb_id);
1298
1299         rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id);
1300
1301         return rc;
1302 }
1303
1304 static bool qed_can_link_change(struct qed_dev *cdev)
1305 {
1306         return true;
1307 }
1308
1309 static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params)
1310 {
1311         struct qed_hwfn *hwfn;
1312         struct qed_mcp_link_params *link_params;
1313         struct qed_ptt *ptt;
1314         int rc;
1315
1316         if (!cdev)
1317                 return -ENODEV;
1318
1319         /* The link should be set only once per PF */
1320         hwfn = &cdev->hwfns[0];
1321
1322         /* When VF wants to set link, force it to read the bulletin instead.
1323          * This mimics the PF behavior, where a noitification [both immediate
1324          * and possible later] would be generated when changing properties.
1325          */
1326         if (IS_VF(cdev)) {
1327                 qed_schedule_iov(hwfn, QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG);
1328                 return 0;
1329         }
1330
1331         ptt = qed_ptt_acquire(hwfn);
1332         if (!ptt)
1333                 return -EBUSY;
1334
1335         link_params = qed_mcp_get_link_params(hwfn);
1336         if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
1337                 link_params->speed.autoneg = params->autoneg;
1338         if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
1339                 link_params->speed.advertised_speeds = 0;
1340                 if ((params->adv_speeds & QED_LM_1000baseT_Half_BIT) ||
1341                     (params->adv_speeds & QED_LM_1000baseT_Full_BIT))
1342                         link_params->speed.advertised_speeds |=
1343                             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
1344                 if (params->adv_speeds & QED_LM_10000baseKR_Full_BIT)
1345                         link_params->speed.advertised_speeds |=
1346                             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
1347                 if (params->adv_speeds & QED_LM_25000baseKR_Full_BIT)
1348                         link_params->speed.advertised_speeds |=
1349                             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
1350                 if (params->adv_speeds & QED_LM_40000baseLR4_Full_BIT)
1351                         link_params->speed.advertised_speeds |=
1352                             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
1353                 if (params->adv_speeds & QED_LM_50000baseKR2_Full_BIT)
1354                         link_params->speed.advertised_speeds |=
1355                             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
1356                 if (params->adv_speeds & QED_LM_100000baseKR4_Full_BIT)
1357                         link_params->speed.advertised_speeds |=
1358                             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G;
1359         }
1360         if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED)
1361                 link_params->speed.forced_speed = params->forced_speed;
1362         if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) {
1363                 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1364                         link_params->pause.autoneg = true;
1365                 else
1366                         link_params->pause.autoneg = false;
1367                 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE)
1368                         link_params->pause.forced_rx = true;
1369                 else
1370                         link_params->pause.forced_rx = false;
1371                 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE)
1372                         link_params->pause.forced_tx = true;
1373                 else
1374                         link_params->pause.forced_tx = false;
1375         }
1376         if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) {
1377                 switch (params->loopback_mode) {
1378                 case QED_LINK_LOOPBACK_INT_PHY:
1379                         link_params->loopback_mode = ETH_LOOPBACK_INT_PHY;
1380                         break;
1381                 case QED_LINK_LOOPBACK_EXT_PHY:
1382                         link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY;
1383                         break;
1384                 case QED_LINK_LOOPBACK_EXT:
1385                         link_params->loopback_mode = ETH_LOOPBACK_EXT;
1386                         break;
1387                 case QED_LINK_LOOPBACK_MAC:
1388                         link_params->loopback_mode = ETH_LOOPBACK_MAC;
1389                         break;
1390                 default:
1391                         link_params->loopback_mode = ETH_LOOPBACK_NONE;
1392                         break;
1393                 }
1394         }
1395
1396         if (params->override_flags & QED_LINK_OVERRIDE_EEE_CONFIG)
1397                 memcpy(&link_params->eee, &params->eee,
1398                        sizeof(link_params->eee));
1399
1400         rc = qed_mcp_set_link(hwfn, ptt, params->link_up);
1401
1402         qed_ptt_release(hwfn, ptt);
1403
1404         return rc;
1405 }
1406
1407 static int qed_get_port_type(u32 media_type)
1408 {
1409         int port_type;
1410
1411         switch (media_type) {
1412         case MEDIA_SFPP_10G_FIBER:
1413         case MEDIA_SFP_1G_FIBER:
1414         case MEDIA_XFP_FIBER:
1415         case MEDIA_MODULE_FIBER:
1416         case MEDIA_KR:
1417                 port_type = PORT_FIBRE;
1418                 break;
1419         case MEDIA_DA_TWINAX:
1420                 port_type = PORT_DA;
1421                 break;
1422         case MEDIA_BASE_T:
1423                 port_type = PORT_TP;
1424                 break;
1425         case MEDIA_NOT_PRESENT:
1426                 port_type = PORT_NONE;
1427                 break;
1428         case MEDIA_UNSPECIFIED:
1429         default:
1430                 port_type = PORT_OTHER;
1431                 break;
1432         }
1433         return port_type;
1434 }
1435
1436 static int qed_get_link_data(struct qed_hwfn *hwfn,
1437                              struct qed_mcp_link_params *params,
1438                              struct qed_mcp_link_state *link,
1439                              struct qed_mcp_link_capabilities *link_caps)
1440 {
1441         void *p;
1442
1443         if (!IS_PF(hwfn->cdev)) {
1444                 qed_vf_get_link_params(hwfn, params);
1445                 qed_vf_get_link_state(hwfn, link);
1446                 qed_vf_get_link_caps(hwfn, link_caps);
1447
1448                 return 0;
1449         }
1450
1451         p = qed_mcp_get_link_params(hwfn);
1452         if (!p)
1453                 return -ENXIO;
1454         memcpy(params, p, sizeof(*params));
1455
1456         p = qed_mcp_get_link_state(hwfn);
1457         if (!p)
1458                 return -ENXIO;
1459         memcpy(link, p, sizeof(*link));
1460
1461         p = qed_mcp_get_link_capabilities(hwfn);
1462         if (!p)
1463                 return -ENXIO;
1464         memcpy(link_caps, p, sizeof(*link_caps));
1465
1466         return 0;
1467 }
1468
1469 static void qed_fill_link(struct qed_hwfn *hwfn,
1470                           struct qed_ptt *ptt,
1471                           struct qed_link_output *if_link)
1472 {
1473         struct qed_mcp_link_params params;
1474         struct qed_mcp_link_state link;
1475         struct qed_mcp_link_capabilities link_caps;
1476         u32 media_type;
1477
1478         memset(if_link, 0, sizeof(*if_link));
1479
1480         /* Prepare source inputs */
1481         if (qed_get_link_data(hwfn, &params, &link, &link_caps)) {
1482                 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n");
1483                 return;
1484         }
1485
1486         /* Set the link parameters to pass to protocol driver */
1487         if (link.link_up)
1488                 if_link->link_up = true;
1489
1490         /* TODO - at the moment assume supported and advertised speed equal */
1491         if_link->supported_caps = QED_LM_FIBRE_BIT;
1492         if (link_caps.default_speed_autoneg)
1493                 if_link->supported_caps |= QED_LM_Autoneg_BIT;
1494         if (params.pause.autoneg ||
1495             (params.pause.forced_rx && params.pause.forced_tx))
1496                 if_link->supported_caps |= QED_LM_Asym_Pause_BIT;
1497         if (params.pause.autoneg || params.pause.forced_rx ||
1498             params.pause.forced_tx)
1499                 if_link->supported_caps |= QED_LM_Pause_BIT;
1500
1501         if_link->advertised_caps = if_link->supported_caps;
1502         if (params.speed.autoneg)
1503                 if_link->advertised_caps |= QED_LM_Autoneg_BIT;
1504         else
1505                 if_link->advertised_caps &= ~QED_LM_Autoneg_BIT;
1506         if (params.speed.advertised_speeds &
1507             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1508                 if_link->advertised_caps |= QED_LM_1000baseT_Half_BIT |
1509                     QED_LM_1000baseT_Full_BIT;
1510         if (params.speed.advertised_speeds &
1511             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1512                 if_link->advertised_caps |= QED_LM_10000baseKR_Full_BIT;
1513         if (params.speed.advertised_speeds &
1514             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1515                 if_link->advertised_caps |= QED_LM_25000baseKR_Full_BIT;
1516         if (params.speed.advertised_speeds &
1517             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1518                 if_link->advertised_caps |= QED_LM_40000baseLR4_Full_BIT;
1519         if (params.speed.advertised_speeds &
1520             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1521                 if_link->advertised_caps |= QED_LM_50000baseKR2_Full_BIT;
1522         if (params.speed.advertised_speeds &
1523             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1524                 if_link->advertised_caps |= QED_LM_100000baseKR4_Full_BIT;
1525
1526         if (link_caps.speed_capabilities &
1527             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1528                 if_link->supported_caps |= QED_LM_1000baseT_Half_BIT |
1529                     QED_LM_1000baseT_Full_BIT;
1530         if (link_caps.speed_capabilities &
1531             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1532                 if_link->supported_caps |= QED_LM_10000baseKR_Full_BIT;
1533         if (link_caps.speed_capabilities &
1534             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1535                 if_link->supported_caps |= QED_LM_25000baseKR_Full_BIT;
1536         if (link_caps.speed_capabilities &
1537             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1538                 if_link->supported_caps |= QED_LM_40000baseLR4_Full_BIT;
1539         if (link_caps.speed_capabilities &
1540             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1541                 if_link->supported_caps |= QED_LM_50000baseKR2_Full_BIT;
1542         if (link_caps.speed_capabilities &
1543             NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1544                 if_link->supported_caps |= QED_LM_100000baseKR4_Full_BIT;
1545
1546         if (link.link_up)
1547                 if_link->speed = link.speed;
1548
1549         /* TODO - fill duplex properly */
1550         if_link->duplex = DUPLEX_FULL;
1551         qed_mcp_get_media_type(hwfn, ptt, &media_type);
1552         if_link->port = qed_get_port_type(media_type);
1553
1554         if_link->autoneg = params.speed.autoneg;
1555
1556         if (params.pause.autoneg)
1557                 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1558         if (params.pause.forced_rx)
1559                 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1560         if (params.pause.forced_tx)
1561                 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1562
1563         /* Link partner capabilities */
1564         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_HD)
1565                 if_link->lp_caps |= QED_LM_1000baseT_Half_BIT;
1566         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_FD)
1567                 if_link->lp_caps |= QED_LM_1000baseT_Full_BIT;
1568         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G)
1569                 if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT;
1570         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G)
1571                 if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT;
1572         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G)
1573                 if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT;
1574         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G)
1575                 if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT;
1576         if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G)
1577                 if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT;
1578
1579         if (link.an_complete)
1580                 if_link->lp_caps |= QED_LM_Autoneg_BIT;
1581
1582         if (link.partner_adv_pause)
1583                 if_link->lp_caps |= QED_LM_Pause_BIT;
1584         if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE ||
1585             link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE)
1586                 if_link->lp_caps |= QED_LM_Asym_Pause_BIT;
1587
1588         if (link_caps.default_eee == QED_MCP_EEE_UNSUPPORTED) {
1589                 if_link->eee_supported = false;
1590         } else {
1591                 if_link->eee_supported = true;
1592                 if_link->eee_active = link.eee_active;
1593                 if_link->sup_caps = link_caps.eee_speed_caps;
1594                 /* MFW clears adv_caps on eee disable; use configured value */
1595                 if_link->eee.adv_caps = link.eee_adv_caps ? link.eee_adv_caps :
1596                                         params.eee.adv_caps;
1597                 if_link->eee.lp_adv_caps = link.eee_lp_adv_caps;
1598                 if_link->eee.enable = params.eee.enable;
1599                 if_link->eee.tx_lpi_enable = params.eee.tx_lpi_enable;
1600                 if_link->eee.tx_lpi_timer = params.eee.tx_lpi_timer;
1601         }
1602 }
1603
1604 static void qed_get_current_link(struct qed_dev *cdev,
1605                                  struct qed_link_output *if_link)
1606 {
1607         struct qed_hwfn *hwfn;
1608         struct qed_ptt *ptt;
1609         int i;
1610
1611         hwfn = &cdev->hwfns[0];
1612         if (IS_PF(cdev)) {
1613                 ptt = qed_ptt_acquire(hwfn);
1614                 if (ptt) {
1615                         qed_fill_link(hwfn, ptt, if_link);
1616                         qed_ptt_release(hwfn, ptt);
1617                 } else {
1618                         DP_NOTICE(hwfn, "Failed to fill link; No PTT\n");
1619                 }
1620         } else {
1621                 qed_fill_link(hwfn, NULL, if_link);
1622         }
1623
1624         for_each_hwfn(cdev, i)
1625                 qed_inform_vf_link_state(&cdev->hwfns[i]);
1626 }
1627
1628 void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt)
1629 {
1630         void *cookie = hwfn->cdev->ops_cookie;
1631         struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common;
1632         struct qed_link_output if_link;
1633
1634         qed_fill_link(hwfn, ptt, &if_link);
1635         qed_inform_vf_link_state(hwfn);
1636
1637         if (IS_LEAD_HWFN(hwfn) && cookie)
1638                 op->link_update(cookie, &if_link);
1639 }
1640
1641 static int qed_drain(struct qed_dev *cdev)
1642 {
1643         struct qed_hwfn *hwfn;
1644         struct qed_ptt *ptt;
1645         int i, rc;
1646
1647         if (IS_VF(cdev))
1648                 return 0;
1649
1650         for_each_hwfn(cdev, i) {
1651                 hwfn = &cdev->hwfns[i];
1652                 ptt = qed_ptt_acquire(hwfn);
1653                 if (!ptt) {
1654                         DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n");
1655                         return -EBUSY;
1656                 }
1657                 rc = qed_mcp_drain(hwfn, ptt);
1658                 qed_ptt_release(hwfn, ptt);
1659                 if (rc)
1660                         return rc;
1661         }
1662
1663         return 0;
1664 }
1665
1666 static u32 qed_nvm_flash_image_access_crc(struct qed_dev *cdev,
1667                                           struct qed_nvm_image_att *nvm_image,
1668                                           u32 *crc)
1669 {
1670         u8 *buf = NULL;
1671         int rc, j;
1672         u32 val;
1673
1674         /* Allocate a buffer for holding the nvram image */
1675         buf = kzalloc(nvm_image->length, GFP_KERNEL);
1676         if (!buf)
1677                 return -ENOMEM;
1678
1679         /* Read image into buffer */
1680         rc = qed_mcp_nvm_read(cdev, nvm_image->start_addr,
1681                               buf, nvm_image->length);
1682         if (rc) {
1683                 DP_ERR(cdev, "Failed reading image from nvm\n");
1684                 goto out;
1685         }
1686
1687         /* Convert the buffer into big-endian format (excluding the
1688          * closing 4 bytes of CRC).
1689          */
1690         for (j = 0; j < nvm_image->length - 4; j += 4) {
1691                 val = cpu_to_be32(*(u32 *)&buf[j]);
1692                 *(u32 *)&buf[j] = val;
1693         }
1694
1695         /* Calc CRC for the "actual" image buffer, i.e. not including
1696          * the last 4 CRC bytes.
1697          */
1698         *crc = (~cpu_to_be32(crc32(0xffffffff, buf, nvm_image->length - 4)));
1699
1700 out:
1701         kfree(buf);
1702
1703         return rc;
1704 }
1705
1706 /* Binary file format -
1707  *     /----------------------------------------------------------------------\
1708  * 0B  |                       0x4 [command index]                            |
1709  * 4B  | image_type     | Options        |  Number of register settings       |
1710  * 8B  |                       Value                                          |
1711  * 12B |                       Mask                                           |
1712  * 16B |                       Offset                                         |
1713  *     \----------------------------------------------------------------------/
1714  * There can be several Value-Mask-Offset sets as specified by 'Number of...'.
1715  * Options - 0'b - Calculate & Update CRC for image
1716  */
1717 static int qed_nvm_flash_image_access(struct qed_dev *cdev, const u8 **data,
1718                                       bool *check_resp)
1719 {
1720         struct qed_nvm_image_att nvm_image;
1721         struct qed_hwfn *p_hwfn;
1722         bool is_crc = false;
1723         u32 image_type;
1724         int rc = 0, i;
1725         u16 len;
1726
1727         *data += 4;
1728         image_type = **data;
1729         p_hwfn = QED_LEADING_HWFN(cdev);
1730         for (i = 0; i < p_hwfn->nvm_info.num_images; i++)
1731                 if (image_type == p_hwfn->nvm_info.image_att[i].image_type)
1732                         break;
1733         if (i == p_hwfn->nvm_info.num_images) {
1734                 DP_ERR(cdev, "Failed to find nvram image of type %08x\n",
1735                        image_type);
1736                 return -ENOENT;
1737         }
1738
1739         nvm_image.start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr;
1740         nvm_image.length = p_hwfn->nvm_info.image_att[i].len;
1741
1742         DP_VERBOSE(cdev, NETIF_MSG_DRV,
1743                    "Read image %02x; type = %08x; NVM [%08x,...,%08x]\n",
1744                    **data, image_type, nvm_image.start_addr,
1745                    nvm_image.start_addr + nvm_image.length - 1);
1746         (*data)++;
1747         is_crc = !!(**data & BIT(0));
1748         (*data)++;
1749         len = *((u16 *)*data);
1750         *data += 2;
1751         if (is_crc) {
1752                 u32 crc = 0;
1753
1754                 rc = qed_nvm_flash_image_access_crc(cdev, &nvm_image, &crc);
1755                 if (rc) {
1756                         DP_ERR(cdev, "Failed calculating CRC, rc = %d\n", rc);
1757                         goto exit;
1758                 }
1759
1760                 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM,
1761                                        (nvm_image.start_addr +
1762                                         nvm_image.length - 4), (u8 *)&crc, 4);
1763                 if (rc)
1764                         DP_ERR(cdev, "Failed writing to %08x, rc = %d\n",
1765                                nvm_image.start_addr + nvm_image.length - 4, rc);
1766                 goto exit;
1767         }
1768
1769         /* Iterate over the values for setting */
1770         while (len) {
1771                 u32 offset, mask, value, cur_value;
1772                 u8 buf[4];
1773
1774                 value = *((u32 *)*data);
1775                 *data += 4;
1776                 mask = *((u32 *)*data);
1777                 *data += 4;
1778                 offset = *((u32 *)*data);
1779                 *data += 4;
1780
1781                 rc = qed_mcp_nvm_read(cdev, nvm_image.start_addr + offset, buf,
1782                                       4);
1783                 if (rc) {
1784                         DP_ERR(cdev, "Failed reading from %08x\n",
1785                                nvm_image.start_addr + offset);
1786                         goto exit;
1787                 }
1788
1789                 cur_value = le32_to_cpu(*((__le32 *)buf));
1790                 DP_VERBOSE(cdev, NETIF_MSG_DRV,
1791                            "NVM %08x: %08x -> %08x [Value %08x Mask %08x]\n",
1792                            nvm_image.start_addr + offset, cur_value,
1793                            (cur_value & ~mask) | (value & mask), value, mask);
1794                 value = (value & mask) | (cur_value & ~mask);
1795                 rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM,
1796                                        nvm_image.start_addr + offset,
1797                                        (u8 *)&value, 4);
1798                 if (rc) {
1799                         DP_ERR(cdev, "Failed writing to %08x\n",
1800                                nvm_image.start_addr + offset);
1801                         goto exit;
1802                 }
1803
1804                 len--;
1805         }
1806 exit:
1807         return rc;
1808 }
1809
1810 /* Binary file format -
1811  *     /----------------------------------------------------------------------\
1812  * 0B  |                       0x3 [command index]                            |
1813  * 4B  | b'0: check_response?   | b'1-31  reserved                            |
1814  * 8B  | File-type |                   reserved                               |
1815  *     \----------------------------------------------------------------------/
1816  *     Start a new file of the provided type
1817  */
1818 static int qed_nvm_flash_image_file_start(struct qed_dev *cdev,
1819                                           const u8 **data, bool *check_resp)
1820 {
1821         int rc;
1822
1823         *data += 4;
1824         *check_resp = !!(**data & BIT(0));
1825         *data += 4;
1826
1827         DP_VERBOSE(cdev, NETIF_MSG_DRV,
1828                    "About to start a new file of type %02x\n", **data);
1829         rc = qed_mcp_nvm_put_file_begin(cdev, **data);
1830         *data += 4;
1831
1832         return rc;
1833 }
1834
1835 /* Binary file format -
1836  *     /----------------------------------------------------------------------\
1837  * 0B  |                       0x2 [command index]                            |
1838  * 4B  |                       Length in bytes                                |
1839  * 8B  | b'0: check_response?   | b'1-31  reserved                            |
1840  * 12B |                       Offset in bytes                                |
1841  * 16B |                       Data ...                                       |
1842  *     \----------------------------------------------------------------------/
1843  *     Write data as part of a file that was previously started. Data should be
1844  *     of length equal to that provided in the message
1845  */
1846 static int qed_nvm_flash_image_file_data(struct qed_dev *cdev,
1847                                          const u8 **data, bool *check_resp)
1848 {
1849         u32 offset, len;
1850         int rc;
1851
1852         *data += 4;
1853         len = *((u32 *)(*data));
1854         *data += 4;
1855         *check_resp = !!(**data & BIT(0));
1856         *data += 4;
1857         offset = *((u32 *)(*data));
1858         *data += 4;
1859
1860         DP_VERBOSE(cdev, NETIF_MSG_DRV,
1861                    "About to write File-data: %08x bytes to offset %08x\n",
1862                    len, offset);
1863
1864         rc = qed_mcp_nvm_write(cdev, QED_PUT_FILE_DATA, offset,
1865                                (char *)(*data), len);
1866         *data += len;
1867
1868         return rc;
1869 }
1870
1871 /* Binary file format [General header] -
1872  *     /----------------------------------------------------------------------\
1873  * 0B  |                       QED_NVM_SIGNATURE                              |
1874  * 4B  |                       Length in bytes                                |
1875  * 8B  | Highest command in this batchfile |          Reserved                |
1876  *     \----------------------------------------------------------------------/
1877  */
1878 static int qed_nvm_flash_image_validate(struct qed_dev *cdev,
1879                                         const struct firmware *image,
1880                                         const u8 **data)
1881 {
1882         u32 signature, len;
1883
1884         /* Check minimum size */
1885         if (image->size < 12) {
1886                 DP_ERR(cdev, "Image is too short [%08x]\n", (u32)image->size);
1887                 return -EINVAL;
1888         }
1889
1890         /* Check signature */
1891         signature = *((u32 *)(*data));
1892         if (signature != QED_NVM_SIGNATURE) {
1893                 DP_ERR(cdev, "Wrong signature '%08x'\n", signature);
1894                 return -EINVAL;
1895         }
1896
1897         *data += 4;
1898         /* Validate internal size equals the image-size */
1899         len = *((u32 *)(*data));
1900         if (len != image->size) {
1901                 DP_ERR(cdev, "Size mismatch: internal = %08x image = %08x\n",
1902                        len, (u32)image->size);
1903                 return -EINVAL;
1904         }
1905
1906         *data += 4;
1907         /* Make sure driver familiar with all commands necessary for this */
1908         if (*((u16 *)(*data)) >= QED_NVM_FLASH_CMD_NVM_MAX) {
1909                 DP_ERR(cdev, "File contains unsupported commands [Need %04x]\n",
1910                        *((u16 *)(*data)));
1911                 return -EINVAL;
1912         }
1913
1914         *data += 4;
1915
1916         return 0;
1917 }
1918
1919 static int qed_nvm_flash(struct qed_dev *cdev, const char *name)
1920 {
1921         const struct firmware *image;
1922         const u8 *data, *data_end;
1923         u32 cmd_type;
1924         int rc;
1925
1926         rc = reject_firmware(&image, name, &cdev->pdev->dev);
1927         if (rc) {
1928                 DP_ERR(cdev, "Failed to find '%s'\n", name);
1929                 return rc;
1930         }
1931
1932         DP_VERBOSE(cdev, NETIF_MSG_DRV,
1933                    "Flashing '%s' - firmware's data at %p, size is %08x\n",
1934                    name, image->data, (u32)image->size);
1935         data = image->data;
1936         data_end = data + image->size;
1937
1938         rc = qed_nvm_flash_image_validate(cdev, image, &data);
1939         if (rc)
1940                 goto exit;
1941
1942         while (data < data_end) {
1943                 bool check_resp = false;
1944
1945                 /* Parse the actual command */
1946                 cmd_type = *((u32 *)data);
1947                 switch (cmd_type) {
1948                 case QED_NVM_FLASH_CMD_FILE_DATA:
1949                         rc = qed_nvm_flash_image_file_data(cdev, &data,
1950                                                            &check_resp);
1951                         break;
1952                 case QED_NVM_FLASH_CMD_FILE_START:
1953                         rc = qed_nvm_flash_image_file_start(cdev, &data,
1954                                                             &check_resp);
1955                         break;
1956                 case QED_NVM_FLASH_CMD_NVM_CHANGE:
1957                         rc = qed_nvm_flash_image_access(cdev, &data,
1958                                                         &check_resp);
1959                         break;
1960                 default:
1961                         DP_ERR(cdev, "Unknown command %08x\n", cmd_type);
1962                         rc = -EINVAL;
1963                         goto exit;
1964                 }
1965
1966                 if (rc) {
1967                         DP_ERR(cdev, "Command %08x failed\n", cmd_type);
1968                         goto exit;
1969                 }
1970
1971                 /* Check response if needed */
1972                 if (check_resp) {
1973                         u32 mcp_response = 0;
1974
1975                         if (qed_mcp_nvm_resp(cdev, (u8 *)&mcp_response)) {
1976                                 DP_ERR(cdev, "Failed getting MCP response\n");
1977                                 rc = -EINVAL;
1978                                 goto exit;
1979                         }
1980
1981                         switch (mcp_response & FW_MSG_CODE_MASK) {
1982                         case FW_MSG_CODE_OK:
1983                         case FW_MSG_CODE_NVM_OK:
1984                         case FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK:
1985                         case FW_MSG_CODE_PHY_OK:
1986                                 break;
1987                         default:
1988                                 DP_ERR(cdev, "MFW returns error: %08x\n",
1989                                        mcp_response);
1990                                 rc = -EINVAL;
1991                                 goto exit;
1992                         }
1993                 }
1994         }
1995
1996 exit:
1997         release_firmware(image);
1998
1999         return rc;
2000 }
2001
2002 static int qed_nvm_get_image(struct qed_dev *cdev, enum qed_nvm_images type,
2003                              u8 *buf, u16 len)
2004 {
2005         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2006
2007         return qed_mcp_get_nvm_image(hwfn, type, buf, len);
2008 }
2009
2010 static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal,
2011                             void *handle)
2012 {
2013                 return qed_set_queue_coalesce(rx_coal, tx_coal, handle);
2014 }
2015
2016 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode)
2017 {
2018         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2019         struct qed_ptt *ptt;
2020         int status = 0;
2021
2022         ptt = qed_ptt_acquire(hwfn);
2023         if (!ptt)
2024                 return -EAGAIN;
2025
2026         status = qed_mcp_set_led(hwfn, ptt, mode);
2027
2028         qed_ptt_release(hwfn, ptt);
2029
2030         return status;
2031 }
2032
2033 static int qed_update_wol(struct qed_dev *cdev, bool enabled)
2034 {
2035         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2036         struct qed_ptt *ptt;
2037         int rc = 0;
2038
2039         if (IS_VF(cdev))
2040                 return 0;
2041
2042         ptt = qed_ptt_acquire(hwfn);
2043         if (!ptt)
2044                 return -EAGAIN;
2045
2046         rc = qed_mcp_ov_update_wol(hwfn, ptt, enabled ? QED_OV_WOL_ENABLED
2047                                    : QED_OV_WOL_DISABLED);
2048         if (rc)
2049                 goto out;
2050         rc = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
2051
2052 out:
2053         qed_ptt_release(hwfn, ptt);
2054         return rc;
2055 }
2056
2057 static int qed_update_drv_state(struct qed_dev *cdev, bool active)
2058 {
2059         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2060         struct qed_ptt *ptt;
2061         int status = 0;
2062
2063         if (IS_VF(cdev))
2064                 return 0;
2065
2066         ptt = qed_ptt_acquire(hwfn);
2067         if (!ptt)
2068                 return -EAGAIN;
2069
2070         status = qed_mcp_ov_update_driver_state(hwfn, ptt, active ?
2071                                                 QED_OV_DRIVER_STATE_ACTIVE :
2072                                                 QED_OV_DRIVER_STATE_DISABLED);
2073
2074         qed_ptt_release(hwfn, ptt);
2075
2076         return status;
2077 }
2078
2079 static int qed_update_mac(struct qed_dev *cdev, u8 *mac)
2080 {
2081         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2082         struct qed_ptt *ptt;
2083         int status = 0;
2084
2085         if (IS_VF(cdev))
2086                 return 0;
2087
2088         ptt = qed_ptt_acquire(hwfn);
2089         if (!ptt)
2090                 return -EAGAIN;
2091
2092         status = qed_mcp_ov_update_mac(hwfn, ptt, mac);
2093         if (status)
2094                 goto out;
2095
2096         status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
2097
2098 out:
2099         qed_ptt_release(hwfn, ptt);
2100         return status;
2101 }
2102
2103 static int qed_update_mtu(struct qed_dev *cdev, u16 mtu)
2104 {
2105         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2106         struct qed_ptt *ptt;
2107         int status = 0;
2108
2109         if (IS_VF(cdev))
2110                 return 0;
2111
2112         ptt = qed_ptt_acquire(hwfn);
2113         if (!ptt)
2114                 return -EAGAIN;
2115
2116         status = qed_mcp_ov_update_mtu(hwfn, ptt, mtu);
2117         if (status)
2118                 goto out;
2119
2120         status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
2121
2122 out:
2123         qed_ptt_release(hwfn, ptt);
2124         return status;
2125 }
2126
2127 static int qed_read_module_eeprom(struct qed_dev *cdev, char *buf,
2128                                   u8 dev_addr, u32 offset, u32 len)
2129 {
2130         struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2131         struct qed_ptt *ptt;
2132         int rc = 0;
2133
2134         if (IS_VF(cdev))
2135                 return 0;
2136
2137         ptt = qed_ptt_acquire(hwfn);
2138         if (!ptt)
2139                 return -EAGAIN;
2140
2141         rc = qed_mcp_phy_sfp_read(hwfn, ptt, MFW_PORT(hwfn), dev_addr,
2142                                   offset, len, buf);
2143
2144         qed_ptt_release(hwfn, ptt);
2145
2146         return rc;
2147 }
2148
2149 static struct qed_selftest_ops qed_selftest_ops_pass = {
2150         .selftest_memory = &qed_selftest_memory,
2151         .selftest_interrupt = &qed_selftest_interrupt,
2152         .selftest_register = &qed_selftest_register,
2153         .selftest_clock = &qed_selftest_clock,
2154         .selftest_nvram = &qed_selftest_nvram,
2155 };
2156
2157 const struct qed_common_ops qed_common_ops_pass = {
2158         .selftest = &qed_selftest_ops_pass,
2159         .probe = &qed_probe,
2160         .remove = &qed_remove,
2161         .set_power_state = &qed_set_power_state,
2162         .set_name = &qed_set_name,
2163         .update_pf_params = &qed_update_pf_params,
2164         .slowpath_start = &qed_slowpath_start,
2165         .slowpath_stop = &qed_slowpath_stop,
2166         .set_fp_int = &qed_set_int_fp,
2167         .get_fp_int = &qed_get_int_fp,
2168         .sb_init = &qed_sb_init,
2169         .sb_release = &qed_sb_release,
2170         .simd_handler_config = &qed_simd_handler_config,
2171         .simd_handler_clean = &qed_simd_handler_clean,
2172         .dbg_grc = &qed_dbg_grc,
2173         .dbg_grc_size = &qed_dbg_grc_size,
2174         .can_link_change = &qed_can_link_change,
2175         .set_link = &qed_set_link,
2176         .get_link = &qed_get_current_link,
2177         .drain = &qed_drain,
2178         .update_msglvl = &qed_init_dp,
2179         .dbg_all_data = &qed_dbg_all_data,
2180         .dbg_all_data_size = &qed_dbg_all_data_size,
2181         .chain_alloc = &qed_chain_alloc,
2182         .chain_free = &qed_chain_free,
2183         .nvm_flash = &qed_nvm_flash,
2184         .nvm_get_image = &qed_nvm_get_image,
2185         .set_coalesce = &qed_set_coalesce,
2186         .set_led = &qed_set_led,
2187         .update_drv_state = &qed_update_drv_state,
2188         .update_mac = &qed_update_mac,
2189         .update_mtu = &qed_update_mtu,
2190         .update_wol = &qed_update_wol,
2191         .read_module_eeprom = &qed_read_module_eeprom,
2192 };
2193
2194 void qed_get_protocol_stats(struct qed_dev *cdev,
2195                             enum qed_mcp_protocol_type type,
2196                             union qed_mcp_protocol_stats *stats)
2197 {
2198         struct qed_eth_stats eth_stats;
2199
2200         memset(stats, 0, sizeof(*stats));
2201
2202         switch (type) {
2203         case QED_MCP_LAN_STATS:
2204                 qed_get_vport_stats(cdev, &eth_stats);
2205                 stats->lan_stats.ucast_rx_pkts =
2206                                         eth_stats.common.rx_ucast_pkts;
2207                 stats->lan_stats.ucast_tx_pkts =
2208                                         eth_stats.common.tx_ucast_pkts;
2209                 stats->lan_stats.fcs_err = -1;
2210                 break;
2211         case QED_MCP_FCOE_STATS:
2212                 qed_get_protocol_stats_fcoe(cdev, &stats->fcoe_stats);
2213                 break;
2214         case QED_MCP_ISCSI_STATS:
2215                 qed_get_protocol_stats_iscsi(cdev, &stats->iscsi_stats);
2216                 break;
2217         default:
2218                 DP_VERBOSE(cdev, QED_MSG_SP,
2219                            "Invalid protocol type = %d\n", type);
2220                 return;
2221         }
2222 }
2223
2224 int qed_mfw_tlv_req(struct qed_hwfn *hwfn)
2225 {
2226         DP_VERBOSE(hwfn->cdev, NETIF_MSG_DRV,
2227                    "Scheduling slowpath task [Flag: %d]\n",
2228                    QED_SLOWPATH_MFW_TLV_REQ);
2229         smp_mb__before_atomic();
2230         set_bit(QED_SLOWPATH_MFW_TLV_REQ, &hwfn->slowpath_task_flags);
2231         smp_mb__after_atomic();
2232         queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, 0);
2233
2234         return 0;
2235 }
2236
2237 static void
2238 qed_fill_generic_tlv_data(struct qed_dev *cdev, struct qed_mfw_tlv_generic *tlv)
2239 {
2240         struct qed_common_cb_ops *op = cdev->protocol_ops.common;
2241         struct qed_eth_stats_common *p_common;
2242         struct qed_generic_tlvs gen_tlvs;
2243         struct qed_eth_stats stats;
2244         int i;
2245
2246         memset(&gen_tlvs, 0, sizeof(gen_tlvs));
2247         op->get_generic_tlv_data(cdev->ops_cookie, &gen_tlvs);
2248
2249         if (gen_tlvs.feat_flags & QED_TLV_IP_CSUM)
2250                 tlv->flags.ipv4_csum_offload = true;
2251         if (gen_tlvs.feat_flags & QED_TLV_LSO)
2252                 tlv->flags.lso_supported = true;
2253         tlv->flags.b_set = true;
2254
2255         for (i = 0; i < QED_TLV_MAC_COUNT; i++) {
2256                 if (is_valid_ether_addr(gen_tlvs.mac[i])) {
2257                         ether_addr_copy(tlv->mac[i], gen_tlvs.mac[i]);
2258                         tlv->mac_set[i] = true;
2259                 }
2260         }
2261
2262         qed_get_vport_stats(cdev, &stats);
2263         p_common = &stats.common;
2264         tlv->rx_frames = p_common->rx_ucast_pkts + p_common->rx_mcast_pkts +
2265                          p_common->rx_bcast_pkts;
2266         tlv->rx_frames_set = true;
2267         tlv->rx_bytes = p_common->rx_ucast_bytes + p_common->rx_mcast_bytes +
2268                         p_common->rx_bcast_bytes;
2269         tlv->rx_bytes_set = true;
2270         tlv->tx_frames = p_common->tx_ucast_pkts + p_common->tx_mcast_pkts +
2271                          p_common->tx_bcast_pkts;
2272         tlv->tx_frames_set = true;
2273         tlv->tx_bytes = p_common->tx_ucast_bytes + p_common->tx_mcast_bytes +
2274                         p_common->tx_bcast_bytes;
2275         tlv->rx_bytes_set = true;
2276 }
2277
2278 int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn, enum qed_mfw_tlv_type type,
2279                           union qed_mfw_tlv_data *tlv_buf)
2280 {
2281         struct qed_dev *cdev = hwfn->cdev;
2282         struct qed_common_cb_ops *ops;
2283
2284         ops = cdev->protocol_ops.common;
2285         if (!ops || !ops->get_protocol_tlv_data || !ops->get_generic_tlv_data) {
2286                 DP_NOTICE(hwfn, "Can't collect TLV management info\n");
2287                 return -EINVAL;
2288         }
2289
2290         switch (type) {
2291         case QED_MFW_TLV_GENERIC:
2292                 qed_fill_generic_tlv_data(hwfn->cdev, &tlv_buf->generic);
2293                 break;
2294         case QED_MFW_TLV_ETH:
2295                 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->eth);
2296                 break;
2297         case QED_MFW_TLV_FCOE:
2298                 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->fcoe);
2299                 break;
2300         case QED_MFW_TLV_ISCSI:
2301                 ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->iscsi);
2302                 break;
2303         default:
2304                 break;
2305         }
2306
2307         return 0;
2308 }