drivers/net/ethernet/qlogic/qed/qed_int.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #include <linux/types.h>
  10 #include <asm/byteorder.h>
  11 #include <linux/io.h>
  12 #include <linux/bitops.h>
  13 #include <linux/delay.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/errno.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/kernel.h>
  18 #include <linux/pci.h>
  19 #include <linux/slab.h>
  20 #include <linux/string.h>
  21 #include "qed.h"
  22 #include "qed_hsi.h"
  23 #include "qed_hw.h"
  24 #include "qed_init_ops.h"
  25 #include "qed_int.h"
  26 #include "qed_mcp.h"
  27 #include "qed_reg_addr.h"
  28 #include "qed_sp.h"
  29
  30 struct qed_pi_info {
  31         qed_int_comp_cb_t       comp_cb;
  32         void                    *cookie;
  33 };
  34
  35 struct qed_sb_sp_info {
  36         struct qed_sb_info      sb_info;
  37
  38         /* per protocol index data */
  39         struct qed_pi_info      pi_info_arr[PIS_PER_SB];
  40 };
  41
  42 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
  43         ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
  44
  45 #define ATTN_STATE_BITS (0xfff)
  46 #define ATTN_BITS_MASKABLE      (0x3ff)
  47 struct qed_sb_attn_info {
  48         /* Virtual & Physical address of the SB */
  49         struct atten_status_block       *sb_attn;
  50         dma_addr_t                    sb_phys;
  51
  52         /* Last seen running index */
  53         u16                          index;
  54
  55         /* Previously asserted attentions, which are still unasserted */
  56         u16                          known_attn;
  57
  58         /* Cleanup address for the link's general hw attention */
  59         u32                          mfw_attn_addr;
  60 };
  61
  62 static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn,
  63                                       struct qed_sb_attn_info   *p_sb_desc)
  64 {
  65         u16     rc = 0;
  66         u16     index;
  67
  68         /* Make certain HW write took affect */
  69         mmiowb();
  70
  71         index = le16_to_cpu(p_sb_desc->sb_attn->sb_index);
  72         if (p_sb_desc->index != index) {
  73                 p_sb_desc->index        = index;
  74                 rc                    = QED_SB_ATT_IDX;
  75         }
  76
  77         /* Make certain we got a consistent view with HW */
  78         mmiowb();
  79
  80         return rc;
  81 }
  82
  83 /**
  84  *  @brief qed_int_assertion - handles asserted attention bits
  85  *
  86  *  @param p_hwfn
  87  *  @param asserted_bits newly asserted bits
  88  *  @return int
  89  */
  90 static int qed_int_assertion(struct qed_hwfn *p_hwfn,
  91                              u16 asserted_bits)
  92 {
  93         struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
  94         u32 igu_mask;
  95
  96         /* Mask the source of the attention in the IGU */
  97         igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
  98                           IGU_REG_ATTENTION_ENABLE);
  99         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
 100                    igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
 101         igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
 102         qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
 103
 104         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
 105                    "inner known ATTN state: 0x%04x --> 0x%04x\n",
 106                    sb_attn_sw->known_attn,
 107                    sb_attn_sw->known_attn | asserted_bits);
 108         sb_attn_sw->known_attn |= asserted_bits;
 109
 110         /* Handle MCP events */
 111         if (asserted_bits & 0x100) {
 112                 qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
 113                 /* Clean the MCP attention */
 114                 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 115                        sb_attn_sw->mfw_attn_addr, 0);
 116         }
 117
 118         DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
 119                       GTT_BAR0_MAP_REG_IGU_CMD +
 120                       ((IGU_CMD_ATTN_BIT_SET_UPPER -
 121                         IGU_CMD_INT_ACK_BASE) << 3),
 122                       (u32)asserted_bits);
 123
 124         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n",
 125                    asserted_bits);
 126
 127         return 0;
 128 }
 129
 130 /**
 131  * @brief - handles deassertion of previously asserted attentions.
 132  *
 133  * @param p_hwfn
 134  * @param deasserted_bits - newly deasserted bits
 135  * @return int
 136  *
 137  */
 138 static int qed_int_deassertion(struct qed_hwfn  *p_hwfn,
 139                                u16 deasserted_bits)
 140 {
 141         struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
 142         u32 aeu_mask;
 143
 144         if (deasserted_bits != 0x100)
 145                 DP_ERR(p_hwfn, "Unexpected - non-link deassertion\n");
 146
 147         /* Clear IGU indication for the deasserted bits */
 148         DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
 149                       GTT_BAR0_MAP_REG_IGU_CMD +
 150                       ((IGU_CMD_ATTN_BIT_CLR_UPPER -
 151                         IGU_CMD_INT_ACK_BASE) << 3),
 152                       ~((u32)deasserted_bits));
 153
 154         /* Unmask deasserted attentions in IGU */
 155         aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 156                           IGU_REG_ATTENTION_ENABLE);
 157         aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
 158         qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
 159
 160         /* Clear deassertion from inner state */
 161         sb_attn_sw->known_attn &= ~deasserted_bits;
 162
 163         return 0;
 164 }
 165
 166 static int qed_int_attentions(struct qed_hwfn *p_hwfn)
 167 {
 168         struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
 169         struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
 170         u32 attn_bits = 0, attn_acks = 0;
 171         u16 asserted_bits, deasserted_bits;
 172         __le16 index;
 173         int rc = 0;
 174
 175         /* Read current attention bits/acks - safeguard against attentions
 176          * by guaranting work on a synchronized timeframe
 177          */
 178         do {
 179                 index = p_sb_attn->sb_index;
 180                 /* finish reading index before the loop condition */
 181                 dma_rmb();
 182                 attn_bits = le32_to_cpu(p_sb_attn->atten_bits);
 183                 attn_acks = le32_to_cpu(p_sb_attn->atten_ack);
 184         } while (index != p_sb_attn->sb_index);
 185         p_sb_attn->sb_index = index;
 186
 187         /* Attention / Deassertion are meaningful (and in correct state)
 188          * only when they differ and consistent with known state - deassertion
 189          * when previous attention & current ack, and assertion when current
 190          * attention with no previous attention
 191          */
 192         asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
 193                 ~p_sb_attn_sw->known_attn;
 194         deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
 195                 p_sb_attn_sw->known_attn;
 196
 197         if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) {
 198                 DP_INFO(p_hwfn,
 199                         "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
 200                         index, attn_bits, attn_acks, asserted_bits,
 201                         deasserted_bits, p_sb_attn_sw->known_attn);
 202         } else if (asserted_bits == 0x100) {
 203                 DP_INFO(p_hwfn,
 204                         "MFW indication via attention\n");
 205         } else {
 206                 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
 207                            "MFW indication [deassertion]\n");
 208         }
 209
 210         if (asserted_bits) {
 211                 rc = qed_int_assertion(p_hwfn, asserted_bits);
 212                 if (rc)
 213                         return rc;
 214         }
 215
 216         if (deasserted_bits) {
 217                 rc = qed_int_deassertion(p_hwfn, deasserted_bits);
 218                 if (rc)
 219                         return rc;
 220         }
 221
 222         return rc;
 223 }
 224
 225 static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn,
 226                             void __iomem *igu_addr,
 227                             u32 ack_cons)
 228 {
 229         struct igu_prod_cons_update igu_ack = { 0 };
 230
 231         igu_ack.sb_id_and_flags =
 232                 ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
 233                  (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
 234                  (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
 235                  (IGU_SEG_ACCESS_ATTN <<
 236                   IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
 237
 238         DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags);
 239
 240         /* Both segments (interrupts & acks) are written to same place address;
 241          * Need to guarantee all commands will be received (in-order) by HW.
 242          */
 243         mmiowb();
 244         barrier();
 245 }
 246
 247 void qed_int_sp_dpc(unsigned long hwfn_cookie)
 248 {
 249         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie;
 250         struct qed_pi_info *pi_info = NULL;
 251         struct qed_sb_attn_info *sb_attn;
 252         struct qed_sb_info *sb_info;
 253         int arr_size;
 254         u16 rc = 0;
 255
 256         if (!p_hwfn->p_sp_sb) {
 257                 DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n");
 258                 return;
 259         }
 260
 261         sb_info = &p_hwfn->p_sp_sb->sb_info;
 262         arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
 263         if (!sb_info) {
 264                 DP_ERR(p_hwfn->cdev,
 265                        "Status block is NULL - cannot ack interrupts\n");
 266                 return;
 267         }
 268
 269         if (!p_hwfn->p_sb_attn) {
 270                 DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn");
 271                 return;
 272         }
 273         sb_attn = p_hwfn->p_sb_attn;
 274
 275         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
 276                    p_hwfn, p_hwfn->my_id);
 277
 278         /* Disable ack for def status block. Required both for msix +
 279          * inta in non-mask mode, in inta does no harm.
 280          */
 281         qed_sb_ack(sb_info, IGU_INT_DISABLE, 0);
 282
 283         /* Gather Interrupts/Attentions information */
 284         if (!sb_info->sb_virt) {
 285                 DP_ERR(
 286                         p_hwfn->cdev,
 287                         "Interrupt Status block is NULL - cannot check for new interrupts!\n");
 288         } else {
 289                 u32 tmp_index = sb_info->sb_ack;
 290
 291                 rc = qed_sb_update_sb_idx(sb_info);
 292                 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
 293                            "Interrupt indices: 0x%08x --> 0x%08x\n",
 294                            tmp_index, sb_info->sb_ack);
 295         }
 296
 297         if (!sb_attn || !sb_attn->sb_attn) {
 298                 DP_ERR(
 299                         p_hwfn->cdev,
 300                         "Attentions Status block is NULL - cannot check for new attentions!\n");
 301         } else {
 302                 u16 tmp_index = sb_attn->index;
 303
 304                 rc |= qed_attn_update_idx(p_hwfn, sb_attn);
 305                 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
 306                            "Attention indices: 0x%08x --> 0x%08x\n",
 307                            tmp_index, sb_attn->index);
 308         }
 309
 310         /* Check if we expect interrupts at this time. if not just ack them */
 311         if (!(rc & QED_SB_EVENT_MASK)) {
 312                 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
 313                 return;
 314         }
 315
 316         /* Check the validity of the DPC ptt. If not ack interrupts and fail */
 317         if (!p_hwfn->p_dpc_ptt) {
 318                 DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n");
 319                 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
 320                 return;
 321         }
 322
 323         if (rc & QED_SB_ATT_IDX)
 324                 qed_int_attentions(p_hwfn);
 325
 326         if (rc & QED_SB_IDX) {
 327                 int pi;
 328
 329                 /* Look for a free index */
 330                 for (pi = 0; pi < arr_size; pi++) {
 331                         pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
 332                         if (pi_info->comp_cb)
 333                                 pi_info->comp_cb(p_hwfn, pi_info->cookie);
 334                 }
 335         }
 336
 337         if (sb_attn && (rc & QED_SB_ATT_IDX))
 338                 /* This should be done before the interrupts are enabled,
 339                  * since otherwise a new attention will be generated.
 340                  */
 341                 qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
 342
 343         qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
 344 }
 345
 346 static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn)
 347 {
 348         struct qed_dev *cdev   = p_hwfn->cdev;
 349         struct qed_sb_attn_info *p_sb   = p_hwfn->p_sb_attn;
 350
 351         if (p_sb) {
 352                 if (p_sb->sb_attn)
 353                         dma_free_coherent(&cdev->pdev->dev,
 354                                           SB_ATTN_ALIGNED_SIZE(p_hwfn),
 355                                           p_sb->sb_attn,
 356                                           p_sb->sb_phys);
 357                 kfree(p_sb);
 358         }
 359 }
 360
 361 static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn,
 362                                   struct qed_ptt *p_ptt)
 363 {
 364         struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
 365
 366         memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
 367
 368         sb_info->index = 0;
 369         sb_info->known_attn = 0;
 370
 371         /* Configure Attention Status Block in IGU */
 372         qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
 373                lower_32_bits(p_hwfn->p_sb_attn->sb_phys));
 374         qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
 375                upper_32_bits(p_hwfn->p_sb_attn->sb_phys));
 376 }
 377
 378 static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn,
 379                                  struct qed_ptt *p_ptt,
 380                                  void *sb_virt_addr,
 381                                  dma_addr_t sb_phy_addr)
 382 {
 383         struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
 384
 385         sb_info->sb_attn = sb_virt_addr;
 386         sb_info->sb_phys = sb_phy_addr;
 387
 388         /* Set the address of cleanup for the mcp attention */
 389         sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
 390                                  MISC_REG_AEU_GENERAL_ATTN_0;
 391
 392         qed_int_sb_attn_setup(p_hwfn, p_ptt);
 393 }
 394
 395 static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn,
 396                                  struct qed_ptt *p_ptt)
 397 {
 398         struct qed_dev *cdev = p_hwfn->cdev;
 399         struct qed_sb_attn_info *p_sb;
 400         void *p_virt;
 401         dma_addr_t p_phys = 0;
 402
 403         /* SB struct */
 404         p_sb = kmalloc(sizeof(*p_sb), GFP_ATOMIC);
 405         if (!p_sb) {
 406                 DP_NOTICE(cdev, "Failed to allocate `struct qed_sb_attn_info'\n");
 407                 return -ENOMEM;
 408         }
 409
 410         /* SB ring  */
 411         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
 412                                     SB_ATTN_ALIGNED_SIZE(p_hwfn),
 413                                     &p_phys, GFP_KERNEL);
 414
 415         if (!p_virt) {
 416                 DP_NOTICE(cdev, "Failed to allocate status block (attentions)\n");
 417                 kfree(p_sb);
 418                 return -ENOMEM;
 419         }
 420
 421         /* Attention setup */
 422         p_hwfn->p_sb_attn = p_sb;
 423         qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
 424
 425         return 0;
 426 }
 427
 428 /* coalescing timeout = timeset << (timer_res + 1) */
 429 #define QED_CAU_DEF_RX_USECS 24
 430 #define QED_CAU_DEF_TX_USECS 48
 431
 432 void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
 433                            struct cau_sb_entry *p_sb_entry,
 434                            u8 pf_id,
 435                            u16 vf_number,
 436                            u8 vf_valid)
 437 {
 438         u32 cau_state;
 439
 440         memset(p_sb_entry, 0, sizeof(*p_sb_entry));
 441
 442         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
 443         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
 444         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
 445         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
 446         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
 447
 448         /* setting the time resultion to a fixed value ( = 1) */
 449         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0,
 450                   QED_CAU_DEF_RX_TIMER_RES);
 451         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1,
 452                   QED_CAU_DEF_TX_TIMER_RES);
 453
 454         cau_state = CAU_HC_DISABLE_STATE;
 455
 456         if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
 457                 cau_state = CAU_HC_ENABLE_STATE;
 458                 if (!p_hwfn->cdev->rx_coalesce_usecs)
 459                         p_hwfn->cdev->rx_coalesce_usecs =
 460                                 QED_CAU_DEF_RX_USECS;
 461                 if (!p_hwfn->cdev->tx_coalesce_usecs)
 462                         p_hwfn->cdev->tx_coalesce_usecs =
 463                                 QED_CAU_DEF_TX_USECS;
 464         }
 465
 466         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
 467         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
 468 }
 469
 470 void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
 471                          struct qed_ptt *p_ptt,
 472                          dma_addr_t sb_phys,
 473                          u16 igu_sb_id,
 474                          u16 vf_number,
 475                          u8 vf_valid)
 476 {
 477         struct cau_sb_entry sb_entry;
 478         u32 val;
 479
 480         qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
 481                               vf_number, vf_valid);
 482
 483         if (p_hwfn->hw_init_done) {
 484                 val = CAU_REG_SB_ADDR_MEMORY + igu_sb_id * sizeof(u64);
 485                 qed_wr(p_hwfn, p_ptt, val, lower_32_bits(sb_phys));
 486                 qed_wr(p_hwfn, p_ptt, val + sizeof(u32),
 487                        upper_32_bits(sb_phys));
 488
 489                 val = CAU_REG_SB_VAR_MEMORY + igu_sb_id * sizeof(u64);
 490                 qed_wr(p_hwfn, p_ptt, val, sb_entry.data);
 491                 qed_wr(p_hwfn, p_ptt, val + sizeof(u32), sb_entry.params);
 492         } else {
 493                 /* Initialize Status Block Address */
 494                 STORE_RT_REG_AGG(p_hwfn,
 495                                  CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
 496                                  igu_sb_id * 2,
 497                                  sb_phys);
 498
 499                 STORE_RT_REG_AGG(p_hwfn,
 500                                  CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
 501                                  igu_sb_id * 2,
 502                                  sb_entry);
 503         }
 504
 505         /* Configure pi coalescing if set */
 506         if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
 507                 u8 timeset = p_hwfn->cdev->rx_coalesce_usecs >>
 508                              (QED_CAU_DEF_RX_TIMER_RES + 1);
 509                 u8 num_tc = 1, i;
 510
 511                 qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
 512                                     QED_COAL_RX_STATE_MACHINE,
 513                                     timeset);
 514
 515                 timeset = p_hwfn->cdev->tx_coalesce_usecs >>
 516                           (QED_CAU_DEF_TX_TIMER_RES + 1);
 517
 518                 for (i = 0; i < num_tc; i++) {
 519                         qed_int_cau_conf_pi(p_hwfn, p_ptt,
 520                                             igu_sb_id, TX_PI(i),
 521                                             QED_COAL_TX_STATE_MACHINE,
 522                                             timeset);
 523                 }
 524         }
 525 }
 526
 527 void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
 528                          struct qed_ptt *p_ptt,
 529                          u16 igu_sb_id,
 530                          u32 pi_index,
 531                          enum qed_coalescing_fsm coalescing_fsm,
 532                          u8 timeset)
 533 {
 534         struct cau_pi_entry pi_entry;
 535         u32 sb_offset;
 536         u32 pi_offset;
 537
 538         sb_offset = igu_sb_id * PIS_PER_SB;
 539         memset(&pi_entry, 0, sizeof(struct cau_pi_entry));
 540
 541         SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
 542         if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE)
 543                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
 544         else
 545                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
 546
 547         pi_offset = sb_offset + pi_index;
 548         if (p_hwfn->hw_init_done) {
 549                 qed_wr(p_hwfn, p_ptt,
 550                        CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
 551                        *((u32 *)&(pi_entry)));
 552         } else {
 553                 STORE_RT_REG(p_hwfn,
 554                              CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
 555                              *((u32 *)&(pi_entry)));
 556         }
 557 }
 558
 559 void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
 560                       struct qed_ptt *p_ptt,
 561                       struct qed_sb_info *sb_info)
 562 {
 563         /* zero status block and ack counter */
 564         sb_info->sb_ack = 0;
 565         memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
 566
 567         qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
 568                             sb_info->igu_sb_id, 0, 0);
 569 }
 570
 571 /**
 572  * @brief qed_get_igu_sb_id - given a sw sb_id return the
 573  *        igu_sb_id
 574  *
 575  * @param p_hwfn
 576  * @param sb_id
 577  *
 578  * @return u16
 579  */
 580 static u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn,
 581                              u16 sb_id)
 582 {
 583         u16 igu_sb_id;
 584
 585         /* Assuming continuous set of IGU SBs dedicated for given PF */
 586         if (sb_id == QED_SP_SB_ID)
 587                 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
 588         else
 589                 igu_sb_id = sb_id + p_hwfn->hw_info.p_igu_info->igu_base_sb;
 590
 591         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "SB [%s] index is 0x%04x\n",
 592                    (sb_id == QED_SP_SB_ID) ? "DSB" : "non-DSB", igu_sb_id);
 593
 594         return igu_sb_id;
 595 }
 596
 597 int qed_int_sb_init(struct qed_hwfn *p_hwfn,
 598                     struct qed_ptt *p_ptt,
 599                     struct qed_sb_info *sb_info,
 600                     void *sb_virt_addr,
 601                     dma_addr_t sb_phy_addr,
 602                     u16 sb_id)
 603 {
 604         sb_info->sb_virt = sb_virt_addr;
 605         sb_info->sb_phys = sb_phy_addr;
 606
 607         sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id);
 608
 609         if (sb_id != QED_SP_SB_ID) {
 610                 p_hwfn->sbs_info[sb_id] = sb_info;
 611                 p_hwfn->num_sbs++;
 612         }
 613
 614         sb_info->cdev = p_hwfn->cdev;
 615
 616         /* The igu address will hold the absolute address that needs to be
 617          * written to for a specific status block
 618          */
 619         sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview +
 620                                           GTT_BAR0_MAP_REG_IGU_CMD +
 621                                           (sb_info->igu_sb_id << 3);
 622
 623         sb_info->flags |= QED_SB_INFO_INIT;
 624
 625         qed_int_sb_setup(p_hwfn, p_ptt, sb_info);
 626
 627         return 0;
 628 }
 629
 630 int qed_int_sb_release(struct qed_hwfn *p_hwfn,
 631                        struct qed_sb_info *sb_info,
 632                        u16 sb_id)
 633 {
 634         if (sb_id == QED_SP_SB_ID) {
 635                 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
 636                 return -EINVAL;
 637         }
 638
 639         /* zero status block and ack counter */
 640         sb_info->sb_ack = 0;
 641         memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
 642
 643         p_hwfn->sbs_info[sb_id] = NULL;
 644         p_hwfn->num_sbs--;
 645
 646         return 0;
 647 }
 648
 649 static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn)
 650 {
 651         struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
 652
 653         if (p_sb) {
 654                 if (p_sb->sb_info.sb_virt)
 655                         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
 656                                           SB_ALIGNED_SIZE(p_hwfn),
 657                                           p_sb->sb_info.sb_virt,
 658                                           p_sb->sb_info.sb_phys);
 659                 kfree(p_sb);
 660         }
 661 }
 662
 663 static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn,
 664                                struct qed_ptt *p_ptt)
 665 {
 666         struct qed_sb_sp_info *p_sb;
 667         dma_addr_t p_phys = 0;
 668         void *p_virt;
 669
 670         /* SB struct */
 671         p_sb = kmalloc(sizeof(*p_sb), GFP_ATOMIC);
 672         if (!p_sb) {
 673                 DP_NOTICE(p_hwfn, "Failed to allocate `struct qed_sb_info'\n");
 674                 return -ENOMEM;
 675         }
 676
 677         /* SB ring  */
 678         p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 679                                     SB_ALIGNED_SIZE(p_hwfn),
 680                                     &p_phys, GFP_KERNEL);
 681         if (!p_virt) {
 682                 DP_NOTICE(p_hwfn, "Failed to allocate status block\n");
 683                 kfree(p_sb);
 684                 return -ENOMEM;
 685         }
 686
 687         /* Status Block setup */
 688         p_hwfn->p_sp_sb = p_sb;
 689         qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt,
 690                         p_phys, QED_SP_SB_ID);
 691
 692         memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
 693
 694         return 0;
 695 }
 696
 697 static void qed_int_sp_sb_setup(struct qed_hwfn *p_hwfn,
 698                                 struct qed_ptt *p_ptt)
 699 {
 700         if (!p_hwfn)
 701                 return;
 702
 703         if (p_hwfn->p_sp_sb)
 704                 qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
 705         else
 706                 DP_NOTICE(p_hwfn->cdev,
 707                           "Failed to setup Slow path status block - NULL pointer\n");
 708
 709         if (p_hwfn->p_sb_attn)
 710                 qed_int_sb_attn_setup(p_hwfn, p_ptt);
 711         else
 712                 DP_NOTICE(p_hwfn->cdev,
 713                           "Failed to setup attentions status block - NULL pointer\n");
 714 }
 715
 716 int qed_int_register_cb(struct qed_hwfn *p_hwfn,
 717                         qed_int_comp_cb_t comp_cb,
 718                         void *cookie,
 719                         u8 *sb_idx,
 720                         __le16 **p_fw_cons)
 721 {
 722         struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
 723         int qed_status = -ENOMEM;
 724         u8 pi;
 725
 726         /* Look for a free index */
 727         for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
 728                 if (!p_sp_sb->pi_info_arr[pi].comp_cb) {
 729                         p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
 730                         p_sp_sb->pi_info_arr[pi].cookie = cookie;
 731                         *sb_idx = pi;
 732                         *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
 733                         qed_status = 0;
 734                         break;
 735                 }
 736         }
 737
 738         return qed_status;
 739 }
 740
 741 int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi)
 742 {
 743         struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
 744         int qed_status = -ENOMEM;
 745
 746         if (p_sp_sb->pi_info_arr[pi].comp_cb) {
 747                 p_sp_sb->pi_info_arr[pi].comp_cb = NULL;
 748                 p_sp_sb->pi_info_arr[pi].cookie = NULL;
 749                 qed_status = 0;
 750         }
 751
 752         return qed_status;
 753 }
 754
 755 u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn)
 756 {
 757         return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
 758 }
 759
 760 void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
 761                             struct qed_ptt *p_ptt,
 762                             enum qed_int_mode int_mode)
 763 {
 764         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
 765
 766         p_hwfn->cdev->int_mode = int_mode;
 767         switch (p_hwfn->cdev->int_mode) {
 768         case QED_INT_MODE_INTA:
 769                 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
 770                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
 771                 break;
 772
 773         case QED_INT_MODE_MSI:
 774                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
 775                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
 776                 break;
 777
 778         case QED_INT_MODE_MSIX:
 779                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
 780                 break;
 781         case QED_INT_MODE_POLL:
 782                 break;
 783         }
 784
 785         qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
 786 }
 787
 788 int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
 789                        enum qed_int_mode int_mode)
 790 {
 791         int rc, i;
 792
 793         /* Mask non-link attentions */
 794         for (i = 0; i < 9; i++)
 795                 qed_wr(p_hwfn, p_ptt,
 796                        MISC_REG_AEU_ENABLE1_IGU_OUT_0 + (i << 2), 0);
 797
 798         /* Configure AEU signal change to produce attentions for link */
 799         qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
 800         qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
 801
 802         /* Flush the writes to IGU */
 803         mmiowb();
 804
 805         /* Unmask AEU signals toward IGU */
 806         qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
 807         if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
 808                 rc = qed_slowpath_irq_req(p_hwfn);
 809                 if (rc != 0) {
 810                         DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n");
 811                         return -EINVAL;
 812                 }
 813                 p_hwfn->b_int_requested = true;
 814         }
 815         /* Enable interrupt Generation */
 816         qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
 817         p_hwfn->b_int_enabled = 1;
 818
 819         return rc;
 820 }
 821
 822 void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,
 823                              struct qed_ptt *p_ptt)
 824 {
 825         p_hwfn->b_int_enabled = 0;
 826
 827         qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
 828 }
 829
 830 #define IGU_CLEANUP_SLEEP_LENGTH                (1000)
 831 void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,
 832                             struct qed_ptt *p_ptt,
 833                             u32 sb_id,
 834                             bool cleanup_set,
 835                             u16 opaque_fid
 836                             )
 837 {
 838         u32 pxp_addr = IGU_CMD_INT_ACK_BASE + sb_id;
 839         u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
 840         u32 data = 0;
 841         u32 cmd_ctrl = 0;
 842         u32 val = 0;
 843         u32 sb_bit = 0;
 844         u32 sb_bit_addr = 0;
 845
 846         /* Set the data field */
 847         SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
 848         SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0);
 849         SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
 850
 851         /* Set the control register */
 852         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
 853         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
 854         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
 855
 856         qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
 857
 858         barrier();
 859
 860         qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
 861
 862         /* Flush the write to IGU */
 863         mmiowb();
 864
 865         /* calculate where to read the status bit from */
 866         sb_bit = 1 << (sb_id % 32);
 867         sb_bit_addr = sb_id / 32 * sizeof(u32);
 868
 869         sb_bit_addr += IGU_REG_CLEANUP_STATUS_0;
 870
 871         /* Now wait for the command to complete */
 872         do {
 873                 val = qed_rd(p_hwfn, p_ptt, sb_bit_addr);
 874
 875                 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
 876                         break;
 877
 878                 usleep_range(5000, 10000);
 879         } while (--sleep_cnt);
 880
 881         if (!sleep_cnt)
 882                 DP_NOTICE(p_hwfn,
 883                           "Timeout waiting for clear status 0x%08x [for sb %d]\n",
 884                           val, sb_id);
 885 }
 886
 887 void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
 888                                      struct qed_ptt *p_ptt,
 889                                      u32 sb_id,
 890                                      u16 opaque,
 891                                      bool b_set)
 892 {
 893         int pi;
 894
 895         /* Set */
 896         if (b_set)
 897                 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 1, opaque);
 898
 899         /* Clear */
 900         qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 0, opaque);
 901
 902         /* Clear the CAU for the SB */
 903         for (pi = 0; pi < 12; pi++)
 904                 qed_wr(p_hwfn, p_ptt,
 905                        CAU_REG_PI_MEMORY + (sb_id * 12 + pi) * 4, 0);
 906 }
 907
 908 void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
 909                               struct qed_ptt *p_ptt,
 910                               bool b_set,
 911                               bool b_slowpath)
 912 {
 913         u32 igu_base_sb = p_hwfn->hw_info.p_igu_info->igu_base_sb;
 914         u32 igu_sb_cnt = p_hwfn->hw_info.p_igu_info->igu_sb_cnt;
 915         u32 sb_id = 0;
 916         u32 val = 0;
 917
 918         val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
 919         val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
 920         val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
 921         qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
 922
 923         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
 924                    "IGU cleaning SBs [%d,...,%d]\n",
 925                    igu_base_sb, igu_base_sb + igu_sb_cnt - 1);
 926
 927         for (sb_id = igu_base_sb; sb_id < igu_base_sb + igu_sb_cnt; sb_id++)
 928                 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
 929                                                 p_hwfn->hw_info.opaque_fid,
 930                                                 b_set);
 931
 932         if (b_slowpath) {
 933                 sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
 934                 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
 935                            "IGU cleaning slowpath SB [%d]\n", sb_id);
 936                 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
 937                                                 p_hwfn->hw_info.opaque_fid,
 938                                                 b_set);
 939         }
 940 }
 941
 942 int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
 943                          struct qed_ptt *p_ptt)
 944 {
 945         struct qed_igu_info *p_igu_info;
 946         struct qed_igu_block *blk;
 947         u32 val;
 948         u16 sb_id;
 949         u16 prev_sb_id = 0xFF;
 950
 951         p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_ATOMIC);
 952
 953         if (!p_hwfn->hw_info.p_igu_info)
 954                 return -ENOMEM;
 955
 956         p_igu_info = p_hwfn->hw_info.p_igu_info;
 957
 958         /* Initialize base sb / sb cnt for PFs */
 959         p_igu_info->igu_base_sb         = 0xffff;
 960         p_igu_info->igu_sb_cnt          = 0;
 961         p_igu_info->igu_dsb_id          = 0xffff;
 962         p_igu_info->igu_base_sb_iov     = 0xffff;
 963
 964         for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
 965              sb_id++) {
 966                 blk = &p_igu_info->igu_map.igu_blocks[sb_id];
 967
 968                 val = qed_rd(p_hwfn, p_ptt,
 969                              IGU_REG_MAPPING_MEMORY + sizeof(u32) * sb_id);
 970
 971                 /* stop scanning when hit first invalid PF entry */
 972                 if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) &&
 973                     GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID))
 974                         break;
 975
 976                 blk->status = QED_IGU_STATUS_VALID;
 977                 blk->function_id = GET_FIELD(val,
 978                                              IGU_MAPPING_LINE_FUNCTION_NUMBER);
 979                 blk->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
 980                 blk->vector_number = GET_FIELD(val,
 981                                                IGU_MAPPING_LINE_VECTOR_NUMBER);
 982
 983                 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
 984                            "IGU_BLOCK[sb_id]:%x:func_id = %d is_pf = %d vector_num = 0x%x\n",
 985                            val, blk->function_id, blk->is_pf,
 986                            blk->vector_number);
 987
 988                 if (blk->is_pf) {
 989                         if (blk->function_id == p_hwfn->rel_pf_id) {
 990                                 blk->status |= QED_IGU_STATUS_PF;
 991
 992                                 if (blk->vector_number == 0) {
 993                                         if (p_igu_info->igu_dsb_id == 0xffff)
 994                                                 p_igu_info->igu_dsb_id = sb_id;
 995                                 } else {
 996                                         if (p_igu_info->igu_base_sb ==
 997                                             0xffff) {
 998                                                 p_igu_info->igu_base_sb = sb_id;
 999                                         } else if (prev_sb_id != sb_id - 1) {
1000                                                 DP_NOTICE(p_hwfn->cdev,
1001                                                           "consecutive igu vectors for HWFN %x broken",
1002                                                           p_hwfn->rel_pf_id);
1003                                                 break;
1004                                         }
1005                                         prev_sb_id = sb_id;
1006                                         /* we don't count the default */
1007                                         (p_igu_info->igu_sb_cnt)++;
1008                                 }
1009                         }
1010                 }
1011         }
1012
1013         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1014                    "IGU igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n",
1015                    p_igu_info->igu_base_sb,
1016                    p_igu_info->igu_sb_cnt,
1017                    p_igu_info->igu_dsb_id);
1018
1019         if (p_igu_info->igu_base_sb == 0xffff ||
1020             p_igu_info->igu_dsb_id == 0xffff ||
1021             p_igu_info->igu_sb_cnt == 0) {
1022                 DP_NOTICE(p_hwfn,
1023                           "IGU CAM returned invalid values igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n",
1024                            p_igu_info->igu_base_sb,
1025                            p_igu_info->igu_sb_cnt,
1026                            p_igu_info->igu_dsb_id);
1027                 return -EINVAL;
1028         }
1029
1030         return 0;
1031 }
1032
1033 /**
1034  * @brief Initialize igu runtime registers
1035  *
1036  * @param p_hwfn
1037  */
1038 void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn)
1039 {
1040         u32 igu_pf_conf = 0;
1041
1042         igu_pf_conf |= IGU_PF_CONF_FUNC_EN;
1043
1044         STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
1045 }
1046
1047 u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn)
1048 {
1049         u64 intr_status = 0;
1050         u32 intr_status_lo = 0;
1051         u32 intr_status_hi = 0;
1052         u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER -
1053                                IGU_CMD_INT_ACK_BASE;
1054         u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER -
1055                                IGU_CMD_INT_ACK_BASE;
1056
1057         intr_status_lo = REG_RD(p_hwfn,
1058                                 GTT_BAR0_MAP_REG_IGU_CMD +
1059                                 lsb_igu_cmd_addr * 8);
1060         intr_status_hi = REG_RD(p_hwfn,
1061                                 GTT_BAR0_MAP_REG_IGU_CMD +
1062                                 msb_igu_cmd_addr * 8);
1063         intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
1064
1065         return intr_status;
1066 }
1067
1068 static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn)
1069 {
1070         tasklet_init(p_hwfn->sp_dpc,
1071                      qed_int_sp_dpc, (unsigned long)p_hwfn);
1072         p_hwfn->b_sp_dpc_enabled = true;
1073 }
1074
1075 static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn)
1076 {
1077         p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_ATOMIC);
1078         if (!p_hwfn->sp_dpc)
1079                 return -ENOMEM;
1080
1081         return 0;
1082 }
1083
1084 static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn)
1085 {
1086         kfree(p_hwfn->sp_dpc);
1087 }
1088
1089 int qed_int_alloc(struct qed_hwfn *p_hwfn,
1090                   struct qed_ptt *p_ptt)
1091 {
1092         int rc = 0;
1093
1094         rc = qed_int_sp_dpc_alloc(p_hwfn);
1095         if (rc) {
1096                 DP_ERR(p_hwfn->cdev, "Failed to allocate sp dpc mem\n");
1097                 return rc;
1098         }
1099         rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt);
1100         if (rc) {
1101                 DP_ERR(p_hwfn->cdev, "Failed to allocate sp sb mem\n");
1102                 return rc;
1103         }
1104         rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt);
1105         if (rc) {
1106                 DP_ERR(p_hwfn->cdev, "Failed to allocate sb attn mem\n");
1107                 return rc;
1108         }
1109         return rc;
1110 }
1111
1112 void qed_int_free(struct qed_hwfn *p_hwfn)
1113 {
1114         qed_int_sp_sb_free(p_hwfn);
1115         qed_int_sb_attn_free(p_hwfn);
1116         qed_int_sp_dpc_free(p_hwfn);
1117 }
1118
1119 void qed_int_setup(struct qed_hwfn *p_hwfn,
1120                    struct qed_ptt *p_ptt)
1121 {
1122         qed_int_sp_sb_setup(p_hwfn, p_ptt);
1123         qed_int_sp_dpc_setup(p_hwfn);
1124 }
1125
1126 int qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
1127                         int *p_iov_blks)
1128 {
1129         struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info;
1130
1131         if (!info)
1132                 return 0;
1133
1134         if (p_iov_blks)
1135                 *p_iov_blks = info->free_blks;
1136
1137         return info->igu_sb_cnt;
1138 }
1139
1140 void qed_int_disable_post_isr_release(struct qed_dev *cdev)
1141 {
1142         int i;
1143
1144         for_each_hwfn(cdev, i)
1145                 cdev->hwfns[i].b_int_requested = false;
1146 }