drivers/net/ethernet/qlogic/qed/qed_int.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/io.h>
  36 #include <linux/bitops.h>
  37 #include <linux/delay.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/errno.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/kernel.h>
  42 #include <linux/pci.h>
  43 #include <linux/slab.h>
  44 #include <linux/string.h>
  45 #include "qed.h"
  46 #include "qed_hsi.h"
  47 #include "qed_hw.h"
  48 #include "qed_init_ops.h"
  49 #include "qed_int.h"
  50 #include "qed_mcp.h"
  51 #include "qed_reg_addr.h"
  52 #include "qed_sp.h"
  53 #include "qed_sriov.h"
  54 #include "qed_vf.h"
  55
  56 struct qed_pi_info {
  57         qed_int_comp_cb_t       comp_cb;
  58         void                    *cookie;
  59 };
  60
  61 struct qed_sb_sp_info {
  62         struct qed_sb_info sb_info;
  63
  64         /* per protocol index data */
  65         struct qed_pi_info pi_info_arr[PIS_PER_SB_E4];
  66 };
  67
  68 enum qed_attention_type {
  69         QED_ATTN_TYPE_ATTN,
  70         QED_ATTN_TYPE_PARITY,
  71 };
  72
  73 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
  74         ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
  75
  76 struct aeu_invert_reg_bit {
  77         char bit_name[30];
  78
  79 #define ATTENTION_PARITY                (1 << 0)
  80
  81 #define ATTENTION_LENGTH_MASK           (0x00000ff0)
  82 #define ATTENTION_LENGTH_SHIFT          (4)
  83 #define ATTENTION_LENGTH(flags)         (((flags) & ATTENTION_LENGTH_MASK) >> \
  84                                          ATTENTION_LENGTH_SHIFT)
  85 #define ATTENTION_SINGLE                BIT(ATTENTION_LENGTH_SHIFT)
  86 #define ATTENTION_PAR                   (ATTENTION_SINGLE | ATTENTION_PARITY)
  87 #define ATTENTION_PAR_INT               ((2 << ATTENTION_LENGTH_SHIFT) | \
  88                                          ATTENTION_PARITY)
  89
  90 /* Multiple bits start with this offset */
  91 #define ATTENTION_OFFSET_MASK           (0x000ff000)
  92 #define ATTENTION_OFFSET_SHIFT          (12)
  93
  94 #define ATTENTION_BB_MASK               (0x00700000)
  95 #define ATTENTION_BB_SHIFT              (20)
  96 #define ATTENTION_BB(value)             (value << ATTENTION_BB_SHIFT)
  97 #define ATTENTION_BB_DIFFERENT          BIT(23)
  98
  99         unsigned int flags;
 100
 101         /* Callback to call if attention will be triggered */
 102         int (*cb)(struct qed_hwfn *p_hwfn);
 103
 104         enum block_id block_index;
 105 };
 106
 107 struct aeu_invert_reg {
 108         struct aeu_invert_reg_bit bits[32];
 109 };
 110
 111 #define MAX_ATTN_GRPS           (8)
 112 #define NUM_ATTN_REGS           (9)
 113
 114 /* Specific HW attention callbacks */
 115 static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn)
 116 {
 117         u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
 118
 119         /* This might occur on certain instances; Log it once then mask it */
 120         DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n",
 121                 tmp);
 122         qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK,
 123                0xffffffff);
 124
 125         return 0;
 126 }
 127
 128 #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS           (0x1)
 129 #define ATTENTION_INCORRECT_ACCESS_WR_MASK              (0x1)
 130 #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT             (0)
 131 #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK          (0xf)
 132 #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT         (1)
 133 #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK        (0x1)
 134 #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT       (5)
 135 #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK           (0xff)
 136 #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT          (6)
 137 #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK           (0xf)
 138 #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT          (14)
 139 #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK         (0xff)
 140 #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT        (18)
 141 static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn)
 142 {
 143         u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 144                          PSWHST_REG_INCORRECT_ACCESS_VALID);
 145
 146         if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) {
 147                 u32 addr, data, length;
 148
 149                 addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 150                               PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
 151                 data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 152                               PSWHST_REG_INCORRECT_ACCESS_DATA);
 153                 length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 154                                 PSWHST_REG_INCORRECT_ACCESS_LENGTH);
 155
 156                 DP_INFO(p_hwfn->cdev,
 157                         "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n",
 158                         addr, length,
 159                         (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID),
 160                         (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID),
 161                         (u8) GET_FIELD(data,
 162                                        ATTENTION_INCORRECT_ACCESS_VF_VALID),
 163                         (u8) GET_FIELD(data,
 164                                        ATTENTION_INCORRECT_ACCESS_CLIENT),
 165                         (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR),
 166                         (u8) GET_FIELD(data,
 167                                        ATTENTION_INCORRECT_ACCESS_BYTE_EN),
 168                         data);
 169         }
 170
 171         return 0;
 172 }
 173
 174 #define QED_GRC_ATTENTION_VALID_BIT     (1 << 0)
 175 #define QED_GRC_ATTENTION_ADDRESS_MASK  (0x7fffff)
 176 #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0)
 177 #define QED_GRC_ATTENTION_RDWR_BIT      (1 << 23)
 178 #define QED_GRC_ATTENTION_MASTER_MASK   (0xf)
 179 #define QED_GRC_ATTENTION_MASTER_SHIFT  (24)
 180 #define QED_GRC_ATTENTION_PF_MASK       (0xf)
 181 #define QED_GRC_ATTENTION_PF_SHIFT      (0)
 182 #define QED_GRC_ATTENTION_VF_MASK       (0xff)
 183 #define QED_GRC_ATTENTION_VF_SHIFT      (4)
 184 #define QED_GRC_ATTENTION_PRIV_MASK     (0x3)
 185 #define QED_GRC_ATTENTION_PRIV_SHIFT    (14)
 186 #define QED_GRC_ATTENTION_PRIV_VF       (0)
 187 static const char *attn_master_to_str(u8 master)
 188 {
 189         switch (master) {
 190         case 1: return "PXP";
 191         case 2: return "MCP";
 192         case 3: return "MSDM";
 193         case 4: return "PSDM";
 194         case 5: return "YSDM";
 195         case 6: return "USDM";
 196         case 7: return "TSDM";
 197         case 8: return "XSDM";
 198         case 9: return "DBU";
 199         case 10: return "DMAE";
 200         default:
 201                 return "Unknown";
 202         }
 203 }
 204
 205 static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn)
 206 {
 207         u32 tmp, tmp2;
 208
 209         /* We've already cleared the timeout interrupt register, so we learn
 210          * of interrupts via the validity register
 211          */
 212         tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 213                      GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
 214         if (!(tmp & QED_GRC_ATTENTION_VALID_BIT))
 215                 goto out;
 216
 217         /* Read the GRC timeout information */
 218         tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 219                      GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
 220         tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 221                       GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
 222
 223         DP_INFO(p_hwfn->cdev,
 224                 "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n",
 225                 tmp2, tmp,
 226                 (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from",
 227                 GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2,
 228                 attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)),
 229                 GET_FIELD(tmp2, QED_GRC_ATTENTION_PF),
 230                 (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) ==
 231                  QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant)",
 232                 GET_FIELD(tmp2, QED_GRC_ATTENTION_VF));
 233
 234 out:
 235         /* Regardles of anything else, clean the validity bit */
 236         qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 237                GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
 238         return 0;
 239 }
 240
 241 #define PGLUE_ATTENTION_VALID                   (1 << 29)
 242 #define PGLUE_ATTENTION_RD_VALID                (1 << 26)
 243 #define PGLUE_ATTENTION_DETAILS_PFID_MASK       (0xf)
 244 #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT      (20)
 245 #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK   (0x1)
 246 #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT  (19)
 247 #define PGLUE_ATTENTION_DETAILS_VFID_MASK       (0xff)
 248 #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT      (24)
 249 #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK   (0x1)
 250 #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT  (21)
 251 #define PGLUE_ATTENTION_DETAILS2_BME_MASK       (0x1)
 252 #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT      (22)
 253 #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK    (0x1)
 254 #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT   (23)
 255 #define PGLUE_ATTENTION_ICPL_VALID              (1 << 23)
 256 #define PGLUE_ATTENTION_ZLR_VALID               (1 << 25)
 257 #define PGLUE_ATTENTION_ILT_VALID               (1 << 23)
 258 static int qed_pglub_rbc_attn_cb(struct qed_hwfn *p_hwfn)
 259 {
 260         u32 tmp;
 261
 262         tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 263                      PGLUE_B_REG_TX_ERR_WR_DETAILS2);
 264         if (tmp & PGLUE_ATTENTION_VALID) {
 265                 u32 addr_lo, addr_hi, details;
 266
 267                 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 268                                  PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
 269                 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 270                                  PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
 271                 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 272                                  PGLUE_B_REG_TX_ERR_WR_DETAILS);
 273
 274                 DP_INFO(p_hwfn,
 275                         "Illegal write by chip to [%08x:%08x] blocked.\n"
 276                         "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n"
 277                         "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
 278                         addr_hi, addr_lo, details,
 279                         (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID),
 280                         (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID),
 281                         GET_FIELD(details,
 282                                   PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0,
 283                         tmp,
 284                         GET_FIELD(tmp,
 285                                   PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0,
 286                         GET_FIELD(tmp,
 287                                   PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0,
 288                         GET_FIELD(tmp,
 289                                   PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0);
 290         }
 291
 292         tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 293                      PGLUE_B_REG_TX_ERR_RD_DETAILS2);
 294         if (tmp & PGLUE_ATTENTION_RD_VALID) {
 295                 u32 addr_lo, addr_hi, details;
 296
 297                 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 298                                  PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
 299                 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 300                                  PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
 301                 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 302                                  PGLUE_B_REG_TX_ERR_RD_DETAILS);
 303
 304                 DP_INFO(p_hwfn,
 305                         "Illegal read by chip from [%08x:%08x] blocked.\n"
 306                         " Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n"
 307                         " Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
 308                         addr_hi, addr_lo, details,
 309                         (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID),
 310                         (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID),
 311                         GET_FIELD(details,
 312                                   PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0,
 313                         tmp,
 314                         GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1
 315                                                                          : 0,
 316                         GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0,
 317                         GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1
 318                                                                         : 0);
 319         }
 320
 321         tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 322                      PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
 323         if (tmp & PGLUE_ATTENTION_ICPL_VALID)
 324                 DP_INFO(p_hwfn, "ICPL error - %08x\n", tmp);
 325
 326         tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 327                      PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
 328         if (tmp & PGLUE_ATTENTION_ZLR_VALID) {
 329                 u32 addr_hi, addr_lo;
 330
 331                 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 332                                  PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
 333                 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 334                                  PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
 335
 336                 DP_INFO(p_hwfn, "ZLR eror - %08x [Address %08x:%08x]\n",
 337                         tmp, addr_hi, addr_lo);
 338         }
 339
 340         tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 341                      PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
 342         if (tmp & PGLUE_ATTENTION_ILT_VALID) {
 343                 u32 addr_hi, addr_lo, details;
 344
 345                 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 346                                  PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
 347                 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 348                                  PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
 349                 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 350                                  PGLUE_B_REG_VF_ILT_ERR_DETAILS);
 351
 352                 DP_INFO(p_hwfn,
 353                         "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n",
 354                         details, tmp, addr_hi, addr_lo);
 355         }
 356
 357         /* Clear the indications */
 358         qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 359                PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2));
 360
 361         return 0;
 362 }
 363
 364 #define QED_DORQ_ATTENTION_REASON_MASK  (0xfffff)
 365 #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff)
 366 #define QED_DORQ_ATTENTION_SIZE_MASK    (0x7f)
 367 #define QED_DORQ_ATTENTION_SIZE_SHIFT   (16)
 368 static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn)
 369 {
 370         u32 reason;
 371
 372         reason = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, DORQ_REG_DB_DROP_REASON) &
 373                         QED_DORQ_ATTENTION_REASON_MASK;
 374         if (reason) {
 375                 u32 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 376                                      DORQ_REG_DB_DROP_DETAILS);
 377
 378                 DP_INFO(p_hwfn->cdev,
 379                         "DORQ db_drop: address 0x%08x Opaque FID 0x%04x Size [bytes] 0x%08x Reason: 0x%08x\n",
 380                         qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 381                                DORQ_REG_DB_DROP_DETAILS_ADDRESS),
 382                         (u16)(details & QED_DORQ_ATTENTION_OPAQUE_MASK),
 383                         GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4,
 384                         reason);
 385         }
 386
 387         return -EINVAL;
 388 }
 389
 390 /* Instead of major changes to the data-structure, we have a some 'special'
 391  * identifiers for sources that changed meaning between adapters.
 392  */
 393 enum aeu_invert_reg_special_type {
 394         AEU_INVERT_REG_SPECIAL_CNIG_0,
 395         AEU_INVERT_REG_SPECIAL_CNIG_1,
 396         AEU_INVERT_REG_SPECIAL_CNIG_2,
 397         AEU_INVERT_REG_SPECIAL_CNIG_3,
 398         AEU_INVERT_REG_SPECIAL_MAX,
 399 };
 400
 401 static struct aeu_invert_reg_bit
 402 aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = {
 403         {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
 404         {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
 405         {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
 406         {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
 407 };
 408
 409 /* Notice aeu_invert_reg must be defined in the same order of bits as HW;  */
 410 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
 411         {
 412                 {       /* After Invert 1 */
 413                         {"GPIO0 function%d",
 414                          (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID},
 415                 }
 416         },
 417
 418         {
 419                 {       /* After Invert 2 */
 420                         {"PGLUE config_space", ATTENTION_SINGLE,
 421                          NULL, MAX_BLOCK_ID},
 422                         {"PGLUE misc_flr", ATTENTION_SINGLE,
 423                          NULL, MAX_BLOCK_ID},
 424                         {"PGLUE B RBC", ATTENTION_PAR_INT,
 425                          qed_pglub_rbc_attn_cb, BLOCK_PGLUE_B},
 426                         {"PGLUE misc_mctp", ATTENTION_SINGLE,
 427                          NULL, MAX_BLOCK_ID},
 428                         {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
 429                         {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
 430                         {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
 431                         {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) |
 432                                           (1 << ATTENTION_OFFSET_SHIFT),
 433                          NULL, MAX_BLOCK_ID},
 434                         {"PCIE glue/PXP VPD %d",
 435                          (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS},
 436                 }
 437         },
 438
 439         {
 440                 {       /* After Invert 3 */
 441                         {"General Attention %d",
 442                          (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID},
 443                 }
 444         },
 445
 446         {
 447                 {       /* After Invert 4 */
 448                         {"General Attention 32", ATTENTION_SINGLE,
 449                          NULL, MAX_BLOCK_ID},
 450                         {"General Attention %d",
 451                          (2 << ATTENTION_LENGTH_SHIFT) |
 452                          (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID},
 453                         {"General Attention 35", ATTENTION_SINGLE,
 454                          NULL, MAX_BLOCK_ID},
 455                         {"NWS Parity",
 456                          ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
 457                          ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0),
 458                          NULL, BLOCK_NWS},
 459                         {"NWS Interrupt",
 460                          ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
 461                          ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1),
 462                          NULL, BLOCK_NWS},
 463                         {"NWM Parity",
 464                          ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
 465                          ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2),
 466                          NULL, BLOCK_NWM},
 467                         {"NWM Interrupt",
 468                          ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
 469                          ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3),
 470                          NULL, BLOCK_NWM},
 471                         {"MCP CPU", ATTENTION_SINGLE,
 472                          qed_mcp_attn_cb, MAX_BLOCK_ID},
 473                         {"MCP Watchdog timer", ATTENTION_SINGLE,
 474                          NULL, MAX_BLOCK_ID},
 475                         {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
 476                         {"AVS stop status ready", ATTENTION_SINGLE,
 477                          NULL, MAX_BLOCK_ID},
 478                         {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID},
 479                         {"MSTAT per-path", ATTENTION_PAR_INT,
 480                          NULL, MAX_BLOCK_ID},
 481                         {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT),
 482                          NULL, MAX_BLOCK_ID},
 483                         {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG},
 484                         {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB},
 485                         {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB},
 486                         {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB},
 487                         {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS},
 488                 }
 489         },
 490
 491         {
 492                 {       /* After Invert 5 */
 493                         {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC},
 494                         {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1},
 495                         {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2},
 496                         {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB},
 497                         {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF},
 498                         {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM},
 499                         {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM},
 500                         {"MCM",  ATTENTION_PAR_INT, NULL, BLOCK_MCM},
 501                         {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM},
 502                         {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM},
 503                         {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM},
 504                         {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM},
 505                         {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM},
 506                         {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM},
 507                         {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM},
 508                         {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM},
 509                 }
 510         },
 511
 512         {
 513                 {       /* After Invert 6 */
 514                         {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM},
 515                         {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM},
 516                         {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM},
 517                         {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM},
 518                         {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM},
 519                         {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM},
 520                         {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM},
 521                         {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM},
 522                         {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM},
 523                         {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD},
 524                         {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD},
 525                         {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD},
 526                         {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD},
 527                         {"DORQ", ATTENTION_PAR_INT,
 528                          qed_dorq_attn_cb, BLOCK_DORQ},
 529                         {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG},
 530                         {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC},
 531                 }
 532         },
 533
 534         {
 535                 {       /* After Invert 7 */
 536                         {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC},
 537                         {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU},
 538                         {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE},
 539                         {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU},
 540                         {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID},
 541                         {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU},
 542                         {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU},
 543                         {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM},
 544                         {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC},
 545                         {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF},
 546                         {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF},
 547                         {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS},
 548                         {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC},
 549                         {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS},
 550                         {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE},
 551                         {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS},
 552                         {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ},
 553                 }
 554         },
 555
 556         {
 557                 {       /* After Invert 8 */
 558                         {"PSWRQ (pci_clk)", ATTENTION_PAR_INT,
 559                          NULL, BLOCK_PSWRQ2},
 560                         {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR},
 561                         {"PSWWR (pci_clk)", ATTENTION_PAR_INT,
 562                          NULL, BLOCK_PSWWR2},
 563                         {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD},
 564                         {"PSWRD (pci_clk)", ATTENTION_PAR_INT,
 565                          NULL, BLOCK_PSWRD2},
 566                         {"PSWHST", ATTENTION_PAR_INT,
 567                          qed_pswhst_attn_cb, BLOCK_PSWHST},
 568                         {"PSWHST (pci_clk)", ATTENTION_PAR_INT,
 569                          NULL, BLOCK_PSWHST2},
 570                         {"GRC", ATTENTION_PAR_INT,
 571                          qed_grc_attn_cb, BLOCK_GRC},
 572                         {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU},
 573                         {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI},
 574                         {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
 575                         {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
 576                         {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
 577                         {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
 578                         {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
 579                         {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
 580                         {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS},
 581                         {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE,
 582                          NULL, BLOCK_PGLCS},
 583                         {"PERST_B assertion", ATTENTION_SINGLE,
 584                          NULL, MAX_BLOCK_ID},
 585                         {"PERST_B deassertion", ATTENTION_SINGLE,
 586                          NULL, MAX_BLOCK_ID},
 587                         {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT),
 588                          NULL, MAX_BLOCK_ID},
 589                 }
 590         },
 591
 592         {
 593                 {       /* After Invert 9 */
 594                         {"MCP Latched memory", ATTENTION_PAR,
 595                          NULL, MAX_BLOCK_ID},
 596                         {"MCP Latched scratchpad cache", ATTENTION_SINGLE,
 597                          NULL, MAX_BLOCK_ID},
 598                         {"MCP Latched ump_tx", ATTENTION_PAR,
 599                          NULL, MAX_BLOCK_ID},
 600                         {"MCP Latched scratchpad", ATTENTION_PAR,
 601                          NULL, MAX_BLOCK_ID},
 602                         {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT),
 603                          NULL, MAX_BLOCK_ID},
 604                 }
 605         },
 606 };
 607
 608 static struct aeu_invert_reg_bit *
 609 qed_int_aeu_translate(struct qed_hwfn *p_hwfn,
 610                       struct aeu_invert_reg_bit *p_bit)
 611 {
 612         if (!QED_IS_BB(p_hwfn->cdev))
 613                 return p_bit;
 614
 615         if (!(p_bit->flags & ATTENTION_BB_DIFFERENT))
 616                 return p_bit;
 617
 618         return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >>
 619                                   ATTENTION_BB_SHIFT];
 620 }
 621
 622 static bool qed_int_is_parity_flag(struct qed_hwfn *p_hwfn,
 623                                    struct aeu_invert_reg_bit *p_bit)
 624 {
 625         return !!(qed_int_aeu_translate(p_hwfn, p_bit)->flags &
 626                    ATTENTION_PARITY);
 627 }
 628
 629 #define ATTN_STATE_BITS         (0xfff)
 630 #define ATTN_BITS_MASKABLE      (0x3ff)
 631 struct qed_sb_attn_info {
 632         /* Virtual & Physical address of the SB */
 633         struct atten_status_block       *sb_attn;
 634         dma_addr_t                      sb_phys;
 635
 636         /* Last seen running index */
 637         u16                             index;
 638
 639         /* A mask of the AEU bits resulting in a parity error */
 640         u32                             parity_mask[NUM_ATTN_REGS];
 641
 642         /* A pointer to the attention description structure */
 643         struct aeu_invert_reg           *p_aeu_desc;
 644
 645         /* Previously asserted attentions, which are still unasserted */
 646         u16                             known_attn;
 647
 648         /* Cleanup address for the link's general hw attention */
 649         u32                             mfw_attn_addr;
 650 };
 651
 652 static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn,
 653                                       struct qed_sb_attn_info *p_sb_desc)
 654 {
 655         u16 rc = 0, index;
 656
 657         /* Make certain HW write took affect */
 658         mmiowb();
 659
 660         index = le16_to_cpu(p_sb_desc->sb_attn->sb_index);
 661         if (p_sb_desc->index != index) {
 662                 p_sb_desc->index        = index;
 663                 rc                    = QED_SB_ATT_IDX;
 664         }
 665
 666         /* Make certain we got a consistent view with HW */
 667         mmiowb();
 668
 669         return rc;
 670 }
 671
 672 /**
 673  *  @brief qed_int_assertion - handles asserted attention bits
 674  *
 675  *  @param p_hwfn
 676  *  @param asserted_bits newly asserted bits
 677  *  @return int
 678  */
 679 static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits)
 680 {
 681         struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
 682         u32 igu_mask;
 683
 684         /* Mask the source of the attention in the IGU */
 685         igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE);
 686         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
 687                    igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
 688         igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
 689         qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
 690
 691         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
 692                    "inner known ATTN state: 0x%04x --> 0x%04x\n",
 693                    sb_attn_sw->known_attn,
 694                    sb_attn_sw->known_attn | asserted_bits);
 695         sb_attn_sw->known_attn |= asserted_bits;
 696
 697         /* Handle MCP events */
 698         if (asserted_bits & 0x100) {
 699                 qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
 700                 /* Clean the MCP attention */
 701                 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 702                        sb_attn_sw->mfw_attn_addr, 0);
 703         }
 704
 705         DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
 706                       GTT_BAR0_MAP_REG_IGU_CMD +
 707                       ((IGU_CMD_ATTN_BIT_SET_UPPER -
 708                         IGU_CMD_INT_ACK_BASE) << 3),
 709                       (u32)asserted_bits);
 710
 711         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n",
 712                    asserted_bits);
 713
 714         return 0;
 715 }
 716
 717 static void qed_int_attn_print(struct qed_hwfn *p_hwfn,
 718                                enum block_id id,
 719                                enum dbg_attn_type type, bool b_clear)
 720 {
 721         struct dbg_attn_block_result attn_results;
 722         enum dbg_status status;
 723
 724         memset(&attn_results, 0, sizeof(attn_results));
 725
 726         status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type,
 727                                    b_clear, &attn_results);
 728         if (status != DBG_STATUS_OK)
 729                 DP_NOTICE(p_hwfn,
 730                           "Failed to parse attention information [status: %s]\n",
 731                           qed_dbg_get_status_str(status));
 732         else
 733                 qed_dbg_parse_attn(p_hwfn, &attn_results);
 734 }
 735
 736 /**
 737  * @brief qed_int_deassertion_aeu_bit - handles the effects of a single
 738  * cause of the attention
 739  *
 740  * @param p_hwfn
 741  * @param p_aeu - descriptor of an AEU bit which caused the attention
 742  * @param aeu_en_reg - register offset of the AEU enable reg. which configured
 743  *  this bit to this group.
 744  * @param bit_index - index of this bit in the aeu_en_reg
 745  *
 746  * @return int
 747  */
 748 static int
 749 qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn,
 750                             struct aeu_invert_reg_bit *p_aeu,
 751                             u32 aeu_en_reg,
 752                             const char *p_bit_name, u32 bitmask)
 753 {
 754         bool b_fatal = false;
 755         int rc = -EINVAL;
 756         u32 val;
 757
 758         DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
 759                 p_bit_name, bitmask);
 760
 761         /* Call callback before clearing the interrupt status */
 762         if (p_aeu->cb) {
 763                 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n",
 764                         p_bit_name);
 765                 rc = p_aeu->cb(p_hwfn);
 766         }
 767
 768         if (rc)
 769                 b_fatal = true;
 770
 771         /* Print HW block interrupt registers */
 772         if (p_aeu->block_index != MAX_BLOCK_ID)
 773                 qed_int_attn_print(p_hwfn, p_aeu->block_index,
 774                                    ATTN_TYPE_INTERRUPT, !b_fatal);
 775
 776
 777         /* If the attention is benign, no need to prevent it */
 778         if (!rc)
 779                 goto out;
 780
 781         /* Prevent this Attention from being asserted in the future */
 782         val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
 783         qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask));
 784         DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n",
 785                 p_bit_name);
 786
 787 out:
 788         return rc;
 789 }
 790
 791 /**
 792  * @brief qed_int_deassertion_parity - handle a single parity AEU source
 793  *
 794  * @param p_hwfn
 795  * @param p_aeu - descriptor of an AEU bit which caused the parity
 796  * @param aeu_en_reg - address of the AEU enable register
 797  * @param bit_index
 798  */
 799 static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn,
 800                                        struct aeu_invert_reg_bit *p_aeu,
 801                                        u32 aeu_en_reg, u8 bit_index)
 802 {
 803         u32 block_id = p_aeu->block_index, mask, val;
 804
 805         DP_NOTICE(p_hwfn->cdev,
 806                   "%s parity attention is set [address 0x%08x, bit %d]\n",
 807                   p_aeu->bit_name, aeu_en_reg, bit_index);
 808
 809         if (block_id != MAX_BLOCK_ID) {
 810                 qed_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false);
 811
 812                 /* In BB, there's a single parity bit for several blocks */
 813                 if (block_id == BLOCK_BTB) {
 814                         qed_int_attn_print(p_hwfn, BLOCK_OPTE,
 815                                            ATTN_TYPE_PARITY, false);
 816                         qed_int_attn_print(p_hwfn, BLOCK_MCP,
 817                                            ATTN_TYPE_PARITY, false);
 818                 }
 819         }
 820
 821         /* Prevent this parity error from being re-asserted */
 822         mask = ~BIT(bit_index);
 823         val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
 824         qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask);
 825         DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n",
 826                 p_aeu->bit_name);
 827 }
 828
 829 /**
 830  * @brief - handles deassertion of previously asserted attentions.
 831  *
 832  * @param p_hwfn
 833  * @param deasserted_bits - newly deasserted bits
 834  * @return int
 835  *
 836  */
 837 static int qed_int_deassertion(struct qed_hwfn  *p_hwfn,
 838                                u16 deasserted_bits)
 839 {
 840         struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
 841         u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en;
 842         u8 i, j, k, bit_idx;
 843         int rc = 0;
 844
 845         /* Read the attention registers in the AEU */
 846         for (i = 0; i < NUM_ATTN_REGS; i++) {
 847                 aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 848                                         MISC_REG_AEU_AFTER_INVERT_1_IGU +
 849                                         i * 0x4);
 850                 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
 851                            "Deasserted bits [%d]: %08x\n",
 852                            i, aeu_inv_arr[i]);
 853         }
 854
 855         /* Find parity attentions first */
 856         for (i = 0; i < NUM_ATTN_REGS; i++) {
 857                 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
 858                 u32 parities;
 859
 860                 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32);
 861                 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
 862
 863                 /* Skip register in which no parity bit is currently set */
 864                 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
 865                 if (!parities)
 866                         continue;
 867
 868                 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
 869                         struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
 870
 871                         if (qed_int_is_parity_flag(p_hwfn, p_bit) &&
 872                             !!(parities & BIT(bit_idx)))
 873                                 qed_int_deassertion_parity(p_hwfn, p_bit,
 874                                                            aeu_en, bit_idx);
 875
 876                         bit_idx += ATTENTION_LENGTH(p_bit->flags);
 877                 }
 878         }
 879
 880         /* Find non-parity cause for attention and act */
 881         for (k = 0; k < MAX_ATTN_GRPS; k++) {
 882                 struct aeu_invert_reg_bit *p_aeu;
 883
 884                 /* Handle only groups whose attention is currently deasserted */
 885                 if (!(deasserted_bits & (1 << k)))
 886                         continue;
 887
 888                 for (i = 0; i < NUM_ATTN_REGS; i++) {
 889                         u32 bits;
 890
 891                         aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
 892                                  i * sizeof(u32) +
 893                                  k * sizeof(u32) * NUM_ATTN_REGS;
 894
 895                         en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
 896                         bits = aeu_inv_arr[i] & en;
 897
 898                         /* Skip if no bit from this group is currently set */
 899                         if (!bits)
 900                                 continue;
 901
 902                         /* Find all set bits from current register which belong
 903                          * to current group, making them responsible for the
 904                          * previous assertion.
 905                          */
 906                         for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
 907                                 long unsigned int bitmask;
 908                                 u8 bit, bit_len;
 909
 910                                 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
 911                                 p_aeu = qed_int_aeu_translate(p_hwfn, p_aeu);
 912
 913                                 bit = bit_idx;
 914                                 bit_len = ATTENTION_LENGTH(p_aeu->flags);
 915                                 if (qed_int_is_parity_flag(p_hwfn, p_aeu)) {
 916                                         /* Skip Parity */
 917                                         bit++;
 918                                         bit_len--;
 919                                 }
 920
 921                                 bitmask = bits & (((1 << bit_len) - 1) << bit);
 922                                 bitmask >>= bit;
 923
 924                                 if (bitmask) {
 925                                         u32 flags = p_aeu->flags;
 926                                         char bit_name[30];
 927                                         u8 num;
 928
 929                                         num = (u8)find_first_bit(&bitmask,
 930                                                                  bit_len);
 931
 932                                         /* Some bits represent more than a
 933                                          * a single interrupt. Correctly print
 934                                          * their name.
 935                                          */
 936                                         if (ATTENTION_LENGTH(flags) > 2 ||
 937                                             ((flags & ATTENTION_PAR_INT) &&
 938                                              ATTENTION_LENGTH(flags) > 1))
 939                                                 snprintf(bit_name, 30,
 940                                                          p_aeu->bit_name, num);
 941                                         else
 942                                                 strlcpy(bit_name,
 943                                                         p_aeu->bit_name, 30);
 944
 945                                         /* We now need to pass bitmask in its
 946                                          * correct position.
 947                                          */
 948                                         bitmask <<= bit;
 949
 950                                         /* Handle source of the attention */
 951                                         qed_int_deassertion_aeu_bit(p_hwfn,
 952                                                                     p_aeu,
 953                                                                     aeu_en,
 954                                                                     bit_name,
 955                                                                     bitmask);
 956                                 }
 957
 958                                 bit_idx += ATTENTION_LENGTH(p_aeu->flags);
 959                         }
 960                 }
 961         }
 962
 963         /* Clear IGU indication for the deasserted bits */
 964         DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
 965                                     GTT_BAR0_MAP_REG_IGU_CMD +
 966                                     ((IGU_CMD_ATTN_BIT_CLR_UPPER -
 967                                       IGU_CMD_INT_ACK_BASE) << 3),
 968                                     ~((u32)deasserted_bits));
 969
 970         /* Unmask deasserted attentions in IGU */
 971         aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE);
 972         aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
 973         qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
 974
 975         /* Clear deassertion from inner state */
 976         sb_attn_sw->known_attn &= ~deasserted_bits;
 977
 978         return rc;
 979 }
 980
 981 static int qed_int_attentions(struct qed_hwfn *p_hwfn)
 982 {
 983         struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
 984         struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
 985         u32 attn_bits = 0, attn_acks = 0;
 986         u16 asserted_bits, deasserted_bits;
 987         __le16 index;
 988         int rc = 0;
 989
 990         /* Read current attention bits/acks - safeguard against attentions
 991          * by guaranting work on a synchronized timeframe
 992          */
 993         do {
 994                 index = p_sb_attn->sb_index;
 995                 /* finish reading index before the loop condition */
 996                 dma_rmb();
 997                 attn_bits = le32_to_cpu(p_sb_attn->atten_bits);
 998                 attn_acks = le32_to_cpu(p_sb_attn->atten_ack);
 999         } while (index != p_sb_attn->sb_index);
1000         p_sb_attn->sb_index = index;
1001
1002         /* Attention / Deassertion are meaningful (and in correct state)
1003          * only when they differ and consistent with known state - deassertion
1004          * when previous attention & current ack, and assertion when current
1005          * attention with no previous attention
1006          */
1007         asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
1008                 ~p_sb_attn_sw->known_attn;
1009         deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
1010                 p_sb_attn_sw->known_attn;
1011
1012         if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) {
1013                 DP_INFO(p_hwfn,
1014                         "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
1015                         index, attn_bits, attn_acks, asserted_bits,
1016                         deasserted_bits, p_sb_attn_sw->known_attn);
1017         } else if (asserted_bits == 0x100) {
1018                 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1019                            "MFW indication via attention\n");
1020         } else {
1021                 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1022                            "MFW indication [deassertion]\n");
1023         }
1024
1025         if (asserted_bits) {
1026                 rc = qed_int_assertion(p_hwfn, asserted_bits);
1027                 if (rc)
1028                         return rc;
1029         }
1030
1031         if (deasserted_bits)
1032                 rc = qed_int_deassertion(p_hwfn, deasserted_bits);
1033
1034         return rc;
1035 }
1036
1037 static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn,
1038                             void __iomem *igu_addr, u32 ack_cons)
1039 {
1040         struct igu_prod_cons_update igu_ack = { 0 };
1041
1042         igu_ack.sb_id_and_flags =
1043                 ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1044                  (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1045                  (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1046                  (IGU_SEG_ACCESS_ATTN <<
1047                   IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1048
1049         DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags);
1050
1051         /* Both segments (interrupts & acks) are written to same place address;
1052          * Need to guarantee all commands will be received (in-order) by HW.
1053          */
1054         mmiowb();
1055         barrier();
1056 }
1057
1058 void qed_int_sp_dpc(unsigned long hwfn_cookie)
1059 {
1060         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie;
1061         struct qed_pi_info *pi_info = NULL;
1062         struct qed_sb_attn_info *sb_attn;
1063         struct qed_sb_info *sb_info;
1064         int arr_size;
1065         u16 rc = 0;
1066
1067         if (!p_hwfn->p_sp_sb) {
1068                 DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n");
1069                 return;
1070         }
1071
1072         sb_info = &p_hwfn->p_sp_sb->sb_info;
1073         arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
1074         if (!sb_info) {
1075                 DP_ERR(p_hwfn->cdev,
1076                        "Status block is NULL - cannot ack interrupts\n");
1077                 return;
1078         }
1079
1080         if (!p_hwfn->p_sb_attn) {
1081                 DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn");
1082                 return;
1083         }
1084         sb_attn = p_hwfn->p_sb_attn;
1085
1086         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
1087                    p_hwfn, p_hwfn->my_id);
1088
1089         /* Disable ack for def status block. Required both for msix +
1090          * inta in non-mask mode, in inta does no harm.
1091          */
1092         qed_sb_ack(sb_info, IGU_INT_DISABLE, 0);
1093
1094         /* Gather Interrupts/Attentions information */
1095         if (!sb_info->sb_virt) {
1096                 DP_ERR(p_hwfn->cdev,
1097                        "Interrupt Status block is NULL - cannot check for new interrupts!\n");
1098         } else {
1099                 u32 tmp_index = sb_info->sb_ack;
1100
1101                 rc = qed_sb_update_sb_idx(sb_info);
1102                 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
1103                            "Interrupt indices: 0x%08x --> 0x%08x\n",
1104                            tmp_index, sb_info->sb_ack);
1105         }
1106
1107         if (!sb_attn || !sb_attn->sb_attn) {
1108                 DP_ERR(p_hwfn->cdev,
1109                        "Attentions Status block is NULL - cannot check for new attentions!\n");
1110         } else {
1111                 u16 tmp_index = sb_attn->index;
1112
1113                 rc |= qed_attn_update_idx(p_hwfn, sb_attn);
1114                 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
1115                            "Attention indices: 0x%08x --> 0x%08x\n",
1116                            tmp_index, sb_attn->index);
1117         }
1118
1119         /* Check if we expect interrupts at this time. if not just ack them */
1120         if (!(rc & QED_SB_EVENT_MASK)) {
1121                 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1122                 return;
1123         }
1124
1125         /* Check the validity of the DPC ptt. If not ack interrupts and fail */
1126         if (!p_hwfn->p_dpc_ptt) {
1127                 DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n");
1128                 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1129                 return;
1130         }
1131
1132         if (rc & QED_SB_ATT_IDX)
1133                 qed_int_attentions(p_hwfn);
1134
1135         if (rc & QED_SB_IDX) {
1136                 int pi;
1137
1138                 /* Look for a free index */
1139                 for (pi = 0; pi < arr_size; pi++) {
1140                         pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
1141                         if (pi_info->comp_cb)
1142                                 pi_info->comp_cb(p_hwfn, pi_info->cookie);
1143                 }
1144         }
1145
1146         if (sb_attn && (rc & QED_SB_ATT_IDX))
1147                 /* This should be done before the interrupts are enabled,
1148                  * since otherwise a new attention will be generated.
1149                  */
1150                 qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
1151
1152         qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1153 }
1154
1155 static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn)
1156 {
1157         struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
1158
1159         if (!p_sb)
1160                 return;
1161
1162         if (p_sb->sb_attn)
1163                 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1164                                   SB_ATTN_ALIGNED_SIZE(p_hwfn),
1165                                   p_sb->sb_attn, p_sb->sb_phys);
1166         kfree(p_sb);
1167         p_hwfn->p_sb_attn = NULL;
1168 }
1169
1170 static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn,
1171                                   struct qed_ptt *p_ptt)
1172 {
1173         struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1174
1175         memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
1176
1177         sb_info->index = 0;
1178         sb_info->known_attn = 0;
1179
1180         /* Configure Attention Status Block in IGU */
1181         qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
1182                lower_32_bits(p_hwfn->p_sb_attn->sb_phys));
1183         qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
1184                upper_32_bits(p_hwfn->p_sb_attn->sb_phys));
1185 }
1186
1187 static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn,
1188                                  struct qed_ptt *p_ptt,
1189                                  void *sb_virt_addr, dma_addr_t sb_phy_addr)
1190 {
1191         struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1192         int i, j, k;
1193
1194         sb_info->sb_attn = sb_virt_addr;
1195         sb_info->sb_phys = sb_phy_addr;
1196
1197         /* Set the pointer to the AEU descriptors */
1198         sb_info->p_aeu_desc = aeu_descs;
1199
1200         /* Calculate Parity Masks */
1201         memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
1202         for (i = 0; i < NUM_ATTN_REGS; i++) {
1203                 /* j is array index, k is bit index */
1204                 for (j = 0, k = 0; k < 32; j++) {
1205                         struct aeu_invert_reg_bit *p_aeu;
1206
1207                         p_aeu = &aeu_descs[i].bits[j];
1208                         if (qed_int_is_parity_flag(p_hwfn, p_aeu))
1209                                 sb_info->parity_mask[i] |= 1 << k;
1210
1211                         k += ATTENTION_LENGTH(p_aeu->flags);
1212                 }
1213                 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1214                            "Attn Mask [Reg %d]: 0x%08x\n",
1215                            i, sb_info->parity_mask[i]);
1216         }
1217
1218         /* Set the address of cleanup for the mcp attention */
1219         sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
1220                                  MISC_REG_AEU_GENERAL_ATTN_0;
1221
1222         qed_int_sb_attn_setup(p_hwfn, p_ptt);
1223 }
1224
1225 static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn,
1226                                  struct qed_ptt *p_ptt)
1227 {
1228         struct qed_dev *cdev = p_hwfn->cdev;
1229         struct qed_sb_attn_info *p_sb;
1230         dma_addr_t p_phys = 0;
1231         void *p_virt;
1232
1233         /* SB struct */
1234         p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL);
1235         if (!p_sb)
1236                 return -ENOMEM;
1237
1238         /* SB ring  */
1239         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
1240                                     SB_ATTN_ALIGNED_SIZE(p_hwfn),
1241                                     &p_phys, GFP_KERNEL);
1242
1243         if (!p_virt) {
1244                 kfree(p_sb);
1245                 return -ENOMEM;
1246         }
1247
1248         /* Attention setup */
1249         p_hwfn->p_sb_attn = p_sb;
1250         qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
1251
1252         return 0;
1253 }
1254
1255 /* coalescing timeout = timeset << (timer_res + 1) */
1256 #define QED_CAU_DEF_RX_USECS 24
1257 #define QED_CAU_DEF_TX_USECS 48
1258
1259 void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
1260                            struct cau_sb_entry *p_sb_entry,
1261                            u8 pf_id, u16 vf_number, u8 vf_valid)
1262 {
1263         struct qed_dev *cdev = p_hwfn->cdev;
1264         u32 cau_state;
1265         u8 timer_res;
1266
1267         memset(p_sb_entry, 0, sizeof(*p_sb_entry));
1268
1269         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
1270         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
1271         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
1272         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
1273         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
1274
1275         cau_state = CAU_HC_DISABLE_STATE;
1276
1277         if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
1278                 cau_state = CAU_HC_ENABLE_STATE;
1279                 if (!cdev->rx_coalesce_usecs)
1280                         cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS;
1281                 if (!cdev->tx_coalesce_usecs)
1282                         cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS;
1283         }
1284
1285         /* Coalesce = (timeset << timer-res), timeset is 7bit wide */
1286         if (cdev->rx_coalesce_usecs <= 0x7F)
1287                 timer_res = 0;
1288         else if (cdev->rx_coalesce_usecs <= 0xFF)
1289                 timer_res = 1;
1290         else
1291                 timer_res = 2;
1292         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
1293
1294         if (cdev->tx_coalesce_usecs <= 0x7F)
1295                 timer_res = 0;
1296         else if (cdev->tx_coalesce_usecs <= 0xFF)
1297                 timer_res = 1;
1298         else
1299                 timer_res = 2;
1300         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
1301
1302         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
1303         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
1304 }
1305
1306 static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
1307                                 struct qed_ptt *p_ptt,
1308                                 u16 igu_sb_id,
1309                                 u32 pi_index,
1310                                 enum qed_coalescing_fsm coalescing_fsm,
1311                                 u8 timeset)
1312 {
1313         struct cau_pi_entry pi_entry;
1314         u32 sb_offset, pi_offset;
1315
1316         if (IS_VF(p_hwfn->cdev))
1317                 return;
1318
1319         sb_offset = igu_sb_id * PIS_PER_SB_E4;
1320         memset(&pi_entry, 0, sizeof(struct cau_pi_entry));
1321
1322         SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
1323         if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE)
1324                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
1325         else
1326                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
1327
1328         pi_offset = sb_offset + pi_index;
1329         if (p_hwfn->hw_init_done) {
1330                 qed_wr(p_hwfn, p_ptt,
1331                        CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
1332                        *((u32 *)&(pi_entry)));
1333         } else {
1334                 STORE_RT_REG(p_hwfn,
1335                              CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
1336                              *((u32 *)&(pi_entry)));
1337         }
1338 }
1339
1340 void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
1341                          struct qed_ptt *p_ptt,
1342                          dma_addr_t sb_phys,
1343                          u16 igu_sb_id, u16 vf_number, u8 vf_valid)
1344 {
1345         struct cau_sb_entry sb_entry;
1346
1347         qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
1348                               vf_number, vf_valid);
1349
1350         if (p_hwfn->hw_init_done) {
1351                 /* Wide-bus, initialize via DMAE */
1352                 u64 phys_addr = (u64)sb_phys;
1353
1354                 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr,
1355                                   CAU_REG_SB_ADDR_MEMORY +
1356                                   igu_sb_id * sizeof(u64), 2, 0);
1357                 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry,
1358                                   CAU_REG_SB_VAR_MEMORY +
1359                                   igu_sb_id * sizeof(u64), 2, 0);
1360         } else {
1361                 /* Initialize Status Block Address */
1362                 STORE_RT_REG_AGG(p_hwfn,
1363                                  CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
1364                                  igu_sb_id * 2,
1365                                  sb_phys);
1366
1367                 STORE_RT_REG_AGG(p_hwfn,
1368                                  CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
1369                                  igu_sb_id * 2,
1370                                  sb_entry);
1371         }
1372
1373         /* Configure pi coalescing if set */
1374         if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
1375                 u8 num_tc = p_hwfn->hw_info.num_hw_tc;
1376                 u8 timeset, timer_res;
1377                 u8 i;
1378
1379                 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */
1380                 if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F)
1381                         timer_res = 0;
1382                 else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF)
1383                         timer_res = 1;
1384                 else
1385                         timer_res = 2;
1386                 timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res);
1387                 qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
1388                                     QED_COAL_RX_STATE_MACHINE, timeset);
1389
1390                 if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F)
1391                         timer_res = 0;
1392                 else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF)
1393                         timer_res = 1;
1394                 else
1395                         timer_res = 2;
1396                 timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res);
1397                 for (i = 0; i < num_tc; i++) {
1398                         qed_int_cau_conf_pi(p_hwfn, p_ptt,
1399                                             igu_sb_id, TX_PI(i),
1400                                             QED_COAL_TX_STATE_MACHINE,
1401                                             timeset);
1402                 }
1403         }
1404 }
1405
1406 void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
1407                       struct qed_ptt *p_ptt, struct qed_sb_info *sb_info)
1408 {
1409         /* zero status block and ack counter */
1410         sb_info->sb_ack = 0;
1411         memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1412
1413         if (IS_PF(p_hwfn->cdev))
1414                 qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
1415                                     sb_info->igu_sb_id, 0, 0);
1416 }
1417
1418 struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, bool b_is_pf)
1419 {
1420         struct qed_igu_block *p_block;
1421         u16 igu_id;
1422
1423         for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
1424              igu_id++) {
1425                 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1426
1427                 if (!(p_block->status & QED_IGU_STATUS_VALID) ||
1428                     !(p_block->status & QED_IGU_STATUS_FREE))
1429                         continue;
1430
1431                 if (!!(p_block->status & QED_IGU_STATUS_PF) == b_is_pf)
1432                         return p_block;
1433         }
1434
1435         return NULL;
1436 }
1437
1438 static u16 qed_get_pf_igu_sb_id(struct qed_hwfn *p_hwfn, u16 vector_id)
1439 {
1440         struct qed_igu_block *p_block;
1441         u16 igu_id;
1442
1443         for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
1444              igu_id++) {
1445                 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1446
1447                 if (!(p_block->status & QED_IGU_STATUS_VALID) ||
1448                     !p_block->is_pf ||
1449                     p_block->vector_number != vector_id)
1450                         continue;
1451
1452                 return igu_id;
1453         }
1454
1455         return QED_SB_INVALID_IDX;
1456 }
1457
1458 u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id)
1459 {
1460         u16 igu_sb_id;
1461
1462         /* Assuming continuous set of IGU SBs dedicated for given PF */
1463         if (sb_id == QED_SP_SB_ID)
1464                 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1465         else if (IS_PF(p_hwfn->cdev))
1466                 igu_sb_id = qed_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
1467         else
1468                 igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id);
1469
1470         if (sb_id == QED_SP_SB_ID)
1471                 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1472                            "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
1473         else
1474                 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1475                            "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
1476
1477         return igu_sb_id;
1478 }
1479
1480 int qed_int_sb_init(struct qed_hwfn *p_hwfn,
1481                     struct qed_ptt *p_ptt,
1482                     struct qed_sb_info *sb_info,
1483                     void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id)
1484 {
1485         sb_info->sb_virt = sb_virt_addr;
1486         sb_info->sb_phys = sb_phy_addr;
1487
1488         sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id);
1489
1490         if (sb_id != QED_SP_SB_ID) {
1491                 if (IS_PF(p_hwfn->cdev)) {
1492                         struct qed_igu_info *p_info;
1493                         struct qed_igu_block *p_block;
1494
1495                         p_info = p_hwfn->hw_info.p_igu_info;
1496                         p_block = &p_info->entry[sb_info->igu_sb_id];
1497
1498                         p_block->sb_info = sb_info;
1499                         p_block->status &= ~QED_IGU_STATUS_FREE;
1500                         p_info->usage.free_cnt--;
1501                 } else {
1502                         qed_vf_set_sb_info(p_hwfn, sb_id, sb_info);
1503                 }
1504         }
1505
1506         sb_info->cdev = p_hwfn->cdev;
1507
1508         /* The igu address will hold the absolute address that needs to be
1509          * written to for a specific status block
1510          */
1511         if (IS_PF(p_hwfn->cdev)) {
1512                 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview +
1513                                                   GTT_BAR0_MAP_REG_IGU_CMD +
1514                                                   (sb_info->igu_sb_id << 3);
1515         } else {
1516                 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview +
1517                                                   PXP_VF_BAR0_START_IGU +
1518                                                   ((IGU_CMD_INT_ACK_BASE +
1519                                                     sb_info->igu_sb_id) << 3);
1520         }
1521
1522         sb_info->flags |= QED_SB_INFO_INIT;
1523
1524         qed_int_sb_setup(p_hwfn, p_ptt, sb_info);
1525
1526         return 0;
1527 }
1528
1529 int qed_int_sb_release(struct qed_hwfn *p_hwfn,
1530                        struct qed_sb_info *sb_info, u16 sb_id)
1531 {
1532         struct qed_igu_block *p_block;
1533         struct qed_igu_info *p_info;
1534
1535         if (!sb_info)
1536                 return 0;
1537
1538         /* zero status block and ack counter */
1539         sb_info->sb_ack = 0;
1540         memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1541
1542         if (IS_VF(p_hwfn->cdev)) {
1543                 qed_vf_set_sb_info(p_hwfn, sb_id, NULL);
1544                 return 0;
1545         }
1546
1547         p_info = p_hwfn->hw_info.p_igu_info;
1548         p_block = &p_info->entry[sb_info->igu_sb_id];
1549
1550         /* Vector 0 is reserved to Default SB */
1551         if (!p_block->vector_number) {
1552                 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
1553                 return -EINVAL;
1554         }
1555
1556         /* Lose reference to client's SB info, and fix counters */
1557         p_block->sb_info = NULL;
1558         p_block->status |= QED_IGU_STATUS_FREE;
1559         p_info->usage.free_cnt++;
1560
1561         return 0;
1562 }
1563
1564 static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn)
1565 {
1566         struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
1567
1568         if (!p_sb)
1569                 return;
1570
1571         if (p_sb->sb_info.sb_virt)
1572                 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1573                                   SB_ALIGNED_SIZE(p_hwfn),
1574                                   p_sb->sb_info.sb_virt,
1575                                   p_sb->sb_info.sb_phys);
1576         kfree(p_sb);
1577         p_hwfn->p_sp_sb = NULL;
1578 }
1579
1580 static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1581 {
1582         struct qed_sb_sp_info *p_sb;
1583         dma_addr_t p_phys = 0;
1584         void *p_virt;
1585
1586         /* SB struct */
1587         p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL);
1588         if (!p_sb)
1589                 return -ENOMEM;
1590
1591         /* SB ring  */
1592         p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1593                                     SB_ALIGNED_SIZE(p_hwfn),
1594                                     &p_phys, GFP_KERNEL);
1595         if (!p_virt) {
1596                 kfree(p_sb);
1597                 return -ENOMEM;
1598         }
1599
1600         /* Status Block setup */
1601         p_hwfn->p_sp_sb = p_sb;
1602         qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt,
1603                         p_phys, QED_SP_SB_ID);
1604
1605         memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
1606
1607         return 0;
1608 }
1609
1610 int qed_int_register_cb(struct qed_hwfn *p_hwfn,
1611                         qed_int_comp_cb_t comp_cb,
1612                         void *cookie, u8 *sb_idx, __le16 **p_fw_cons)
1613 {
1614         struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1615         int rc = -ENOMEM;
1616         u8 pi;
1617
1618         /* Look for a free index */
1619         for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
1620                 if (p_sp_sb->pi_info_arr[pi].comp_cb)
1621                         continue;
1622
1623                 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
1624                 p_sp_sb->pi_info_arr[pi].cookie = cookie;
1625                 *sb_idx = pi;
1626                 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
1627                 rc = 0;
1628                 break;
1629         }
1630
1631         return rc;
1632 }
1633
1634 int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi)
1635 {
1636         struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1637
1638         if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL)
1639                 return -ENOMEM;
1640
1641         p_sp_sb->pi_info_arr[pi].comp_cb = NULL;
1642         p_sp_sb->pi_info_arr[pi].cookie = NULL;
1643
1644         return 0;
1645 }
1646
1647 u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn)
1648 {
1649         return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
1650 }
1651
1652 void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
1653                             struct qed_ptt *p_ptt, enum qed_int_mode int_mode)
1654 {
1655         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
1656
1657         p_hwfn->cdev->int_mode = int_mode;
1658         switch (p_hwfn->cdev->int_mode) {
1659         case QED_INT_MODE_INTA:
1660                 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
1661                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1662                 break;
1663
1664         case QED_INT_MODE_MSI:
1665                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1666                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1667                 break;
1668
1669         case QED_INT_MODE_MSIX:
1670                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1671                 break;
1672         case QED_INT_MODE_POLL:
1673                 break;
1674         }
1675
1676         qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
1677 }
1678
1679 static void qed_int_igu_enable_attn(struct qed_hwfn *p_hwfn,
1680                                     struct qed_ptt *p_ptt)
1681 {
1682
1683         /* Configure AEU signal change to produce attentions */
1684         qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
1685         qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
1686         qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
1687         qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
1688
1689         /* Flush the writes to IGU */
1690         mmiowb();
1691
1692         /* Unmask AEU signals toward IGU */
1693         qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
1694 }
1695
1696 int
1697 qed_int_igu_enable(struct qed_hwfn *p_hwfn,
1698                    struct qed_ptt *p_ptt, enum qed_int_mode int_mode)
1699 {
1700         int rc = 0;
1701
1702         qed_int_igu_enable_attn(p_hwfn, p_ptt);
1703
1704         if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
1705                 rc = qed_slowpath_irq_req(p_hwfn);
1706                 if (rc) {
1707                         DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n");
1708                         return -EINVAL;
1709                 }
1710                 p_hwfn->b_int_requested = true;
1711         }
1712         /* Enable interrupt Generation */
1713         qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
1714         p_hwfn->b_int_enabled = 1;
1715
1716         return rc;
1717 }
1718
1719 void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1720 {
1721         p_hwfn->b_int_enabled = 0;
1722
1723         if (IS_VF(p_hwfn->cdev))
1724                 return;
1725
1726         qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
1727 }
1728
1729 #define IGU_CLEANUP_SLEEP_LENGTH                (1000)
1730 static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,
1731                                    struct qed_ptt *p_ptt,
1732                                    u16 igu_sb_id,
1733                                    bool cleanup_set, u16 opaque_fid)
1734 {
1735         u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0;
1736         u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id;
1737         u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
1738
1739         /* Set the data field */
1740         SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
1741         SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0);
1742         SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
1743
1744         /* Set the control register */
1745         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
1746         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
1747         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
1748
1749         qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
1750
1751         barrier();
1752
1753         qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
1754
1755         /* Flush the write to IGU */
1756         mmiowb();
1757
1758         /* calculate where to read the status bit from */
1759         sb_bit = 1 << (igu_sb_id % 32);
1760         sb_bit_addr = igu_sb_id / 32 * sizeof(u32);
1761
1762         sb_bit_addr += IGU_REG_CLEANUP_STATUS_0;
1763
1764         /* Now wait for the command to complete */
1765         do {
1766                 val = qed_rd(p_hwfn, p_ptt, sb_bit_addr);
1767
1768                 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
1769                         break;
1770
1771                 usleep_range(5000, 10000);
1772         } while (--sleep_cnt);
1773
1774         if (!sleep_cnt)
1775                 DP_NOTICE(p_hwfn,
1776                           "Timeout waiting for clear status 0x%08x [for sb %d]\n",
1777                           val, igu_sb_id);
1778 }
1779
1780 void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
1781                                      struct qed_ptt *p_ptt,
1782                                      u16 igu_sb_id, u16 opaque, bool b_set)
1783 {
1784         struct qed_igu_block *p_block;
1785         int pi, i;
1786
1787         p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
1788         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1789                    "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n",
1790                    igu_sb_id,
1791                    p_block->function_id,
1792                    p_block->is_pf, p_block->vector_number);
1793
1794         /* Set */
1795         if (b_set)
1796                 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque);
1797
1798         /* Clear */
1799         qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque);
1800
1801         /* Wait for the IGU SB to cleanup */
1802         for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
1803                 u32 val;
1804
1805                 val = qed_rd(p_hwfn, p_ptt,
1806                              IGU_REG_WRITE_DONE_PENDING +
1807                              ((igu_sb_id / 32) * 4));
1808                 if (val & BIT((igu_sb_id % 32)))
1809                         usleep_range(10, 20);
1810                 else
1811                         break;
1812         }
1813         if (i == IGU_CLEANUP_SLEEP_LENGTH)
1814                 DP_NOTICE(p_hwfn,
1815                           "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
1816                           igu_sb_id);
1817
1818         /* Clear the CAU for the SB */
1819         for (pi = 0; pi < 12; pi++)
1820                 qed_wr(p_hwfn, p_ptt,
1821                        CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0);
1822 }
1823
1824 void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
1825                               struct qed_ptt *p_ptt,
1826                               bool b_set, bool b_slowpath)
1827 {
1828         struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
1829         struct qed_igu_block *p_block;
1830         u16 igu_sb_id = 0;
1831         u32 val = 0;
1832
1833         val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
1834         val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
1835         val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
1836         qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
1837
1838         for (igu_sb_id = 0;
1839              igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) {
1840                 p_block = &p_info->entry[igu_sb_id];
1841
1842                 if (!(p_block->status & QED_IGU_STATUS_VALID) ||
1843                     !p_block->is_pf ||
1844                     (p_block->status & QED_IGU_STATUS_DSB))
1845                         continue;
1846
1847                 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id,
1848                                                 p_hwfn->hw_info.opaque_fid,
1849                                                 b_set);
1850         }
1851
1852         if (b_slowpath)
1853                 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt,
1854                                                 p_info->igu_dsb_id,
1855                                                 p_hwfn->hw_info.opaque_fid,
1856                                                 b_set);
1857 }
1858
1859 int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1860 {
1861         struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
1862         struct qed_igu_block *p_block;
1863         int pf_sbs, vf_sbs;
1864         u16 igu_sb_id;
1865         u32 val, rval;
1866
1867         if (!RESC_NUM(p_hwfn, QED_SB)) {
1868                 p_info->b_allow_pf_vf_change = false;
1869         } else {
1870                 /* Use the numbers the MFW have provided -
1871                  * don't forget MFW accounts for the default SB as well.
1872                  */
1873                 p_info->b_allow_pf_vf_change = true;
1874
1875                 if (p_info->usage.cnt != RESC_NUM(p_hwfn, QED_SB) - 1) {
1876                         DP_INFO(p_hwfn,
1877                                 "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n",
1878                                 RESC_NUM(p_hwfn, QED_SB) - 1,
1879                                 p_info->usage.cnt);
1880                         p_info->usage.cnt = RESC_NUM(p_hwfn, QED_SB) - 1;
1881                 }
1882
1883                 if (IS_PF_SRIOV(p_hwfn)) {
1884                         u16 vfs = p_hwfn->cdev->p_iov_info->total_vfs;
1885
1886                         if (vfs != p_info->usage.iov_cnt)
1887                                 DP_VERBOSE(p_hwfn,
1888                                            NETIF_MSG_INTR,
1889                                            "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n",
1890                                            p_info->usage.iov_cnt, vfs);
1891
1892                         /* At this point we know how many SBs we have totally
1893                          * in IGU + number of PF SBs. So we can validate that
1894                          * we'd have sufficient for VF.
1895                          */
1896                         if (vfs > p_info->usage.free_cnt +
1897                             p_info->usage.free_cnt_iov - p_info->usage.cnt) {
1898                                 DP_NOTICE(p_hwfn,
1899                                           "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n",
1900                                           p_info->usage.free_cnt +
1901                                           p_info->usage.free_cnt_iov,
1902                                           p_info->usage.cnt, vfs);
1903                                 return -EINVAL;
1904                         }
1905
1906                         /* Currently cap the number of VFs SBs by the
1907                          * number of VFs.
1908                          */
1909                         p_info->usage.iov_cnt = vfs;
1910                 }
1911         }
1912
1913         /* Mark all SBs as free, now in the right PF/VFs division */
1914         p_info->usage.free_cnt = p_info->usage.cnt;
1915         p_info->usage.free_cnt_iov = p_info->usage.iov_cnt;
1916         p_info->usage.orig = p_info->usage.cnt;
1917         p_info->usage.iov_orig = p_info->usage.iov_cnt;
1918
1919         /* We now proceed to re-configure the IGU cam to reflect the initial
1920          * configuration. We can start with the Default SB.
1921          */
1922         pf_sbs = p_info->usage.cnt;
1923         vf_sbs = p_info->usage.iov_cnt;
1924
1925         for (igu_sb_id = p_info->igu_dsb_id;
1926              igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) {
1927                 p_block = &p_info->entry[igu_sb_id];
1928                 val = 0;
1929
1930                 if (!(p_block->status & QED_IGU_STATUS_VALID))
1931                         continue;
1932
1933                 if (p_block->status & QED_IGU_STATUS_DSB) {
1934                         p_block->function_id = p_hwfn->rel_pf_id;
1935                         p_block->is_pf = 1;
1936                         p_block->vector_number = 0;
1937                         p_block->status = QED_IGU_STATUS_VALID |
1938                                           QED_IGU_STATUS_PF |
1939                                           QED_IGU_STATUS_DSB;
1940                 } else if (pf_sbs) {
1941                         pf_sbs--;
1942                         p_block->function_id = p_hwfn->rel_pf_id;
1943                         p_block->is_pf = 1;
1944                         p_block->vector_number = p_info->usage.cnt - pf_sbs;
1945                         p_block->status = QED_IGU_STATUS_VALID |
1946                                           QED_IGU_STATUS_PF |
1947                                           QED_IGU_STATUS_FREE;
1948                 } else if (vf_sbs) {
1949                         p_block->function_id =
1950                             p_hwfn->cdev->p_iov_info->first_vf_in_pf +
1951                             p_info->usage.iov_cnt - vf_sbs;
1952                         p_block->is_pf = 0;
1953                         p_block->vector_number = 0;
1954                         p_block->status = QED_IGU_STATUS_VALID |
1955                                           QED_IGU_STATUS_FREE;
1956                         vf_sbs--;
1957                 } else {
1958                         p_block->function_id = 0;
1959                         p_block->is_pf = 0;
1960                         p_block->vector_number = 0;
1961                 }
1962
1963                 SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
1964                           p_block->function_id);
1965                 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
1966                 SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
1967                           p_block->vector_number);
1968
1969                 /* VF entries would be enabled when VF is initializaed */
1970                 SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
1971
1972                 rval = qed_rd(p_hwfn, p_ptt,
1973                               IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id);
1974
1975                 if (rval != val) {
1976                         qed_wr(p_hwfn, p_ptt,
1977                                IGU_REG_MAPPING_MEMORY +
1978                                sizeof(u32) * igu_sb_id, val);
1979
1980                         DP_VERBOSE(p_hwfn,
1981                                    NETIF_MSG_INTR,
1982                                    "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n",
1983                                    igu_sb_id,
1984                                    p_block->function_id,
1985                                    p_block->is_pf,
1986                                    p_block->vector_number, rval, val);
1987                 }
1988         }
1989
1990         return 0;
1991 }
1992
1993 static void qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn,
1994                                        struct qed_ptt *p_ptt, u16 igu_sb_id)
1995 {
1996         u32 val = qed_rd(p_hwfn, p_ptt,
1997                          IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id);
1998         struct qed_igu_block *p_block;
1999
2000         p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
2001
2002         /* Fill the block information */
2003         p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER);
2004         p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
2005         p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER);
2006         p_block->igu_sb_id = igu_sb_id;
2007 }
2008
2009 int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2010 {
2011         struct qed_igu_info *p_igu_info;
2012         struct qed_igu_block *p_block;
2013         u32 min_vf = 0, max_vf = 0;
2014         u16 igu_sb_id;
2015
2016         p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL);
2017         if (!p_hwfn->hw_info.p_igu_info)
2018                 return -ENOMEM;
2019
2020         p_igu_info = p_hwfn->hw_info.p_igu_info;
2021
2022         /* Distinguish between existent and non-existent default SB */
2023         p_igu_info->igu_dsb_id = QED_SB_INVALID_IDX;
2024
2025         /* Find the range of VF ids whose SB belong to this PF */
2026         if (p_hwfn->cdev->p_iov_info) {
2027                 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
2028
2029                 min_vf  = p_iov->first_vf_in_pf;
2030                 max_vf  = p_iov->first_vf_in_pf + p_iov->total_vfs;
2031         }
2032
2033         for (igu_sb_id = 0;
2034              igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) {
2035                 /* Read current entry; Notice it might not belong to this PF */
2036                 qed_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id);
2037                 p_block = &p_igu_info->entry[igu_sb_id];
2038
2039                 if ((p_block->is_pf) &&
2040                     (p_block->function_id == p_hwfn->rel_pf_id)) {
2041                         p_block->status = QED_IGU_STATUS_PF |
2042                                           QED_IGU_STATUS_VALID |
2043                                           QED_IGU_STATUS_FREE;
2044
2045                         if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX)
2046                                 p_igu_info->usage.cnt++;
2047                 } else if (!(p_block->is_pf) &&
2048                            (p_block->function_id >= min_vf) &&
2049                            (p_block->function_id < max_vf)) {
2050                         /* Available for VFs of this PF */
2051                         p_block->status = QED_IGU_STATUS_VALID |
2052                                           QED_IGU_STATUS_FREE;
2053
2054                         if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX)
2055                                 p_igu_info->usage.iov_cnt++;
2056                 }
2057
2058                 /* Mark the First entry belonging to the PF or its VFs
2059                  * as the default SB [we'll reset IGU prior to first usage].
2060                  */
2061                 if ((p_block->status & QED_IGU_STATUS_VALID) &&
2062                     (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX)) {
2063                         p_igu_info->igu_dsb_id = igu_sb_id;
2064                         p_block->status |= QED_IGU_STATUS_DSB;
2065                 }
2066
2067                 /* limit number of prints by having each PF print only its
2068                  * entries with the exception of PF0 which would print
2069                  * everything.
2070                  */
2071                 if ((p_block->status & QED_IGU_STATUS_VALID) ||
2072                     (p_hwfn->abs_pf_id == 0)) {
2073                         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2074                                    "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2075                                    igu_sb_id, p_block->function_id,
2076                                    p_block->is_pf, p_block->vector_number);
2077                 }
2078         }
2079
2080         if (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX) {
2081                 DP_NOTICE(p_hwfn,
2082                           "IGU CAM returned invalid values igu_dsb_id=0x%x\n",
2083                           p_igu_info->igu_dsb_id);
2084                 return -EINVAL;
2085         }
2086
2087         /* All non default SB are considered free at this point */
2088         p_igu_info->usage.free_cnt = p_igu_info->usage.cnt;
2089         p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt;
2090
2091         DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2092                    "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n",
2093                    p_igu_info->igu_dsb_id,
2094                    p_igu_info->usage.cnt, p_igu_info->usage.iov_cnt);
2095
2096         return 0;
2097 }
2098
2099 /**
2100  * @brief Initialize igu runtime registers
2101  *
2102  * @param p_hwfn
2103  */
2104 void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn)
2105 {
2106         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
2107
2108         STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
2109 }
2110
2111 u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn)
2112 {
2113         u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER -
2114                                IGU_CMD_INT_ACK_BASE;
2115         u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER -
2116                                IGU_CMD_INT_ACK_BASE;
2117         u32 intr_status_hi = 0, intr_status_lo = 0;
2118         u64 intr_status = 0;
2119
2120         intr_status_lo = REG_RD(p_hwfn,
2121                                 GTT_BAR0_MAP_REG_IGU_CMD +
2122                                 lsb_igu_cmd_addr * 8);
2123         intr_status_hi = REG_RD(p_hwfn,
2124                                 GTT_BAR0_MAP_REG_IGU_CMD +
2125                                 msb_igu_cmd_addr * 8);
2126         intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
2127
2128         return intr_status;
2129 }
2130
2131 static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn)
2132 {
2133         tasklet_init(p_hwfn->sp_dpc,
2134                      qed_int_sp_dpc, (unsigned long)p_hwfn);
2135         p_hwfn->b_sp_dpc_enabled = true;
2136 }
2137
2138 static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn)
2139 {
2140         p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL);
2141         if (!p_hwfn->sp_dpc)
2142                 return -ENOMEM;
2143
2144         return 0;
2145 }
2146
2147 static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn)
2148 {
2149         kfree(p_hwfn->sp_dpc);
2150         p_hwfn->sp_dpc = NULL;
2151 }
2152
2153 int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2154 {
2155         int rc = 0;
2156
2157         rc = qed_int_sp_dpc_alloc(p_hwfn);
2158         if (rc)
2159                 return rc;
2160
2161         rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt);
2162         if (rc)
2163                 return rc;
2164
2165         rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt);
2166
2167         return rc;
2168 }
2169
2170 void qed_int_free(struct qed_hwfn *p_hwfn)
2171 {
2172         qed_int_sp_sb_free(p_hwfn);
2173         qed_int_sb_attn_free(p_hwfn);
2174         qed_int_sp_dpc_free(p_hwfn);
2175 }
2176
2177 void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2178 {
2179         qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
2180         qed_int_sb_attn_setup(p_hwfn, p_ptt);
2181         qed_int_sp_dpc_setup(p_hwfn);
2182 }
2183
2184 void qed_int_get_num_sbs(struct qed_hwfn        *p_hwfn,
2185                          struct qed_sb_cnt_info *p_sb_cnt_info)
2186 {
2187         struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info;
2188
2189         if (!info || !p_sb_cnt_info)
2190                 return;
2191
2192         memcpy(p_sb_cnt_info, &info->usage, sizeof(*p_sb_cnt_info));
2193 }
2194
2195 void qed_int_disable_post_isr_release(struct qed_dev *cdev)
2196 {
2197         int i;
2198
2199         for_each_hwfn(cdev, i)
2200                 cdev->hwfns[i].b_int_requested = false;
2201 }
2202
2203 int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2204                           u8 timer_res, u16 sb_id, bool tx)
2205 {
2206         struct cau_sb_entry sb_entry;
2207         int rc;
2208
2209         if (!p_hwfn->hw_init_done) {
2210                 DP_ERR(p_hwfn, "hardware not initialized yet\n");
2211                 return -EINVAL;
2212         }
2213
2214         rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2215                                sb_id * sizeof(u64),
2216                                (u64)(uintptr_t)&sb_entry, 2, 0);
2217         if (rc) {
2218                 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2219                 return rc;
2220         }
2221
2222         if (tx)
2223                 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
2224         else
2225                 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
2226
2227         rc = qed_dmae_host2grc(p_hwfn, p_ptt,
2228                                (u64)(uintptr_t)&sb_entry,
2229                                CAU_REG_SB_VAR_MEMORY +
2230                                sb_id * sizeof(u64), 2, 0);
2231         if (rc) {
2232                 DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
2233                 return rc;
2234         }
2235
2236         return rc;
2237 }