1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
12 #include <linux/types.h>
14 #include <linux/bitops.h>
15 #include <linux/delay.h>
16 #include <linux/kernel.h>
17 #include <linux/list.h>
18 #include <linux/slab.h>
19 #include <linux/qed/common_hsi.h>
20 #include <linux/qed/storage_common.h>
21 #include <linux/qed/tcp_common.h>
22 #include <linux/qed/eth_common.h>
23 #include <linux/qed/iscsi_common.h>
24 #include <linux/qed/rdma_common.h>
25 #include <linux/qed/roce_common.h>
30 /* opcodes for the event ring */
31 enum common_event_opcode {
32 COMMON_EVENT_PF_START,
34 COMMON_EVENT_VF_START,
36 COMMON_EVENT_VF_PF_CHANNEL,
38 COMMON_EVENT_PF_UPDATE,
39 COMMON_EVENT_MALICIOUS_VF,
40 COMMON_EVENT_RL_UPDATE,
42 MAX_COMMON_EVENT_OPCODE
45 /* Common Ramrod Command IDs */
46 enum common_ramrod_cmd_id {
48 COMMON_RAMROD_PF_START,
49 COMMON_RAMROD_PF_STOP,
50 COMMON_RAMROD_VF_START,
51 COMMON_RAMROD_VF_STOP,
52 COMMON_RAMROD_PF_UPDATE,
53 COMMON_RAMROD_RL_UPDATE,
55 MAX_COMMON_RAMROD_CMD_ID
58 /* The core storm context for the Ystorm */
59 struct ystorm_core_conn_st_ctx {
63 /* The core storm context for the Pstorm */
64 struct pstorm_core_conn_st_ctx {
68 /* Core Slowpath Connection storm context of Xstorm */
69 struct xstorm_core_conn_st_ctx {
72 struct regpair consolid_base_addr;
78 struct xstorm_core_conn_ag_ctx {
82 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
83 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
84 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
85 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
86 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
87 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
88 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
89 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
90 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
91 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
92 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
93 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
94 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
95 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
96 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
97 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
99 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
100 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
101 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
102 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
103 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
104 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
105 #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
106 #define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
107 #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
108 #define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
109 #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
110 #define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
111 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
112 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
113 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
114 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
116 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
117 #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
118 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
119 #define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
120 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
121 #define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
122 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
123 #define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
125 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
126 #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
127 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
128 #define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
129 #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
130 #define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
131 #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
132 #define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
134 #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
135 #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
136 #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
137 #define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
138 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
139 #define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
140 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
141 #define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
143 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
144 #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
145 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
146 #define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
147 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
148 #define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
149 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
150 #define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
152 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
153 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
154 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
155 #define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
156 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
157 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
158 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
159 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
161 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
162 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
163 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
164 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
165 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
166 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
167 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
168 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
169 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
170 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
172 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
173 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
174 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
175 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
176 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
177 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
178 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
179 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
180 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
181 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
182 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
183 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
184 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
185 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
186 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
187 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
189 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
190 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
191 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
192 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
193 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
194 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
195 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
196 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
197 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
198 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
199 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
200 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
201 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
202 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
203 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
204 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
206 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
207 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
208 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
209 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
210 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
211 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
212 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
213 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
214 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
215 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
216 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
217 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
218 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
219 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
220 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
221 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
223 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
224 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
225 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
226 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
227 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
228 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
229 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
230 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
231 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
232 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
233 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
234 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
235 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
236 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
237 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
238 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
240 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
241 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
242 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
243 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
244 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
245 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
246 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
247 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
248 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
249 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
250 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
251 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
252 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
253 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
254 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
255 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
257 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
258 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
259 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
260 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
261 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
262 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
263 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
264 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
265 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
266 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
267 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
268 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
269 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
270 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
271 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
272 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
274 #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
275 #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
276 #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
277 #define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
278 #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
279 #define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
280 #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
281 #define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
282 #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
283 #define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
284 #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
285 #define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
286 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
287 #define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
290 __le16 consolid_prod;
293 __le16 tx_bd_or_spq_prod;
341 struct tstorm_core_conn_ag_ctx {
345 #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
346 #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
347 #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
348 #define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
349 #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1
350 #define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
351 #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1
352 #define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
353 #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1
354 #define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
355 #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1
356 #define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
357 #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
358 #define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
360 #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
361 #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
362 #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
363 #define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
364 #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
365 #define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
366 #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
367 #define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
369 #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
370 #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
371 #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
372 #define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
373 #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
374 #define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
375 #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
376 #define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
378 #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
379 #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
380 #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
381 #define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
382 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
383 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
384 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
385 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
386 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
387 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
388 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
389 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
391 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
392 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
393 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
394 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
395 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
396 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
397 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
398 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
399 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
400 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
401 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
402 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
403 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
404 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
405 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
406 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
408 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
409 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
410 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
411 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
412 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
413 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
414 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
415 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
416 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
417 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
418 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
419 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
420 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
421 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
422 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
423 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
445 struct ustorm_core_conn_ag_ctx {
449 #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
450 #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
451 #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
452 #define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
453 #define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
454 #define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
455 #define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
456 #define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
457 #define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
458 #define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
460 #define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
461 #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
462 #define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
463 #define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
464 #define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
465 #define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
466 #define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
467 #define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
469 #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
470 #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
471 #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
472 #define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
473 #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
474 #define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
475 #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
476 #define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
477 #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
478 #define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
479 #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
480 #define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
481 #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
482 #define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
483 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
484 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
486 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
487 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
488 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
489 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
490 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
491 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
492 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
493 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
494 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
495 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
496 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
497 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
498 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
499 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
500 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
501 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
514 /* The core storm context for the Mstorm */
515 struct mstorm_core_conn_st_ctx {
519 /* The core storm context for the Ustorm */
520 struct ustorm_core_conn_st_ctx {
524 /* core connection context */
525 struct core_conn_context {
526 struct ystorm_core_conn_st_ctx ystorm_st_context;
527 struct regpair ystorm_st_padding[2];
528 struct pstorm_core_conn_st_ctx pstorm_st_context;
529 struct regpair pstorm_st_padding[2];
530 struct xstorm_core_conn_st_ctx xstorm_st_context;
531 struct xstorm_core_conn_ag_ctx xstorm_ag_context;
532 struct tstorm_core_conn_ag_ctx tstorm_ag_context;
533 struct ustorm_core_conn_ag_ctx ustorm_ag_context;
534 struct mstorm_core_conn_st_ctx mstorm_st_context;
535 struct ustorm_core_conn_st_ctx ustorm_st_context;
536 struct regpair ustorm_st_padding[2];
539 enum core_error_handle {
543 MAX_CORE_ERROR_HANDLE
546 enum core_event_opcode {
547 CORE_EVENT_TX_QUEUE_START,
548 CORE_EVENT_TX_QUEUE_STOP,
549 CORE_EVENT_RX_QUEUE_START,
550 CORE_EVENT_RX_QUEUE_STOP,
551 MAX_CORE_EVENT_OPCODE
554 enum core_l4_pseudo_checksum_mode {
555 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
556 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
557 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
560 struct core_ll2_port_stats {
561 struct regpair gsi_invalid_hdr;
562 struct regpair gsi_invalid_pkt_length;
563 struct regpair gsi_unsupported_pkt_typ;
564 struct regpair gsi_crcchksm_error;
567 struct core_ll2_pstorm_per_queue_stat {
568 struct regpair sent_ucast_bytes;
569 struct regpair sent_mcast_bytes;
570 struct regpair sent_bcast_bytes;
571 struct regpair sent_ucast_pkts;
572 struct regpair sent_mcast_pkts;
573 struct regpair sent_bcast_pkts;
576 struct core_ll2_rx_prod {
582 struct core_ll2_tstorm_per_queue_stat {
583 struct regpair packet_too_big_discard;
584 struct regpair no_buff_discard;
587 struct core_ll2_ustorm_per_queue_stat {
588 struct regpair rcv_ucast_bytes;
589 struct regpair rcv_mcast_bytes;
590 struct regpair rcv_bcast_bytes;
591 struct regpair rcv_ucast_pkts;
592 struct regpair rcv_mcast_pkts;
593 struct regpair rcv_bcast_pkts;
596 enum core_ramrod_cmd_id {
598 CORE_RAMROD_RX_QUEUE_START,
599 CORE_RAMROD_TX_QUEUE_START,
600 CORE_RAMROD_RX_QUEUE_STOP,
601 CORE_RAMROD_TX_QUEUE_STOP,
602 MAX_CORE_RAMROD_CMD_ID
605 enum core_roce_flavor_type {
608 MAX_CORE_ROCE_FLAVOR_TYPE
611 struct core_rx_action_on_error {
613 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
614 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
615 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
616 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2
617 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
618 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4
626 struct core_rx_bd_with_buff_len {
632 union core_rx_bd_union {
633 struct core_rx_bd rx_bd;
634 struct core_rx_bd_with_buff_len rx_bd_with_len;
637 struct core_rx_cqe_opaque_data {
641 enum core_rx_cqe_type {
642 CORE_RX_CQE_ILLIGAL_TYPE,
643 CORE_RX_CQE_TYPE_REGULAR,
644 CORE_RX_CQE_TYPE_GSI_OFFLOAD,
645 CORE_RX_CQE_TYPE_SLOW_PATH,
649 struct core_rx_fast_path_cqe {
652 struct parsing_and_err_flags parse_flags;
653 __le16 packet_length;
655 struct core_rx_cqe_opaque_data opaque_data;
659 struct core_rx_gsi_offload_cqe {
661 u8 data_length_error;
662 struct parsing_and_err_flags parse_flags;
665 __le32 src_mac_addrhi;
666 __le16 src_mac_addrlo;
671 struct core_rx_slow_path_cqe {
678 union core_rx_cqe_union {
679 struct core_rx_fast_path_cqe rx_cqe_fp;
680 struct core_rx_gsi_offload_cqe rx_cqe_gsi;
681 struct core_rx_slow_path_cqe rx_cqe_sp;
684 struct core_rx_start_ramrod_data {
685 struct regpair bd_base;
686 struct regpair cqe_pbl_addr;
691 u8 complete_event_flg;
693 __le16 num_of_pbl_pages;
694 u8 inner_vlan_removal_en;
697 u8 mf_si_bcast_accept_all;
698 u8 mf_si_mcast_accept_all;
699 struct core_rx_action_on_error action_on_error;
704 struct core_rx_stop_ramrod_data {
706 u8 complete_event_flg;
712 struct core_tx_bd_flags {
714 #define CORE_TX_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
715 #define CORE_TX_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 0
716 #define CORE_TX_BD_FLAGS_VLAN_INSERTION_MASK 0x1
717 #define CORE_TX_BD_FLAGS_VLAN_INSERTION_SHIFT 1
718 #define CORE_TX_BD_FLAGS_START_BD_MASK 0x1
719 #define CORE_TX_BD_FLAGS_START_BD_SHIFT 2
720 #define CORE_TX_BD_FLAGS_IP_CSUM_MASK 0x1
721 #define CORE_TX_BD_FLAGS_IP_CSUM_SHIFT 3
722 #define CORE_TX_BD_FLAGS_L4_CSUM_MASK 0x1
723 #define CORE_TX_BD_FLAGS_L4_CSUM_SHIFT 4
724 #define CORE_TX_BD_FLAGS_IPV6_EXT_MASK 0x1
725 #define CORE_TX_BD_FLAGS_IPV6_EXT_SHIFT 5
726 #define CORE_TX_BD_FLAGS_L4_PROTOCOL_MASK 0x1
727 #define CORE_TX_BD_FLAGS_L4_PROTOCOL_SHIFT 6
728 #define CORE_TX_BD_FLAGS_L4_PSEUDO_CSUM_MODE_MASK 0x1
729 #define CORE_TX_BD_FLAGS_L4_PSEUDO_CSUM_MODE_SHIFT 7
735 __le16 nw_vlan_or_lb_echo;
737 #define CORE_TX_BD_NBDS_MASK 0xF
738 #define CORE_TX_BD_NBDS_SHIFT 0
739 #define CORE_TX_BD_ROCE_FLAV_MASK 0x1
740 #define CORE_TX_BD_ROCE_FLAV_SHIFT 4
741 #define CORE_TX_BD_RESERVED0_MASK 0x7
742 #define CORE_TX_BD_RESERVED0_SHIFT 5
743 struct core_tx_bd_flags bd_flags;
745 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
746 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
747 #define CORE_TX_BD_TX_DST_MASK 0x1
748 #define CORE_TX_BD_TX_DST_SHIFT 14
749 #define CORE_TX_BD_RESERVED1_MASK 0x1
750 #define CORE_TX_BD_RESERVED1_SHIFT 15
759 struct core_tx_start_ramrod_data {
760 struct regpair pbl_base_addr;
773 struct core_tx_stop_ramrod_data {
777 struct eth_mstorm_per_pf_stat {
778 struct regpair gre_discard_pkts;
779 struct regpair vxlan_discard_pkts;
780 struct regpair geneve_discard_pkts;
781 struct regpair lb_discard_pkts;
784 struct eth_mstorm_per_queue_stat {
785 struct regpair ttl0_discard;
786 struct regpair packet_too_big_discard;
787 struct regpair no_buff_discard;
788 struct regpair not_active_discard;
789 struct regpair tpa_coalesced_pkts;
790 struct regpair tpa_coalesced_events;
791 struct regpair tpa_aborts_num;
792 struct regpair tpa_coalesced_bytes;
795 /* Ethernet TX Per PF */
796 struct eth_pstorm_per_pf_stat {
797 struct regpair sent_lb_ucast_bytes;
798 struct regpair sent_lb_mcast_bytes;
799 struct regpair sent_lb_bcast_bytes;
800 struct regpair sent_lb_ucast_pkts;
801 struct regpair sent_lb_mcast_pkts;
802 struct regpair sent_lb_bcast_pkts;
803 struct regpair sent_gre_bytes;
804 struct regpair sent_vxlan_bytes;
805 struct regpair sent_geneve_bytes;
806 struct regpair sent_gre_pkts;
807 struct regpair sent_vxlan_pkts;
808 struct regpair sent_geneve_pkts;
809 struct regpair gre_drop_pkts;
810 struct regpair vxlan_drop_pkts;
811 struct regpair geneve_drop_pkts;
814 /* Ethernet TX Per Queue Stats */
815 struct eth_pstorm_per_queue_stat {
816 struct regpair sent_ucast_bytes;
817 struct regpair sent_mcast_bytes;
818 struct regpair sent_bcast_bytes;
819 struct regpair sent_ucast_pkts;
820 struct regpair sent_mcast_pkts;
821 struct regpair sent_bcast_pkts;
822 struct regpair error_drop_pkts;
825 /* ETH Rx producers data */
826 struct eth_rx_rate_limit {
834 struct eth_ustorm_per_pf_stat {
835 struct regpair rcv_lb_ucast_bytes;
836 struct regpair rcv_lb_mcast_bytes;
837 struct regpair rcv_lb_bcast_bytes;
838 struct regpair rcv_lb_ucast_pkts;
839 struct regpair rcv_lb_mcast_pkts;
840 struct regpair rcv_lb_bcast_pkts;
841 struct regpair rcv_gre_bytes;
842 struct regpair rcv_vxlan_bytes;
843 struct regpair rcv_geneve_bytes;
844 struct regpair rcv_gre_pkts;
845 struct regpair rcv_vxlan_pkts;
846 struct regpair rcv_geneve_pkts;
849 struct eth_ustorm_per_queue_stat {
850 struct regpair rcv_ucast_bytes;
851 struct regpair rcv_mcast_bytes;
852 struct regpair rcv_bcast_bytes;
853 struct regpair rcv_ucast_pkts;
854 struct regpair rcv_mcast_pkts;
855 struct regpair rcv_bcast_pkts;
858 /* Event Ring Next Page Address */
859 struct event_ring_next_addr {
864 /* Event Ring Element */
865 union event_ring_element {
866 struct event_ring_entry entry;
867 struct event_ring_next_addr next_addr;
870 /* Major and Minor hsi Versions */
871 struct hsi_fp_ver_struct {
876 /* Mstorm non-triggering VF zone */
877 enum malicious_vf_error_id {
878 MALICIOUS_VF_NO_ERROR,
879 VF_PF_CHANNEL_NOT_READY,
880 VF_ZONE_MSG_NOT_VALID,
881 VF_ZONE_FUNC_NOT_ENABLED,
882 ETH_PACKET_TOO_SMALL,
883 ETH_ILLEGAL_VLAN_MODE,
885 ETH_ILLEGAL_INBAND_TAGS,
886 ETH_VLAN_INSERT_AND_INBAND_VLAN,
889 ETH_INSUFFICIENT_BDS,
890 ETH_ILLEGAL_LSO_HDR_NBDS,
893 ETH_ILLEGAL_LSO_HDR_LEN,
894 ETH_INSUFFICIENT_PAYLOAD,
895 ETH_EDPM_OUT_OF_SYNC,
896 ETH_TUNN_IPV6_EXT_NBD_ERR,
897 ETH_CONTROL_PACKET_VIOLATION,
898 MAX_MALICIOUS_VF_ERROR_ID
901 struct mstorm_non_trigger_vf_zone {
902 struct eth_mstorm_per_queue_stat eth_queue_stat;
903 struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
907 struct mstorm_vf_zone {
908 struct mstorm_non_trigger_vf_zone non_trigger;
912 /* personality per PF */
913 enum personality_type {
916 PERSONALITY_RESERVED2,
917 PERSONALITY_RDMA_AND_ETH,
918 PERSONALITY_RESERVED3,
921 PERSONALITY_RESERVED4,
925 /* tunnel configuration */
926 struct pf_start_tunnel_config {
927 u8 set_vxlan_udp_port_flg;
928 u8 set_geneve_udp_port_flg;
930 u8 tx_enable_l2geneve;
931 u8 tx_enable_ipgeneve;
934 u8 tunnel_clss_vxlan;
935 u8 tunnel_clss_l2geneve;
936 u8 tunnel_clss_ipgeneve;
937 u8 tunnel_clss_l2gre;
938 u8 tunnel_clss_ipgre;
939 __le16 vxlan_udp_port;
940 __le16 geneve_udp_port;
943 /* Ramrod data for PF start ramrod */
944 struct pf_start_ramrod_data {
945 struct regpair event_ring_pbl_addr;
946 struct regpair consolid_q_pbl_addr;
947 struct pf_start_tunnel_config tunnel_config;
948 __le16 event_ring_sb_id;
951 u8 event_ring_num_pages;
952 u8 event_ring_sb_index;
957 __le16 log_type_mask;
960 u8 allow_npar_tx_switching;
961 u8 inner_to_outer_pri_map[8];
964 struct hsi_fp_ver_struct hsi_fp_ver;
968 struct protocol_dcb_data {
977 struct pf_update_tunnel_config {
978 u8 update_rx_pf_clss;
979 u8 update_rx_def_ucast_clss;
980 u8 update_rx_def_non_ucast_clss;
981 u8 update_tx_pf_clss;
982 u8 set_vxlan_udp_port_flg;
983 u8 set_geneve_udp_port_flg;
985 u8 tx_enable_l2geneve;
986 u8 tx_enable_ipgeneve;
989 u8 tunnel_clss_vxlan;
990 u8 tunnel_clss_l2geneve;
991 u8 tunnel_clss_ipgeneve;
992 u8 tunnel_clss_l2gre;
993 u8 tunnel_clss_ipgre;
994 __le16 vxlan_udp_port;
995 __le16 geneve_udp_port;
999 struct pf_update_ramrod_data {
1001 u8 update_eth_dcb_data_flag;
1002 u8 update_fcoe_dcb_data_flag;
1003 u8 update_iscsi_dcb_data_flag;
1004 u8 update_roce_dcb_data_flag;
1005 u8 update_rroce_dcb_data_flag;
1006 u8 update_iwarp_dcb_data_flag;
1007 u8 update_mf_vlan_flag;
1008 struct protocol_dcb_data eth_dcb_data;
1009 struct protocol_dcb_data fcoe_dcb_data;
1010 struct protocol_dcb_data iscsi_dcb_data;
1011 struct protocol_dcb_data roce_dcb_data;
1012 struct protocol_dcb_data rroce_dcb_data;
1013 struct protocol_dcb_data iwarp_dcb_data;
1016 struct pf_update_tunnel_config tunnel_config;
1029 /* use to index in hsi_fp_[major|minor]_ver_arr per protocol */
1030 enum protocol_version_array_key {
1033 MAX_PROTOCOL_VERSION_ARRAY_KEY
1036 struct rdma_sent_stats {
1037 struct regpair sent_bytes;
1038 struct regpair sent_pkts;
1041 struct pstorm_non_trigger_vf_zone {
1042 struct eth_pstorm_per_queue_stat eth_queue_stat;
1043 struct rdma_sent_stats rdma_stats;
1046 /* Pstorm VF zone */
1047 struct pstorm_vf_zone {
1048 struct pstorm_non_trigger_vf_zone non_trigger;
1049 struct regpair reserved[7];
1052 /* Ramrod Header of SPQE */
1053 struct ramrod_header {
1060 struct rdma_rcv_stats {
1061 struct regpair rcv_bytes;
1062 struct regpair rcv_pkts;
1065 struct slow_path_element {
1066 struct ramrod_header hdr;
1067 struct regpair data_ptr;
1070 /* Tstorm non-triggering VF zone */
1071 struct tstorm_non_trigger_vf_zone {
1072 struct rdma_rcv_stats rdma_stats;
1075 struct tstorm_per_port_stat {
1076 struct regpair trunc_error_discard;
1077 struct regpair mac_error_discard;
1078 struct regpair mftag_filter_discard;
1079 struct regpair eth_mac_filter_discard;
1080 struct regpair ll2_mac_filter_discard;
1081 struct regpair ll2_conn_disabled_discard;
1082 struct regpair iscsi_irregular_pkt;
1083 struct regpair reserved;
1084 struct regpair roce_irregular_pkt;
1085 struct regpair eth_irregular_pkt;
1086 struct regpair reserved1;
1087 struct regpair preroce_irregular_pkt;
1088 struct regpair eth_gre_tunn_filter_discard;
1089 struct regpair eth_vxlan_tunn_filter_discard;
1090 struct regpair eth_geneve_tunn_filter_discard;
1093 /* Tstorm VF zone */
1094 struct tstorm_vf_zone {
1095 struct tstorm_non_trigger_vf_zone non_trigger;
1098 /* Tunnel classification scheme */
1100 TUNNEL_CLSS_MAC_VLAN = 0,
1101 TUNNEL_CLSS_MAC_VNI,
1102 TUNNEL_CLSS_INNER_MAC_VLAN,
1103 TUNNEL_CLSS_INNER_MAC_VNI,
1104 TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
1108 /* Ustorm non-triggering VF zone */
1109 struct ustorm_non_trigger_vf_zone {
1110 struct eth_ustorm_per_queue_stat eth_queue_stat;
1111 struct regpair vf_pf_msg_addr;
1114 /* Ustorm triggering VF zone */
1115 struct ustorm_trigger_vf_zone {
1120 /* Ustorm VF zone */
1121 struct ustorm_vf_zone {
1122 struct ustorm_non_trigger_vf_zone non_trigger;
1123 struct ustorm_trigger_vf_zone trigger;
1126 /* VF-PF channel data */
1127 struct vf_pf_channel_data {
1134 /* Ramrod data for VF start ramrod */
1135 struct vf_start_ramrod_data {
1141 struct hsi_fp_ver_struct hsi_fp_ver;
1145 /* Ramrod data for VF start ramrod */
1146 struct vf_stop_ramrod_data {
1153 enum vf_zone_size_mode {
1154 VF_ZONE_SIZE_MODE_DEFAULT,
1155 VF_ZONE_SIZE_MODE_DOUBLE,
1156 VF_ZONE_SIZE_MODE_QUAD,
1157 MAX_VF_ZONE_SIZE_MODE
1160 struct atten_status_block {
1168 enum command_type_bit {
1169 IGU_COMMAND_TYPE_NOP = 0,
1170 IGU_COMMAND_TYPE_SET = 1,
1171 MAX_COMMAND_TYPE_BIT
1177 #define DMAE_CMD_SRC_MASK 0x1
1178 #define DMAE_CMD_SRC_SHIFT 0
1179 #define DMAE_CMD_DST_MASK 0x3
1180 #define DMAE_CMD_DST_SHIFT 1
1181 #define DMAE_CMD_C_DST_MASK 0x1
1182 #define DMAE_CMD_C_DST_SHIFT 3
1183 #define DMAE_CMD_CRC_RESET_MASK 0x1
1184 #define DMAE_CMD_CRC_RESET_SHIFT 4
1185 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
1186 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5
1187 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
1188 #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6
1189 #define DMAE_CMD_COMP_FUNC_MASK 0x1
1190 #define DMAE_CMD_COMP_FUNC_SHIFT 7
1191 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1
1192 #define DMAE_CMD_COMP_WORD_EN_SHIFT 8
1193 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1
1194 #define DMAE_CMD_COMP_CRC_EN_SHIFT 9
1195 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
1196 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
1197 #define DMAE_CMD_RESERVED1_MASK 0x1
1198 #define DMAE_CMD_RESERVED1_SHIFT 13
1199 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
1200 #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14
1201 #define DMAE_CMD_ERR_HANDLING_MASK 0x3
1202 #define DMAE_CMD_ERR_HANDLING_SHIFT 16
1203 #define DMAE_CMD_PORT_ID_MASK 0x3
1204 #define DMAE_CMD_PORT_ID_SHIFT 18
1205 #define DMAE_CMD_SRC_PF_ID_MASK 0xF
1206 #define DMAE_CMD_SRC_PF_ID_SHIFT 20
1207 #define DMAE_CMD_DST_PF_ID_MASK 0xF
1208 #define DMAE_CMD_DST_PF_ID_SHIFT 24
1209 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1
1210 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
1211 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1
1212 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
1213 #define DMAE_CMD_RESERVED2_MASK 0x3
1214 #define DMAE_CMD_RESERVED2_SHIFT 30
1221 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF
1222 #define DMAE_CMD_SRC_VF_ID_SHIFT 0
1223 #define DMAE_CMD_DST_VF_ID_MASK 0xFF
1224 #define DMAE_CMD_DST_VF_ID_SHIFT 8
1225 __le32 comp_addr_lo;
1226 __le32 comp_addr_hi;
1238 enum dmae_cmd_comp_crc_en_enum {
1239 dmae_cmd_comp_crc_disabled,
1240 dmae_cmd_comp_crc_enabled,
1241 MAX_DMAE_CMD_COMP_CRC_EN_ENUM
1244 enum dmae_cmd_comp_func_enum {
1245 dmae_cmd_comp_func_to_src,
1246 dmae_cmd_comp_func_to_dst,
1247 MAX_DMAE_CMD_COMP_FUNC_ENUM
1250 enum dmae_cmd_comp_word_en_enum {
1251 dmae_cmd_comp_word_disabled,
1252 dmae_cmd_comp_word_enabled,
1253 MAX_DMAE_CMD_COMP_WORD_EN_ENUM
1256 enum dmae_cmd_c_dst_enum {
1257 dmae_cmd_c_dst_pcie,
1259 MAX_DMAE_CMD_C_DST_ENUM
1262 enum dmae_cmd_dst_enum {
1263 dmae_cmd_dst_none_0,
1266 dmae_cmd_dst_none_3,
1267 MAX_DMAE_CMD_DST_ENUM
1270 enum dmae_cmd_error_handling_enum {
1271 dmae_cmd_error_handling_send_regular_comp,
1272 dmae_cmd_error_handling_send_comp_with_err,
1273 dmae_cmd_error_handling_dont_send_comp,
1274 MAX_DMAE_CMD_ERROR_HANDLING_ENUM
1277 enum dmae_cmd_src_enum {
1280 MAX_DMAE_CMD_SRC_ENUM
1283 /* IGU cleanup command */
1284 struct igu_cleanup {
1285 __le32 sb_id_and_flags;
1286 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
1287 #define IGU_CLEANUP_RESERVED0_SHIFT 0
1288 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1
1289 #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27
1290 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
1291 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
1292 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
1293 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
1297 /* IGU firmware driver command */
1299 struct igu_prod_cons_update prod_cons_update;
1300 struct igu_cleanup cleanup;
1303 /* IGU firmware driver command */
1304 struct igu_command_reg_ctrl {
1306 __le16 igu_command_reg_ctrl_fields;
1307 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
1308 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
1309 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
1310 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12
1311 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
1312 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
1315 /* IGU mapping line structure */
1316 struct igu_mapping_line {
1317 __le32 igu_mapping_line_fields;
1318 #define IGU_MAPPING_LINE_VALID_MASK 0x1
1319 #define IGU_MAPPING_LINE_VALID_SHIFT 0
1320 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
1321 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1
1322 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
1323 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
1324 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1
1325 #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17
1326 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
1327 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18
1328 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
1329 #define IGU_MAPPING_LINE_RESERVED_SHIFT 24
1332 /* IGU MSIX line structure */
1333 struct igu_msix_vector {
1334 struct regpair address;
1336 __le32 msix_vector_fields;
1337 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
1338 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
1339 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
1340 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1
1341 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
1342 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
1343 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
1344 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
1347 struct mstorm_core_conn_ag_ctx {
1351 #define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1352 #define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1353 #define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1354 #define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1355 #define MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1356 #define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1357 #define MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1358 #define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1359 #define MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1360 #define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1362 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1363 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1364 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1365 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1366 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1367 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1368 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1369 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1370 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1371 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1372 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1373 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1374 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1375 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1376 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1377 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1384 /* per encapsulation type enabling flags */
1385 struct prs_reg_encapsulation_type_en {
1387 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
1388 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
1389 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
1390 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1
1391 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
1392 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2
1393 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
1394 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3
1395 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
1396 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
1397 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
1398 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5
1399 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
1400 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6
1403 enum pxp_tph_st_hint {
1405 TPH_ST_HINT_REQUESTER,
1407 TPH_ST_HINT_TARGET_PRIO,
1411 /* QM hardware structure of enable bypass credit mask */
1412 struct qm_rf_bypass_mask {
1414 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
1415 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
1416 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
1417 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
1418 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
1419 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2
1420 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
1421 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3
1422 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
1423 #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4
1424 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
1425 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5
1426 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
1427 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6
1428 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
1429 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
1432 /* QM hardware structure of opportunistic credit mask */
1433 struct qm_rf_opportunistic_mask {
1435 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
1436 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
1437 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
1438 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1
1439 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
1440 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2
1441 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
1442 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3
1443 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
1444 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4
1445 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
1446 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5
1447 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
1448 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6
1449 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
1450 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7
1451 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
1452 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
1453 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
1454 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9
1457 /* QM hardware structure of QM map memory */
1458 struct qm_rf_pq_map {
1460 #define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1
1461 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0
1462 #define QM_RF_PQ_MAP_RL_ID_MASK 0xFF
1463 #define QM_RF_PQ_MAP_RL_ID_SHIFT 1
1464 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF
1465 #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9
1466 #define QM_RF_PQ_MAP_VOQ_MASK 0x1F
1467 #define QM_RF_PQ_MAP_VOQ_SHIFT 18
1468 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3
1469 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
1470 #define QM_RF_PQ_MAP_RL_VALID_MASK 0x1
1471 #define QM_RF_PQ_MAP_RL_VALID_SHIFT 25
1472 #define QM_RF_PQ_MAP_RESERVED_MASK 0x3F
1473 #define QM_RF_PQ_MAP_RESERVED_SHIFT 26
1476 /* Completion params for aggregated interrupt completion */
1477 struct sdm_agg_int_comp_params {
1479 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
1480 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
1481 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
1482 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
1483 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
1484 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7
1487 /* SDM operation gen command (generate aggregative interrupt) */
1490 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF
1491 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1492 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF
1493 #define SDM_OP_GEN_COMP_TYPE_SHIFT 16
1494 #define SDM_OP_GEN_RESERVED_MASK 0xFFF
1495 #define SDM_OP_GEN_RESERVED_SHIFT 20
1498 struct ystorm_core_conn_ag_ctx {
1502 #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1503 #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1504 #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1505 #define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1506 #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1507 #define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1508 #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1509 #define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1510 #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1511 #define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1513 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1514 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1515 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1516 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1517 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1518 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1519 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1520 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1521 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1522 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1523 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1524 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1525 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1526 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1527 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1528 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1542 /****************************************/
1543 /* Debug Tools HSI constants and macros */
1544 /****************************************/
1547 GRCBASE_GRC = 0x50000,
1548 GRCBASE_MISCS = 0x9000,
1549 GRCBASE_MISC = 0x8000,
1550 GRCBASE_DBU = 0xa000,
1551 GRCBASE_PGLUE_B = 0x2a8000,
1552 GRCBASE_CNIG = 0x218000,
1553 GRCBASE_CPMU = 0x30000,
1554 GRCBASE_NCSI = 0x40000,
1555 GRCBASE_OPTE = 0x53000,
1556 GRCBASE_BMB = 0x540000,
1557 GRCBASE_PCIE = 0x54000,
1558 GRCBASE_MCP = 0xe00000,
1559 GRCBASE_MCP2 = 0x52000,
1560 GRCBASE_PSWHST = 0x2a0000,
1561 GRCBASE_PSWHST2 = 0x29e000,
1562 GRCBASE_PSWRD = 0x29c000,
1563 GRCBASE_PSWRD2 = 0x29d000,
1564 GRCBASE_PSWWR = 0x29a000,
1565 GRCBASE_PSWWR2 = 0x29b000,
1566 GRCBASE_PSWRQ = 0x280000,
1567 GRCBASE_PSWRQ2 = 0x240000,
1568 GRCBASE_PGLCS = 0x0,
1569 GRCBASE_DMAE = 0xc000,
1570 GRCBASE_PTU = 0x560000,
1571 GRCBASE_TCM = 0x1180000,
1572 GRCBASE_MCM = 0x1200000,
1573 GRCBASE_UCM = 0x1280000,
1574 GRCBASE_XCM = 0x1000000,
1575 GRCBASE_YCM = 0x1080000,
1576 GRCBASE_PCM = 0x1100000,
1577 GRCBASE_QM = 0x2f0000,
1578 GRCBASE_TM = 0x2c0000,
1579 GRCBASE_DORQ = 0x100000,
1580 GRCBASE_BRB = 0x340000,
1581 GRCBASE_SRC = 0x238000,
1582 GRCBASE_PRS = 0x1f0000,
1583 GRCBASE_TSDM = 0xfb0000,
1584 GRCBASE_MSDM = 0xfc0000,
1585 GRCBASE_USDM = 0xfd0000,
1586 GRCBASE_XSDM = 0xf80000,
1587 GRCBASE_YSDM = 0xf90000,
1588 GRCBASE_PSDM = 0xfa0000,
1589 GRCBASE_TSEM = 0x1700000,
1590 GRCBASE_MSEM = 0x1800000,
1591 GRCBASE_USEM = 0x1900000,
1592 GRCBASE_XSEM = 0x1400000,
1593 GRCBASE_YSEM = 0x1500000,
1594 GRCBASE_PSEM = 0x1600000,
1595 GRCBASE_RSS = 0x238800,
1596 GRCBASE_TMLD = 0x4d0000,
1597 GRCBASE_MULD = 0x4e0000,
1598 GRCBASE_YULD = 0x4c8000,
1599 GRCBASE_XYLD = 0x4c0000,
1600 GRCBASE_PRM = 0x230000,
1601 GRCBASE_PBF_PB1 = 0xda0000,
1602 GRCBASE_PBF_PB2 = 0xda4000,
1603 GRCBASE_RPB = 0x23c000,
1604 GRCBASE_BTB = 0xdb0000,
1605 GRCBASE_PBF = 0xd80000,
1606 GRCBASE_RDIF = 0x300000,
1607 GRCBASE_TDIF = 0x310000,
1608 GRCBASE_CDU = 0x580000,
1609 GRCBASE_CCFC = 0x2e0000,
1610 GRCBASE_TCFC = 0x2d0000,
1611 GRCBASE_IGU = 0x180000,
1612 GRCBASE_CAU = 0x1c0000,
1613 GRCBASE_UMAC = 0x51000,
1614 GRCBASE_XMAC = 0x210000,
1615 GRCBASE_DBG = 0x10000,
1616 GRCBASE_NIG = 0x500000,
1617 GRCBASE_WOL = 0x600000,
1618 GRCBASE_BMBN = 0x610000,
1619 GRCBASE_IPC = 0x20000,
1620 GRCBASE_NWM = 0x800000,
1621 GRCBASE_NWS = 0x700000,
1622 GRCBASE_MS = 0x6a0000,
1623 GRCBASE_PHY_PCIE = 0x620000,
1624 GRCBASE_LED = 0x6b8000,
1625 GRCBASE_MISC_AEU = 0x8000,
1626 GRCBASE_BAR0_MAP = 0x1c00000,
1714 /* binary debug buffer types */
1715 enum bin_dbg_buffer_type {
1716 BIN_BUF_DBG_MODE_TREE,
1717 BIN_BUF_DBG_DUMP_REG,
1718 BIN_BUF_DBG_DUMP_MEM,
1719 BIN_BUF_DBG_IDLE_CHK_REGS,
1720 BIN_BUF_DBG_IDLE_CHK_IMMS,
1721 BIN_BUF_DBG_IDLE_CHK_RULES,
1722 BIN_BUF_DBG_IDLE_CHK_PARSING_DATA,
1723 BIN_BUF_DBG_ATTN_BLOCKS,
1724 BIN_BUF_DBG_ATTN_REGS,
1725 BIN_BUF_DBG_ATTN_INDEXES,
1726 BIN_BUF_DBG_ATTN_NAME_OFFSETS,
1727 BIN_BUF_DBG_PARSING_STRINGS,
1728 MAX_BIN_DBG_BUFFER_TYPE
1732 /* Attention bit mapping */
1733 struct dbg_attn_bit_mapping {
1735 #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF
1736 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0
1737 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1
1738 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15
1741 /* Attention block per-type data */
1742 struct dbg_attn_block_type_data {
1743 __le16 names_offset;
1750 /* Block attentions */
1751 struct dbg_attn_block {
1752 struct dbg_attn_block_type_data per_type_data[2];
1755 /* Attention register result */
1756 struct dbg_attn_reg_result {
1758 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF
1759 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0
1760 #define DBG_ATTN_REG_RESULT_NUM_ATTN_IDX_MASK 0xFF
1761 #define DBG_ATTN_REG_RESULT_NUM_ATTN_IDX_SHIFT 24
1762 __le16 attn_idx_offset;
1768 /* Attention block result */
1769 struct dbg_attn_block_result {
1772 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3
1773 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0
1774 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F
1775 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2
1776 __le16 names_offset;
1777 struct dbg_attn_reg_result reg_results[15];
1781 struct dbg_mode_hdr {
1783 #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1
1784 #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0
1785 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF
1786 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1
1789 /* Attention register */
1790 struct dbg_attn_reg {
1791 struct dbg_mode_hdr mode;
1792 __le16 attn_idx_offset;
1794 #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF
1795 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0
1796 #define DBG_ATTN_REG_NUM_ATTN_IDX_MASK 0xFF
1797 #define DBG_ATTN_REG_NUM_ATTN_IDX_SHIFT 24
1798 __le32 sts_clr_address;
1799 __le32 mask_address;
1802 /* attention types */
1803 enum dbg_attn_type {
1804 ATTN_TYPE_INTERRUPT,
1809 /* condition header for registers dump */
1810 struct dbg_dump_cond_hdr {
1811 struct dbg_mode_hdr mode; /* Mode header */
1812 u8 block_id; /* block ID */
1813 u8 data_size; /* size in dwords of the data following this header */
1816 /* memory data for registers dump */
1817 struct dbg_dump_mem {
1819 #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF
1820 #define DBG_DUMP_MEM_ADDRESS_SHIFT 0
1821 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF
1822 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
1824 #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF
1825 #define DBG_DUMP_MEM_LENGTH_SHIFT 0
1826 #define DBG_DUMP_MEM_RESERVED_MASK 0xFF
1827 #define DBG_DUMP_MEM_RESERVED_SHIFT 24
1830 /* register data for registers dump */
1831 struct dbg_dump_reg {
1833 #define DBG_DUMP_REG_ADDRESS_MASK 0xFFFFFF /* register address (in dwords) */
1834 #define DBG_DUMP_REG_ADDRESS_SHIFT 0
1835 #define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */
1836 #define DBG_DUMP_REG_LENGTH_SHIFT 24
1839 /* split header for registers dump */
1840 struct dbg_dump_split_hdr {
1842 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF
1843 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0
1844 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF
1845 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24
1848 /* condition header for idle check */
1849 struct dbg_idle_chk_cond_hdr {
1850 struct dbg_mode_hdr mode; /* Mode header */
1851 __le16 data_size; /* size in dwords of the data following this header */
1854 /* Idle Check condition register */
1855 struct dbg_idle_chk_cond_reg {
1857 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0xFFFFFF
1858 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0
1859 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF
1860 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24
1861 __le16 num_entries; /* number of registers entries to check */
1862 u8 entry_size; /* size of registers entry (in dwords) */
1863 u8 start_entry; /* index of the first entry to check */
1866 /* Idle Check info register */
1867 struct dbg_idle_chk_info_reg {
1869 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0xFFFFFF
1870 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0
1871 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF
1872 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24
1873 __le16 size; /* register size in dwords */
1874 struct dbg_mode_hdr mode; /* Mode header */
1877 /* Idle Check register */
1878 union dbg_idle_chk_reg {
1879 struct dbg_idle_chk_cond_reg cond_reg; /* condition register */
1880 struct dbg_idle_chk_info_reg info_reg; /* info register */
1883 /* Idle Check result header */
1884 struct dbg_idle_chk_result_hdr {
1885 __le16 rule_id; /* Failing rule index */
1886 __le16 mem_entry_id; /* Failing memory entry index */
1887 u8 num_dumped_cond_regs; /* number of dumped condition registers */
1888 u8 num_dumped_info_regs; /* number of dumped condition registers */
1889 u8 severity; /* from dbg_idle_chk_severity_types enum */
1893 /* Idle Check result register header */
1894 struct dbg_idle_chk_result_reg_hdr {
1896 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1
1897 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
1898 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F
1899 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
1900 u8 start_entry; /* index of the first checked entry */
1901 __le16 size; /* register size in dwords */
1904 /* Idle Check rule */
1905 struct dbg_idle_chk_rule {
1906 __le16 rule_id; /* Idle Check rule ID */
1907 u8 severity; /* value from dbg_idle_chk_severity_types enum */
1908 u8 cond_id; /* Condition ID */
1909 u8 num_cond_regs; /* number of condition registers */
1910 u8 num_info_regs; /* number of info registers */
1911 u8 num_imms; /* number of immediates in the condition */
1913 __le16 reg_offset; /* offset of this rules registers in the idle check
1914 * register array (in dbg_idle_chk_reg units).
1916 __le16 imm_offset; /* offset of this rules immediate values in the
1917 * immediate values array (in dwords).
1921 /* Idle Check rule parsing data */
1922 struct dbg_idle_chk_rule_parsing_data {
1924 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1
1925 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
1926 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF
1927 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
1930 /* idle check severity types */
1931 enum dbg_idle_chk_severity_types {
1932 /* idle check failure should cause an error */
1933 IDLE_CHK_SEVERITY_ERROR,
1934 /* idle check failure should cause an error only if theres no traffic */
1935 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
1936 /* idle check failure should cause a warning */
1937 IDLE_CHK_SEVERITY_WARNING,
1938 MAX_DBG_IDLE_CHK_SEVERITY_TYPES
1941 /* Debug Bus block data */
1942 struct dbg_bus_block_data {
1943 u8 enabled; /* Indicates if the block is enabled for recording (0/1) */
1944 u8 hw_id; /* HW ID associated with the block */
1945 u8 line_num; /* Debug line number to select */
1946 u8 right_shift; /* Number of units to right the debug data (0-3) */
1947 u8 cycle_en; /* 4-bit value: bit i set -> unit i is enabled. */
1948 u8 force_valid; /* 4-bit value: bit i set -> unit i is forced valid. */
1949 u8 force_frame; /* 4-bit value: bit i set -> unit i frame bit is forced.
1954 /* Debug Bus Clients */
1955 enum dbg_bus_clients {
1956 DBG_BUS_CLIENT_RBCN,
1957 DBG_BUS_CLIENT_RBCP,
1958 DBG_BUS_CLIENT_RBCR,
1959 DBG_BUS_CLIENT_RBCT,
1960 DBG_BUS_CLIENT_RBCU,
1961 DBG_BUS_CLIENT_RBCF,
1962 DBG_BUS_CLIENT_RBCX,
1963 DBG_BUS_CLIENT_RBCS,
1964 DBG_BUS_CLIENT_RBCH,
1965 DBG_BUS_CLIENT_RBCZ,
1966 DBG_BUS_CLIENT_OTHER_ENGINE,
1967 DBG_BUS_CLIENT_TIMESTAMP,
1969 DBG_BUS_CLIENT_RBCY,
1970 DBG_BUS_CLIENT_RBCQ,
1971 DBG_BUS_CLIENT_RBCM,
1972 DBG_BUS_CLIENT_RBCB,
1973 DBG_BUS_CLIENT_RBCW,
1974 DBG_BUS_CLIENT_RBCV,
1978 /* Debug Bus memory address */
1979 struct dbg_bus_mem_addr {
1984 /* Debug Bus PCI buffer data */
1985 struct dbg_bus_pci_buf_data {
1986 struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */
1987 struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */
1988 __le32 size; /* PCI buffer size in bytes */
1991 /* Debug Bus Storm EID range filter params */
1992 struct dbg_bus_storm_eid_range_params {
1993 u8 min; /* Minimal event ID to filter on */
1994 u8 max; /* Maximal event ID to filter on */
1997 /* Debug Bus Storm EID mask filter params */
1998 struct dbg_bus_storm_eid_mask_params {
1999 u8 val; /* Event ID value */
2000 u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */
2003 /* Debug Bus Storm EID filter params */
2004 union dbg_bus_storm_eid_params {
2005 struct dbg_bus_storm_eid_range_params range;
2006 struct dbg_bus_storm_eid_mask_params mask;
2009 /* Debug Bus Storm data */
2010 struct dbg_bus_storm_data {
2017 u8 eid_range_not_mask;
2019 union dbg_bus_storm_eid_params eid_filter_params;
2024 /* Debug Bus data */
2025 struct dbg_bus_data {
2026 __le32 app_version; /* The tools version number of the application */
2027 u8 state; /* The current debug bus state */
2028 u8 hw_dwords; /* HW dwords per cycle */
2029 u8 next_hw_id; /* Next HW ID to be associated with an input */
2030 u8 num_enabled_blocks; /* Number of blocks enabled for recording */
2031 u8 num_enabled_storms; /* Number of Storms enabled for recording */
2032 u8 target; /* Output target */
2033 u8 next_trigger_state; /* ID of next trigger state to be added */
2034 u8 next_constraint_id; /* ID of next filter/trigger constraint to be
2037 u8 one_shot_en; /* Indicates if one-shot mode is enabled (0/1) */
2038 u8 grc_input_en; /* Indicates if GRC recording is enabled (0/1) */
2039 u8 timestamp_input_en; /* Indicates if timestamp recording is enabled
2042 u8 filter_en; /* Indicates if the recording filter is enabled (0/1) */
2043 u8 trigger_en; /* Indicates if the recording trigger is enabled (0/1) */
2044 u8 adding_filter; /* If true, the next added constraint belong to the
2045 * filter. Otherwise, it belongs to the last added
2046 * trigger state. Valid only if either filter or
2047 * triggers are enabled.
2049 u8 filter_pre_trigger; /* Indicates if the recording filter should be
2050 * applied before the trigger. Valid only if both
2051 * filter and trigger are enabled (0/1).
2053 u8 filter_post_trigger; /* Indicates if the recording filter should be
2054 * applied after the trigger. Valid only if both
2055 * filter and trigger are enabled (0/1).
2057 u8 unify_inputs; /* If true, all inputs are associated with HW ID 0.
2058 * Otherwise, each input is assigned a different HW ID
2061 u8 rcv_from_other_engine; /* Indicates if the other engine sends it NW
2062 * recording to this engine (0/1).
2064 struct dbg_bus_pci_buf_data pci_buf; /* Debug Bus PCI buffer data. Valid
2065 * only when the target is
2066 * DBG_BUS_TARGET_ID_PCI.
2069 struct dbg_bus_block_data blocks[80];/* Debug Bus data for each block */
2070 struct dbg_bus_storm_data storms[6]; /* Debug Bus data for each block */
2073 /* Debug bus frame modes */
2074 enum dbg_bus_frame_modes {
2075 DBG_BUS_FRAME_MODE_0HW_4ST = 0, /* 0 HW dwords, 4 Storm dwords */
2076 DBG_BUS_FRAME_MODE_4HW_0ST = 3, /* 4 HW dwords, 0 Storm dwords */
2077 DBG_BUS_FRAME_MODE_8HW_0ST = 4, /* 8 HW dwords, 0 Storm dwords */
2078 MAX_DBG_BUS_FRAME_MODES
2081 /* Debug bus states */
2082 enum dbg_bus_states {
2083 DBG_BUS_STATE_IDLE, /* debug bus idle state (not recording) */
2084 DBG_BUS_STATE_READY, /* debug bus is ready for configuration and
2087 DBG_BUS_STATE_RECORDING, /* debug bus is currently recording */
2088 DBG_BUS_STATE_STOPPED, /* debug bus recording has stopped */
2092 /* Debug bus target IDs */
2093 enum dbg_bus_targets {
2094 /* records debug bus to DBG block internal buffer */
2095 DBG_BUS_TARGET_ID_INT_BUF,
2096 /* records debug bus to the NW */
2097 DBG_BUS_TARGET_ID_NIG,
2098 /* records debug bus to a PCI buffer */
2099 DBG_BUS_TARGET_ID_PCI,
2104 struct dbg_grc_data {
2105 __le32 param_val[40]; /* Value of each GRC parameter. Array size must
2106 * match the enum dbg_grc_params.
2108 u8 param_set_by_user[40]; /* Indicates for each GRC parameter if it was
2109 * set by the user (0/1). Array size must
2110 * match the enum dbg_grc_params.
2114 /* Debug GRC params */
2115 enum dbg_grc_params {
2116 DBG_GRC_PARAM_DUMP_TSTORM, /* dump Tstorm memories (0/1) */
2117 DBG_GRC_PARAM_DUMP_MSTORM, /* dump Mstorm memories (0/1) */
2118 DBG_GRC_PARAM_DUMP_USTORM, /* dump Ustorm memories (0/1) */
2119 DBG_GRC_PARAM_DUMP_XSTORM, /* dump Xstorm memories (0/1) */
2120 DBG_GRC_PARAM_DUMP_YSTORM, /* dump Ystorm memories (0/1) */
2121 DBG_GRC_PARAM_DUMP_PSTORM, /* dump Pstorm memories (0/1) */
2122 DBG_GRC_PARAM_DUMP_REGS, /* dump non-memory registers (0/1) */
2123 DBG_GRC_PARAM_DUMP_RAM, /* dump Storm internal RAMs (0/1) */
2124 DBG_GRC_PARAM_DUMP_PBUF, /* dump Storm passive buffer (0/1) */
2125 DBG_GRC_PARAM_DUMP_IOR, /* dump Storm IORs (0/1) */
2126 DBG_GRC_PARAM_DUMP_VFC, /* dump VFC memories (0/1) */
2127 DBG_GRC_PARAM_DUMP_CM_CTX, /* dump CM contexts (0/1) */
2128 DBG_GRC_PARAM_DUMP_PXP, /* dump PXP memories (0/1) */
2129 DBG_GRC_PARAM_DUMP_RSS, /* dump RSS memories (0/1) */
2130 DBG_GRC_PARAM_DUMP_CAU, /* dump CAU memories (0/1) */
2131 DBG_GRC_PARAM_DUMP_QM, /* dump QM memories (0/1) */
2132 DBG_GRC_PARAM_DUMP_MCP, /* dump MCP memories (0/1) */
2133 DBG_GRC_PARAM_RESERVED, /* reserved */
2134 DBG_GRC_PARAM_DUMP_CFC, /* dump CFC memories (0/1) */
2135 DBG_GRC_PARAM_DUMP_IGU, /* dump IGU memories (0/1) */
2136 DBG_GRC_PARAM_DUMP_BRB, /* dump BRB memories (0/1) */
2137 DBG_GRC_PARAM_DUMP_BTB, /* dump BTB memories (0/1) */
2138 DBG_GRC_PARAM_DUMP_BMB, /* dump BMB memories (0/1) */
2139 DBG_GRC_PARAM_DUMP_NIG, /* dump NIG memories (0/1) */
2140 DBG_GRC_PARAM_DUMP_MULD, /* dump MULD memories (0/1) */
2141 DBG_GRC_PARAM_DUMP_PRS, /* dump PRS memories (0/1) */
2142 DBG_GRC_PARAM_DUMP_DMAE, /* dump PRS memories (0/1) */
2143 DBG_GRC_PARAM_DUMP_TM, /* dump TM (timers) memories (0/1) */
2144 DBG_GRC_PARAM_DUMP_SDM, /* dump SDM memories (0/1) */
2145 DBG_GRC_PARAM_DUMP_DIF, /* dump DIF memories (0/1) */
2146 DBG_GRC_PARAM_DUMP_STATIC, /* dump static debug data (0/1) */
2147 DBG_GRC_PARAM_UNSTALL, /* un-stall Storms after dump (0/1) */
2148 DBG_GRC_PARAM_NUM_LCIDS, /* number of LCIDs (0..320) */
2149 DBG_GRC_PARAM_NUM_LTIDS, /* number of LTIDs (0..320) */
2150 /* preset: exclude all memories from dump (1 only) */
2151 DBG_GRC_PARAM_EXCLUDE_ALL,
2152 /* preset: include memories for crash dump (1 only) */
2153 DBG_GRC_PARAM_CRASH,
2154 /* perform dump only if MFW is responding (0/1) */
2155 DBG_GRC_PARAM_PARITY_SAFE,
2156 DBG_GRC_PARAM_DUMP_CM, /* dump CM memories (0/1) */
2157 DBG_GRC_PARAM_DUMP_PHY, /* dump PHY memories (0/1) */
2161 /* Debug reset registers */
2162 enum dbg_reset_regs {
2163 DBG_RESET_REG_MISCS_PL_UA,
2164 DBG_RESET_REG_MISCS_PL_HV,
2165 DBG_RESET_REG_MISCS_PL_HV_2,
2166 DBG_RESET_REG_MISC_PL_UA,
2167 DBG_RESET_REG_MISC_PL_HV,
2168 DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
2169 DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
2170 DBG_RESET_REG_MISC_PL_PDA_VAUX,
2174 /* Debug status codes */
2177 DBG_STATUS_APP_VERSION_NOT_SET,
2178 DBG_STATUS_UNSUPPORTED_APP_VERSION,
2179 DBG_STATUS_DBG_BLOCK_NOT_RESET,
2180 DBG_STATUS_INVALID_ARGS,
2181 DBG_STATUS_OUTPUT_ALREADY_SET,
2182 DBG_STATUS_INVALID_PCI_BUF_SIZE,
2183 DBG_STATUS_PCI_BUF_ALLOC_FAILED,
2184 DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
2185 DBG_STATUS_TOO_MANY_INPUTS,
2186 DBG_STATUS_INPUT_OVERLAP,
2187 DBG_STATUS_HW_ONLY_RECORDING,
2188 DBG_STATUS_STORM_ALREADY_ENABLED,
2189 DBG_STATUS_STORM_NOT_ENABLED,
2190 DBG_STATUS_BLOCK_ALREADY_ENABLED,
2191 DBG_STATUS_BLOCK_NOT_ENABLED,
2192 DBG_STATUS_NO_INPUT_ENABLED,
2193 DBG_STATUS_NO_FILTER_TRIGGER_64B,
2194 DBG_STATUS_FILTER_ALREADY_ENABLED,
2195 DBG_STATUS_TRIGGER_ALREADY_ENABLED,
2196 DBG_STATUS_TRIGGER_NOT_ENABLED,
2197 DBG_STATUS_CANT_ADD_CONSTRAINT,
2198 DBG_STATUS_TOO_MANY_TRIGGER_STATES,
2199 DBG_STATUS_TOO_MANY_CONSTRAINTS,
2200 DBG_STATUS_RECORDING_NOT_STARTED,
2201 DBG_STATUS_DATA_DIDNT_TRIGGER,
2202 DBG_STATUS_NO_DATA_RECORDED,
2203 DBG_STATUS_DUMP_BUF_TOO_SMALL,
2204 DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
2205 DBG_STATUS_UNKNOWN_CHIP,
2206 DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
2207 DBG_STATUS_BLOCK_IN_RESET,
2208 DBG_STATUS_INVALID_TRACE_SIGNATURE,
2209 DBG_STATUS_INVALID_NVRAM_BUNDLE,
2210 DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
2211 DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
2212 DBG_STATUS_NVRAM_READ_FAILED,
2213 DBG_STATUS_IDLE_CHK_PARSE_FAILED,
2214 DBG_STATUS_MCP_TRACE_BAD_DATA,
2215 DBG_STATUS_MCP_TRACE_NO_META,
2216 DBG_STATUS_MCP_COULD_NOT_HALT,
2217 DBG_STATUS_MCP_COULD_NOT_RESUME,
2218 DBG_STATUS_DMAE_FAILED,
2219 DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
2220 DBG_STATUS_IGU_FIFO_BAD_DATA,
2221 DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
2222 DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
2223 DBG_STATUS_REG_FIFO_BAD_DATA,
2224 DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
2225 DBG_STATUS_DBG_ARRAY_NOT_SET,
2226 DBG_STATUS_MULTI_BLOCKS_WITH_FILTER,
2230 /* Debug Storms IDs */
2241 /* Idle Check data */
2242 struct idle_chk_data {
2243 __le32 buf_size; /* Idle check buffer size in dwords */
2244 u8 buf_size_set; /* Indicates if the idle check buffer size was set
2251 /* Debug Tools data (per HW function) */
2252 struct dbg_tools_data {
2253 struct dbg_grc_data grc; /* GRC Dump data */
2254 struct dbg_bus_data bus; /* Debug Bus data */
2255 struct idle_chk_data idle_chk; /* Idle Check data */
2256 u8 mode_enable[40]; /* Indicates if a mode is enabled (0/1) */
2257 u8 block_in_reset[80]; /* Indicates if a block is in reset state (0/1).
2259 u8 chip_id; /* Chip ID (from enum chip_ids) */
2260 u8 platform_id; /* Platform ID (from enum platform_ids) */
2261 u8 initialized; /* Indicates if the data was initialized */
2265 /********************************/
2266 /* HSI Init Functions constants */
2267 /********************************/
2269 /* Number of VLAN priorities */
2270 #define NUM_OF_VLAN_PRIORITIES 8
2272 struct init_brb_ram_req {
2273 __le32 guranteed_per_tc;
2274 __le32 headroom_per_tc;
2275 __le32 min_pkt_size;
2276 __le32 max_ports_per_engine;
2277 u8 num_active_tcs[MAX_NUM_PORTS];
2280 struct init_ets_tc_req {
2286 struct init_ets_req {
2288 struct init_ets_tc_req tc_req[NUM_OF_TCS];
2291 struct init_nig_lb_rl_req {
2295 __le16 tc_rate[NUM_OF_PHYS_TCS];
2298 struct init_nig_pri_tc_map_entry {
2303 struct init_nig_pri_tc_map_req {
2304 struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
2307 struct init_qm_port_params {
2310 __le16 num_pbf_cmd_lines;
2311 __le16 num_btb_blocks;
2315 /* QM per-PQ init parameters */
2316 struct init_qm_pq_params {
2323 /* QM per-vport init parameters */
2324 struct init_qm_vport_params {
2327 __le16 first_tx_pq_id[NUM_OF_TCS];
2330 /**************************************/
2331 /* Init Tool HSI constants and macros */
2332 /**************************************/
2334 /* Width of GRC address in bits (addresses are specified in dwords) */
2335 #define GRC_ADDR_BITS 23
2336 #define MAX_GRC_ADDR (BIT(GRC_ADDR_BITS) - 1)
2338 /* indicates an init that should be applied to any phase ID */
2339 #define ANY_PHASE_ID 0xffff
2341 /* Max size in dwords of a zipped array */
2342 #define MAX_ZIPPED_SIZE 8192
2344 struct fw_asserts_ram_section {
2345 __le16 section_ram_line_offset;
2346 __le16 section_ram_line_size;
2347 u8 list_dword_offset;
2348 u8 list_element_dword_size;
2349 u8 list_num_elements;
2350 u8 list_next_index_dword_offset;
2354 u8 major; /* Firmware major version number */
2355 u8 minor; /* Firmware minor version number */
2356 u8 rev; /* Firmware revision version number */
2357 u8 eng; /* Firmware engineering version number (for bootleg versions) */
2360 struct fw_ver_info {
2361 __le16 tools_ver; /* Tools version number */
2362 u8 image_id; /* FW image ID (e.g. main) */
2364 struct fw_ver_num num; /* FW version number */
2365 __le32 timestamp; /* FW Timestamp in unix time (sec. since 1970) */
2370 struct fw_ver_info ver;
2371 struct fw_asserts_ram_section fw_asserts_section;
2374 struct fw_info_location {
2391 MODE_PORTS_PER_ENG_1,
2392 MODE_PORTS_PER_ENG_2,
2393 MODE_PORTS_PER_ENG_4,
2409 enum init_split_types {
2415 MAX_INIT_SPLIT_TYPES
2418 /* Binary buffer header */
2419 struct bin_buffer_hdr {
2424 /* binary init buffer types */
2425 enum bin_init_buffer_type {
2426 BIN_BUF_INIT_FW_VER_INFO,
2429 BIN_BUF_INIT_MODE_TREE,
2431 MAX_BIN_INIT_BUFFER_TYPE
2434 /* init array header: raw */
2435 struct init_array_raw_hdr {
2437 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
2438 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
2439 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
2440 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
2443 /* init array header: standard */
2444 struct init_array_standard_hdr {
2446 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
2447 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
2448 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
2449 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
2452 /* init array header: zipped */
2453 struct init_array_zipped_hdr {
2455 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
2456 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
2457 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
2458 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
2461 /* init array header: pattern */
2462 struct init_array_pattern_hdr {
2464 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
2465 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
2466 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
2467 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
2468 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
2469 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
2472 /* init array header union */
2473 union init_array_hdr {
2474 struct init_array_raw_hdr raw;
2475 struct init_array_standard_hdr standard;
2476 struct init_array_zipped_hdr zipped;
2477 struct init_array_pattern_hdr pattern;
2480 /* init array types */
2481 enum init_array_types {
2485 MAX_INIT_ARRAY_TYPES
2488 /* init operation: callback */
2489 struct init_callback_op {
2491 #define INIT_CALLBACK_OP_OP_MASK 0xF
2492 #define INIT_CALLBACK_OP_OP_SHIFT 0
2493 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
2494 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
2499 /* init operation: delay */
2500 struct init_delay_op {
2502 #define INIT_DELAY_OP_OP_MASK 0xF
2503 #define INIT_DELAY_OP_OP_SHIFT 0
2504 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
2505 #define INIT_DELAY_OP_RESERVED_SHIFT 4
2509 /* init operation: if_mode */
2510 struct init_if_mode_op {
2512 #define INIT_IF_MODE_OP_OP_MASK 0xF
2513 #define INIT_IF_MODE_OP_OP_SHIFT 0
2514 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
2515 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
2516 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
2517 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
2519 __le16 modes_buf_offset;
2522 /* init operation: if_phase */
2523 struct init_if_phase_op {
2525 #define INIT_IF_PHASE_OP_OP_MASK 0xF
2526 #define INIT_IF_PHASE_OP_OP_SHIFT 0
2527 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
2528 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
2529 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
2530 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
2531 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
2532 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
2534 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF
2535 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0
2536 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
2537 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
2538 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF
2539 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
2542 /* init mode operators */
2543 enum init_mode_ops {
2550 /* init operation: raw */
2551 struct init_raw_op {
2553 #define INIT_RAW_OP_OP_MASK 0xF
2554 #define INIT_RAW_OP_OP_SHIFT 0
2555 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF
2556 #define INIT_RAW_OP_PARAM1_SHIFT 4
2560 /* init array params */
2561 struct init_op_array_params {
2566 /* Write init operation arguments */
2567 union init_write_args {
2570 __le32 array_offset;
2571 struct init_op_array_params runtime;
2574 /* init operation: write */
2575 struct init_write_op {
2577 #define INIT_WRITE_OP_OP_MASK 0xF
2578 #define INIT_WRITE_OP_OP_SHIFT 0
2579 #define INIT_WRITE_OP_SOURCE_MASK 0x7
2580 #define INIT_WRITE_OP_SOURCE_SHIFT 4
2581 #define INIT_WRITE_OP_RESERVED_MASK 0x1
2582 #define INIT_WRITE_OP_RESERVED_SHIFT 7
2583 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
2584 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
2585 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
2586 #define INIT_WRITE_OP_ADDRESS_SHIFT 9
2587 union init_write_args args;
2590 /* init operation: read */
2591 struct init_read_op {
2593 #define INIT_READ_OP_OP_MASK 0xF
2594 #define INIT_READ_OP_OP_SHIFT 0
2595 #define INIT_READ_OP_POLL_TYPE_MASK 0xF
2596 #define INIT_READ_OP_POLL_TYPE_SHIFT 4
2597 #define INIT_READ_OP_RESERVED_MASK 0x1
2598 #define INIT_READ_OP_RESERVED_SHIFT 8
2599 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
2600 #define INIT_READ_OP_ADDRESS_SHIFT 9
2601 __le32 expected_val;
2605 /* Init operations union */
2607 struct init_raw_op raw;
2608 struct init_write_op write;
2609 struct init_read_op read;
2610 struct init_if_mode_op if_mode;
2611 struct init_if_phase_op if_phase;
2612 struct init_callback_op callback;
2613 struct init_delay_op delay;
2616 /* Init command operation types */
2617 enum init_op_types {
2627 /* init polling types */
2628 enum init_poll_types {
2636 /* init source types */
2637 enum init_source_types {
2642 MAX_INIT_SOURCE_TYPES
2645 /* Internal RAM Offsets macro data */
2654 /***************************** Public Functions *******************************/
2656 * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug
2659 * @param bin_ptr - a pointer to the binary data with debug arrays.
2661 enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr);
2663 * @brief qed_dbg_grc_get_dump_buf_size - Returns the required buffer size for
2666 * @param p_hwfn - HW device data
2667 * @param p_ptt - Ptt window used for writing the registers.
2668 * @param buf_size - OUT: required buffer size (in dwords) for the GRC Dump
2671 * @return error if one of the following holds:
2672 * - the version wasn't set
2673 * Otherwise, returns ok.
2675 enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2676 struct qed_ptt *p_ptt,
2679 * @brief qed_dbg_grc_dump - Dumps GRC data into the specified buffer.
2681 * @param p_hwfn - HW device data
2682 * @param p_ptt - Ptt window used for writing the registers.
2683 * @param dump_buf - Pointer to write the collected GRC data into.
2684 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2685 * @param num_dumped_dwords - OUT: number of dumped dwords.
2687 * @return error if one of the following holds:
2688 * - the version wasn't set
2689 * - the specified dump buffer is too small
2690 * Otherwise, returns ok.
2692 enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn,
2693 struct qed_ptt *p_ptt,
2695 u32 buf_size_in_dwords,
2696 u32 *num_dumped_dwords);
2698 * @brief qed_dbg_idle_chk_get_dump_buf_size - Returns the required buffer size
2699 * for idle check results.
2701 * @param p_hwfn - HW device data
2702 * @param p_ptt - Ptt window used for writing the registers.
2703 * @param buf_size - OUT: required buffer size (in dwords) for the idle check
2706 * @return error if one of the following holds:
2707 * - the version wasn't set
2708 * Otherwise, returns ok.
2710 enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2711 struct qed_ptt *p_ptt,
2714 * @brief qed_dbg_idle_chk_dump - Performs idle check and writes the results
2715 * into the specified buffer.
2717 * @param p_hwfn - HW device data
2718 * @param p_ptt - Ptt window used for writing the registers.
2719 * @param dump_buf - Pointer to write the idle check data into.
2720 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2721 * @param num_dumped_dwords - OUT: number of dumped dwords.
2723 * @return error if one of the following holds:
2724 * - the version wasn't set
2725 * - the specified buffer is too small
2726 * Otherwise, returns ok.
2728 enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn,
2729 struct qed_ptt *p_ptt,
2731 u32 buf_size_in_dwords,
2732 u32 *num_dumped_dwords);
2734 * @brief qed_dbg_mcp_trace_get_dump_buf_size - Returns the required buffer size
2735 * for mcp trace results.
2737 * @param p_hwfn - HW device data
2738 * @param p_ptt - Ptt window used for writing the registers.
2739 * @param buf_size - OUT: required buffer size (in dwords) for mcp trace data.
2741 * @return error if one of the following holds:
2742 * - the version wasn't set
2743 * - the trace data in MCP scratchpad contain an invalid signature
2744 * - the bundle ID in NVRAM is invalid
2745 * - the trace meta data cannot be found (in NVRAM or image file)
2746 * Otherwise, returns ok.
2748 enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2749 struct qed_ptt *p_ptt,
2752 * @brief qed_dbg_mcp_trace_dump - Performs mcp trace and writes the results
2753 * into the specified buffer.
2755 * @param p_hwfn - HW device data
2756 * @param p_ptt - Ptt window used for writing the registers.
2757 * @param dump_buf - Pointer to write the mcp trace data into.
2758 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2759 * @param num_dumped_dwords - OUT: number of dumped dwords.
2761 * @return error if one of the following holds:
2762 * - the version wasn't set
2763 * - the specified buffer is too small
2764 * - the trace data in MCP scratchpad contain an invalid signature
2765 * - the bundle ID in NVRAM is invalid
2766 * - the trace meta data cannot be found (in NVRAM or image file)
2767 * - the trace meta data cannot be read (from NVRAM or image file)
2768 * Otherwise, returns ok.
2770 enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn,
2771 struct qed_ptt *p_ptt,
2773 u32 buf_size_in_dwords,
2774 u32 *num_dumped_dwords);
2776 * @brief qed_dbg_reg_fifo_get_dump_buf_size - Returns the required buffer size
2777 * for grc trace fifo results.
2779 * @param p_hwfn - HW device data
2780 * @param p_ptt - Ptt window used for writing the registers.
2781 * @param buf_size - OUT: required buffer size (in dwords) for reg fifo data.
2783 * @return error if one of the following holds:
2784 * - the version wasn't set
2785 * Otherwise, returns ok.
2787 enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2788 struct qed_ptt *p_ptt,
2791 * @brief qed_dbg_reg_fifo_dump - Reads the reg fifo and writes the results into
2792 * the specified buffer.
2794 * @param p_hwfn - HW device data
2795 * @param p_ptt - Ptt window used for writing the registers.
2796 * @param dump_buf - Pointer to write the reg fifo data into.
2797 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2798 * @param num_dumped_dwords - OUT: number of dumped dwords.
2800 * @return error if one of the following holds:
2801 * - the version wasn't set
2802 * - the specified buffer is too small
2803 * - DMAE transaction failed
2804 * Otherwise, returns ok.
2806 enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn,
2807 struct qed_ptt *p_ptt,
2809 u32 buf_size_in_dwords,
2810 u32 *num_dumped_dwords);
2812 * @brief qed_dbg_igu_fifo_get_dump_buf_size - Returns the required buffer size
2813 * for the IGU fifo results.
2815 * @param p_hwfn - HW device data
2816 * @param p_ptt - Ptt window used for writing the registers.
2817 * @param buf_size - OUT: required buffer size (in dwords) for the IGU fifo
2820 * @return error if one of the following holds:
2821 * - the version wasn't set
2822 * Otherwise, returns ok.
2824 enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2825 struct qed_ptt *p_ptt,
2828 * @brief qed_dbg_igu_fifo_dump - Reads the IGU fifo and writes the results into
2829 * the specified buffer.
2831 * @param p_hwfn - HW device data
2832 * @param p_ptt - Ptt window used for writing the registers.
2833 * @param dump_buf - Pointer to write the IGU fifo data into.
2834 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2835 * @param num_dumped_dwords - OUT: number of dumped dwords.
2837 * @return error if one of the following holds:
2838 * - the version wasn't set
2839 * - the specified buffer is too small
2840 * - DMAE transaction failed
2841 * Otherwise, returns ok.
2843 enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn,
2844 struct qed_ptt *p_ptt,
2846 u32 buf_size_in_dwords,
2847 u32 *num_dumped_dwords);
2849 * @brief qed_dbg_protection_override_get_dump_buf_size - Returns the required
2850 * buffer size for protection override window results.
2852 * @param p_hwfn - HW device data
2853 * @param p_ptt - Ptt window used for writing the registers.
2854 * @param buf_size - OUT: required buffer size (in dwords) for protection
2857 * @return error if one of the following holds:
2858 * - the version wasn't set
2859 * Otherwise, returns ok.
2862 qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2863 struct qed_ptt *p_ptt,
2866 * @brief qed_dbg_protection_override_dump - Reads protection override window
2867 * entries and writes the results into the specified buffer.
2869 * @param p_hwfn - HW device data
2870 * @param p_ptt - Ptt window used for writing the registers.
2871 * @param dump_buf - Pointer to write the protection override data into.
2872 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2873 * @param num_dumped_dwords - OUT: number of dumped dwords.
2875 * @return error if one of the following holds:
2876 * - the version wasn't set
2877 * - the specified buffer is too small
2878 * - DMAE transaction failed
2879 * Otherwise, returns ok.
2881 enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn,
2882 struct qed_ptt *p_ptt,
2884 u32 buf_size_in_dwords,
2885 u32 *num_dumped_dwords);
2887 * @brief qed_dbg_fw_asserts_get_dump_buf_size - Returns the required buffer
2888 * size for FW Asserts results.
2890 * @param p_hwfn - HW device data
2891 * @param p_ptt - Ptt window used for writing the registers.
2892 * @param buf_size - OUT: required buffer size (in dwords) for FW Asserts data.
2894 * @return error if one of the following holds:
2895 * - the version wasn't set
2896 * Otherwise, returns ok.
2898 enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2899 struct qed_ptt *p_ptt,
2902 * @brief qed_dbg_fw_asserts_dump - Reads the FW Asserts and writes the results
2903 * into the specified buffer.
2905 * @param p_hwfn - HW device data
2906 * @param p_ptt - Ptt window used for writing the registers.
2907 * @param dump_buf - Pointer to write the FW Asserts data into.
2908 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2909 * @param num_dumped_dwords - OUT: number of dumped dwords.
2911 * @return error if one of the following holds:
2912 * - the version wasn't set
2913 * - the specified buffer is too small
2914 * Otherwise, returns ok.
2916 enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn,
2917 struct qed_ptt *p_ptt,
2919 u32 buf_size_in_dwords,
2920 u32 *num_dumped_dwords);
2922 * @brief qed_dbg_print_attn - Prints attention registers values in the
2923 * specified results struct.
2926 * @param results - Pointer to the attention read results
2928 * @return error if one of the following holds:
2929 * - the version wasn't set
2930 * Otherwise, returns ok.
2932 enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
2933 struct dbg_attn_block_result *results);
2935 /******************************** Constants **********************************/
2937 #define MAX_NAME_LEN 16
2939 /***************************** Public Functions *******************************/
2941 * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with
2944 * @param bin_ptr - a pointer to the binary data with debug arrays.
2946 enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr);
2948 * @brief qed_dbg_get_status_str - Returns a string for the specified status.
2950 * @param status - a debug status code.
2952 * @return a string for the specified status
2954 const char *qed_dbg_get_status_str(enum dbg_status status);
2956 * @brief qed_get_idle_chk_results_buf_size - Returns the required buffer size
2957 * for idle check results (in bytes).
2959 * @param p_hwfn - HW device data
2960 * @param dump_buf - idle check dump buffer.
2961 * @param num_dumped_dwords - number of dwords that were dumped.
2962 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
2965 * @return error if the parsing fails, ok otherwise.
2967 enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn,
2969 u32 num_dumped_dwords,
2970 u32 *results_buf_size);
2972 * @brief qed_print_idle_chk_results - Prints idle check results
2974 * @param p_hwfn - HW device data
2975 * @param dump_buf - idle check dump buffer.
2976 * @param num_dumped_dwords - number of dwords that were dumped.
2977 * @param results_buf - buffer for printing the idle check results.
2978 * @param num_errors - OUT: number of errors found in idle check.
2979 * @param num_warnings - OUT: number of warnings found in idle check.
2981 * @return error if the parsing fails, ok otherwise.
2983 enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn,
2985 u32 num_dumped_dwords,
2990 * @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size
2991 * for MCP Trace results (in bytes).
2993 * @param p_hwfn - HW device data
2994 * @param dump_buf - MCP Trace dump buffer.
2995 * @param num_dumped_dwords - number of dwords that were dumped.
2996 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
2999 * @return error if the parsing fails, ok otherwise.
3001 enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn,
3003 u32 num_dumped_dwords,
3004 u32 *results_buf_size);
3006 * @brief qed_print_mcp_trace_results - Prints MCP Trace results
3008 * @param p_hwfn - HW device data
3009 * @param dump_buf - mcp trace dump buffer, starting from the header.
3010 * @param num_dumped_dwords - number of dwords that were dumped.
3011 * @param results_buf - buffer for printing the mcp trace results.
3013 * @return error if the parsing fails, ok otherwise.
3015 enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn,
3017 u32 num_dumped_dwords,
3020 * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size
3021 * for reg_fifo results (in bytes).
3023 * @param p_hwfn - HW device data
3024 * @param dump_buf - reg fifo dump buffer.
3025 * @param num_dumped_dwords - number of dwords that were dumped.
3026 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3029 * @return error if the parsing fails, ok otherwise.
3031 enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3033 u32 num_dumped_dwords,
3034 u32 *results_buf_size);
3036 * @brief qed_print_reg_fifo_results - Prints reg fifo results
3038 * @param p_hwfn - HW device data
3039 * @param dump_buf - reg fifo dump buffer, starting from the header.
3040 * @param num_dumped_dwords - number of dwords that were dumped.
3041 * @param results_buf - buffer for printing the reg fifo results.
3043 * @return error if the parsing fails, ok otherwise.
3045 enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn,
3047 u32 num_dumped_dwords,
3050 * @brief qed_get_igu_fifo_results_buf_size - Returns the required buffer size
3051 * for igu_fifo results (in bytes).
3053 * @param p_hwfn - HW device data
3054 * @param dump_buf - IGU fifo dump buffer.
3055 * @param num_dumped_dwords - number of dwords that were dumped.
3056 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3059 * @return error if the parsing fails, ok otherwise.
3061 enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3063 u32 num_dumped_dwords,
3064 u32 *results_buf_size);
3066 * @brief qed_print_igu_fifo_results - Prints IGU fifo results
3068 * @param p_hwfn - HW device data
3069 * @param dump_buf - IGU fifo dump buffer, starting from the header.
3070 * @param num_dumped_dwords - number of dwords that were dumped.
3071 * @param results_buf - buffer for printing the IGU fifo results.
3073 * @return error if the parsing fails, ok otherwise.
3075 enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn,
3077 u32 num_dumped_dwords,
3080 * @brief qed_get_protection_override_results_buf_size - Returns the required
3081 * buffer size for protection override results (in bytes).
3083 * @param p_hwfn - HW device data
3084 * @param dump_buf - protection override dump buffer.
3085 * @param num_dumped_dwords - number of dwords that were dumped.
3086 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3089 * @return error if the parsing fails, ok otherwise.
3092 qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn,
3094 u32 num_dumped_dwords,
3095 u32 *results_buf_size);
3097 * @brief qed_print_protection_override_results - Prints protection override
3100 * @param p_hwfn - HW device data
3101 * @param dump_buf - protection override dump buffer, starting from the header.
3102 * @param num_dumped_dwords - number of dwords that were dumped.
3103 * @param results_buf - buffer for printing the reg fifo results.
3105 * @return error if the parsing fails, ok otherwise.
3107 enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn,
3109 u32 num_dumped_dwords,
3112 * @brief qed_get_fw_asserts_results_buf_size - Returns the required buffer size
3113 * for FW Asserts results (in bytes).
3115 * @param p_hwfn - HW device data
3116 * @param dump_buf - FW Asserts dump buffer.
3117 * @param num_dumped_dwords - number of dwords that were dumped.
3118 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3121 * @return error if the parsing fails, ok otherwise.
3123 enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn,
3125 u32 num_dumped_dwords,
3126 u32 *results_buf_size);
3128 * @brief qed_print_fw_asserts_results - Prints FW Asserts results
3130 * @param p_hwfn - HW device data
3131 * @param dump_buf - FW Asserts dump buffer, starting from the header.
3132 * @param num_dumped_dwords - number of dwords that were dumped.
3133 * @param results_buf - buffer for printing the FW Asserts results.
3135 * @return error if the parsing fails, ok otherwise.
3137 enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn,
3139 u32 num_dumped_dwords,
3142 #define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL
3145 #define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL
3148 #define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL
3151 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL
3154 #define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL
3157 #define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL
3160 #define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL
3163 #define GTT_BAR0_MAP_REG_XSDM_RAM 0x016000UL
3166 #define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL
3169 #define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL
3172 * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
3174 * Returns the required host memory size in 4KB units.
3175 * Must be called before all QM init HSI functions.
3177 * @param pf_id - physical function ID
3178 * @param num_pf_cids - number of connections used by this PF
3179 * @param num_vf_cids - number of connections used by VFs of this PF
3180 * @param num_tids - number of tasks used by this PF
3181 * @param num_pf_pqs - number of PQs used by this PF
3182 * @param num_vf_pqs - number of PQs used by VFs of this PF
3184 * @return The required host memory size in 4KB units.
3186 u32 qed_qm_pf_mem_size(u8 pf_id,
3189 u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
3191 struct qed_qm_common_rt_init_params {
3192 u8 max_ports_per_engine;
3193 u8 max_phys_tcs_per_port;
3198 struct init_qm_port_params *port_params;
3201 int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
3202 struct qed_qm_common_rt_init_params *p_params);
3204 struct qed_qm_pf_rt_init_params {
3207 u8 max_phys_tcs_per_port;
3219 struct init_qm_pq_params *pq_params;
3220 struct init_qm_vport_params *vport_params;
3223 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
3224 struct qed_ptt *p_ptt,
3225 struct qed_qm_pf_rt_init_params *p_params);
3228 * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF
3231 * @param p_ptt - ptt window used for writing the registers
3232 * @param pf_id - PF ID
3233 * @param pf_wfq - WFQ weight. Must be non-zero.
3235 * @return 0 on success, -1 on error.
3237 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
3238 struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq);
3241 * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF
3244 * @param p_ptt - ptt window used for writing the registers
3245 * @param pf_id - PF ID
3246 * @param pf_rl - rate limit in Mb/sec units
3248 * @return 0 on success, -1 on error.
3250 int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
3251 struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl);
3254 * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT
3257 * @param p_ptt - ptt window used for writing the registers
3258 * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
3259 * with the VPORT for each TC. This array is filled by
3261 * @param vport_wfq - WFQ weight. Must be non-zero.
3263 * @return 0 on success, -1 on error.
3265 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
3266 struct qed_ptt *p_ptt,
3267 u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq);
3270 * @brief qed_init_vport_rl - Initializes the rate limit of the specified VPORT
3273 * @param p_ptt - ptt window used for writing the registers
3274 * @param vport_id - VPORT ID
3275 * @param vport_rl - rate limit in Mb/sec units
3277 * @return 0 on success, -1 on error.
3279 int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
3280 struct qed_ptt *p_ptt, u8 vport_id, u32 vport_rl);
3282 * @brief qed_send_qm_stop_cmd Sends a stop command to the QM
3286 * @param is_release_cmd - true for release, false for stop.
3287 * @param is_tx_pq - true for Tx PQs, false for Other PQs.
3288 * @param start_pq - first PQ ID to stop
3289 * @param num_pqs - Number of PQs to stop, starting from start_pq.
3291 * @return bool, true if successful, false if timeout occured while waiting for QM command done.
3293 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
3294 struct qed_ptt *p_ptt,
3295 bool is_release_cmd,
3296 bool is_tx_pq, u16 start_pq, u16 num_pqs);
3299 * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port
3301 * @param p_ptt - ptt window used for writing the registers.
3302 * @param dest_port - vxlan destination udp port.
3304 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
3305 struct qed_ptt *p_ptt, u16 dest_port);
3308 * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW
3310 * @param p_ptt - ptt window used for writing the registers.
3311 * @param vxlan_enable - vxlan enable flag.
3313 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
3314 struct qed_ptt *p_ptt, bool vxlan_enable);
3317 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3319 * @param p_ptt - ptt window used for writing the registers.
3320 * @param eth_gre_enable - eth GRE enable enable flag.
3321 * @param ip_gre_enable - IP GRE enable enable flag.
3323 void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
3324 struct qed_ptt *p_ptt,
3325 bool eth_gre_enable, bool ip_gre_enable);
3328 * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port
3330 * @param p_ptt - ptt window used for writing the registers.
3331 * @param dest_port - geneve destination udp port.
3333 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
3334 struct qed_ptt *p_ptt, u16 dest_port);
3337 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3339 * @param p_ptt - ptt window used for writing the registers.
3340 * @param eth_geneve_enable - eth GENEVE enable enable flag.
3341 * @param ip_geneve_enable - IP GENEVE enable enable flag.
3343 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
3344 struct qed_ptt *p_ptt,
3345 bool eth_geneve_enable, bool ip_geneve_enable);
3347 #define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
3348 #define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
3349 #define TSTORM_PORT_STAT_OFFSET(port_id) \
3350 (IRO[1].base + ((port_id) * IRO[1].m1))
3351 #define TSTORM_PORT_STAT_SIZE (IRO[1].size)
3352 #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
3353 (IRO[2].base + ((port_id) * IRO[2].m1))
3354 #define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
3355 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
3356 (IRO[3].base + ((vf_id) * IRO[3].m1))
3357 #define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
3358 #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
3359 (IRO[4].base + (pf_id) * IRO[4].m1)
3360 #define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
3361 #define USTORM_EQE_CONS_OFFSET(pf_id) \
3362 (IRO[5].base + ((pf_id) * IRO[5].m1))
3363 #define USTORM_EQE_CONS_SIZE (IRO[5].size)
3364 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
3365 (IRO[6].base + ((queue_zone_id) * IRO[6].m1))
3366 #define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size)
3367 #define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
3368 (IRO[7].base + ((queue_zone_id) * IRO[7].m1))
3369 #define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size)
3370 #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
3371 (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
3372 #define TSTORM_LL2_RX_PRODS_SIZE (IRO[14].size)
3373 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
3374 (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
3375 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[15].size)
3376 #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
3377 (IRO[16].base + ((core_rx_queue_id) * IRO[16].m1))
3378 #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[16].size)
3379 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
3380 (IRO[17].base + ((core_tx_stats_id) * IRO[17].m1))
3381 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[17]. size)
3382 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
3383 (IRO[18].base + ((stat_counter_id) * IRO[18].m1))
3384 #define MSTORM_QUEUE_STAT_SIZE (IRO[18].size)
3385 #define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
3386 (IRO[19].base + ((queue_id) * IRO[19].m1))
3387 #define MSTORM_ETH_PF_PRODS_SIZE (IRO[19].size)
3388 #define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
3389 (IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2))
3390 #define MSTORM_ETH_VF_PRODS_SIZE (IRO[20].size)
3391 #define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[21].base)
3392 #define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[21].size)
3393 #define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
3394 (IRO[22].base + ((pf_id) * IRO[22].m1))
3395 #define MSTORM_ETH_PF_STAT_SIZE (IRO[21].size)
3396 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
3397 (IRO[23].base + ((stat_counter_id) * IRO[23].m1))
3398 #define USTORM_QUEUE_STAT_SIZE (IRO[23].size)
3399 #define USTORM_ETH_PF_STAT_OFFSET(pf_id) \
3400 (IRO[24].base + ((pf_id) * IRO[24].m1))
3401 #define USTORM_ETH_PF_STAT_SIZE (IRO[24].size)
3402 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
3403 (IRO[25].base + ((stat_counter_id) * IRO[25].m1))
3404 #define PSTORM_QUEUE_STAT_SIZE (IRO[25].size)
3405 #define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
3406 (IRO[26].base + ((pf_id) * IRO[26].m1))
3407 #define PSTORM_ETH_PF_STAT_SIZE (IRO[26].size)
3408 #define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethtype) \
3409 (IRO[27].base + ((ethtype) * IRO[27].m1))
3410 #define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[27].size)
3411 #define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[28].base)
3412 #define TSTORM_ETH_PRS_INPUT_SIZE (IRO[28].size)
3413 #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
3414 (IRO[29].base + ((pf_id) * IRO[29].m1))
3415 #define ETH_RX_RATE_LIMIT_SIZE (IRO[29].size)
3416 #define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
3417 (IRO[30].base + ((queue_id) * IRO[30].m1))
3418 #define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[30].size)
3419 #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
3420 (IRO[34].base + ((cmdq_queue_id) * IRO[34].m1))
3421 #define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[34].size)
3422 #define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
3423 (IRO[35].base + ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2))
3424 #define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[35].size)
3425 #define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
3426 (IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2))
3427 #define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size)
3428 #define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
3429 (IRO[37].base + ((pf_id) * IRO[37].m1))
3430 #define TSTORM_ISCSI_RX_STATS_SIZE (IRO[37].size)
3431 #define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
3432 (IRO[38].base + ((pf_id) * IRO[38].m1))
3433 #define MSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size)
3434 #define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
3435 (IRO[39].base + ((pf_id) * IRO[39].m1))
3436 #define USTORM_ISCSI_RX_STATS_SIZE (IRO[39].size)
3437 #define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
3438 (IRO[40].base + ((pf_id) * IRO[40].m1))
3439 #define XSTORM_ISCSI_TX_STATS_SIZE (IRO[40].size)
3440 #define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
3441 (IRO[41].base + ((pf_id) * IRO[41].m1))
3442 #define YSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size)
3443 #define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
3444 (IRO[42].base + ((pf_id) * IRO[42].m1))
3445 #define PSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size)
3446 #define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
3447 (IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1))
3448 #define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[45].size)
3449 #define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
3450 (IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1))
3451 #define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size)
3453 static const struct iro iro_arr[47] = {
3454 {0x0, 0x0, 0x0, 0x0, 0x8},
3455 {0x4cb0, 0x78, 0x0, 0x0, 0x78},
3456 {0x6318, 0x20, 0x0, 0x0, 0x20},
3457 {0xb00, 0x8, 0x0, 0x0, 0x4},
3458 {0xa80, 0x8, 0x0, 0x0, 0x4},
3459 {0x0, 0x8, 0x0, 0x0, 0x2},
3460 {0x80, 0x8, 0x0, 0x0, 0x4},
3461 {0x84, 0x8, 0x0, 0x0, 0x2},
3462 {0x4bc0, 0x0, 0x0, 0x0, 0x78},
3463 {0x3df0, 0x0, 0x0, 0x0, 0x78},
3464 {0x29b0, 0x0, 0x0, 0x0, 0x78},
3465 {0x4c38, 0x0, 0x0, 0x0, 0x78},
3466 {0x4990, 0x0, 0x0, 0x0, 0x78},
3467 {0x7e48, 0x0, 0x0, 0x0, 0x78},
3468 {0xa28, 0x8, 0x0, 0x0, 0x8},
3469 {0x60f8, 0x10, 0x0, 0x0, 0x10},
3470 {0xb820, 0x30, 0x0, 0x0, 0x30},
3471 {0x95b8, 0x30, 0x0, 0x0, 0x30},
3472 {0x4b60, 0x80, 0x0, 0x0, 0x40},
3473 {0x1f8, 0x4, 0x0, 0x0, 0x4},
3474 {0x53a0, 0x80, 0x4, 0x0, 0x4},
3475 {0xc8f0, 0x0, 0x0, 0x0, 0x4},
3476 {0x4ba0, 0x80, 0x0, 0x0, 0x20},
3477 {0x8050, 0x40, 0x0, 0x0, 0x30},
3478 {0xe770, 0x60, 0x0, 0x0, 0x60},
3479 {0x2b48, 0x80, 0x0, 0x0, 0x38},
3480 {0xf188, 0x78, 0x0, 0x0, 0x78},
3481 {0x1f8, 0x4, 0x0, 0x0, 0x4},
3482 {0xacf0, 0x0, 0x0, 0x0, 0xf0},
3483 {0xade0, 0x8, 0x0, 0x0, 0x8},
3484 {0x1f8, 0x8, 0x0, 0x0, 0x8},
3485 {0xac0, 0x8, 0x0, 0x0, 0x8},
3486 {0x2578, 0x8, 0x0, 0x0, 0x8},
3487 {0x24f8, 0x8, 0x0, 0x0, 0x8},
3488 {0x0, 0x8, 0x0, 0x0, 0x8},
3489 {0x200, 0x10, 0x8, 0x0, 0x8},
3490 {0xb78, 0x10, 0x8, 0x0, 0x2},
3491 {0xd888, 0x38, 0x0, 0x0, 0x24},
3492 {0x12c38, 0x10, 0x0, 0x0, 0x8},
3493 {0x11aa0, 0x38, 0x0, 0x0, 0x18},
3494 {0xa8c0, 0x30, 0x0, 0x0, 0x10},
3495 {0x86f8, 0x28, 0x0, 0x0, 0x18},
3496 {0x101f8, 0x10, 0x0, 0x0, 0x10},
3497 {0xdd08, 0x48, 0x0, 0x0, 0x38},
3498 {0x10660, 0x20, 0x0, 0x0, 0x20},
3499 {0x2b80, 0x80, 0x0, 0x0, 0x10},
3500 {0x5000, 0x10, 0x0, 0x0, 0x10},
3503 /* Runtime array offsets */
3504 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
3505 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
3506 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
3507 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
3508 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
3509 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
3510 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
3511 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
3512 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
3513 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
3514 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
3515 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
3516 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
3517 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
3518 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
3519 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
3520 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
3521 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
3522 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18
3523 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19
3524 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20
3525 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21
3526 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22
3527 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23
3528 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24
3529 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
3530 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
3531 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
3532 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
3533 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497
3534 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
3535 #define CAU_REG_PI_MEMORY_RT_OFFSET 2233
3536 #define CAU_REG_PI_MEMORY_RT_SIZE 4416
3537 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649
3538 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650
3539 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651
3540 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
3541 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
3542 #define PRS_REG_SEARCH_TCP_RT_OFFSET 6654
3543 #define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655
3544 #define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656
3545 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657
3546 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658
3547 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659
3548 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660
3549 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661
3550 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662
3551 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663
3552 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664
3553 #define SRC_REG_FIRSTFREE_RT_OFFSET 6665
3554 #define SRC_REG_FIRSTFREE_RT_SIZE 2
3555 #define SRC_REG_LASTFREE_RT_OFFSET 6667
3556 #define SRC_REG_LASTFREE_RT_SIZE 2
3557 #define SRC_REG_COUNTFREE_RT_OFFSET 6669
3558 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670
3559 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671
3560 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672
3561 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673
3562 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674
3563 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675
3564 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6676
3565 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6677
3566 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6678
3567 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6679
3568 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6680
3569 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6681
3570 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6682
3571 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6683
3572 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6684
3573 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6685
3574 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6686
3575 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6687
3576 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6688
3577 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689
3578 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690
3579 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6691
3580 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6692
3581 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6693
3582 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6694
3583 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6695
3584 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6696
3585 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697
3586 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 6698
3587 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6699
3588 #define PSWRQ2_REG_WR_MBS0_RT_OFFSET 6700
3589 #define PSWRQ2_REG_RD_MBS0_RT_OFFSET 6701
3590 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6702
3591 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6703
3592 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6704
3593 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
3594 #define PGLUE_REG_B_VF_BASE_RT_OFFSET 28704
3595 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 28705
3596 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 28706
3597 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28707
3598 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28708
3599 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28709
3600 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28710
3601 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28711
3602 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28712
3603 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28713
3604 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28714
3605 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28715
3606 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28716
3607 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
3608 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29132
3609 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
3610 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 29644
3611 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 29645
3612 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 29646
3613 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29647
3614 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29648
3615 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29649
3616 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29650
3617 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29651
3618 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29652
3619 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29653
3620 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29654
3621 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29655
3622 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29656
3623 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29657
3624 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29658
3625 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29659
3626 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29660
3627 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29661
3628 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29662
3629 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29663
3630 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29664
3631 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29665
3632 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29666
3633 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29667
3634 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29668
3635 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29669
3636 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29670
3637 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29671
3638 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29672
3639 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29673
3640 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29674
3641 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29675
3642 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29676
3643 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29677
3644 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29678
3645 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29679
3646 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29680
3647 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29681
3648 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29682
3649 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29683
3650 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29684
3651 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29685
3652 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29686
3653 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29687
3654 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29688
3655 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29689
3656 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29690
3657 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29691
3658 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29692
3659 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29693
3660 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29694
3661 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29695
3662 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29696
3663 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29697
3664 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29698
3665 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29699
3666 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29700
3667 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29701
3668 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29702
3669 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29703
3670 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29704
3671 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29705
3672 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29706
3673 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29707
3674 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29708
3675 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29709
3676 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29710
3677 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29711
3678 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
3679 #define QM_REG_VOQCRDLINE_RT_OFFSET 29839
3680 #define QM_REG_VOQCRDLINE_RT_SIZE 20
3681 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 29859
3682 #define QM_REG_VOQINITCRDLINE_RT_SIZE 20
3683 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29879
3684 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29880
3685 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29881
3686 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29882
3687 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29883
3688 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29884
3689 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29885
3690 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29886
3691 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29887
3692 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29888
3693 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29889
3694 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29890
3695 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29891
3696 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29892
3697 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29893
3698 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29894
3699 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29895
3700 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29896
3701 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29897
3702 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29898
3703 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29899
3704 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29900
3705 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29901
3706 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29902
3707 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29903
3708 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29904
3709 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29905
3710 #define QM_REG_PQTX2PF_0_RT_OFFSET 29906
3711 #define QM_REG_PQTX2PF_1_RT_OFFSET 29907
3712 #define QM_REG_PQTX2PF_2_RT_OFFSET 29908
3713 #define QM_REG_PQTX2PF_3_RT_OFFSET 29909
3714 #define QM_REG_PQTX2PF_4_RT_OFFSET 29910
3715 #define QM_REG_PQTX2PF_5_RT_OFFSET 29911
3716 #define QM_REG_PQTX2PF_6_RT_OFFSET 29912
3717 #define QM_REG_PQTX2PF_7_RT_OFFSET 29913
3718 #define QM_REG_PQTX2PF_8_RT_OFFSET 29914
3719 #define QM_REG_PQTX2PF_9_RT_OFFSET 29915
3720 #define QM_REG_PQTX2PF_10_RT_OFFSET 29916
3721 #define QM_REG_PQTX2PF_11_RT_OFFSET 29917
3722 #define QM_REG_PQTX2PF_12_RT_OFFSET 29918
3723 #define QM_REG_PQTX2PF_13_RT_OFFSET 29919
3724 #define QM_REG_PQTX2PF_14_RT_OFFSET 29920
3725 #define QM_REG_PQTX2PF_15_RT_OFFSET 29921
3726 #define QM_REG_PQTX2PF_16_RT_OFFSET 29922
3727 #define QM_REG_PQTX2PF_17_RT_OFFSET 29923
3728 #define QM_REG_PQTX2PF_18_RT_OFFSET 29924
3729 #define QM_REG_PQTX2PF_19_RT_OFFSET 29925
3730 #define QM_REG_PQTX2PF_20_RT_OFFSET 29926
3731 #define QM_REG_PQTX2PF_21_RT_OFFSET 29927
3732 #define QM_REG_PQTX2PF_22_RT_OFFSET 29928
3733 #define QM_REG_PQTX2PF_23_RT_OFFSET 29929
3734 #define QM_REG_PQTX2PF_24_RT_OFFSET 29930
3735 #define QM_REG_PQTX2PF_25_RT_OFFSET 29931
3736 #define QM_REG_PQTX2PF_26_RT_OFFSET 29932
3737 #define QM_REG_PQTX2PF_27_RT_OFFSET 29933
3738 #define QM_REG_PQTX2PF_28_RT_OFFSET 29934
3739 #define QM_REG_PQTX2PF_29_RT_OFFSET 29935
3740 #define QM_REG_PQTX2PF_30_RT_OFFSET 29936
3741 #define QM_REG_PQTX2PF_31_RT_OFFSET 29937
3742 #define QM_REG_PQTX2PF_32_RT_OFFSET 29938
3743 #define QM_REG_PQTX2PF_33_RT_OFFSET 29939
3744 #define QM_REG_PQTX2PF_34_RT_OFFSET 29940
3745 #define QM_REG_PQTX2PF_35_RT_OFFSET 29941
3746 #define QM_REG_PQTX2PF_36_RT_OFFSET 29942
3747 #define QM_REG_PQTX2PF_37_RT_OFFSET 29943
3748 #define QM_REG_PQTX2PF_38_RT_OFFSET 29944
3749 #define QM_REG_PQTX2PF_39_RT_OFFSET 29945
3750 #define QM_REG_PQTX2PF_40_RT_OFFSET 29946
3751 #define QM_REG_PQTX2PF_41_RT_OFFSET 29947
3752 #define QM_REG_PQTX2PF_42_RT_OFFSET 29948
3753 #define QM_REG_PQTX2PF_43_RT_OFFSET 29949
3754 #define QM_REG_PQTX2PF_44_RT_OFFSET 29950
3755 #define QM_REG_PQTX2PF_45_RT_OFFSET 29951
3756 #define QM_REG_PQTX2PF_46_RT_OFFSET 29952
3757 #define QM_REG_PQTX2PF_47_RT_OFFSET 29953
3758 #define QM_REG_PQTX2PF_48_RT_OFFSET 29954
3759 #define QM_REG_PQTX2PF_49_RT_OFFSET 29955
3760 #define QM_REG_PQTX2PF_50_RT_OFFSET 29956
3761 #define QM_REG_PQTX2PF_51_RT_OFFSET 29957
3762 #define QM_REG_PQTX2PF_52_RT_OFFSET 29958
3763 #define QM_REG_PQTX2PF_53_RT_OFFSET 29959
3764 #define QM_REG_PQTX2PF_54_RT_OFFSET 29960
3765 #define QM_REG_PQTX2PF_55_RT_OFFSET 29961
3766 #define QM_REG_PQTX2PF_56_RT_OFFSET 29962
3767 #define QM_REG_PQTX2PF_57_RT_OFFSET 29963
3768 #define QM_REG_PQTX2PF_58_RT_OFFSET 29964
3769 #define QM_REG_PQTX2PF_59_RT_OFFSET 29965
3770 #define QM_REG_PQTX2PF_60_RT_OFFSET 29966
3771 #define QM_REG_PQTX2PF_61_RT_OFFSET 29967
3772 #define QM_REG_PQTX2PF_62_RT_OFFSET 29968
3773 #define QM_REG_PQTX2PF_63_RT_OFFSET 29969
3774 #define QM_REG_PQOTHER2PF_0_RT_OFFSET 29970
3775 #define QM_REG_PQOTHER2PF_1_RT_OFFSET 29971
3776 #define QM_REG_PQOTHER2PF_2_RT_OFFSET 29972
3777 #define QM_REG_PQOTHER2PF_3_RT_OFFSET 29973
3778 #define QM_REG_PQOTHER2PF_4_RT_OFFSET 29974
3779 #define QM_REG_PQOTHER2PF_5_RT_OFFSET 29975
3780 #define QM_REG_PQOTHER2PF_6_RT_OFFSET 29976
3781 #define QM_REG_PQOTHER2PF_7_RT_OFFSET 29977
3782 #define QM_REG_PQOTHER2PF_8_RT_OFFSET 29978
3783 #define QM_REG_PQOTHER2PF_9_RT_OFFSET 29979
3784 #define QM_REG_PQOTHER2PF_10_RT_OFFSET 29980
3785 #define QM_REG_PQOTHER2PF_11_RT_OFFSET 29981
3786 #define QM_REG_PQOTHER2PF_12_RT_OFFSET 29982
3787 #define QM_REG_PQOTHER2PF_13_RT_OFFSET 29983
3788 #define QM_REG_PQOTHER2PF_14_RT_OFFSET 29984
3789 #define QM_REG_PQOTHER2PF_15_RT_OFFSET 29985
3790 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29986
3791 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29987
3792 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29988
3793 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29989
3794 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29990
3795 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29991
3796 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29992
3797 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29993
3798 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29994
3799 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29995
3800 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29996
3801 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29997
3802 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 29998
3803 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256
3804 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30254
3805 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
3806 #define QM_REG_RLGLBLCRD_RT_OFFSET 30510
3807 #define QM_REG_RLGLBLCRD_RT_SIZE 256
3808 #define QM_REG_RLGLBLENABLE_RT_OFFSET 30766
3809 #define QM_REG_RLPFPERIOD_RT_OFFSET 30767
3810 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30768
3811 #define QM_REG_RLPFINCVAL_RT_OFFSET 30769
3812 #define QM_REG_RLPFINCVAL_RT_SIZE 16
3813 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30785
3814 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
3815 #define QM_REG_RLPFCRD_RT_OFFSET 30801
3816 #define QM_REG_RLPFCRD_RT_SIZE 16
3817 #define QM_REG_RLPFENABLE_RT_OFFSET 30817
3818 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 30818
3819 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 30819
3820 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16
3821 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30835
3822 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
3823 #define QM_REG_WFQPFCRD_RT_OFFSET 30851
3824 #define QM_REG_WFQPFCRD_RT_SIZE 160
3825 #define QM_REG_WFQPFENABLE_RT_OFFSET 31011
3826 #define QM_REG_WFQVPENABLE_RT_OFFSET 31012
3827 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 31013
3828 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512
3829 #define QM_REG_TXPQMAP_RT_OFFSET 31525
3830 #define QM_REG_TXPQMAP_RT_SIZE 512
3831 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 32037
3832 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512
3833 #define QM_REG_WFQVPCRD_RT_OFFSET 32549
3834 #define QM_REG_WFQVPCRD_RT_SIZE 512
3835 #define QM_REG_WFQVPMAP_RT_OFFSET 33061
3836 #define QM_REG_WFQVPMAP_RT_SIZE 512
3837 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33573
3838 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
3839 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 33733
3840 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 33734
3841 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 33735
3842 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 33736
3843 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 33737
3844 #define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 33738
3845 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 33739
3846 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 33740
3847 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
3848 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 33744
3849 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
3850 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 33748
3851 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
3852 #define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 33752
3853 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 33753
3854 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
3855 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 33785
3856 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
3857 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 33801
3858 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
3859 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 33817
3860 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
3861 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 33833
3862 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
3863 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 33849
3864 #define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 33850
3865 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 33851
3866 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 33852
3867 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 33853
3868 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 33854
3869 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 33855
3870 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 33856
3871 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 33857
3872 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 33858
3873 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 33859
3874 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 33860
3875 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 33861
3876 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 33862
3877 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 33863
3878 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 33864
3879 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 33865
3880 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 33866
3881 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 33867
3882 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 33868
3883 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 33869
3884 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 33870
3885 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 33871
3886 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 33872
3887 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 33873
3888 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 33874
3889 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 33875
3890 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 33876
3891 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 33877
3892 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 33878
3893 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 33879
3894 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 33880
3895 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 33881
3896 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 33882
3897 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 33883
3898 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 33884
3899 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 33885
3900 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 33886
3901 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 33887
3902 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 33888
3903 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 33889
3904 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 33890
3905 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 33891
3906 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 33892
3907 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 33893
3908 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 33894
3909 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 33895
3910 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 33896
3911 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 33897
3912 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 33898
3913 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 33899
3914 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 33900
3915 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 33901
3916 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 33902
3917 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 33903
3918 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 33904
3919 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 33905
3920 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 33906
3921 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 33907
3922 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 33908
3923 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 33909
3924 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 33910
3925 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 33911
3926 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 33912
3927 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 33913
3928 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 33914
3929 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 33915
3930 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 33916
3931 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 33917
3932 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 33918
3933 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 33919
3934 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 33920
3935 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 33921
3936 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 33922
3937 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 33923
3938 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 33924
3939 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 33925
3940 #define XCM_REG_CON_PHY_Q3_RT_OFFSET 33926
3942 #define RUNTIME_ARRAY_SIZE 33927
3944 /* The eth storm context for the Tstorm */
3945 struct tstorm_eth_conn_st_ctx {
3949 /* The eth storm context for the Pstorm */
3950 struct pstorm_eth_conn_st_ctx {
3954 /* The eth storm context for the Xstorm */
3955 struct xstorm_eth_conn_st_ctx {
3956 __le32 reserved[60];
3959 struct xstorm_eth_conn_ag_ctx {
3963 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
3964 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
3965 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
3966 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
3967 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
3968 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
3969 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
3970 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
3971 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
3972 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
3973 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
3974 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
3975 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
3976 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
3977 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
3978 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
3980 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
3981 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
3982 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
3983 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
3984 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
3985 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
3986 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
3987 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
3988 #define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1
3989 #define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
3990 #define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1
3991 #define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
3992 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
3993 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
3994 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
3995 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
3997 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
3998 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
3999 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4000 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
4001 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4002 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
4003 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4004 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
4006 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
4007 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
4008 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
4009 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
4010 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
4011 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
4012 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
4013 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
4015 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
4016 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
4017 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
4018 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
4019 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
4020 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
4021 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
4022 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
4024 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
4025 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
4026 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
4027 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
4028 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
4029 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
4030 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
4031 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
4033 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
4034 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
4035 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
4036 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
4037 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
4038 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
4039 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
4040 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
4042 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
4043 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
4044 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
4045 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
4046 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
4047 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
4048 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
4049 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
4050 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
4051 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
4053 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4054 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
4055 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
4056 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
4057 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
4058 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
4059 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
4060 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
4061 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
4062 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
4063 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
4064 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
4065 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
4066 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
4067 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
4068 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
4070 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
4071 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
4072 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
4073 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
4074 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
4075 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
4076 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
4077 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
4078 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
4079 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
4080 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
4081 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
4082 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
4083 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
4084 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
4085 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
4087 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
4088 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
4089 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
4090 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
4091 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
4092 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
4093 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
4094 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
4095 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
4096 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
4097 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
4098 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
4099 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
4100 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
4101 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
4102 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
4104 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
4105 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
4106 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
4107 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
4108 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
4109 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
4110 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
4111 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
4112 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
4113 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
4114 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
4115 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
4116 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
4117 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
4118 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
4119 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
4121 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
4122 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
4123 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
4124 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
4125 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
4126 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
4127 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
4128 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
4129 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
4130 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
4131 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
4132 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
4133 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
4134 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
4135 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
4136 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
4138 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
4139 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
4140 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
4141 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
4142 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
4143 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
4144 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
4145 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
4146 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
4147 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
4148 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
4149 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
4150 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
4151 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
4152 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
4153 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
4155 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
4156 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
4157 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
4158 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
4159 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
4160 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
4161 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
4162 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
4163 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
4164 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
4165 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
4166 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
4167 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
4168 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
4172 __le16 edpm_num_bds;
4222 /* The eth storm context for the Ystorm */
4223 struct ystorm_eth_conn_st_ctx {
4227 struct ystorm_eth_conn_ag_ctx {
4231 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
4232 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
4233 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4234 #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
4235 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
4236 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
4237 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
4238 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
4239 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4240 #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
4242 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
4243 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
4244 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
4245 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
4246 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4247 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
4248 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4249 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
4250 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4251 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
4252 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4253 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
4254 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4255 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
4256 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4257 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
4258 u8 tx_q0_int_coallecing_timeset;
4261 __le32 terminate_spqe;
4263 __le16 tx_bd_cons_upd;
4271 struct tstorm_eth_conn_ag_ctx {
4275 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
4276 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
4277 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4278 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
4279 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
4280 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
4281 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
4282 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
4283 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
4284 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
4285 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
4286 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
4287 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4288 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
4290 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4291 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
4292 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4293 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
4294 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4295 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
4296 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
4297 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
4299 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
4300 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
4301 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
4302 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
4303 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
4304 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
4305 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
4306 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
4308 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
4309 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
4310 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
4311 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
4312 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
4313 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
4314 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
4315 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
4316 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4317 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
4318 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
4319 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
4321 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
4322 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
4323 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
4324 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
4325 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
4326 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
4327 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
4328 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
4329 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
4330 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
4331 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
4332 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
4333 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
4334 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
4335 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4336 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
4338 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4339 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
4340 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4341 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
4342 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4343 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
4344 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4345 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
4346 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
4347 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
4348 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
4349 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
4350 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
4351 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
4352 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
4353 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
4375 struct ustorm_eth_conn_ag_ctx {
4379 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
4380 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
4381 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4382 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
4383 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
4384 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
4385 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
4386 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
4387 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4388 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
4390 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4391 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
4392 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
4393 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
4394 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
4395 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
4396 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
4397 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
4399 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
4400 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
4401 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
4402 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
4403 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4404 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
4405 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
4406 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
4407 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
4408 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
4409 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
4410 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
4411 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
4412 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
4413 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4414 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
4416 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4417 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
4418 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4419 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
4420 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4421 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
4422 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4423 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
4424 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
4425 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
4426 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
4427 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
4428 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
4429 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
4430 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
4431 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
4439 __le32 tx_int_coallecing_timeset;
4440 __le16 tx_drv_bd_cons;
4441 __le16 rx_drv_cqe_cons;
4444 /* The eth storm context for the Ustorm */
4445 struct ustorm_eth_conn_st_ctx {
4446 __le32 reserved[40];
4449 /* The eth storm context for the Mstorm */
4450 struct mstorm_eth_conn_st_ctx {
4454 /* eth connection context */
4455 struct eth_conn_context {
4456 struct tstorm_eth_conn_st_ctx tstorm_st_context;
4457 struct regpair tstorm_st_padding[2];
4458 struct pstorm_eth_conn_st_ctx pstorm_st_context;
4459 struct xstorm_eth_conn_st_ctx xstorm_st_context;
4460 struct xstorm_eth_conn_ag_ctx xstorm_ag_context;
4461 struct ystorm_eth_conn_st_ctx ystorm_st_context;
4462 struct ystorm_eth_conn_ag_ctx ystorm_ag_context;
4463 struct tstorm_eth_conn_ag_ctx tstorm_ag_context;
4464 struct ustorm_eth_conn_ag_ctx ustorm_ag_context;
4465 struct ustorm_eth_conn_st_ctx ustorm_st_context;
4466 struct mstorm_eth_conn_st_ctx mstorm_st_context;
4469 enum eth_error_code {
4471 ETH_FILTERS_MAC_ADD_FAIL_FULL,
4472 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
4473 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
4474 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
4475 ETH_FILTERS_MAC_DEL_FAIL_NOF,
4476 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
4477 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
4478 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
4479 ETH_FILTERS_VLAN_ADD_FAIL_FULL,
4480 ETH_FILTERS_VLAN_ADD_FAIL_DUP,
4481 ETH_FILTERS_VLAN_DEL_FAIL_NOF,
4482 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
4483 ETH_FILTERS_PAIR_ADD_FAIL_DUP,
4484 ETH_FILTERS_PAIR_ADD_FAIL_FULL,
4485 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
4486 ETH_FILTERS_PAIR_DEL_FAIL_NOF,
4487 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
4488 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
4489 ETH_FILTERS_VNI_ADD_FAIL_FULL,
4490 ETH_FILTERS_VNI_ADD_FAIL_DUP,
4494 enum eth_event_opcode {
4496 ETH_EVENT_VPORT_START,
4497 ETH_EVENT_VPORT_UPDATE,
4498 ETH_EVENT_VPORT_STOP,
4499 ETH_EVENT_TX_QUEUE_START,
4500 ETH_EVENT_TX_QUEUE_STOP,
4501 ETH_EVENT_RX_QUEUE_START,
4502 ETH_EVENT_RX_QUEUE_UPDATE,
4503 ETH_EVENT_RX_QUEUE_STOP,
4504 ETH_EVENT_FILTERS_UPDATE,
4506 ETH_EVENT_RESERVED2,
4507 ETH_EVENT_RESERVED3,
4508 ETH_EVENT_RX_ADD_UDP_FILTER,
4509 ETH_EVENT_RX_DELETE_UDP_FILTER,
4510 ETH_EVENT_RESERVED4,
4511 ETH_EVENT_RESERVED5,
4512 MAX_ETH_EVENT_OPCODE
4515 /* Classify rule types in E2/E3 */
4516 enum eth_filter_action {
4517 ETH_FILTER_ACTION_UNUSED,
4518 ETH_FILTER_ACTION_REMOVE,
4519 ETH_FILTER_ACTION_ADD,
4520 ETH_FILTER_ACTION_REMOVE_ALL,
4521 MAX_ETH_FILTER_ACTION
4524 /* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */
4525 struct eth_filter_cmd {
4537 /* $$KEEP_ENDIANNESS$$ */
4538 struct eth_filter_cmd_header {
4546 /* Ethernet filter types: mac/vlan/pair */
4547 enum eth_filter_type {
4548 ETH_FILTER_TYPE_UNUSED,
4549 ETH_FILTER_TYPE_MAC,
4550 ETH_FILTER_TYPE_VLAN,
4551 ETH_FILTER_TYPE_PAIR,
4552 ETH_FILTER_TYPE_INNER_MAC,
4553 ETH_FILTER_TYPE_INNER_VLAN,
4554 ETH_FILTER_TYPE_INNER_PAIR,
4555 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
4556 ETH_FILTER_TYPE_MAC_VNI_PAIR,
4557 ETH_FILTER_TYPE_VNI,
4561 enum eth_ipv4_frag_type {
4563 ETH_IPV4_FIRST_FRAG,
4564 ETH_IPV4_NON_FIRST_FRAG,
4565 MAX_ETH_IPV4_FRAG_TYPE
4568 enum eth_ramrod_cmd_id {
4570 ETH_RAMROD_VPORT_START,
4571 ETH_RAMROD_VPORT_UPDATE,
4572 ETH_RAMROD_VPORT_STOP,
4573 ETH_RAMROD_RX_QUEUE_START,
4574 ETH_RAMROD_RX_QUEUE_STOP,
4575 ETH_RAMROD_TX_QUEUE_START,
4576 ETH_RAMROD_TX_QUEUE_STOP,
4577 ETH_RAMROD_FILTERS_UPDATE,
4578 ETH_RAMROD_RX_QUEUE_UPDATE,
4579 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
4580 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
4581 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
4582 ETH_RAMROD_RX_ADD_UDP_FILTER,
4583 ETH_RAMROD_RX_DELETE_UDP_FILTER,
4584 ETH_RAMROD_RX_CREATE_GFT_ACTION,
4585 ETH_RAMROD_GFT_UPDATE_FILTER,
4586 MAX_ETH_RAMROD_CMD_ID
4589 /* return code from eth sp ramrods */
4590 struct eth_return_code {
4592 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F
4593 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
4594 #define ETH_RETURN_CODE_RESERVED_MASK 0x3
4595 #define ETH_RETURN_CODE_RESERVED_SHIFT 5
4596 #define ETH_RETURN_CODE_RX_TX_MASK 0x1
4597 #define ETH_RETURN_CODE_RX_TX_SHIFT 7
4600 /* What to do in case an error occurs */
4603 ETH_TX_ERR_ASSERT_MALICIOUS,
4607 /* Array of the different error type behaviors */
4608 struct eth_tx_err_vals {
4610 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
4611 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
4612 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
4613 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
4614 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
4615 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
4616 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
4617 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
4618 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
4619 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
4620 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
4621 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
4622 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
4623 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
4624 #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF
4625 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7
4628 /* vport rss configuration data */
4629 struct eth_vport_rss_config {
4630 __le16 capabilities;
4631 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
4632 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
4633 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
4634 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
4635 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
4636 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
4637 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
4638 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
4639 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
4640 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
4641 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
4642 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
4643 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
4644 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
4645 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
4646 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
4650 u8 update_rss_ind_table;
4651 u8 update_rss_capabilities;
4653 __le32 reserved2[2];
4654 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
4656 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
4657 __le32 reserved3[2];
4660 /* eth vport RSS mode */
4661 enum eth_vport_rss_mode {
4662 ETH_VPORT_RSS_MODE_DISABLED,
4663 ETH_VPORT_RSS_MODE_REGULAR,
4664 MAX_ETH_VPORT_RSS_MODE
4667 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
4668 struct eth_vport_rx_mode {
4670 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
4671 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
4672 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
4673 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
4674 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
4675 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
4676 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
4677 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
4678 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
4679 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
4680 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
4681 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
4682 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF
4683 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6
4684 __le16 reserved2[3];
4687 /* Command for setting tpa parameters */
4688 struct eth_vport_tpa_param {
4691 u8 tpa_ipv4_tunn_en_flg;
4692 u8 tpa_ipv6_tunn_en_flg;
4693 u8 tpa_pkt_split_flg;
4694 u8 tpa_hdr_data_split_flg;
4695 u8 tpa_gro_consistent_flg;
4697 u8 tpa_max_aggs_num;
4699 __le16 tpa_max_size;
4700 __le16 tpa_min_size_to_start;
4702 __le16 tpa_min_size_to_cont;
4707 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
4708 struct eth_vport_tx_mode {
4710 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
4711 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
4712 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
4713 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
4714 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
4715 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
4716 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
4717 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
4718 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
4719 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
4720 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
4721 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
4722 __le16 reserved2[3];
4725 /* Ramrod data for rx queue start ramrod */
4726 struct rx_queue_start_ramrod_data {
4728 __le16 num_of_pbl_pages;
4729 __le16 bd_max_bytes;
4733 u8 default_rss_queue_flg;
4734 u8 complete_cqe_flg;
4735 u8 complete_event_flg;
4736 u8 stats_counter_id;
4738 u8 pxp_tph_valid_bd;
4739 u8 pxp_tph_valid_pkt;
4742 __le16 pxp_st_index;
4748 u8 vf_rx_prod_index;
4749 u8 vf_rx_prod_use_zone_a;
4752 struct regpair cqe_pbl_addr;
4753 struct regpair bd_base;
4754 struct regpair reserved2;
4757 /* Ramrod data for rx queue start ramrod */
4758 struct rx_queue_stop_ramrod_data {
4760 u8 complete_cqe_flg;
4761 u8 complete_event_flg;
4766 /* Ramrod data for rx queue update ramrod */
4767 struct rx_queue_update_ramrod_data {
4769 u8 complete_cqe_flg;
4770 u8 complete_event_flg;
4778 struct regpair reserved6;
4781 /* Ramrod data for rx Add UDP Filter */
4782 struct rx_udp_filter_data {
4786 u8 tenant_id_exists;
4788 __le32 ip_dst_addr[4];
4789 __le32 ip_src_addr[4];
4790 __le16 udp_dst_port;
4791 __le16 udp_src_port;
4795 /* Ramrod data for rx queue start ramrod */
4796 struct tx_queue_start_ramrod_data {
4801 u8 stats_counter_id;
4804 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
4805 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
4806 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
4807 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
4808 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
4809 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
4810 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
4811 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3
4812 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
4813 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4
4814 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
4815 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5
4816 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3
4817 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6
4819 u8 pxp_tph_valid_bd;
4820 u8 pxp_tph_valid_pkt;
4821 __le16 pxp_st_index;
4822 __le16 comp_agg_size;
4823 __le16 queue_zone_id;
4827 __le16 same_as_last_id;
4829 struct regpair pbl_base_addr;
4830 struct regpair bd_cons_address;
4833 /* Ramrod data for tx queue stop ramrod */
4834 struct tx_queue_stop_ramrod_data {
4838 /* Ramrod data for vport update ramrod */
4839 struct vport_filter_update_ramrod_data {
4840 struct eth_filter_cmd_header filter_cmd_hdr;
4841 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
4844 /* Ramrod data for vport start ramrod */
4845 struct vport_start_ramrod_data {
4850 u8 inner_vlan_removal_en;
4851 struct eth_vport_rx_mode rx_mode;
4852 struct eth_vport_tx_mode tx_mode;
4853 struct eth_vport_tpa_param tpa_param;
4854 __le16 default_vlan;
4856 u8 anti_spoofing_en;
4861 u8 silent_vlan_removal_en;
4863 struct eth_tx_err_vals tx_err_behav;
4865 u8 zero_placement_offset;
4866 u8 ctl_frame_mac_check_en;
4867 u8 ctl_frame_ethtype_check_en;
4871 /* Ramrod data for vport stop ramrod */
4872 struct vport_stop_ramrod_data {
4877 /* Ramrod data for vport update ramrod */
4878 struct vport_update_ramrod_data_cmn {
4880 u8 update_rx_active_flg;
4882 u8 update_tx_active_flg;
4884 u8 update_rx_mode_flg;
4885 u8 update_tx_mode_flg;
4886 u8 update_approx_mcast_flg;
4889 u8 update_inner_vlan_removal_en_flg;
4891 u8 inner_vlan_removal_en;
4892 u8 update_tpa_param_flg;
4893 u8 update_tpa_en_flg;
4894 u8 update_tx_switching_en_flg;
4897 u8 update_anti_spoofing_en_flg;
4899 u8 anti_spoofing_en;
4900 u8 update_handle_ptp_pkts;
4903 u8 update_default_vlan_en_flg;
4907 u8 update_default_vlan_flg;
4909 __le16 default_vlan;
4910 u8 update_accept_any_vlan_flg;
4913 u8 silent_vlan_removal_en;
4920 struct vport_update_ramrod_mcast {
4921 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
4924 /* Ramrod data for vport update ramrod */
4925 struct vport_update_ramrod_data {
4926 struct vport_update_ramrod_data_cmn common;
4928 struct eth_vport_rx_mode rx_mode;
4929 struct eth_vport_tx_mode tx_mode;
4930 struct eth_vport_tpa_param tpa_param;
4931 struct vport_update_ramrod_mcast approx_mcast;
4932 struct eth_vport_rss_config rss_config;
4935 struct mstorm_rdma_task_st_ctx {
4936 struct regpair temp[4];
4939 struct rdma_close_func_ramrod_data {
4940 u8 cnq_start_offset;
4947 struct rdma_cnq_params {
4952 struct regpair pbl_base_addr;
4953 __le16 queue_zone_num;
4957 struct rdma_create_cq_ramrod_data {
4958 struct regpair cq_handle;
4959 struct regpair pbl_addr;
4961 __le16 pbl_num_pages;
4963 u8 is_two_level_pbl;
4965 u8 pbl_log_page_size;
4971 struct rdma_deregister_tid_ramrod_data {
4976 struct rdma_destroy_cq_output_params {
4982 struct rdma_destroy_cq_ramrod_data {
4983 struct regpair output_params_addr;
4986 enum rdma_event_opcode {
4988 RDMA_EVENT_FUNC_INIT,
4989 RDMA_EVENT_FUNC_CLOSE,
4990 RDMA_EVENT_REGISTER_MR,
4991 RDMA_EVENT_DEREGISTER_MR,
4992 RDMA_EVENT_CREATE_CQ,
4993 RDMA_EVENT_RESIZE_CQ,
4994 RDMA_EVENT_DESTROY_CQ,
4995 RDMA_EVENT_CREATE_SRQ,
4996 RDMA_EVENT_MODIFY_SRQ,
4997 RDMA_EVENT_DESTROY_SRQ,
4998 MAX_RDMA_EVENT_OPCODE
5001 enum rdma_fw_return_code {
5003 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
5004 RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
5005 RDMA_RETURN_RESIZE_CQ_ERR,
5006 RDMA_RETURN_NIG_DRAIN_REQ,
5007 MAX_RDMA_FW_RETURN_CODE
5010 struct rdma_init_func_hdr {
5011 u8 cnq_start_offset;
5014 u8 cnp_vlan_priority;
5015 __le32 cnp_send_timeout;
5022 struct rdma_init_func_ramrod_data {
5023 struct rdma_init_func_hdr params_header;
5024 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
5027 enum rdma_ramrod_cmd_id {
5029 RDMA_RAMROD_FUNC_INIT,
5030 RDMA_RAMROD_FUNC_CLOSE,
5031 RDMA_RAMROD_REGISTER_MR,
5032 RDMA_RAMROD_DEREGISTER_MR,
5033 RDMA_RAMROD_CREATE_CQ,
5034 RDMA_RAMROD_RESIZE_CQ,
5035 RDMA_RAMROD_DESTROY_CQ,
5036 RDMA_RAMROD_CREATE_SRQ,
5037 RDMA_RAMROD_MODIFY_SRQ,
5038 RDMA_RAMROD_DESTROY_SRQ,
5039 MAX_RDMA_RAMROD_CMD_ID
5042 struct rdma_register_tid_ramrod_data {
5044 #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_MASK 0x3FFFF
5045 #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_SHIFT 0
5046 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F
5047 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 18
5048 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
5049 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 23
5050 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
5051 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 24
5052 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
5053 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 25
5054 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
5055 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 26
5056 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
5057 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 27
5058 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
5059 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 28
5060 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
5061 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 29
5062 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
5063 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 30
5064 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
5065 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 31
5067 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F
5068 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
5069 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7
5070 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5
5072 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1
5073 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0
5074 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1
5075 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1
5076 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F
5077 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2
5087 struct regpair pbl_base;
5088 struct regpair dif_error_addr;
5089 struct regpair dif_runt_addr;
5090 __le32 reserved3[2];
5093 struct rdma_resize_cq_output_params {
5098 struct rdma_resize_cq_ramrod_data {
5100 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1
5101 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
5102 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
5103 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
5104 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F
5105 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2
5106 u8 pbl_log_page_size;
5107 __le16 pbl_num_pages;
5109 struct regpair pbl_addr;
5110 struct regpair output_params_addr;
5113 struct rdma_srq_context {
5114 struct regpair temp[8];
5117 struct rdma_srq_create_ramrod_data {
5118 struct regpair pbl_base_addr;
5119 __le16 pages_in_srq_pbl;
5121 struct rdma_srq_id srq_id;
5125 struct regpair producers_addr;
5128 struct rdma_srq_destroy_ramrod_data {
5129 struct rdma_srq_id srq_id;
5133 struct rdma_srq_modify_ramrod_data {
5134 struct rdma_srq_id srq_id;
5138 struct ystorm_rdma_task_st_ctx {
5139 struct regpair temp[4];
5142 struct ystorm_rdma_task_ag_ctx {
5145 __le16 msem_ctx_upd_seq;
5147 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
5148 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
5149 #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5150 #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
5151 #define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5152 #define YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
5153 #define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
5154 #define YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
5155 #define YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
5156 #define YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
5158 #define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
5159 #define YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
5160 #define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
5161 #define YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
5162 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
5163 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
5164 #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
5165 #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
5166 #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
5167 #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
5169 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
5170 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
5171 #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5172 #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
5173 #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5174 #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
5175 #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5176 #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
5177 #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
5178 #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
5179 #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5180 #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
5181 #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
5182 #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
5183 #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5184 #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
5190 __le16 tx_ref_count;
5191 __le16 last_used_ltid;
5192 __le16 parent_mr_lo;
5193 __le16 parent_mr_hi;
5198 struct mstorm_rdma_task_ag_ctx {
5203 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
5204 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
5205 #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5206 #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
5207 #define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5208 #define MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
5209 #define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
5210 #define MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
5211 #define MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
5212 #define MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
5214 #define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
5215 #define MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
5216 #define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
5217 #define MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
5218 #define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
5219 #define MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
5220 #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
5221 #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
5222 #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
5223 #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
5225 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
5226 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
5227 #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5228 #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
5229 #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5230 #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
5231 #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5232 #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
5233 #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
5234 #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
5235 #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5236 #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
5237 #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
5238 #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
5239 #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5240 #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
5246 __le16 tx_ref_count;
5247 __le16 last_used_ltid;
5248 __le16 parent_mr_lo;
5249 __le16 parent_mr_hi;
5254 struct ustorm_rdma_task_st_ctx {
5255 struct regpair temp[2];
5258 struct ustorm_rdma_task_ag_ctx {
5263 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
5264 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
5265 #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5266 #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
5267 #define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1
5268 #define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5
5269 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
5270 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
5272 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
5273 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
5274 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
5275 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
5276 #define USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
5277 #define USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4
5278 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
5279 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
5281 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
5282 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
5283 #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
5284 #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
5285 #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
5286 #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
5287 #define USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
5288 #define USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3
5289 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
5290 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
5291 #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5292 #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
5293 #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5294 #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
5295 #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5296 #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
5298 #define USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
5299 #define USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0
5300 #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5301 #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
5302 #define USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
5303 #define USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2
5304 #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5305 #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
5306 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
5307 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
5308 __le32 dif_err_intervals;
5309 __le32 dif_error_1st_interval;
5311 __le32 dif_runt_value;
5316 struct rdma_task_context {
5317 struct ystorm_rdma_task_st_ctx ystorm_st_context;
5318 struct ystorm_rdma_task_ag_ctx ystorm_ag_context;
5319 struct tdif_task_context tdif_context;
5320 struct mstorm_rdma_task_ag_ctx mstorm_ag_context;
5321 struct mstorm_rdma_task_st_ctx mstorm_st_context;
5322 struct rdif_task_context rdif_context;
5323 struct ustorm_rdma_task_st_ctx ustorm_st_context;
5324 struct regpair ustorm_st_padding[2];
5325 struct ustorm_rdma_task_ag_ctx ustorm_ag_context;
5328 enum rdma_tid_type {
5329 RDMA_TID_REGISTERED_MR,
5336 struct mstorm_rdma_conn_ag_ctx {
5340 #define MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
5341 #define MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
5342 #define MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
5343 #define MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
5344 #define MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
5345 #define MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
5346 #define MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
5347 #define MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
5348 #define MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
5349 #define MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
5351 #define MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
5352 #define MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
5353 #define MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
5354 #define MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
5355 #define MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
5356 #define MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
5357 #define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
5358 #define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
5359 #define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
5360 #define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
5361 #define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
5362 #define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
5363 #define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
5364 #define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
5365 #define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
5366 #define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
5373 struct tstorm_rdma_conn_ag_ctx {
5377 #define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5378 #define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5379 #define TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
5380 #define TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
5381 #define TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
5382 #define TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
5383 #define TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1
5384 #define TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3
5385 #define TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
5386 #define TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
5387 #define TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
5388 #define TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
5389 #define TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
5390 #define TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6
5392 #define TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
5393 #define TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0
5394 #define TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
5395 #define TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2
5396 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
5397 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
5398 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
5399 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
5401 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
5402 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
5403 #define TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
5404 #define TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2
5405 #define TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3
5406 #define TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4
5407 #define TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
5408 #define TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6
5410 #define TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
5411 #define TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0
5412 #define TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
5413 #define TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2
5414 #define TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
5415 #define TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4
5416 #define TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
5417 #define TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5
5418 #define TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
5419 #define TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6
5420 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
5421 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
5423 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
5424 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
5425 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
5426 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
5427 #define TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
5428 #define TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2
5429 #define TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1
5430 #define TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3
5431 #define TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
5432 #define TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4
5433 #define TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
5434 #define TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5
5435 #define TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
5436 #define TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6
5437 #define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
5438 #define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7
5440 #define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
5441 #define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0
5442 #define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
5443 #define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
5444 #define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
5445 #define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
5446 #define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
5447 #define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
5448 #define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
5449 #define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
5450 #define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
5451 #define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
5452 #define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
5453 #define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
5454 #define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
5455 #define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
5477 struct tstorm_rdma_task_ag_ctx {
5482 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF
5483 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
5484 #define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1
5485 #define TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4
5486 #define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5487 #define TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
5488 #define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
5489 #define TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
5490 #define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
5491 #define TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
5493 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
5494 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
5495 #define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1
5496 #define TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1
5497 #define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
5498 #define TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2
5499 #define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
5500 #define TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4
5501 #define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
5502 #define TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6
5504 #define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
5505 #define TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
5506 #define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
5507 #define TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2
5508 #define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
5509 #define TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4
5510 #define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
5511 #define TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6
5513 #define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
5514 #define TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
5515 #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
5516 #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2
5517 #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
5518 #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3
5519 #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
5520 #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4
5521 #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
5522 #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5
5523 #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1
5524 #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6
5525 #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1
5526 #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7
5528 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1
5529 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
5530 #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1
5531 #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1
5532 #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5533 #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
5534 #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5535 #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
5536 #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5537 #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
5538 #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
5539 #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
5540 #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5541 #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
5542 #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
5543 #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
5556 struct ustorm_rdma_conn_ag_ctx {
5560 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5561 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5562 #define USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
5563 #define USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
5564 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
5565 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2
5566 #define USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
5567 #define USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
5568 #define USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
5569 #define USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
5571 #define USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
5572 #define USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
5573 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
5574 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
5575 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
5576 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
5577 #define USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
5578 #define USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6
5580 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
5581 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
5582 #define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
5583 #define USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
5584 #define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
5585 #define USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
5586 #define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
5587 #define USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3
5588 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
5589 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
5590 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
5591 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
5592 #define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
5593 #define USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6
5594 #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
5595 #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
5597 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1
5598 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
5599 #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
5600 #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
5601 #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
5602 #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
5603 #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
5604 #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
5605 #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
5606 #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
5607 #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
5608 #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
5609 #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
5610 #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
5611 #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
5612 #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
5625 struct xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
5629 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
5630 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
5631 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1
5632 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1
5633 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1
5634 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2
5635 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
5636 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
5637 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1
5638 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4
5639 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1
5640 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5
5641 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1
5642 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6
5643 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1
5644 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7
5646 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1
5647 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
5648 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1
5649 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1
5650 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1
5651 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
5652 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
5653 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
5654 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
5655 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
5656 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_MASK 0x1
5657 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
5658 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
5659 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6
5660 #define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
5661 #define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
5663 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
5664 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
5665 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
5666 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2
5667 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
5668 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4
5669 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
5670 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6
5672 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
5673 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
5674 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
5675 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2
5676 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
5677 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4
5678 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
5679 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6
5681 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
5682 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
5683 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
5684 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2
5685 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
5686 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4
5687 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
5688 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6
5690 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
5691 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
5692 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
5693 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2
5694 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
5695 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4
5696 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
5697 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6
5699 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
5700 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
5701 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
5702 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2
5703 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
5704 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4
5705 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
5706 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6
5708 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
5709 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
5710 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
5711 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2
5712 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
5713 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
5714 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
5715 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
5716 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
5717 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
5719 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
5720 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
5721 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
5722 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
5723 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
5724 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
5725 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
5726 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
5727 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
5728 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
5729 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1
5730 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5
5731 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
5732 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
5733 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
5734 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
5736 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
5737 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
5738 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
5739 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
5740 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
5741 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
5742 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
5743 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
5744 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
5745 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
5746 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
5747 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
5748 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1
5749 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6
5750 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1
5751 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7
5753 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1
5754 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
5755 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1
5756 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1
5757 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1
5758 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2
5759 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1
5760 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3
5761 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
5762 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
5763 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1
5764 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5
5765 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1
5766 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6
5767 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1
5768 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7
5770 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1
5771 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
5772 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1
5773 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1
5774 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1
5775 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2
5776 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
5777 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
5778 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
5779 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
5780 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
5781 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
5782 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
5783 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
5784 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
5785 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
5787 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
5788 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
5789 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
5790 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
5791 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
5792 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
5793 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
5794 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
5795 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
5796 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
5797 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
5798 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
5799 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
5800 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
5801 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
5802 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
5804 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
5805 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
5806 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
5807 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
5808 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
5809 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
5810 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
5811 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
5812 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
5813 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
5814 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
5815 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
5816 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
5817 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
5818 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
5819 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
5821 #define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1
5822 #define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
5823 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1
5824 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1
5825 #define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
5826 #define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2
5827 #define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1
5828 #define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4
5829 #define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
5830 #define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
5831 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
5832 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6
5852 struct xstorm_rdma_conn_ag_ctx {
5856 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5857 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5858 #define XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
5859 #define XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
5860 #define XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
5861 #define XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
5862 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
5863 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
5864 #define XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
5865 #define XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
5866 #define XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
5867 #define XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
5868 #define XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1
5869 #define XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6
5870 #define XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1
5871 #define XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7
5873 #define XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1
5874 #define XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0
5875 #define XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1
5876 #define XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1
5877 #define XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1
5878 #define XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2
5879 #define XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1
5880 #define XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3
5881 #define XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1
5882 #define XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4
5883 #define XSTORM_RDMA_CONN_AG_CTX_BIT13_MASK 0x1
5884 #define XSTORM_RDMA_CONN_AG_CTX_BIT13_SHIFT 5
5885 #define XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1
5886 #define XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6
5887 #define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
5888 #define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
5890 #define XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
5891 #define XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0
5892 #define XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
5893 #define XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2
5894 #define XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
5895 #define XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4
5896 #define XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
5897 #define XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6
5899 #define XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3
5900 #define XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0
5901 #define XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3
5902 #define XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2
5903 #define XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
5904 #define XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4
5905 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
5906 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
5908 #define XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
5909 #define XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0
5910 #define XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
5911 #define XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2
5912 #define XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
5913 #define XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4
5914 #define XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3
5915 #define XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6
5917 #define XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3
5918 #define XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0
5919 #define XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3
5920 #define XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2
5921 #define XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3
5922 #define XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4
5923 #define XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3
5924 #define XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6
5926 #define XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3
5927 #define XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0
5928 #define XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3
5929 #define XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2
5930 #define XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3
5931 #define XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4
5932 #define XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3
5933 #define XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6
5935 #define XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3
5936 #define XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0
5937 #define XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3
5938 #define XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2
5939 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3
5940 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4
5941 #define XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
5942 #define XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6
5943 #define XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
5944 #define XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7
5946 #define XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
5947 #define XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0
5948 #define XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
5949 #define XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1
5950 #define XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1
5951 #define XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2
5952 #define XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1
5953 #define XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3
5954 #define XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
5955 #define XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4
5956 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
5957 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
5958 #define XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
5959 #define XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6
5960 #define XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
5961 #define XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7
5963 #define XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
5964 #define XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0
5965 #define XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1
5966 #define XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1
5967 #define XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1
5968 #define XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2
5969 #define XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1
5970 #define XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3
5971 #define XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1
5972 #define XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4
5973 #define XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1
5974 #define XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5
5975 #define XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1
5976 #define XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6
5977 #define XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1
5978 #define XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7
5980 #define XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1
5981 #define XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0
5982 #define XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1
5983 #define XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1
5984 #define XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1
5985 #define XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2
5986 #define XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1
5987 #define XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3
5988 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
5989 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
5990 #define XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1
5991 #define XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5
5992 #define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
5993 #define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6
5994 #define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
5995 #define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7
5997 #define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
5998 #define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0
5999 #define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6000 #define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1
6001 #define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6002 #define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2
6003 #define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
6004 #define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3
6005 #define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
6006 #define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4
6007 #define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
6008 #define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5
6009 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
6010 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
6011 #define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1
6012 #define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7
6014 #define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1
6015 #define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0
6016 #define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1
6017 #define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1
6018 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
6019 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
6020 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
6021 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
6022 #define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1
6023 #define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4
6024 #define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1
6025 #define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5
6026 #define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1
6027 #define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6
6028 #define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1
6029 #define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7
6031 #define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1
6032 #define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0
6033 #define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1
6034 #define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1
6035 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
6036 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
6037 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
6038 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
6039 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
6040 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
6041 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
6042 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
6043 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
6044 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
6045 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
6046 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
6048 #define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1
6049 #define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0
6050 #define XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1
6051 #define XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1
6052 #define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
6053 #define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
6054 #define XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1
6055 #define XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4
6056 #define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
6057 #define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
6058 #define XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3
6059 #define XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6
6081 struct ystorm_rdma_conn_ag_ctx {
6085 #define YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
6086 #define YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
6087 #define YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
6088 #define YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
6089 #define YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
6090 #define YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
6091 #define YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6092 #define YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
6093 #define YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6094 #define YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
6096 #define YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
6097 #define YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
6098 #define YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6099 #define YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
6100 #define YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6101 #define YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
6102 #define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
6103 #define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
6104 #define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
6105 #define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
6106 #define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6107 #define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
6108 #define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6109 #define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
6110 #define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6111 #define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
6125 struct mstorm_roce_conn_st_ctx {
6126 struct regpair temp[6];
6129 struct pstorm_roce_conn_st_ctx {
6130 struct regpair temp[16];
6133 struct ystorm_roce_conn_st_ctx {
6134 struct regpair temp[2];
6137 struct xstorm_roce_conn_st_ctx {
6138 struct regpair temp[22];
6141 struct tstorm_roce_conn_st_ctx {
6142 struct regpair temp[30];
6145 struct ustorm_roce_conn_st_ctx {
6146 struct regpair temp[12];
6149 struct roce_conn_context {
6150 struct ystorm_roce_conn_st_ctx ystorm_st_context;
6151 struct regpair ystorm_st_padding[2];
6152 struct pstorm_roce_conn_st_ctx pstorm_st_context;
6153 struct xstorm_roce_conn_st_ctx xstorm_st_context;
6154 struct regpair xstorm_st_padding[2];
6155 struct xstorm_rdma_conn_ag_ctx xstorm_ag_context;
6156 struct tstorm_rdma_conn_ag_ctx tstorm_ag_context;
6157 struct timers_context timer_context;
6158 struct ustorm_rdma_conn_ag_ctx ustorm_ag_context;
6159 struct tstorm_roce_conn_st_ctx tstorm_st_context;
6160 struct mstorm_roce_conn_st_ctx mstorm_st_context;
6161 struct ustorm_roce_conn_st_ctx ustorm_st_context;
6162 struct regpair ustorm_st_padding[2];
6165 struct roce_create_qp_req_ramrod_data {
6167 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
6168 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
6169 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
6170 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2
6171 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
6172 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3
6173 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
6174 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4
6175 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1
6176 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 7
6177 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
6178 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8
6179 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
6180 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12
6188 __le32 ack_timeout_val;
6192 __le16 sq_num_pages;
6194 struct regpair sq_pbl_addr;
6195 struct regpair orq_pbl_addr;
6196 __le16 local_mac_addr[3];
6197 __le16 remote_mac_addr[3];
6199 __le16 udp_src_port;
6202 struct regpair qp_handle_for_cqe;
6203 struct regpair qp_handle_for_async;
6204 u8 stats_counter_id;
6207 __le16 physical_queue0;
6211 struct roce_create_qp_resp_ramrod_data {
6213 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
6214 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
6215 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
6216 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
6217 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
6218 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
6219 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
6220 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
6221 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
6222 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5
6223 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
6224 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6
6225 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
6226 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7
6227 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
6228 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8
6229 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
6230 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11
6238 u8 stats_counter_id;
6243 __le16 rq_num_pages;
6244 struct rdma_srq_id srq_id;
6245 struct regpair rq_pbl_addr;
6246 struct regpair irq_pbl_addr;
6247 __le16 local_mac_addr[3];
6248 __le16 remote_mac_addr[3];
6250 __le16 udp_src_port;
6253 struct regpair qp_handle_for_cqe;
6254 struct regpair qp_handle_for_async;
6255 __le32 reserved2[2];
6257 __le16 physical_queue0;
6261 struct roce_destroy_qp_req_output_params {
6262 __le32 num_bound_mw;
6266 struct roce_destroy_qp_req_ramrod_data {
6267 struct regpair output_params_addr;
6270 struct roce_destroy_qp_resp_output_params {
6271 __le32 num_invalidated_mw;
6275 struct roce_destroy_qp_resp_ramrod_data {
6276 struct regpair output_params_addr;
6279 enum roce_event_opcode {
6280 ROCE_EVENT_CREATE_QP = 11,
6281 ROCE_EVENT_MODIFY_QP,
6282 ROCE_EVENT_QUERY_QP,
6283 ROCE_EVENT_DESTROY_QP,
6284 MAX_ROCE_EVENT_OPCODE
6287 struct roce_init_func_ramrod_data {
6288 struct rdma_init_func_ramrod_data rdma;
6291 struct roce_modify_qp_req_ramrod_data {
6293 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
6294 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
6295 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1
6296 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1
6297 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1
6298 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2
6299 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1
6300 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3
6301 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
6302 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4
6303 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1
6304 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5
6305 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1
6306 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6
6307 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1
6308 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7
6309 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1
6310 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8
6311 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1
6312 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9
6313 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
6314 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10
6315 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x7
6316 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 13
6318 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
6319 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0
6320 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
6321 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4
6327 __le32 ack_timeout_val;
6330 __le32 reserved3[3];
6335 struct roce_modify_qp_resp_ramrod_data {
6337 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
6338 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
6339 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
6340 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1
6341 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
6342 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2
6343 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
6344 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3
6345 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1
6346 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4
6347 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
6348 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5
6349 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1
6350 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6
6351 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1
6352 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7
6353 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1
6354 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8
6355 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
6356 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9
6357 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x3F
6358 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 10
6360 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
6361 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0
6362 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
6363 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3
6375 struct roce_query_qp_req_output_params {
6378 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
6379 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
6380 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1
6381 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1
6382 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF
6383 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2
6386 struct roce_query_qp_req_ramrod_data {
6387 struct regpair output_params_addr;
6390 struct roce_query_qp_resp_output_params {
6393 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
6394 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
6395 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
6396 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
6399 struct roce_query_qp_resp_ramrod_data {
6400 struct regpair output_params_addr;
6403 enum roce_ramrod_cmd_id {
6404 ROCE_RAMROD_CREATE_QP = 11,
6405 ROCE_RAMROD_MODIFY_QP,
6406 ROCE_RAMROD_QUERY_QP,
6407 ROCE_RAMROD_DESTROY_QP,
6408 MAX_ROCE_RAMROD_CMD_ID
6411 struct mstorm_roce_req_conn_ag_ctx {
6415 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
6416 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
6417 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
6418 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
6419 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
6420 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
6421 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
6422 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
6423 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
6424 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
6426 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
6427 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
6428 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
6429 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
6430 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
6431 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
6432 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
6433 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
6434 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
6435 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
6436 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
6437 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
6438 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
6439 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
6440 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
6441 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
6448 struct mstorm_roce_resp_conn_ag_ctx {
6452 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
6453 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
6454 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
6455 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
6456 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
6457 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
6458 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
6459 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
6460 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
6461 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
6463 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
6464 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
6465 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
6466 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
6467 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
6468 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
6469 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
6470 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
6471 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
6472 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
6473 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
6474 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
6475 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
6476 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
6477 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
6478 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
6486 PLAIN_ROCE /* RoCE v1 */ ,
6487 RROCE_IPV4 /* RoCE v2 (Routable RoCE) over ipv4 */ ,
6488 RROCE_IPV6 /* RoCE v2 (Routable RoCE) over ipv6 */ ,
6492 struct tstorm_roce_req_conn_ag_ctx {
6496 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6497 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6498 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1
6499 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1
6500 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1
6501 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2
6502 #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1
6503 #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3
6504 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
6505 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
6506 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
6507 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
6508 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
6509 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6
6511 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
6512 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0
6513 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
6514 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2
6515 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
6516 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
6517 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6518 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
6520 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
6521 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
6522 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
6523 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2
6524 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
6525 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4
6526 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
6527 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6
6529 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
6530 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
6531 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
6532 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2
6533 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1
6534 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4
6535 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
6536 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5
6537 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1
6538 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6
6539 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
6540 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
6542 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6543 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
6544 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
6545 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
6546 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1
6547 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2
6548 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1
6549 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3
6550 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1
6551 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4
6552 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1
6553 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
6554 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1
6555 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6
6556 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
6557 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
6559 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
6560 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
6561 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
6562 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
6563 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
6564 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
6565 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
6566 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
6567 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
6568 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
6569 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1
6570 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5
6571 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
6572 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
6573 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
6574 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
6584 u8 tx_cqe_error_type;
6586 __le16 snd_sq_cons_th;
6596 struct tstorm_roce_resp_conn_ag_ctx {
6600 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6601 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6602 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
6603 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
6604 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1
6605 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2
6606 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1
6607 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3
6608 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
6609 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
6610 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1
6611 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5
6612 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
6613 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6
6615 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
6616 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
6617 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
6618 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2
6619 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
6620 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4
6621 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6622 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
6624 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
6625 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
6626 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
6627 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2
6628 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
6629 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4
6630 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
6631 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6
6633 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
6634 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
6635 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
6636 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2
6637 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
6638 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4
6639 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
6640 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5
6641 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1
6642 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6
6643 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
6644 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7
6646 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6647 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
6648 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
6649 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
6650 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
6651 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2
6652 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1
6653 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3
6654 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
6655 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4
6656 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
6657 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5
6658 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
6659 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6
6660 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
6661 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
6663 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
6664 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
6665 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
6666 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
6667 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
6668 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
6669 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
6670 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
6671 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
6672 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
6673 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1
6674 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5
6675 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
6676 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
6677 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
6678 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
6679 __le32 psn_and_rxmit_id_echo;
6688 u8 tx_async_error_type;
6696 __le32 num_invlidated_mw;
6700 struct ustorm_roce_req_conn_ag_ctx {
6704 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
6705 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
6706 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
6707 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
6708 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
6709 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
6710 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
6711 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
6712 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
6713 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
6715 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
6716 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
6717 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
6718 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2
6719 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
6720 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4
6721 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
6722 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6
6724 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
6725 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
6726 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
6727 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
6728 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
6729 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
6730 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
6731 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3
6732 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1
6733 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4
6734 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1
6735 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5
6736 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1
6737 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6
6738 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
6739 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
6741 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
6742 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
6743 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
6744 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
6745 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
6746 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
6747 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
6748 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
6749 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
6750 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
6751 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
6752 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5
6753 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
6754 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
6755 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
6756 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
6769 struct ustorm_roce_resp_conn_ag_ctx {
6773 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
6774 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
6775 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
6776 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
6777 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
6778 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
6779 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
6780 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
6781 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
6782 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
6784 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
6785 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
6786 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
6787 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2
6788 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
6789 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4
6790 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
6791 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6
6793 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
6794 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
6795 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
6796 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
6797 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
6798 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
6799 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
6800 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3
6801 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1
6802 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4
6803 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1
6804 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5
6805 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
6806 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6
6807 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
6808 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
6810 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
6811 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
6812 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
6813 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
6814 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
6815 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
6816 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
6817 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
6818 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
6819 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
6820 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
6821 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5
6822 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
6823 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
6824 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
6825 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
6838 struct xstorm_roce_req_conn_ag_ctx {
6842 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6843 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6844 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1
6845 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1
6846 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1
6847 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2
6848 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
6849 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
6850 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1
6851 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4
6852 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1
6853 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5
6854 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1
6855 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6
6856 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1
6857 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7
6859 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1
6860 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
6861 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1
6862 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1
6863 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1
6864 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2
6865 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
6866 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3
6867 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1
6868 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4
6869 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1
6870 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5
6871 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
6872 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6
6873 #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
6874 #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
6876 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
6877 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
6878 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
6879 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2
6880 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
6881 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4
6882 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
6883 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6
6885 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
6886 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
6887 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
6888 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
6889 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
6890 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4
6891 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6892 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
6894 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3
6895 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0
6896 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3
6897 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2
6898 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
6899 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4
6900 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
6901 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6
6903 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
6904 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
6905 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
6906 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2
6907 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
6908 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4
6909 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
6910 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6
6912 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
6913 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
6914 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
6915 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2
6916 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
6917 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4
6918 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
6919 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6
6921 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
6922 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
6923 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
6924 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2
6925 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
6926 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4
6927 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
6928 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6
6929 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
6930 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7
6932 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
6933 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
6934 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
6935 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1
6936 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
6937 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2
6938 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
6939 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
6940 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1
6941 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4
6942 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6943 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
6944 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1
6945 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6
6946 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1
6947 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7
6949 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1
6950 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
6951 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1
6952 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1
6953 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1
6954 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2
6955 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1
6956 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3
6957 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1
6958 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4
6959 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1
6960 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5
6961 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1
6962 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6
6963 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1
6964 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7
6966 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1
6967 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
6968 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1
6969 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1
6970 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1
6971 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2
6972 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1
6973 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3
6974 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
6975 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
6976 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1
6977 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5
6978 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
6979 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6
6980 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
6981 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7
6983 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
6984 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
6985 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
6986 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1
6987 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
6988 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2
6989 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
6990 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3
6991 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
6992 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4
6993 #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1
6994 #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
6995 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
6996 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
6997 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1
6998 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7
7000 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1
7001 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
7002 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1
7003 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1
7004 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
7005 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
7006 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
7007 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
7008 #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1
7009 #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4
7010 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1
7011 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5
7012 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1
7013 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6
7014 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1
7015 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7
7017 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1
7018 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
7019 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1
7020 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1
7021 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
7022 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
7023 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
7024 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
7025 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
7026 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
7027 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
7028 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
7029 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
7030 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
7031 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
7032 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
7034 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1
7035 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
7036 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1
7037 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1
7038 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
7039 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
7040 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1
7041 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4
7042 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
7043 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
7044 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
7045 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6
7067 struct xstorm_roce_resp_conn_ag_ctx {
7071 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7072 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7073 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1
7074 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1
7075 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1
7076 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2
7077 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
7078 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
7079 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1
7080 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4
7081 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1
7082 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5
7083 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1
7084 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6
7085 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1
7086 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7
7088 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1
7089 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
7090 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1
7091 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1
7092 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1
7093 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2
7094 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
7095 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3
7096 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1
7097 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4
7098 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1
7099 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5
7100 #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
7101 #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6
7102 #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
7103 #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
7105 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7106 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
7107 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
7108 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2
7109 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
7110 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4
7111 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
7112 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6
7114 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
7115 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
7116 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
7117 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
7118 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
7119 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4
7120 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7121 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7123 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
7124 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
7125 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
7126 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2
7127 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
7128 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4
7129 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
7130 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6
7132 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
7133 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
7134 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
7135 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2
7136 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
7137 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4
7138 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
7139 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6
7141 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
7142 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
7143 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
7144 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2
7145 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
7146 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4
7147 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
7148 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6
7150 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
7151 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
7152 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
7153 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2
7154 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
7155 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
7156 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7157 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6
7158 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
7159 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7
7161 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
7162 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
7163 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
7164 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1
7165 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1
7166 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2
7167 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
7168 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
7169 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1
7170 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4
7171 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7172 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
7173 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
7174 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6
7175 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
7176 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7
7178 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
7179 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
7180 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1
7181 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1
7182 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1
7183 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2
7184 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1
7185 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3
7186 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1
7187 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4
7188 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1
7189 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5
7190 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1
7191 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6
7192 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1
7193 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7
7195 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1
7196 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
7197 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1
7198 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1
7199 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1
7200 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2
7201 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1
7202 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3
7203 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
7204 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
7205 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1
7206 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5
7207 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7208 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6
7209 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7210 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7
7212 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7213 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
7214 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7215 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1
7216 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7217 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2
7218 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
7219 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3
7220 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
7221 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4
7222 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
7223 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5
7224 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
7225 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
7226 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1
7227 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7
7229 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_MASK 0x1
7230 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_SHIFT 0
7231 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1
7232 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 1
7233 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
7234 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
7235 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
7236 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
7237 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1
7238 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4
7239 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1
7240 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5
7241 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1
7242 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6
7243 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1
7244 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7
7246 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1
7247 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
7248 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1
7249 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1
7250 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
7251 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
7252 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
7253 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
7254 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
7255 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
7256 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
7257 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
7258 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
7259 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
7260 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
7261 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
7263 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1
7264 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
7265 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1
7266 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1
7267 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1
7268 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2
7269 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1
7270 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3
7271 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1
7272 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4
7273 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1
7274 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5
7275 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
7276 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6
7289 __le32 rxmit_psn_and_id;
7290 __le32 rxmit_bytes_length;
7295 __le32 msn_and_syndrome;
7298 struct ystorm_roce_req_conn_ag_ctx {
7302 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7303 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
7304 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7305 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
7306 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7307 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
7308 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7309 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
7310 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7311 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
7313 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7314 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
7315 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7316 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
7317 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7318 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
7319 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7320 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
7321 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7322 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
7323 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7324 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
7325 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7326 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
7327 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7328 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
7342 struct ystorm_roce_resp_conn_ag_ctx {
7346 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
7347 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
7348 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
7349 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
7350 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7351 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
7352 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
7353 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
7354 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
7355 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
7357 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7358 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
7359 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
7360 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
7361 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
7362 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
7363 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7364 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
7365 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7366 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
7367 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7368 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
7369 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7370 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
7371 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7372 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
7386 struct ystorm_iscsi_conn_st_ctx {
7390 struct pstorm_iscsi_tcp_conn_st_ctx {
7395 struct xstorm_iscsi_tcp_conn_st_ctx {
7396 __le32 reserved_iscsi[40];
7397 __le32 reserved_tcp[4];
7400 struct xstorm_iscsi_conn_ag_ctx {
7404 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7405 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7406 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
7407 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
7408 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1
7409 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2
7410 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
7411 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
7412 #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
7413 #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
7414 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1
7415 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5
7416 #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1
7417 #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6
7418 #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1
7419 #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7
7421 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1
7422 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0
7423 #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1
7424 #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1
7425 #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1
7426 #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2
7427 #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1
7428 #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3
7429 #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1
7430 #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4
7431 #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1
7432 #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5
7433 #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1
7434 #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6
7435 #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1
7436 #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7
7438 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
7439 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0
7440 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
7441 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2
7442 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
7443 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4
7444 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
7445 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
7447 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
7448 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0
7449 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
7450 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2
7451 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
7452 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4
7453 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
7454 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6
7456 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
7457 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0
7458 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
7459 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2
7460 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
7461 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4
7462 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
7463 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6
7465 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
7466 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0
7467 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
7468 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2
7469 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
7470 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4
7471 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
7472 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6
7474 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
7475 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0
7476 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
7477 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2
7478 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
7479 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4
7480 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
7481 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
7483 #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
7484 #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
7485 #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
7486 #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q1_SHIFT 2
7487 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
7488 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4
7489 #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
7490 #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6
7491 #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
7492 #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7
7494 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
7495 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0
7496 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
7497 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
7498 #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
7499 #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2
7500 #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
7501 #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3
7502 #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
7503 #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4
7504 #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
7505 #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5
7506 #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
7507 #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6
7508 #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1
7509 #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7
7511 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
7512 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0
7513 #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1
7514 #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1
7515 #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1
7516 #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2
7517 #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1
7518 #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3
7519 #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1
7520 #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4
7521 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1
7522 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5
7523 #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1
7524 #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6
7525 #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1
7526 #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7
7528 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1
7529 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0
7530 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
7531 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
7532 #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
7533 #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
7534 #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
7535 #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3
7536 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
7537 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
7538 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1
7539 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5
7540 #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
7541 #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6
7542 #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1
7543 #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7
7545 #define XSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
7546 #define XSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 0
7547 #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
7548 #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1
7549 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1
7550 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2
7551 #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
7552 #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3
7553 #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
7554 #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4
7555 #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
7556 #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5
7557 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
7558 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
7559 #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1
7560 #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7
7562 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1
7563 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0
7564 #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1
7565 #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1
7566 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
7567 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
7568 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
7569 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
7570 #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1
7571 #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4
7572 #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1
7573 #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5
7574 #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1
7575 #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6
7576 #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1
7577 #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7
7579 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1
7580 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0
7581 #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1
7582 #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1
7583 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
7584 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
7585 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
7586 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
7587 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
7588 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
7589 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
7590 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
7591 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
7592 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
7593 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
7594 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
7596 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1
7597 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0
7598 #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1
7599 #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1
7600 #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1
7601 #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2
7602 #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1
7603 #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3
7604 #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1
7605 #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4
7606 #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1
7607 #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5
7608 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
7609 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6
7613 __le16 dummy_dorq_var;
7617 __le16 slow_io_total_data_tx_update;
7625 __le32 more_to_send_seq;
7628 __le32 hq_scan_next_relevant_ack;
7634 __le32 bytes_to_next_pdu;
7657 struct tstorm_iscsi_conn_ag_ctx {
7661 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7662 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7663 #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
7664 #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
7665 #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1
7666 #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2
7667 #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1
7668 #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3
7669 #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
7670 #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
7671 #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1
7672 #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5
7673 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
7674 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6
7676 #define TSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
7677 #define TSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 0
7678 #define TSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
7679 #define TSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 2
7680 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
7681 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
7682 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
7683 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6
7685 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
7686 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0
7687 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
7688 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2
7689 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
7690 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4
7691 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
7692 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6
7694 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
7695 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
7696 #define TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
7697 #define TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 2
7698 #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
7699 #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4
7700 #define TSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
7701 #define TSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 5
7702 #define TSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
7703 #define TSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 6
7704 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
7705 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
7707 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
7708 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0
7709 #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
7710 #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1
7711 #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
7712 #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2
7713 #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
7714 #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3
7715 #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
7716 #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4
7717 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
7718 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
7719 #define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
7720 #define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 6
7721 #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
7722 #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
7724 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
7725 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
7726 #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
7727 #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
7728 #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
7729 #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
7730 #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
7731 #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
7732 #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
7733 #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
7734 #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
7735 #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
7736 #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
7737 #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
7738 #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
7739 #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
7754 struct ustorm_iscsi_conn_ag_ctx {
7758 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
7759 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
7760 #define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
7761 #define USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
7762 #define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
7763 #define USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
7764 #define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
7765 #define USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
7766 #define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
7767 #define USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
7769 #define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
7770 #define USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0
7771 #define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
7772 #define USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2
7773 #define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
7774 #define USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4
7775 #define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
7776 #define USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6
7778 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
7779 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
7780 #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
7781 #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
7782 #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
7783 #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
7784 #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1
7785 #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3
7786 #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
7787 #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4
7788 #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
7789 #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5
7790 #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
7791 #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6
7792 #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
7793 #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
7795 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
7796 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
7797 #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
7798 #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
7799 #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
7800 #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
7801 #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
7802 #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
7803 #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
7804 #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
7805 #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
7806 #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
7807 #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
7808 #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
7809 #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
7810 #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
7823 struct tstorm_iscsi_conn_st_ctx {
7824 __le32 reserved[40];
7827 struct mstorm_iscsi_conn_ag_ctx {
7831 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
7832 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
7833 #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
7834 #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
7835 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
7836 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
7837 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
7838 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
7839 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
7840 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
7842 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
7843 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
7844 #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
7845 #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
7846 #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
7847 #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
7848 #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
7849 #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
7850 #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
7851 #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
7852 #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
7853 #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
7854 #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
7855 #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
7856 #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
7857 #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
7864 struct mstorm_iscsi_tcp_conn_st_ctx {
7865 __le32 reserved_tcp[20];
7866 __le32 reserved_iscsi[8];
7869 struct ustorm_iscsi_conn_st_ctx {
7870 __le32 reserved[52];
7873 struct iscsi_conn_context {
7874 struct ystorm_iscsi_conn_st_ctx ystorm_st_context;
7875 struct regpair ystorm_st_padding[2];
7876 struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context;
7877 struct regpair pstorm_st_padding[2];
7878 struct pb_context xpb2_context;
7879 struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context;
7880 struct regpair xstorm_st_padding[2];
7881 struct xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
7882 struct tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
7883 struct regpair tstorm_ag_padding[2];
7884 struct timers_context timer_context;
7885 struct ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
7886 struct pb_context upb_context;
7887 struct tstorm_iscsi_conn_st_ctx tstorm_st_context;
7888 struct regpair tstorm_st_padding[2];
7889 struct mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
7890 struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context;
7891 struct ustorm_iscsi_conn_st_ctx ustorm_st_context;
7894 struct iscsi_init_ramrod_params {
7895 struct iscsi_spe_func_init iscsi_init_spe;
7896 struct tcp_init_params tcp_init;
7899 struct ystorm_iscsi_conn_ag_ctx {
7903 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
7904 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
7905 #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
7906 #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
7907 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
7908 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
7909 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
7910 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
7911 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
7912 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
7914 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
7915 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
7916 #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
7917 #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
7918 #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
7919 #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
7920 #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
7921 #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
7922 #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
7923 #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
7924 #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
7925 #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
7926 #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
7927 #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
7928 #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
7929 #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
7943 #define MFW_TRACE_SIGNATURE 0x25071946
7945 /* The trace in the buffer */
7946 #define MFW_TRACE_EVENTID_MASK 0x00ffff
7947 #define MFW_TRACE_PRM_SIZE_MASK 0x0f0000
7948 #define MFW_TRACE_PRM_SIZE_SHIFT 16
7949 #define MFW_TRACE_ENTRY_SIZE 3
7952 u32 signature; /* Help to identify that the trace is valid */
7953 u32 size; /* the size of the trace buffer in bytes */
7954 u32 curr_level; /* 2 - all will be written to the buffer
7955 * 1 - debug trace will not be written
7956 * 0 - just errors will be written to the buffer
7958 u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means
7962 /* Warning: the following pointers are assumed to be 32bits as they are
7963 * used only in the MFW.
7965 u32 trace_prod; /* The next trace will be written to this offset */
7966 u32 trace_oldest; /* The oldest valid trace starts at this offset
7967 * (usually very close after the current producer).
7971 #define VF_MAX_STATIC 192
7973 #define MCP_GLOB_PATH_MAX 2
7974 #define MCP_PORT_MAX 2
7975 #define MCP_GLOB_PORT_MAX 4
7976 #define MCP_GLOB_FUNC_MAX 16
7978 typedef u32 offsize_t; /* In DWORDS !!! */
7979 /* Offset from the beginning of the MCP scratchpad */
7980 #define OFFSIZE_OFFSET_SHIFT 0
7981 #define OFFSIZE_OFFSET_MASK 0x0000ffff
7982 /* Size of specific element (not the whole array if any) */
7983 #define OFFSIZE_SIZE_SHIFT 16
7984 #define OFFSIZE_SIZE_MASK 0xffff0000
7986 #define SECTION_OFFSET(_offsize) ((((_offsize & \
7987 OFFSIZE_OFFSET_MASK) >> \
7988 OFFSIZE_OFFSET_SHIFT) << 2))
7990 #define QED_SECTION_SIZE(_offsize) (((_offsize & \
7991 OFFSIZE_SIZE_MASK) >> \
7992 OFFSIZE_SIZE_SHIFT) << 2)
7994 #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + \
7995 SECTION_OFFSET(_offsize) + \
7996 (QED_SECTION_SIZE(_offsize) * idx))
7998 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \
7999 (_pub_base + offsetof(struct mcp_public_data, sections[_section]))
8001 /* PHY configuration */
8002 struct eth_phy_cfg {
8004 #define ETH_SPEED_AUTONEG 0
8005 #define ETH_SPEED_SMARTLINQ 0x8
8008 #define ETH_PAUSE_NONE 0x0
8009 #define ETH_PAUSE_AUTONEG 0x1
8010 #define ETH_PAUSE_RX 0x2
8011 #define ETH_PAUSE_TX 0x4
8015 #define ETH_LOOPBACK_NONE (0)
8016 #define ETH_LOOPBACK_INT_PHY (1)
8017 #define ETH_LOOPBACK_EXT_PHY (2)
8018 #define ETH_LOOPBACK_EXT (3)
8019 #define ETH_LOOPBACK_MAC (4)
8021 u32 feature_config_flags;
8022 #define ETH_EEE_MODE_ADV_LPI (1 << 0)
8025 struct port_mf_cfg {
8027 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
8028 #define PORT_MF_CFG_OV_TAG_SHIFT 0
8029 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
8083 u64 brb_truncate[8];
8088 struct brb_stats brb;
8089 struct eth_stats eth;
8092 struct couple_mode_teaming {
8093 u8 port_cmt[MCP_GLOB_PORT_MAX];
8094 #define PORT_CMT_IN_TEAM (1 << 0)
8096 #define PORT_CMT_PORT_ROLE (1 << 1)
8097 #define PORT_CMT_PORT_INACTIVE (0 << 1)
8098 #define PORT_CMT_PORT_ACTIVE (1 << 1)
8100 #define PORT_CMT_TEAM_MASK (1 << 2)
8101 #define PORT_CMT_TEAM0 (0 << 2)
8102 #define PORT_CMT_TEAM1 (1 << 2)
8105 #define LLDP_CHASSIS_ID_STAT_LEN 4
8106 #define LLDP_PORT_ID_STAT_LEN 4
8107 #define DCBX_MAX_APP_PROTOCOL 32
8108 #define MAX_SYSTEM_LLDP_TLV_DATA 32
8111 LLDP_NEAREST_BRIDGE = 0,
8112 LLDP_NEAREST_NON_TPMR_BRIDGE,
8113 LLDP_NEAREST_CUSTOMER_BRIDGE,
8114 LLDP_MAX_LLDP_AGENTS
8117 struct lldp_config_params_s {
8119 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
8120 #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0
8121 #define LLDP_CONFIG_HOLD_MASK 0x00000f00
8122 #define LLDP_CONFIG_HOLD_SHIFT 8
8123 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
8124 #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12
8125 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
8126 #define LLDP_CONFIG_ENABLE_RX_SHIFT 30
8127 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
8128 #define LLDP_CONFIG_ENABLE_TX_SHIFT 31
8129 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
8130 u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
8133 struct lldp_status_params_s {
8136 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
8137 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
8141 struct dcbx_ets_feature {
8143 #define DCBX_ETS_ENABLED_MASK 0x00000001
8144 #define DCBX_ETS_ENABLED_SHIFT 0
8145 #define DCBX_ETS_WILLING_MASK 0x00000002
8146 #define DCBX_ETS_WILLING_SHIFT 1
8147 #define DCBX_ETS_ERROR_MASK 0x00000004
8148 #define DCBX_ETS_ERROR_SHIFT 2
8149 #define DCBX_ETS_CBS_MASK 0x00000008
8150 #define DCBX_ETS_CBS_SHIFT 3
8151 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0
8152 #define DCBX_ETS_MAX_TCS_SHIFT 4
8153 #define DCBX_ISCSI_OOO_TC_MASK 0x00000f00
8154 #define DCBX_ISCSI_OOO_TC_SHIFT 8
8156 #define DCBX_ISCSI_OOO_TC (4)
8158 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_ISCSI_OOO_TC + 1)
8159 #define DCBX_CEE_STRICT_PRIORITY 0xf
8162 #define DCBX_ETS_TSA_STRICT 0
8163 #define DCBX_ETS_TSA_CBS 1
8164 #define DCBX_ETS_TSA_ETS 2
8167 struct dcbx_app_priority_entry {
8169 #define DCBX_APP_PRI_MAP_MASK 0x000000ff
8170 #define DCBX_APP_PRI_MAP_SHIFT 0
8171 #define DCBX_APP_PRI_0 0x01
8172 #define DCBX_APP_PRI_1 0x02
8173 #define DCBX_APP_PRI_2 0x04
8174 #define DCBX_APP_PRI_3 0x08
8175 #define DCBX_APP_PRI_4 0x10
8176 #define DCBX_APP_PRI_5 0x20
8177 #define DCBX_APP_PRI_6 0x40
8178 #define DCBX_APP_PRI_7 0x80
8179 #define DCBX_APP_SF_MASK 0x00000300
8180 #define DCBX_APP_SF_SHIFT 8
8181 #define DCBX_APP_SF_ETHTYPE 0
8182 #define DCBX_APP_SF_PORT 1
8183 #define DCBX_APP_SF_IEEE_MASK 0x0000f000
8184 #define DCBX_APP_SF_IEEE_SHIFT 12
8185 #define DCBX_APP_SF_IEEE_RESERVED 0
8186 #define DCBX_APP_SF_IEEE_ETHTYPE 1
8187 #define DCBX_APP_SF_IEEE_TCP_PORT 2
8188 #define DCBX_APP_SF_IEEE_UDP_PORT 3
8189 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4
8191 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
8192 #define DCBX_APP_PROTOCOL_ID_SHIFT 16
8195 struct dcbx_app_priority_feature {
8197 #define DCBX_APP_ENABLED_MASK 0x00000001
8198 #define DCBX_APP_ENABLED_SHIFT 0
8199 #define DCBX_APP_WILLING_MASK 0x00000002
8200 #define DCBX_APP_WILLING_SHIFT 1
8201 #define DCBX_APP_ERROR_MASK 0x00000004
8202 #define DCBX_APP_ERROR_SHIFT 2
8203 #define DCBX_APP_MAX_TCS_MASK 0x0000f000
8204 #define DCBX_APP_MAX_TCS_SHIFT 12
8205 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
8206 #define DCBX_APP_NUM_ENTRIES_SHIFT 16
8207 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
8210 struct dcbx_features {
8211 struct dcbx_ets_feature ets;
8213 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
8214 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0
8215 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
8216 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
8217 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
8218 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
8219 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
8220 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
8221 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
8222 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
8224 #define DCBX_PFC_FLAGS_MASK 0x0000ff00
8225 #define DCBX_PFC_FLAGS_SHIFT 8
8226 #define DCBX_PFC_CAPS_MASK 0x00000f00
8227 #define DCBX_PFC_CAPS_SHIFT 8
8228 #define DCBX_PFC_MBC_MASK 0x00004000
8229 #define DCBX_PFC_MBC_SHIFT 14
8230 #define DCBX_PFC_WILLING_MASK 0x00008000
8231 #define DCBX_PFC_WILLING_SHIFT 15
8232 #define DCBX_PFC_ENABLED_MASK 0x00010000
8233 #define DCBX_PFC_ENABLED_SHIFT 16
8234 #define DCBX_PFC_ERROR_MASK 0x00020000
8235 #define DCBX_PFC_ERROR_SHIFT 17
8237 struct dcbx_app_priority_feature app;
8240 struct dcbx_local_params {
8242 #define DCBX_CONFIG_VERSION_MASK 0x00000007
8243 #define DCBX_CONFIG_VERSION_SHIFT 0
8244 #define DCBX_CONFIG_VERSION_DISABLED 0
8245 #define DCBX_CONFIG_VERSION_IEEE 1
8246 #define DCBX_CONFIG_VERSION_CEE 2
8247 #define DCBX_CONFIG_VERSION_STATIC 4
8250 struct dcbx_features features;
8256 struct dcbx_features features;
8260 struct lldp_system_tlvs_buffer_s {
8263 u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
8266 struct dcb_dscp_map {
8268 #define DCB_DSCP_ENABLE_MASK 0x1
8269 #define DCB_DSCP_ENABLE_SHIFT 0
8270 #define DCB_DSCP_ENABLE 1
8271 u32 dscp_pri_map[8];
8274 struct public_global {
8277 u32 debug_mb_offset;
8278 u32 phymod_dbg_mb_offset;
8279 struct couple_mode_teaming cmt;
8280 s32 internal_temperature;
8282 u32 running_bundle_id;
8283 s32 external_temperature;
8293 struct public_path {
8294 struct fw_flr_mb flr_mb;
8295 u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
8298 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff
8299 #define PROCESS_KILL_COUNTER_SHIFT 0
8300 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
8301 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
8302 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
8305 struct public_port {
8309 #define LINK_STATUS_LINK_UP 0x00000001
8310 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
8311 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1)
8312 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
8313 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
8314 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
8315 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
8316 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
8317 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
8318 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
8320 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
8322 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
8323 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
8325 #define LINK_STATUS_PFC_ENABLED 0x00000100
8326 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
8327 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
8328 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
8329 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
8330 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
8331 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
8332 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
8333 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
8335 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
8336 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
8337 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18)
8338 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
8339 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
8341 #define LINK_STATUS_SFP_TX_FAULT 0x00100000
8342 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
8343 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
8344 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000
8345 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000
8346 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000
8347 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000
8350 u32 ext_phy_fw_version;
8351 u32 drv_phy_cfg_addr;
8357 struct port_mf_cfg port_mf_config;
8358 struct port_stats stats;
8361 #define MEDIA_UNSPECIFIED 0x0
8362 #define MEDIA_SFPP_10G_FIBER 0x1
8363 #define MEDIA_XFP_FIBER 0x2
8364 #define MEDIA_DA_TWINAX 0x3
8365 #define MEDIA_BASE_T 0x4
8366 #define MEDIA_SFP_1G_FIBER 0x5
8367 #define MEDIA_MODULE_FIBER 0x6
8368 #define MEDIA_KR 0xf0
8369 #define MEDIA_NOT_PRESENT 0xff
8372 u32 link_change_count;
8374 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];
8375 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
8376 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
8378 /* DCBX related MIB */
8379 struct dcbx_local_params local_admin_dcbx_mib;
8380 struct dcbx_mib remote_dcbx_mib;
8381 struct dcbx_mib operational_dcbx_mib;
8384 u32 transceiver_data;
8385 #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF
8386 #define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000
8387 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
8388 #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001
8389 #define ETH_TRANSCEIVER_STATE_VALID 0x00000003
8390 #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008
8394 u32 wol_pkt_details;
8395 struct dcb_dscp_map dcb_dscp_map;
8398 struct public_func {
8406 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
8407 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
8408 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
8410 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
8411 #define FUNC_MF_CFG_PROTOCOL_SHIFT 4
8412 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
8413 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
8414 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
8415 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
8417 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
8418 #define FUNC_MF_CFG_MIN_BW_SHIFT 8
8419 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
8420 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
8421 #define FUNC_MF_CFG_MAX_BW_SHIFT 16
8422 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
8425 #define FUNC_STATUS_VLINK_DOWN 0x00000001
8428 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
8429 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
8430 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
8432 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
8434 u32 fcoe_wwn_port_name_upper;
8435 u32 fcoe_wwn_port_name_lower;
8437 u32 fcoe_wwn_node_name_upper;
8438 u32 fcoe_wwn_node_name_lower;
8441 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
8442 #define FUNC_MF_CFG_OV_STAG_SHIFT 0
8443 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
8449 u32 driver_last_activity_ts;
8451 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];
8454 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
8455 #define DRV_ID_PDA_COMP_VER_SHIFT 0
8457 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
8458 #define DRV_ID_MCP_HSI_VER_SHIFT 16
8459 #define DRV_ID_MCP_HSI_VER_CURRENT (1 << DRV_ID_MCP_HSI_VER_SHIFT)
8461 #define DRV_ID_DRV_TYPE_MASK 0x7f000000
8462 #define DRV_ID_DRV_TYPE_SHIFT 24
8463 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
8464 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT)
8466 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000
8467 #define DRV_ID_DRV_INIT_HW_SHIFT 31
8468 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT)
8481 struct mcp_file_att {
8486 struct bist_nvm_image_att {
8493 #define MCP_DRV_VER_STR_SIZE 16
8494 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
8495 #define MCP_DRV_NVM_BUF_LEN 32
8496 struct drv_version_stc {
8498 u8 name[MCP_DRV_VER_STR_SIZE - 4];
8501 struct lan_stats_stc {
8508 struct ocbb_data_stc {
8511 u32 ocsd_req_update_interval;
8514 #define MAX_NUM_OF_SENSORS 7
8515 struct temperature_status_stc {
8517 u32 sensor[MAX_NUM_OF_SENSORS];
8520 /* crash dump configuration header */
8521 struct mdump_config_stc {
8529 union drv_union_data {
8530 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
8531 struct mcp_mac wol_mac;
8533 struct eth_phy_cfg drv_phy_cfg;
8535 struct mcp_val64 val64;
8537 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
8539 struct mcp_file_att file_att;
8541 u32 ack_vf_disabled[VF_MAX_STATIC / 32];
8543 struct drv_version_stc drv_version;
8545 struct lan_stats_stc lan_stats;
8546 u64 reserved_stats[11];
8547 struct ocbb_data_stc ocbb_info;
8548 struct temperature_status_stc temp_info;
8549 struct bist_nvm_image_att nvm_image_att;
8550 struct mdump_config_stc mdump_config;
8553 struct public_drv_mb {
8555 #define DRV_MSG_CODE_MASK 0xffff0000
8556 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
8557 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
8558 #define DRV_MSG_CODE_INIT_HW 0x12000000
8559 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
8560 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
8561 #define DRV_MSG_CODE_INIT_PHY 0x22000000
8562 #define DRV_MSG_CODE_LINK_RESET 0x23000000
8563 #define DRV_MSG_CODE_SET_DCBX 0x25000000
8565 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
8566 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000
8567 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
8568 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
8569 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
8570 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
8571 #define DRV_MSG_CODE_MCP_RESET 0x00090000
8572 #define DRV_MSG_CODE_SET_VERSION 0x000f0000
8573 #define DRV_MSG_CODE_MCP_HALT 0x00100000
8575 #define DRV_MSG_CODE_GET_STATS 0x00130000
8576 #define DRV_MSG_CODE_STATS_TYPE_LAN 1
8577 #define DRV_MSG_CODE_STATS_TYPE_FCOE 2
8578 #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3
8579 #define DRV_MSG_CODE_STATS_TYPE_RDMA 4
8581 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000
8583 #define DRV_MSG_CODE_BIST_TEST 0x001e0000
8584 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000
8586 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
8589 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
8590 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x000000FF
8591 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
8593 #define DRV_MB_PARAM_NVM_LEN_SHIFT 24
8595 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
8596 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
8597 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8
8598 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
8599 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
8600 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
8603 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
8604 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
8605 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
8607 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1
8608 #define DRV_MB_PARAM_BIST_CLOCK_TEST 2
8610 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
8611 #define DRV_MB_PARAM_BIST_RC_PASSED 1
8612 #define DRV_MB_PARAM_BIST_RC_FAILED 2
8613 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
8615 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
8616 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
8619 #define FW_MSG_CODE_MASK 0xffff0000
8620 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
8621 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
8622 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
8623 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
8624 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10210000
8625 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
8626 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
8627 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
8628 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
8629 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
8630 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
8631 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
8633 #define FW_MSG_CODE_NVM_OK 0x00010000
8634 #define FW_MSG_CODE_OK 0x00160000
8636 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
8641 #define DRV_PULSE_SEQ_MASK 0x00007fff
8642 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
8643 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
8646 #define MCP_PULSE_SEQ_MASK 0x00007fff
8647 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
8648 #define MCP_EVENT_MASK 0xffff0000
8649 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
8651 union drv_union_data union_data;
8654 enum MFW_DRV_MSG_TYPE {
8655 MFW_DRV_MSG_LINK_CHANGE,
8656 MFW_DRV_MSG_FLR_FW_ACK_FAILED,
8657 MFW_DRV_MSG_VF_DISABLED,
8658 MFW_DRV_MSG_LLDP_DATA_UPDATED,
8659 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
8660 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
8661 MFW_DRV_MSG_RESERVED4,
8662 MFW_DRV_MSG_BW_UPDATE,
8663 MFW_DRV_MSG_BW_UPDATE5,
8664 MFW_DRV_MSG_GET_LAN_STATS,
8665 MFW_DRV_MSG_GET_FCOE_STATS,
8666 MFW_DRV_MSG_GET_ISCSI_STATS,
8667 MFW_DRV_MSG_GET_RDMA_STATS,
8668 MFW_DRV_MSG_BW_UPDATE10,
8669 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
8670 MFW_DRV_MSG_BW_UPDATE11,
8674 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1)
8675 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2)
8676 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
8677 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
8679 struct public_mfw_mb {
8681 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
8682 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
8685 enum public_sections {
8695 struct mcp_public_data {
8697 u32 sections[PUBLIC_MAX_SECTIONS];
8698 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
8699 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
8700 struct public_global global;
8701 struct public_path path[MCP_GLOB_PATH_MAX];
8702 struct public_port port[MCP_GLOB_PORT_MAX];
8703 struct public_func func[MCP_GLOB_FUNC_MAX];
8706 struct nvm_cfg_mac_address {
8708 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
8709 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
8713 struct nvm_cfg1_glob {
8715 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
8716 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
8717 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
8718 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
8719 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
8720 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
8721 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
8722 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
8723 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
8724 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
8725 u32 engineering_change[3];
8726 u32 manufacturing_id;
8727 u32 serial_number[4];
8731 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
8732 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
8733 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
8734 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
8735 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
8736 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
8737 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
8738 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
8739 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB
8740 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC
8741 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD
8742 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE
8747 u32 mps10_preemphasis;
8748 u32 mps10_driver_current;
8749 u32 mps25_preemphasis;
8750 u32 mps25_driver_current;
8754 u32 mps10_txfir_main;
8755 u32 mps10_txfir_post;
8756 u32 mps25_txfir_main;
8757 u32 mps25_txfir_post;
8758 u32 manufacture_ver;
8759 u32 manufacture_time;
8760 u32 led_global_settings;
8765 u32 device_capabilities;
8766 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
8767 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
8768 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
8769 u32 power_dissipated;
8772 u32 multi_network_modes_capability;
8776 struct nvm_cfg1_path {
8780 struct nvm_cfg1_port {
8781 u32 reserved__m_relocated_to_option_123;
8782 u32 reserved__m_relocated_to_option_124;
8784 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
8785 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
8786 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
8787 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
8788 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
8789 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
8790 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
8791 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
8792 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
8793 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
8794 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
8798 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
8799 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
8800 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
8801 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
8802 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
8803 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
8804 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
8805 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
8807 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
8808 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
8809 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
8810 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
8811 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
8812 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
8813 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
8814 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
8815 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
8816 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8
8817 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
8818 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
8819 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
8820 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
8821 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
8828 struct nvm_cfg_mac_address lldp_mac_address;
8829 u32 led_port_settings;
8851 struct nvm_cfg1_func {
8852 struct nvm_cfg_mac_address mac_address;
8858 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr;
8859 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr;
8860 u32 preboot_generic_cfg;
8865 struct nvm_cfg1_glob glob;
8866 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX];
8867 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX];
8868 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX];
8871 enum spad_sections {
8873 SPAD_SECTION_NVM_CFG,
8874 SPAD_SECTION_PUBLIC,
8875 SPAD_SECTION_PRIVATE,
8879 #define MCP_TRACE_SIZE 2048 /* 2kb */
8881 /* This section is located at a fixed location in the beginning of the
8882 * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade.
8883 * All the rest of data has a floating location which differs from version to
8884 * version, and is pointed by the mcp_meta_data below.
8885 * Moreover, the spad_layout section is part of the MFW firmware, and is loaded
8886 * with it from nvram in order to clear this portion.
8888 struct static_init {
8890 offsize_t sections[SPAD_SECTION_MAX];
8891 #define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_]))))
8893 struct mcp_trace trace;
8894 #define MCP_TRACE_P ((struct mcp_trace *)(STRUCT_OFFSET(trace)))
8895 u8 trace_buffer[MCP_TRACE_SIZE];
8896 #define MCP_TRACE_BUF ((u8 *)(STRUCT_OFFSET(trace_buffer)))
8897 /* running_mfw has the same definition as in nvm_map.h.
8898 * This bit indicate both the running dir, and the running bundle.
8899 * It is set once when the LIM is loaded.
8902 #define RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(running_mfw))))
8904 #define MFW_BUILD_TIME (*((u32 *)(STRUCT_OFFSET(build_time))))
8906 #define RESET_TYPE (*((u32 *)(STRUCT_OFFSET(reset_type))))
8907 u32 mfw_secure_mode;
8908 #define MFW_SECURE_MODE (*((u32 *)(STRUCT_OFFSET(mfw_secure_mode))))
8909 u16 pme_status_pf_bitmap;
8910 #define PME_STATUS_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_status_pf_bitmap))))
8911 u16 pme_enable_pf_bitmap;
8912 #define PME_ENABLE_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_enable_pf_bitmap))))
8915 u32 ah_pcie_link_params;
8916 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff)
8917 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT (0)
8918 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00)
8919 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT (8)
8920 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000)
8921 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT (16)
8922 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000)
8923 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT (24)
8924 #define AH_PCIE_LINK_PARAMS (*((u32 *)(STRUCT_OFFSET(ah_pcie_link_params))))
8926 u32 rsrv_persist[5]; /* Persist reserved for MFW upgrades */
8929 enum nvm_image_type {
8930 NVM_TYPE_TIM1 = 0x01,
8931 NVM_TYPE_TIM2 = 0x02,
8932 NVM_TYPE_MIM1 = 0x03,
8933 NVM_TYPE_MIM2 = 0x04,
8934 NVM_TYPE_MBA = 0x05,
8935 NVM_TYPE_MODULES_PN = 0x06,
8936 NVM_TYPE_VPD = 0x07,
8937 NVM_TYPE_MFW_TRACE1 = 0x08,
8938 NVM_TYPE_MFW_TRACE2 = 0x09,
8939 NVM_TYPE_NVM_CFG1 = 0x0a,
8940 NVM_TYPE_L2B = 0x0b,
8941 NVM_TYPE_DIR1 = 0x0c,
8942 NVM_TYPE_EAGLE_FW1 = 0x0d,
8943 NVM_TYPE_FALCON_FW1 = 0x0e,
8944 NVM_TYPE_PCIE_FW1 = 0x0f,
8945 NVM_TYPE_HW_SET = 0x10,
8946 NVM_TYPE_LIM = 0x11,
8947 NVM_TYPE_AVS_FW1 = 0x12,
8948 NVM_TYPE_DIR2 = 0x13,
8949 NVM_TYPE_CCM = 0x14,
8950 NVM_TYPE_EAGLE_FW2 = 0x15,
8951 NVM_TYPE_FALCON_FW2 = 0x16,
8952 NVM_TYPE_PCIE_FW2 = 0x17,
8953 NVM_TYPE_AVS_FW2 = 0x18,
8954 NVM_TYPE_INIT_HW = 0x19,
8955 NVM_TYPE_DEFAULT_CFG = 0x1a,
8956 NVM_TYPE_MDUMP = 0x1b,
8957 NVM_TYPE_META = 0x1c,
8958 NVM_TYPE_ISCSI_CFG = 0x1d,
8959 NVM_TYPE_FCOE_CFG = 0x1f,
8960 NVM_TYPE_ETH_PHY_FW1 = 0x20,
8961 NVM_TYPE_ETH_PHY_FW2 = 0x21,
8965 #define DIR_ID_1 (0)