1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
38 #include <linux/bitops.h>
39 #include <linux/delay.h>
40 #include <linux/kernel.h>
41 #include <linux/list.h>
42 #include <linux/slab.h>
43 #include <linux/qed/common_hsi.h>
44 #include <linux/qed/storage_common.h>
45 #include <linux/qed/tcp_common.h>
46 #include <linux/qed/fcoe_common.h>
47 #include <linux/qed/eth_common.h>
48 #include <linux/qed/iscsi_common.h>
49 #include <linux/qed/iwarp_common.h>
50 #include <linux/qed/rdma_common.h>
51 #include <linux/qed/roce_common.h>
52 #include <linux/qed/qed_fcoe_if.h>
57 /* opcodes for the event ring */
58 enum common_event_opcode {
59 COMMON_EVENT_PF_START,
61 COMMON_EVENT_VF_START,
63 COMMON_EVENT_VF_PF_CHANNEL,
65 COMMON_EVENT_PF_UPDATE,
66 COMMON_EVENT_MALICIOUS_VF,
67 COMMON_EVENT_RL_UPDATE,
69 MAX_COMMON_EVENT_OPCODE
72 /* Common Ramrod Command IDs */
73 enum common_ramrod_cmd_id {
75 COMMON_RAMROD_PF_START,
76 COMMON_RAMROD_PF_STOP,
77 COMMON_RAMROD_VF_START,
78 COMMON_RAMROD_VF_STOP,
79 COMMON_RAMROD_PF_UPDATE,
80 COMMON_RAMROD_RL_UPDATE,
82 MAX_COMMON_RAMROD_CMD_ID
85 /* The core storm context for the Ystorm */
86 struct ystorm_core_conn_st_ctx {
90 /* The core storm context for the Pstorm */
91 struct pstorm_core_conn_st_ctx {
95 /* Core Slowpath Connection storm context of Xstorm */
96 struct xstorm_core_conn_st_ctx {
99 struct regpair consolid_base_addr;
101 __le16 consolid_cons;
102 __le32 reserved0[55];
105 struct xstorm_core_conn_ag_ctx {
109 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
110 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
111 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
112 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
113 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
114 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
115 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
116 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
117 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
118 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
119 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
120 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
121 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
122 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
123 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
124 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
126 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
127 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
128 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
129 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
130 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
131 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
132 #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
133 #define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
134 #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
135 #define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
136 #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
137 #define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
138 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
139 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
140 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
141 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
143 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
144 #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
145 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
146 #define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
147 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
148 #define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
149 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
150 #define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
152 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
153 #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
154 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
155 #define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
156 #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
157 #define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
158 #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
159 #define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
161 #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
162 #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
163 #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
164 #define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
165 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
166 #define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
167 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
168 #define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
170 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
171 #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
172 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
173 #define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
174 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
175 #define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
176 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
177 #define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
179 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
180 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
181 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
182 #define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
183 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
184 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
185 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
186 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
188 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
189 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
190 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
191 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
192 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
193 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
194 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
195 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
196 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
197 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
199 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
200 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
201 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
202 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
203 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
204 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
205 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
206 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
207 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
208 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
209 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
210 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
211 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
212 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
213 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
214 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
216 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
217 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
218 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
219 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
220 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
221 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
222 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
223 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
224 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
225 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
226 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
227 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
228 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
229 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
230 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
231 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
233 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
234 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
235 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
236 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
237 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
238 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
239 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
240 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
241 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
242 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
243 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
244 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
245 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
246 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
247 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
248 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
250 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
251 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
252 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
253 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
254 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
255 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
256 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
257 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
258 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
259 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
260 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
261 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
262 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
263 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
264 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
265 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
267 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
268 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
269 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
270 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
271 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
272 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
273 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
274 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
275 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
276 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
277 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
278 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
279 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
280 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
281 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
282 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
284 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
285 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
286 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
287 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
288 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
289 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
290 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
291 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
292 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
293 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
294 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
295 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
296 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
297 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
298 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
299 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
301 #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
302 #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
303 #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
304 #define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
305 #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
306 #define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
307 #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
308 #define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
309 #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
310 #define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
311 #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
312 #define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
313 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
314 #define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
317 __le16 consolid_prod;
320 __le16 tx_bd_or_spq_prod;
368 struct tstorm_core_conn_ag_ctx {
372 #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
373 #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
374 #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
375 #define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
376 #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
377 #define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
378 #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
379 #define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
380 #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
381 #define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
382 #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
383 #define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
384 #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
385 #define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
387 #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
388 #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
389 #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
390 #define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
391 #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
392 #define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
393 #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
394 #define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
396 #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
397 #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
398 #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
399 #define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
400 #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
401 #define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
402 #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
403 #define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
405 #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
406 #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
407 #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
408 #define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
409 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
410 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
411 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
412 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
413 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
414 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
415 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
416 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
418 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
419 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
420 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
421 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
422 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
423 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
424 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
425 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
426 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
427 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
428 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
429 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
430 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
431 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
432 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
433 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
435 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
436 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
437 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
438 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
439 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
440 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
441 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
442 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
443 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
444 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
445 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
446 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
447 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
448 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
449 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
450 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
472 struct ustorm_core_conn_ag_ctx {
476 #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
477 #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
478 #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
479 #define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
480 #define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
481 #define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
482 #define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
483 #define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
484 #define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
485 #define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
487 #define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
488 #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
489 #define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
490 #define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
491 #define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
492 #define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
493 #define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
494 #define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
496 #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
497 #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
498 #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
499 #define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
500 #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
501 #define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
502 #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
503 #define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
504 #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
505 #define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
506 #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
507 #define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
508 #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
509 #define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
510 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
511 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
513 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
514 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
515 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
516 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
517 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
518 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
519 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
520 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
521 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
522 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
523 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
524 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
525 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
526 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
527 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
528 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
541 /* The core storm context for the Mstorm */
542 struct mstorm_core_conn_st_ctx {
546 /* The core storm context for the Ustorm */
547 struct ustorm_core_conn_st_ctx {
551 /* core connection context */
552 struct core_conn_context {
553 struct ystorm_core_conn_st_ctx ystorm_st_context;
554 struct regpair ystorm_st_padding[2];
555 struct pstorm_core_conn_st_ctx pstorm_st_context;
556 struct regpair pstorm_st_padding[2];
557 struct xstorm_core_conn_st_ctx xstorm_st_context;
558 struct xstorm_core_conn_ag_ctx xstorm_ag_context;
559 struct tstorm_core_conn_ag_ctx tstorm_ag_context;
560 struct ustorm_core_conn_ag_ctx ustorm_ag_context;
561 struct mstorm_core_conn_st_ctx mstorm_st_context;
562 struct ustorm_core_conn_st_ctx ustorm_st_context;
563 struct regpair ustorm_st_padding[2];
566 enum core_error_handle {
570 MAX_CORE_ERROR_HANDLE
573 enum core_event_opcode {
574 CORE_EVENT_TX_QUEUE_START,
575 CORE_EVENT_TX_QUEUE_STOP,
576 CORE_EVENT_RX_QUEUE_START,
577 CORE_EVENT_RX_QUEUE_STOP,
578 CORE_EVENT_RX_QUEUE_FLUSH,
579 MAX_CORE_EVENT_OPCODE
582 enum core_l4_pseudo_checksum_mode {
583 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
584 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
585 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
588 struct core_ll2_port_stats {
589 struct regpair gsi_invalid_hdr;
590 struct regpair gsi_invalid_pkt_length;
591 struct regpair gsi_unsupported_pkt_typ;
592 struct regpair gsi_crcchksm_error;
595 struct core_ll2_pstorm_per_queue_stat {
596 struct regpair sent_ucast_bytes;
597 struct regpair sent_mcast_bytes;
598 struct regpair sent_bcast_bytes;
599 struct regpair sent_ucast_pkts;
600 struct regpair sent_mcast_pkts;
601 struct regpair sent_bcast_pkts;
604 struct core_ll2_rx_prod {
610 struct core_ll2_tstorm_per_queue_stat {
611 struct regpair packet_too_big_discard;
612 struct regpair no_buff_discard;
615 struct core_ll2_ustorm_per_queue_stat {
616 struct regpair rcv_ucast_bytes;
617 struct regpair rcv_mcast_bytes;
618 struct regpair rcv_bcast_bytes;
619 struct regpair rcv_ucast_pkts;
620 struct regpair rcv_mcast_pkts;
621 struct regpair rcv_bcast_pkts;
624 enum core_ramrod_cmd_id {
626 CORE_RAMROD_RX_QUEUE_START,
627 CORE_RAMROD_TX_QUEUE_START,
628 CORE_RAMROD_RX_QUEUE_STOP,
629 CORE_RAMROD_TX_QUEUE_STOP,
630 CORE_RAMROD_RX_QUEUE_FLUSH,
631 MAX_CORE_RAMROD_CMD_ID
634 enum core_roce_flavor_type {
637 MAX_CORE_ROCE_FLAVOR_TYPE
640 struct core_rx_action_on_error {
642 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
643 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
644 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
645 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2
646 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
647 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4
655 struct core_rx_bd_with_buff_len {
661 union core_rx_bd_union {
662 struct core_rx_bd rx_bd;
663 struct core_rx_bd_with_buff_len rx_bd_with_len;
666 struct core_rx_cqe_opaque_data {
670 enum core_rx_cqe_type {
671 CORE_RX_CQE_ILLIGAL_TYPE,
672 CORE_RX_CQE_TYPE_REGULAR,
673 CORE_RX_CQE_TYPE_GSI_OFFLOAD,
674 CORE_RX_CQE_TYPE_SLOW_PATH,
678 struct core_rx_fast_path_cqe {
681 struct parsing_and_err_flags parse_flags;
682 __le16 packet_length;
684 struct core_rx_cqe_opaque_data opaque_data;
685 struct parsing_err_flags err_flags;
690 struct core_rx_gsi_offload_cqe {
692 u8 data_length_error;
693 struct parsing_and_err_flags parse_flags;
696 __le32 src_mac_addrhi;
697 __le16 src_mac_addrlo;
702 struct core_rx_slow_path_cqe {
706 struct core_rx_cqe_opaque_data opaque_data;
710 union core_rx_cqe_union {
711 struct core_rx_fast_path_cqe rx_cqe_fp;
712 struct core_rx_gsi_offload_cqe rx_cqe_gsi;
713 struct core_rx_slow_path_cqe rx_cqe_sp;
716 struct core_rx_start_ramrod_data {
717 struct regpair bd_base;
718 struct regpair cqe_pbl_addr;
723 u8 complete_event_flg;
725 __le16 num_of_pbl_pages;
726 u8 inner_vlan_removal_en;
729 u8 mf_si_bcast_accept_all;
730 u8 mf_si_mcast_accept_all;
731 struct core_rx_action_on_error action_on_error;
736 struct core_rx_stop_ramrod_data {
738 u8 complete_event_flg;
744 struct core_tx_bd_data {
746 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
747 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
748 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
749 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1
750 #define CORE_TX_BD_DATA_START_BD_MASK 0x1
751 #define CORE_TX_BD_DATA_START_BD_SHIFT 2
752 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
753 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
754 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
755 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4
756 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
757 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5
758 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
759 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6
760 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
761 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7
762 #define CORE_TX_BD_DATA_NBDS_MASK 0xF
763 #define CORE_TX_BD_DATA_NBDS_SHIFT 8
764 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
765 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12
766 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
767 #define CORE_TX_BD_DATA_IP_LEN_SHIFT 13
768 #define CORE_TX_BD_DATA_RESERVED0_MASK 0x3
769 #define CORE_TX_BD_DATA_RESERVED0_SHIFT 14
775 __le16 nw_vlan_or_lb_echo;
776 struct core_tx_bd_data bd_data;
778 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
779 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
780 #define CORE_TX_BD_TX_DST_MASK 0x3
781 #define CORE_TX_BD_TX_DST_SHIFT 14
787 CORE_TX_DEST_RESERVED,
792 struct core_tx_start_ramrod_data {
793 struct regpair pbl_base_addr;
806 struct core_tx_stop_ramrod_data {
810 enum dcb_dscp_update_mode {
811 DONT_UPDATE_DCB_DSCP,
815 MAX_DCB_DSCP_UPDATE_MODE
818 struct eth_mstorm_per_pf_stat {
819 struct regpair gre_discard_pkts;
820 struct regpair vxlan_discard_pkts;
821 struct regpair geneve_discard_pkts;
822 struct regpair lb_discard_pkts;
825 struct eth_mstorm_per_queue_stat {
826 struct regpair ttl0_discard;
827 struct regpair packet_too_big_discard;
828 struct regpair no_buff_discard;
829 struct regpair not_active_discard;
830 struct regpair tpa_coalesced_pkts;
831 struct regpair tpa_coalesced_events;
832 struct regpair tpa_aborts_num;
833 struct regpair tpa_coalesced_bytes;
836 /* Ethernet TX Per PF */
837 struct eth_pstorm_per_pf_stat {
838 struct regpair sent_lb_ucast_bytes;
839 struct regpair sent_lb_mcast_bytes;
840 struct regpair sent_lb_bcast_bytes;
841 struct regpair sent_lb_ucast_pkts;
842 struct regpair sent_lb_mcast_pkts;
843 struct regpair sent_lb_bcast_pkts;
844 struct regpair sent_gre_bytes;
845 struct regpair sent_vxlan_bytes;
846 struct regpair sent_geneve_bytes;
847 struct regpair sent_gre_pkts;
848 struct regpair sent_vxlan_pkts;
849 struct regpair sent_geneve_pkts;
850 struct regpair gre_drop_pkts;
851 struct regpair vxlan_drop_pkts;
852 struct regpair geneve_drop_pkts;
855 /* Ethernet TX Per Queue Stats */
856 struct eth_pstorm_per_queue_stat {
857 struct regpair sent_ucast_bytes;
858 struct regpair sent_mcast_bytes;
859 struct regpair sent_bcast_bytes;
860 struct regpair sent_ucast_pkts;
861 struct regpair sent_mcast_pkts;
862 struct regpair sent_bcast_pkts;
863 struct regpair error_drop_pkts;
866 /* ETH Rx producers data */
867 struct eth_rx_rate_limit {
875 struct eth_ustorm_per_pf_stat {
876 struct regpair rcv_lb_ucast_bytes;
877 struct regpair rcv_lb_mcast_bytes;
878 struct regpair rcv_lb_bcast_bytes;
879 struct regpair rcv_lb_ucast_pkts;
880 struct regpair rcv_lb_mcast_pkts;
881 struct regpair rcv_lb_bcast_pkts;
882 struct regpair rcv_gre_bytes;
883 struct regpair rcv_vxlan_bytes;
884 struct regpair rcv_geneve_bytes;
885 struct regpair rcv_gre_pkts;
886 struct regpair rcv_vxlan_pkts;
887 struct regpair rcv_geneve_pkts;
890 struct eth_ustorm_per_queue_stat {
891 struct regpair rcv_ucast_bytes;
892 struct regpair rcv_mcast_bytes;
893 struct regpair rcv_bcast_bytes;
894 struct regpair rcv_ucast_pkts;
895 struct regpair rcv_mcast_pkts;
896 struct regpair rcv_bcast_pkts;
899 /* Event Ring Next Page Address */
900 struct event_ring_next_addr {
905 /* Event Ring Element */
906 union event_ring_element {
907 struct event_ring_entry entry;
908 struct event_ring_next_addr next_addr;
911 enum fw_flow_ctrl_mode {
914 MAX_FW_FLOW_CTRL_MODE
917 /* Major and Minor hsi Versions */
918 struct hsi_fp_ver_struct {
923 enum iwarp_ll2_tx_queues {
924 IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
925 IWARP_LL2_ALIGNED_TX_QUEUE,
926 IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE,
928 MAX_IWARP_LL2_TX_QUEUES
931 /* Mstorm non-triggering VF zone */
932 enum malicious_vf_error_id {
933 MALICIOUS_VF_NO_ERROR,
934 VF_PF_CHANNEL_NOT_READY,
935 VF_ZONE_MSG_NOT_VALID,
936 VF_ZONE_FUNC_NOT_ENABLED,
937 ETH_PACKET_TOO_SMALL,
938 ETH_ILLEGAL_VLAN_MODE,
940 ETH_ILLEGAL_INBAND_TAGS,
941 ETH_VLAN_INSERT_AND_INBAND_VLAN,
944 ETH_INSUFFICIENT_BDS,
945 ETH_ILLEGAL_LSO_HDR_NBDS,
948 ETH_ILLEGAL_LSO_HDR_LEN,
949 ETH_INSUFFICIENT_PAYLOAD,
950 ETH_EDPM_OUT_OF_SYNC,
951 ETH_TUNN_IPV6_EXT_NBD_ERR,
952 ETH_CONTROL_PACKET_VIOLATION,
953 ETH_ANTI_SPOOFING_ERR,
954 MAX_MALICIOUS_VF_ERROR_ID
957 struct mstorm_non_trigger_vf_zone {
958 struct eth_mstorm_per_queue_stat eth_queue_stat;
959 struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
963 struct mstorm_vf_zone {
964 struct mstorm_non_trigger_vf_zone non_trigger;
968 /* personality per PF */
969 enum personality_type {
973 PERSONALITY_RDMA_AND_ETH,
977 PERSONALITY_RESERVED4,
981 /* tunnel configuration */
982 struct pf_start_tunnel_config {
983 u8 set_vxlan_udp_port_flg;
984 u8 set_geneve_udp_port_flg;
985 u8 tunnel_clss_vxlan;
986 u8 tunnel_clss_l2geneve;
987 u8 tunnel_clss_ipgeneve;
988 u8 tunnel_clss_l2gre;
989 u8 tunnel_clss_ipgre;
991 __le16 vxlan_udp_port;
992 __le16 geneve_udp_port;
995 /* Ramrod data for PF start ramrod */
996 struct pf_start_ramrod_data {
997 struct regpair event_ring_pbl_addr;
998 struct regpair consolid_q_pbl_addr;
999 struct pf_start_tunnel_config tunnel_config;
1001 __le16 event_ring_sb_id;
1004 u8 event_ring_num_pages;
1005 u8 event_ring_sb_index;
1007 u8 warning_as_error;
1008 u8 dont_log_ramrods;
1010 __le16 log_type_mask;
1013 u8 allow_npar_tx_switching;
1014 u8 inner_to_outer_pri_map[8];
1017 struct hsi_fp_ver_struct hsi_fp_ver;
1020 struct protocol_dcb_data {
1029 struct pf_update_tunnel_config {
1030 u8 update_rx_pf_clss;
1031 u8 update_rx_def_ucast_clss;
1032 u8 update_rx_def_non_ucast_clss;
1033 u8 set_vxlan_udp_port_flg;
1034 u8 set_geneve_udp_port_flg;
1035 u8 tunnel_clss_vxlan;
1036 u8 tunnel_clss_l2geneve;
1037 u8 tunnel_clss_ipgeneve;
1038 u8 tunnel_clss_l2gre;
1039 u8 tunnel_clss_ipgre;
1040 __le16 vxlan_udp_port;
1041 __le16 geneve_udp_port;
1045 struct pf_update_ramrod_data {
1047 u8 update_eth_dcb_data_mode;
1048 u8 update_fcoe_dcb_data_mode;
1049 u8 update_iscsi_dcb_data_mode;
1050 u8 update_roce_dcb_data_mode;
1051 u8 update_rroce_dcb_data_mode;
1052 u8 update_iwarp_dcb_data_mode;
1053 u8 update_mf_vlan_flag;
1054 struct protocol_dcb_data eth_dcb_data;
1055 struct protocol_dcb_data fcoe_dcb_data;
1056 struct protocol_dcb_data iscsi_dcb_data;
1057 struct protocol_dcb_data roce_dcb_data;
1058 struct protocol_dcb_data rroce_dcb_data;
1059 struct protocol_dcb_data iwarp_dcb_data;
1062 struct pf_update_tunnel_config tunnel_config;
1075 /* use to index in hsi_fp_[major|minor]_ver_arr per protocol */
1076 enum protocol_version_array_key {
1079 MAX_PROTOCOL_VERSION_ARRAY_KEY
1082 struct rdma_sent_stats {
1083 struct regpair sent_bytes;
1084 struct regpair sent_pkts;
1087 struct pstorm_non_trigger_vf_zone {
1088 struct eth_pstorm_per_queue_stat eth_queue_stat;
1089 struct rdma_sent_stats rdma_stats;
1092 /* Pstorm VF zone */
1093 struct pstorm_vf_zone {
1094 struct pstorm_non_trigger_vf_zone non_trigger;
1095 struct regpair reserved[7];
1098 /* Ramrod Header of SPQE */
1099 struct ramrod_header {
1106 struct rdma_rcv_stats {
1107 struct regpair rcv_bytes;
1108 struct regpair rcv_pkts;
1111 struct slow_path_element {
1112 struct ramrod_header hdr;
1113 struct regpair data_ptr;
1116 /* Tstorm non-triggering VF zone */
1117 struct tstorm_non_trigger_vf_zone {
1118 struct rdma_rcv_stats rdma_stats;
1121 struct tstorm_per_port_stat {
1122 struct regpair trunc_error_discard;
1123 struct regpair mac_error_discard;
1124 struct regpair mftag_filter_discard;
1125 struct regpair eth_mac_filter_discard;
1126 struct regpair ll2_mac_filter_discard;
1127 struct regpair ll2_conn_disabled_discard;
1128 struct regpair iscsi_irregular_pkt;
1129 struct regpair fcoe_irregular_pkt;
1130 struct regpair roce_irregular_pkt;
1131 struct regpair iwarp_irregular_pkt;
1132 struct regpair eth_irregular_pkt;
1133 struct regpair reserved1;
1134 struct regpair preroce_irregular_pkt;
1135 struct regpair eth_gre_tunn_filter_discard;
1136 struct regpair eth_vxlan_tunn_filter_discard;
1137 struct regpair eth_geneve_tunn_filter_discard;
1140 /* Tstorm VF zone */
1141 struct tstorm_vf_zone {
1142 struct tstorm_non_trigger_vf_zone non_trigger;
1145 /* Tunnel classification scheme */
1147 TUNNEL_CLSS_MAC_VLAN = 0,
1148 TUNNEL_CLSS_MAC_VNI,
1149 TUNNEL_CLSS_INNER_MAC_VLAN,
1150 TUNNEL_CLSS_INNER_MAC_VNI,
1151 TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
1155 /* Ustorm non-triggering VF zone */
1156 struct ustorm_non_trigger_vf_zone {
1157 struct eth_ustorm_per_queue_stat eth_queue_stat;
1158 struct regpair vf_pf_msg_addr;
1161 /* Ustorm triggering VF zone */
1162 struct ustorm_trigger_vf_zone {
1167 /* Ustorm VF zone */
1168 struct ustorm_vf_zone {
1169 struct ustorm_non_trigger_vf_zone non_trigger;
1170 struct ustorm_trigger_vf_zone trigger;
1173 /* VF-PF channel data */
1174 struct vf_pf_channel_data {
1181 /* Ramrod data for VF start ramrod */
1182 struct vf_start_ramrod_data {
1188 struct hsi_fp_ver_struct hsi_fp_ver;
1192 /* Ramrod data for VF start ramrod */
1193 struct vf_stop_ramrod_data {
1200 enum vf_zone_size_mode {
1201 VF_ZONE_SIZE_MODE_DEFAULT,
1202 VF_ZONE_SIZE_MODE_DOUBLE,
1203 VF_ZONE_SIZE_MODE_QUAD,
1204 MAX_VF_ZONE_SIZE_MODE
1207 struct atten_status_block {
1215 enum command_type_bit {
1216 IGU_COMMAND_TYPE_NOP = 0,
1217 IGU_COMMAND_TYPE_SET = 1,
1218 MAX_COMMAND_TYPE_BIT
1224 #define DMAE_CMD_SRC_MASK 0x1
1225 #define DMAE_CMD_SRC_SHIFT 0
1226 #define DMAE_CMD_DST_MASK 0x3
1227 #define DMAE_CMD_DST_SHIFT 1
1228 #define DMAE_CMD_C_DST_MASK 0x1
1229 #define DMAE_CMD_C_DST_SHIFT 3
1230 #define DMAE_CMD_CRC_RESET_MASK 0x1
1231 #define DMAE_CMD_CRC_RESET_SHIFT 4
1232 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
1233 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5
1234 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
1235 #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6
1236 #define DMAE_CMD_COMP_FUNC_MASK 0x1
1237 #define DMAE_CMD_COMP_FUNC_SHIFT 7
1238 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1
1239 #define DMAE_CMD_COMP_WORD_EN_SHIFT 8
1240 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1
1241 #define DMAE_CMD_COMP_CRC_EN_SHIFT 9
1242 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
1243 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
1244 #define DMAE_CMD_RESERVED1_MASK 0x1
1245 #define DMAE_CMD_RESERVED1_SHIFT 13
1246 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
1247 #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14
1248 #define DMAE_CMD_ERR_HANDLING_MASK 0x3
1249 #define DMAE_CMD_ERR_HANDLING_SHIFT 16
1250 #define DMAE_CMD_PORT_ID_MASK 0x3
1251 #define DMAE_CMD_PORT_ID_SHIFT 18
1252 #define DMAE_CMD_SRC_PF_ID_MASK 0xF
1253 #define DMAE_CMD_SRC_PF_ID_SHIFT 20
1254 #define DMAE_CMD_DST_PF_ID_MASK 0xF
1255 #define DMAE_CMD_DST_PF_ID_SHIFT 24
1256 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1
1257 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
1258 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1
1259 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
1260 #define DMAE_CMD_RESERVED2_MASK 0x3
1261 #define DMAE_CMD_RESERVED2_SHIFT 30
1268 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF
1269 #define DMAE_CMD_SRC_VF_ID_SHIFT 0
1270 #define DMAE_CMD_DST_VF_ID_MASK 0xFF
1271 #define DMAE_CMD_DST_VF_ID_SHIFT 8
1272 __le32 comp_addr_lo;
1273 __le32 comp_addr_hi;
1285 enum dmae_cmd_comp_crc_en_enum {
1286 dmae_cmd_comp_crc_disabled,
1287 dmae_cmd_comp_crc_enabled,
1288 MAX_DMAE_CMD_COMP_CRC_EN_ENUM
1291 enum dmae_cmd_comp_func_enum {
1292 dmae_cmd_comp_func_to_src,
1293 dmae_cmd_comp_func_to_dst,
1294 MAX_DMAE_CMD_COMP_FUNC_ENUM
1297 enum dmae_cmd_comp_word_en_enum {
1298 dmae_cmd_comp_word_disabled,
1299 dmae_cmd_comp_word_enabled,
1300 MAX_DMAE_CMD_COMP_WORD_EN_ENUM
1303 enum dmae_cmd_c_dst_enum {
1304 dmae_cmd_c_dst_pcie,
1306 MAX_DMAE_CMD_C_DST_ENUM
1309 enum dmae_cmd_dst_enum {
1310 dmae_cmd_dst_none_0,
1313 dmae_cmd_dst_none_3,
1314 MAX_DMAE_CMD_DST_ENUM
1317 enum dmae_cmd_error_handling_enum {
1318 dmae_cmd_error_handling_send_regular_comp,
1319 dmae_cmd_error_handling_send_comp_with_err,
1320 dmae_cmd_error_handling_dont_send_comp,
1321 MAX_DMAE_CMD_ERROR_HANDLING_ENUM
1324 enum dmae_cmd_src_enum {
1327 MAX_DMAE_CMD_SRC_ENUM
1330 struct mstorm_core_conn_ag_ctx {
1334 #define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1335 #define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1336 #define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1337 #define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1338 #define MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1339 #define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1340 #define MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1341 #define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1342 #define MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1343 #define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1345 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1346 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1347 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1348 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1349 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1350 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1351 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1352 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1353 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1354 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1355 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1356 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1357 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1358 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1359 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1360 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1367 struct ystorm_core_conn_ag_ctx {
1371 #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1372 #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1373 #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1374 #define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1375 #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1376 #define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1377 #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1378 #define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1379 #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1380 #define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1382 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1383 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1384 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1385 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1386 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1387 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1388 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1389 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1390 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1391 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1392 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1393 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1394 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1395 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1396 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1397 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1411 /* IGU cleanup command */
1412 struct igu_cleanup {
1413 __le32 sb_id_and_flags;
1414 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
1415 #define IGU_CLEANUP_RESERVED0_SHIFT 0
1416 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1
1417 #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27
1418 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
1419 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
1420 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
1421 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
1425 /* IGU firmware driver command */
1427 struct igu_prod_cons_update prod_cons_update;
1428 struct igu_cleanup cleanup;
1431 /* IGU firmware driver command */
1432 struct igu_command_reg_ctrl {
1434 __le16 igu_command_reg_ctrl_fields;
1435 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
1436 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
1437 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
1438 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12
1439 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
1440 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
1443 /* IGU mapping line structure */
1444 struct igu_mapping_line {
1445 __le32 igu_mapping_line_fields;
1446 #define IGU_MAPPING_LINE_VALID_MASK 0x1
1447 #define IGU_MAPPING_LINE_VALID_SHIFT 0
1448 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
1449 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1
1450 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
1451 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
1452 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1
1453 #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17
1454 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
1455 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18
1456 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
1457 #define IGU_MAPPING_LINE_RESERVED_SHIFT 24
1460 /* IGU MSIX line structure */
1461 struct igu_msix_vector {
1462 struct regpair address;
1464 __le32 msix_vector_fields;
1465 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
1466 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
1467 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
1468 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1
1469 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
1470 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
1471 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
1472 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
1474 /* per encapsulation type enabling flags */
1475 struct prs_reg_encapsulation_type_en {
1477 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
1478 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
1479 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
1480 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1
1481 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
1482 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2
1483 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
1484 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3
1485 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
1486 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
1487 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
1488 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5
1489 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
1490 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6
1493 enum pxp_tph_st_hint {
1495 TPH_ST_HINT_REQUESTER,
1497 TPH_ST_HINT_TARGET_PRIO,
1501 /* QM hardware structure of enable bypass credit mask */
1502 struct qm_rf_bypass_mask {
1504 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
1505 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
1506 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
1507 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
1508 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
1509 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2
1510 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
1511 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3
1512 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
1513 #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4
1514 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
1515 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5
1516 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
1517 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6
1518 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
1519 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
1522 /* QM hardware structure of opportunistic credit mask */
1523 struct qm_rf_opportunistic_mask {
1525 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
1526 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
1527 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
1528 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1
1529 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
1530 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2
1531 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
1532 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3
1533 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
1534 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4
1535 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
1536 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5
1537 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
1538 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6
1539 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
1540 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7
1541 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
1542 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
1543 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
1544 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9
1547 /* QM hardware structure of QM map memory */
1548 struct qm_rf_pq_map {
1550 #define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1
1551 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0
1552 #define QM_RF_PQ_MAP_RL_ID_MASK 0xFF
1553 #define QM_RF_PQ_MAP_RL_ID_SHIFT 1
1554 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF
1555 #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9
1556 #define QM_RF_PQ_MAP_VOQ_MASK 0x1F
1557 #define QM_RF_PQ_MAP_VOQ_SHIFT 18
1558 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3
1559 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
1560 #define QM_RF_PQ_MAP_RL_VALID_MASK 0x1
1561 #define QM_RF_PQ_MAP_RL_VALID_SHIFT 25
1562 #define QM_RF_PQ_MAP_RESERVED_MASK 0x3F
1563 #define QM_RF_PQ_MAP_RESERVED_SHIFT 26
1566 /* Completion params for aggregated interrupt completion */
1567 struct sdm_agg_int_comp_params {
1569 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
1570 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
1571 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
1572 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
1573 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
1574 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7
1577 /* SDM operation gen command (generate aggregative interrupt) */
1580 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF
1581 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1582 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF
1583 #define SDM_OP_GEN_COMP_TYPE_SHIFT 16
1584 #define SDM_OP_GEN_RESERVED_MASK 0xFFF
1585 #define SDM_OP_GEN_RESERVED_SHIFT 20
1588 /****************************************/
1589 /* Debug Tools HSI constants and macros */
1590 /****************************************/
1593 GRCBASE_GRC = 0x50000,
1594 GRCBASE_MISCS = 0x9000,
1595 GRCBASE_MISC = 0x8000,
1596 GRCBASE_DBU = 0xa000,
1597 GRCBASE_PGLUE_B = 0x2a8000,
1598 GRCBASE_CNIG = 0x218000,
1599 GRCBASE_CPMU = 0x30000,
1600 GRCBASE_NCSI = 0x40000,
1601 GRCBASE_OPTE = 0x53000,
1602 GRCBASE_BMB = 0x540000,
1603 GRCBASE_PCIE = 0x54000,
1604 GRCBASE_MCP = 0xe00000,
1605 GRCBASE_MCP2 = 0x52000,
1606 GRCBASE_PSWHST = 0x2a0000,
1607 GRCBASE_PSWHST2 = 0x29e000,
1608 GRCBASE_PSWRD = 0x29c000,
1609 GRCBASE_PSWRD2 = 0x29d000,
1610 GRCBASE_PSWWR = 0x29a000,
1611 GRCBASE_PSWWR2 = 0x29b000,
1612 GRCBASE_PSWRQ = 0x280000,
1613 GRCBASE_PSWRQ2 = 0x240000,
1614 GRCBASE_PGLCS = 0x0,
1615 GRCBASE_DMAE = 0xc000,
1616 GRCBASE_PTU = 0x560000,
1617 GRCBASE_TCM = 0x1180000,
1618 GRCBASE_MCM = 0x1200000,
1619 GRCBASE_UCM = 0x1280000,
1620 GRCBASE_XCM = 0x1000000,
1621 GRCBASE_YCM = 0x1080000,
1622 GRCBASE_PCM = 0x1100000,
1623 GRCBASE_QM = 0x2f0000,
1624 GRCBASE_TM = 0x2c0000,
1625 GRCBASE_DORQ = 0x100000,
1626 GRCBASE_BRB = 0x340000,
1627 GRCBASE_SRC = 0x238000,
1628 GRCBASE_PRS = 0x1f0000,
1629 GRCBASE_TSDM = 0xfb0000,
1630 GRCBASE_MSDM = 0xfc0000,
1631 GRCBASE_USDM = 0xfd0000,
1632 GRCBASE_XSDM = 0xf80000,
1633 GRCBASE_YSDM = 0xf90000,
1634 GRCBASE_PSDM = 0xfa0000,
1635 GRCBASE_TSEM = 0x1700000,
1636 GRCBASE_MSEM = 0x1800000,
1637 GRCBASE_USEM = 0x1900000,
1638 GRCBASE_XSEM = 0x1400000,
1639 GRCBASE_YSEM = 0x1500000,
1640 GRCBASE_PSEM = 0x1600000,
1641 GRCBASE_RSS = 0x238800,
1642 GRCBASE_TMLD = 0x4d0000,
1643 GRCBASE_MULD = 0x4e0000,
1644 GRCBASE_YULD = 0x4c8000,
1645 GRCBASE_XYLD = 0x4c0000,
1646 GRCBASE_PTLD = 0x590000,
1647 GRCBASE_YPLD = 0x5b0000,
1648 GRCBASE_PRM = 0x230000,
1649 GRCBASE_PBF_PB1 = 0xda0000,
1650 GRCBASE_PBF_PB2 = 0xda4000,
1651 GRCBASE_RPB = 0x23c000,
1652 GRCBASE_BTB = 0xdb0000,
1653 GRCBASE_PBF = 0xd80000,
1654 GRCBASE_RDIF = 0x300000,
1655 GRCBASE_TDIF = 0x310000,
1656 GRCBASE_CDU = 0x580000,
1657 GRCBASE_CCFC = 0x2e0000,
1658 GRCBASE_TCFC = 0x2d0000,
1659 GRCBASE_IGU = 0x180000,
1660 GRCBASE_CAU = 0x1c0000,
1661 GRCBASE_RGFS = 0xf00000,
1662 GRCBASE_RGSRC = 0x320000,
1663 GRCBASE_TGFS = 0xd00000,
1664 GRCBASE_TGSRC = 0x322000,
1665 GRCBASE_UMAC = 0x51000,
1666 GRCBASE_XMAC = 0x210000,
1667 GRCBASE_DBG = 0x10000,
1668 GRCBASE_NIG = 0x500000,
1669 GRCBASE_WOL = 0x600000,
1670 GRCBASE_BMBN = 0x610000,
1671 GRCBASE_IPC = 0x20000,
1672 GRCBASE_NWM = 0x800000,
1673 GRCBASE_NWS = 0x700000,
1674 GRCBASE_MS = 0x6a0000,
1675 GRCBASE_PHY_PCIE = 0x620000,
1676 GRCBASE_LED = 0x6b8000,
1677 GRCBASE_AVS_WRAP = 0x6b0000,
1678 GRCBASE_MISC_AEU = 0x8000,
1679 GRCBASE_BAR0_MAP = 0x1c00000,
1774 /* binary debug buffer types */
1775 enum bin_dbg_buffer_type {
1776 BIN_BUF_DBG_MODE_TREE,
1777 BIN_BUF_DBG_DUMP_REG,
1778 BIN_BUF_DBG_DUMP_MEM,
1779 BIN_BUF_DBG_IDLE_CHK_REGS,
1780 BIN_BUF_DBG_IDLE_CHK_IMMS,
1781 BIN_BUF_DBG_IDLE_CHK_RULES,
1782 BIN_BUF_DBG_IDLE_CHK_PARSING_DATA,
1783 BIN_BUF_DBG_ATTN_BLOCKS,
1784 BIN_BUF_DBG_ATTN_REGS,
1785 BIN_BUF_DBG_ATTN_INDEXES,
1786 BIN_BUF_DBG_ATTN_NAME_OFFSETS,
1787 BIN_BUF_DBG_BUS_BLOCKS,
1788 BIN_BUF_DBG_BUS_LINES,
1789 BIN_BUF_DBG_BUS_BLOCKS_USER_DATA,
1790 BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS,
1791 BIN_BUF_DBG_PARSING_STRINGS,
1792 MAX_BIN_DBG_BUFFER_TYPE
1796 /* Attention bit mapping */
1797 struct dbg_attn_bit_mapping {
1799 #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF
1800 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0
1801 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1
1802 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15
1805 /* Attention block per-type data */
1806 struct dbg_attn_block_type_data {
1807 __le16 names_offset;
1814 /* Block attentions */
1815 struct dbg_attn_block {
1816 struct dbg_attn_block_type_data per_type_data[2];
1819 /* Attention register result */
1820 struct dbg_attn_reg_result {
1822 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF
1823 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0
1824 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF
1825 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24
1826 __le16 block_attn_offset;
1832 /* Attention block result */
1833 struct dbg_attn_block_result {
1836 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3
1837 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0
1838 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F
1839 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2
1840 __le16 names_offset;
1841 struct dbg_attn_reg_result reg_results[15];
1845 struct dbg_mode_hdr {
1847 #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1
1848 #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0
1849 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF
1850 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1
1853 /* Attention register */
1854 struct dbg_attn_reg {
1855 struct dbg_mode_hdr mode;
1856 __le16 block_attn_offset;
1858 #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF
1859 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0
1860 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF
1861 #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24
1862 __le32 sts_clr_address;
1863 __le32 mask_address;
1866 /* attention types */
1867 enum dbg_attn_type {
1868 ATTN_TYPE_INTERRUPT,
1873 struct dbg_bus_block {
1875 u8 has_latency_events;
1876 __le16 lines_offset;
1879 struct dbg_bus_block_user_data {
1881 u8 has_latency_events;
1882 __le16 names_offset;
1885 struct dbg_bus_line {
1887 #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF
1888 #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0
1889 #define DBG_BUS_LINE_IS_256B_MASK 0x1
1890 #define DBG_BUS_LINE_IS_256B_SHIFT 4
1891 #define DBG_BUS_LINE_RESERVED_MASK 0x7
1892 #define DBG_BUS_LINE_RESERVED_SHIFT 5
1896 /* condition header for registers dump */
1897 struct dbg_dump_cond_hdr {
1898 struct dbg_mode_hdr mode; /* Mode header */
1899 u8 block_id; /* block ID */
1900 u8 data_size; /* size in dwords of the data following this header */
1903 /* memory data for registers dump */
1904 struct dbg_dump_mem {
1906 #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF
1907 #define DBG_DUMP_MEM_ADDRESS_SHIFT 0
1908 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF
1909 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
1911 #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF
1912 #define DBG_DUMP_MEM_LENGTH_SHIFT 0
1913 #define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1
1914 #define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24
1915 #define DBG_DUMP_MEM_RESERVED_MASK 0x7F
1916 #define DBG_DUMP_MEM_RESERVED_SHIFT 25
1919 /* register data for registers dump */
1920 struct dbg_dump_reg {
1922 #define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF /* register address (in dwords) */
1923 #define DBG_DUMP_REG_ADDRESS_SHIFT 0
1924 #define DBG_DUMP_REG_WIDE_BUS_MASK 0x1 /* indicates register is wide-bus */
1925 #define DBG_DUMP_REG_WIDE_BUS_SHIFT 23
1926 #define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */
1927 #define DBG_DUMP_REG_LENGTH_SHIFT 24
1930 /* split header for registers dump */
1931 struct dbg_dump_split_hdr {
1933 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF
1934 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0
1935 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF
1936 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24
1939 /* condition header for idle check */
1940 struct dbg_idle_chk_cond_hdr {
1941 struct dbg_mode_hdr mode; /* Mode header */
1942 __le16 data_size; /* size in dwords of the data following this header */
1945 /* Idle Check condition register */
1946 struct dbg_idle_chk_cond_reg {
1948 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF
1949 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0
1950 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1
1951 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23
1952 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF
1953 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24
1959 /* Idle Check info register */
1960 struct dbg_idle_chk_info_reg {
1962 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF
1963 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0
1964 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1
1965 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23
1966 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF
1967 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24
1968 __le16 size; /* register size in dwords */
1969 struct dbg_mode_hdr mode; /* Mode header */
1972 /* Idle Check register */
1973 union dbg_idle_chk_reg {
1974 struct dbg_idle_chk_cond_reg cond_reg; /* condition register */
1975 struct dbg_idle_chk_info_reg info_reg; /* info register */
1978 /* Idle Check result header */
1979 struct dbg_idle_chk_result_hdr {
1980 __le16 rule_id; /* Failing rule index */
1981 __le16 mem_entry_id; /* Failing memory entry index */
1982 u8 num_dumped_cond_regs; /* number of dumped condition registers */
1983 u8 num_dumped_info_regs; /* number of dumped condition registers */
1984 u8 severity; /* from dbg_idle_chk_severity_types enum */
1988 /* Idle Check result register header */
1989 struct dbg_idle_chk_result_reg_hdr {
1991 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1
1992 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
1993 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F
1994 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
1995 u8 start_entry; /* index of the first checked entry */
1996 __le16 size; /* register size in dwords */
1999 /* Idle Check rule */
2000 struct dbg_idle_chk_rule {
2001 __le16 rule_id; /* Idle Check rule ID */
2002 u8 severity; /* value from dbg_idle_chk_severity_types enum */
2003 u8 cond_id; /* Condition ID */
2004 u8 num_cond_regs; /* number of condition registers */
2005 u8 num_info_regs; /* number of info registers */
2006 u8 num_imms; /* number of immediates in the condition */
2008 __le16 reg_offset; /* offset of this rules registers in the idle check
2009 * register array (in dbg_idle_chk_reg units).
2011 __le16 imm_offset; /* offset of this rules immediate values in the
2012 * immediate values array (in dwords).
2016 /* Idle Check rule parsing data */
2017 struct dbg_idle_chk_rule_parsing_data {
2019 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1
2020 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
2021 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF
2022 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
2025 /* idle check severity types */
2026 enum dbg_idle_chk_severity_types {
2027 /* idle check failure should cause an error */
2028 IDLE_CHK_SEVERITY_ERROR,
2029 /* idle check failure should cause an error only if theres no traffic */
2030 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
2031 /* idle check failure should cause a warning */
2032 IDLE_CHK_SEVERITY_WARNING,
2033 MAX_DBG_IDLE_CHK_SEVERITY_TYPES
2036 /* Debug Bus block data */
2037 struct dbg_bus_block_data {
2039 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF
2040 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0
2041 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF
2042 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4
2043 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF
2044 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8
2045 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF
2046 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12
2051 /* Debug Bus Clients */
2052 enum dbg_bus_clients {
2053 DBG_BUS_CLIENT_RBCN,
2054 DBG_BUS_CLIENT_RBCP,
2055 DBG_BUS_CLIENT_RBCR,
2056 DBG_BUS_CLIENT_RBCT,
2057 DBG_BUS_CLIENT_RBCU,
2058 DBG_BUS_CLIENT_RBCF,
2059 DBG_BUS_CLIENT_RBCX,
2060 DBG_BUS_CLIENT_RBCS,
2061 DBG_BUS_CLIENT_RBCH,
2062 DBG_BUS_CLIENT_RBCZ,
2063 DBG_BUS_CLIENT_OTHER_ENGINE,
2064 DBG_BUS_CLIENT_TIMESTAMP,
2066 DBG_BUS_CLIENT_RBCY,
2067 DBG_BUS_CLIENT_RBCQ,
2068 DBG_BUS_CLIENT_RBCM,
2069 DBG_BUS_CLIENT_RBCB,
2070 DBG_BUS_CLIENT_RBCW,
2071 DBG_BUS_CLIENT_RBCV,
2075 enum dbg_bus_constraint_ops {
2076 DBG_BUS_CONSTRAINT_OP_EQ,
2077 DBG_BUS_CONSTRAINT_OP_NE,
2078 DBG_BUS_CONSTRAINT_OP_LT,
2079 DBG_BUS_CONSTRAINT_OP_LTC,
2080 DBG_BUS_CONSTRAINT_OP_LE,
2081 DBG_BUS_CONSTRAINT_OP_LEC,
2082 DBG_BUS_CONSTRAINT_OP_GT,
2083 DBG_BUS_CONSTRAINT_OP_GTC,
2084 DBG_BUS_CONSTRAINT_OP_GE,
2085 DBG_BUS_CONSTRAINT_OP_GEC,
2086 MAX_DBG_BUS_CONSTRAINT_OPS
2089 struct dbg_bus_trigger_state_data {
2091 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF
2092 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0
2093 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF
2094 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4
2097 /* Debug Bus memory address */
2098 struct dbg_bus_mem_addr {
2103 /* Debug Bus PCI buffer data */
2104 struct dbg_bus_pci_buf_data {
2105 struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */
2106 struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */
2107 __le32 size; /* PCI buffer size in bytes */
2110 /* Debug Bus Storm EID range filter params */
2111 struct dbg_bus_storm_eid_range_params {
2112 u8 min; /* Minimal event ID to filter on */
2113 u8 max; /* Maximal event ID to filter on */
2116 /* Debug Bus Storm EID mask filter params */
2117 struct dbg_bus_storm_eid_mask_params {
2118 u8 val; /* Event ID value */
2119 u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */
2122 /* Debug Bus Storm EID filter params */
2123 union dbg_bus_storm_eid_params {
2124 struct dbg_bus_storm_eid_range_params range;
2125 struct dbg_bus_storm_eid_mask_params mask;
2128 /* Debug Bus Storm data */
2129 struct dbg_bus_storm_data {
2134 u8 eid_range_not_mask;
2136 union dbg_bus_storm_eid_params eid_filter_params;
2140 /* Debug Bus data */
2141 struct dbg_bus_data {
2146 u8 num_enabled_blocks;
2147 u8 num_enabled_storms;
2151 u8 timestamp_input_en;
2154 u8 filter_pre_trigger;
2155 u8 filter_post_trigger;
2158 struct dbg_bus_trigger_state_data trigger_states[3];
2159 u8 next_trigger_state;
2160 u8 next_constraint_id;
2162 u8 rcv_from_other_engine;
2163 struct dbg_bus_pci_buf_data pci_buf;
2164 struct dbg_bus_block_data blocks[88];
2165 struct dbg_bus_storm_data storms[6];
2168 enum dbg_bus_filter_types {
2169 DBG_BUS_FILTER_TYPE_OFF,
2170 DBG_BUS_FILTER_TYPE_PRE,
2171 DBG_BUS_FILTER_TYPE_POST,
2172 DBG_BUS_FILTER_TYPE_ON,
2173 MAX_DBG_BUS_FILTER_TYPES
2176 /* Debug bus frame modes */
2177 enum dbg_bus_frame_modes {
2178 DBG_BUS_FRAME_MODE_0HW_4ST = 0, /* 0 HW dwords, 4 Storm dwords */
2179 DBG_BUS_FRAME_MODE_4HW_0ST = 3, /* 4 HW dwords, 0 Storm dwords */
2180 DBG_BUS_FRAME_MODE_8HW_0ST = 4, /* 8 HW dwords, 0 Storm dwords */
2181 MAX_DBG_BUS_FRAME_MODES
2184 enum dbg_bus_other_engine_modes {
2185 DBG_BUS_OTHER_ENGINE_MODE_NONE,
2186 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,
2187 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX,
2188 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX,
2189 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX,
2190 MAX_DBG_BUS_OTHER_ENGINE_MODES
2193 enum dbg_bus_post_trigger_types {
2194 DBG_BUS_POST_TRIGGER_RECORD,
2195 DBG_BUS_POST_TRIGGER_DROP,
2196 MAX_DBG_BUS_POST_TRIGGER_TYPES
2199 enum dbg_bus_pre_trigger_types {
2200 DBG_BUS_PRE_TRIGGER_START_FROM_ZERO,
2201 DBG_BUS_PRE_TRIGGER_NUM_CHUNKS,
2202 DBG_BUS_PRE_TRIGGER_DROP,
2203 MAX_DBG_BUS_PRE_TRIGGER_TYPES
2206 enum dbg_bus_semi_frame_modes {
2207 DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST =
2209 DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST =
2211 MAX_DBG_BUS_SEMI_FRAME_MODES
2214 /* Debug bus states */
2215 enum dbg_bus_states {
2217 DBG_BUS_STATE_READY,
2218 DBG_BUS_STATE_RECORDING,
2219 DBG_BUS_STATE_STOPPED,
2223 enum dbg_bus_storm_modes {
2224 DBG_BUS_STORM_MODE_PRINTF,
2225 DBG_BUS_STORM_MODE_PRAM_ADDR,
2226 DBG_BUS_STORM_MODE_DRA_RW,
2227 DBG_BUS_STORM_MODE_DRA_W,
2228 DBG_BUS_STORM_MODE_LD_ST_ADDR,
2229 DBG_BUS_STORM_MODE_DRA_FSM,
2230 DBG_BUS_STORM_MODE_RH,
2231 DBG_BUS_STORM_MODE_FOC,
2232 DBG_BUS_STORM_MODE_EXT_STORE,
2233 MAX_DBG_BUS_STORM_MODES
2236 /* Debug bus target IDs */
2237 enum dbg_bus_targets {
2238 DBG_BUS_TARGET_ID_INT_BUF,
2239 DBG_BUS_TARGET_ID_NIG,
2240 DBG_BUS_TARGET_ID_PCI,
2245 struct dbg_grc_data {
2246 u8 params_initialized;
2249 __le32 param_val[48];
2252 /* Debug GRC params */
2253 enum dbg_grc_params {
2254 DBG_GRC_PARAM_DUMP_TSTORM,
2255 DBG_GRC_PARAM_DUMP_MSTORM,
2256 DBG_GRC_PARAM_DUMP_USTORM,
2257 DBG_GRC_PARAM_DUMP_XSTORM,
2258 DBG_GRC_PARAM_DUMP_YSTORM,
2259 DBG_GRC_PARAM_DUMP_PSTORM,
2260 DBG_GRC_PARAM_DUMP_REGS,
2261 DBG_GRC_PARAM_DUMP_RAM,
2262 DBG_GRC_PARAM_DUMP_PBUF,
2263 DBG_GRC_PARAM_DUMP_IOR,
2264 DBG_GRC_PARAM_DUMP_VFC,
2265 DBG_GRC_PARAM_DUMP_CM_CTX,
2266 DBG_GRC_PARAM_DUMP_PXP,
2267 DBG_GRC_PARAM_DUMP_RSS,
2268 DBG_GRC_PARAM_DUMP_CAU,
2269 DBG_GRC_PARAM_DUMP_QM,
2270 DBG_GRC_PARAM_DUMP_MCP,
2271 DBG_GRC_PARAM_RESERVED,
2272 DBG_GRC_PARAM_DUMP_CFC,
2273 DBG_GRC_PARAM_DUMP_IGU,
2274 DBG_GRC_PARAM_DUMP_BRB,
2275 DBG_GRC_PARAM_DUMP_BTB,
2276 DBG_GRC_PARAM_DUMP_BMB,
2277 DBG_GRC_PARAM_DUMP_NIG,
2278 DBG_GRC_PARAM_DUMP_MULD,
2279 DBG_GRC_PARAM_DUMP_PRS,
2280 DBG_GRC_PARAM_DUMP_DMAE,
2281 DBG_GRC_PARAM_DUMP_TM,
2282 DBG_GRC_PARAM_DUMP_SDM,
2283 DBG_GRC_PARAM_DUMP_DIF,
2284 DBG_GRC_PARAM_DUMP_STATIC,
2285 DBG_GRC_PARAM_UNSTALL,
2286 DBG_GRC_PARAM_NUM_LCIDS,
2287 DBG_GRC_PARAM_NUM_LTIDS,
2288 DBG_GRC_PARAM_EXCLUDE_ALL,
2289 DBG_GRC_PARAM_CRASH,
2290 DBG_GRC_PARAM_PARITY_SAFE,
2291 DBG_GRC_PARAM_DUMP_CM,
2292 DBG_GRC_PARAM_DUMP_PHY,
2293 DBG_GRC_PARAM_NO_MCP,
2294 DBG_GRC_PARAM_NO_FW_VER,
2298 /* Debug reset registers */
2299 enum dbg_reset_regs {
2300 DBG_RESET_REG_MISCS_PL_UA,
2301 DBG_RESET_REG_MISCS_PL_HV,
2302 DBG_RESET_REG_MISCS_PL_HV_2,
2303 DBG_RESET_REG_MISC_PL_UA,
2304 DBG_RESET_REG_MISC_PL_HV,
2305 DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
2306 DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
2307 DBG_RESET_REG_MISC_PL_PDA_VAUX,
2311 /* Debug status codes */
2314 DBG_STATUS_APP_VERSION_NOT_SET,
2315 DBG_STATUS_UNSUPPORTED_APP_VERSION,
2316 DBG_STATUS_DBG_BLOCK_NOT_RESET,
2317 DBG_STATUS_INVALID_ARGS,
2318 DBG_STATUS_OUTPUT_ALREADY_SET,
2319 DBG_STATUS_INVALID_PCI_BUF_SIZE,
2320 DBG_STATUS_PCI_BUF_ALLOC_FAILED,
2321 DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
2322 DBG_STATUS_TOO_MANY_INPUTS,
2323 DBG_STATUS_INPUT_OVERLAP,
2324 DBG_STATUS_HW_ONLY_RECORDING,
2325 DBG_STATUS_STORM_ALREADY_ENABLED,
2326 DBG_STATUS_STORM_NOT_ENABLED,
2327 DBG_STATUS_BLOCK_ALREADY_ENABLED,
2328 DBG_STATUS_BLOCK_NOT_ENABLED,
2329 DBG_STATUS_NO_INPUT_ENABLED,
2330 DBG_STATUS_NO_FILTER_TRIGGER_64B,
2331 DBG_STATUS_FILTER_ALREADY_ENABLED,
2332 DBG_STATUS_TRIGGER_ALREADY_ENABLED,
2333 DBG_STATUS_TRIGGER_NOT_ENABLED,
2334 DBG_STATUS_CANT_ADD_CONSTRAINT,
2335 DBG_STATUS_TOO_MANY_TRIGGER_STATES,
2336 DBG_STATUS_TOO_MANY_CONSTRAINTS,
2337 DBG_STATUS_RECORDING_NOT_STARTED,
2338 DBG_STATUS_DATA_DIDNT_TRIGGER,
2339 DBG_STATUS_NO_DATA_RECORDED,
2340 DBG_STATUS_DUMP_BUF_TOO_SMALL,
2341 DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
2342 DBG_STATUS_UNKNOWN_CHIP,
2343 DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
2344 DBG_STATUS_BLOCK_IN_RESET,
2345 DBG_STATUS_INVALID_TRACE_SIGNATURE,
2346 DBG_STATUS_INVALID_NVRAM_BUNDLE,
2347 DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
2348 DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
2349 DBG_STATUS_NVRAM_READ_FAILED,
2350 DBG_STATUS_IDLE_CHK_PARSE_FAILED,
2351 DBG_STATUS_MCP_TRACE_BAD_DATA,
2352 DBG_STATUS_MCP_TRACE_NO_META,
2353 DBG_STATUS_MCP_COULD_NOT_HALT,
2354 DBG_STATUS_MCP_COULD_NOT_RESUME,
2355 DBG_STATUS_DMAE_FAILED,
2356 DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
2357 DBG_STATUS_IGU_FIFO_BAD_DATA,
2358 DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
2359 DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
2360 DBG_STATUS_REG_FIFO_BAD_DATA,
2361 DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
2362 DBG_STATUS_DBG_ARRAY_NOT_SET,
2363 DBG_STATUS_FILTER_BUG,
2364 DBG_STATUS_NON_MATCHING_LINES,
2365 DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET,
2366 DBG_STATUS_DBG_BUS_IN_USE,
2370 /* Debug Storms IDs */
2381 /* Idle Check data */
2382 struct idle_chk_data {
2389 /* Debug Tools data (per HW function) */
2390 struct dbg_tools_data {
2391 struct dbg_grc_data grc;
2392 struct dbg_bus_data bus;
2393 struct idle_chk_data idle_chk;
2395 u8 block_in_reset[88];
2402 /********************************/
2403 /* HSI Init Functions constants */
2404 /********************************/
2406 /* Number of VLAN priorities */
2407 #define NUM_OF_VLAN_PRIORITIES 8
2409 struct init_brb_ram_req {
2410 __le32 guranteed_per_tc;
2411 __le32 headroom_per_tc;
2412 __le32 min_pkt_size;
2413 __le32 max_ports_per_engine;
2414 u8 num_active_tcs[MAX_NUM_PORTS];
2417 struct init_ets_tc_req {
2423 struct init_ets_req {
2425 struct init_ets_tc_req tc_req[NUM_OF_TCS];
2428 struct init_nig_lb_rl_req {
2432 __le16 tc_rate[NUM_OF_PHYS_TCS];
2435 struct init_nig_pri_tc_map_entry {
2440 struct init_nig_pri_tc_map_req {
2441 struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
2444 struct init_qm_port_params {
2447 __le16 num_pbf_cmd_lines;
2448 __le16 num_btb_blocks;
2452 /* QM per-PQ init parameters */
2453 struct init_qm_pq_params {
2460 /* QM per-vport init parameters */
2461 struct init_qm_vport_params {
2464 __le16 first_tx_pq_id[NUM_OF_TCS];
2467 /**************************************/
2468 /* Init Tool HSI constants and macros */
2469 /**************************************/
2471 /* Width of GRC address in bits (addresses are specified in dwords) */
2472 #define GRC_ADDR_BITS 23
2473 #define MAX_GRC_ADDR (BIT(GRC_ADDR_BITS) - 1)
2475 /* indicates an init that should be applied to any phase ID */
2476 #define ANY_PHASE_ID 0xffff
2478 /* Max size in dwords of a zipped array */
2479 #define MAX_ZIPPED_SIZE 8192
2487 struct fw_asserts_ram_section {
2488 __le16 section_ram_line_offset;
2489 __le16 section_ram_line_size;
2490 u8 list_dword_offset;
2491 u8 list_element_dword_size;
2492 u8 list_num_elements;
2493 u8 list_next_index_dword_offset;
2503 struct fw_ver_info {
2507 struct fw_ver_num num;
2513 struct fw_ver_info ver;
2514 struct fw_asserts_ram_section fw_asserts_section;
2517 struct fw_info_location {
2534 MODE_PORTS_PER_ENG_1,
2535 MODE_PORTS_PER_ENG_2,
2536 MODE_PORTS_PER_ENG_4,
2551 enum init_split_types {
2557 MAX_INIT_SPLIT_TYPES
2560 /* Binary buffer header */
2561 struct bin_buffer_hdr {
2566 /* binary init buffer types */
2567 enum bin_init_buffer_type {
2568 BIN_BUF_INIT_FW_VER_INFO,
2571 BIN_BUF_INIT_MODE_TREE,
2573 MAX_BIN_INIT_BUFFER_TYPE
2576 /* init array header: raw */
2577 struct init_array_raw_hdr {
2579 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
2580 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
2581 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
2582 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
2585 /* init array header: standard */
2586 struct init_array_standard_hdr {
2588 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
2589 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
2590 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
2591 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
2594 /* init array header: zipped */
2595 struct init_array_zipped_hdr {
2597 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
2598 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
2599 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
2600 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
2603 /* init array header: pattern */
2604 struct init_array_pattern_hdr {
2606 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
2607 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
2608 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
2609 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
2610 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
2611 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
2614 /* init array header union */
2615 union init_array_hdr {
2616 struct init_array_raw_hdr raw;
2617 struct init_array_standard_hdr standard;
2618 struct init_array_zipped_hdr zipped;
2619 struct init_array_pattern_hdr pattern;
2622 /* init array types */
2623 enum init_array_types {
2627 MAX_INIT_ARRAY_TYPES
2630 /* init operation: callback */
2631 struct init_callback_op {
2633 #define INIT_CALLBACK_OP_OP_MASK 0xF
2634 #define INIT_CALLBACK_OP_OP_SHIFT 0
2635 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
2636 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
2641 /* init operation: delay */
2642 struct init_delay_op {
2644 #define INIT_DELAY_OP_OP_MASK 0xF
2645 #define INIT_DELAY_OP_OP_SHIFT 0
2646 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
2647 #define INIT_DELAY_OP_RESERVED_SHIFT 4
2651 /* init operation: if_mode */
2652 struct init_if_mode_op {
2654 #define INIT_IF_MODE_OP_OP_MASK 0xF
2655 #define INIT_IF_MODE_OP_OP_SHIFT 0
2656 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
2657 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
2658 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
2659 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
2661 __le16 modes_buf_offset;
2664 /* init operation: if_phase */
2665 struct init_if_phase_op {
2667 #define INIT_IF_PHASE_OP_OP_MASK 0xF
2668 #define INIT_IF_PHASE_OP_OP_SHIFT 0
2669 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
2670 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
2671 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
2672 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
2673 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
2674 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
2676 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF
2677 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0
2678 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
2679 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
2680 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF
2681 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
2684 /* init mode operators */
2685 enum init_mode_ops {
2692 /* init operation: raw */
2693 struct init_raw_op {
2695 #define INIT_RAW_OP_OP_MASK 0xF
2696 #define INIT_RAW_OP_OP_SHIFT 0
2697 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF
2698 #define INIT_RAW_OP_PARAM1_SHIFT 4
2702 /* init array params */
2703 struct init_op_array_params {
2708 /* Write init operation arguments */
2709 union init_write_args {
2712 __le32 array_offset;
2713 struct init_op_array_params runtime;
2716 /* init operation: write */
2717 struct init_write_op {
2719 #define INIT_WRITE_OP_OP_MASK 0xF
2720 #define INIT_WRITE_OP_OP_SHIFT 0
2721 #define INIT_WRITE_OP_SOURCE_MASK 0x7
2722 #define INIT_WRITE_OP_SOURCE_SHIFT 4
2723 #define INIT_WRITE_OP_RESERVED_MASK 0x1
2724 #define INIT_WRITE_OP_RESERVED_SHIFT 7
2725 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
2726 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
2727 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
2728 #define INIT_WRITE_OP_ADDRESS_SHIFT 9
2729 union init_write_args args;
2732 /* init operation: read */
2733 struct init_read_op {
2735 #define INIT_READ_OP_OP_MASK 0xF
2736 #define INIT_READ_OP_OP_SHIFT 0
2737 #define INIT_READ_OP_POLL_TYPE_MASK 0xF
2738 #define INIT_READ_OP_POLL_TYPE_SHIFT 4
2739 #define INIT_READ_OP_RESERVED_MASK 0x1
2740 #define INIT_READ_OP_RESERVED_SHIFT 8
2741 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
2742 #define INIT_READ_OP_ADDRESS_SHIFT 9
2743 __le32 expected_val;
2746 /* Init operations union */
2748 struct init_raw_op raw;
2749 struct init_write_op write;
2750 struct init_read_op read;
2751 struct init_if_mode_op if_mode;
2752 struct init_if_phase_op if_phase;
2753 struct init_callback_op callback;
2754 struct init_delay_op delay;
2757 /* Init command operation types */
2758 enum init_op_types {
2768 /* init polling types */
2769 enum init_poll_types {
2777 /* init source types */
2778 enum init_source_types {
2783 MAX_INIT_SOURCE_TYPES
2786 /* Internal RAM Offsets macro data */
2795 /***************************** Public Functions *******************************/
2797 * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug
2800 * @param bin_ptr - a pointer to the binary data with debug arrays.
2802 enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr);
2805 * @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their
2808 * @param p_hwfn - HW device data
2810 void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn);
2812 * @brief qed_dbg_grc_get_dump_buf_size - Returns the required buffer size for
2815 * @param p_hwfn - HW device data
2816 * @param p_ptt - Ptt window used for writing the registers.
2817 * @param buf_size - OUT: required buffer size (in dwords) for the GRC Dump
2820 * @return error if one of the following holds:
2821 * - the version wasn't set
2822 * Otherwise, returns ok.
2824 enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2825 struct qed_ptt *p_ptt,
2829 * @brief qed_dbg_grc_dump - Dumps GRC data into the specified buffer.
2831 * @param p_hwfn - HW device data
2832 * @param p_ptt - Ptt window used for writing the registers.
2833 * @param dump_buf - Pointer to write the collected GRC data into.
2834 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2835 * @param num_dumped_dwords - OUT: number of dumped dwords.
2837 * @return error if one of the following holds:
2838 * - the version wasn't set
2839 * - the specified dump buffer is too small
2840 * Otherwise, returns ok.
2842 enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn,
2843 struct qed_ptt *p_ptt,
2845 u32 buf_size_in_dwords,
2846 u32 *num_dumped_dwords);
2849 * @brief qed_dbg_idle_chk_get_dump_buf_size - Returns the required buffer size
2850 * for idle check results.
2852 * @param p_hwfn - HW device data
2853 * @param p_ptt - Ptt window used for writing the registers.
2854 * @param buf_size - OUT: required buffer size (in dwords) for the idle check
2857 * @return error if one of the following holds:
2858 * - the version wasn't set
2859 * Otherwise, returns ok.
2861 enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2862 struct qed_ptt *p_ptt,
2866 * @brief qed_dbg_idle_chk_dump - Performs idle check and writes the results
2867 * into the specified buffer.
2869 * @param p_hwfn - HW device data
2870 * @param p_ptt - Ptt window used for writing the registers.
2871 * @param dump_buf - Pointer to write the idle check data into.
2872 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2873 * @param num_dumped_dwords - OUT: number of dumped dwords.
2875 * @return error if one of the following holds:
2876 * - the version wasn't set
2877 * - the specified buffer is too small
2878 * Otherwise, returns ok.
2880 enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn,
2881 struct qed_ptt *p_ptt,
2883 u32 buf_size_in_dwords,
2884 u32 *num_dumped_dwords);
2887 * @brief qed_dbg_mcp_trace_get_dump_buf_size - Returns the required buffer size
2888 * for mcp trace results.
2890 * @param p_hwfn - HW device data
2891 * @param p_ptt - Ptt window used for writing the registers.
2892 * @param buf_size - OUT: required buffer size (in dwords) for mcp trace data.
2894 * @return error if one of the following holds:
2895 * - the version wasn't set
2896 * - the trace data in MCP scratchpad contain an invalid signature
2897 * - the bundle ID in NVRAM is invalid
2898 * - the trace meta data cannot be found (in NVRAM or image file)
2899 * Otherwise, returns ok.
2901 enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2902 struct qed_ptt *p_ptt,
2906 * @brief qed_dbg_mcp_trace_dump - Performs mcp trace and writes the results
2907 * into the specified buffer.
2909 * @param p_hwfn - HW device data
2910 * @param p_ptt - Ptt window used for writing the registers.
2911 * @param dump_buf - Pointer to write the mcp trace data into.
2912 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2913 * @param num_dumped_dwords - OUT: number of dumped dwords.
2915 * @return error if one of the following holds:
2916 * - the version wasn't set
2917 * - the specified buffer is too small
2918 * - the trace data in MCP scratchpad contain an invalid signature
2919 * - the bundle ID in NVRAM is invalid
2920 * - the trace meta data cannot be found (in NVRAM or image file)
2921 * - the trace meta data cannot be read (from NVRAM or image file)
2922 * Otherwise, returns ok.
2924 enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn,
2925 struct qed_ptt *p_ptt,
2927 u32 buf_size_in_dwords,
2928 u32 *num_dumped_dwords);
2931 * @brief qed_dbg_reg_fifo_get_dump_buf_size - Returns the required buffer size
2932 * for grc trace fifo results.
2934 * @param p_hwfn - HW device data
2935 * @param p_ptt - Ptt window used for writing the registers.
2936 * @param buf_size - OUT: required buffer size (in dwords) for reg fifo data.
2938 * @return error if one of the following holds:
2939 * - the version wasn't set
2940 * Otherwise, returns ok.
2942 enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2943 struct qed_ptt *p_ptt,
2947 * @brief qed_dbg_reg_fifo_dump - Reads the reg fifo and writes the results into
2948 * the specified buffer.
2950 * @param p_hwfn - HW device data
2951 * @param p_ptt - Ptt window used for writing the registers.
2952 * @param dump_buf - Pointer to write the reg fifo data into.
2953 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2954 * @param num_dumped_dwords - OUT: number of dumped dwords.
2956 * @return error if one of the following holds:
2957 * - the version wasn't set
2958 * - the specified buffer is too small
2959 * - DMAE transaction failed
2960 * Otherwise, returns ok.
2962 enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn,
2963 struct qed_ptt *p_ptt,
2965 u32 buf_size_in_dwords,
2966 u32 *num_dumped_dwords);
2969 * @brief qed_dbg_igu_fifo_get_dump_buf_size - Returns the required buffer size
2970 * for the IGU fifo results.
2972 * @param p_hwfn - HW device data
2973 * @param p_ptt - Ptt window used for writing the registers.
2974 * @param buf_size - OUT: required buffer size (in dwords) for the IGU fifo
2977 * @return error if one of the following holds:
2978 * - the version wasn't set
2979 * Otherwise, returns ok.
2981 enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2982 struct qed_ptt *p_ptt,
2986 * @brief qed_dbg_igu_fifo_dump - Reads the IGU fifo and writes the results into
2987 * the specified buffer.
2989 * @param p_hwfn - HW device data
2990 * @param p_ptt - Ptt window used for writing the registers.
2991 * @param dump_buf - Pointer to write the IGU fifo data into.
2992 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2993 * @param num_dumped_dwords - OUT: number of dumped dwords.
2995 * @return error if one of the following holds:
2996 * - the version wasn't set
2997 * - the specified buffer is too small
2998 * - DMAE transaction failed
2999 * Otherwise, returns ok.
3001 enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn,
3002 struct qed_ptt *p_ptt,
3004 u32 buf_size_in_dwords,
3005 u32 *num_dumped_dwords);
3008 * @brief qed_dbg_protection_override_get_dump_buf_size - Returns the required
3009 * buffer size for protection override window results.
3011 * @param p_hwfn - HW device data
3012 * @param p_ptt - Ptt window used for writing the registers.
3013 * @param buf_size - OUT: required buffer size (in dwords) for protection
3016 * @return error if one of the following holds:
3017 * - the version wasn't set
3018 * Otherwise, returns ok.
3021 qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3022 struct qed_ptt *p_ptt,
3025 * @brief qed_dbg_protection_override_dump - Reads protection override window
3026 * entries and writes the results into the specified buffer.
3028 * @param p_hwfn - HW device data
3029 * @param p_ptt - Ptt window used for writing the registers.
3030 * @param dump_buf - Pointer to write the protection override data into.
3031 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3032 * @param num_dumped_dwords - OUT: number of dumped dwords.
3034 * @return error if one of the following holds:
3035 * - the version wasn't set
3036 * - the specified buffer is too small
3037 * - DMAE transaction failed
3038 * Otherwise, returns ok.
3040 enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn,
3041 struct qed_ptt *p_ptt,
3043 u32 buf_size_in_dwords,
3044 u32 *num_dumped_dwords);
3046 * @brief qed_dbg_fw_asserts_get_dump_buf_size - Returns the required buffer
3047 * size for FW Asserts results.
3049 * @param p_hwfn - HW device data
3050 * @param p_ptt - Ptt window used for writing the registers.
3051 * @param buf_size - OUT: required buffer size (in dwords) for FW Asserts data.
3053 * @return error if one of the following holds:
3054 * - the version wasn't set
3055 * Otherwise, returns ok.
3057 enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3058 struct qed_ptt *p_ptt,
3061 * @brief qed_dbg_fw_asserts_dump - Reads the FW Asserts and writes the results
3062 * into the specified buffer.
3064 * @param p_hwfn - HW device data
3065 * @param p_ptt - Ptt window used for writing the registers.
3066 * @param dump_buf - Pointer to write the FW Asserts data into.
3067 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3068 * @param num_dumped_dwords - OUT: number of dumped dwords.
3070 * @return error if one of the following holds:
3071 * - the version wasn't set
3072 * - the specified buffer is too small
3073 * Otherwise, returns ok.
3075 enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn,
3076 struct qed_ptt *p_ptt,
3078 u32 buf_size_in_dwords,
3079 u32 *num_dumped_dwords);
3082 * @brief qed_dbg_read_attn - Reads the attention registers of the specified
3083 * block and type, and writes the results into the specified buffer.
3085 * @param p_hwfn - HW device data
3086 * @param p_ptt - Ptt window used for writing the registers.
3087 * @param block - Block ID.
3088 * @param attn_type - Attention type.
3089 * @param clear_status - Indicates if the attention status should be cleared.
3090 * @param results - OUT: Pointer to write the read results into
3092 * @return error if one of the following holds:
3093 * - the version wasn't set
3094 * Otherwise, returns ok.
3096 enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn,
3097 struct qed_ptt *p_ptt,
3098 enum block_id block,
3099 enum dbg_attn_type attn_type,
3101 struct dbg_attn_block_result *results);
3104 * @brief qed_dbg_print_attn - Prints attention registers values in the
3105 * specified results struct.
3108 * @param results - Pointer to the attention read results
3110 * @return error if one of the following holds:
3111 * - the version wasn't set
3112 * Otherwise, returns ok.
3114 enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
3115 struct dbg_attn_block_result *results);
3117 /******************************** Constants **********************************/
3119 #define MAX_NAME_LEN 16
3121 /***************************** Public Functions *******************************/
3123 * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with
3126 * @param bin_ptr - a pointer to the binary data with debug arrays.
3128 enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr);
3131 * @brief qed_dbg_get_status_str - Returns a string for the specified status.
3133 * @param status - a debug status code.
3135 * @return a string for the specified status
3137 const char *qed_dbg_get_status_str(enum dbg_status status);
3140 * @brief qed_get_idle_chk_results_buf_size - Returns the required buffer size
3141 * for idle check results (in bytes).
3143 * @param p_hwfn - HW device data
3144 * @param dump_buf - idle check dump buffer.
3145 * @param num_dumped_dwords - number of dwords that were dumped.
3146 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3149 * @return error if the parsing fails, ok otherwise.
3151 enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn,
3153 u32 num_dumped_dwords,
3154 u32 *results_buf_size);
3156 * @brief qed_print_idle_chk_results - Prints idle check results
3158 * @param p_hwfn - HW device data
3159 * @param dump_buf - idle check dump buffer.
3160 * @param num_dumped_dwords - number of dwords that were dumped.
3161 * @param results_buf - buffer for printing the idle check results.
3162 * @param num_errors - OUT: number of errors found in idle check.
3163 * @param num_warnings - OUT: number of warnings found in idle check.
3165 * @return error if the parsing fails, ok otherwise.
3167 enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn,
3169 u32 num_dumped_dwords,
3175 * @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size
3176 * for MCP Trace results (in bytes).
3178 * @param p_hwfn - HW device data
3179 * @param dump_buf - MCP Trace dump buffer.
3180 * @param num_dumped_dwords - number of dwords that were dumped.
3181 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3184 * @return error if the parsing fails, ok otherwise.
3186 enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn,
3188 u32 num_dumped_dwords,
3189 u32 *results_buf_size);
3192 * @brief qed_print_mcp_trace_results - Prints MCP Trace results
3194 * @param p_hwfn - HW device data
3195 * @param dump_buf - mcp trace dump buffer, starting from the header.
3196 * @param num_dumped_dwords - number of dwords that were dumped.
3197 * @param results_buf - buffer for printing the mcp trace results.
3199 * @return error if the parsing fails, ok otherwise.
3201 enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn,
3203 u32 num_dumped_dwords,
3207 * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size
3208 * for reg_fifo results (in bytes).
3210 * @param p_hwfn - HW device data
3211 * @param dump_buf - reg fifo dump buffer.
3212 * @param num_dumped_dwords - number of dwords that were dumped.
3213 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3216 * @return error if the parsing fails, ok otherwise.
3218 enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3220 u32 num_dumped_dwords,
3221 u32 *results_buf_size);
3224 * @brief qed_print_reg_fifo_results - Prints reg fifo results
3226 * @param p_hwfn - HW device data
3227 * @param dump_buf - reg fifo dump buffer, starting from the header.
3228 * @param num_dumped_dwords - number of dwords that were dumped.
3229 * @param results_buf - buffer for printing the reg fifo results.
3231 * @return error if the parsing fails, ok otherwise.
3233 enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn,
3235 u32 num_dumped_dwords,
3239 * @brief qed_get_igu_fifo_results_buf_size - Returns the required buffer size
3240 * for igu_fifo results (in bytes).
3242 * @param p_hwfn - HW device data
3243 * @param dump_buf - IGU fifo dump buffer.
3244 * @param num_dumped_dwords - number of dwords that were dumped.
3245 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3248 * @return error if the parsing fails, ok otherwise.
3250 enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3252 u32 num_dumped_dwords,
3253 u32 *results_buf_size);
3256 * @brief qed_print_igu_fifo_results - Prints IGU fifo results
3258 * @param p_hwfn - HW device data
3259 * @param dump_buf - IGU fifo dump buffer, starting from the header.
3260 * @param num_dumped_dwords - number of dwords that were dumped.
3261 * @param results_buf - buffer for printing the IGU fifo results.
3263 * @return error if the parsing fails, ok otherwise.
3265 enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn,
3267 u32 num_dumped_dwords,
3271 * @brief qed_get_protection_override_results_buf_size - Returns the required
3272 * buffer size for protection override results (in bytes).
3274 * @param p_hwfn - HW device data
3275 * @param dump_buf - protection override dump buffer.
3276 * @param num_dumped_dwords - number of dwords that were dumped.
3277 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3280 * @return error if the parsing fails, ok otherwise.
3283 qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn,
3285 u32 num_dumped_dwords,
3286 u32 *results_buf_size);
3289 * @brief qed_print_protection_override_results - Prints protection override
3292 * @param p_hwfn - HW device data
3293 * @param dump_buf - protection override dump buffer, starting from the header.
3294 * @param num_dumped_dwords - number of dwords that were dumped.
3295 * @param results_buf - buffer for printing the reg fifo results.
3297 * @return error if the parsing fails, ok otherwise.
3299 enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn,
3301 u32 num_dumped_dwords,
3305 * @brief qed_get_fw_asserts_results_buf_size - Returns the required buffer size
3306 * for FW Asserts results (in bytes).
3308 * @param p_hwfn - HW device data
3309 * @param dump_buf - FW Asserts dump buffer.
3310 * @param num_dumped_dwords - number of dwords that were dumped.
3311 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3314 * @return error if the parsing fails, ok otherwise.
3316 enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn,
3318 u32 num_dumped_dwords,
3319 u32 *results_buf_size);
3322 * @brief qed_print_fw_asserts_results - Prints FW Asserts results
3324 * @param p_hwfn - HW device data
3325 * @param dump_buf - FW Asserts dump buffer, starting from the header.
3326 * @param num_dumped_dwords - number of dwords that were dumped.
3327 * @param results_buf - buffer for printing the FW Asserts results.
3329 * @return error if the parsing fails, ok otherwise.
3331 enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn,
3333 u32 num_dumped_dwords,
3337 * @brief qed_dbg_parse_attn - Parses and prints attention registers values in
3338 * the specified results struct.
3340 * @param p_hwfn - HW device data
3341 * @param results - Pointer to the attention read results
3343 * @return error if one of the following holds:
3344 * - the version wasn't set
3345 * Otherwise, returns ok.
3347 enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
3348 struct dbg_attn_block_result *results);
3350 /* Debug Bus blocks */
3351 static const u32 dbg_bus_blocks[] = {
3352 0x0000000f, /* grc, bb, 15 lines */
3353 0x0000000f, /* grc, k2, 15 lines */
3355 0x00000000, /* miscs, bb, 0 lines */
3356 0x00000000, /* miscs, k2, 0 lines */
3358 0x00000000, /* misc, bb, 0 lines */
3359 0x00000000, /* misc, k2, 0 lines */
3361 0x00000000, /* dbu, bb, 0 lines */
3362 0x00000000, /* dbu, k2, 0 lines */
3364 0x000f0127, /* pglue_b, bb, 39 lines */
3365 0x0036012a, /* pglue_b, k2, 42 lines */
3367 0x00000000, /* cnig, bb, 0 lines */
3368 0x00120102, /* cnig, k2, 2 lines */
3370 0x00000000, /* cpmu, bb, 0 lines */
3371 0x00000000, /* cpmu, k2, 0 lines */
3373 0x00000001, /* ncsi, bb, 1 lines */
3374 0x00000001, /* ncsi, k2, 1 lines */
3376 0x00000000, /* opte, bb, 0 lines */
3377 0x00000000, /* opte, k2, 0 lines */
3379 0x00600085, /* bmb, bb, 133 lines */
3380 0x00600085, /* bmb, k2, 133 lines */
3382 0x00000000, /* pcie, bb, 0 lines */
3383 0x00e50033, /* pcie, k2, 51 lines */
3385 0x00000000, /* mcp, bb, 0 lines */
3386 0x00000000, /* mcp, k2, 0 lines */
3388 0x01180009, /* mcp2, bb, 9 lines */
3389 0x01180009, /* mcp2, k2, 9 lines */
3391 0x01210104, /* pswhst, bb, 4 lines */
3392 0x01210104, /* pswhst, k2, 4 lines */
3394 0x01250103, /* pswhst2, bb, 3 lines */
3395 0x01250103, /* pswhst2, k2, 3 lines */
3397 0x00340101, /* pswrd, bb, 1 lines */
3398 0x00340101, /* pswrd, k2, 1 lines */
3400 0x01280119, /* pswrd2, bb, 25 lines */
3401 0x01280119, /* pswrd2, k2, 25 lines */
3403 0x01410109, /* pswwr, bb, 9 lines */
3404 0x01410109, /* pswwr, k2, 9 lines */
3406 0x00000000, /* pswwr2, bb, 0 lines */
3407 0x00000000, /* pswwr2, k2, 0 lines */
3409 0x001c0001, /* pswrq, bb, 1 lines */
3410 0x001c0001, /* pswrq, k2, 1 lines */
3412 0x014a0015, /* pswrq2, bb, 21 lines */
3413 0x014a0015, /* pswrq2, k2, 21 lines */
3415 0x00000000, /* pglcs, bb, 0 lines */
3416 0x00120006, /* pglcs, k2, 6 lines */
3418 0x00100001, /* dmae, bb, 1 lines */
3419 0x00100001, /* dmae, k2, 1 lines */
3421 0x015f0105, /* ptu, bb, 5 lines */
3422 0x015f0105, /* ptu, k2, 5 lines */
3424 0x01640120, /* tcm, bb, 32 lines */
3425 0x01640120, /* tcm, k2, 32 lines */
3427 0x01640120, /* mcm, bb, 32 lines */
3428 0x01640120, /* mcm, k2, 32 lines */
3430 0x01640120, /* ucm, bb, 32 lines */
3431 0x01640120, /* ucm, k2, 32 lines */
3433 0x01640120, /* xcm, bb, 32 lines */
3434 0x01640120, /* xcm, k2, 32 lines */
3436 0x01640120, /* ycm, bb, 32 lines */
3437 0x01640120, /* ycm, k2, 32 lines */
3439 0x01640120, /* pcm, bb, 32 lines */
3440 0x01640120, /* pcm, k2, 32 lines */
3442 0x01840062, /* qm, bb, 98 lines */
3443 0x01840062, /* qm, k2, 98 lines */
3445 0x01e60021, /* tm, bb, 33 lines */
3446 0x01e60021, /* tm, k2, 33 lines */
3448 0x02070107, /* dorq, bb, 7 lines */
3449 0x02070107, /* dorq, k2, 7 lines */
3451 0x00600185, /* brb, bb, 133 lines */
3452 0x00600185, /* brb, k2, 133 lines */
3454 0x020e0019, /* src, bb, 25 lines */
3455 0x020c001a, /* src, k2, 26 lines */
3457 0x02270104, /* prs, bb, 4 lines */
3458 0x02270104, /* prs, k2, 4 lines */
3460 0x022b0133, /* tsdm, bb, 51 lines */
3461 0x022b0133, /* tsdm, k2, 51 lines */
3463 0x022b0133, /* msdm, bb, 51 lines */
3464 0x022b0133, /* msdm, k2, 51 lines */
3466 0x022b0133, /* usdm, bb, 51 lines */
3467 0x022b0133, /* usdm, k2, 51 lines */
3469 0x022b0133, /* xsdm, bb, 51 lines */
3470 0x022b0133, /* xsdm, k2, 51 lines */
3472 0x022b0133, /* ysdm, bb, 51 lines */
3473 0x022b0133, /* ysdm, k2, 51 lines */
3475 0x022b0133, /* psdm, bb, 51 lines */
3476 0x022b0133, /* psdm, k2, 51 lines */
3478 0x025e010c, /* tsem, bb, 12 lines */
3479 0x025e010c, /* tsem, k2, 12 lines */
3481 0x025e010c, /* msem, bb, 12 lines */
3482 0x025e010c, /* msem, k2, 12 lines */
3484 0x025e010c, /* usem, bb, 12 lines */
3485 0x025e010c, /* usem, k2, 12 lines */
3487 0x025e010c, /* xsem, bb, 12 lines */
3488 0x025e010c, /* xsem, k2, 12 lines */
3490 0x025e010c, /* ysem, bb, 12 lines */
3491 0x025e010c, /* ysem, k2, 12 lines */
3493 0x025e010c, /* psem, bb, 12 lines */
3494 0x025e010c, /* psem, k2, 12 lines */
3496 0x026a000d, /* rss, bb, 13 lines */
3497 0x026a000d, /* rss, k2, 13 lines */
3499 0x02770106, /* tmld, bb, 6 lines */
3500 0x02770106, /* tmld, k2, 6 lines */
3502 0x027d0106, /* muld, bb, 6 lines */
3503 0x027d0106, /* muld, k2, 6 lines */
3505 0x02770005, /* yuld, bb, 5 lines */
3506 0x02770005, /* yuld, k2, 5 lines */
3508 0x02830107, /* xyld, bb, 7 lines */
3509 0x027d0107, /* xyld, k2, 7 lines */
3511 0x00000000, /* ptld, bb, 0 lines */
3512 0x00000000, /* ptld, k2, 0 lines */
3514 0x00000000, /* ypld, bb, 0 lines */
3515 0x00000000, /* ypld, k2, 0 lines */
3517 0x028a010e, /* prm, bb, 14 lines */
3518 0x02980110, /* prm, k2, 16 lines */
3520 0x02a8000d, /* pbf_pb1, bb, 13 lines */
3521 0x02a8000d, /* pbf_pb1, k2, 13 lines */
3523 0x02a8000d, /* pbf_pb2, bb, 13 lines */
3524 0x02a8000d, /* pbf_pb2, k2, 13 lines */
3526 0x02a8000d, /* rpb, bb, 13 lines */
3527 0x02a8000d, /* rpb, k2, 13 lines */
3529 0x00600185, /* btb, bb, 133 lines */
3530 0x00600185, /* btb, k2, 133 lines */
3532 0x02b50117, /* pbf, bb, 23 lines */
3533 0x02b50117, /* pbf, k2, 23 lines */
3535 0x02cc0006, /* rdif, bb, 6 lines */
3536 0x02cc0006, /* rdif, k2, 6 lines */
3538 0x02d20006, /* tdif, bb, 6 lines */
3539 0x02d20006, /* tdif, k2, 6 lines */
3541 0x02d80003, /* cdu, bb, 3 lines */
3542 0x02db000e, /* cdu, k2, 14 lines */
3544 0x02e9010d, /* ccfc, bb, 13 lines */
3545 0x02f60117, /* ccfc, k2, 23 lines */
3547 0x02e9010d, /* tcfc, bb, 13 lines */
3548 0x02f60117, /* tcfc, k2, 23 lines */
3550 0x030d0133, /* igu, bb, 51 lines */
3551 0x030d0133, /* igu, k2, 51 lines */
3553 0x03400106, /* cau, bb, 6 lines */
3554 0x03400106, /* cau, k2, 6 lines */
3556 0x00000000, /* rgfs, bb, 0 lines */
3557 0x00000000, /* rgfs, k2, 0 lines */
3559 0x00000000, /* rgsrc, bb, 0 lines */
3560 0x00000000, /* rgsrc, k2, 0 lines */
3562 0x00000000, /* tgfs, bb, 0 lines */
3563 0x00000000, /* tgfs, k2, 0 lines */
3565 0x00000000, /* tgsrc, bb, 0 lines */
3566 0x00000000, /* tgsrc, k2, 0 lines */
3568 0x00000000, /* umac, bb, 0 lines */
3569 0x00120006, /* umac, k2, 6 lines */
3571 0x00000000, /* xmac, bb, 0 lines */
3572 0x00000000, /* xmac, k2, 0 lines */
3574 0x00000000, /* dbg, bb, 0 lines */
3575 0x00000000, /* dbg, k2, 0 lines */
3577 0x0346012b, /* nig, bb, 43 lines */
3578 0x0346011d, /* nig, k2, 29 lines */
3580 0x00000000, /* wol, bb, 0 lines */
3581 0x001c0002, /* wol, k2, 2 lines */
3583 0x00000000, /* bmbn, bb, 0 lines */
3584 0x00210008, /* bmbn, k2, 8 lines */
3586 0x00000000, /* ipc, bb, 0 lines */
3587 0x00000000, /* ipc, k2, 0 lines */
3589 0x00000000, /* nwm, bb, 0 lines */
3590 0x0371000b, /* nwm, k2, 11 lines */
3592 0x00000000, /* nws, bb, 0 lines */
3593 0x037c0009, /* nws, k2, 9 lines */
3595 0x00000000, /* ms, bb, 0 lines */
3596 0x00120004, /* ms, k2, 4 lines */
3598 0x00000000, /* phy_pcie, bb, 0 lines */
3599 0x00e5001a, /* phy_pcie, k2, 26 lines */
3601 0x00000000, /* led, bb, 0 lines */
3602 0x00000000, /* led, k2, 0 lines */
3604 0x00000000, /* avs_wrap, bb, 0 lines */
3605 0x00000000, /* avs_wrap, k2, 0 lines */
3607 0x00000000, /* bar0_map, bb, 0 lines */
3608 0x00000000, /* bar0_map, k2, 0 lines */
3613 #define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL
3616 #define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL
3619 #define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL
3622 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL
3625 #define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL
3628 #define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL
3631 #define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL
3634 #define GTT_BAR0_MAP_REG_XSDM_RAM 0x016000UL
3637 #define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL
3640 #define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL
3643 * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
3645 * Returns the required host memory size in 4KB units.
3646 * Must be called before all QM init HSI functions.
3648 * @param pf_id - physical function ID
3649 * @param num_pf_cids - number of connections used by this PF
3650 * @param num_vf_cids - number of connections used by VFs of this PF
3651 * @param num_tids - number of tasks used by this PF
3652 * @param num_pf_pqs - number of PQs used by this PF
3653 * @param num_vf_pqs - number of PQs used by VFs of this PF
3655 * @return The required host memory size in 4KB units.
3657 u32 qed_qm_pf_mem_size(u8 pf_id,
3660 u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
3662 struct qed_qm_common_rt_init_params {
3663 u8 max_ports_per_engine;
3664 u8 max_phys_tcs_per_port;
3669 struct init_qm_port_params *port_params;
3672 int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
3673 struct qed_qm_common_rt_init_params *p_params);
3675 struct qed_qm_pf_rt_init_params {
3678 u8 max_phys_tcs_per_port;
3690 struct init_qm_pq_params *pq_params;
3691 struct init_qm_vport_params *vport_params;
3694 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
3695 struct qed_ptt *p_ptt,
3696 struct qed_qm_pf_rt_init_params *p_params);
3699 * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF
3702 * @param p_ptt - ptt window used for writing the registers
3703 * @param pf_id - PF ID
3704 * @param pf_wfq - WFQ weight. Must be non-zero.
3706 * @return 0 on success, -1 on error.
3708 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
3709 struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq);
3712 * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF
3715 * @param p_ptt - ptt window used for writing the registers
3716 * @param pf_id - PF ID
3717 * @param pf_rl - rate limit in Mb/sec units
3719 * @return 0 on success, -1 on error.
3721 int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
3722 struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl);
3725 * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT
3728 * @param p_ptt - ptt window used for writing the registers
3729 * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
3730 * with the VPORT for each TC. This array is filled by
3732 * @param vport_wfq - WFQ weight. Must be non-zero.
3734 * @return 0 on success, -1 on error.
3736 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
3737 struct qed_ptt *p_ptt,
3738 u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq);
3741 * @brief qed_init_vport_rl - Initializes the rate limit of the specified VPORT
3744 * @param p_ptt - ptt window used for writing the registers
3745 * @param vport_id - VPORT ID
3746 * @param vport_rl - rate limit in Mb/sec units
3748 * @return 0 on success, -1 on error.
3750 int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
3751 struct qed_ptt *p_ptt, u8 vport_id, u32 vport_rl);
3753 * @brief qed_send_qm_stop_cmd Sends a stop command to the QM
3757 * @param is_release_cmd - true for release, false for stop.
3758 * @param is_tx_pq - true for Tx PQs, false for Other PQs.
3759 * @param start_pq - first PQ ID to stop
3760 * @param num_pqs - Number of PQs to stop, starting from start_pq.
3762 * @return bool, true if successful, false if timeout occured while waiting for QM command done.
3764 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
3765 struct qed_ptt *p_ptt,
3766 bool is_release_cmd,
3767 bool is_tx_pq, u16 start_pq, u16 num_pqs);
3770 * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port
3772 * @param p_ptt - ptt window used for writing the registers.
3773 * @param dest_port - vxlan destination udp port.
3775 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
3776 struct qed_ptt *p_ptt, u16 dest_port);
3779 * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW
3781 * @param p_ptt - ptt window used for writing the registers.
3782 * @param vxlan_enable - vxlan enable flag.
3784 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
3785 struct qed_ptt *p_ptt, bool vxlan_enable);
3788 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3790 * @param p_ptt - ptt window used for writing the registers.
3791 * @param eth_gre_enable - eth GRE enable enable flag.
3792 * @param ip_gre_enable - IP GRE enable enable flag.
3794 void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
3795 struct qed_ptt *p_ptt,
3796 bool eth_gre_enable, bool ip_gre_enable);
3799 * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port
3801 * @param p_ptt - ptt window used for writing the registers.
3802 * @param dest_port - geneve destination udp port.
3804 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
3805 struct qed_ptt *p_ptt, u16 dest_port);
3808 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3810 * @param p_ptt - ptt window used for writing the registers.
3811 * @param eth_geneve_enable - eth GENEVE enable enable flag.
3812 * @param ip_geneve_enable - IP GENEVE enable enable flag.
3814 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
3815 struct qed_ptt *p_ptt,
3816 bool eth_geneve_enable, bool ip_geneve_enable);
3817 void qed_set_rfs_mode_disable(struct qed_hwfn *p_hwfn,
3818 struct qed_ptt *p_ptt, u16 pf_id);
3819 void qed_set_rfs_mode_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3820 u16 pf_id, bool tcp, bool udp,
3821 bool ipv4, bool ipv6);
3823 #define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
3824 #define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
3825 #define TSTORM_PORT_STAT_OFFSET(port_id) \
3826 (IRO[1].base + ((port_id) * IRO[1].m1))
3827 #define TSTORM_PORT_STAT_SIZE (IRO[1].size)
3828 #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
3829 (IRO[2].base + ((port_id) * IRO[2].m1))
3830 #define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
3831 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
3832 (IRO[3].base + ((vf_id) * IRO[3].m1))
3833 #define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
3834 #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
3835 (IRO[4].base + (pf_id) * IRO[4].m1)
3836 #define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
3837 #define USTORM_EQE_CONS_OFFSET(pf_id) \
3838 (IRO[5].base + ((pf_id) * IRO[5].m1))
3839 #define USTORM_EQE_CONS_SIZE (IRO[5].size)
3840 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
3841 (IRO[6].base + ((queue_zone_id) * IRO[6].m1))
3842 #define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size)
3843 #define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
3844 (IRO[7].base + ((queue_zone_id) * IRO[7].m1))
3845 #define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size)
3846 #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
3847 (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
3848 #define TSTORM_LL2_RX_PRODS_SIZE (IRO[14].size)
3849 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
3850 (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
3851 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[15].size)
3852 #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
3853 (IRO[16].base + ((core_rx_queue_id) * IRO[16].m1))
3854 #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[16].size)
3855 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
3856 (IRO[17].base + ((core_tx_stats_id) * IRO[17].m1))
3857 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[17]. size)
3858 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
3859 (IRO[18].base + ((stat_counter_id) * IRO[18].m1))
3860 #define MSTORM_QUEUE_STAT_SIZE (IRO[18].size)
3861 #define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
3862 (IRO[19].base + ((queue_id) * IRO[19].m1))
3863 #define MSTORM_ETH_PF_PRODS_SIZE (IRO[19].size)
3864 #define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
3865 (IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2))
3866 #define MSTORM_ETH_VF_PRODS_SIZE (IRO[20].size)
3867 #define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[21].base)
3868 #define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[21].size)
3869 #define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
3870 (IRO[22].base + ((pf_id) * IRO[22].m1))
3871 #define MSTORM_ETH_PF_STAT_SIZE (IRO[22].size)
3872 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
3873 (IRO[23].base + ((stat_counter_id) * IRO[23].m1))
3874 #define USTORM_QUEUE_STAT_SIZE (IRO[23].size)
3875 #define USTORM_ETH_PF_STAT_OFFSET(pf_id) \
3876 (IRO[24].base + ((pf_id) * IRO[24].m1))
3877 #define USTORM_ETH_PF_STAT_SIZE (IRO[24].size)
3878 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
3879 (IRO[25].base + ((stat_counter_id) * IRO[25].m1))
3880 #define PSTORM_QUEUE_STAT_SIZE (IRO[25].size)
3881 #define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
3882 (IRO[26].base + ((pf_id) * IRO[26].m1))
3883 #define PSTORM_ETH_PF_STAT_SIZE (IRO[26].size)
3884 #define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethtype) \
3885 (IRO[27].base + ((ethtype) * IRO[27].m1))
3886 #define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[27].size)
3887 #define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[28].base)
3888 #define TSTORM_ETH_PRS_INPUT_SIZE (IRO[28].size)
3889 #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
3890 (IRO[29].base + ((pf_id) * IRO[29].m1))
3891 #define ETH_RX_RATE_LIMIT_SIZE (IRO[29].size)
3892 #define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
3893 (IRO[30].base + ((queue_id) * IRO[30].m1))
3894 #define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[30].size)
3895 #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
3896 (IRO[34].base + ((cmdq_queue_id) * IRO[34].m1))
3897 #define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[34].size)
3898 #define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
3899 (IRO[35].base + ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2))
3900 #define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[35].size)
3901 #define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
3902 (IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2))
3903 #define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size)
3904 #define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
3905 (IRO[37].base + ((pf_id) * IRO[37].m1))
3906 #define TSTORM_ISCSI_RX_STATS_SIZE (IRO[37].size)
3907 #define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
3908 (IRO[38].base + ((pf_id) * IRO[38].m1))
3909 #define MSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size)
3910 #define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
3911 (IRO[39].base + ((pf_id) * IRO[39].m1))
3912 #define USTORM_ISCSI_RX_STATS_SIZE (IRO[39].size)
3913 #define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
3914 (IRO[40].base + ((pf_id) * IRO[40].m1))
3915 #define XSTORM_ISCSI_TX_STATS_SIZE (IRO[40].size)
3916 #define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
3917 (IRO[41].base + ((pf_id) * IRO[41].m1))
3918 #define YSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size)
3919 #define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
3920 (IRO[42].base + ((pf_id) * IRO[42].m1))
3921 #define PSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size)
3922 #define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
3923 (IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1))
3924 #define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[45].size)
3925 #define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
3926 (IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1))
3927 #define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size)
3928 #define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
3929 (IRO[43].base + ((pf_id) * IRO[43].m1))
3930 #define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
3931 (IRO[44].base + ((pf_id) * IRO[44].m1))
3933 static const struct iro iro_arr[49] = {
3934 {0x0, 0x0, 0x0, 0x0, 0x8},
3935 {0x4cb0, 0x80, 0x0, 0x0, 0x80},
3936 {0x6518, 0x20, 0x0, 0x0, 0x20},
3937 {0xb00, 0x8, 0x0, 0x0, 0x4},
3938 {0xa80, 0x8, 0x0, 0x0, 0x4},
3939 {0x0, 0x8, 0x0, 0x0, 0x2},
3940 {0x80, 0x8, 0x0, 0x0, 0x4},
3941 {0x84, 0x8, 0x0, 0x0, 0x2},
3942 {0x4c40, 0x0, 0x0, 0x0, 0x78},
3943 {0x3df0, 0x0, 0x0, 0x0, 0x78},
3944 {0x29b0, 0x0, 0x0, 0x0, 0x78},
3945 {0x4c38, 0x0, 0x0, 0x0, 0x78},
3946 {0x4990, 0x0, 0x0, 0x0, 0x78},
3947 {0x7f48, 0x0, 0x0, 0x0, 0x78},
3948 {0xa28, 0x8, 0x0, 0x0, 0x8},
3949 {0x61f8, 0x10, 0x0, 0x0, 0x10},
3950 {0xbd20, 0x30, 0x0, 0x0, 0x30},
3951 {0x95b8, 0x30, 0x0, 0x0, 0x30},
3952 {0x4b60, 0x80, 0x0, 0x0, 0x40},
3953 {0x1f8, 0x4, 0x0, 0x0, 0x4},
3954 {0x53a0, 0x80, 0x4, 0x0, 0x4},
3955 {0xc7c8, 0x0, 0x0, 0x0, 0x4},
3956 {0x4ba0, 0x80, 0x0, 0x0, 0x20},
3957 {0x8150, 0x40, 0x0, 0x0, 0x30},
3958 {0xec70, 0x60, 0x0, 0x0, 0x60},
3959 {0x2b48, 0x80, 0x0, 0x0, 0x38},
3960 {0xf1b0, 0x78, 0x0, 0x0, 0x78},
3961 {0x1f8, 0x4, 0x0, 0x0, 0x4},
3962 {0xaef8, 0x0, 0x0, 0x0, 0xf0},
3963 {0xafe8, 0x8, 0x0, 0x0, 0x8},
3964 {0x1f8, 0x8, 0x0, 0x0, 0x8},
3965 {0xac0, 0x8, 0x0, 0x0, 0x8},
3966 {0x2578, 0x8, 0x0, 0x0, 0x8},
3967 {0x24f8, 0x8, 0x0, 0x0, 0x8},
3968 {0x0, 0x8, 0x0, 0x0, 0x8},
3969 {0x200, 0x10, 0x8, 0x0, 0x8},
3970 {0xb78, 0x10, 0x8, 0x0, 0x2},
3971 {0xd9a8, 0x38, 0x0, 0x0, 0x24},
3972 {0x12988, 0x10, 0x0, 0x0, 0x8},
3973 {0x11fa0, 0x38, 0x0, 0x0, 0x18},
3974 {0xa580, 0x38, 0x0, 0x0, 0x10},
3975 {0x86f8, 0x30, 0x0, 0x0, 0x18},
3976 {0x101f8, 0x10, 0x0, 0x0, 0x10},
3977 {0xde28, 0x48, 0x0, 0x0, 0x38},
3978 {0x10660, 0x20, 0x0, 0x0, 0x20},
3979 {0x2b80, 0x80, 0x0, 0x0, 0x10},
3980 {0x5020, 0x10, 0x0, 0x0, 0x10},
3981 {0xc9b0, 0x30, 0x0, 0x0, 0x10},
3982 {0xeec0, 0x10, 0x0, 0x0, 0x10},
3985 /* Runtime array offsets */
3986 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
3987 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
3988 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
3989 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
3990 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
3991 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
3992 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
3993 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
3994 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
3995 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
3996 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
3997 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
3998 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
3999 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
4000 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
4001 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
4002 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
4003 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
4004 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18
4005 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19
4006 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20
4007 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21
4008 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22
4009 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23
4010 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24
4011 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
4012 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
4013 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
4014 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
4015 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497
4016 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
4017 #define CAU_REG_PI_MEMORY_RT_OFFSET 2233
4018 #define CAU_REG_PI_MEMORY_RT_SIZE 4416
4019 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649
4020 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650
4021 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651
4022 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
4023 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
4024 #define PRS_REG_SEARCH_TCP_RT_OFFSET 6654
4025 #define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655
4026 #define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656
4027 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657
4028 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658
4029 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659
4030 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660
4031 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661
4032 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662
4033 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663
4034 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664
4035 #define SRC_REG_FIRSTFREE_RT_OFFSET 6665
4036 #define SRC_REG_FIRSTFREE_RT_SIZE 2
4037 #define SRC_REG_LASTFREE_RT_OFFSET 6667
4038 #define SRC_REG_LASTFREE_RT_SIZE 2
4039 #define SRC_REG_COUNTFREE_RT_OFFSET 6669
4040 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670
4041 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671
4042 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672
4043 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673
4044 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674
4045 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675
4046 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6676
4047 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6677
4048 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6678
4049 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6679
4050 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6680
4051 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6681
4052 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6682
4053 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6683
4054 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6684
4055 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6685
4056 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6686
4057 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6687
4058 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6688
4059 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689
4060 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690
4061 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6691
4062 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6692
4063 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6693
4064 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6694
4065 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6695
4066 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6696
4067 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697
4068 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 6698
4069 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6699
4070 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6700
4071 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6701
4072 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6702
4073 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
4074 #define PGLUE_REG_B_VF_BASE_RT_OFFSET 28702
4075 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 28703
4076 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 28704
4077 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28705
4078 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28706
4079 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28707
4080 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28708
4081 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28709
4082 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28710
4083 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28711
4084 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28712
4085 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28713
4086 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28714
4087 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
4088 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29130
4089 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 608
4090 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 29738
4091 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 29739
4092 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 29740
4093 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29741
4094 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29742
4095 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29743
4096 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29744
4097 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29745
4098 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29746
4099 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29747
4100 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29748
4101 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29749
4102 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29750
4103 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29751
4104 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29752
4105 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29753
4106 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29754
4107 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29755
4108 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29756
4109 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29757
4110 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29758
4111 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29759
4112 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29760
4113 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29761
4114 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29762
4115 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29763
4116 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29764
4117 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29765
4118 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29766
4119 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29767
4120 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29768
4121 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29769
4122 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29770
4123 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29771
4124 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29772
4125 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29773
4126 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29774
4127 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29775
4128 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29776
4129 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29777
4130 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29778
4131 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29779
4132 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29780
4133 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29781
4134 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29782
4135 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29783
4136 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29784
4137 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29785
4138 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29786
4139 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29787
4140 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29788
4141 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29789
4142 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29790
4143 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29791
4144 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29792
4145 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29793
4146 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29794
4147 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29795
4148 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29796
4149 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29797
4150 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29798
4151 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29799
4152 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29800
4153 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29801
4154 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29802
4155 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29803
4156 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29804
4157 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29805
4158 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
4159 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29933
4160 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29934
4161 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29935
4162 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29936
4163 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29937
4164 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29938
4165 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29939
4166 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29940
4167 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29941
4168 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29942
4169 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29943
4170 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29944
4171 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29945
4172 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29946
4173 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29947
4174 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29948
4175 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29949
4176 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29950
4177 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29951
4178 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29952
4179 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29953
4180 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29954
4181 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29955
4182 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29956
4183 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29957
4184 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29958
4185 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29959
4186 #define QM_REG_PQTX2PF_0_RT_OFFSET 29960
4187 #define QM_REG_PQTX2PF_1_RT_OFFSET 29961
4188 #define QM_REG_PQTX2PF_2_RT_OFFSET 29962
4189 #define QM_REG_PQTX2PF_3_RT_OFFSET 29963
4190 #define QM_REG_PQTX2PF_4_RT_OFFSET 29964
4191 #define QM_REG_PQTX2PF_5_RT_OFFSET 29965
4192 #define QM_REG_PQTX2PF_6_RT_OFFSET 29966
4193 #define QM_REG_PQTX2PF_7_RT_OFFSET 29967
4194 #define QM_REG_PQTX2PF_8_RT_OFFSET 29968
4195 #define QM_REG_PQTX2PF_9_RT_OFFSET 29969
4196 #define QM_REG_PQTX2PF_10_RT_OFFSET 29970
4197 #define QM_REG_PQTX2PF_11_RT_OFFSET 29971
4198 #define QM_REG_PQTX2PF_12_RT_OFFSET 29972
4199 #define QM_REG_PQTX2PF_13_RT_OFFSET 29973
4200 #define QM_REG_PQTX2PF_14_RT_OFFSET 29974
4201 #define QM_REG_PQTX2PF_15_RT_OFFSET 29975
4202 #define QM_REG_PQTX2PF_16_RT_OFFSET 29976
4203 #define QM_REG_PQTX2PF_17_RT_OFFSET 29977
4204 #define QM_REG_PQTX2PF_18_RT_OFFSET 29978
4205 #define QM_REG_PQTX2PF_19_RT_OFFSET 29979
4206 #define QM_REG_PQTX2PF_20_RT_OFFSET 29980
4207 #define QM_REG_PQTX2PF_21_RT_OFFSET 29981
4208 #define QM_REG_PQTX2PF_22_RT_OFFSET 29982
4209 #define QM_REG_PQTX2PF_23_RT_OFFSET 29983
4210 #define QM_REG_PQTX2PF_24_RT_OFFSET 29984
4211 #define QM_REG_PQTX2PF_25_RT_OFFSET 29985
4212 #define QM_REG_PQTX2PF_26_RT_OFFSET 29986
4213 #define QM_REG_PQTX2PF_27_RT_OFFSET 29987
4214 #define QM_REG_PQTX2PF_28_RT_OFFSET 29988
4215 #define QM_REG_PQTX2PF_29_RT_OFFSET 29989
4216 #define QM_REG_PQTX2PF_30_RT_OFFSET 29990
4217 #define QM_REG_PQTX2PF_31_RT_OFFSET 29991
4218 #define QM_REG_PQTX2PF_32_RT_OFFSET 29992
4219 #define QM_REG_PQTX2PF_33_RT_OFFSET 29993
4220 #define QM_REG_PQTX2PF_34_RT_OFFSET 29994
4221 #define QM_REG_PQTX2PF_35_RT_OFFSET 29995
4222 #define QM_REG_PQTX2PF_36_RT_OFFSET 29996
4223 #define QM_REG_PQTX2PF_37_RT_OFFSET 29997
4224 #define QM_REG_PQTX2PF_38_RT_OFFSET 29998
4225 #define QM_REG_PQTX2PF_39_RT_OFFSET 29999
4226 #define QM_REG_PQTX2PF_40_RT_OFFSET 30000
4227 #define QM_REG_PQTX2PF_41_RT_OFFSET 30001
4228 #define QM_REG_PQTX2PF_42_RT_OFFSET 30002
4229 #define QM_REG_PQTX2PF_43_RT_OFFSET 30003
4230 #define QM_REG_PQTX2PF_44_RT_OFFSET 30004
4231 #define QM_REG_PQTX2PF_45_RT_OFFSET 30005
4232 #define QM_REG_PQTX2PF_46_RT_OFFSET 30006
4233 #define QM_REG_PQTX2PF_47_RT_OFFSET 30007
4234 #define QM_REG_PQTX2PF_48_RT_OFFSET 30008
4235 #define QM_REG_PQTX2PF_49_RT_OFFSET 30009
4236 #define QM_REG_PQTX2PF_50_RT_OFFSET 30010
4237 #define QM_REG_PQTX2PF_51_RT_OFFSET 30011
4238 #define QM_REG_PQTX2PF_52_RT_OFFSET 30012
4239 #define QM_REG_PQTX2PF_53_RT_OFFSET 30013
4240 #define QM_REG_PQTX2PF_54_RT_OFFSET 30014
4241 #define QM_REG_PQTX2PF_55_RT_OFFSET 30015
4242 #define QM_REG_PQTX2PF_56_RT_OFFSET 30016
4243 #define QM_REG_PQTX2PF_57_RT_OFFSET 30017
4244 #define QM_REG_PQTX2PF_58_RT_OFFSET 30018
4245 #define QM_REG_PQTX2PF_59_RT_OFFSET 30019
4246 #define QM_REG_PQTX2PF_60_RT_OFFSET 30020
4247 #define QM_REG_PQTX2PF_61_RT_OFFSET 30021
4248 #define QM_REG_PQTX2PF_62_RT_OFFSET 30022
4249 #define QM_REG_PQTX2PF_63_RT_OFFSET 30023
4250 #define QM_REG_PQOTHER2PF_0_RT_OFFSET 30024
4251 #define QM_REG_PQOTHER2PF_1_RT_OFFSET 30025
4252 #define QM_REG_PQOTHER2PF_2_RT_OFFSET 30026
4253 #define QM_REG_PQOTHER2PF_3_RT_OFFSET 30027
4254 #define QM_REG_PQOTHER2PF_4_RT_OFFSET 30028
4255 #define QM_REG_PQOTHER2PF_5_RT_OFFSET 30029
4256 #define QM_REG_PQOTHER2PF_6_RT_OFFSET 30030
4257 #define QM_REG_PQOTHER2PF_7_RT_OFFSET 30031
4258 #define QM_REG_PQOTHER2PF_8_RT_OFFSET 30032
4259 #define QM_REG_PQOTHER2PF_9_RT_OFFSET 30033
4260 #define QM_REG_PQOTHER2PF_10_RT_OFFSET 30034
4261 #define QM_REG_PQOTHER2PF_11_RT_OFFSET 30035
4262 #define QM_REG_PQOTHER2PF_12_RT_OFFSET 30036
4263 #define QM_REG_PQOTHER2PF_13_RT_OFFSET 30037
4264 #define QM_REG_PQOTHER2PF_14_RT_OFFSET 30038
4265 #define QM_REG_PQOTHER2PF_15_RT_OFFSET 30039
4266 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 30040
4267 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 30041
4268 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 30042
4269 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 30043
4270 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 30044
4271 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 30045
4272 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 30046
4273 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 30047
4274 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 30048
4275 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 30049
4276 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 30050
4277 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 30051
4278 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 30052
4279 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256
4280 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30308
4281 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
4282 #define QM_REG_RLGLBLCRD_RT_OFFSET 30564
4283 #define QM_REG_RLGLBLCRD_RT_SIZE 256
4284 #define QM_REG_RLGLBLENABLE_RT_OFFSET 30820
4285 #define QM_REG_RLPFPERIOD_RT_OFFSET 30821
4286 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30822
4287 #define QM_REG_RLPFINCVAL_RT_OFFSET 30823
4288 #define QM_REG_RLPFINCVAL_RT_SIZE 16
4289 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30839
4290 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
4291 #define QM_REG_RLPFCRD_RT_OFFSET 30855
4292 #define QM_REG_RLPFCRD_RT_SIZE 16
4293 #define QM_REG_RLPFENABLE_RT_OFFSET 30871
4294 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 30872
4295 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 30873
4296 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16
4297 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30889
4298 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
4299 #define QM_REG_WFQPFCRD_RT_OFFSET 30905
4300 #define QM_REG_WFQPFCRD_RT_SIZE 256
4301 #define QM_REG_WFQPFENABLE_RT_OFFSET 31161
4302 #define QM_REG_WFQVPENABLE_RT_OFFSET 31162
4303 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 31163
4304 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512
4305 #define QM_REG_TXPQMAP_RT_OFFSET 31675
4306 #define QM_REG_TXPQMAP_RT_SIZE 512
4307 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 32187
4308 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512
4309 #define QM_REG_WFQVPCRD_RT_OFFSET 32699
4310 #define QM_REG_WFQVPCRD_RT_SIZE 512
4311 #define QM_REG_WFQVPMAP_RT_OFFSET 33211
4312 #define QM_REG_WFQVPMAP_RT_SIZE 512
4313 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33723
4314 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 320
4315 #define QM_REG_VOQCRDLINE_RT_OFFSET 34043
4316 #define QM_REG_VOQCRDLINE_RT_SIZE 36
4317 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 34079
4318 #define QM_REG_VOQINITCRDLINE_RT_SIZE 36
4319 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34115
4320 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34116
4321 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34117
4322 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34118
4323 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34119
4324 #define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 34120
4325 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34121
4326 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34122
4327 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
4328 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 34126
4329 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
4330 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34130
4331 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
4332 #define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 34134
4333 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34135
4334 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
4335 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34167
4336 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
4337 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34183
4338 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
4339 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34199
4340 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
4341 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34215
4342 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
4343 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34231
4344 #define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 34232
4345 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34233
4346 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34234
4347 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34235
4348 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34236
4349 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34237
4350 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34238
4351 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34239
4352 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34240
4353 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34241
4354 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34242
4355 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34243
4356 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34244
4357 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34245
4358 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 34246
4359 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34247
4360 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34248
4361 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34249
4362 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34250
4363 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34251
4364 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34252
4365 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34253
4366 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34254
4367 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34255
4368 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34256
4369 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34257
4370 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34258
4371 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34259
4372 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34260
4373 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34261
4374 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34262
4375 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34263
4376 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34264
4377 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34265
4378 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34266
4379 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34267
4380 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34268
4381 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34269
4382 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34270
4383 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34271
4384 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34272
4385 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34273
4386 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34274
4387 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34275
4388 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34276
4389 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34277
4390 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34278
4391 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34279
4392 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34280
4393 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34281
4394 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34282
4395 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34283
4396 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34284
4397 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34285
4398 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34286
4399 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34287
4400 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34288
4401 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34289
4402 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34290
4403 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34291
4404 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34292
4405 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34293
4406 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34294
4407 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34295
4408 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34296
4409 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34297
4410 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34298
4411 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34299
4412 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34300
4413 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34301
4414 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34302
4415 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34303
4416 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34304
4417 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34305
4418 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34306
4419 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34307
4420 #define XCM_REG_CON_PHY_Q3_RT_OFFSET 34308
4422 #define RUNTIME_ARRAY_SIZE 34309
4424 /* The eth storm context for the Tstorm */
4425 struct tstorm_eth_conn_st_ctx {
4429 /* The eth storm context for the Pstorm */
4430 struct pstorm_eth_conn_st_ctx {
4434 /* The eth storm context for the Xstorm */
4435 struct xstorm_eth_conn_st_ctx {
4436 __le32 reserved[60];
4439 struct xstorm_eth_conn_ag_ctx {
4443 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
4444 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
4445 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
4446 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
4447 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
4448 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
4449 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
4450 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
4451 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
4452 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
4453 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
4454 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
4455 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
4456 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
4457 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
4458 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
4460 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
4461 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
4462 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
4463 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
4464 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
4465 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
4466 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
4467 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
4468 #define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1
4469 #define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
4470 #define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1
4471 #define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
4472 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
4473 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
4474 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
4475 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
4477 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4478 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
4479 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4480 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
4481 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4482 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
4483 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4484 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
4486 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
4487 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
4488 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
4489 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
4490 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
4491 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
4492 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
4493 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
4495 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
4496 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
4497 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
4498 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
4499 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
4500 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
4501 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
4502 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
4504 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
4505 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
4506 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
4507 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
4508 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
4509 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
4510 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
4511 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
4513 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
4514 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
4515 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
4516 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
4517 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
4518 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
4519 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
4520 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
4522 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
4523 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
4524 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
4525 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
4526 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
4527 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
4528 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
4529 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
4530 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
4531 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
4533 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4534 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
4535 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
4536 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
4537 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
4538 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
4539 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
4540 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
4541 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
4542 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
4543 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
4544 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
4545 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
4546 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
4547 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
4548 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
4550 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
4551 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
4552 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
4553 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
4554 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
4555 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
4556 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
4557 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
4558 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
4559 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
4560 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
4561 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
4562 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
4563 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
4564 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
4565 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
4567 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
4568 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
4569 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
4570 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
4571 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
4572 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
4573 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
4574 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
4575 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
4576 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
4577 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
4578 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
4579 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
4580 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
4581 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
4582 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
4584 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
4585 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
4586 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
4587 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
4588 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
4589 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
4590 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
4591 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
4592 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
4593 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
4594 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
4595 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
4596 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
4597 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
4598 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
4599 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
4601 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
4602 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
4603 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
4604 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
4605 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
4606 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
4607 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
4608 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
4609 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
4610 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
4611 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
4612 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
4613 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
4614 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
4615 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
4616 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
4618 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
4619 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
4620 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
4621 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
4622 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
4623 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
4624 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
4625 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
4626 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
4627 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
4628 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
4629 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
4630 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
4631 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
4632 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
4633 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
4635 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
4636 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
4637 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
4638 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
4639 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
4640 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
4641 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
4642 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
4643 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
4644 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
4645 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
4646 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
4647 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
4648 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
4652 __le16 edpm_num_bds;
4702 /* The eth storm context for the Ystorm */
4703 struct ystorm_eth_conn_st_ctx {
4707 struct ystorm_eth_conn_ag_ctx {
4711 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
4712 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
4713 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4714 #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
4715 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
4716 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
4717 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
4718 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
4719 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4720 #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
4722 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
4723 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
4724 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
4725 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
4726 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4727 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
4728 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4729 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
4730 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4731 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
4732 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4733 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
4734 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4735 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
4736 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4737 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
4738 u8 tx_q0_int_coallecing_timeset;
4741 __le32 terminate_spqe;
4743 __le16 tx_bd_cons_upd;
4751 struct tstorm_eth_conn_ag_ctx {
4755 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
4756 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
4757 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4758 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
4759 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
4760 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
4761 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
4762 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
4763 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
4764 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
4765 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
4766 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
4767 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4768 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
4770 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4771 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
4772 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4773 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
4774 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4775 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
4776 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
4777 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
4779 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
4780 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
4781 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
4782 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
4783 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
4784 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
4785 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
4786 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
4788 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
4789 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
4790 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
4791 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
4792 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
4793 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
4794 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
4795 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
4796 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4797 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
4798 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
4799 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
4801 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
4802 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
4803 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
4804 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
4805 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
4806 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
4807 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
4808 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
4809 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
4810 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
4811 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
4812 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
4813 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
4814 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
4815 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4816 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
4818 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4819 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
4820 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4821 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
4822 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4823 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
4824 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4825 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
4826 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
4827 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
4828 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
4829 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
4830 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
4831 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
4832 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
4833 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
4855 struct ustorm_eth_conn_ag_ctx {
4859 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
4860 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
4861 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4862 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
4863 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
4864 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
4865 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
4866 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
4867 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4868 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
4870 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4871 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
4872 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
4873 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
4874 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
4875 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
4876 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
4877 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
4879 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
4880 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
4881 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
4882 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
4883 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4884 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
4885 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
4886 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
4887 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
4888 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
4889 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
4890 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
4891 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
4892 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
4893 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4894 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
4896 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4897 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
4898 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4899 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
4900 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4901 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
4902 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4903 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
4904 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
4905 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
4906 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
4907 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
4908 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
4909 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
4910 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
4911 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
4919 __le32 tx_int_coallecing_timeset;
4920 __le16 tx_drv_bd_cons;
4921 __le16 rx_drv_cqe_cons;
4924 /* The eth storm context for the Ustorm */
4925 struct ustorm_eth_conn_st_ctx {
4926 __le32 reserved[40];
4929 /* The eth storm context for the Mstorm */
4930 struct mstorm_eth_conn_st_ctx {
4934 /* eth connection context */
4935 struct eth_conn_context {
4936 struct tstorm_eth_conn_st_ctx tstorm_st_context;
4937 struct regpair tstorm_st_padding[2];
4938 struct pstorm_eth_conn_st_ctx pstorm_st_context;
4939 struct xstorm_eth_conn_st_ctx xstorm_st_context;
4940 struct xstorm_eth_conn_ag_ctx xstorm_ag_context;
4941 struct ystorm_eth_conn_st_ctx ystorm_st_context;
4942 struct ystorm_eth_conn_ag_ctx ystorm_ag_context;
4943 struct tstorm_eth_conn_ag_ctx tstorm_ag_context;
4944 struct ustorm_eth_conn_ag_ctx ustorm_ag_context;
4945 struct ustorm_eth_conn_st_ctx ustorm_st_context;
4946 struct mstorm_eth_conn_st_ctx mstorm_st_context;
4949 enum eth_error_code {
4951 ETH_FILTERS_MAC_ADD_FAIL_FULL,
4952 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
4953 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
4954 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
4955 ETH_FILTERS_MAC_DEL_FAIL_NOF,
4956 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
4957 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
4958 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
4959 ETH_FILTERS_VLAN_ADD_FAIL_FULL,
4960 ETH_FILTERS_VLAN_ADD_FAIL_DUP,
4961 ETH_FILTERS_VLAN_DEL_FAIL_NOF,
4962 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
4963 ETH_FILTERS_PAIR_ADD_FAIL_DUP,
4964 ETH_FILTERS_PAIR_ADD_FAIL_FULL,
4965 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
4966 ETH_FILTERS_PAIR_DEL_FAIL_NOF,
4967 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
4968 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
4969 ETH_FILTERS_VNI_ADD_FAIL_FULL,
4970 ETH_FILTERS_VNI_ADD_FAIL_DUP,
4971 ETH_FILTERS_GFT_UPDATE_FAIL,
4975 enum eth_event_opcode {
4977 ETH_EVENT_VPORT_START,
4978 ETH_EVENT_VPORT_UPDATE,
4979 ETH_EVENT_VPORT_STOP,
4980 ETH_EVENT_TX_QUEUE_START,
4981 ETH_EVENT_TX_QUEUE_STOP,
4982 ETH_EVENT_RX_QUEUE_START,
4983 ETH_EVENT_RX_QUEUE_UPDATE,
4984 ETH_EVENT_RX_QUEUE_STOP,
4985 ETH_EVENT_FILTERS_UPDATE,
4987 ETH_EVENT_RESERVED2,
4988 ETH_EVENT_RESERVED3,
4989 ETH_EVENT_RX_ADD_UDP_FILTER,
4990 ETH_EVENT_RX_DELETE_UDP_FILTER,
4991 ETH_EVENT_RESERVED4,
4992 ETH_EVENT_RESERVED5,
4993 MAX_ETH_EVENT_OPCODE
4996 /* Classify rule types in E2/E3 */
4997 enum eth_filter_action {
4998 ETH_FILTER_ACTION_UNUSED,
4999 ETH_FILTER_ACTION_REMOVE,
5000 ETH_FILTER_ACTION_ADD,
5001 ETH_FILTER_ACTION_REMOVE_ALL,
5002 MAX_ETH_FILTER_ACTION
5005 /* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */
5006 struct eth_filter_cmd {
5018 /* $$KEEP_ENDIANNESS$$ */
5019 struct eth_filter_cmd_header {
5027 /* Ethernet filter types: mac/vlan/pair */
5028 enum eth_filter_type {
5029 ETH_FILTER_TYPE_UNUSED,
5030 ETH_FILTER_TYPE_MAC,
5031 ETH_FILTER_TYPE_VLAN,
5032 ETH_FILTER_TYPE_PAIR,
5033 ETH_FILTER_TYPE_INNER_MAC,
5034 ETH_FILTER_TYPE_INNER_VLAN,
5035 ETH_FILTER_TYPE_INNER_PAIR,
5036 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
5037 ETH_FILTER_TYPE_MAC_VNI_PAIR,
5038 ETH_FILTER_TYPE_VNI,
5042 enum eth_ipv4_frag_type {
5044 ETH_IPV4_FIRST_FRAG,
5045 ETH_IPV4_NON_FIRST_FRAG,
5046 MAX_ETH_IPV4_FRAG_TYPE
5055 enum eth_ramrod_cmd_id {
5057 ETH_RAMROD_VPORT_START,
5058 ETH_RAMROD_VPORT_UPDATE,
5059 ETH_RAMROD_VPORT_STOP,
5060 ETH_RAMROD_RX_QUEUE_START,
5061 ETH_RAMROD_RX_QUEUE_STOP,
5062 ETH_RAMROD_TX_QUEUE_START,
5063 ETH_RAMROD_TX_QUEUE_STOP,
5064 ETH_RAMROD_FILTERS_UPDATE,
5065 ETH_RAMROD_RX_QUEUE_UPDATE,
5066 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
5067 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
5068 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
5069 ETH_RAMROD_RX_ADD_UDP_FILTER,
5070 ETH_RAMROD_RX_DELETE_UDP_FILTER,
5071 ETH_RAMROD_RX_CREATE_GFT_ACTION,
5072 ETH_RAMROD_GFT_UPDATE_FILTER,
5073 MAX_ETH_RAMROD_CMD_ID
5076 /* return code from eth sp ramrods */
5077 struct eth_return_code {
5079 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F
5080 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
5081 #define ETH_RETURN_CODE_RESERVED_MASK 0x3
5082 #define ETH_RETURN_CODE_RESERVED_SHIFT 5
5083 #define ETH_RETURN_CODE_RX_TX_MASK 0x1
5084 #define ETH_RETURN_CODE_RX_TX_SHIFT 7
5087 /* What to do in case an error occurs */
5090 ETH_TX_ERR_ASSERT_MALICIOUS,
5094 /* Array of the different error type behaviors */
5095 struct eth_tx_err_vals {
5097 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
5098 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
5099 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
5100 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
5101 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
5102 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
5103 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
5104 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
5105 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
5106 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
5107 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
5108 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
5109 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
5110 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
5111 #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF
5112 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7
5115 /* vport rss configuration data */
5116 struct eth_vport_rss_config {
5117 __le16 capabilities;
5118 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
5119 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
5120 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
5121 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
5122 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
5123 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
5124 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
5125 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
5126 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
5127 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
5128 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
5129 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
5130 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
5131 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
5132 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
5133 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
5137 u8 update_rss_ind_table;
5138 u8 update_rss_capabilities;
5140 __le32 reserved2[2];
5141 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
5143 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
5144 __le32 reserved3[2];
5147 /* eth vport RSS mode */
5148 enum eth_vport_rss_mode {
5149 ETH_VPORT_RSS_MODE_DISABLED,
5150 ETH_VPORT_RSS_MODE_REGULAR,
5151 MAX_ETH_VPORT_RSS_MODE
5154 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
5155 struct eth_vport_rx_mode {
5157 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
5158 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
5159 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
5160 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
5161 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
5162 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
5163 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
5164 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
5165 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
5166 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
5167 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
5168 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
5169 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF
5170 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6
5171 __le16 reserved2[3];
5174 /* Command for setting tpa parameters */
5175 struct eth_vport_tpa_param {
5178 u8 tpa_ipv4_tunn_en_flg;
5179 u8 tpa_ipv6_tunn_en_flg;
5180 u8 tpa_pkt_split_flg;
5181 u8 tpa_hdr_data_split_flg;
5182 u8 tpa_gro_consistent_flg;
5184 u8 tpa_max_aggs_num;
5186 __le16 tpa_max_size;
5187 __le16 tpa_min_size_to_start;
5189 __le16 tpa_min_size_to_cont;
5194 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
5195 struct eth_vport_tx_mode {
5197 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
5198 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
5199 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
5200 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
5201 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
5202 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
5203 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
5204 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
5205 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
5206 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
5207 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
5208 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
5209 __le16 reserved2[3];
5212 enum gft_filter_update_action {
5215 MAX_GFT_FILTER_UPDATE_ACTION
5218 enum gft_logic_filter_type {
5221 MAX_GFT_LOGIC_FILTER_TYPE
5224 struct rx_add_openflow_filter_data {
5240 u8 tenant_id_exists;
5241 __le32 ipv4_dst_addr;
5242 __le32 ipv4_src_addr;
5247 struct rx_create_gft_action_data {
5252 struct rx_create_openflow_action_data {
5257 /* Ramrod data for rx queue start ramrod */
5258 struct rx_queue_start_ramrod_data {
5260 __le16 num_of_pbl_pages;
5261 __le16 bd_max_bytes;
5265 u8 default_rss_queue_flg;
5266 u8 complete_cqe_flg;
5267 u8 complete_event_flg;
5268 u8 stats_counter_id;
5270 u8 pxp_tph_valid_bd;
5271 u8 pxp_tph_valid_pkt;
5274 __le16 pxp_st_index;
5280 u8 vf_rx_prod_index;
5281 u8 vf_rx_prod_use_zone_a;
5284 struct regpair cqe_pbl_addr;
5285 struct regpair bd_base;
5286 struct regpair reserved2;
5289 /* Ramrod data for rx queue start ramrod */
5290 struct rx_queue_stop_ramrod_data {
5292 u8 complete_cqe_flg;
5293 u8 complete_event_flg;
5298 /* Ramrod data for rx queue update ramrod */
5299 struct rx_queue_update_ramrod_data {
5301 u8 complete_cqe_flg;
5302 u8 complete_event_flg;
5310 struct regpair reserved6;
5313 /* Ramrod data for rx Add UDP Filter */
5314 struct rx_udp_filter_data {
5318 u8 tenant_id_exists;
5320 __le32 ip_dst_addr[4];
5321 __le32 ip_src_addr[4];
5322 __le16 udp_dst_port;
5323 __le16 udp_src_port;
5327 struct rx_update_gft_filter_data {
5328 struct regpair pkt_hdr_addr;
5329 __le16 pkt_hdr_length;
5330 __le16 rx_qid_or_action_icid;
5337 /* Ramrod data for rx queue start ramrod */
5338 struct tx_queue_start_ramrod_data {
5343 u8 stats_counter_id;
5346 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
5347 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
5348 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
5349 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
5350 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
5351 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
5352 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
5353 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3
5354 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
5355 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4
5356 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
5357 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5
5358 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3
5359 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6
5361 u8 pxp_tph_valid_bd;
5362 u8 pxp_tph_valid_pkt;
5363 __le16 pxp_st_index;
5364 __le16 comp_agg_size;
5365 __le16 queue_zone_id;
5369 __le16 same_as_last_id;
5371 struct regpair pbl_base_addr;
5372 struct regpair bd_cons_address;
5375 /* Ramrod data for tx queue stop ramrod */
5376 struct tx_queue_stop_ramrod_data {
5380 /* Ramrod data for vport update ramrod */
5381 struct vport_filter_update_ramrod_data {
5382 struct eth_filter_cmd_header filter_cmd_hdr;
5383 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
5386 /* Ramrod data for vport start ramrod */
5387 struct vport_start_ramrod_data {
5392 u8 inner_vlan_removal_en;
5393 struct eth_vport_rx_mode rx_mode;
5394 struct eth_vport_tx_mode tx_mode;
5395 struct eth_vport_tpa_param tpa_param;
5396 __le16 default_vlan;
5398 u8 anti_spoofing_en;
5403 u8 silent_vlan_removal_en;
5405 struct eth_tx_err_vals tx_err_behav;
5407 u8 zero_placement_offset;
5408 u8 ctl_frame_mac_check_en;
5409 u8 ctl_frame_ethtype_check_en;
5413 /* Ramrod data for vport stop ramrod */
5414 struct vport_stop_ramrod_data {
5419 /* Ramrod data for vport update ramrod */
5420 struct vport_update_ramrod_data_cmn {
5422 u8 update_rx_active_flg;
5424 u8 update_tx_active_flg;
5426 u8 update_rx_mode_flg;
5427 u8 update_tx_mode_flg;
5428 u8 update_approx_mcast_flg;
5431 u8 update_inner_vlan_removal_en_flg;
5433 u8 inner_vlan_removal_en;
5434 u8 update_tpa_param_flg;
5435 u8 update_tpa_en_flg;
5436 u8 update_tx_switching_en_flg;
5439 u8 update_anti_spoofing_en_flg;
5441 u8 anti_spoofing_en;
5442 u8 update_handle_ptp_pkts;
5445 u8 update_default_vlan_en_flg;
5449 u8 update_default_vlan_flg;
5451 __le16 default_vlan;
5452 u8 update_accept_any_vlan_flg;
5455 u8 silent_vlan_removal_en;
5459 u8 update_ctl_frame_checks_en_flg;
5460 u8 ctl_frame_mac_check_en;
5461 u8 ctl_frame_ethtype_check_en;
5465 struct vport_update_ramrod_mcast {
5466 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
5469 /* Ramrod data for vport update ramrod */
5470 struct vport_update_ramrod_data {
5471 struct vport_update_ramrod_data_cmn common;
5473 struct eth_vport_rx_mode rx_mode;
5474 struct eth_vport_tx_mode tx_mode;
5475 struct eth_vport_tpa_param tpa_param;
5476 struct vport_update_ramrod_mcast approx_mcast;
5477 struct eth_vport_rss_config rss_config;
5480 struct xstorm_eth_conn_agctxdq_ext_ldpart {
5484 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
5485 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
5486 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
5487 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
5488 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
5489 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
5490 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
5491 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
5492 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
5493 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
5494 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
5495 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
5496 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
5497 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
5498 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
5499 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
5501 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
5502 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
5503 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
5504 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
5505 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
5506 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
5507 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
5508 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
5509 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
5510 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
5511 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1
5512 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
5513 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
5514 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
5515 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
5516 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
5518 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
5519 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
5520 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
5521 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
5522 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
5523 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
5524 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
5525 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
5527 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
5528 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
5529 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
5530 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
5531 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
5532 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
5533 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
5534 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
5536 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
5537 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
5538 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
5539 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
5540 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
5541 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
5542 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
5543 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
5545 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
5546 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
5547 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
5548 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
5549 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
5550 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
5551 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
5552 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
5554 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
5555 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
5556 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
5557 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
5558 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
5559 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
5560 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
5561 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
5563 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
5564 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
5565 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
5566 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
5567 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
5568 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
5569 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
5570 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
5571 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
5572 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
5574 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
5575 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
5576 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
5577 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
5578 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
5579 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
5580 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
5581 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
5582 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
5583 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
5584 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
5585 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
5586 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
5587 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
5588 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
5589 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
5591 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
5592 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
5593 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
5594 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
5595 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
5596 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
5597 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
5598 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
5599 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
5600 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
5601 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
5602 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
5603 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
5604 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
5605 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
5606 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
5608 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
5609 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
5610 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
5611 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
5612 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
5613 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
5614 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
5615 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
5616 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
5617 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
5618 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
5619 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
5620 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
5621 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
5622 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
5623 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
5625 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
5626 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
5627 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
5628 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
5629 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
5630 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
5631 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
5632 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
5633 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
5634 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
5635 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
5636 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
5637 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
5638 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
5639 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
5640 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
5642 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
5643 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
5644 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
5645 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
5646 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
5647 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
5648 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
5649 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
5650 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
5651 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
5652 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
5653 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
5654 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
5655 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
5656 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
5657 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
5659 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
5660 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
5661 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
5662 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
5663 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
5664 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
5665 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
5666 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
5667 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
5668 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
5669 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
5670 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
5671 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
5672 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
5673 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
5674 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
5676 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
5677 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
5678 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
5679 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
5680 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
5681 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
5682 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
5683 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
5684 #define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
5685 #define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
5686 #define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
5687 #define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
5688 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
5689 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
5693 __le16 edpm_num_bds;
5709 struct mstorm_eth_conn_ag_ctx {
5713 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5714 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5715 #define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
5716 #define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
5717 #define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
5718 #define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
5719 #define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
5720 #define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
5721 #define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
5722 #define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
5724 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
5725 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
5726 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
5727 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
5728 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
5729 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
5730 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
5731 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
5732 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
5733 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
5734 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
5735 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
5736 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
5737 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
5738 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
5739 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
5746 struct xstorm_eth_hw_conn_ag_ctx {
5750 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5751 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5752 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
5753 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
5754 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
5755 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
5756 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
5757 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
5758 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
5759 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
5760 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
5761 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
5762 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
5763 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
5764 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
5765 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
5767 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
5768 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
5769 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
5770 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
5771 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
5772 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
5773 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
5774 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
5775 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1
5776 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4
5777 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1
5778 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5
5779 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
5780 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
5781 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
5782 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
5784 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
5785 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
5786 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
5787 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
5788 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
5789 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
5790 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
5791 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
5793 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
5794 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
5795 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
5796 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
5797 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
5798 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
5799 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
5800 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
5802 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
5803 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
5804 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
5805 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
5806 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
5807 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
5808 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
5809 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
5811 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
5812 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
5813 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
5814 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
5815 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
5816 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
5817 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
5818 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
5820 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
5821 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
5822 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
5823 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
5824 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
5825 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
5826 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
5827 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
5829 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
5830 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
5831 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
5832 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
5833 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
5834 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
5835 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
5836 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
5837 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
5838 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
5840 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
5841 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
5842 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
5843 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
5844 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
5845 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
5846 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
5847 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
5848 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
5849 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
5850 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
5851 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
5852 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
5853 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
5854 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
5855 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
5857 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
5858 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
5859 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
5860 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
5861 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
5862 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
5863 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
5864 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
5865 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
5866 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
5867 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
5868 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
5869 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
5870 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
5871 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
5872 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
5874 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
5875 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
5876 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
5877 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
5878 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
5879 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
5880 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
5881 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
5882 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
5883 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
5884 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
5885 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
5886 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
5887 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
5888 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
5889 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
5891 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
5892 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
5893 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
5894 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
5895 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
5896 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
5897 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
5898 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
5899 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
5900 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
5901 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
5902 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
5903 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
5904 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
5905 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
5906 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
5908 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
5909 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
5910 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
5911 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
5912 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
5913 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
5914 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
5915 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
5916 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
5917 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
5918 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
5919 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
5920 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
5921 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
5922 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
5923 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
5925 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
5926 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
5927 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
5928 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
5929 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
5930 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
5931 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
5932 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
5933 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
5934 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
5935 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
5936 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
5937 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
5938 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
5939 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
5940 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
5942 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
5943 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
5944 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
5945 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
5946 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
5947 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
5948 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
5949 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
5950 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
5951 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
5952 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
5953 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
5954 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
5955 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
5959 __le16 edpm_num_bds;
5966 struct gft_cam_line {
5968 #define GFT_CAM_LINE_VALID_MASK 0x1
5969 #define GFT_CAM_LINE_VALID_SHIFT 0
5970 #define GFT_CAM_LINE_DATA_MASK 0x3FFF
5971 #define GFT_CAM_LINE_DATA_SHIFT 1
5972 #define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF
5973 #define GFT_CAM_LINE_MASK_BITS_SHIFT 15
5974 #define GFT_CAM_LINE_RESERVED1_MASK 0x7
5975 #define GFT_CAM_LINE_RESERVED1_SHIFT 29
5978 struct gft_cam_line_mapped {
5980 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
5981 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0
5982 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1
5983 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1
5984 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1
5985 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2
5986 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF
5987 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3
5988 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF
5989 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7
5990 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF
5991 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11
5992 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1
5993 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15
5994 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1
5995 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16
5996 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF
5997 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17
5998 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF
5999 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21
6000 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF
6001 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25
6002 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7
6003 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29
6006 union gft_cam_line_union {
6007 struct gft_cam_line cam_line;
6008 struct gft_cam_line_mapped cam_line_mapped;
6011 enum gft_profile_ip_version {
6012 GFT_PROFILE_IPV4 = 0,
6013 GFT_PROFILE_IPV6 = 1,
6014 MAX_GFT_PROFILE_IP_VERSION
6017 struct gft_profile_key {
6019 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
6020 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0
6021 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
6022 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1
6023 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF
6024 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2
6025 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF
6026 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6
6027 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF
6028 #define GFT_PROFILE_KEY_PF_ID_SHIFT 10
6029 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
6030 #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14
6033 enum gft_profile_tunnel_type {
6034 GFT_PROFILE_NO_TUNNEL = 0,
6035 GFT_PROFILE_VXLAN_TUNNEL = 1,
6036 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2,
6037 GFT_PROFILE_GRE_IP_TUNNEL = 3,
6038 GFT_PROFILE_GENEVE_MAC_TUNNEL = 4,
6039 GFT_PROFILE_GENEVE_IP_TUNNEL = 5,
6040 MAX_GFT_PROFILE_TUNNEL_TYPE
6043 enum gft_profile_upper_protocol_type {
6044 GFT_PROFILE_ROCE_PROTOCOL = 0,
6045 GFT_PROFILE_RROCE_PROTOCOL = 1,
6046 GFT_PROFILE_FCOE_PROTOCOL = 2,
6047 GFT_PROFILE_ICMP_PROTOCOL = 3,
6048 GFT_PROFILE_ARP_PROTOCOL = 4,
6049 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
6050 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
6051 GFT_PROFILE_TCP_PROTOCOL = 7,
6052 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
6053 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
6054 GFT_PROFILE_UDP_PROTOCOL = 10,
6055 GFT_PROFILE_USER_IP_1_INNER = 11,
6056 GFT_PROFILE_USER_IP_2_OUTER = 12,
6057 GFT_PROFILE_USER_ETH_1_INNER = 13,
6058 GFT_PROFILE_USER_ETH_2_OUTER = 14,
6059 GFT_PROFILE_RAW = 15,
6060 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
6063 struct gft_ram_line {
6065 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
6066 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0
6067 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1
6068 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2
6069 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1
6070 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3
6071 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1
6072 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4
6073 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1
6074 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5
6075 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1
6076 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6
6077 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1
6078 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7
6079 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1
6080 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8
6081 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1
6082 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9
6083 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1
6084 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10
6085 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1
6086 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11
6087 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1
6088 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12
6089 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1
6090 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13
6091 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1
6092 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14
6093 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1
6094 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15
6095 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1
6096 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16
6097 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1
6098 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17
6099 #define GFT_RAM_LINE_TTL_MASK 0x1
6100 #define GFT_RAM_LINE_TTL_SHIFT 18
6101 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1
6102 #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19
6103 #define GFT_RAM_LINE_RESERVED0_MASK 0x1
6104 #define GFT_RAM_LINE_RESERVED0_SHIFT 20
6105 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1
6106 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21
6107 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1
6108 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22
6109 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1
6110 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23
6111 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1
6112 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24
6113 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1
6114 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25
6115 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1
6116 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26
6117 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1
6118 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27
6119 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1
6120 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28
6121 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1
6122 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29
6123 #define GFT_RAM_LINE_DST_PORT_MASK 0x1
6124 #define GFT_RAM_LINE_DST_PORT_SHIFT 30
6125 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1
6126 #define GFT_RAM_LINE_SRC_PORT_SHIFT 31
6128 #define GFT_RAM_LINE_DSCP_MASK 0x1
6129 #define GFT_RAM_LINE_DSCP_SHIFT 0
6130 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1
6131 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1
6132 #define GFT_RAM_LINE_DST_IP_MASK 0x1
6133 #define GFT_RAM_LINE_DST_IP_SHIFT 2
6134 #define GFT_RAM_LINE_SRC_IP_MASK 0x1
6135 #define GFT_RAM_LINE_SRC_IP_SHIFT 3
6136 #define GFT_RAM_LINE_PRIORITY_MASK 0x1
6137 #define GFT_RAM_LINE_PRIORITY_SHIFT 4
6138 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1
6139 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5
6140 #define GFT_RAM_LINE_VLAN_MASK 0x1
6141 #define GFT_RAM_LINE_VLAN_SHIFT 6
6142 #define GFT_RAM_LINE_DST_MAC_MASK 0x1
6143 #define GFT_RAM_LINE_DST_MAC_SHIFT 7
6144 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1
6145 #define GFT_RAM_LINE_SRC_MAC_SHIFT 8
6146 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1
6147 #define GFT_RAM_LINE_TENANT_ID_SHIFT 9
6148 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF
6149 #define GFT_RAM_LINE_RESERVED1_SHIFT 10
6152 enum gft_vlan_select {
6153 INNER_PROVIDER_VLAN = 0,
6155 OUTER_PROVIDER_VLAN = 2,
6160 struct mstorm_rdma_task_st_ctx {
6161 struct regpair temp[4];
6164 struct rdma_close_func_ramrod_data {
6165 u8 cnq_start_offset;
6172 struct rdma_cnq_params {
6177 struct regpair pbl_base_addr;
6178 __le16 queue_zone_num;
6182 struct rdma_create_cq_ramrod_data {
6183 struct regpair cq_handle;
6184 struct regpair pbl_addr;
6186 __le16 pbl_num_pages;
6188 u8 is_two_level_pbl;
6190 u8 pbl_log_page_size;
6196 struct rdma_deregister_tid_ramrod_data {
6201 struct rdma_destroy_cq_output_params {
6207 struct rdma_destroy_cq_ramrod_data {
6208 struct regpair output_params_addr;
6211 enum rdma_event_opcode {
6213 RDMA_EVENT_FUNC_INIT,
6214 RDMA_EVENT_FUNC_CLOSE,
6215 RDMA_EVENT_REGISTER_MR,
6216 RDMA_EVENT_DEREGISTER_MR,
6217 RDMA_EVENT_CREATE_CQ,
6218 RDMA_EVENT_RESIZE_CQ,
6219 RDMA_EVENT_DESTROY_CQ,
6220 RDMA_EVENT_CREATE_SRQ,
6221 RDMA_EVENT_MODIFY_SRQ,
6222 RDMA_EVENT_DESTROY_SRQ,
6223 MAX_RDMA_EVENT_OPCODE
6226 enum rdma_fw_return_code {
6228 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
6229 RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
6230 RDMA_RETURN_RESIZE_CQ_ERR,
6231 RDMA_RETURN_NIG_DRAIN_REQ,
6232 MAX_RDMA_FW_RETURN_CODE
6235 struct rdma_init_func_hdr {
6236 u8 cnq_start_offset;
6244 struct rdma_init_func_ramrod_data {
6245 struct rdma_init_func_hdr params_header;
6246 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
6249 enum rdma_ramrod_cmd_id {
6251 RDMA_RAMROD_FUNC_INIT,
6252 RDMA_RAMROD_FUNC_CLOSE,
6253 RDMA_RAMROD_REGISTER_MR,
6254 RDMA_RAMROD_DEREGISTER_MR,
6255 RDMA_RAMROD_CREATE_CQ,
6256 RDMA_RAMROD_RESIZE_CQ,
6257 RDMA_RAMROD_DESTROY_CQ,
6258 RDMA_RAMROD_CREATE_SRQ,
6259 RDMA_RAMROD_MODIFY_SRQ,
6260 RDMA_RAMROD_DESTROY_SRQ,
6261 MAX_RDMA_RAMROD_CMD_ID
6264 struct rdma_register_tid_ramrod_data {
6266 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F
6267 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0
6268 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
6269 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 5
6270 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
6271 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 6
6272 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
6273 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 7
6274 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
6275 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 8
6276 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
6277 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 9
6278 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
6279 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 10
6280 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
6281 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 11
6282 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
6283 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 12
6284 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
6285 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 13
6286 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3
6287 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT 14
6289 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F
6290 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
6291 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7
6292 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5
6294 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1
6295 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0
6296 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1
6297 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1
6298 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F
6299 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2
6310 struct regpair pbl_base;
6311 struct regpair dif_error_addr;
6312 struct regpair dif_runt_addr;
6313 __le32 reserved4[2];
6316 struct rdma_resize_cq_output_params {
6321 struct rdma_resize_cq_ramrod_data {
6323 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1
6324 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
6325 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
6326 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
6327 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F
6328 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2
6329 u8 pbl_log_page_size;
6330 __le16 pbl_num_pages;
6332 struct regpair pbl_addr;
6333 struct regpair output_params_addr;
6336 struct rdma_srq_context {
6337 struct regpair temp[8];
6340 struct rdma_srq_create_ramrod_data {
6341 struct regpair pbl_base_addr;
6342 __le16 pages_in_srq_pbl;
6344 struct rdma_srq_id srq_id;
6348 struct regpair producers_addr;
6351 struct rdma_srq_destroy_ramrod_data {
6352 struct rdma_srq_id srq_id;
6356 struct rdma_srq_modify_ramrod_data {
6357 struct rdma_srq_id srq_id;
6361 struct ystorm_rdma_task_st_ctx {
6362 struct regpair temp[4];
6365 struct ystorm_rdma_task_ag_ctx {
6368 __le16 msem_ctx_upd_seq;
6370 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6371 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6372 #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6373 #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6374 #define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6375 #define YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6376 #define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
6377 #define YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
6378 #define YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
6379 #define YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
6381 #define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6382 #define YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
6383 #define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6384 #define YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
6385 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
6386 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
6387 #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6388 #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
6389 #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6390 #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
6392 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
6393 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
6394 #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6395 #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
6396 #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6397 #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
6398 #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6399 #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
6400 #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6401 #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
6402 #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6403 #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
6404 #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6405 #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
6406 #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6407 #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
6413 __le16 tx_ref_count;
6414 __le16 last_used_ltid;
6415 __le16 parent_mr_lo;
6416 __le16 parent_mr_hi;
6421 struct mstorm_rdma_task_ag_ctx {
6426 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6427 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6428 #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6429 #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6430 #define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6431 #define MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6432 #define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
6433 #define MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
6434 #define MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
6435 #define MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
6437 #define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6438 #define MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
6439 #define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6440 #define MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
6441 #define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
6442 #define MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
6443 #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6444 #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
6445 #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6446 #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
6448 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
6449 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
6450 #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6451 #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
6452 #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6453 #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
6454 #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6455 #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
6456 #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6457 #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
6458 #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6459 #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
6460 #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6461 #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
6462 #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6463 #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
6469 __le16 tx_ref_count;
6470 __le16 last_used_ltid;
6471 __le16 parent_mr_lo;
6472 __le16 parent_mr_hi;
6477 struct ustorm_rdma_task_st_ctx {
6478 struct regpair temp[2];
6481 struct ustorm_rdma_task_ag_ctx {
6486 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6487 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6488 #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6489 #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6490 #define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1
6491 #define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5
6492 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
6493 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
6495 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
6496 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
6497 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
6498 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
6499 #define USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
6500 #define USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4
6501 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
6502 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
6504 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
6505 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
6506 #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
6507 #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
6508 #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
6509 #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
6510 #define USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
6511 #define USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3
6512 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
6513 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
6514 #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6515 #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
6516 #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6517 #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
6518 #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6519 #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
6521 #define USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6522 #define USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0
6523 #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6524 #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
6525 #define USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6526 #define USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2
6527 #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6528 #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
6529 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
6530 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
6531 __le32 dif_err_intervals;
6532 __le32 dif_error_1st_interval;
6534 __le32 dif_runt_value;
6539 struct rdma_task_context {
6540 struct ystorm_rdma_task_st_ctx ystorm_st_context;
6541 struct ystorm_rdma_task_ag_ctx ystorm_ag_context;
6542 struct tdif_task_context tdif_context;
6543 struct mstorm_rdma_task_ag_ctx mstorm_ag_context;
6544 struct mstorm_rdma_task_st_ctx mstorm_st_context;
6545 struct rdif_task_context rdif_context;
6546 struct ustorm_rdma_task_st_ctx ustorm_st_context;
6547 struct regpair ustorm_st_padding[2];
6548 struct ustorm_rdma_task_ag_ctx ustorm_ag_context;
6551 enum rdma_tid_type {
6552 RDMA_TID_REGISTERED_MR,
6559 struct xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
6563 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
6564 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
6565 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1
6566 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1
6567 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1
6568 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2
6569 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
6570 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
6571 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1
6572 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4
6573 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1
6574 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5
6575 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1
6576 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6
6577 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1
6578 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7
6580 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1
6581 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
6582 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1
6583 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1
6584 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1
6585 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
6586 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
6587 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
6588 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
6589 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
6590 #define XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK 0x1
6591 #define XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT 5
6592 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
6593 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6
6594 #define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
6595 #define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
6597 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
6598 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
6599 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
6600 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2
6601 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
6602 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4
6603 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
6604 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6
6606 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
6607 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
6608 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
6609 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2
6610 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
6611 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4
6612 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
6613 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6
6615 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
6616 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
6617 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
6618 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2
6619 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
6620 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4
6621 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
6622 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6
6624 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
6625 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
6626 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
6627 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2
6628 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
6629 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4
6630 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
6631 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6
6633 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
6634 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
6635 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
6636 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2
6637 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
6638 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4
6639 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
6640 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6
6642 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
6643 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
6644 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
6645 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2
6646 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
6647 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
6648 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
6649 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
6650 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
6651 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
6653 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
6654 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
6655 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
6656 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
6657 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
6658 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
6659 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
6660 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
6661 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
6662 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
6663 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1
6664 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5
6665 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
6666 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
6667 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
6668 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
6670 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
6671 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
6672 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
6673 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
6674 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
6675 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
6676 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
6677 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
6678 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
6679 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
6680 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
6681 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
6682 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1
6683 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6
6684 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1
6685 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7
6687 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1
6688 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
6689 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1
6690 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1
6691 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1
6692 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2
6693 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1
6694 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3
6695 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
6696 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
6697 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1
6698 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5
6699 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1
6700 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6
6701 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1
6702 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7
6704 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1
6705 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
6706 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1
6707 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1
6708 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1
6709 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2
6710 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
6711 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
6712 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
6713 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
6714 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
6715 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
6716 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
6717 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
6718 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
6719 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
6721 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
6722 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
6723 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
6724 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
6725 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
6726 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
6727 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
6728 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
6729 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
6730 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
6731 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
6732 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
6733 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
6734 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
6735 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
6736 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
6738 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
6739 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
6740 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
6741 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
6742 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
6743 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
6744 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
6745 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
6746 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
6747 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
6748 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
6749 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
6750 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
6751 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
6752 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
6753 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
6755 #define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1
6756 #define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
6757 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1
6758 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1
6759 #define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
6760 #define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2
6761 #define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1
6762 #define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4
6763 #define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
6764 #define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
6765 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
6766 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6
6786 struct mstorm_rdma_conn_ag_ctx {
6790 #define MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
6791 #define MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
6792 #define MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
6793 #define MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
6794 #define MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
6795 #define MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
6796 #define MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6797 #define MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
6798 #define MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6799 #define MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
6801 #define MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
6802 #define MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
6803 #define MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6804 #define MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
6805 #define MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6806 #define MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
6807 #define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
6808 #define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
6809 #define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
6810 #define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
6811 #define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6812 #define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
6813 #define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6814 #define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
6815 #define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6816 #define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
6823 struct tstorm_rdma_conn_ag_ctx {
6827 #define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6828 #define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6829 #define TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
6830 #define TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
6831 #define TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
6832 #define TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
6833 #define TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1
6834 #define TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3
6835 #define TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
6836 #define TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
6837 #define TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
6838 #define TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
6839 #define TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
6840 #define TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6
6842 #define TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6843 #define TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0
6844 #define TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6845 #define TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2
6846 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
6847 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
6848 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6849 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
6851 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
6852 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
6853 #define TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
6854 #define TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2
6855 #define TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3
6856 #define TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4
6857 #define TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
6858 #define TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6
6860 #define TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
6861 #define TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0
6862 #define TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
6863 #define TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2
6864 #define TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
6865 #define TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4
6866 #define TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6867 #define TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5
6868 #define TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6869 #define TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6
6870 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
6871 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
6873 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6874 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
6875 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
6876 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
6877 #define TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
6878 #define TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2
6879 #define TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1
6880 #define TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3
6881 #define TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
6882 #define TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4
6883 #define TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
6884 #define TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5
6885 #define TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
6886 #define TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6
6887 #define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
6888 #define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7
6890 #define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
6891 #define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0
6892 #define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6893 #define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
6894 #define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6895 #define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
6896 #define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6897 #define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
6898 #define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
6899 #define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
6900 #define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
6901 #define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
6902 #define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
6903 #define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
6904 #define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
6905 #define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
6927 struct tstorm_rdma_task_ag_ctx {
6932 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF
6933 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
6934 #define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1
6935 #define TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4
6936 #define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6937 #define TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6938 #define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
6939 #define TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
6940 #define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
6941 #define TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
6943 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
6944 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
6945 #define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1
6946 #define TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1
6947 #define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6948 #define TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2
6949 #define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6950 #define TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4
6951 #define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
6952 #define TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6
6954 #define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
6955 #define TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
6956 #define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
6957 #define TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2
6958 #define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
6959 #define TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4
6960 #define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
6961 #define TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6
6963 #define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
6964 #define TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
6965 #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6966 #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2
6967 #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6968 #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3
6969 #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
6970 #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4
6971 #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
6972 #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5
6973 #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1
6974 #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6
6975 #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1
6976 #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7
6978 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1
6979 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
6980 #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1
6981 #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1
6982 #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6983 #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
6984 #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6985 #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
6986 #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6987 #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
6988 #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6989 #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
6990 #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6991 #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
6992 #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6993 #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
7006 struct ustorm_rdma_conn_ag_ctx {
7010 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7011 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7012 #define USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
7013 #define USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
7014 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7015 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2
7016 #define USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
7017 #define USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
7018 #define USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
7019 #define USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
7021 #define USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
7022 #define USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
7023 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
7024 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
7025 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
7026 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
7027 #define USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
7028 #define USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6
7030 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7031 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7032 #define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
7033 #define USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
7034 #define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
7035 #define USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
7036 #define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
7037 #define USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3
7038 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
7039 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
7040 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
7041 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
7042 #define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
7043 #define USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6
7044 #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
7045 #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
7047 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1
7048 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
7049 #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
7050 #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
7051 #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
7052 #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
7053 #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
7054 #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
7055 #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
7056 #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
7057 #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
7058 #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
7059 #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
7060 #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
7061 #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
7062 #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
7075 struct xstorm_rdma_conn_ag_ctx {
7079 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7080 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7081 #define XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
7082 #define XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
7083 #define XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
7084 #define XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
7085 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
7086 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
7087 #define XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
7088 #define XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
7089 #define XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
7090 #define XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
7091 #define XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1
7092 #define XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6
7093 #define XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1
7094 #define XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7
7096 #define XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1
7097 #define XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0
7098 #define XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1
7099 #define XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1
7100 #define XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1
7101 #define XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2
7102 #define XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1
7103 #define XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3
7104 #define XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1
7105 #define XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4
7106 #define XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7107 #define XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5
7108 #define XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1
7109 #define XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6
7110 #define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
7111 #define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
7113 #define XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
7114 #define XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0
7115 #define XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
7116 #define XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2
7117 #define XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
7118 #define XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4
7119 #define XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
7120 #define XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6
7122 #define XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3
7123 #define XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0
7124 #define XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3
7125 #define XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2
7126 #define XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
7127 #define XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4
7128 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7129 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7131 #define XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
7132 #define XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0
7133 #define XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
7134 #define XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2
7135 #define XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
7136 #define XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4
7137 #define XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3
7138 #define XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6
7140 #define XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3
7141 #define XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0
7142 #define XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3
7143 #define XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2
7144 #define XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3
7145 #define XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4
7146 #define XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3
7147 #define XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6
7149 #define XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3
7150 #define XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0
7151 #define XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3
7152 #define XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2
7153 #define XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3
7154 #define XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4
7155 #define XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3
7156 #define XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6
7158 #define XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3
7159 #define XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0
7160 #define XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3
7161 #define XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2
7162 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3
7163 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4
7164 #define XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
7165 #define XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6
7166 #define XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
7167 #define XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7
7169 #define XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
7170 #define XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0
7171 #define XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
7172 #define XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1
7173 #define XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1
7174 #define XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2
7175 #define XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1
7176 #define XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3
7177 #define XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
7178 #define XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4
7179 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7180 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
7181 #define XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
7182 #define XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6
7183 #define XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
7184 #define XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7
7186 #define XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
7187 #define XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0
7188 #define XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1
7189 #define XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1
7190 #define XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1
7191 #define XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2
7192 #define XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1
7193 #define XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3
7194 #define XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1
7195 #define XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4
7196 #define XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1
7197 #define XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5
7198 #define XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1
7199 #define XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6
7200 #define XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1
7201 #define XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7
7203 #define XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1
7204 #define XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0
7205 #define XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1
7206 #define XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1
7207 #define XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1
7208 #define XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2
7209 #define XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1
7210 #define XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3
7211 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
7212 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
7213 #define XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1
7214 #define XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5
7215 #define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
7216 #define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6
7217 #define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
7218 #define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7
7220 #define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
7221 #define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0
7222 #define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
7223 #define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1
7224 #define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
7225 #define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2
7226 #define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
7227 #define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3
7228 #define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
7229 #define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4
7230 #define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
7231 #define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5
7232 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
7233 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
7234 #define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1
7235 #define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7
7237 #define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1
7238 #define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0
7239 #define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1
7240 #define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1
7241 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
7242 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
7243 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
7244 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
7245 #define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1
7246 #define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4
7247 #define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1
7248 #define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5
7249 #define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1
7250 #define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6
7251 #define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1
7252 #define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7
7254 #define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1
7255 #define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0
7256 #define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1
7257 #define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1
7258 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
7259 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
7260 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
7261 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
7262 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
7263 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
7264 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
7265 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
7266 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
7267 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
7268 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
7269 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
7271 #define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1
7272 #define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0
7273 #define XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1
7274 #define XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1
7275 #define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
7276 #define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
7277 #define XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1
7278 #define XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4
7279 #define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
7280 #define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
7281 #define XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3
7282 #define XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6
7304 struct ystorm_rdma_conn_ag_ctx {
7308 #define YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
7309 #define YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
7310 #define YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
7311 #define YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
7312 #define YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
7313 #define YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
7314 #define YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
7315 #define YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
7316 #define YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
7317 #define YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
7319 #define YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
7320 #define YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
7321 #define YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
7322 #define YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
7323 #define YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
7324 #define YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
7325 #define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
7326 #define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
7327 #define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
7328 #define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
7329 #define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
7330 #define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
7331 #define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
7332 #define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
7333 #define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
7334 #define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
7348 struct mstorm_roce_conn_st_ctx {
7349 struct regpair temp[6];
7352 struct pstorm_roce_conn_st_ctx {
7353 struct regpair temp[16];
7356 struct ystorm_roce_conn_st_ctx {
7357 struct regpair temp[2];
7360 struct xstorm_roce_conn_st_ctx {
7361 struct regpair temp[24];
7364 struct tstorm_roce_conn_st_ctx {
7365 struct regpair temp[30];
7368 struct ustorm_roce_conn_st_ctx {
7369 struct regpair temp[12];
7372 struct roce_conn_context {
7373 struct ystorm_roce_conn_st_ctx ystorm_st_context;
7374 struct regpair ystorm_st_padding[2];
7375 struct pstorm_roce_conn_st_ctx pstorm_st_context;
7376 struct xstorm_roce_conn_st_ctx xstorm_st_context;
7377 struct regpair xstorm_st_padding[2];
7378 struct xstorm_rdma_conn_ag_ctx xstorm_ag_context;
7379 struct tstorm_rdma_conn_ag_ctx tstorm_ag_context;
7380 struct timers_context timer_context;
7381 struct ustorm_rdma_conn_ag_ctx ustorm_ag_context;
7382 struct tstorm_roce_conn_st_ctx tstorm_st_context;
7383 struct mstorm_roce_conn_st_ctx mstorm_st_context;
7384 struct ustorm_roce_conn_st_ctx ustorm_st_context;
7385 struct regpair ustorm_st_padding[2];
7388 struct roce_create_qp_req_ramrod_data {
7390 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
7391 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
7392 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
7393 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2
7394 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
7395 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3
7396 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
7397 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4
7398 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1
7399 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 7
7400 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
7401 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8
7402 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
7403 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12
7411 __le32 ack_timeout_val;
7415 __le16 sq_num_pages;
7416 __le16 low_latency_phy_queue;
7417 struct regpair sq_pbl_addr;
7418 struct regpair orq_pbl_addr;
7419 __le16 local_mac_addr[3];
7420 __le16 remote_mac_addr[3];
7422 __le16 udp_src_port;
7425 struct regpair qp_handle_for_cqe;
7426 struct regpair qp_handle_for_async;
7427 u8 stats_counter_id;
7430 __le16 regular_latency_phy_queue;
7434 struct roce_create_qp_resp_ramrod_data {
7436 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
7437 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
7438 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
7439 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
7440 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
7441 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
7442 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
7443 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
7444 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
7445 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5
7446 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
7447 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6
7448 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
7449 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7
7450 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
7451 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8
7452 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
7453 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11
7461 u8 stats_counter_id;
7466 __le16 rq_num_pages;
7467 struct rdma_srq_id srq_id;
7468 struct regpair rq_pbl_addr;
7469 struct regpair irq_pbl_addr;
7470 __le16 local_mac_addr[3];
7471 __le16 remote_mac_addr[3];
7473 __le16 udp_src_port;
7476 struct regpair qp_handle_for_cqe;
7477 struct regpair qp_handle_for_async;
7478 __le16 low_latency_phy_queue;
7481 __le16 regular_latency_phy_queue;
7485 struct roce_destroy_qp_req_output_params {
7486 __le32 num_bound_mw;
7490 struct roce_destroy_qp_req_ramrod_data {
7491 struct regpair output_params_addr;
7494 struct roce_destroy_qp_resp_output_params {
7495 __le32 num_invalidated_mw;
7499 struct roce_destroy_qp_resp_ramrod_data {
7500 struct regpair output_params_addr;
7503 struct roce_events_stats {
7504 __le16 silent_drops;
7505 __le16 rnr_naks_sent;
7506 __le32 retransmit_count;
7507 __le32 icrc_error_count;
7511 enum roce_event_opcode {
7512 ROCE_EVENT_CREATE_QP = 11,
7513 ROCE_EVENT_MODIFY_QP,
7514 ROCE_EVENT_QUERY_QP,
7515 ROCE_EVENT_DESTROY_QP,
7516 ROCE_EVENT_CREATE_UD_QP,
7517 ROCE_EVENT_DESTROY_UD_QP,
7518 MAX_ROCE_EVENT_OPCODE
7521 struct roce_init_func_params {
7523 u8 cnp_vlan_priority;
7526 __le32 cnp_send_timeout;
7529 struct roce_init_func_ramrod_data {
7530 struct rdma_init_func_ramrod_data rdma;
7531 struct roce_init_func_params roce;
7534 struct roce_modify_qp_req_ramrod_data {
7536 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7537 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7538 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1
7539 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1
7540 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1
7541 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2
7542 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7543 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3
7544 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7545 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4
7546 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1
7547 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5
7548 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1
7549 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6
7550 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1
7551 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7
7552 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1
7553 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8
7554 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1
7555 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9
7556 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
7557 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10
7558 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x7
7559 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 13
7561 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
7562 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0
7563 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
7564 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4
7570 __le32 ack_timeout_val;
7573 __le32 reserved3[3];
7578 struct roce_modify_qp_resp_ramrod_data {
7580 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7581 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7582 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
7583 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1
7584 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
7585 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2
7586 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
7587 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3
7588 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7589 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4
7590 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7591 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5
7592 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1
7593 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6
7594 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1
7595 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7
7596 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1
7597 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8
7598 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
7599 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9
7600 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x3F
7601 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 10
7603 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
7604 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0
7605 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
7606 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3
7618 struct roce_query_qp_req_output_params {
7621 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
7622 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
7623 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1
7624 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1
7625 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7626 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2
7629 struct roce_query_qp_req_ramrod_data {
7630 struct regpair output_params_addr;
7633 struct roce_query_qp_resp_output_params {
7636 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
7637 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
7638 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
7639 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
7642 struct roce_query_qp_resp_ramrod_data {
7643 struct regpair output_params_addr;
7646 enum roce_ramrod_cmd_id {
7647 ROCE_RAMROD_CREATE_QP = 11,
7648 ROCE_RAMROD_MODIFY_QP,
7649 ROCE_RAMROD_QUERY_QP,
7650 ROCE_RAMROD_DESTROY_QP,
7651 ROCE_RAMROD_CREATE_UD_QP,
7652 ROCE_RAMROD_DESTROY_UD_QP,
7653 MAX_ROCE_RAMROD_CMD_ID
7656 struct mstorm_roce_req_conn_ag_ctx {
7660 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7661 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
7662 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7663 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
7664 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7665 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
7666 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7667 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
7668 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7669 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
7671 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7672 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
7673 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7674 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
7675 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7676 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
7677 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7678 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
7679 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7680 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
7681 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7682 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
7683 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7684 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
7685 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7686 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
7693 struct mstorm_roce_resp_conn_ag_ctx {
7697 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
7698 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
7699 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
7700 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
7701 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7702 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
7703 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
7704 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
7705 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
7706 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
7708 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7709 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
7710 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
7711 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
7712 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
7713 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
7714 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7715 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
7716 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7717 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
7718 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7719 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
7720 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7721 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
7722 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7723 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
7730 struct tstorm_roce_req_conn_ag_ctx {
7734 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7735 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7736 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1
7737 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1
7738 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1
7739 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2
7740 #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1
7741 #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3
7742 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7743 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
7744 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
7745 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
7746 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
7747 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6
7749 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7750 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0
7751 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
7752 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2
7753 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
7754 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
7755 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7756 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7758 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7759 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7760 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
7761 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2
7762 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
7763 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4
7764 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
7765 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6
7767 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
7768 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
7769 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
7770 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2
7771 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1
7772 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4
7773 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7774 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5
7775 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1
7776 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6
7777 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
7778 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
7780 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7781 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7782 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7783 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
7784 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1
7785 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2
7786 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1
7787 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3
7788 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1
7789 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4
7790 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1
7791 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
7792 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1
7793 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6
7794 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7795 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
7797 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7798 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
7799 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7800 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
7801 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7802 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
7803 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7804 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
7805 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
7806 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
7807 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1
7808 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5
7809 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
7810 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
7811 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
7812 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
7822 u8 tx_cqe_error_type;
7824 __le16 snd_sq_cons_th;
7834 struct tstorm_roce_resp_conn_ag_ctx {
7838 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7839 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7840 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1
7841 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1
7842 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1
7843 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2
7844 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1
7845 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3
7846 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7847 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
7848 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1
7849 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5
7850 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7851 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6
7853 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
7854 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
7855 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
7856 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2
7857 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
7858 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4
7859 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7860 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7862 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7863 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7864 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
7865 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2
7866 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
7867 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4
7868 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
7869 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6
7871 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
7872 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
7873 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
7874 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2
7875 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7876 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4
7877 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
7878 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5
7879 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1
7880 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6
7881 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
7882 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7
7884 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7885 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7886 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7887 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
7888 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
7889 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2
7890 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1
7891 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3
7892 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
7893 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4
7894 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
7895 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5
7896 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
7897 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6
7898 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7899 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
7901 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7902 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
7903 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7904 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
7905 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7906 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
7907 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7908 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
7909 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
7910 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
7911 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1
7912 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5
7913 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
7914 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
7915 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
7916 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
7917 __le32 psn_and_rxmit_id_echo;
7926 u8 tx_async_error_type;
7934 __le32 num_invlidated_mw;
7938 struct ustorm_roce_req_conn_ag_ctx {
7942 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7943 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
7944 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7945 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
7946 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7947 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
7948 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7949 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
7950 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7951 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
7953 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
7954 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
7955 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
7956 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2
7957 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
7958 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4
7959 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
7960 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6
7962 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7963 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
7964 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7965 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
7966 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7967 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
7968 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
7969 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3
7970 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1
7971 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4
7972 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1
7973 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5
7974 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1
7975 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6
7976 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7977 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
7979 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7980 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
7981 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7982 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
7983 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7984 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
7985 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7986 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
7987 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
7988 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
7989 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
7990 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5
7991 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
7992 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
7993 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
7994 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
8007 struct ustorm_roce_resp_conn_ag_ctx {
8011 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8012 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8013 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8014 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
8015 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8016 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
8017 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8018 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
8019 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8020 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
8022 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8023 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
8024 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
8025 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2
8026 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
8027 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4
8028 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
8029 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6
8031 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8032 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8033 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8034 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
8035 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8036 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
8037 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8038 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3
8039 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1
8040 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4
8041 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1
8042 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5
8043 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
8044 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6
8045 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8046 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
8048 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8049 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
8050 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8051 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
8052 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8053 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
8054 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8055 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
8056 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8057 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
8058 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
8059 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5
8060 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8061 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
8062 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
8063 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
8076 struct xstorm_roce_req_conn_ag_ctx {
8080 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8081 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8082 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1
8083 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1
8084 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1
8085 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2
8086 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8087 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8088 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1
8089 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4
8090 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1
8091 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5
8092 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1
8093 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6
8094 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1
8095 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7
8097 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1
8098 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
8099 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1
8100 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1
8101 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1
8102 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2
8103 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
8104 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3
8105 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1
8106 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4
8107 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1
8108 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5
8109 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8110 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6
8111 #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8112 #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
8114 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8115 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
8116 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8117 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2
8118 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8119 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4
8120 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
8121 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6
8123 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8124 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
8125 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8126 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
8127 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
8128 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4
8129 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8130 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
8132 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3
8133 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0
8134 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3
8135 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2
8136 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
8137 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4
8138 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
8139 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6
8141 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
8142 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
8143 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
8144 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2
8145 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
8146 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4
8147 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
8148 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6
8150 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
8151 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
8152 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
8153 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2
8154 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
8155 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4
8156 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
8157 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6
8159 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
8160 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
8161 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
8162 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2
8163 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8164 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8165 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8166 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6
8167 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8168 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7
8170 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8171 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
8172 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
8173 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1
8174 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
8175 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2
8176 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8177 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
8178 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1
8179 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4
8180 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8181 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
8182 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1
8183 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6
8184 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1
8185 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7
8187 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1
8188 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
8189 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1
8190 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1
8191 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1
8192 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2
8193 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1
8194 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3
8195 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1
8196 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4
8197 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1
8198 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5
8199 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1
8200 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6
8201 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1
8202 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7
8204 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1
8205 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
8206 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1
8207 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1
8208 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1
8209 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2
8210 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1
8211 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3
8212 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8213 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
8214 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1
8215 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5
8216 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8217 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6
8218 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8219 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7
8221 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8222 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
8223 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8224 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1
8225 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8226 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2
8227 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
8228 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3
8229 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
8230 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4
8231 #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1
8232 #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
8233 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8234 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
8235 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1
8236 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7
8238 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1
8239 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
8240 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1
8241 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1
8242 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8243 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
8244 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8245 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
8246 #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1
8247 #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4
8248 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1
8249 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5
8250 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1
8251 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6
8252 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1
8253 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7
8255 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1
8256 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
8257 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1
8258 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1
8259 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8260 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
8261 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8262 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
8263 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8264 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
8265 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8266 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
8267 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8268 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
8269 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8270 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
8272 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1
8273 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
8274 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1
8275 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1
8276 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
8277 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
8278 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1
8279 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4
8280 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
8281 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
8282 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
8283 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6
8305 struct xstorm_roce_resp_conn_ag_ctx {
8309 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8310 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8311 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1
8312 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1
8313 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1
8314 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2
8315 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8316 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8317 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1
8318 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4
8319 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1
8320 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5
8321 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1
8322 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6
8323 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1
8324 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7
8326 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1
8327 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
8328 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1
8329 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1
8330 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1
8331 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2
8332 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
8333 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3
8334 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1
8335 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4
8336 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1
8337 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5
8338 #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8339 #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6
8340 #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8341 #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
8343 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8344 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
8345 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8346 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2
8347 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8348 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4
8349 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8350 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6
8352 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
8353 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
8354 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8355 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
8356 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
8357 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4
8358 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8359 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
8361 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
8362 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
8363 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
8364 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2
8365 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
8366 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4
8367 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
8368 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6
8370 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
8371 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
8372 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
8373 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2
8374 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
8375 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4
8376 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
8377 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6
8379 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
8380 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
8381 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
8382 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2
8383 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
8384 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4
8385 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
8386 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6
8388 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
8389 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
8390 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
8391 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2
8392 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8393 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8394 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8395 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6
8396 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8397 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7
8399 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8400 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
8401 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8402 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1
8403 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1
8404 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2
8405 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8406 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
8407 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1
8408 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4
8409 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8410 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
8411 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
8412 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6
8413 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
8414 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7
8416 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
8417 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
8418 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1
8419 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1
8420 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1
8421 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2
8422 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1
8423 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3
8424 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1
8425 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4
8426 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1
8427 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5
8428 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1
8429 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6
8430 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1
8431 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7
8433 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1
8434 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
8435 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1
8436 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1
8437 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1
8438 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2
8439 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1
8440 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3
8441 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8442 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
8443 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1
8444 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5
8445 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8446 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6
8447 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8448 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7
8450 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8451 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
8452 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8453 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1
8454 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8455 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2
8456 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8457 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3
8458 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
8459 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4
8460 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8461 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5
8462 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8463 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
8464 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1
8465 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7
8467 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_MASK 0x1
8468 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_SHIFT 0
8469 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1
8470 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 1
8471 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8472 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
8473 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8474 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
8475 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1
8476 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4
8477 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1
8478 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5
8479 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1
8480 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6
8481 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1
8482 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7
8484 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1
8485 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
8486 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1
8487 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1
8488 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8489 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
8490 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8491 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
8492 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8493 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
8494 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8495 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
8496 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8497 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
8498 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8499 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
8501 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1
8502 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
8503 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1
8504 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1
8505 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1
8506 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2
8507 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1
8508 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3
8509 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1
8510 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4
8511 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1
8512 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5
8513 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
8514 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6
8527 __le32 rxmit_psn_and_id;
8528 __le32 rxmit_bytes_length;
8533 __le32 msn_and_syndrome;
8536 struct ystorm_roce_req_conn_ag_ctx {
8540 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
8541 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
8542 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
8543 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
8544 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8545 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
8546 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8547 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
8548 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8549 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
8551 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8552 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
8553 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8554 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
8555 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8556 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
8557 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8558 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
8559 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8560 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
8561 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8562 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
8563 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8564 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
8565 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8566 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
8580 struct ystorm_roce_resp_conn_ag_ctx {
8584 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8585 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8586 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8587 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
8588 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8589 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
8590 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8591 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
8592 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8593 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
8595 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8596 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8597 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8598 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
8599 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8600 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
8601 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8602 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
8603 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8604 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
8605 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8606 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
8607 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8608 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
8609 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8610 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
8631 struct ystorm_iwarp_conn_st_ctx {
8635 struct pstorm_iwarp_conn_st_ctx {
8636 __le32 reserved[36];
8639 struct xstorm_iwarp_conn_st_ctx {
8640 __le32 reserved[44];
8643 struct xstorm_iwarp_conn_ag_ctx {
8647 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8648 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8649 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
8650 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
8651 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1
8652 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2
8653 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8654 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8655 #define XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
8656 #define XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
8657 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1
8658 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5
8659 #define XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1
8660 #define XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6
8661 #define XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1
8662 #define XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7
8664 #define XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1
8665 #define XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0
8666 #define XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1
8667 #define XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1
8668 #define XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1
8669 #define XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2
8670 #define XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1
8671 #define XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3
8672 #define XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1
8673 #define XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4
8674 #define XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1
8675 #define XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5
8676 #define XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1
8677 #define XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6
8678 #define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1
8679 #define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7
8681 #define XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
8682 #define XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0
8683 #define XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
8684 #define XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2
8685 #define XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
8686 #define XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4
8687 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
8688 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
8690 #define XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
8691 #define XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0
8692 #define XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
8693 #define XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2
8694 #define XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
8695 #define XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4
8696 #define XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
8697 #define XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6
8699 #define XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
8700 #define XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0
8701 #define XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3
8702 #define XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2
8703 #define XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3
8704 #define XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4
8705 #define XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3
8706 #define XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6
8708 #define XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3
8709 #define XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0
8710 #define XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3
8711 #define XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2
8712 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8713 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4
8714 #define XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3
8715 #define XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6
8717 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3
8718 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
8719 #define XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3
8720 #define XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2
8721 #define XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3
8722 #define XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4
8723 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
8724 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
8726 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
8727 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
8728 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
8729 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2
8730 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8731 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8732 #define XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
8733 #define XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6
8734 #define XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
8735 #define XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7
8737 #define XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
8738 #define XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0
8739 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
8740 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
8741 #define XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
8742 #define XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2
8743 #define XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
8744 #define XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3
8745 #define XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
8746 #define XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4
8747 #define XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
8748 #define XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5
8749 #define XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
8750 #define XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6
8751 #define XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1
8752 #define XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7
8754 #define XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1
8755 #define XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0
8756 #define XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1
8757 #define XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1
8758 #define XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1
8759 #define XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2
8760 #define XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1
8761 #define XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3
8762 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
8763 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4
8764 #define XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1
8765 #define XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5
8766 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
8767 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6
8768 #define XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1
8769 #define XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7
8771 #define XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1
8772 #define XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0
8773 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
8774 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
8775 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
8776 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
8777 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
8778 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3
8779 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8780 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
8781 #define XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1
8782 #define XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5
8783 #define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
8784 #define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6
8785 #define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
8786 #define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7
8788 #define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
8789 #define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
8790 #define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
8791 #define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1
8792 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1
8793 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2
8794 #define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
8795 #define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3
8796 #define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
8797 #define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4
8798 #define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
8799 #define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5
8800 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8801 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
8802 #define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1
8803 #define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7
8805 #define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1
8806 #define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0
8807 #define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1
8808 #define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1
8809 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8810 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
8811 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8812 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
8813 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1
8814 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4
8815 #define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1
8816 #define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5
8817 #define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1
8818 #define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6
8819 #define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1
8820 #define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7
8822 #define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1
8823 #define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0
8824 #define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1
8825 #define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1
8826 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1
8827 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2
8828 #define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1
8829 #define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3
8830 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8831 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
8832 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1
8833 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5
8834 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8835 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
8836 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8837 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
8839 #define XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1
8840 #define XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0
8841 #define XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1
8842 #define XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1
8843 #define XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1
8844 #define XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2
8845 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1
8846 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3
8847 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
8848 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
8849 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
8850 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
8851 #define XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3
8852 #define XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6
8856 __le16 sq_comp_cons;
8868 __le32 more_to_send_seq;
8870 __le32 rewinded_snd_max;
8872 __le16 irq_prod_via_msdm;
8874 __le16 hq_cons_th_or_mpa_data;
8881 u8 wqe_data_pad_bytes;
8883 u8 irq_prod_via_msem;
8885 u8 max_pkt_pdu_size_lo;
8886 u8 max_pkt_pdu_size_hi;
8889 __le16 e5_reserved4;
8892 __le32 shared_queue_page_addr_lo;
8893 __le32 shared_queue_page_addr_hi;
8900 struct tstorm_iwarp_conn_ag_ctx {
8904 #define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8905 #define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8906 #define TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
8907 #define TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
8908 #define TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1
8909 #define TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2
8910 #define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
8911 #define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3
8912 #define TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
8913 #define TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
8914 #define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
8915 #define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
8916 #define TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
8917 #define TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6
8919 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3
8920 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0
8921 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3
8922 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2
8923 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
8924 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
8925 #define TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
8926 #define TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6
8928 #define TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
8929 #define TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0
8930 #define TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
8931 #define TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2
8932 #define TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
8933 #define TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4
8934 #define TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
8935 #define TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6
8937 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
8938 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
8939 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3
8940 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2
8941 #define TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
8942 #define TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4
8943 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1
8944 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5
8945 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1
8946 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6
8947 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
8948 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
8950 #define TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
8951 #define TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0
8952 #define TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
8953 #define TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1
8954 #define TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
8955 #define TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2
8956 #define TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
8957 #define TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3
8958 #define TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
8959 #define TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4
8960 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
8961 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
8962 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1
8963 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6
8964 #define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
8965 #define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7
8967 #define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
8968 #define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0
8969 #define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
8970 #define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
8971 #define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
8972 #define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
8973 #define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
8974 #define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
8975 #define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
8976 #define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
8977 #define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1
8978 #define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5
8979 #define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
8980 #define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
8981 #define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
8982 #define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
8985 __le32 unaligned_nxt_seq;
8994 __le16 sq_tx_cons_th;
9001 __le32 last_hq_sequence;
9004 struct tstorm_iwarp_conn_st_ctx {
9005 __le32 reserved[60];
9008 struct mstorm_iwarp_conn_st_ctx {
9009 __le32 reserved[32];
9012 struct ustorm_iwarp_conn_st_ctx {
9013 __le32 reserved[24];
9016 struct iwarp_conn_context {
9017 struct ystorm_iwarp_conn_st_ctx ystorm_st_context;
9018 struct regpair ystorm_st_padding[2];
9019 struct pstorm_iwarp_conn_st_ctx pstorm_st_context;
9020 struct regpair pstorm_st_padding[2];
9021 struct xstorm_iwarp_conn_st_ctx xstorm_st_context;
9022 struct regpair xstorm_st_padding[2];
9023 struct xstorm_iwarp_conn_ag_ctx xstorm_ag_context;
9024 struct tstorm_iwarp_conn_ag_ctx tstorm_ag_context;
9025 struct timers_context timer_context;
9026 struct ustorm_rdma_conn_ag_ctx ustorm_ag_context;
9027 struct tstorm_iwarp_conn_st_ctx tstorm_st_context;
9028 struct regpair tstorm_st_padding[2];
9029 struct mstorm_iwarp_conn_st_ctx mstorm_st_context;
9030 struct ustorm_iwarp_conn_st_ctx ustorm_st_context;
9033 struct iwarp_create_qp_ramrod_data {
9035 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
9036 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0
9037 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
9038 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1
9039 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9040 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
9041 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9042 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
9043 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9044 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
9045 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1
9046 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5
9047 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x3
9048 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 6
9051 __le16 sq_num_pages;
9052 __le16 rq_num_pages;
9053 __le32 reserved3[2];
9054 struct regpair qp_handle_for_cqe;
9055 struct rdma_srq_id srq_id;
9056 __le32 cq_cid_for_sq;
9057 __le32 cq_cid_for_rq;
9064 enum iwarp_eqe_async_opcode {
9065 IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE,
9066 IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED,
9067 IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE,
9068 IWARP_EVENT_TYPE_ASYNC_CID_CLEANED,
9069 IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED,
9070 IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE,
9071 IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW,
9072 MAX_IWARP_EQE_ASYNC_OPCODE
9075 struct iwarp_eqe_data_mpa_async_completion {
9076 __le16 ulp_data_len;
9080 struct iwarp_eqe_data_tcp_async_completion {
9081 __le16 ulp_data_len;
9082 u8 mpa_handshake_mode;
9086 enum iwarp_eqe_sync_opcode {
9087 IWARP_EVENT_TYPE_TCP_OFFLOAD =
9089 IWARP_EVENT_TYPE_MPA_OFFLOAD,
9090 IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR,
9091 IWARP_EVENT_TYPE_CREATE_QP,
9092 IWARP_EVENT_TYPE_QUERY_QP,
9093 IWARP_EVENT_TYPE_MODIFY_QP,
9094 IWARP_EVENT_TYPE_DESTROY_QP,
9095 MAX_IWARP_EQE_SYNC_OPCODE
9098 enum iwarp_fw_return_code {
9099 IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 5,
9100 IWARP_CONN_ERROR_TCP_CONNECTION_RST,
9101 IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT,
9102 IWARP_CONN_ERROR_MPA_ERROR_REJECT,
9103 IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER,
9104 IWARP_CONN_ERROR_MPA_RST,
9105 IWARP_CONN_ERROR_MPA_FIN,
9106 IWARP_CONN_ERROR_MPA_RTR_MISMATCH,
9107 IWARP_CONN_ERROR_MPA_INSUF_IRD,
9108 IWARP_CONN_ERROR_MPA_INVALID_PACKET,
9109 IWARP_CONN_ERROR_MPA_LOCAL_ERROR,
9110 IWARP_CONN_ERROR_MPA_TIMEOUT,
9111 IWARP_CONN_ERROR_MPA_TERMINATE,
9112 IWARP_QP_IN_ERROR_GOOD_CLOSE,
9113 IWARP_QP_IN_ERROR_BAD_CLOSE,
9114 IWARP_EXCEPTION_DETECTED_LLP_CLOSED,
9115 IWARP_EXCEPTION_DETECTED_LLP_RESET,
9116 IWARP_EXCEPTION_DETECTED_IRQ_FULL,
9117 IWARP_EXCEPTION_DETECTED_RQ_EMPTY,
9118 IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT,
9119 IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR,
9120 IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW,
9121 IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC,
9122 IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR,
9123 IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR,
9124 IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED,
9125 MAX_IWARP_FW_RETURN_CODE
9128 struct iwarp_init_func_params {
9133 struct iwarp_init_func_ramrod_data {
9134 struct rdma_init_func_ramrod_data rdma;
9135 struct tcp_init_params tcp;
9136 struct iwarp_init_func_params iwarp;
9139 enum iwarp_modify_qp_new_state_type {
9140 IWARP_MODIFY_QP_STATE_CLOSING = 1,
9141 IWARP_MODIFY_QP_STATE_ERROR =
9143 MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE
9146 struct iwarp_modify_qp_ramrod_data {
9147 __le16 transition_to_state;
9149 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9150 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0
9151 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9152 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1
9153 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9154 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2
9155 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1
9156 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3
9157 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
9158 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4
9159 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x7FF
9160 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 5
9161 __le32 reserved3[3];
9162 __le32 reserved4[8];
9165 struct mpa_rq_params {
9170 struct mpa_ulp_buffer {
9171 struct regpair addr;
9176 struct mpa_outgoing_params {
9180 struct mpa_rq_params out_rq;
9181 struct mpa_ulp_buffer outgoing_ulp_buffer;
9184 struct iwarp_mpa_offload_ramrod_data {
9185 struct mpa_outgoing_params common;
9188 u8 tcp_connect_side;
9190 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7
9191 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0
9192 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F
9193 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3
9195 struct mpa_ulp_buffer incoming_ulp_buffer;
9196 struct regpair async_eqe_output_buf;
9197 struct regpair handle_for_async;
9198 struct regpair shared_queue_addr;
9199 u8 stats_counter_id;
9203 struct iwarp_offload_params {
9204 struct mpa_ulp_buffer incoming_ulp_buffer;
9205 struct regpair async_eqe_output_buf;
9206 struct regpair handle_for_async;
9209 u8 stats_counter_id;
9214 struct iwarp_query_qp_output_params {
9216 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
9217 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
9218 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
9219 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
9223 struct iwarp_query_qp_ramrod_data {
9224 struct regpair output_params_addr;
9227 enum iwarp_ramrod_cmd_id {
9228 IWARP_RAMROD_CMD_ID_TCP_OFFLOAD =
9230 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD,
9231 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR,
9232 IWARP_RAMROD_CMD_ID_CREATE_QP,
9233 IWARP_RAMROD_CMD_ID_QUERY_QP,
9234 IWARP_RAMROD_CMD_ID_MODIFY_QP,
9235 IWARP_RAMROD_CMD_ID_DESTROY_QP,
9236 MAX_IWARP_RAMROD_CMD_ID
9239 struct iwarp_rxmit_stats_drv {
9240 struct regpair tx_go_to_slow_start_event_cnt;
9241 struct regpair tx_fast_retransmit_event_cnt;
9244 struct iwarp_tcp_offload_ramrod_data {
9245 struct iwarp_offload_params iwarp;
9246 struct tcp_offload_params_opt2 tcp;
9249 enum mpa_negotiation_mode {
9250 MPA_NEGOTIATION_TYPE_BASIC = 1,
9251 MPA_NEGOTIATION_TYPE_ENHANCED = 2,
9252 MAX_MPA_NEGOTIATION_MODE
9256 MPA_RTR_TYPE_NONE = 0,
9257 MPA_RTR_TYPE_ZERO_SEND = 1,
9258 MPA_RTR_TYPE_ZERO_WRITE = 2,
9259 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE = 3,
9260 MPA_RTR_TYPE_ZERO_READ = 4,
9261 MPA_RTR_TYPE_ZERO_SEND_AND_READ = 5,
9262 MPA_RTR_TYPE_ZERO_WRITE_AND_READ = 6,
9263 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ = 7,
9267 struct unaligned_opaque_data {
9268 __le16 first_mpa_offset;
9269 u8 tcp_payload_offset;
9271 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1
9272 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0
9273 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1
9274 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT 1
9275 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F
9276 #define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 2
9280 struct mstorm_iwarp_conn_ag_ctx {
9284 #define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9285 #define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9286 #define MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9287 #define MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
9288 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3
9289 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2
9290 #define MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9291 #define MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
9292 #define MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9293 #define MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
9295 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1
9296 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0
9297 #define MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9298 #define MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
9299 #define MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9300 #define MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
9301 #define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9302 #define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
9303 #define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9304 #define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
9305 #define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9306 #define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
9307 #define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1
9308 #define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6
9309 #define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9310 #define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
9317 struct ustorm_iwarp_conn_ag_ctx {
9321 #define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9322 #define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9323 #define USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9324 #define USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
9325 #define USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9326 #define USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
9327 #define USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9328 #define USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
9329 #define USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9330 #define USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
9332 #define USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3
9333 #define USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0
9334 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
9335 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
9336 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
9337 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
9338 #define USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
9339 #define USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6
9341 #define USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9342 #define USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
9343 #define USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9344 #define USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
9345 #define USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9346 #define USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
9347 #define USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1
9348 #define USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3
9349 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
9350 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
9351 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
9352 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
9353 #define USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
9354 #define USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6
9355 #define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
9356 #define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
9358 #define USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1
9359 #define USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0
9360 #define USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9361 #define USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
9362 #define USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9363 #define USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
9364 #define USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9365 #define USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
9366 #define USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
9367 #define USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
9368 #define USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
9369 #define USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5
9370 #define USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
9371 #define USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
9372 #define USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
9373 #define USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
9386 struct ystorm_iwarp_conn_ag_ctx {
9390 #define YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1
9391 #define YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0
9392 #define YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9393 #define YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
9394 #define YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9395 #define YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
9396 #define YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9397 #define YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
9398 #define YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9399 #define YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
9401 #define YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9402 #define YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
9403 #define YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9404 #define YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
9405 #define YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9406 #define YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
9407 #define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9408 #define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
9409 #define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9410 #define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
9411 #define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9412 #define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
9413 #define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9414 #define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6
9415 #define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9416 #define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
9430 struct ystorm_fcoe_conn_st_ctx {
9435 __le16 stat_ram_addr;
9437 __le16 max_fc_payload_len;
9438 __le16 tx_max_fc_pay_len;
9442 struct regpair reserved;
9443 __le16 min_frame_size;
9444 u8 protection_info_flags;
9445 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
9446 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0
9447 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
9448 #define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1
9449 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F
9450 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2
9451 u8 dst_protection_per_mss;
9452 u8 src_protection_per_mss;
9453 u8 ptu_log_page_size;
9455 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9456 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0
9457 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
9458 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1
9459 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F
9460 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2
9464 struct fcoe_vlan_fields {
9466 #define FCOE_VLAN_FIELDS_VID_MASK 0xFFF
9467 #define FCOE_VLAN_FIELDS_VID_SHIFT 0
9468 #define FCOE_VLAN_FIELDS_CLI_MASK 0x1
9469 #define FCOE_VLAN_FIELDS_CLI_SHIFT 12
9470 #define FCOE_VLAN_FIELDS_PRI_MASK 0x7
9471 #define FCOE_VLAN_FIELDS_PRI_SHIFT 13
9474 union fcoe_vlan_field_union {
9475 struct fcoe_vlan_fields fields;
9479 union fcoe_vlan_vif_field_union {
9480 union fcoe_vlan_field_union vlan;
9484 struct pstorm_fcoe_eth_context_section {
9497 union fcoe_vlan_vif_field_union vif_outer_vlan;
9498 __le16 vif_outer_eth_type;
9499 union fcoe_vlan_vif_field_union inner_vlan;
9500 __le16 inner_eth_type;
9503 struct pstorm_fcoe_conn_st_ctx {
9508 __le16 stat_ram_addr;
9510 struct regpair abts_cleanup_addr;
9511 struct pstorm_fcoe_eth_context_section eth;
9516 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1
9517 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0
9518 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1
9519 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1
9520 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9521 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2
9522 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
9523 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3
9524 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0xF
9525 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 4
9530 __le16 rec_rr_tov_val;
9531 u8 q_relative_offset;
9535 struct xstorm_fcoe_conn_st_ctx {
9539 u8 cached_wqes_avail;
9540 __le16 stat_ram_addr;
9542 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1
9543 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0
9544 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9545 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1
9546 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1
9547 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2
9548 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
9549 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3
9550 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7
9551 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5
9552 u8 cached_wqes_offset;
9557 __le16 num_pages_in_pbl;
9559 struct regpair sq_pbl_addr;
9560 struct regpair sq_curr_page_addr;
9561 struct regpair sq_next_page_addr;
9562 struct regpair xferq_pbl_addr;
9563 struct regpair xferq_curr_page_addr;
9564 struct regpair xferq_next_page_addr;
9565 struct regpair respq_pbl_addr;
9566 struct regpair respq_curr_page_addr;
9567 struct regpair respq_next_page_addr;
9569 __le16 tx_max_fc_pay_len;
9570 __le16 max_fc_payload_len;
9571 __le16 min_frame_size;
9572 __le16 sq_pbl_next_index;
9573 __le16 respq_pbl_next_index;
9574 u8 fcp_cmd_byte_credit;
9575 u8 fcp_rsp_byte_credit;
9576 __le16 protection_info;
9577 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1
9578 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0
9579 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
9580 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1
9581 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
9582 #define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2
9583 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1
9584 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3
9585 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF
9586 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4
9587 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF
9588 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8
9589 __le16 xferq_pbl_next_index;
9592 u8 fcp_xfer_byte_credit;
9594 struct fcoe_wqe cached_wqes[16];
9597 struct xstorm_fcoe_conn_ag_ctx {
9601 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9602 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9603 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1
9604 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1
9605 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1
9606 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2
9607 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
9608 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
9609 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1
9610 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4
9611 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1
9612 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5
9613 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1
9614 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6
9615 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1
9616 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7
9618 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1
9619 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0
9620 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1
9621 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1
9622 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1
9623 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2
9624 #define XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1
9625 #define XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3
9626 #define XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1
9627 #define XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4
9628 #define XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1
9629 #define XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5
9630 #define XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1
9631 #define XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6
9632 #define XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1
9633 #define XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7
9635 #define XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
9636 #define XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0
9637 #define XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
9638 #define XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2
9639 #define XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
9640 #define XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4
9641 #define XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
9642 #define XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6
9644 #define XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
9645 #define XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0
9646 #define XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
9647 #define XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2
9648 #define XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
9649 #define XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4
9650 #define XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
9651 #define XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6
9653 #define XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
9654 #define XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0
9655 #define XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
9656 #define XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2
9657 #define XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
9658 #define XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4
9659 #define XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
9660 #define XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6
9662 #define XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
9663 #define XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0
9664 #define XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
9665 #define XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2
9666 #define XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
9667 #define XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4
9668 #define XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
9669 #define XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6
9671 #define XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
9672 #define XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0
9673 #define XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
9674 #define XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2
9675 #define XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
9676 #define XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4
9677 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
9678 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6
9680 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
9681 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
9682 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
9683 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2
9684 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
9685 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
9686 #define XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
9687 #define XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6
9688 #define XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
9689 #define XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7
9691 #define XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
9692 #define XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0
9693 #define XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
9694 #define XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1
9695 #define XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
9696 #define XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2
9697 #define XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
9698 #define XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3
9699 #define XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
9700 #define XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4
9701 #define XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
9702 #define XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5
9703 #define XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
9704 #define XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6
9705 #define XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
9706 #define XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7
9708 #define XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
9709 #define XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
9710 #define XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1
9711 #define XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1
9712 #define XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1
9713 #define XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2
9714 #define XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1
9715 #define XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3
9716 #define XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1
9717 #define XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4
9718 #define XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1
9719 #define XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5
9720 #define XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1
9721 #define XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6
9722 #define XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1
9723 #define XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7
9725 #define XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1
9726 #define XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0
9727 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
9728 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1
9729 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
9730 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
9731 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1
9732 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3
9733 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
9734 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
9735 #define XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1
9736 #define XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5
9737 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1
9738 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6
9739 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1
9740 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7
9742 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1
9743 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0
9744 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1
9745 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1
9746 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1
9747 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2
9748 #define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
9749 #define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3
9750 #define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
9751 #define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4
9752 #define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
9753 #define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5
9754 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
9755 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
9756 #define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1
9757 #define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7
9759 #define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1
9760 #define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
9761 #define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1
9762 #define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1
9763 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
9764 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
9765 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
9766 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
9767 #define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1
9768 #define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4
9769 #define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1
9770 #define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5
9771 #define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1
9772 #define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6
9773 #define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1
9774 #define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7
9776 #define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1
9777 #define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
9778 #define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1
9779 #define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1
9780 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
9781 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
9782 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
9783 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
9784 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
9785 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
9786 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
9787 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
9788 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
9789 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
9790 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
9791 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
9793 #define XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1
9794 #define XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0
9795 #define XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1
9796 #define XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1
9797 #define XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1
9798 #define XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2
9799 #define XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1
9800 #define XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3
9801 #define XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1
9802 #define XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4
9803 #define XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1
9804 #define XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5
9805 #define XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
9806 #define XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6
9834 struct ustorm_fcoe_conn_st_ctx {
9835 struct regpair respq_pbl_addr;
9836 __le16 num_pages_in_pbl;
9837 u8 ptu_log_page_size;
9843 struct tstorm_fcoe_conn_ag_ctx {
9847 #define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9848 #define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9849 #define TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
9850 #define TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
9851 #define TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1
9852 #define TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2
9853 #define TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1
9854 #define TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3
9855 #define TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1
9856 #define TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4
9857 #define TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1
9858 #define TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5
9859 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
9860 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6
9862 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
9863 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0
9864 #define TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
9865 #define TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2
9866 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
9867 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
9868 #define TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
9869 #define TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6
9871 #define TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
9872 #define TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0
9873 #define TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
9874 #define TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2
9875 #define TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
9876 #define TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4
9877 #define TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
9878 #define TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6
9880 #define TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
9881 #define TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0
9882 #define TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
9883 #define TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2
9884 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1
9885 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4
9886 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
9887 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
9888 #define TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
9889 #define TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6
9890 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
9891 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
9893 #define TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
9894 #define TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0
9895 #define TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
9896 #define TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1
9897 #define TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
9898 #define TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2
9899 #define TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
9900 #define TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3
9901 #define TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
9902 #define TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4
9903 #define TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
9904 #define TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5
9905 #define TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
9906 #define TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6
9907 #define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
9908 #define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
9910 #define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
9911 #define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
9912 #define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
9913 #define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
9914 #define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
9915 #define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
9916 #define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
9917 #define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
9918 #define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
9919 #define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
9920 #define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
9921 #define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
9922 #define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
9923 #define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
9924 #define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
9925 #define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
9930 struct ustorm_fcoe_conn_ag_ctx {
9934 #define USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
9935 #define USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
9936 #define USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
9937 #define USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
9938 #define USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
9939 #define USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
9940 #define USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
9941 #define USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
9942 #define USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
9943 #define USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
9945 #define USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
9946 #define USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0
9947 #define USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
9948 #define USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2
9949 #define USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
9950 #define USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4
9951 #define USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
9952 #define USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6
9954 #define USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
9955 #define USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
9956 #define USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
9957 #define USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
9958 #define USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
9959 #define USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
9960 #define USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
9961 #define USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3
9962 #define USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
9963 #define USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4
9964 #define USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
9965 #define USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5
9966 #define USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
9967 #define USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6
9968 #define USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
9969 #define USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
9971 #define USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
9972 #define USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
9973 #define USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
9974 #define USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
9975 #define USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
9976 #define USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
9977 #define USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
9978 #define USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
9979 #define USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
9980 #define USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
9981 #define USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
9982 #define USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
9983 #define USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
9984 #define USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
9985 #define USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
9986 #define USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
9999 struct tstorm_fcoe_conn_st_ctx {
10000 __le16 stat_ram_addr;
10001 __le16 rx_max_fc_payload_len;
10002 __le16 e_d_tov_val;
10004 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1
10005 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0
10006 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1
10007 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1
10008 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F
10009 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2
10010 u8 timers_cleanup_invocation_cnt;
10011 __le32 reserved1[2];
10012 __le32 dst_mac_address_bytes0to3;
10013 __le16 dst_mac_address_bytes4to5;
10014 __le16 ramrod_echo;
10016 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3
10017 #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0
10018 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F
10019 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2
10020 u8 q_relative_offset;
10021 u8 bdq_resource_id;
10025 struct mstorm_fcoe_conn_ag_ctx {
10029 #define MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10030 #define MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10031 #define MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10032 #define MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
10033 #define MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10034 #define MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
10035 #define MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10036 #define MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
10037 #define MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10038 #define MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
10040 #define MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10041 #define MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10042 #define MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10043 #define MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
10044 #define MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10045 #define MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
10046 #define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10047 #define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
10048 #define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10049 #define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
10050 #define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10051 #define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
10052 #define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10053 #define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
10054 #define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10055 #define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
10062 struct fcoe_mstorm_fcoe_conn_st_ctx_fp {
10065 u8 protection_info;
10066 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1
10067 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
10068 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1
10069 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT 1
10070 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F
10071 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT 2
10072 u8 q_relative_offset;
10076 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp {
10078 __le16 stat_ram_addr;
10079 __le16 num_pages_in_pbl;
10080 u8 ptu_log_page_size;
10082 __le16 unsolicited_cq_count;
10084 u8 bdq_resource_id;
10086 struct regpair xferq_pbl_addr;
10087 struct regpair reserved1;
10088 struct regpair reserved2[3];
10091 struct mstorm_fcoe_conn_st_ctx {
10092 struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp;
10093 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp;
10096 struct fcoe_conn_context {
10097 struct ystorm_fcoe_conn_st_ctx ystorm_st_context;
10098 struct pstorm_fcoe_conn_st_ctx pstorm_st_context;
10099 struct regpair pstorm_st_padding[2];
10100 struct xstorm_fcoe_conn_st_ctx xstorm_st_context;
10101 struct xstorm_fcoe_conn_ag_ctx xstorm_ag_context;
10102 struct regpair xstorm_ag_padding[6];
10103 struct ustorm_fcoe_conn_st_ctx ustorm_st_context;
10104 struct regpair ustorm_st_padding[2];
10105 struct tstorm_fcoe_conn_ag_ctx tstorm_ag_context;
10106 struct regpair tstorm_ag_padding[2];
10107 struct timers_context timer_context;
10108 struct ustorm_fcoe_conn_ag_ctx ustorm_ag_context;
10109 struct tstorm_fcoe_conn_st_ctx tstorm_st_context;
10110 struct mstorm_fcoe_conn_ag_ctx mstorm_ag_context;
10111 struct mstorm_fcoe_conn_st_ctx mstorm_st_context;
10114 struct fcoe_conn_offload_ramrod_params {
10115 struct fcoe_conn_offload_ramrod_data offload_ramrod_data;
10118 struct fcoe_conn_terminate_ramrod_params {
10119 struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data;
10122 enum fcoe_event_type {
10123 FCOE_EVENT_INIT_FUNC,
10124 FCOE_EVENT_DESTROY_FUNC,
10125 FCOE_EVENT_STAT_FUNC,
10126 FCOE_EVENT_OFFLOAD_CONN,
10127 FCOE_EVENT_TERMINATE_CONN,
10129 MAX_FCOE_EVENT_TYPE
10132 struct fcoe_init_ramrod_params {
10133 struct fcoe_init_func_ramrod_data init_ramrod_data;
10136 enum fcoe_ramrod_cmd_id {
10137 FCOE_RAMROD_CMD_ID_INIT_FUNC,
10138 FCOE_RAMROD_CMD_ID_DESTROY_FUNC,
10139 FCOE_RAMROD_CMD_ID_STAT_FUNC,
10140 FCOE_RAMROD_CMD_ID_OFFLOAD_CONN,
10141 FCOE_RAMROD_CMD_ID_TERMINATE_CONN,
10142 MAX_FCOE_RAMROD_CMD_ID
10145 struct fcoe_stat_ramrod_params {
10146 struct fcoe_stat_ramrod_data stat_ramrod_data;
10149 struct ystorm_fcoe_conn_ag_ctx {
10153 #define YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10154 #define YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10155 #define YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10156 #define YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
10157 #define YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10158 #define YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
10159 #define YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10160 #define YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
10161 #define YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10162 #define YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
10164 #define YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10165 #define YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10166 #define YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10167 #define YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
10168 #define YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10169 #define YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
10170 #define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10171 #define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
10172 #define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10173 #define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
10174 #define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10175 #define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
10176 #define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10177 #define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
10178 #define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10179 #define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
10193 struct ystorm_iscsi_conn_st_ctx {
10194 __le32 reserved[4];
10197 struct pstorm_iscsi_tcp_conn_st_ctx {
10202 struct xstorm_iscsi_tcp_conn_st_ctx {
10203 __le32 reserved_iscsi[40];
10204 __le32 reserved_tcp[4];
10207 struct xstorm_iscsi_conn_ag_ctx {
10211 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10212 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10213 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
10214 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
10215 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1
10216 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2
10217 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
10218 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
10219 #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
10220 #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
10221 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1
10222 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5
10223 #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1
10224 #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6
10225 #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1
10226 #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7
10228 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1
10229 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0
10230 #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1
10231 #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1
10232 #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1
10233 #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2
10234 #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1
10235 #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3
10236 #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1
10237 #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4
10238 #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1
10239 #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5
10240 #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1
10241 #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6
10242 #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1
10243 #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7
10245 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10246 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0
10247 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10248 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2
10249 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10250 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4
10251 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10252 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
10254 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10255 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0
10256 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10257 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2
10258 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10259 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4
10260 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10261 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6
10263 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10264 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0
10265 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
10266 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2
10267 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
10268 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4
10269 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
10270 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6
10272 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
10273 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0
10274 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
10275 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2
10276 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
10277 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4
10278 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
10279 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6
10281 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
10282 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0
10283 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
10284 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2
10285 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
10286 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4
10287 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
10288 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
10290 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3
10291 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0
10292 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3
10293 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2
10294 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
10295 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4
10296 #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10297 #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6
10298 #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10299 #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7
10301 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10302 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0
10303 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
10304 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
10305 #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10306 #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2
10307 #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10308 #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3
10309 #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10310 #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4
10311 #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
10312 #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5
10313 #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
10314 #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6
10315 #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1
10316 #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7
10318 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
10319 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0
10320 #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1
10321 #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1
10322 #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1
10323 #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2
10324 #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1
10325 #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3
10326 #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1
10327 #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4
10328 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1
10329 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5
10330 #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1
10331 #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6
10332 #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1
10333 #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7
10335 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1
10336 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0
10337 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
10338 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
10339 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1
10340 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2
10341 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1
10342 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3
10343 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
10344 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
10345 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1
10346 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5
10347 #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10348 #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6
10349 #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1
10350 #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7
10352 #define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
10353 #define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
10354 #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10355 #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1
10356 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1
10357 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2
10358 #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10359 #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3
10360 #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10361 #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4
10362 #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10363 #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5
10364 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
10365 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
10366 #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1
10367 #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7
10369 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1
10370 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0
10371 #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1
10372 #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1
10373 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
10374 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
10375 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
10376 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
10377 #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1
10378 #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4
10379 #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1
10380 #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5
10381 #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1
10382 #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6
10383 #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1
10384 #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7
10386 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1
10387 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0
10388 #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1
10389 #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1
10390 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
10391 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
10392 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
10393 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
10394 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
10395 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
10396 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
10397 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
10398 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
10399 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
10400 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
10401 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
10403 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1
10404 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0
10405 #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1
10406 #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1
10407 #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1
10408 #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2
10409 #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1
10410 #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3
10411 #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1
10412 #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4
10413 #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1
10414 #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5
10415 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
10416 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6
10418 __le16 physical_q0;
10419 __le16 physical_q1;
10420 __le16 dummy_dorq_var;
10424 __le16 slow_io_total_data_tx_update;
10432 __le32 more_to_send_seq;
10435 __le32 hq_scan_next_relevant_ack;
10441 __le32 bytes_to_next_pdu;
10456 __le32 exp_stat_sn;
10457 __le32 ongoing_fast_rxmit_seq;
10464 struct tstorm_iscsi_conn_ag_ctx {
10468 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10469 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10470 #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10471 #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
10472 #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1
10473 #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2
10474 #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1
10475 #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3
10476 #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
10477 #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
10478 #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1
10479 #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5
10480 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10481 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6
10483 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3
10484 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0
10485 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3
10486 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2
10487 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10488 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
10489 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10490 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6
10492 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10493 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0
10494 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10495 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2
10496 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10497 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4
10498 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10499 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6
10501 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
10502 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
10503 #define TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
10504 #define TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 2
10505 #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10506 #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4
10507 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1
10508 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5
10509 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1
10510 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6
10511 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
10512 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
10514 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10515 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0
10516 #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10517 #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1
10518 #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10519 #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2
10520 #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
10521 #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3
10522 #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
10523 #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4
10524 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
10525 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
10526 #define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
10527 #define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 6
10528 #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10529 #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
10531 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10532 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
10533 #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10534 #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
10535 #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10536 #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
10537 #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10538 #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
10539 #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10540 #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
10541 #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10542 #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
10543 #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10544 #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
10545 #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
10546 #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
10556 u8 cid_offload_cnt;
10561 struct ustorm_iscsi_conn_ag_ctx {
10565 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10566 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
10567 #define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10568 #define USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
10569 #define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10570 #define USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
10571 #define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10572 #define USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
10573 #define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10574 #define USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
10576 #define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
10577 #define USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0
10578 #define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10579 #define USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2
10580 #define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10581 #define USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4
10582 #define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10583 #define USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6
10585 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10586 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
10587 #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10588 #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
10589 #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10590 #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
10591 #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1
10592 #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3
10593 #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10594 #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4
10595 #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10596 #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5
10597 #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10598 #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6
10599 #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10600 #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
10602 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10603 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
10604 #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10605 #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
10606 #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10607 #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
10608 #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10609 #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
10610 #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10611 #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
10612 #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10613 #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
10614 #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10615 #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
10616 #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
10617 #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
10630 struct tstorm_iscsi_conn_st_ctx {
10631 __le32 reserved[40];
10634 struct mstorm_iscsi_conn_ag_ctx {
10638 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10639 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
10640 #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10641 #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
10642 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10643 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
10644 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10645 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
10646 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10647 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
10649 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10650 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
10651 #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10652 #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
10653 #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10654 #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
10655 #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10656 #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
10657 #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10658 #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
10659 #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10660 #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
10661 #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10662 #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
10663 #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10664 #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
10671 struct mstorm_iscsi_tcp_conn_st_ctx {
10672 __le32 reserved_tcp[20];
10673 __le32 reserved_iscsi[8];
10676 struct ustorm_iscsi_conn_st_ctx {
10677 __le32 reserved[52];
10680 struct iscsi_conn_context {
10681 struct ystorm_iscsi_conn_st_ctx ystorm_st_context;
10682 struct regpair ystorm_st_padding[2];
10683 struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context;
10684 struct regpair pstorm_st_padding[2];
10685 struct pb_context xpb2_context;
10686 struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context;
10687 struct regpair xstorm_st_padding[2];
10688 struct xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
10689 struct tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
10690 struct regpair tstorm_ag_padding[2];
10691 struct timers_context timer_context;
10692 struct ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
10693 struct pb_context upb_context;
10694 struct tstorm_iscsi_conn_st_ctx tstorm_st_context;
10695 struct regpair tstorm_st_padding[2];
10696 struct mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
10697 struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context;
10698 struct ustorm_iscsi_conn_st_ctx ustorm_st_context;
10701 struct iscsi_init_ramrod_params {
10702 struct iscsi_spe_func_init iscsi_init_spe;
10703 struct tcp_init_params tcp_init;
10706 struct ystorm_iscsi_conn_ag_ctx {
10710 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10711 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
10712 #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10713 #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
10714 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10715 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
10716 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10717 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
10718 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10719 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
10721 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10722 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
10723 #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10724 #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
10725 #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10726 #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
10727 #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10728 #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
10729 #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10730 #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
10731 #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10732 #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
10733 #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10734 #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
10735 #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10736 #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
10750 #define MFW_TRACE_SIGNATURE 0x25071946
10752 /* The trace in the buffer */
10753 #define MFW_TRACE_EVENTID_MASK 0x00ffff
10754 #define MFW_TRACE_PRM_SIZE_MASK 0x0f0000
10755 #define MFW_TRACE_PRM_SIZE_SHIFT 16
10756 #define MFW_TRACE_ENTRY_SIZE 3
10759 u32 signature; /* Help to identify that the trace is valid */
10760 u32 size; /* the size of the trace buffer in bytes */
10761 u32 curr_level; /* 2 - all will be written to the buffer
10762 * 1 - debug trace will not be written
10763 * 0 - just errors will be written to the buffer
10765 u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means
10769 /* Warning: the following pointers are assumed to be 32bits as they are
10770 * used only in the MFW.
10772 u32 trace_prod; /* The next trace will be written to this offset */
10773 u32 trace_oldest; /* The oldest valid trace starts at this offset
10774 * (usually very close after the current producer).
10778 #define VF_MAX_STATIC 192
10780 #define MCP_GLOB_PATH_MAX 2
10781 #define MCP_PORT_MAX 2
10782 #define MCP_GLOB_PORT_MAX 4
10783 #define MCP_GLOB_FUNC_MAX 16
10785 typedef u32 offsize_t; /* In DWORDS !!! */
10786 /* Offset from the beginning of the MCP scratchpad */
10787 #define OFFSIZE_OFFSET_SHIFT 0
10788 #define OFFSIZE_OFFSET_MASK 0x0000ffff
10789 /* Size of specific element (not the whole array if any) */
10790 #define OFFSIZE_SIZE_SHIFT 16
10791 #define OFFSIZE_SIZE_MASK 0xffff0000
10793 #define SECTION_OFFSET(_offsize) ((((_offsize & \
10794 OFFSIZE_OFFSET_MASK) >> \
10795 OFFSIZE_OFFSET_SHIFT) << 2))
10797 #define QED_SECTION_SIZE(_offsize) (((_offsize & \
10798 OFFSIZE_SIZE_MASK) >> \
10799 OFFSIZE_SIZE_SHIFT) << 2)
10801 #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + \
10802 SECTION_OFFSET(_offsize) + \
10803 (QED_SECTION_SIZE(_offsize) * idx))
10805 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \
10806 (_pub_base + offsetof(struct mcp_public_data, sections[_section]))
10808 /* PHY configuration */
10809 struct eth_phy_cfg {
10811 #define ETH_SPEED_AUTONEG 0
10812 #define ETH_SPEED_SMARTLINQ 0x8
10815 #define ETH_PAUSE_NONE 0x0
10816 #define ETH_PAUSE_AUTONEG 0x1
10817 #define ETH_PAUSE_RX 0x2
10818 #define ETH_PAUSE_TX 0x4
10822 #define ETH_LOOPBACK_NONE (0)
10823 #define ETH_LOOPBACK_INT_PHY (1)
10824 #define ETH_LOOPBACK_EXT_PHY (2)
10825 #define ETH_LOOPBACK_EXT (3)
10826 #define ETH_LOOPBACK_MAC (4)
10829 #define EEE_CFG_EEE_ENABLED BIT(0)
10830 #define EEE_CFG_TX_LPI BIT(1)
10831 #define EEE_CFG_ADV_SPEED_1G BIT(2)
10832 #define EEE_CFG_ADV_SPEED_10G BIT(3)
10833 #define EEE_TX_TIMER_USEC_MASK (0xfffffff0)
10834 #define EEE_TX_TIMER_USEC_OFFSET 4
10835 #define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00)
10836 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100)
10837 #define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000)
10839 u32 feature_config_flags;
10840 #define ETH_EEE_MODE_ADV_LPI (1 << 0)
10843 struct port_mf_cfg {
10845 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
10846 #define PORT_MF_CFG_OV_TAG_SHIFT 0
10847 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
10936 u64 brb_truncate[8];
10937 u64 brb_discard[8];
10940 struct port_stats {
10941 struct brb_stats brb;
10942 struct eth_stats eth;
10945 struct couple_mode_teaming {
10946 u8 port_cmt[MCP_GLOB_PORT_MAX];
10947 #define PORT_CMT_IN_TEAM (1 << 0)
10949 #define PORT_CMT_PORT_ROLE (1 << 1)
10950 #define PORT_CMT_PORT_INACTIVE (0 << 1)
10951 #define PORT_CMT_PORT_ACTIVE (1 << 1)
10953 #define PORT_CMT_TEAM_MASK (1 << 2)
10954 #define PORT_CMT_TEAM0 (0 << 2)
10955 #define PORT_CMT_TEAM1 (1 << 2)
10958 #define LLDP_CHASSIS_ID_STAT_LEN 4
10959 #define LLDP_PORT_ID_STAT_LEN 4
10960 #define DCBX_MAX_APP_PROTOCOL 32
10961 #define MAX_SYSTEM_LLDP_TLV_DATA 32
10964 LLDP_NEAREST_BRIDGE = 0,
10965 LLDP_NEAREST_NON_TPMR_BRIDGE,
10966 LLDP_NEAREST_CUSTOMER_BRIDGE,
10967 LLDP_MAX_LLDP_AGENTS
10970 struct lldp_config_params_s {
10972 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
10973 #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0
10974 #define LLDP_CONFIG_HOLD_MASK 0x00000f00
10975 #define LLDP_CONFIG_HOLD_SHIFT 8
10976 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
10977 #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12
10978 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
10979 #define LLDP_CONFIG_ENABLE_RX_SHIFT 30
10980 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
10981 #define LLDP_CONFIG_ENABLE_TX_SHIFT 31
10982 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
10983 u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
10986 struct lldp_status_params_s {
10987 u32 prefix_seq_num;
10989 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
10990 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
10991 u32 suffix_seq_num;
10994 struct dcbx_ets_feature {
10996 #define DCBX_ETS_ENABLED_MASK 0x00000001
10997 #define DCBX_ETS_ENABLED_SHIFT 0
10998 #define DCBX_ETS_WILLING_MASK 0x00000002
10999 #define DCBX_ETS_WILLING_SHIFT 1
11000 #define DCBX_ETS_ERROR_MASK 0x00000004
11001 #define DCBX_ETS_ERROR_SHIFT 2
11002 #define DCBX_ETS_CBS_MASK 0x00000008
11003 #define DCBX_ETS_CBS_SHIFT 3
11004 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0
11005 #define DCBX_ETS_MAX_TCS_SHIFT 4
11006 #define DCBX_OOO_TC_MASK 0x00000f00
11007 #define DCBX_OOO_TC_SHIFT 8
11009 #define DCBX_TCP_OOO_TC (4)
11011 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1)
11012 #define DCBX_CEE_STRICT_PRIORITY 0xf
11015 #define DCBX_ETS_TSA_STRICT 0
11016 #define DCBX_ETS_TSA_CBS 1
11017 #define DCBX_ETS_TSA_ETS 2
11020 #define DCBX_TCP_OOO_TC (4)
11021 #define DCBX_TCP_OOO_K2_4PORT_TC (3)
11023 struct dcbx_app_priority_entry {
11025 #define DCBX_APP_PRI_MAP_MASK 0x000000ff
11026 #define DCBX_APP_PRI_MAP_SHIFT 0
11027 #define DCBX_APP_PRI_0 0x01
11028 #define DCBX_APP_PRI_1 0x02
11029 #define DCBX_APP_PRI_2 0x04
11030 #define DCBX_APP_PRI_3 0x08
11031 #define DCBX_APP_PRI_4 0x10
11032 #define DCBX_APP_PRI_5 0x20
11033 #define DCBX_APP_PRI_6 0x40
11034 #define DCBX_APP_PRI_7 0x80
11035 #define DCBX_APP_SF_MASK 0x00000300
11036 #define DCBX_APP_SF_SHIFT 8
11037 #define DCBX_APP_SF_ETHTYPE 0
11038 #define DCBX_APP_SF_PORT 1
11039 #define DCBX_APP_SF_IEEE_MASK 0x0000f000
11040 #define DCBX_APP_SF_IEEE_SHIFT 12
11041 #define DCBX_APP_SF_IEEE_RESERVED 0
11042 #define DCBX_APP_SF_IEEE_ETHTYPE 1
11043 #define DCBX_APP_SF_IEEE_TCP_PORT 2
11044 #define DCBX_APP_SF_IEEE_UDP_PORT 3
11045 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4
11047 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
11048 #define DCBX_APP_PROTOCOL_ID_SHIFT 16
11051 struct dcbx_app_priority_feature {
11053 #define DCBX_APP_ENABLED_MASK 0x00000001
11054 #define DCBX_APP_ENABLED_SHIFT 0
11055 #define DCBX_APP_WILLING_MASK 0x00000002
11056 #define DCBX_APP_WILLING_SHIFT 1
11057 #define DCBX_APP_ERROR_MASK 0x00000004
11058 #define DCBX_APP_ERROR_SHIFT 2
11059 #define DCBX_APP_MAX_TCS_MASK 0x0000f000
11060 #define DCBX_APP_MAX_TCS_SHIFT 12
11061 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
11062 #define DCBX_APP_NUM_ENTRIES_SHIFT 16
11063 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
11066 struct dcbx_features {
11067 struct dcbx_ets_feature ets;
11069 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
11070 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0
11071 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
11072 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
11073 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
11074 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
11075 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
11076 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
11077 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
11078 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
11080 #define DCBX_PFC_FLAGS_MASK 0x0000ff00
11081 #define DCBX_PFC_FLAGS_SHIFT 8
11082 #define DCBX_PFC_CAPS_MASK 0x00000f00
11083 #define DCBX_PFC_CAPS_SHIFT 8
11084 #define DCBX_PFC_MBC_MASK 0x00004000
11085 #define DCBX_PFC_MBC_SHIFT 14
11086 #define DCBX_PFC_WILLING_MASK 0x00008000
11087 #define DCBX_PFC_WILLING_SHIFT 15
11088 #define DCBX_PFC_ENABLED_MASK 0x00010000
11089 #define DCBX_PFC_ENABLED_SHIFT 16
11090 #define DCBX_PFC_ERROR_MASK 0x00020000
11091 #define DCBX_PFC_ERROR_SHIFT 17
11093 struct dcbx_app_priority_feature app;
11096 struct dcbx_local_params {
11098 #define DCBX_CONFIG_VERSION_MASK 0x00000007
11099 #define DCBX_CONFIG_VERSION_SHIFT 0
11100 #define DCBX_CONFIG_VERSION_DISABLED 0
11101 #define DCBX_CONFIG_VERSION_IEEE 1
11102 #define DCBX_CONFIG_VERSION_CEE 2
11103 #define DCBX_CONFIG_VERSION_STATIC 4
11106 struct dcbx_features features;
11110 u32 prefix_seq_num;
11112 struct dcbx_features features;
11113 u32 suffix_seq_num;
11116 struct lldp_system_tlvs_buffer_s {
11119 u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
11122 struct dcb_dscp_map {
11124 #define DCB_DSCP_ENABLE_MASK 0x1
11125 #define DCB_DSCP_ENABLE_SHIFT 0
11126 #define DCB_DSCP_ENABLE 1
11127 u32 dscp_pri_map[8];
11130 struct public_global {
11137 u32 debug_mb_offset;
11138 u32 phymod_dbg_mb_offset;
11139 struct couple_mode_teaming cmt;
11140 s32 internal_temperature;
11142 u32 running_bundle_id;
11143 s32 external_temperature;
11153 struct public_path {
11154 struct fw_flr_mb flr_mb;
11155 u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
11158 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff
11159 #define PROCESS_KILL_COUNTER_SHIFT 0
11160 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
11161 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
11162 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
11165 struct public_port {
11169 #define LINK_STATUS_LINK_UP 0x00000001
11170 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
11171 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1)
11172 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
11173 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
11174 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
11175 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
11176 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
11177 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
11178 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
11180 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
11182 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
11183 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
11185 #define LINK_STATUS_PFC_ENABLED 0x00000100
11186 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
11187 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
11188 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
11189 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
11190 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
11191 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
11192 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
11193 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
11195 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
11196 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
11197 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18)
11198 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
11199 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
11201 #define LINK_STATUS_SFP_TX_FAULT 0x00100000
11202 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
11203 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
11204 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000
11205 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000
11206 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000
11207 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000
11210 u32 ext_phy_fw_version;
11211 u32 drv_phy_cfg_addr;
11215 u32 stat_nig_timer;
11217 struct port_mf_cfg port_mf_config;
11218 struct port_stats stats;
11221 #define MEDIA_UNSPECIFIED 0x0
11222 #define MEDIA_SFPP_10G_FIBER 0x1
11223 #define MEDIA_XFP_FIBER 0x2
11224 #define MEDIA_DA_TWINAX 0x3
11225 #define MEDIA_BASE_T 0x4
11226 #define MEDIA_SFP_1G_FIBER 0x5
11227 #define MEDIA_MODULE_FIBER 0x6
11228 #define MEDIA_KR 0xf0
11229 #define MEDIA_NOT_PRESENT 0xff
11232 u32 link_change_count;
11234 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];
11235 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
11236 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
11238 /* DCBX related MIB */
11239 struct dcbx_local_params local_admin_dcbx_mib;
11240 struct dcbx_mib remote_dcbx_mib;
11241 struct dcbx_mib operational_dcbx_mib;
11244 u32 transceiver_data;
11245 #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF
11246 #define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000
11247 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
11248 #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001
11249 #define ETH_TRANSCEIVER_STATE_VALID 0x00000003
11250 #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008
11254 u32 wol_pkt_details;
11255 struct dcb_dscp_map dcb_dscp_map;
11258 #define EEE_ACTIVE_BIT BIT(0)
11259 #define EEE_LD_ADV_STATUS_MASK 0x000000f0
11260 #define EEE_LD_ADV_STATUS_OFFSET 4
11261 #define EEE_1G_ADV BIT(1)
11262 #define EEE_10G_ADV BIT(2)
11263 #define EEE_LP_ADV_STATUS_MASK 0x00000f00
11264 #define EEE_LP_ADV_STATUS_OFFSET 8
11265 #define EEE_SUPPORTED_SPEED_MASK 0x0000f000
11266 #define EEE_SUPPORTED_SPEED_OFFSET 12
11267 #define EEE_1G_SUPPORTED BIT(1)
11268 #define EEE_10G_SUPPORTED BIT(2)
11271 #define EEE_REMOTE_TW_TX_MASK 0x0000ffff
11272 #define EEE_REMOTE_TW_TX_OFFSET 0
11273 #define EEE_REMOTE_TW_RX_MASK 0xffff0000
11274 #define EEE_REMOTE_TW_RX_OFFSET 16
11277 struct public_func {
11285 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
11286 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
11287 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
11289 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
11290 #define FUNC_MF_CFG_PROTOCOL_SHIFT 4
11291 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
11292 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
11293 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
11294 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
11295 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
11297 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
11298 #define FUNC_MF_CFG_MIN_BW_SHIFT 8
11299 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
11300 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
11301 #define FUNC_MF_CFG_MAX_BW_SHIFT 16
11302 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
11305 #define FUNC_STATUS_VLINK_DOWN 0x00000001
11308 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
11309 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
11310 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
11312 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
11314 u32 fcoe_wwn_port_name_upper;
11315 u32 fcoe_wwn_port_name_lower;
11317 u32 fcoe_wwn_node_name_upper;
11318 u32 fcoe_wwn_node_name_lower;
11321 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
11322 #define FUNC_MF_CFG_OV_STAG_SHIFT 0
11323 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
11329 u32 driver_last_activity_ts;
11331 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];
11334 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
11335 #define DRV_ID_PDA_COMP_VER_SHIFT 0
11337 #define LOAD_REQ_HSI_VERSION 2
11338 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
11339 #define DRV_ID_MCP_HSI_VER_SHIFT 16
11340 #define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << \
11341 DRV_ID_MCP_HSI_VER_SHIFT)
11343 #define DRV_ID_DRV_TYPE_MASK 0x7f000000
11344 #define DRV_ID_DRV_TYPE_SHIFT 24
11345 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
11346 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT)
11348 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000
11349 #define DRV_ID_DRV_INIT_HW_SHIFT 31
11350 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT)
11363 struct mcp_file_att {
11364 u32 nvm_start_addr;
11368 struct bist_nvm_image_att {
11371 u32 nvm_start_addr;
11375 #define MCP_DRV_VER_STR_SIZE 16
11376 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
11377 #define MCP_DRV_NVM_BUF_LEN 32
11378 struct drv_version_stc {
11380 u8 name[MCP_DRV_VER_STR_SIZE - 4];
11383 struct lan_stats_stc {
11390 struct fcoe_stats_stc {
11397 struct ocbb_data_stc {
11398 u32 ocbb_host_addr;
11399 u32 ocsd_host_addr;
11400 u32 ocsd_req_update_interval;
11403 #define MAX_NUM_OF_SENSORS 7
11404 struct temperature_status_stc {
11405 u32 num_of_sensors;
11406 u32 sensor[MAX_NUM_OF_SENSORS];
11409 /* crash dump configuration header */
11410 struct mdump_config_stc {
11418 enum resource_id_enum {
11419 RESOURCE_NUM_SB_E = 0,
11420 RESOURCE_NUM_L2_QUEUE_E = 1,
11421 RESOURCE_NUM_VPORT_E = 2,
11422 RESOURCE_NUM_VMQ_E = 3,
11423 RESOURCE_FACTOR_NUM_RSS_PF_E = 4,
11424 RESOURCE_FACTOR_RSS_PER_VF_E = 5,
11425 RESOURCE_NUM_RL_E = 6,
11426 RESOURCE_NUM_PQ_E = 7,
11427 RESOURCE_NUM_VF_E = 8,
11428 RESOURCE_VFC_FILTER_E = 9,
11429 RESOURCE_ILT_E = 10,
11430 RESOURCE_CQS_E = 11,
11431 RESOURCE_GFT_PROFILES_E = 12,
11432 RESOURCE_NUM_TC_E = 13,
11433 RESOURCE_NUM_RSS_ENGINES_E = 14,
11434 RESOURCE_LL2_QUEUE_E = 15,
11435 RESOURCE_RDMA_STATS_QUEUE_E = 16,
11436 RESOURCE_BDQ_E = 17,
11438 RESOURCE_NUM_INVALID = 0xFFFFFFFF
11441 /* Resource ID is to be filled by the driver in the MB request
11442 * Size, offset & flags to be filled by the MFW in the MB response
11444 struct resource_info {
11445 enum resource_id_enum res_id;
11446 u32 size; /* number of allocated resources */
11447 u32 offset; /* Offset of the 1st resource */
11451 #define RESOURCE_ELEMENT_STRICT (1 << 0)
11454 #define DRV_ROLE_NONE 0
11455 #define DRV_ROLE_PREBOOT 1
11456 #define DRV_ROLE_OS 2
11457 #define DRV_ROLE_KDUMP 3
11459 struct load_req_stc {
11464 #define LOAD_REQ_ROLE_MASK 0x000000FF
11465 #define LOAD_REQ_ROLE_SHIFT 0
11466 #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00
11467 #define LOAD_REQ_LOCK_TO_SHIFT 8
11468 #define LOAD_REQ_LOCK_TO_DEFAULT 0
11469 #define LOAD_REQ_LOCK_TO_NONE 255
11470 #define LOAD_REQ_FORCE_MASK 0x000F0000
11471 #define LOAD_REQ_FORCE_SHIFT 16
11472 #define LOAD_REQ_FORCE_NONE 0
11473 #define LOAD_REQ_FORCE_PF 1
11474 #define LOAD_REQ_FORCE_ALL 2
11475 #define LOAD_REQ_FLAGS0_MASK 0x00F00000
11476 #define LOAD_REQ_FLAGS0_SHIFT 20
11477 #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0)
11480 struct load_rsp_stc {
11485 #define LOAD_RSP_ROLE_MASK 0x000000FF
11486 #define LOAD_RSP_ROLE_SHIFT 0
11487 #define LOAD_RSP_HSI_MASK 0x0000FF00
11488 #define LOAD_RSP_HSI_SHIFT 8
11489 #define LOAD_RSP_FLAGS0_MASK 0x000F0000
11490 #define LOAD_RSP_FLAGS0_SHIFT 16
11491 #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0)
11494 union drv_union_data {
11495 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
11496 struct mcp_mac wol_mac;
11498 struct eth_phy_cfg drv_phy_cfg;
11500 struct mcp_val64 val64;
11502 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
11504 struct mcp_file_att file_att;
11506 u32 ack_vf_disabled[VF_MAX_STATIC / 32];
11508 struct drv_version_stc drv_version;
11510 struct lan_stats_stc lan_stats;
11511 struct fcoe_stats_stc fcoe_stats;
11512 struct ocbb_data_stc ocbb_info;
11513 struct temperature_status_stc temp_info;
11514 struct resource_info resource;
11515 struct bist_nvm_image_att nvm_image_att;
11516 struct mdump_config_stc mdump_config;
11519 struct public_drv_mb {
11521 #define DRV_MSG_CODE_MASK 0xffff0000
11522 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
11523 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
11524 #define DRV_MSG_CODE_INIT_HW 0x12000000
11525 #define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000
11526 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
11527 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
11528 #define DRV_MSG_CODE_INIT_PHY 0x22000000
11529 #define DRV_MSG_CODE_LINK_RESET 0x23000000
11530 #define DRV_MSG_CODE_SET_DCBX 0x25000000
11531 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000
11532 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000
11533 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000
11534 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000
11535 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000
11536 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
11537 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000
11538 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000
11539 #define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000
11540 #define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000
11541 #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000
11543 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
11544 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000
11545 #define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000
11546 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000
11547 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
11548 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
11549 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000
11550 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
11551 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
11552 #define DRV_MSG_CODE_MCP_RESET 0x00090000
11553 #define DRV_MSG_CODE_SET_VERSION 0x000f0000
11554 #define DRV_MSG_CODE_MCP_HALT 0x00100000
11555 #define DRV_MSG_CODE_SET_VMAC 0x00110000
11556 #define DRV_MSG_CODE_GET_VMAC 0x00120000
11557 #define DRV_MSG_CODE_VMAC_TYPE_SHIFT 4
11558 #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30
11559 #define DRV_MSG_CODE_VMAC_TYPE_MAC 1
11560 #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2
11561 #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3
11563 #define DRV_MSG_CODE_GET_STATS 0x00130000
11564 #define DRV_MSG_CODE_STATS_TYPE_LAN 1
11565 #define DRV_MSG_CODE_STATS_TYPE_FCOE 2
11566 #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3
11567 #define DRV_MSG_CODE_STATS_TYPE_RDMA 4
11569 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000
11571 #define DRV_MSG_CODE_BIST_TEST 0x001e0000
11572 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000
11573 #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000
11575 #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F
11576 #define RESOURCE_CMD_REQ_RESC_SHIFT 0
11577 #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0
11578 #define RESOURCE_CMD_REQ_OPCODE_SHIFT 5
11579 #define RESOURCE_OPCODE_REQ 1
11580 #define RESOURCE_OPCODE_REQ_WO_AGING 2
11581 #define RESOURCE_OPCODE_REQ_W_AGING 3
11582 #define RESOURCE_OPCODE_RELEASE 4
11583 #define RESOURCE_OPCODE_FORCE_RELEASE 5
11584 #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00
11585 #define RESOURCE_CMD_REQ_AGE_SHIFT 8
11587 #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF
11588 #define RESOURCE_CMD_RSP_OWNER_SHIFT 0
11589 #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700
11590 #define RESOURCE_CMD_RSP_OPCODE_SHIFT 8
11591 #define RESOURCE_OPCODE_GNT 1
11592 #define RESOURCE_OPCODE_BUSY 2
11593 #define RESOURCE_OPCODE_RELEASED 3
11594 #define RESOURCE_OPCODE_RELEASED_PREVIOUS 4
11595 #define RESOURCE_OPCODE_WRONG_OWNER 5
11596 #define RESOURCE_OPCODE_UNKNOWN_CMD 255
11598 #define RESOURCE_DUMP 0
11600 #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000
11601 #define DRV_MSG_CODE_OS_WOL 0x002e0000
11603 #define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000
11604 #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000
11606 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
11609 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
11610 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
11611 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
11612 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
11613 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x000000FF
11614 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
11616 #define DRV_MB_PARAM_NVM_LEN_SHIFT 24
11618 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
11619 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
11620 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8
11621 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
11622 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
11623 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
11625 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0
11626 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F
11627 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0
11628 #define DRV_MB_PARAM_OV_CURR_CFG_OS 1
11629 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2
11630 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3
11632 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0
11633 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF
11634 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
11635 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
11636 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
11637 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF
11639 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0
11640 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF
11641 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1
11642 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2
11643 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3
11644 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4
11645 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5
11647 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0
11648 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF
11650 #define DRV_MB_PARAM_WOL_MASK (DRV_MB_PARAM_WOL_DEFAULT | \
11651 DRV_MB_PARAM_WOL_DISABLED | \
11652 DRV_MB_PARAM_WOL_ENABLED)
11653 #define DRV_MB_PARAM_WOL_DEFAULT DRV_MB_PARAM_UNLOAD_WOL_MCP
11654 #define DRV_MB_PARAM_WOL_DISABLED DRV_MB_PARAM_UNLOAD_WOL_DISABLED
11655 #define DRV_MB_PARAM_WOL_ENABLED DRV_MB_PARAM_UNLOAD_WOL_ENABLED
11657 #define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE | \
11658 DRV_MB_PARAM_ESWITCH_MODE_VEB | \
11659 DRV_MB_PARAM_ESWITCH_MODE_VEPA)
11660 #define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0
11661 #define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1
11662 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2
11664 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
11665 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
11666 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
11668 /* Resource Allocation params - Driver version support */
11669 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
11670 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
11671 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
11672 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
11674 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1
11675 #define DRV_MB_PARAM_BIST_CLOCK_TEST 2
11676 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3
11677 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4
11679 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
11680 #define DRV_MB_PARAM_BIST_RC_PASSED 1
11681 #define DRV_MB_PARAM_BIST_RC_FAILED 2
11682 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
11684 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
11685 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
11686 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8
11687 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00
11689 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF
11690 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0
11691 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002
11694 #define FW_MSG_CODE_MASK 0xffff0000
11695 #define FW_MSG_CODE_UNSUPPORTED 0x00000000
11696 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
11697 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
11698 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
11699 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
11700 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000
11701 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
11702 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000
11703 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000
11704 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000
11705 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
11706 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
11707 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
11708 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
11709 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
11710 #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000
11711 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000
11712 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000
11713 #define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE 0x3b000000
11714 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
11716 #define FW_MSG_CODE_NVM_OK 0x00010000
11717 #define FW_MSG_CODE_OK 0x00160000
11719 #define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000
11720 #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000
11721 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000
11722 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
11725 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
11726 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
11727 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
11728 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
11730 /* get pf rdma protocol command responce */
11731 #define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0
11732 #define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1
11733 #define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2
11734 #define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3
11736 /* get MFW feature support response */
11737 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002
11739 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0)
11742 #define DRV_PULSE_SEQ_MASK 0x00007fff
11743 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
11744 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
11747 #define MCP_PULSE_SEQ_MASK 0x00007fff
11748 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
11749 #define MCP_EVENT_MASK 0xffff0000
11750 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
11752 union drv_union_data union_data;
11755 enum MFW_DRV_MSG_TYPE {
11756 MFW_DRV_MSG_LINK_CHANGE,
11757 MFW_DRV_MSG_FLR_FW_ACK_FAILED,
11758 MFW_DRV_MSG_VF_DISABLED,
11759 MFW_DRV_MSG_LLDP_DATA_UPDATED,
11760 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
11761 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
11762 MFW_DRV_MSG_RESERVED4,
11763 MFW_DRV_MSG_BW_UPDATE,
11764 MFW_DRV_MSG_S_TAG_UPDATE,
11765 MFW_DRV_MSG_GET_LAN_STATS,
11766 MFW_DRV_MSG_GET_FCOE_STATS,
11767 MFW_DRV_MSG_GET_ISCSI_STATS,
11768 MFW_DRV_MSG_GET_RDMA_STATS,
11769 MFW_DRV_MSG_BW_UPDATE10,
11770 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
11771 MFW_DRV_MSG_BW_UPDATE11,
11775 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1)
11776 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2)
11777 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
11778 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
11780 struct public_mfw_mb {
11782 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
11783 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
11786 enum public_sections {
11793 PUBLIC_MAX_SECTIONS
11796 struct mcp_public_data {
11798 u32 sections[PUBLIC_MAX_SECTIONS];
11799 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
11800 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
11801 struct public_global global;
11802 struct public_path path[MCP_GLOB_PATH_MAX];
11803 struct public_port port[MCP_GLOB_PORT_MAX];
11804 struct public_func func[MCP_GLOB_FUNC_MAX];
11807 struct nvm_cfg_mac_address {
11809 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
11810 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
11814 struct nvm_cfg1_glob {
11816 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
11817 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
11818 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
11819 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
11820 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
11821 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
11822 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
11823 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
11824 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
11825 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
11826 u32 engineering_change[3];
11827 u32 manufacturing_id;
11828 u32 serial_number[4];
11832 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
11833 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
11834 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
11835 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
11836 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
11837 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
11838 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
11839 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
11840 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB
11841 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC
11842 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD
11843 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE
11844 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF
11850 u32 mps10_preemphasis;
11851 u32 mps10_driver_current;
11852 u32 mps25_preemphasis;
11853 u32 mps25_driver_current;
11857 u32 mps10_txfir_main;
11858 u32 mps10_txfir_post;
11859 u32 mps25_txfir_main;
11860 u32 mps25_txfir_post;
11861 u32 manufacture_ver;
11862 u32 manufacture_time;
11863 u32 led_global_settings;
11866 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
11867 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
11868 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00
11869 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
11870 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000
11871 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
11874 u32 device_capabilities;
11875 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
11876 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
11877 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
11878 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
11879 u32 power_dissipated;
11880 u32 power_consumed;
11882 u32 multi_network_modes_capability;
11886 struct nvm_cfg1_path {
11890 struct nvm_cfg1_port {
11891 u32 reserved__m_relocated_to_option_123;
11892 u32 reserved__m_relocated_to_option_124;
11894 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
11895 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
11896 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
11897 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
11898 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
11899 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
11900 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
11901 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
11902 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
11903 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
11904 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
11907 u32 speed_cap_mask;
11908 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
11909 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
11910 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
11911 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
11912 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
11913 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
11914 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
11915 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
11917 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
11918 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
11919 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
11920 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
11921 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
11922 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
11923 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
11924 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
11925 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
11926 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8
11927 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
11928 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
11929 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
11930 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
11931 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
11936 /* EEE power saving mode */
11937 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000
11938 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16
11939 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0
11940 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1
11941 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2
11942 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3
11947 struct nvm_cfg_mac_address lldp_mac_address;
11948 u32 led_port_settings;
11949 u32 transceiver_00;
11970 struct nvm_cfg1_func {
11971 struct nvm_cfg_mac_address mac_address;
11977 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr;
11978 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr;
11979 u32 preboot_generic_cfg;
11984 struct nvm_cfg1_glob glob;
11985 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX];
11986 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX];
11987 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX];
11990 enum spad_sections {
11991 SPAD_SECTION_TRACE,
11992 SPAD_SECTION_NVM_CFG,
11993 SPAD_SECTION_PUBLIC,
11994 SPAD_SECTION_PRIVATE,
11998 #define MCP_TRACE_SIZE 2048 /* 2kb */
12000 /* This section is located at a fixed location in the beginning of the
12001 * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade.
12002 * All the rest of data has a floating location which differs from version to
12003 * version, and is pointed by the mcp_meta_data below.
12004 * Moreover, the spad_layout section is part of the MFW firmware, and is loaded
12005 * with it from nvram in order to clear this portion.
12007 struct static_init {
12009 offsize_t sections[SPAD_SECTION_MAX];
12010 #define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_]))))
12012 struct mcp_trace trace;
12013 #define MCP_TRACE_P ((struct mcp_trace *)(STRUCT_OFFSET(trace)))
12014 u8 trace_buffer[MCP_TRACE_SIZE];
12015 #define MCP_TRACE_BUF ((u8 *)(STRUCT_OFFSET(trace_buffer)))
12016 /* running_mfw has the same definition as in nvm_map.h.
12017 * This bit indicate both the running dir, and the running bundle.
12018 * It is set once when the LIM is loaded.
12021 #define RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(running_mfw))))
12023 #define MFW_BUILD_TIME (*((u32 *)(STRUCT_OFFSET(build_time))))
12025 #define RESET_TYPE (*((u32 *)(STRUCT_OFFSET(reset_type))))
12026 u32 mfw_secure_mode;
12027 #define MFW_SECURE_MODE (*((u32 *)(STRUCT_OFFSET(mfw_secure_mode))))
12028 u16 pme_status_pf_bitmap;
12029 #define PME_STATUS_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_status_pf_bitmap))))
12030 u16 pme_enable_pf_bitmap;
12031 #define PME_ENABLE_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_enable_pf_bitmap))))
12033 u32 mim_start_addr;
12034 u32 ah_pcie_link_params;
12035 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff)
12036 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT (0)
12037 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00)
12038 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT (8)
12039 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000)
12040 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT (16)
12041 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000)
12042 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT (24)
12043 #define AH_PCIE_LINK_PARAMS (*((u32 *)(STRUCT_OFFSET(ah_pcie_link_params))))
12045 u32 rsrv_persist[5]; /* Persist reserved for MFW upgrades */
12048 #define NVM_MAGIC_VALUE 0x669955aa
12050 enum nvm_image_type {
12051 NVM_TYPE_TIM1 = 0x01,
12052 NVM_TYPE_TIM2 = 0x02,
12053 NVM_TYPE_MIM1 = 0x03,
12054 NVM_TYPE_MIM2 = 0x04,
12055 NVM_TYPE_MBA = 0x05,
12056 NVM_TYPE_MODULES_PN = 0x06,
12057 NVM_TYPE_VPD = 0x07,
12058 NVM_TYPE_MFW_TRACE1 = 0x08,
12059 NVM_TYPE_MFW_TRACE2 = 0x09,
12060 NVM_TYPE_NVM_CFG1 = 0x0a,
12061 NVM_TYPE_L2B = 0x0b,
12062 NVM_TYPE_DIR1 = 0x0c,
12063 NVM_TYPE_EAGLE_FW1 = 0x0d,
12064 NVM_TYPE_FALCON_FW1 = 0x0e,
12065 NVM_TYPE_PCIE_FW1 = 0x0f,
12066 NVM_TYPE_HW_SET = 0x10,
12067 NVM_TYPE_LIM = 0x11,
12068 NVM_TYPE_AVS_FW1 = 0x12,
12069 NVM_TYPE_DIR2 = 0x13,
12070 NVM_TYPE_CCM = 0x14,
12071 NVM_TYPE_EAGLE_FW2 = 0x15,
12072 NVM_TYPE_FALCON_FW2 = 0x16,
12073 NVM_TYPE_PCIE_FW2 = 0x17,
12074 NVM_TYPE_AVS_FW2 = 0x18,
12075 NVM_TYPE_INIT_HW = 0x19,
12076 NVM_TYPE_DEFAULT_CFG = 0x1a,
12077 NVM_TYPE_MDUMP = 0x1b,
12078 NVM_TYPE_META = 0x1c,
12079 NVM_TYPE_ISCSI_CFG = 0x1d,
12080 NVM_TYPE_FCOE_CFG = 0x1f,
12081 NVM_TYPE_ETH_PHY_FW1 = 0x20,
12082 NVM_TYPE_ETH_PHY_FW2 = 0x21,
12086 #define DIR_ID_1 (0)