drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/errno.h>
  39 #include <linux/kernel.h>
  40 #include <linux/mutex.h>
  41 #include <linux/pci.h>
  42 #include <linux/slab.h>
  43 #include <linux/string.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/qed/qed_chain.h>
  47 #include <linux/qed/qed_if.h>
  48 #include "qed.h"
  49 #include "qed_cxt.h"
  50 #include "qed_dcbx.h"
  51 #include "qed_dev_api.h"
  52 #include "qed_fcoe.h"
  53 #include "qed_hsi.h"
  54 #include "qed_hw.h"
  55 #include "qed_init_ops.h"
  56 #include "qed_int.h"
  57 #include "qed_iscsi.h"
  58 #include "qed_ll2.h"
  59 #include "qed_mcp.h"
  60 #include "qed_ooo.h"
  61 #include "qed_reg_addr.h"
  62 #include "qed_sp.h"
  63 #include "qed_sriov.h"
  64 #include "qed_vf.h"
  65 #include "qed_rdma.h"
  66
  67 static DEFINE_SPINLOCK(qm_lock);
  68
  69 #define QED_MIN_DPIS            (4)
  70 #define QED_MIN_PWM_REGION      (QED_WID_SIZE * QED_MIN_DPIS)
  71
  72 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
  73                            struct qed_ptt *p_ptt, enum BAR_ID bar_id)
  74 {
  75         u32 bar_reg = (bar_id == BAR_ID_0 ?
  76                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  77         u32 val;
  78
  79         if (IS_VF(p_hwfn->cdev))
  80                 return qed_vf_hw_bar_size(p_hwfn, bar_id);
  81
  82         val = qed_rd(p_hwfn, p_ptt, bar_reg);
  83         if (val)
  84                 return 1 << (val + 15);
  85
  86         /* Old MFW initialized above registered only conditionally */
  87         if (p_hwfn->cdev->num_hwfns > 1) {
  88                 DP_INFO(p_hwfn,
  89                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
  90                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  91         } else {
  92                 DP_INFO(p_hwfn,
  93                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
  94                         return 512 * 1024;
  95         }
  96 }
  97
  98 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
  99 {
 100         u32 i;
 101
 102         cdev->dp_level = dp_level;
 103         cdev->dp_module = dp_module;
 104         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 105                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 106
 107                 p_hwfn->dp_level = dp_level;
 108                 p_hwfn->dp_module = dp_module;
 109         }
 110 }
 111
 112 void qed_init_struct(struct qed_dev *cdev)
 113 {
 114         u8 i;
 115
 116         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 117                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 118
 119                 p_hwfn->cdev = cdev;
 120                 p_hwfn->my_id = i;
 121                 p_hwfn->b_active = false;
 122
 123                 mutex_init(&p_hwfn->dmae_info.mutex);
 124         }
 125
 126         /* hwfn 0 is always active */
 127         cdev->hwfns[0].b_active = true;
 128
 129         /* set the default cache alignment to 128 */
 130         cdev->cache_shift = 7;
 131 }
 132
 133 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
 134 {
 135         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 136
 137         kfree(qm_info->qm_pq_params);
 138         qm_info->qm_pq_params = NULL;
 139         kfree(qm_info->qm_vport_params);
 140         qm_info->qm_vport_params = NULL;
 141         kfree(qm_info->qm_port_params);
 142         qm_info->qm_port_params = NULL;
 143         kfree(qm_info->wfq_data);
 144         qm_info->wfq_data = NULL;
 145 }
 146
 147 void qed_resc_free(struct qed_dev *cdev)
 148 {
 149         int i;
 150
 151         if (IS_VF(cdev)) {
 152                 for_each_hwfn(cdev, i)
 153                         qed_l2_free(&cdev->hwfns[i]);
 154                 return;
 155         }
 156
 157         kfree(cdev->fw_data);
 158         cdev->fw_data = NULL;
 159
 160         kfree(cdev->reset_stats);
 161         cdev->reset_stats = NULL;
 162
 163         for_each_hwfn(cdev, i) {
 164                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 165
 166                 qed_cxt_mngr_free(p_hwfn);
 167                 qed_qm_info_free(p_hwfn);
 168                 qed_spq_free(p_hwfn);
 169                 qed_eq_free(p_hwfn);
 170                 qed_consq_free(p_hwfn);
 171                 qed_int_free(p_hwfn);
 172 #ifdef CONFIG_QED_LL2
 173                 qed_ll2_free(p_hwfn);
 174 #endif
 175                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
 176                         qed_fcoe_free(p_hwfn);
 177
 178                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 179                         qed_iscsi_free(p_hwfn);
 180                         qed_ooo_free(p_hwfn);
 181                 }
 182
 183                 if (QED_IS_RDMA_PERSONALITY(p_hwfn))
 184                         qed_rdma_info_free(p_hwfn);
 185
 186                 qed_iov_free(p_hwfn);
 187                 qed_l2_free(p_hwfn);
 188                 qed_dmae_info_free(p_hwfn);
 189                 qed_dcbx_info_free(p_hwfn);
 190         }
 191 }
 192
 193 /******************** QM initialization *******************/
 194 #define ACTIVE_TCS_BMAP 0x9f
 195 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 196
 197 /* determines the physical queue flags for a given PF. */
 198 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
 199 {
 200         u32 flags;
 201
 202         /* common flags */
 203         flags = PQ_FLAGS_LB;
 204
 205         /* feature flags */
 206         if (IS_QED_SRIOV(p_hwfn->cdev))
 207                 flags |= PQ_FLAGS_VFS;
 208
 209         /* protocol flags */
 210         switch (p_hwfn->hw_info.personality) {
 211         case QED_PCI_ETH:
 212                 flags |= PQ_FLAGS_MCOS;
 213                 break;
 214         case QED_PCI_FCOE:
 215                 flags |= PQ_FLAGS_OFLD;
 216                 break;
 217         case QED_PCI_ISCSI:
 218                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 219                 break;
 220         case QED_PCI_ETH_ROCE:
 221                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
 222                 if (IS_QED_MULTI_TC_ROCE(p_hwfn))
 223                         flags |= PQ_FLAGS_MTC;
 224                 break;
 225         case QED_PCI_ETH_IWARP:
 226                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 227                     PQ_FLAGS_OFLD;
 228                 break;
 229         default:
 230                 DP_ERR(p_hwfn,
 231                        "unknown personality %d\n", p_hwfn->hw_info.personality);
 232                 return 0;
 233         }
 234
 235         return flags;
 236 }
 237
 238 /* Getters for resource amounts necessary for qm initialization */
 239 static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
 240 {
 241         return p_hwfn->hw_info.num_hw_tc;
 242 }
 243
 244 static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
 245 {
 246         return IS_QED_SRIOV(p_hwfn->cdev) ?
 247                p_hwfn->cdev->p_iov_info->total_vfs : 0;
 248 }
 249
 250 static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn)
 251 {
 252         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 253
 254         if (!(PQ_FLAGS_MTC & pq_flags))
 255                 return 1;
 256
 257         return qed_init_qm_get_num_tcs(p_hwfn);
 258 }
 259
 260 #define NUM_DEFAULT_RLS 1
 261
 262 static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
 263 {
 264         u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 265
 266         /* num RLs can't exceed resource amount of rls or vports */
 267         num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
 268                                  RESC_NUM(p_hwfn, QED_VPORT));
 269
 270         /* Make sure after we reserve there's something left */
 271         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
 272                 return 0;
 273
 274         /* subtract rls necessary for VFs and one default one for the PF */
 275         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 276
 277         return num_pf_rls;
 278 }
 279
 280 static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
 281 {
 282         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 283
 284         /* all pqs share the same vport, except for vfs and pf_rl pqs */
 285         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 286                qed_init_qm_get_num_pf_rls(p_hwfn) +
 287                (!!(PQ_FLAGS_VFS & pq_flags)) *
 288                qed_init_qm_get_num_vfs(p_hwfn) + 1;
 289 }
 290
 291 /* calc amount of PQs according to the requested flags */
 292 static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
 293 {
 294         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 295
 296         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 297                qed_init_qm_get_num_pf_rls(p_hwfn) +
 298                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 299                qed_init_qm_get_num_tcs(p_hwfn) +
 300                (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
 301                (!!(PQ_FLAGS_ACK & pq_flags)) +
 302                (!!(PQ_FLAGS_OFLD & pq_flags)) *
 303                qed_init_qm_get_num_mtc_tcs(p_hwfn) +
 304                (!!(PQ_FLAGS_LLT & pq_flags)) *
 305                qed_init_qm_get_num_mtc_tcs(p_hwfn) +
 306                (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
 307 }
 308
 309 /* initialize the top level QM params */
 310 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
 311 {
 312         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 313         bool four_port;
 314
 315         /* pq and vport bases for this PF */
 316         qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
 317         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
 318
 319         /* rate limiting and weighted fair queueing are always enabled */
 320         qm_info->vport_rl_en = true;
 321         qm_info->vport_wfq_en = true;
 322
 323         /* TC config is different for AH 4 port */
 324         four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 325
 326         /* in AH 4 port we have fewer TCs per port */
 327         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 328                                                      NUM_OF_PHYS_TCS;
 329
 330         /* unless MFW indicated otherwise, ooo_tc == 3 for
 331          * AH 4-port and 4 otherwise.
 332          */
 333         if (!qm_info->ooo_tc)
 334                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 335                                               DCBX_TCP_OOO_TC;
 336 }
 337
 338 /* initialize qm vport params */
 339 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
 340 {
 341         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 342         u8 i;
 343
 344         /* all vports participate in weighted fair queueing */
 345         for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
 346                 qm_info->qm_vport_params[i].vport_wfq = 1;
 347 }
 348
 349 /* initialize qm port params */
 350 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
 351 {
 352         /* Initialize qm port parameters */
 353         u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
 354
 355         /* indicate how ooo and high pri traffic is dealt with */
 356         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 357                           ACTIVE_TCS_BMAP_4PORT_K2 :
 358                           ACTIVE_TCS_BMAP;
 359
 360         for (i = 0; i < num_ports; i++) {
 361                 struct init_qm_port_params *p_qm_port =
 362                     &p_hwfn->qm_info.qm_port_params[i];
 363
 364                 p_qm_port->active = 1;
 365                 p_qm_port->active_phys_tcs = active_phys_tcs;
 366                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 367                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 368         }
 369 }
 370
 371 /* Reset the params which must be reset for qm init. QM init may be called as
 372  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 373  * params may be affected by the init but would simply recalculate to the same
 374  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 375  * affected as these amounts stay the same.
 376  */
 377 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
 378 {
 379         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 380
 381         qm_info->num_pqs = 0;
 382         qm_info->num_vports = 0;
 383         qm_info->num_pf_rls = 0;
 384         qm_info->num_vf_pqs = 0;
 385         qm_info->first_vf_pq = 0;
 386         qm_info->first_mcos_pq = 0;
 387         qm_info->first_rl_pq = 0;
 388 }
 389
 390 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
 391 {
 392         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 393
 394         qm_info->num_vports++;
 395
 396         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 397                 DP_ERR(p_hwfn,
 398                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 399                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 400 }
 401
 402 /* initialize a single pq and manage qm_info resources accounting.
 403  * The pq_init_flags param determines whether the PQ is rate limited
 404  * (for VF or PF) and whether a new vport is allocated to the pq or not
 405  * (i.e. vport will be shared).
 406  */
 407
 408 /* flags for pq init */
 409 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 410 #define PQ_INIT_PF_RL           (1 << 1)
 411 #define PQ_INIT_VF_RL           (1 << 2)
 412
 413 /* defines for pq init */
 414 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 415 #define PQ_INIT_DEFAULT_TC              0
 416
 417 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc)
 418 {
 419         p_info->offload_tc = tc;
 420         p_info->offload_tc_set = true;
 421 }
 422
 423 static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn)
 424 {
 425         return p_hwfn->hw_info.offload_tc_set;
 426 }
 427
 428 static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn)
 429 {
 430         if (qed_is_offload_tc_set(p_hwfn))
 431                 return p_hwfn->hw_info.offload_tc;
 432
 433         return PQ_INIT_DEFAULT_TC;
 434 }
 435
 436 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
 437                            struct qed_qm_info *qm_info,
 438                            u8 tc, u32 pq_init_flags)
 439 {
 440         u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
 441
 442         if (pq_idx > max_pq)
 443                 DP_ERR(p_hwfn,
 444                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 445
 446         /* init pq params */
 447         qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
 448         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 449             qm_info->num_vports;
 450         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 451         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 452         qm_info->qm_pq_params[pq_idx].rl_valid =
 453             (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
 454
 455         /* qm params accounting */
 456         qm_info->num_pqs++;
 457         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 458                 qm_info->num_vports++;
 459
 460         if (pq_init_flags & PQ_INIT_PF_RL)
 461                 qm_info->num_pf_rls++;
 462
 463         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 464                 DP_ERR(p_hwfn,
 465                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 466                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 467
 468         if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
 469                 DP_ERR(p_hwfn,
 470                        "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
 471                        qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
 472 }
 473
 474 /* get pq index according to PQ_FLAGS */
 475 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
 476                                            unsigned long pq_flags)
 477 {
 478         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 479
 480         /* Can't have multiple flags set here */
 481         if (bitmap_weight(&pq_flags,
 482                           sizeof(pq_flags) * BITS_PER_BYTE) > 1) {
 483                 DP_ERR(p_hwfn, "requested multiple pq flags 0x%lx\n", pq_flags);
 484                 goto err;
 485         }
 486
 487         if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) {
 488                 DP_ERR(p_hwfn, "pq flag 0x%lx is not set\n", pq_flags);
 489                 goto err;
 490         }
 491
 492         switch (pq_flags) {
 493         case PQ_FLAGS_RLS:
 494                 return &qm_info->first_rl_pq;
 495         case PQ_FLAGS_MCOS:
 496                 return &qm_info->first_mcos_pq;
 497         case PQ_FLAGS_LB:
 498                 return &qm_info->pure_lb_pq;
 499         case PQ_FLAGS_OOO:
 500                 return &qm_info->ooo_pq;
 501         case PQ_FLAGS_ACK:
 502                 return &qm_info->pure_ack_pq;
 503         case PQ_FLAGS_OFLD:
 504                 return &qm_info->first_ofld_pq;
 505         case PQ_FLAGS_LLT:
 506                 return &qm_info->first_llt_pq;
 507         case PQ_FLAGS_VFS:
 508                 return &qm_info->first_vf_pq;
 509         default:
 510                 goto err;
 511         }
 512
 513 err:
 514         return &qm_info->start_pq;
 515 }
 516
 517 /* save pq index in qm info */
 518 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
 519                                 u32 pq_flags, u16 pq_val)
 520 {
 521         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 522
 523         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 524 }
 525
 526 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 527 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
 528 {
 529         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 530
 531         return *base_pq_idx + CM_TX_PQ_BASE;
 532 }
 533
 534 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
 535 {
 536         u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
 537
 538         if (max_tc == 0) {
 539                 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
 540                        PQ_FLAGS_MCOS);
 541                 return p_hwfn->qm_info.start_pq;
 542         }
 543
 544         if (tc > max_tc)
 545                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 546
 547         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
 548 }
 549
 550 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
 551 {
 552         u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
 553
 554         if (max_vf == 0) {
 555                 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
 556                        PQ_FLAGS_VFS);
 557                 return p_hwfn->qm_info.start_pq;
 558         }
 559
 560         if (vf > max_vf)
 561                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 562
 563         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
 564 }
 565
 566 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc)
 567 {
 568         u16 first_ofld_pq, pq_offset;
 569
 570         first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
 571         pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
 572                     tc : PQ_INIT_DEFAULT_TC;
 573
 574         return first_ofld_pq + pq_offset;
 575 }
 576
 577 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc)
 578 {
 579         u16 first_llt_pq, pq_offset;
 580
 581         first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT);
 582         pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
 583                     tc : PQ_INIT_DEFAULT_TC;
 584
 585         return first_llt_pq + pq_offset;
 586 }
 587
 588 /* Functions for creating specific types of pqs */
 589 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
 590 {
 591         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 592
 593         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 594                 return;
 595
 596         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 597         qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 598 }
 599
 600 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
 601 {
 602         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 603
 604         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 605                 return;
 606
 607         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 608         qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 609 }
 610
 611 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
 612 {
 613         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 614
 615         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 616                 return;
 617
 618         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 619         qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
 620                        PQ_INIT_SHARE_VPORT);
 621 }
 622
 623 static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn)
 624 {
 625         u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn);
 626         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 627         u8 tc;
 628
 629         /* override pq's TC if offload TC is set */
 630         for (tc = 0; tc < num_tcs; tc++)
 631                 qed_init_qm_pq(p_hwfn, qm_info,
 632                                qed_is_offload_tc_set(p_hwfn) ?
 633                                p_hwfn->hw_info.offload_tc : tc,
 634                                PQ_INIT_SHARE_VPORT);
 635 }
 636
 637 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
 638 {
 639         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 640
 641         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 642                 return;
 643
 644         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 645         qed_init_qm_mtc_pqs(p_hwfn);
 646 }
 647
 648 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
 649 {
 650         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 651
 652         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
 653                 return;
 654
 655         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
 656         qed_init_qm_mtc_pqs(p_hwfn);
 657 }
 658
 659 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
 660 {
 661         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 662         u8 tc_idx;
 663
 664         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 665                 return;
 666
 667         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 668         for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 669                 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 670 }
 671
 672 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
 673 {
 674         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 675         u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 676
 677         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 678                 return;
 679
 680         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 681         qm_info->num_vf_pqs = num_vfs;
 682         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 683                 qed_init_qm_pq(p_hwfn,
 684                                qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
 685 }
 686
 687 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
 688 {
 689         u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
 690         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 691
 692         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 693                 return;
 694
 695         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 696         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 697                 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
 698                                PQ_INIT_PF_RL);
 699 }
 700
 701 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
 702 {
 703         /* rate limited pqs, must come first (FW assumption) */
 704         qed_init_qm_rl_pqs(p_hwfn);
 705
 706         /* pqs for multi cos */
 707         qed_init_qm_mcos_pqs(p_hwfn);
 708
 709         /* pure loopback pq */
 710         qed_init_qm_lb_pq(p_hwfn);
 711
 712         /* out of order pq */
 713         qed_init_qm_ooo_pq(p_hwfn);
 714
 715         /* pure ack pq */
 716         qed_init_qm_pure_ack_pq(p_hwfn);
 717
 718         /* pq for offloaded protocol */
 719         qed_init_qm_offload_pq(p_hwfn);
 720
 721         /* low latency pq */
 722         qed_init_qm_low_latency_pq(p_hwfn);
 723
 724         /* done sharing vports */
 725         qed_init_qm_advance_vport(p_hwfn);
 726
 727         /* pqs for vfs */
 728         qed_init_qm_vf_pqs(p_hwfn);
 729 }
 730
 731 /* compare values of getters against resources amounts */
 732 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
 733 {
 734         if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
 735                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 736                 return -EINVAL;
 737         }
 738
 739         if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
 740                 return 0;
 741
 742         if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
 743                 p_hwfn->hw_info.multi_tc_roce_en = 0;
 744                 DP_NOTICE(p_hwfn,
 745                           "multi-tc roce was disabled to reduce requested amount of pqs\n");
 746                 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
 747                         return 0;
 748         }
 749
 750         DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 751         return -EINVAL;
 752 }
 753
 754 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
 755 {
 756         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 757         struct init_qm_vport_params *vport;
 758         struct init_qm_port_params *port;
 759         struct init_qm_pq_params *pq;
 760         int i, tc;
 761
 762         /* top level params */
 763         DP_VERBOSE(p_hwfn,
 764                    NETIF_MSG_HW,
 765                    "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n",
 766                    qm_info->start_pq,
 767                    qm_info->start_vport,
 768                    qm_info->pure_lb_pq,
 769                    qm_info->first_ofld_pq,
 770                    qm_info->first_llt_pq,
 771                    qm_info->pure_ack_pq);
 772         DP_VERBOSE(p_hwfn,
 773                    NETIF_MSG_HW,
 774                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
 775                    qm_info->ooo_pq,
 776                    qm_info->first_vf_pq,
 777                    qm_info->num_pqs,
 778                    qm_info->num_vf_pqs,
 779                    qm_info->num_vports, qm_info->max_phys_tcs_per_port);
 780         DP_VERBOSE(p_hwfn,
 781                    NETIF_MSG_HW,
 782                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 783                    qm_info->pf_rl_en,
 784                    qm_info->pf_wfq_en,
 785                    qm_info->vport_rl_en,
 786                    qm_info->vport_wfq_en,
 787                    qm_info->pf_wfq,
 788                    qm_info->pf_rl,
 789                    qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
 790
 791         /* port table */
 792         for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
 793                 port = &(qm_info->qm_port_params[i]);
 794                 DP_VERBOSE(p_hwfn,
 795                            NETIF_MSG_HW,
 796                            "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
 797                            i,
 798                            port->active,
 799                            port->active_phys_tcs,
 800                            port->num_pbf_cmd_lines,
 801                            port->num_btb_blocks, port->reserved);
 802         }
 803
 804         /* vport table */
 805         for (i = 0; i < qm_info->num_vports; i++) {
 806                 vport = &(qm_info->qm_vport_params[i]);
 807                 DP_VERBOSE(p_hwfn,
 808                            NETIF_MSG_HW,
 809                            "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
 810                            qm_info->start_vport + i,
 811                            vport->vport_rl, vport->vport_wfq);
 812                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 813                         DP_VERBOSE(p_hwfn,
 814                                    NETIF_MSG_HW,
 815                                    "%d ", vport->first_tx_pq_id[tc]);
 816                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
 817         }
 818
 819         /* pq table */
 820         for (i = 0; i < qm_info->num_pqs; i++) {
 821                 pq = &(qm_info->qm_pq_params[i]);
 822                 DP_VERBOSE(p_hwfn,
 823                            NETIF_MSG_HW,
 824                            "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
 825                            qm_info->start_pq + i,
 826                            pq->port_id,
 827                            pq->vport_id,
 828                            pq->tc_id, pq->wrr_group, pq->rl_valid);
 829         }
 830 }
 831
 832 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
 833 {
 834         /* reset params required for init run */
 835         qed_init_qm_reset_params(p_hwfn);
 836
 837         /* init QM top level params */
 838         qed_init_qm_params(p_hwfn);
 839
 840         /* init QM port params */
 841         qed_init_qm_port_params(p_hwfn);
 842
 843         /* init QM vport params */
 844         qed_init_qm_vport_params(p_hwfn);
 845
 846         /* init QM physical queue params */
 847         qed_init_qm_pq_params(p_hwfn);
 848
 849         /* display all that init */
 850         qed_dp_init_qm_params(p_hwfn);
 851 }
 852
 853 /* This function reconfigures the QM pf on the fly.
 854  * For this purpose we:
 855  * 1. reconfigure the QM database
 856  * 2. set new values to runtime array
 857  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 858  * 4. activate init tool in QM_PF stage
 859  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 860  */
 861 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 862 {
 863         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 864         bool b_rc;
 865         int rc;
 866
 867         /* initialize qed's qm data structure */
 868         qed_init_qm_info(p_hwfn);
 869
 870         /* stop PF's qm queues */
 871         spin_lock_bh(&qm_lock);
 872         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 873                                     qm_info->start_pq, qm_info->num_pqs);
 874         spin_unlock_bh(&qm_lock);
 875         if (!b_rc)
 876                 return -EINVAL;
 877
 878         /* clear the QM_PF runtime phase leftovers from previous init */
 879         qed_init_clear_rt_data(p_hwfn);
 880
 881         /* prepare QM portion of runtime array */
 882         qed_qm_init_pf(p_hwfn, p_ptt, false);
 883
 884         /* activate init tool on runtime array */
 885         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 886                           p_hwfn->hw_info.hw_mode);
 887         if (rc)
 888                 return rc;
 889
 890         /* start PF's qm queues */
 891         spin_lock_bh(&qm_lock);
 892         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 893                                     qm_info->start_pq, qm_info->num_pqs);
 894         spin_unlock_bh(&qm_lock);
 895         if (!b_rc)
 896                 return -EINVAL;
 897
 898         return 0;
 899 }
 900
 901 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
 902 {
 903         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 904         int rc;
 905
 906         rc = qed_init_qm_sanity(p_hwfn);
 907         if (rc)
 908                 goto alloc_err;
 909
 910         qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn),
 911                                         sizeof(*qm_info->qm_pq_params),
 912                                         GFP_KERNEL);
 913         if (!qm_info->qm_pq_params)
 914                 goto alloc_err;
 915
 916         qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
 917                                            sizeof(*qm_info->qm_vport_params),
 918                                            GFP_KERNEL);
 919         if (!qm_info->qm_vport_params)
 920                 goto alloc_err;
 921
 922         qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine,
 923                                           sizeof(*qm_info->qm_port_params),
 924                                           GFP_KERNEL);
 925         if (!qm_info->qm_port_params)
 926                 goto alloc_err;
 927
 928         qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
 929                                     sizeof(*qm_info->wfq_data),
 930                                     GFP_KERNEL);
 931         if (!qm_info->wfq_data)
 932                 goto alloc_err;
 933
 934         return 0;
 935
 936 alloc_err:
 937         DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
 938         qed_qm_info_free(p_hwfn);
 939         return -ENOMEM;
 940 }
 941
 942 int qed_resc_alloc(struct qed_dev *cdev)
 943 {
 944         u32 rdma_tasks, excess_tasks;
 945         u32 line_count;
 946         int i, rc = 0;
 947
 948         if (IS_VF(cdev)) {
 949                 for_each_hwfn(cdev, i) {
 950                         rc = qed_l2_alloc(&cdev->hwfns[i]);
 951                         if (rc)
 952                                 return rc;
 953                 }
 954                 return rc;
 955         }
 956
 957         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
 958         if (!cdev->fw_data)
 959                 return -ENOMEM;
 960
 961         for_each_hwfn(cdev, i) {
 962                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 963                 u32 n_eqes, num_cons;
 964
 965                 /* First allocate the context manager structure */
 966                 rc = qed_cxt_mngr_alloc(p_hwfn);
 967                 if (rc)
 968                         goto alloc_err;
 969
 970                 /* Set the HW cid/tid numbers (in the contest manager)
 971                  * Must be done prior to any further computations.
 972                  */
 973                 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
 974                 if (rc)
 975                         goto alloc_err;
 976
 977                 rc = qed_alloc_qm_data(p_hwfn);
 978                 if (rc)
 979                         goto alloc_err;
 980
 981                 /* init qm info */
 982                 qed_init_qm_info(p_hwfn);
 983
 984                 /* Compute the ILT client partition */
 985                 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
 986                 if (rc) {
 987                         DP_NOTICE(p_hwfn,
 988                                   "too many ILT lines; re-computing with less lines\n");
 989                         /* In case there are not enough ILT lines we reduce the
 990                          * number of RDMA tasks and re-compute.
 991                          */
 992                         excess_tasks =
 993                             qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
 994                         if (!excess_tasks)
 995                                 goto alloc_err;
 996
 997                         rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
 998                         rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
 999                         if (rc)
1000                                 goto alloc_err;
1001
1002                         rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
1003                         if (rc) {
1004                                 DP_ERR(p_hwfn,
1005                                        "failed ILT compute. Requested too many lines: %u\n",
1006                                        line_count);
1007
1008                                 goto alloc_err;
1009                         }
1010                 }
1011
1012                 /* CID map / ILT shadow table / T2
1013                  * The talbes sizes are determined by the computations above
1014                  */
1015                 rc = qed_cxt_tables_alloc(p_hwfn);
1016                 if (rc)
1017                         goto alloc_err;
1018
1019                 /* SPQ, must follow ILT because initializes SPQ context */
1020                 rc = qed_spq_alloc(p_hwfn);
1021                 if (rc)
1022                         goto alloc_err;
1023
1024                 /* SP status block allocation */
1025                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
1026                                                          RESERVED_PTT_DPC);
1027
1028                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1029                 if (rc)
1030                         goto alloc_err;
1031
1032                 rc = qed_iov_alloc(p_hwfn);
1033                 if (rc)
1034                         goto alloc_err;
1035
1036                 /* EQ */
1037                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
1038                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
1039                         enum protocol_type rdma_proto;
1040
1041                         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
1042                                 rdma_proto = PROTOCOLID_ROCE;
1043                         else
1044                                 rdma_proto = PROTOCOLID_IWARP;
1045
1046                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
1047                                                                rdma_proto,
1048                                                                NULL) * 2;
1049                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1050                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1051                         num_cons =
1052                             qed_cxt_get_proto_cid_count(p_hwfn,
1053                                                         PROTOCOLID_ISCSI,
1054                                                         NULL);
1055                         n_eqes += 2 * num_cons;
1056                 }
1057
1058                 if (n_eqes > 0xFFFF) {
1059                         DP_ERR(p_hwfn,
1060                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
1061                                n_eqes, 0xFFFF);
1062                         goto alloc_no_mem;
1063                 }
1064
1065                 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
1066                 if (rc)
1067                         goto alloc_err;
1068
1069                 rc = qed_consq_alloc(p_hwfn);
1070                 if (rc)
1071                         goto alloc_err;
1072
1073                 rc = qed_l2_alloc(p_hwfn);
1074                 if (rc)
1075                         goto alloc_err;
1076
1077 #ifdef CONFIG_QED_LL2
1078                 if (p_hwfn->using_ll2) {
1079                         rc = qed_ll2_alloc(p_hwfn);
1080                         if (rc)
1081                                 goto alloc_err;
1082                 }
1083 #endif
1084
1085                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1086                         rc = qed_fcoe_alloc(p_hwfn);
1087                         if (rc)
1088                                 goto alloc_err;
1089                 }
1090
1091                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1092                         rc = qed_iscsi_alloc(p_hwfn);
1093                         if (rc)
1094                                 goto alloc_err;
1095                         rc = qed_ooo_alloc(p_hwfn);
1096                         if (rc)
1097                                 goto alloc_err;
1098                 }
1099
1100                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
1101                         rc = qed_rdma_info_alloc(p_hwfn);
1102                         if (rc)
1103                                 goto alloc_err;
1104                 }
1105
1106                 /* DMA info initialization */
1107                 rc = qed_dmae_info_alloc(p_hwfn);
1108                 if (rc)
1109                         goto alloc_err;
1110
1111                 /* DCBX initialization */
1112                 rc = qed_dcbx_info_alloc(p_hwfn);
1113                 if (rc)
1114                         goto alloc_err;
1115         }
1116
1117         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
1118         if (!cdev->reset_stats)
1119                 goto alloc_no_mem;
1120
1121         return 0;
1122
1123 alloc_no_mem:
1124         rc = -ENOMEM;
1125 alloc_err:
1126         qed_resc_free(cdev);
1127         return rc;
1128 }
1129
1130 void qed_resc_setup(struct qed_dev *cdev)
1131 {
1132         int i;
1133
1134         if (IS_VF(cdev)) {
1135                 for_each_hwfn(cdev, i)
1136                         qed_l2_setup(&cdev->hwfns[i]);
1137                 return;
1138         }
1139
1140         for_each_hwfn(cdev, i) {
1141                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1142
1143                 qed_cxt_mngr_setup(p_hwfn);
1144                 qed_spq_setup(p_hwfn);
1145                 qed_eq_setup(p_hwfn);
1146                 qed_consq_setup(p_hwfn);
1147
1148                 /* Read shadow of current MFW mailbox */
1149                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1150                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1151                        p_hwfn->mcp_info->mfw_mb_cur,
1152                        p_hwfn->mcp_info->mfw_mb_length);
1153
1154                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1155
1156                 qed_l2_setup(p_hwfn);
1157                 qed_iov_setup(p_hwfn);
1158 #ifdef CONFIG_QED_LL2
1159                 if (p_hwfn->using_ll2)
1160                         qed_ll2_setup(p_hwfn);
1161 #endif
1162                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1163                         qed_fcoe_setup(p_hwfn);
1164
1165                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1166                         qed_iscsi_setup(p_hwfn);
1167                         qed_ooo_setup(p_hwfn);
1168                 }
1169         }
1170 }
1171
1172 #define FINAL_CLEANUP_POLL_CNT          (100)
1173 #define FINAL_CLEANUP_POLL_TIME         (10)
1174 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
1175                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
1176 {
1177         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1178         int rc = -EBUSY;
1179
1180         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1181                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1182
1183         if (is_vf)
1184                 id += 0x10;
1185
1186         command |= X_FINAL_CLEANUP_AGG_INT <<
1187                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1188         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1189         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1190         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1191
1192         /* Make sure notification is not set before initiating final cleanup */
1193         if (REG_RD(p_hwfn, addr)) {
1194                 DP_NOTICE(p_hwfn,
1195                           "Unexpected; Found final cleanup notification before initiating final cleanup\n");
1196                 REG_WR(p_hwfn, addr, 0);
1197         }
1198
1199         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1200                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1201                    id, command);
1202
1203         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1204
1205         /* Poll until completion */
1206         while (!REG_RD(p_hwfn, addr) && count--)
1207                 msleep(FINAL_CLEANUP_POLL_TIME);
1208
1209         if (REG_RD(p_hwfn, addr))
1210                 rc = 0;
1211         else
1212                 DP_NOTICE(p_hwfn,
1213                           "Failed to receive FW final cleanup notification\n");
1214
1215         /* Cleanup afterwards */
1216         REG_WR(p_hwfn, addr, 0);
1217
1218         return rc;
1219 }
1220
1221 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
1222 {
1223         int hw_mode = 0;
1224
1225         if (QED_IS_BB_B0(p_hwfn->cdev)) {
1226                 hw_mode |= 1 << MODE_BB;
1227         } else if (QED_IS_AH(p_hwfn->cdev)) {
1228                 hw_mode |= 1 << MODE_K2;
1229         } else {
1230                 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1231                           p_hwfn->cdev->type);
1232                 return -EINVAL;
1233         }
1234
1235         switch (p_hwfn->cdev->num_ports_in_engine) {
1236         case 1:
1237                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1238                 break;
1239         case 2:
1240                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1241                 break;
1242         case 4:
1243                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1244                 break;
1245         default:
1246                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
1247                           p_hwfn->cdev->num_ports_in_engine);
1248                 return -EINVAL;
1249         }
1250
1251         if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
1252                 hw_mode |= 1 << MODE_MF_SD;
1253         else
1254                 hw_mode |= 1 << MODE_MF_SI;
1255
1256         hw_mode |= 1 << MODE_ASIC;
1257
1258         if (p_hwfn->cdev->num_hwfns > 1)
1259                 hw_mode |= 1 << MODE_100G;
1260
1261         p_hwfn->hw_info.hw_mode = hw_mode;
1262
1263         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1264                    "Configuring function for hw_mode: 0x%08x\n",
1265                    p_hwfn->hw_info.hw_mode);
1266
1267         return 0;
1268 }
1269
1270 /* Init run time data for all PFs on an engine. */
1271 static void qed_init_cau_rt_data(struct qed_dev *cdev)
1272 {
1273         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1274         int i, igu_sb_id;
1275
1276         for_each_hwfn(cdev, i) {
1277                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1278                 struct qed_igu_info *p_igu_info;
1279                 struct qed_igu_block *p_block;
1280                 struct cau_sb_entry sb_entry;
1281
1282                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1283
1284                 for (igu_sb_id = 0;
1285                      igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
1286                         p_block = &p_igu_info->entry[igu_sb_id];
1287
1288                         if (!p_block->is_pf)
1289                                 continue;
1290
1291                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1292                                               p_block->function_id, 0, 0);
1293                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1294                                          sb_entry);
1295                 }
1296         }
1297 }
1298
1299 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
1300                                      struct qed_ptt *p_ptt)
1301 {
1302         u32 val, wr_mbs, cache_line_size;
1303
1304         val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1305         switch (val) {
1306         case 0:
1307                 wr_mbs = 128;
1308                 break;
1309         case 1:
1310                 wr_mbs = 256;
1311                 break;
1312         case 2:
1313                 wr_mbs = 512;
1314                 break;
1315         default:
1316                 DP_INFO(p_hwfn,
1317                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1318                         val);
1319                 return;
1320         }
1321
1322         cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
1323         switch (cache_line_size) {
1324         case 32:
1325                 val = 0;
1326                 break;
1327         case 64:
1328                 val = 1;
1329                 break;
1330         case 128:
1331                 val = 2;
1332                 break;
1333         case 256:
1334                 val = 3;
1335                 break;
1336         default:
1337                 DP_INFO(p_hwfn,
1338                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1339                         cache_line_size);
1340         }
1341
1342         if (L1_CACHE_BYTES > wr_mbs)
1343                 DP_INFO(p_hwfn,
1344                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1345                         L1_CACHE_BYTES, wr_mbs);
1346
1347         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1348         if (val > 0) {
1349                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1350                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1351         }
1352 }
1353
1354 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1355                               struct qed_ptt *p_ptt, int hw_mode)
1356 {
1357         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1358         struct qed_qm_common_rt_init_params params;
1359         struct qed_dev *cdev = p_hwfn->cdev;
1360         u8 vf_id, max_num_vfs;
1361         u16 num_pfs, pf_id;
1362         u32 concrete_fid;
1363         int rc = 0;
1364
1365         qed_init_cau_rt_data(cdev);
1366
1367         /* Program GTT windows */
1368         qed_gtt_init(p_hwfn);
1369
1370         if (p_hwfn->mcp_info) {
1371                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1372                         qm_info->pf_rl_en = true;
1373                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1374                         qm_info->pf_wfq_en = true;
1375         }
1376
1377         memset(&params, 0, sizeof(params));
1378         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
1379         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1380         params.pf_rl_en = qm_info->pf_rl_en;
1381         params.pf_wfq_en = qm_info->pf_wfq_en;
1382         params.vport_rl_en = qm_info->vport_rl_en;
1383         params.vport_wfq_en = qm_info->vport_wfq_en;
1384         params.port_params = qm_info->qm_port_params;
1385
1386         qed_qm_common_rt_init(p_hwfn, &params);
1387
1388         qed_cxt_hw_init_common(p_hwfn);
1389
1390         qed_init_cache_line_size(p_hwfn, p_ptt);
1391
1392         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1393         if (rc)
1394                 return rc;
1395
1396         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1397         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1398
1399         if (QED_IS_BB(p_hwfn->cdev)) {
1400                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1401                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1402                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1403                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1404                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1405                 }
1406                 /* pretend to original PF */
1407                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1408         }
1409
1410         max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1411         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1412                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1413                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1414                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1415                 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1416                 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1417                 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1418         }
1419         /* pretend to original PF */
1420         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1421
1422         return rc;
1423 }
1424
1425 static int
1426 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1427                      struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1428 {
1429         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1430         u32 min_dpis;
1431         u32 n_wids;
1432
1433         /* Calculate DPI size */
1434         n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
1435         dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
1436         dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
1437         dpi_bit_shift = ilog2(dpi_page_size / 4096);
1438         dpi_count = pwm_region_size / dpi_page_size;
1439
1440         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1441         min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1442
1443         p_hwfn->dpi_size = dpi_page_size;
1444         p_hwfn->dpi_count = dpi_count;
1445
1446         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1447
1448         if (dpi_count < min_dpis)
1449                 return -EINVAL;
1450
1451         return 0;
1452 }
1453
1454 enum QED_ROCE_EDPM_MODE {
1455         QED_ROCE_EDPM_MODE_ENABLE = 0,
1456         QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1457         QED_ROCE_EDPM_MODE_DISABLE = 2,
1458 };
1459
1460 static int
1461 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1462 {
1463         u32 pwm_regsize, norm_regsize;
1464         u32 non_pwm_conn, min_addr_reg1;
1465         u32 db_bar_size, n_cpus = 1;
1466         u32 roce_edpm_mode;
1467         u32 pf_dems_shift;
1468         int rc = 0;
1469         u8 cond;
1470
1471         db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1472         if (p_hwfn->cdev->num_hwfns > 1)
1473                 db_bar_size /= 2;
1474
1475         /* Calculate doorbell regions */
1476         non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1477                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1478                                                    NULL) +
1479                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1480                                                    NULL);
1481         norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
1482         min_addr_reg1 = norm_regsize / 4096;
1483         pwm_regsize = db_bar_size - norm_regsize;
1484
1485         /* Check that the normal and PWM sizes are valid */
1486         if (db_bar_size < norm_regsize) {
1487                 DP_ERR(p_hwfn->cdev,
1488                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1489                        db_bar_size, norm_regsize);
1490                 return -EINVAL;
1491         }
1492
1493         if (pwm_regsize < QED_MIN_PWM_REGION) {
1494                 DP_ERR(p_hwfn->cdev,
1495                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1496                        pwm_regsize,
1497                        QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1498                 return -EINVAL;
1499         }
1500
1501         /* Calculate number of DPIs */
1502         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1503         if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1504             ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1505                 /* Either EDPM is mandatory, or we are attempting to allocate a
1506                  * WID per CPU.
1507                  */
1508                 n_cpus = num_present_cpus();
1509                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1510         }
1511
1512         cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1513                (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1514         if (cond || p_hwfn->dcbx_no_edpm) {
1515                 /* Either EDPM is disabled from user configuration, or it is
1516                  * disabled via DCBx, or it is not mandatory and we failed to
1517                  * allocated a WID per CPU.
1518                  */
1519                 n_cpus = 1;
1520                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1521
1522                 if (cond)
1523                         qed_rdma_dpm_bar(p_hwfn, p_ptt);
1524         }
1525
1526         p_hwfn->wid_count = (u16) n_cpus;
1527
1528         DP_INFO(p_hwfn,
1529                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1530                 norm_regsize,
1531                 pwm_regsize,
1532                 p_hwfn->dpi_size,
1533                 p_hwfn->dpi_count,
1534                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1535                 "disabled" : "enabled");
1536
1537         if (rc) {
1538                 DP_ERR(p_hwfn,
1539                        "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1540                        p_hwfn->dpi_count,
1541                        p_hwfn->pf_params.rdma_pf_params.min_dpis);
1542                 return -EINVAL;
1543         }
1544
1545         p_hwfn->dpi_start_offset = norm_regsize;
1546
1547         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1548         pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1549         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1550         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1551
1552         return 0;
1553 }
1554
1555 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1556                             struct qed_ptt *p_ptt, int hw_mode)
1557 {
1558         int rc = 0;
1559
1560         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
1561         if (rc)
1562                 return rc;
1563
1564         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
1565
1566         return 0;
1567 }
1568
1569 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1570                           struct qed_ptt *p_ptt,
1571                           struct qed_tunnel_info *p_tunn,
1572                           int hw_mode,
1573                           bool b_hw_start,
1574                           enum qed_int_mode int_mode,
1575                           bool allow_npar_tx_switch)
1576 {
1577         u8 rel_pf_id = p_hwfn->rel_pf_id;
1578         int rc = 0;
1579
1580         if (p_hwfn->mcp_info) {
1581                 struct qed_mcp_function_info *p_info;
1582
1583                 p_info = &p_hwfn->mcp_info->func_info;
1584                 if (p_info->bandwidth_min)
1585                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1586
1587                 /* Update rate limit once we'll actually have a link */
1588                 p_hwfn->qm_info.pf_rl = 100000;
1589         }
1590
1591         qed_cxt_hw_init_pf(p_hwfn, p_ptt);
1592
1593         qed_int_igu_init_rt(p_hwfn);
1594
1595         /* Set VLAN in NIG if needed */
1596         if (hw_mode & BIT(MODE_MF_SD)) {
1597                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1598                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1599                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1600                              p_hwfn->hw_info.ovlan);
1601
1602                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1603                            "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
1604                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
1605                              1);
1606         }
1607
1608         /* Enable classification by MAC if needed */
1609         if (hw_mode & BIT(MODE_MF_SI)) {
1610                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1611                            "Configuring TAGMAC_CLS_TYPE\n");
1612                 STORE_RT_REG(p_hwfn,
1613                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1614         }
1615
1616         /* Protocol Configuration */
1617         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1618                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1619         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1620                      (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
1621         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1622
1623         /* Cleanup chip from previous driver if such remains exist */
1624         rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1625         if (rc)
1626                 return rc;
1627
1628         /* Sanity check before the PF init sequence that uses DMAE */
1629         rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
1630         if (rc)
1631                 return rc;
1632
1633         /* PF Init sequence */
1634         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1635         if (rc)
1636                 return rc;
1637
1638         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1639         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1640         if (rc)
1641                 return rc;
1642
1643         /* Pure runtime initializations - directly to the HW  */
1644         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1645
1646         rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1647         if (rc)
1648                 return rc;
1649
1650         if (b_hw_start) {
1651                 /* enable interrupts */
1652                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1653
1654                 /* send function start command */
1655                 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
1656                                      allow_npar_tx_switch);
1657                 if (rc) {
1658                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1659                         return rc;
1660                 }
1661                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1662                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1663                         qed_wr(p_hwfn, p_ptt,
1664                                PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1665                                0x100);
1666                 }
1667         }
1668         return rc;
1669 }
1670
1671 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1672                                struct qed_ptt *p_ptt,
1673                                u8 enable)
1674 {
1675         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1676
1677         /* Change PF in PXP */
1678         qed_wr(p_hwfn, p_ptt,
1679                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1680
1681         /* wait until value is set - try for 1 second every 50us */
1682         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1683                 val = qed_rd(p_hwfn, p_ptt,
1684                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1685                 if (val == set_val)
1686                         break;
1687
1688                 usleep_range(50, 60);
1689         }
1690
1691         if (val != set_val) {
1692                 DP_NOTICE(p_hwfn,
1693                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1694                 return -EAGAIN;
1695         }
1696
1697         return 0;
1698 }
1699
1700 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1701                                 struct qed_ptt *p_main_ptt)
1702 {
1703         /* Read shadow of current MFW mailbox */
1704         qed_mcp_read_mb(p_hwfn, p_main_ptt);
1705         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1706                p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
1707 }
1708
1709 static void
1710 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
1711                          struct qed_drv_load_params *p_drv_load)
1712 {
1713         memset(p_load_req, 0, sizeof(*p_load_req));
1714
1715         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1716                                QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
1717         p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
1718         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
1719         p_load_req->override_force_load = p_drv_load->override_force_load;
1720 }
1721
1722 static int qed_vf_start(struct qed_hwfn *p_hwfn,
1723                         struct qed_hw_init_params *p_params)
1724 {
1725         if (p_params->p_tunn) {
1726                 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1727                 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1728         }
1729
1730         p_hwfn->b_int_enabled = true;
1731
1732         return 0;
1733 }
1734
1735 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
1736 {
1737         struct qed_load_req_params load_req_params;
1738         u32 load_code, resp, param, drv_mb_param;
1739         bool b_default_mtu = true;
1740         struct qed_hwfn *p_hwfn;
1741         int rc = 0, mfw_rc, i;
1742         u16 ether_type;
1743
1744         if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
1745                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1746                 return -EINVAL;
1747         }
1748
1749         if (IS_PF(cdev)) {
1750                 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
1751                 if (rc)
1752                         return rc;
1753         }
1754
1755         for_each_hwfn(cdev, i) {
1756                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1757
1758                 /* If management didn't provide a default, set one of our own */
1759                 if (!p_hwfn->hw_info.mtu) {
1760                         p_hwfn->hw_info.mtu = 1500;
1761                         b_default_mtu = false;
1762                 }
1763
1764                 if (IS_VF(cdev)) {
1765                         qed_vf_start(p_hwfn, p_params);
1766                         continue;
1767                 }
1768
1769                 /* Enable DMAE in PXP */
1770                 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1771
1772                 rc = qed_calc_hw_mode(p_hwfn);
1773                 if (rc)
1774                         return rc;
1775
1776                 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING,
1777                                              &cdev->mf_bits) ||
1778                                     test_bit(QED_MF_8021AD_TAGGING,
1779                                              &cdev->mf_bits))) {
1780                         if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits))
1781                                 ether_type = ETH_P_8021Q;
1782                         else
1783                                 ether_type = ETH_P_8021AD;
1784                         STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1785                                      ether_type);
1786                         STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1787                                      ether_type);
1788                         STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1789                                      ether_type);
1790                         STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
1791                                      ether_type);
1792                 }
1793
1794                 qed_fill_load_req_params(&load_req_params,
1795                                          p_params->p_drv_load_params);
1796                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1797                                       &load_req_params);
1798                 if (rc) {
1799                         DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
1800                         return rc;
1801                 }
1802
1803                 load_code = load_req_params.load_code;
1804                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1805                            "Load request was sent. Load code: 0x%x\n",
1806                            load_code);
1807
1808                 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
1809
1810                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1811
1812                 p_hwfn->first_on_engine = (load_code ==
1813                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1814
1815                 switch (load_code) {
1816                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1817                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1818                                                 p_hwfn->hw_info.hw_mode);
1819                         if (rc)
1820                                 break;
1821                 /* Fall through */
1822                 case FW_MSG_CODE_DRV_LOAD_PORT:
1823                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1824                                               p_hwfn->hw_info.hw_mode);
1825                         if (rc)
1826                                 break;
1827
1828                 /* Fall through */
1829                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1830                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1831                                             p_params->p_tunn,
1832                                             p_hwfn->hw_info.hw_mode,
1833                                             p_params->b_hw_start,
1834                                             p_params->int_mode,
1835                                             p_params->allow_npar_tx_switch);
1836                         break;
1837                 default:
1838                         DP_NOTICE(p_hwfn,
1839                                   "Unexpected load code [0x%08x]", load_code);
1840                         rc = -EINVAL;
1841                         break;
1842                 }
1843
1844                 if (rc)
1845                         DP_NOTICE(p_hwfn,
1846                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1847                                    load_code, rc);
1848
1849                 /* ACK mfw regardless of success or failure of initialization */
1850                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1851                                      DRV_MSG_CODE_LOAD_DONE,
1852                                      0, &load_code, &param);
1853                 if (rc)
1854                         return rc;
1855                 if (mfw_rc) {
1856                         DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1857                         return mfw_rc;
1858                 }
1859
1860                 /* Check if there is a DID mismatch between nvm-cfg/efuse */
1861                 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1862                         DP_NOTICE(p_hwfn,
1863                                   "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1864
1865                 /* send DCBX attention request command */
1866                 DP_VERBOSE(p_hwfn,
1867                            QED_MSG_DCB,
1868                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1869                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1870                                      DRV_MSG_CODE_SET_DCBX,
1871                                      1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1872                                      &load_code, &param);
1873                 if (mfw_rc) {
1874                         DP_NOTICE(p_hwfn,
1875                                   "Failed to send DCBX attention request\n");
1876                         return mfw_rc;
1877                 }
1878
1879                 p_hwfn->hw_init_done = true;
1880         }
1881
1882         if (IS_PF(cdev)) {
1883                 p_hwfn = QED_LEADING_HWFN(cdev);
1884
1885                 /* Get pre-negotiated values for stag, bandwidth etc. */
1886                 DP_VERBOSE(p_hwfn,
1887                            QED_MSG_SPQ,
1888                            "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
1889                 drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET;
1890                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1891                                  DRV_MSG_CODE_GET_OEM_UPDATES,
1892                                  drv_mb_param, &resp, &param);
1893                 if (rc)
1894                         DP_NOTICE(p_hwfn,
1895                                   "Failed to send GET_OEM_UPDATES attention request\n");
1896
1897                 drv_mb_param = STORM_FW_VERSION;
1898                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1899                                  DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1900                                  drv_mb_param, &load_code, &param);
1901                 if (rc)
1902                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
1903
1904                 if (!b_default_mtu) {
1905                         rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1906                                                    p_hwfn->hw_info.mtu);
1907                         if (rc)
1908                                 DP_INFO(p_hwfn,
1909                                         "Failed to update default mtu\n");
1910                 }
1911
1912                 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1913                                                     p_hwfn->p_main_ptt,
1914                                                   QED_OV_DRIVER_STATE_DISABLED);
1915                 if (rc)
1916                         DP_INFO(p_hwfn, "Failed to update driver state\n");
1917
1918                 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1919                                                QED_OV_ESWITCH_NONE);
1920                 if (rc)
1921                         DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1922         }
1923
1924         return 0;
1925 }
1926
1927 #define QED_HW_STOP_RETRY_LIMIT (10)
1928 static void qed_hw_timers_stop(struct qed_dev *cdev,
1929                                struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1930 {
1931         int i;
1932
1933         /* close timers */
1934         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1935         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1936
1937         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1938                 if ((!qed_rd(p_hwfn, p_ptt,
1939                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1940                     (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1941                         break;
1942
1943                 /* Dependent on number of connection/tasks, possibly
1944                  * 1ms sleep is required between polls
1945                  */
1946                 usleep_range(1000, 2000);
1947         }
1948
1949         if (i < QED_HW_STOP_RETRY_LIMIT)
1950                 return;
1951
1952         DP_NOTICE(p_hwfn,
1953                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1954                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1955                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1956 }
1957
1958 void qed_hw_timers_stop_all(struct qed_dev *cdev)
1959 {
1960         int j;
1961
1962         for_each_hwfn(cdev, j) {
1963                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1964                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1965
1966                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1967         }
1968 }
1969
1970 int qed_hw_stop(struct qed_dev *cdev)
1971 {
1972         struct qed_hwfn *p_hwfn;
1973         struct qed_ptt *p_ptt;
1974         int rc, rc2 = 0;
1975         int j;
1976
1977         for_each_hwfn(cdev, j) {
1978                 p_hwfn = &cdev->hwfns[j];
1979                 p_ptt = p_hwfn->p_main_ptt;
1980
1981                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1982
1983                 if (IS_VF(cdev)) {
1984                         qed_vf_pf_int_cleanup(p_hwfn);
1985                         rc = qed_vf_pf_reset(p_hwfn);
1986                         if (rc) {
1987                                 DP_NOTICE(p_hwfn,
1988                                           "qed_vf_pf_reset failed. rc = %d.\n",
1989                                           rc);
1990                                 rc2 = -EINVAL;
1991                         }
1992                         continue;
1993                 }
1994
1995                 /* mark the hw as uninitialized... */
1996                 p_hwfn->hw_init_done = false;
1997
1998                 /* Send unload command to MCP */
1999                 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
2000                 if (rc) {
2001                         DP_NOTICE(p_hwfn,
2002                                   "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2003                                   rc);
2004                         rc2 = -EINVAL;
2005                 }
2006
2007                 qed_slowpath_irq_sync(p_hwfn);
2008
2009                 /* After this point no MFW attentions are expected, e.g. prevent
2010                  * race between pf stop and dcbx pf update.
2011                  */
2012                 rc = qed_sp_pf_stop(p_hwfn);
2013                 if (rc) {
2014                         DP_NOTICE(p_hwfn,
2015                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2016                                   rc);
2017                         rc2 = -EINVAL;
2018                 }
2019
2020                 qed_wr(p_hwfn, p_ptt,
2021                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2022
2023                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2024                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2025                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2026                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2027                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2028
2029                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
2030
2031                 /* Disable Attention Generation */
2032                 qed_int_igu_disable_int(p_hwfn, p_ptt);
2033
2034                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2035                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2036
2037                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2038
2039                 /* Need to wait 1ms to guarantee SBs are cleared */
2040                 usleep_range(1000, 2000);
2041
2042                 /* Disable PF in HW blocks */
2043                 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2044                 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2045
2046                 qed_mcp_unload_done(p_hwfn, p_ptt);
2047                 if (rc) {
2048                         DP_NOTICE(p_hwfn,
2049                                   "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2050                                   rc);
2051                         rc2 = -EINVAL;
2052                 }
2053         }
2054
2055         if (IS_PF(cdev)) {
2056                 p_hwfn = QED_LEADING_HWFN(cdev);
2057                 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
2058
2059                 /* Disable DMAE in PXP - in CMT, this should only be done for
2060                  * first hw-function, and only after all transactions have
2061                  * stopped for all active hw-functions.
2062                  */
2063                 rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false);
2064                 if (rc) {
2065                         DP_NOTICE(p_hwfn,
2066                                   "qed_change_pci_hwfn failed. rc = %d.\n", rc);
2067                         rc2 = -EINVAL;
2068                 }
2069         }
2070
2071         return rc2;
2072 }
2073
2074 int qed_hw_stop_fastpath(struct qed_dev *cdev)
2075 {
2076         int j;
2077
2078         for_each_hwfn(cdev, j) {
2079                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
2080                 struct qed_ptt *p_ptt;
2081
2082                 if (IS_VF(cdev)) {
2083                         qed_vf_pf_int_cleanup(p_hwfn);
2084                         continue;
2085                 }
2086                 p_ptt = qed_ptt_acquire(p_hwfn);
2087                 if (!p_ptt)
2088                         return -EAGAIN;
2089
2090                 DP_VERBOSE(p_hwfn,
2091                            NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
2092
2093                 qed_wr(p_hwfn, p_ptt,
2094                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2095
2096                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2097                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2098                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2099                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2100                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2101
2102                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2103
2104                 /* Need to wait 1ms to guarantee SBs are cleared */
2105                 usleep_range(1000, 2000);
2106                 qed_ptt_release(p_hwfn, p_ptt);
2107         }
2108
2109         return 0;
2110 }
2111
2112 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
2113 {
2114         struct qed_ptt *p_ptt;
2115
2116         if (IS_VF(p_hwfn->cdev))
2117                 return 0;
2118
2119         p_ptt = qed_ptt_acquire(p_hwfn);
2120         if (!p_ptt)
2121                 return -EAGAIN;
2122
2123         if (p_hwfn->p_rdma_info &&
2124             p_hwfn->p_rdma_info->active && p_hwfn->b_rdma_enabled_in_prs)
2125                 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
2126
2127         /* Re-open incoming traffic */
2128         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2129         qed_ptt_release(p_hwfn, p_ptt);
2130
2131         return 0;
2132 }
2133
2134 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2135 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
2136 {
2137         qed_ptt_pool_free(p_hwfn);
2138         kfree(p_hwfn->hw_info.p_igu_info);
2139         p_hwfn->hw_info.p_igu_info = NULL;
2140 }
2141
2142 /* Setup bar access */
2143 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
2144 {
2145         /* clear indirect access */
2146         if (QED_IS_AH(p_hwfn->cdev)) {
2147                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2148                        PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
2149                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2150                        PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
2151                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2152                        PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
2153                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2154                        PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
2155         } else {
2156                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2157                        PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2158                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2159                        PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2160                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2161                        PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2162                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2163                        PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2164         }
2165
2166         /* Clean Previous errors if such exist */
2167         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2168                PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2169
2170         /* enable internal target-read */
2171         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2172                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2173 }
2174
2175 static void get_function_id(struct qed_hwfn *p_hwfn)
2176 {
2177         /* ME Register */
2178         p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
2179                                                   PXP_PF_ME_OPAQUE_ADDR);
2180
2181         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2182
2183         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2184         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2185                                       PXP_CONCRETE_FID_PFID);
2186         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2187                                     PXP_CONCRETE_FID_PORT);
2188
2189         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2190                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2191                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2192 }
2193
2194 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
2195 {
2196         u32 *feat_num = p_hwfn->hw_info.feat_num;
2197         struct qed_sb_cnt_info sb_cnt;
2198         u32 non_l2_sbs = 0;
2199
2200         memset(&sb_cnt, 0, sizeof(sb_cnt));
2201         qed_int_get_num_sbs(p_hwfn, &sb_cnt);
2202
2203         if (IS_ENABLED(CONFIG_QED_RDMA) &&
2204             QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2205                 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
2206                  * the status blocks equally between L2 / RoCE but with
2207                  * consideration as to how many l2 queues / cnqs we have.
2208                  */
2209                 feat_num[QED_RDMA_CNQ] =
2210                         min_t(u32, sb_cnt.cnt / 2,
2211                               RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
2212
2213                 non_l2_sbs = feat_num[QED_RDMA_CNQ];
2214         }
2215         if (QED_IS_L2_PERSONALITY(p_hwfn)) {
2216                 /* Start by allocating VF queues, then PF's */
2217                 feat_num[QED_VF_L2_QUE] = min_t(u32,
2218                                                 RESC_NUM(p_hwfn, QED_L2_QUEUE),
2219                                                 sb_cnt.iov_cnt);
2220                 feat_num[QED_PF_L2_QUE] = min_t(u32,
2221                                                 sb_cnt.cnt - non_l2_sbs,
2222                                                 RESC_NUM(p_hwfn,
2223                                                          QED_L2_QUEUE) -
2224                                                 FEAT_NUM(p_hwfn,
2225                                                          QED_VF_L2_QUE));
2226         }
2227
2228         if (QED_IS_FCOE_PERSONALITY(p_hwfn))
2229                 feat_num[QED_FCOE_CQ] =  min_t(u32, sb_cnt.cnt,
2230                                                RESC_NUM(p_hwfn,
2231                                                         QED_CMDQS_CQS));
2232
2233         if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
2234                 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
2235                                                RESC_NUM(p_hwfn,
2236                                                         QED_CMDQS_CQS));
2237         DP_VERBOSE(p_hwfn,
2238                    NETIF_MSG_PROBE,
2239                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
2240                    (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2241                    (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2242                    (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
2243                    (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
2244                    (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
2245                    (int)sb_cnt.cnt);
2246 }
2247
2248 const char *qed_hw_get_resc_name(enum qed_resources res_id)
2249 {
2250         switch (res_id) {
2251         case QED_L2_QUEUE:
2252                 return "L2_QUEUE";
2253         case QED_VPORT:
2254                 return "VPORT";
2255         case QED_RSS_ENG:
2256                 return "RSS_ENG";
2257         case QED_PQ:
2258                 return "PQ";
2259         case QED_RL:
2260                 return "RL";
2261         case QED_MAC:
2262                 return "MAC";
2263         case QED_VLAN:
2264                 return "VLAN";
2265         case QED_RDMA_CNQ_RAM:
2266                 return "RDMA_CNQ_RAM";
2267         case QED_ILT:
2268                 return "ILT";
2269         case QED_LL2_QUEUE:
2270                 return "LL2_QUEUE";
2271         case QED_CMDQS_CQS:
2272                 return "CMDQS_CQS";
2273         case QED_RDMA_STATS_QUEUE:
2274                 return "RDMA_STATS_QUEUE";
2275         case QED_BDQ:
2276                 return "BDQ";
2277         case QED_SB:
2278                 return "SB";
2279         default:
2280                 return "UNKNOWN_RESOURCE";
2281         }
2282 }
2283
2284 static int
2285 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2286                             struct qed_ptt *p_ptt,
2287                             enum qed_resources res_id,
2288                             u32 resc_max_val, u32 *p_mcp_resp)
2289 {
2290         int rc;
2291
2292         rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2293                                       resc_max_val, p_mcp_resp);
2294         if (rc) {
2295                 DP_NOTICE(p_hwfn,
2296                           "MFW response failure for a max value setting of resource %d [%s]\n",
2297                           res_id, qed_hw_get_resc_name(res_id));
2298                 return rc;
2299         }
2300
2301         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2302                 DP_INFO(p_hwfn,
2303                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2304                         res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2305
2306         return 0;
2307 }
2308
2309 static int
2310 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2311 {
2312         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2313         u32 resc_max_val, mcp_resp;
2314         u8 res_id;
2315         int rc;
2316
2317         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2318                 switch (res_id) {
2319                 case QED_LL2_QUEUE:
2320                         resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2321                         break;
2322                 case QED_RDMA_CNQ_RAM:
2323                         /* No need for a case for QED_CMDQS_CQS since
2324                          * CNQ/CMDQS are the same resource.
2325                          */
2326                         resc_max_val = NUM_OF_GLOBAL_QUEUES;
2327                         break;
2328                 case QED_RDMA_STATS_QUEUE:
2329                         resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2330                             : RDMA_NUM_STATISTIC_COUNTERS_BB;
2331                         break;
2332                 case QED_BDQ:
2333                         resc_max_val = BDQ_NUM_RESOURCES;
2334                         break;
2335                 default:
2336                         continue;
2337                 }
2338
2339                 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2340                                                  resc_max_val, &mcp_resp);
2341                 if (rc)
2342                         return rc;
2343
2344                 /* There's no point to continue to the next resource if the
2345                  * command is not supported by the MFW.
2346                  * We do continue if the command is supported but the resource
2347                  * is unknown to the MFW. Such a resource will be later
2348                  * configured with the default allocation values.
2349                  */
2350                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2351                         return -EINVAL;
2352         }
2353
2354         return 0;
2355 }
2356
2357 static
2358 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2359                          enum qed_resources res_id,
2360                          u32 *p_resc_num, u32 *p_resc_start)
2361 {
2362         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2363         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2364
2365         switch (res_id) {
2366         case QED_L2_QUEUE:
2367                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2368                                MAX_NUM_L2_QUEUES_BB) / num_funcs;
2369                 break;
2370         case QED_VPORT:
2371                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2372                                MAX_NUM_VPORTS_BB) / num_funcs;
2373                 break;
2374         case QED_RSS_ENG:
2375                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2376                                ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2377                 break;
2378         case QED_PQ:
2379                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2380                                MAX_QM_TX_QUEUES_BB) / num_funcs;
2381                 *p_resc_num &= ~0x7;    /* The granularity of the PQs is 8 */
2382                 break;
2383         case QED_RL:
2384                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2385                 break;
2386         case QED_MAC:
2387         case QED_VLAN:
2388                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2389                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2390                 break;
2391         case QED_ILT:
2392                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2393                                PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2394                 break;
2395         case QED_LL2_QUEUE:
2396                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2397                 break;
2398         case QED_RDMA_CNQ_RAM:
2399         case QED_CMDQS_CQS:
2400                 /* CNQ/CMDQS are the same resource */
2401                 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
2402                 break;
2403         case QED_RDMA_STATS_QUEUE:
2404                 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2405                                RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2406                 break;
2407         case QED_BDQ:
2408                 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2409                     p_hwfn->hw_info.personality != QED_PCI_FCOE)
2410                         *p_resc_num = 0;
2411                 else
2412                         *p_resc_num = 1;
2413                 break;
2414         case QED_SB:
2415                 /* Since we want its value to reflect whether MFW supports
2416                  * the new scheme, have a default of 0.
2417                  */
2418                 *p_resc_num = 0;
2419                 break;
2420         default:
2421                 return -EINVAL;
2422         }
2423
2424         switch (res_id) {
2425         case QED_BDQ:
2426                 if (!*p_resc_num)
2427                         *p_resc_start = 0;
2428                 else if (p_hwfn->cdev->num_ports_in_engine == 4)
2429                         *p_resc_start = p_hwfn->port_id;
2430                 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2431                         *p_resc_start = p_hwfn->port_id;
2432                 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2433                         *p_resc_start = p_hwfn->port_id + 2;
2434                 break;
2435         default:
2436                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2437                 break;
2438         }
2439
2440         return 0;
2441 }
2442
2443 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2444                                   enum qed_resources res_id)
2445 {
2446         u32 dflt_resc_num = 0, dflt_resc_start = 0;
2447         u32 mcp_resp, *p_resc_num, *p_resc_start;
2448         int rc;
2449
2450         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2451         p_resc_start = &RESC_START(p_hwfn, res_id);
2452
2453         rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2454                                   &dflt_resc_start);
2455         if (rc) {
2456                 DP_ERR(p_hwfn,
2457                        "Failed to get default amount for resource %d [%s]\n",
2458                        res_id, qed_hw_get_resc_name(res_id));
2459                 return rc;
2460         }
2461
2462         rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2463                                    &mcp_resp, p_resc_num, p_resc_start);
2464         if (rc) {
2465                 DP_NOTICE(p_hwfn,
2466                           "MFW response failure for an allocation request for resource %d [%s]\n",
2467                           res_id, qed_hw_get_resc_name(res_id));
2468                 return rc;
2469         }
2470
2471         /* Default driver values are applied in the following cases:
2472          * - The resource allocation MB command is not supported by the MFW
2473          * - There is an internal error in the MFW while processing the request
2474          * - The resource ID is unknown to the MFW
2475          */
2476         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2477                 DP_INFO(p_hwfn,
2478                         "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2479                         res_id,
2480                         qed_hw_get_resc_name(res_id),
2481                         mcp_resp, dflt_resc_num, dflt_resc_start);
2482                 *p_resc_num = dflt_resc_num;
2483                 *p_resc_start = dflt_resc_start;
2484                 goto out;
2485         }
2486
2487 out:
2488         /* PQs have to divide by 8 [that's the HW granularity].
2489          * Reduce number so it would fit.
2490          */
2491         if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2492                 DP_INFO(p_hwfn,
2493                         "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2494                         *p_resc_num,
2495                         (*p_resc_num) & ~0x7,
2496                         *p_resc_start, (*p_resc_start) & ~0x7);
2497                 *p_resc_num &= ~0x7;
2498                 *p_resc_start &= ~0x7;
2499         }
2500
2501         return 0;
2502 }
2503
2504 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
2505 {
2506         int rc;
2507         u8 res_id;
2508
2509         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2510                 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2511                 if (rc)
2512                         return rc;
2513         }
2514
2515         return 0;
2516 }
2517
2518 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2519 {
2520         struct qed_resc_unlock_params resc_unlock_params;
2521         struct qed_resc_lock_params resc_lock_params;
2522         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2523         u8 res_id;
2524         int rc;
2525
2526         /* Setting the max values of the soft resources and the following
2527          * resources allocation queries should be atomic. Since several PFs can
2528          * run in parallel - a resource lock is needed.
2529          * If either the resource lock or resource set value commands are not
2530          * supported - skip the the max values setting, release the lock if
2531          * needed, and proceed to the queries. Other failures, including a
2532          * failure to acquire the lock, will cause this function to fail.
2533          */
2534         qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
2535                                        QED_RESC_LOCK_RESC_ALLOC, false);
2536
2537         rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2538         if (rc && rc != -EINVAL) {
2539                 return rc;
2540         } else if (rc == -EINVAL) {
2541                 DP_INFO(p_hwfn,
2542                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2543         } else if (!rc && !resc_lock_params.b_granted) {
2544                 DP_NOTICE(p_hwfn,
2545                           "Failed to acquire the resource lock for the resource allocation commands\n");
2546                 return -EBUSY;
2547         } else {
2548                 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2549                 if (rc && rc != -EINVAL) {
2550                         DP_NOTICE(p_hwfn,
2551                                   "Failed to set the max values of the soft resources\n");
2552                         goto unlock_and_exit;
2553                 } else if (rc == -EINVAL) {
2554                         DP_INFO(p_hwfn,
2555                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2556                         rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2557                                                  &resc_unlock_params);
2558                         if (rc)
2559                                 DP_INFO(p_hwfn,
2560                                         "Failed to release the resource lock for the resource allocation commands\n");
2561                 }
2562         }
2563
2564         rc = qed_hw_set_resc_info(p_hwfn);
2565         if (rc)
2566                 goto unlock_and_exit;
2567
2568         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2569                 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2570                 if (rc)
2571                         DP_INFO(p_hwfn,
2572                                 "Failed to release the resource lock for the resource allocation commands\n");
2573         }
2574
2575         /* Sanity for ILT */
2576         if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2577             (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2578                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2579                           RESC_START(p_hwfn, QED_ILT),
2580                           RESC_END(p_hwfn, QED_ILT) - 1);
2581                 return -EINVAL;
2582         }
2583
2584         /* This will also learn the number of SBs from MFW */
2585         if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
2586                 return -EINVAL;
2587
2588         qed_hw_set_feat(p_hwfn);
2589
2590         for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2591                 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2592                            qed_hw_get_resc_name(res_id),
2593                            RESC_NUM(p_hwfn, res_id),
2594                            RESC_START(p_hwfn, res_id));
2595
2596         return 0;
2597
2598 unlock_and_exit:
2599         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2600                 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2601         return rc;
2602 }
2603
2604 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2605 {
2606         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2607         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2608         struct qed_mcp_link_capabilities *p_caps;
2609         struct qed_mcp_link_params *link;
2610
2611         /* Read global nvm_cfg address */
2612         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2613
2614         /* Verify MCP has initialized it */
2615         if (!nvm_cfg_addr) {
2616                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2617                 return -EINVAL;
2618         }
2619
2620         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2621         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2622
2623         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2624                offsetof(struct nvm_cfg1, glob) +
2625                offsetof(struct nvm_cfg1_glob, core_cfg);
2626
2627         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2628
2629         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2630                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2631         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2632                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
2633                 break;
2634         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2635                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
2636                 break;
2637         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2638                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
2639                 break;
2640         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2641                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
2642                 break;
2643         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2644                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
2645                 break;
2646         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2647                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
2648                 break;
2649         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2650                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
2651                 break;
2652         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2653                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
2654                 break;
2655         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2656                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
2657                 break;
2658         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2659                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
2660                 break;
2661         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2662                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
2663                 break;
2664         default:
2665                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
2666                 break;
2667         }
2668
2669         /* Read default link configuration */
2670         link = &p_hwfn->mcp_info->link_input;
2671         p_caps = &p_hwfn->mcp_info->link_capabilities;
2672         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2673                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2674         link_temp = qed_rd(p_hwfn, p_ptt,
2675                            port_cfg_addr +
2676                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
2677         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2678         link->speed.advertised_speeds = link_temp;
2679
2680         link_temp = link->speed.advertised_speeds;
2681         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2682
2683         link_temp = qed_rd(p_hwfn, p_ptt,
2684                            port_cfg_addr +
2685                            offsetof(struct nvm_cfg1_port, link_settings));
2686         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2687                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2688         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2689                 link->speed.autoneg = true;
2690                 break;
2691         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2692                 link->speed.forced_speed = 1000;
2693                 break;
2694         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2695                 link->speed.forced_speed = 10000;
2696                 break;
2697         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2698                 link->speed.forced_speed = 25000;
2699                 break;
2700         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2701                 link->speed.forced_speed = 40000;
2702                 break;
2703         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2704                 link->speed.forced_speed = 50000;
2705                 break;
2706         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2707                 link->speed.forced_speed = 100000;
2708                 break;
2709         default:
2710                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
2711         }
2712
2713         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2714                 link->speed.autoneg;
2715
2716         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2717         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2718         link->pause.autoneg = !!(link_temp &
2719                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2720         link->pause.forced_rx = !!(link_temp &
2721                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2722         link->pause.forced_tx = !!(link_temp &
2723                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2724         link->loopback_mode = 0;
2725
2726         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
2727                 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
2728                                    offsetof(struct nvm_cfg1_port, ext_phy));
2729                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
2730                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
2731                 p_caps->default_eee = QED_MCP_EEE_ENABLED;
2732                 link->eee.enable = true;
2733                 switch (link_temp) {
2734                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
2735                         p_caps->default_eee = QED_MCP_EEE_DISABLED;
2736                         link->eee.enable = false;
2737                         break;
2738                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
2739                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
2740                         break;
2741                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
2742                         p_caps->eee_lpi_timer =
2743                             EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
2744                         break;
2745                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
2746                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
2747                         break;
2748                 }
2749
2750                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
2751                 link->eee.tx_lpi_enable = link->eee.enable;
2752                 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
2753         } else {
2754                 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
2755         }
2756
2757         DP_VERBOSE(p_hwfn,
2758                    NETIF_MSG_LINK,
2759                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
2760                    link->speed.forced_speed,
2761                    link->speed.advertised_speeds,
2762                    link->speed.autoneg,
2763                    link->pause.autoneg,
2764                    p_caps->default_eee, p_caps->eee_lpi_timer);
2765
2766         if (IS_LEAD_HWFN(p_hwfn)) {
2767                 struct qed_dev *cdev = p_hwfn->cdev;
2768
2769                 /* Read Multi-function information from shmem */
2770                 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2771                        offsetof(struct nvm_cfg1, glob) +
2772                        offsetof(struct nvm_cfg1_glob, generic_cont0);
2773
2774                 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
2775
2776                 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2777                           NVM_CFG1_GLOB_MF_MODE_OFFSET;
2778
2779                 switch (mf_mode) {
2780                 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2781                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
2782                         break;
2783                 case NVM_CFG1_GLOB_MF_MODE_UFP:
2784                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
2785                                         BIT(QED_MF_LLH_PROTO_CLSS) |
2786                                         BIT(QED_MF_UFP_SPECIFIC) |
2787                                         BIT(QED_MF_8021Q_TAGGING);
2788                         break;
2789                 case NVM_CFG1_GLOB_MF_MODE_BD:
2790                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
2791                                         BIT(QED_MF_LLH_PROTO_CLSS) |
2792                                         BIT(QED_MF_8021AD_TAGGING);
2793                         break;
2794                 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2795                         cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
2796                                         BIT(QED_MF_LLH_PROTO_CLSS) |
2797                                         BIT(QED_MF_LL2_NON_UNICAST) |
2798                                         BIT(QED_MF_INTER_PF_SWITCH);
2799                         break;
2800                 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2801                         cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
2802                                         BIT(QED_MF_LLH_PROTO_CLSS) |
2803                                         BIT(QED_MF_LL2_NON_UNICAST);
2804                         if (QED_IS_BB(p_hwfn->cdev))
2805                                 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
2806                         break;
2807                 }
2808
2809                 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
2810                         cdev->mf_bits);
2811         }
2812
2813         DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
2814                 p_hwfn->cdev->mf_bits);
2815
2816         /* Read device capabilities information from shmem */
2817         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2818                 offsetof(struct nvm_cfg1, glob) +
2819                 offsetof(struct nvm_cfg1_glob, device_capabilities);
2820
2821         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
2822         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2823                 __set_bit(QED_DEV_CAP_ETH,
2824                           &p_hwfn->hw_info.device_capabilities);
2825         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2826                 __set_bit(QED_DEV_CAP_FCOE,
2827                           &p_hwfn->hw_info.device_capabilities);
2828         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2829                 __set_bit(QED_DEV_CAP_ISCSI,
2830                           &p_hwfn->hw_info.device_capabilities);
2831         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2832                 __set_bit(QED_DEV_CAP_ROCE,
2833                           &p_hwfn->hw_info.device_capabilities);
2834
2835         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2836 }
2837
2838 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2839 {
2840         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2841         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2842         struct qed_dev *cdev = p_hwfn->cdev;
2843
2844         num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2845
2846         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2847          * in the other bits are selected.
2848          * Bits 1-15 are for functions 1-15, respectively, and their value is
2849          * '0' only for enabled functions (function 0 always exists and
2850          * enabled).
2851          * In case of CMT, only the "even" functions are enabled, and thus the
2852          * number of functions for both hwfns is learnt from the same bits.
2853          */
2854         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2855
2856         if (reg_function_hide & 0x1) {
2857                 if (QED_IS_BB(cdev)) {
2858                         if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
2859                                 num_funcs = 0;
2860                                 eng_mask = 0xaaaa;
2861                         } else {
2862                                 num_funcs = 1;
2863                                 eng_mask = 0x5554;
2864                         }
2865                 } else {
2866                         num_funcs = 1;
2867                         eng_mask = 0xfffe;
2868                 }
2869
2870                 /* Get the number of the enabled functions on the engine */
2871                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2872                 while (tmp) {
2873                         if (tmp & 0x1)
2874                                 num_funcs++;
2875                         tmp >>= 0x1;
2876                 }
2877
2878                 /* Get the PF index within the enabled functions */
2879                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2880                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2881                 while (tmp) {
2882                         if (tmp & 0x1)
2883                                 enabled_func_idx--;
2884                         tmp >>= 0x1;
2885                 }
2886         }
2887
2888         p_hwfn->num_funcs_on_engine = num_funcs;
2889         p_hwfn->enabled_func_idx = enabled_func_idx;
2890
2891         DP_VERBOSE(p_hwfn,
2892                    NETIF_MSG_PROBE,
2893                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2894                    p_hwfn->rel_pf_id,
2895                    p_hwfn->abs_pf_id,
2896                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2897 }
2898
2899 static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
2900                                     struct qed_ptt *p_ptt)
2901 {
2902         u32 port_mode;
2903
2904         port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
2905
2906         if (port_mode < 3) {
2907                 p_hwfn->cdev->num_ports_in_engine = 1;
2908         } else if (port_mode <= 5) {
2909                 p_hwfn->cdev->num_ports_in_engine = 2;
2910         } else {
2911                 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
2912                           p_hwfn->cdev->num_ports_in_engine);
2913
2914                 /* Default num_ports_in_engine to something */
2915                 p_hwfn->cdev->num_ports_in_engine = 1;
2916         }
2917 }
2918
2919 static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
2920                                     struct qed_ptt *p_ptt)
2921 {
2922         u32 port;
2923         int i;
2924
2925         p_hwfn->cdev->num_ports_in_engine = 0;
2926
2927         for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2928                 port = qed_rd(p_hwfn, p_ptt,
2929                               CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2930                 if (port & 1)
2931                         p_hwfn->cdev->num_ports_in_engine++;
2932         }
2933
2934         if (!p_hwfn->cdev->num_ports_in_engine) {
2935                 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
2936
2937                 /* Default num_ports_in_engine to something */
2938                 p_hwfn->cdev->num_ports_in_engine = 1;
2939         }
2940 }
2941
2942 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2943 {
2944         if (QED_IS_BB(p_hwfn->cdev))
2945                 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
2946         else
2947                 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
2948 }
2949
2950 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2951 {
2952         struct qed_mcp_link_capabilities *p_caps;
2953         u32 eee_status;
2954
2955         p_caps = &p_hwfn->mcp_info->link_capabilities;
2956         if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
2957                 return;
2958
2959         p_caps->eee_speed_caps = 0;
2960         eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
2961                             offsetof(struct public_port, eee_status));
2962         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
2963                         EEE_SUPPORTED_SPEED_OFFSET;
2964
2965         if (eee_status & EEE_1G_SUPPORTED)
2966                 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
2967         if (eee_status & EEE_10G_ADV)
2968                 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
2969 }
2970
2971 static int
2972 qed_get_hw_info(struct qed_hwfn *p_hwfn,
2973                 struct qed_ptt *p_ptt,
2974                 enum qed_pci_personality personality)
2975 {
2976         int rc;
2977
2978         /* Since all information is common, only first hwfns should do this */
2979         if (IS_LEAD_HWFN(p_hwfn)) {
2980                 rc = qed_iov_hw_info(p_hwfn);
2981                 if (rc)
2982                         return rc;
2983         }
2984
2985         qed_hw_info_port_num(p_hwfn, p_ptt);
2986
2987         qed_mcp_get_capabilities(p_hwfn, p_ptt);
2988
2989         qed_hw_get_nvm_info(p_hwfn, p_ptt);
2990
2991         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
2992         if (rc)
2993                 return rc;
2994
2995         if (qed_mcp_is_init(p_hwfn))
2996                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
2997                                 p_hwfn->mcp_info->func_info.mac);
2998         else
2999                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
3000
3001         if (qed_mcp_is_init(p_hwfn)) {
3002                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
3003                         p_hwfn->hw_info.ovlan =
3004                                 p_hwfn->mcp_info->func_info.ovlan;
3005
3006                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
3007
3008                 qed_get_eee_caps(p_hwfn, p_ptt);
3009
3010                 qed_mcp_read_ufp_config(p_hwfn, p_ptt);
3011         }
3012
3013         if (qed_mcp_is_init(p_hwfn)) {
3014                 enum qed_pci_personality protocol;
3015
3016                 protocol = p_hwfn->mcp_info->func_info.protocol;
3017                 p_hwfn->hw_info.personality = protocol;
3018         }
3019
3020         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
3021                 p_hwfn->hw_info.multi_tc_roce_en = 1;
3022
3023         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3024         p_hwfn->hw_info.num_active_tc = 1;
3025
3026         qed_get_num_funcs(p_hwfn, p_ptt);
3027
3028         if (qed_mcp_is_init(p_hwfn))
3029                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3030
3031         return qed_hw_get_resc(p_hwfn, p_ptt);
3032 }
3033
3034 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3035 {
3036         struct qed_dev *cdev = p_hwfn->cdev;
3037         u16 device_id_mask;
3038         u32 tmp;
3039
3040         /* Read Vendor Id / Device Id */
3041         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
3042         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
3043
3044         /* Determine type */
3045         device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
3046         switch (device_id_mask) {
3047         case QED_DEV_ID_MASK_BB:
3048                 cdev->type = QED_DEV_TYPE_BB;
3049                 break;
3050         case QED_DEV_ID_MASK_AH:
3051                 cdev->type = QED_DEV_TYPE_AH;
3052                 break;
3053         default:
3054                 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
3055                 return -EBUSY;
3056         }
3057
3058         cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
3059         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
3060
3061         MASK_FIELD(CHIP_REV, cdev->chip_rev);
3062
3063         /* Learn number of HW-functions */
3064         tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3065
3066         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3067                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
3068                 cdev->num_hwfns = 2;
3069         } else {
3070                 cdev->num_hwfns = 1;
3071         }
3072
3073         cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
3074                                     MISCS_REG_CHIP_TEST_REG) >> 4;
3075         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
3076         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
3077         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
3078
3079         DP_INFO(cdev->hwfns,
3080                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3081                 QED_IS_BB(cdev) ? "BB" : "AH",
3082                 'A' + cdev->chip_rev,
3083                 (int)cdev->chip_metal,
3084                 cdev->chip_num, cdev->chip_rev,
3085                 cdev->chip_bond_id, cdev->chip_metal);
3086
3087         return 0;
3088 }
3089
3090 static void qed_nvm_info_free(struct qed_hwfn *p_hwfn)
3091 {
3092         kfree(p_hwfn->nvm_info.image_att);
3093         p_hwfn->nvm_info.image_att = NULL;
3094 }
3095
3096 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
3097                                  void __iomem *p_regview,
3098                                  void __iomem *p_doorbells,
3099                                  u64 db_phys_addr,
3100                                  enum qed_pci_personality personality)
3101 {
3102         int rc = 0;
3103
3104         /* Split PCI bars evenly between hwfns */
3105         p_hwfn->regview = p_regview;
3106         p_hwfn->doorbells = p_doorbells;
3107         p_hwfn->db_phys_addr = db_phys_addr;
3108
3109         if (IS_VF(p_hwfn->cdev))
3110                 return qed_vf_hw_prepare(p_hwfn);
3111
3112         /* Validate that chip access is feasible */
3113         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3114                 DP_ERR(p_hwfn,
3115                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3116                 return -EINVAL;
3117         }
3118
3119         get_function_id(p_hwfn);
3120
3121         /* Allocate PTT pool */
3122         rc = qed_ptt_pool_alloc(p_hwfn);
3123         if (rc)
3124                 goto err0;
3125
3126         /* Allocate the main PTT */
3127         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3128
3129         /* First hwfn learns basic information, e.g., number of hwfns */
3130         if (!p_hwfn->my_id) {
3131                 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
3132                 if (rc)
3133                         goto err1;
3134         }
3135
3136         qed_hw_hwfn_prepare(p_hwfn);
3137
3138         /* Initialize MCP structure */
3139         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3140         if (rc) {
3141                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
3142                 goto err1;
3143         }
3144
3145         /* Read the device configuration information from the HW and SHMEM */
3146         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
3147         if (rc) {
3148                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
3149                 goto err2;
3150         }
3151
3152         /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
3153          * is called as it sets the ports number in an engine.
3154          */
3155         if (IS_LEAD_HWFN(p_hwfn)) {
3156                 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3157                 if (rc)
3158                         DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
3159         }
3160
3161         /* NVRAM info initialization and population */
3162         if (IS_LEAD_HWFN(p_hwfn)) {
3163                 rc = qed_mcp_nvm_info_populate(p_hwfn);
3164                 if (rc) {
3165                         DP_NOTICE(p_hwfn,
3166                                   "Failed to populate nvm info shadow\n");
3167                         goto err2;
3168                 }
3169         }
3170
3171         /* Allocate the init RT array and initialize the init-ops engine */
3172         rc = qed_init_alloc(p_hwfn);
3173         if (rc)
3174                 goto err3;
3175
3176         return rc;
3177 err3:
3178         if (IS_LEAD_HWFN(p_hwfn))
3179                 qed_nvm_info_free(p_hwfn);
3180 err2:
3181         if (IS_LEAD_HWFN(p_hwfn))
3182                 qed_iov_free_hw_info(p_hwfn->cdev);
3183         qed_mcp_free(p_hwfn);
3184 err1:
3185         qed_hw_hwfn_free(p_hwfn);
3186 err0:
3187         return rc;
3188 }
3189
3190 int qed_hw_prepare(struct qed_dev *cdev,
3191                    int personality)
3192 {
3193         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3194         int rc;
3195
3196         /* Store the precompiled init data ptrs */
3197         if (IS_PF(cdev))
3198                 qed_init_iro_array(cdev);
3199
3200         /* Initialize the first hwfn - will learn number of hwfns */
3201         rc = qed_hw_prepare_single(p_hwfn,
3202                                    cdev->regview,
3203                                    cdev->doorbells,
3204                                    cdev->db_phys_addr,
3205                                    personality);
3206         if (rc)
3207                 return rc;
3208
3209         personality = p_hwfn->hw_info.personality;
3210
3211         /* Initialize the rest of the hwfns */
3212         if (cdev->num_hwfns > 1) {
3213                 void __iomem *p_regview, *p_doorbell;
3214                 u64 db_phys_addr;
3215                 u32 offset;
3216
3217                 /* adjust bar offset for second engine */
3218                 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3219                                          BAR_ID_0) / 2;
3220                 p_regview = cdev->regview + offset;
3221
3222                 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3223                                          BAR_ID_1) / 2;
3224
3225                 p_doorbell = cdev->doorbells + offset;
3226
3227                 db_phys_addr = cdev->db_phys_addr + offset;
3228
3229                 /* prepare second hw function */
3230                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
3231                                            p_doorbell, db_phys_addr,
3232                                            personality);
3233
3234                 /* in case of error, need to free the previously
3235                  * initiliazed hwfn 0.
3236                  */
3237                 if (rc) {
3238                         if (IS_PF(cdev)) {
3239                                 qed_init_free(p_hwfn);
3240                                 qed_nvm_info_free(p_hwfn);
3241                                 qed_mcp_free(p_hwfn);
3242                                 qed_hw_hwfn_free(p_hwfn);
3243                         }
3244                 }
3245         }
3246
3247         return rc;
3248 }
3249
3250 void qed_hw_remove(struct qed_dev *cdev)
3251 {
3252         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3253         int i;
3254
3255         if (IS_PF(cdev))
3256                 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3257                                                QED_OV_DRIVER_STATE_NOT_LOADED);
3258
3259         for_each_hwfn(cdev, i) {
3260                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3261
3262                 if (IS_VF(cdev)) {
3263                         qed_vf_pf_release(p_hwfn);
3264                         continue;
3265                 }
3266
3267                 qed_init_free(p_hwfn);
3268                 qed_hw_hwfn_free(p_hwfn);
3269                 qed_mcp_free(p_hwfn);
3270         }
3271
3272         qed_iov_free_hw_info(cdev);
3273
3274         qed_nvm_info_free(p_hwfn);
3275 }
3276
3277 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
3278                                     struct qed_chain *p_chain)
3279 {
3280         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
3281         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3282         struct qed_chain_next *p_next;
3283         u32 size, i;
3284
3285         if (!p_virt)
3286                 return;
3287
3288         size = p_chain->elem_size * p_chain->usable_per_page;
3289
3290         for (i = 0; i < p_chain->page_cnt; i++) {
3291                 if (!p_virt)
3292                         break;
3293
3294                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
3295                 p_virt_next = p_next->next_virt;
3296                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3297
3298                 dma_free_coherent(&cdev->pdev->dev,
3299                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
3300
3301                 p_virt = p_virt_next;
3302                 p_phys = p_phys_next;
3303         }
3304 }
3305
3306 static void qed_chain_free_single(struct qed_dev *cdev,
3307                                   struct qed_chain *p_chain)
3308 {
3309         if (!p_chain->p_virt_addr)
3310                 return;
3311
3312         dma_free_coherent(&cdev->pdev->dev,
3313                           QED_CHAIN_PAGE_SIZE,
3314                           p_chain->p_virt_addr, p_chain->p_phys_addr);
3315 }
3316
3317 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3318 {
3319         struct addr_tbl_entry *pp_addr_tbl = p_chain->pbl.pp_addr_tbl;
3320         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3321
3322         if (!pp_addr_tbl)
3323                 return;
3324
3325         for (i = 0; i < page_cnt; i++) {
3326                 if (!pp_addr_tbl[i].virt_addr || !pp_addr_tbl[i].dma_map)
3327                         break;
3328
3329                 dma_free_coherent(&cdev->pdev->dev,
3330                                   QED_CHAIN_PAGE_SIZE,
3331                                   pp_addr_tbl[i].virt_addr,
3332                                   pp_addr_tbl[i].dma_map);
3333         }
3334
3335         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3336
3337         if (!p_chain->b_external_pbl)
3338                 dma_free_coherent(&cdev->pdev->dev,
3339                                   pbl_size,
3340                                   p_chain->pbl_sp.p_virt_table,
3341                                   p_chain->pbl_sp.p_phys_table);
3342
3343         vfree(p_chain->pbl.pp_addr_tbl);
3344         p_chain->pbl.pp_addr_tbl = NULL;
3345 }
3346
3347 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3348 {
3349         switch (p_chain->mode) {
3350         case QED_CHAIN_MODE_NEXT_PTR:
3351                 qed_chain_free_next_ptr(cdev, p_chain);
3352                 break;
3353         case QED_CHAIN_MODE_SINGLE:
3354                 qed_chain_free_single(cdev, p_chain);
3355                 break;
3356         case QED_CHAIN_MODE_PBL:
3357                 qed_chain_free_pbl(cdev, p_chain);
3358                 break;
3359         }
3360 }
3361
3362 static int
3363 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3364                              enum qed_chain_cnt_type cnt_type,
3365                              size_t elem_size, u32 page_cnt)
3366 {
3367         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3368
3369         /* The actual chain size can be larger than the maximal possible value
3370          * after rounding up the requested elements number to pages, and after
3371          * taking into acount the unusuable elements (next-ptr elements).
3372          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3373          * size/capacity fields are of a u32 type.
3374          */
3375         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
3376              chain_size > ((u32)U16_MAX + 1)) ||
3377             (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
3378                 DP_NOTICE(cdev,
3379                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3380                           chain_size);
3381                 return -EINVAL;
3382         }
3383
3384         return 0;
3385 }
3386
3387 static int
3388 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3389 {
3390         void *p_virt = NULL, *p_virt_prev = NULL;
3391         dma_addr_t p_phys = 0;
3392         u32 i;
3393
3394         for (i = 0; i < p_chain->page_cnt; i++) {
3395                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3396                                             QED_CHAIN_PAGE_SIZE,
3397                                             &p_phys, GFP_KERNEL);
3398                 if (!p_virt)
3399                         return -ENOMEM;
3400
3401                 if (i == 0) {
3402                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3403                         qed_chain_reset(p_chain);
3404                 } else {
3405                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3406                                                      p_virt, p_phys);
3407                 }
3408
3409                 p_virt_prev = p_virt;
3410         }
3411         /* Last page's next element should point to the beginning of the
3412          * chain.
3413          */
3414         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3415                                      p_chain->p_virt_addr,
3416                                      p_chain->p_phys_addr);
3417
3418         return 0;
3419 }
3420
3421 static int
3422 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3423 {
3424         dma_addr_t p_phys = 0;
3425         void *p_virt = NULL;
3426
3427         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3428                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
3429         if (!p_virt)
3430                 return -ENOMEM;
3431
3432         qed_chain_init_mem(p_chain, p_virt, p_phys);
3433         qed_chain_reset(p_chain);
3434
3435         return 0;
3436 }
3437
3438 static int
3439 qed_chain_alloc_pbl(struct qed_dev *cdev,
3440                     struct qed_chain *p_chain,
3441                     struct qed_chain_ext_pbl *ext_pbl)
3442 {
3443         u32 page_cnt = p_chain->page_cnt, size, i;
3444         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3445         struct addr_tbl_entry *pp_addr_tbl;
3446         u8 *p_pbl_virt = NULL;
3447         void *p_virt = NULL;
3448
3449         size = page_cnt * sizeof(*pp_addr_tbl);
3450         pp_addr_tbl =  vzalloc(size);
3451         if (!pp_addr_tbl)
3452                 return -ENOMEM;
3453
3454         /* The allocation of the PBL table is done with its full size, since it
3455          * is expected to be successive.
3456          * qed_chain_init_pbl_mem() is called even in a case of an allocation
3457          * failure, since tbl was previously allocated, and it
3458          * should be saved to allow its freeing during the error flow.
3459          */
3460         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3461
3462         if (!ext_pbl) {
3463                 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3464                                                 size, &p_pbl_phys, GFP_KERNEL);
3465         } else {
3466                 p_pbl_virt = ext_pbl->p_pbl_virt;
3467                 p_pbl_phys = ext_pbl->p_pbl_phys;
3468                 p_chain->b_external_pbl = true;
3469         }
3470
3471         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, pp_addr_tbl);
3472         if (!p_pbl_virt)
3473                 return -ENOMEM;
3474
3475         for (i = 0; i < page_cnt; i++) {
3476                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3477                                             QED_CHAIN_PAGE_SIZE,
3478                                             &p_phys, GFP_KERNEL);
3479                 if (!p_virt)
3480                         return -ENOMEM;
3481
3482                 if (i == 0) {
3483                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3484                         qed_chain_reset(p_chain);
3485                 }
3486
3487                 /* Fill the PBL table with the physical address of the page */
3488                 *(dma_addr_t *)p_pbl_virt = p_phys;
3489                 /* Keep the virtual address of the page */
3490                 p_chain->pbl.pp_addr_tbl[i].virt_addr = p_virt;
3491                 p_chain->pbl.pp_addr_tbl[i].dma_map = p_phys;
3492
3493                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3494         }
3495
3496         return 0;
3497 }
3498
3499 int qed_chain_alloc(struct qed_dev *cdev,
3500                     enum qed_chain_use_mode intended_use,
3501                     enum qed_chain_mode mode,
3502                     enum qed_chain_cnt_type cnt_type,
3503                     u32 num_elems,
3504                     size_t elem_size,
3505                     struct qed_chain *p_chain,
3506                     struct qed_chain_ext_pbl *ext_pbl)
3507 {
3508         u32 page_cnt;
3509         int rc = 0;
3510
3511         if (mode == QED_CHAIN_MODE_SINGLE)
3512                 page_cnt = 1;
3513         else
3514                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3515
3516         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3517         if (rc) {
3518                 DP_NOTICE(cdev,
3519                           "Cannot allocate a chain with the given arguments:\n");
3520                 DP_NOTICE(cdev,
3521                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3522                           intended_use, mode, cnt_type, num_elems, elem_size);
3523                 return rc;
3524         }
3525
3526         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3527                               mode, cnt_type);
3528
3529         switch (mode) {
3530         case QED_CHAIN_MODE_NEXT_PTR:
3531                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3532                 break;
3533         case QED_CHAIN_MODE_SINGLE:
3534                 rc = qed_chain_alloc_single(cdev, p_chain);
3535                 break;
3536         case QED_CHAIN_MODE_PBL:
3537                 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
3538                 break;
3539         }
3540         if (rc)
3541                 goto nomem;
3542
3543         return 0;
3544
3545 nomem:
3546         qed_chain_free(cdev, p_chain);
3547         return rc;
3548 }
3549
3550 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
3551 {
3552         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3553                 u16 min, max;
3554
3555                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
3556                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3557                 DP_NOTICE(p_hwfn,
3558                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3559                           src_id, min, max);
3560
3561                 return -EINVAL;
3562         }
3563
3564         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3565
3566         return 0;
3567 }
3568
3569 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3570 {
3571         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3572                 u8 min, max;
3573
3574                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3575                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3576                 DP_NOTICE(p_hwfn,
3577                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3578                           src_id, min, max);
3579
3580                 return -EINVAL;
3581         }
3582
3583         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3584
3585         return 0;
3586 }
3587
3588 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3589 {
3590         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3591                 u8 min, max;
3592
3593                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3594                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3595                 DP_NOTICE(p_hwfn,
3596                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3597                           src_id, min, max);
3598
3599                 return -EINVAL;
3600         }
3601
3602         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3603
3604         return 0;
3605 }
3606
3607 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3608                                   u8 *p_filter)
3609 {
3610         *p_high = p_filter[1] | (p_filter[0] << 8);
3611         *p_low = p_filter[5] | (p_filter[4] << 8) |
3612                  (p_filter[3] << 16) | (p_filter[2] << 24);
3613 }
3614
3615 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3616                            struct qed_ptt *p_ptt, u8 *p_filter)
3617 {
3618         u32 high = 0, low = 0, en;
3619         int i;
3620
3621         if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
3622                 return 0;
3623
3624         qed_llh_mac_to_filter(&high, &low, p_filter);
3625
3626         /* Find a free entry and utilize it */
3627         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3628                 en = qed_rd(p_hwfn, p_ptt,
3629                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3630                 if (en)
3631                         continue;
3632                 qed_wr(p_hwfn, p_ptt,
3633                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3634                        2 * i * sizeof(u32), low);
3635                 qed_wr(p_hwfn, p_ptt,
3636                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3637                        (2 * i + 1) * sizeof(u32), high);
3638                 qed_wr(p_hwfn, p_ptt,
3639                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3640                 qed_wr(p_hwfn, p_ptt,
3641                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3642                        i * sizeof(u32), 0);
3643                 qed_wr(p_hwfn, p_ptt,
3644                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3645                 break;
3646         }
3647         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3648                 DP_NOTICE(p_hwfn,
3649                           "Failed to find an empty LLH filter to utilize\n");
3650                 return -EINVAL;
3651         }
3652
3653         DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3654                    "mac: %pM is added at %d\n",
3655                    p_filter, i);
3656
3657         return 0;
3658 }
3659
3660 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
3661                                struct qed_ptt *p_ptt, u8 *p_filter)
3662 {
3663         u32 high = 0, low = 0;
3664         int i;
3665
3666         if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
3667                 return;
3668
3669         qed_llh_mac_to_filter(&high, &low, p_filter);
3670
3671         /* Find the entry and clean it */
3672         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3673                 if (qed_rd(p_hwfn, p_ptt,
3674                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3675                            2 * i * sizeof(u32)) != low)
3676                         continue;
3677                 if (qed_rd(p_hwfn, p_ptt,
3678                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3679                            (2 * i + 1) * sizeof(u32)) != high)
3680                         continue;
3681
3682                 qed_wr(p_hwfn, p_ptt,
3683                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3684                 qed_wr(p_hwfn, p_ptt,
3685                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3686                 qed_wr(p_hwfn, p_ptt,
3687                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3688                        (2 * i + 1) * sizeof(u32), 0);
3689
3690                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3691                            "mac: %pM is removed from %d\n",
3692                            p_filter, i);
3693                 break;
3694         }
3695         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3696                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3697 }
3698
3699 int
3700 qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
3701                             struct qed_ptt *p_ptt,
3702                             u16 source_port_or_eth_type,
3703                             u16 dest_port, enum qed_llh_port_filter_type_t type)
3704 {
3705         u32 high = 0, low = 0, en;
3706         int i;
3707
3708         if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
3709                 return 0;
3710
3711         switch (type) {
3712         case QED_LLH_FILTER_ETHERTYPE:
3713                 high = source_port_or_eth_type;
3714                 break;
3715         case QED_LLH_FILTER_TCP_SRC_PORT:
3716         case QED_LLH_FILTER_UDP_SRC_PORT:
3717                 low = source_port_or_eth_type << 16;
3718                 break;
3719         case QED_LLH_FILTER_TCP_DEST_PORT:
3720         case QED_LLH_FILTER_UDP_DEST_PORT:
3721                 low = dest_port;
3722                 break;
3723         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3724         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3725                 low = (source_port_or_eth_type << 16) | dest_port;
3726                 break;
3727         default:
3728                 DP_NOTICE(p_hwfn,
3729                           "Non valid LLH protocol filter type %d\n", type);
3730                 return -EINVAL;
3731         }
3732         /* Find a free entry and utilize it */
3733         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3734                 en = qed_rd(p_hwfn, p_ptt,
3735                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3736                 if (en)
3737                         continue;
3738                 qed_wr(p_hwfn, p_ptt,
3739                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3740                        2 * i * sizeof(u32), low);
3741                 qed_wr(p_hwfn, p_ptt,
3742                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3743                        (2 * i + 1) * sizeof(u32), high);
3744                 qed_wr(p_hwfn, p_ptt,
3745                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3746                 qed_wr(p_hwfn, p_ptt,
3747                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3748                        i * sizeof(u32), 1 << type);
3749                 qed_wr(p_hwfn, p_ptt,
3750                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3751                 break;
3752         }
3753         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3754                 DP_NOTICE(p_hwfn,
3755                           "Failed to find an empty LLH filter to utilize\n");
3756                 return -EINVAL;
3757         }
3758         switch (type) {
3759         case QED_LLH_FILTER_ETHERTYPE:
3760                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3761                            "ETH type %x is added at %d\n",
3762                            source_port_or_eth_type, i);
3763                 break;
3764         case QED_LLH_FILTER_TCP_SRC_PORT:
3765                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3766                            "TCP src port %x is added at %d\n",
3767                            source_port_or_eth_type, i);
3768                 break;
3769         case QED_LLH_FILTER_UDP_SRC_PORT:
3770                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3771                            "UDP src port %x is added at %d\n",
3772                            source_port_or_eth_type, i);
3773                 break;
3774         case QED_LLH_FILTER_TCP_DEST_PORT:
3775                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3776                            "TCP dst port %x is added at %d\n", dest_port, i);
3777                 break;
3778         case QED_LLH_FILTER_UDP_DEST_PORT:
3779                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3780                            "UDP dst port %x is added at %d\n", dest_port, i);
3781                 break;
3782         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3783                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3784                            "TCP src/dst ports %x/%x are added at %d\n",
3785                            source_port_or_eth_type, dest_port, i);
3786                 break;
3787         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3788                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3789                            "UDP src/dst ports %x/%x are added at %d\n",
3790                            source_port_or_eth_type, dest_port, i);
3791                 break;
3792         }
3793         return 0;
3794 }
3795
3796 void
3797 qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
3798                                struct qed_ptt *p_ptt,
3799                                u16 source_port_or_eth_type,
3800                                u16 dest_port,
3801                                enum qed_llh_port_filter_type_t type)
3802 {
3803         u32 high = 0, low = 0;
3804         int i;
3805
3806         if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
3807                 return;
3808
3809         switch (type) {
3810         case QED_LLH_FILTER_ETHERTYPE:
3811                 high = source_port_or_eth_type;
3812                 break;
3813         case QED_LLH_FILTER_TCP_SRC_PORT:
3814         case QED_LLH_FILTER_UDP_SRC_PORT:
3815                 low = source_port_or_eth_type << 16;
3816                 break;
3817         case QED_LLH_FILTER_TCP_DEST_PORT:
3818         case QED_LLH_FILTER_UDP_DEST_PORT:
3819                 low = dest_port;
3820                 break;
3821         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3822         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3823                 low = (source_port_or_eth_type << 16) | dest_port;
3824                 break;
3825         default:
3826                 DP_NOTICE(p_hwfn,
3827                           "Non valid LLH protocol filter type %d\n", type);
3828                 return;
3829         }
3830
3831         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3832                 if (!qed_rd(p_hwfn, p_ptt,
3833                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3834                         continue;
3835                 if (!qed_rd(p_hwfn, p_ptt,
3836                             NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3837                         continue;
3838                 if (!(qed_rd(p_hwfn, p_ptt,
3839                              NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3840                              i * sizeof(u32)) & BIT(type)))
3841                         continue;
3842                 if (qed_rd(p_hwfn, p_ptt,
3843                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3844                            2 * i * sizeof(u32)) != low)
3845                         continue;
3846                 if (qed_rd(p_hwfn, p_ptt,
3847                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3848                            (2 * i + 1) * sizeof(u32)) != high)
3849                         continue;
3850
3851                 qed_wr(p_hwfn, p_ptt,
3852                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3853                 qed_wr(p_hwfn, p_ptt,
3854                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3855                 qed_wr(p_hwfn, p_ptt,
3856                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3857                        i * sizeof(u32), 0);
3858                 qed_wr(p_hwfn, p_ptt,
3859                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3860                 qed_wr(p_hwfn, p_ptt,
3861                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3862                        (2 * i + 1) * sizeof(u32), 0);
3863                 break;
3864         }
3865
3866         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3867                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3868 }
3869
3870 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3871                             u32 hw_addr, void *p_eth_qzone,
3872                             size_t eth_qzone_size, u8 timeset)
3873 {
3874         struct coalescing_timeset *p_coal_timeset;
3875
3876         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
3877                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
3878                 return -EINVAL;
3879         }
3880
3881         p_coal_timeset = p_eth_qzone;
3882         memset(p_eth_qzone, 0, eth_qzone_size);
3883         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3884         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3885         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3886
3887         return 0;
3888 }
3889
3890 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
3891 {
3892         struct qed_queue_cid *p_cid = p_handle;
3893         struct qed_hwfn *p_hwfn;
3894         struct qed_ptt *p_ptt;
3895         int rc = 0;
3896
3897         p_hwfn = p_cid->p_owner;
3898
3899         if (IS_VF(p_hwfn->cdev))
3900                 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
3901
3902         p_ptt = qed_ptt_acquire(p_hwfn);
3903         if (!p_ptt)
3904                 return -EAGAIN;
3905
3906         if (rx_coal) {
3907                 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
3908                 if (rc)
3909                         goto out;
3910                 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
3911         }
3912
3913         if (tx_coal) {
3914                 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
3915                 if (rc)
3916                         goto out;
3917                 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
3918         }
3919 out:
3920         qed_ptt_release(p_hwfn, p_ptt);
3921         return rc;
3922 }
3923
3924 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
3925                          struct qed_ptt *p_ptt,
3926                          u16 coalesce, struct qed_queue_cid *p_cid)
3927 {
3928         struct ustorm_eth_queue_zone eth_qzone;
3929         u8 timeset, timer_res;
3930         u32 address;
3931         int rc;
3932
3933         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3934         if (coalesce <= 0x7F) {
3935                 timer_res = 0;
3936         } else if (coalesce <= 0xFF) {
3937                 timer_res = 1;
3938         } else if (coalesce <= 0x1FF) {
3939                 timer_res = 2;
3940         } else {
3941                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3942                 return -EINVAL;
3943         }
3944         timeset = (u8)(coalesce >> timer_res);
3945
3946         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3947                                    p_cid->sb_igu_id, false);
3948         if (rc)
3949                 goto out;
3950
3951         address = BAR0_MAP_REG_USDM_RAM +
3952                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
3953
3954         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3955                               sizeof(struct ustorm_eth_queue_zone), timeset);
3956         if (rc)
3957                 goto out;
3958
3959 out:
3960         return rc;
3961 }
3962
3963 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
3964                          struct qed_ptt *p_ptt,
3965                          u16 coalesce, struct qed_queue_cid *p_cid)
3966 {
3967         struct xstorm_eth_queue_zone eth_qzone;
3968         u8 timeset, timer_res;
3969         u32 address;
3970         int rc;
3971
3972         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3973         if (coalesce <= 0x7F) {
3974                 timer_res = 0;
3975         } else if (coalesce <= 0xFF) {
3976                 timer_res = 1;
3977         } else if (coalesce <= 0x1FF) {
3978                 timer_res = 2;
3979         } else {
3980                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3981                 return -EINVAL;
3982         }
3983         timeset = (u8)(coalesce >> timer_res);
3984
3985         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3986                                    p_cid->sb_igu_id, true);
3987         if (rc)
3988                 goto out;
3989
3990         address = BAR0_MAP_REG_XSDM_RAM +
3991                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
3992
3993         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3994                               sizeof(struct xstorm_eth_queue_zone), timeset);
3995 out:
3996         return rc;
3997 }
3998
3999 /* Calculate final WFQ values for all vports and configure them.
4000  * After this configuration each vport will have
4001  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
4002  */
4003 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
4004                                              struct qed_ptt *p_ptt,
4005                                              u32 min_pf_rate)
4006 {
4007         struct init_qm_vport_params *vport_params;
4008         int i;
4009
4010         vport_params = p_hwfn->qm_info.qm_vport_params;
4011
4012         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4013                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4014
4015                 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
4016                                                 min_pf_rate;
4017                 qed_init_vport_wfq(p_hwfn, p_ptt,
4018                                    vport_params[i].first_tx_pq_id,
4019                                    vport_params[i].vport_wfq);
4020         }
4021 }
4022
4023 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
4024                                        u32 min_pf_rate)
4025
4026 {
4027         int i;
4028
4029         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4030                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4031 }
4032
4033 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
4034                                            struct qed_ptt *p_ptt,
4035                                            u32 min_pf_rate)
4036 {
4037         struct init_qm_vport_params *vport_params;
4038         int i;
4039
4040         vport_params = p_hwfn->qm_info.qm_vport_params;
4041
4042         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4043                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
4044                 qed_init_vport_wfq(p_hwfn, p_ptt,
4045                                    vport_params[i].first_tx_pq_id,
4046                                    vport_params[i].vport_wfq);
4047         }
4048 }
4049
4050 /* This function performs several validations for WFQ
4051  * configuration and required min rate for a given vport
4052  * 1. req_rate must be greater than one percent of min_pf_rate.
4053  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4054  *    rates to get less than one percent of min_pf_rate.
4055  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4056  */
4057 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
4058                               u16 vport_id, u32 req_rate, u32 min_pf_rate)
4059 {
4060         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4061         int non_requested_count = 0, req_count = 0, i, num_vports;
4062
4063         num_vports = p_hwfn->qm_info.num_vports;
4064
4065         /* Accounting for the vports which are configured for WFQ explicitly */
4066         for (i = 0; i < num_vports; i++) {
4067                 u32 tmp_speed;
4068
4069                 if ((i != vport_id) &&
4070                     p_hwfn->qm_info.wfq_data[i].configured) {
4071                         req_count++;
4072                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4073                         total_req_min_rate += tmp_speed;
4074                 }
4075         }
4076
4077         /* Include current vport data as well */
4078         req_count++;
4079         total_req_min_rate += req_rate;
4080         non_requested_count = num_vports - req_count;
4081
4082         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
4083                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4084                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4085                            vport_id, req_rate, min_pf_rate);
4086                 return -EINVAL;
4087         }
4088
4089         if (num_vports > QED_WFQ_UNIT) {
4090                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4091                            "Number of vports is greater than %d\n",
4092                            QED_WFQ_UNIT);
4093                 return -EINVAL;
4094         }
4095
4096         if (total_req_min_rate > min_pf_rate) {
4097                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4098                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4099                            total_req_min_rate, min_pf_rate);
4100                 return -EINVAL;
4101         }
4102
4103         total_left_rate = min_pf_rate - total_req_min_rate;
4104
4105         left_rate_per_vp = total_left_rate / non_requested_count;
4106         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
4107                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4108                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4109                            left_rate_per_vp, min_pf_rate);
4110                 return -EINVAL;
4111         }
4112
4113         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4114         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4115
4116         for (i = 0; i < num_vports; i++) {
4117                 if (p_hwfn->qm_info.wfq_data[i].configured)
4118                         continue;
4119
4120                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4121         }
4122
4123         return 0;
4124 }
4125
4126 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
4127                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
4128 {
4129         struct qed_mcp_link_state *p_link;
4130         int rc = 0;
4131
4132         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
4133
4134         if (!p_link->min_pf_rate) {
4135                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4136                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4137                 return rc;
4138         }
4139
4140         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4141
4142         if (!rc)
4143                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4144                                                  p_link->min_pf_rate);
4145         else
4146                 DP_NOTICE(p_hwfn,
4147                           "Validation failed while configuring min rate\n");
4148
4149         return rc;
4150 }
4151
4152 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
4153                                                  struct qed_ptt *p_ptt,
4154                                                  u32 min_pf_rate)
4155 {
4156         bool use_wfq = false;
4157         int rc = 0;
4158         u16 i;
4159
4160         /* Validate all pre configured vports for wfq */
4161         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4162                 u32 rate;
4163
4164                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4165                         continue;
4166
4167                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4168                 use_wfq = true;
4169
4170                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4171                 if (rc) {
4172                         DP_NOTICE(p_hwfn,
4173                                   "WFQ validation failed while configuring min rate\n");
4174                         break;
4175                 }
4176         }
4177
4178         if (!rc && use_wfq)
4179                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4180         else
4181                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4182
4183         return rc;
4184 }
4185
4186 /* Main API for qed clients to configure vport min rate.
4187  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4188  * rate - Speed in Mbps needs to be assigned to a given vport.
4189  */
4190 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
4191 {
4192         int i, rc = -EINVAL;
4193
4194         /* Currently not supported; Might change in future */
4195         if (cdev->num_hwfns > 1) {
4196                 DP_NOTICE(cdev,
4197                           "WFQ configuration is not supported for this device\n");
4198                 return rc;
4199         }
4200
4201         for_each_hwfn(cdev, i) {
4202                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4203                 struct qed_ptt *p_ptt;
4204
4205                 p_ptt = qed_ptt_acquire(p_hwfn);
4206                 if (!p_ptt)
4207                         return -EBUSY;
4208
4209                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4210
4211                 if (rc) {
4212                         qed_ptt_release(p_hwfn, p_ptt);
4213                         return rc;
4214                 }
4215
4216                 qed_ptt_release(p_hwfn, p_ptt);
4217         }
4218
4219         return rc;
4220 }
4221
4222 /* API to configure WFQ from mcp link change */
4223 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
4224                                          struct qed_ptt *p_ptt, u32 min_pf_rate)
4225 {
4226         int i;
4227
4228         if (cdev->num_hwfns > 1) {
4229                 DP_VERBOSE(cdev,
4230                            NETIF_MSG_LINK,
4231                            "WFQ configuration is not supported for this device\n");
4232                 return;
4233         }
4234
4235         for_each_hwfn(cdev, i) {
4236                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4237
4238                 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
4239                                                       min_pf_rate);
4240         }
4241 }
4242
4243 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
4244                                      struct qed_ptt *p_ptt,
4245                                      struct qed_mcp_link_state *p_link,
4246                                      u8 max_bw)
4247 {
4248         int rc = 0;
4249
4250         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4251
4252         if (!p_link->line_speed && (max_bw != 100))
4253                 return rc;
4254
4255         p_link->speed = (p_link->line_speed * max_bw) / 100;
4256         p_hwfn->qm_info.pf_rl = p_link->speed;
4257
4258         /* Since the limiter also affects Tx-switched traffic, we don't want it
4259          * to limit such traffic in case there's no actual limit.
4260          * In that case, set limit to imaginary high boundary.
4261          */
4262         if (max_bw == 100)
4263                 p_hwfn->qm_info.pf_rl = 100000;
4264
4265         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4266                             p_hwfn->qm_info.pf_rl);
4267
4268         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4269                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4270                    p_link->speed);
4271
4272         return rc;
4273 }
4274
4275 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4276 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
4277 {
4278         int i, rc = -EINVAL;
4279
4280         if (max_bw < 1 || max_bw > 100) {
4281                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
4282                 return rc;
4283         }
4284
4285         for_each_hwfn(cdev, i) {
4286                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4287                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4288                 struct qed_mcp_link_state *p_link;
4289                 struct qed_ptt *p_ptt;
4290
4291                 p_link = &p_lead->mcp_info->link_output;
4292
4293                 p_ptt = qed_ptt_acquire(p_hwfn);
4294                 if (!p_ptt)
4295                         return -EBUSY;
4296
4297                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4298                                                       p_link, max_bw);
4299
4300                 qed_ptt_release(p_hwfn, p_ptt);
4301
4302                 if (rc)
4303                         break;
4304         }
4305
4306         return rc;
4307 }
4308
4309 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
4310                                      struct qed_ptt *p_ptt,
4311                                      struct qed_mcp_link_state *p_link,
4312                                      u8 min_bw)
4313 {
4314         int rc = 0;
4315
4316         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4317         p_hwfn->qm_info.pf_wfq = min_bw;
4318
4319         if (!p_link->line_speed)
4320                 return rc;
4321
4322         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4323
4324         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4325
4326         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4327                    "Configured MIN bandwidth to be %d Mb/sec\n",
4328                    p_link->min_pf_rate);
4329
4330         return rc;
4331 }
4332
4333 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4334 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
4335 {
4336         int i, rc = -EINVAL;
4337
4338         if (min_bw < 1 || min_bw > 100) {
4339                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
4340                 return rc;
4341         }
4342
4343         for_each_hwfn(cdev, i) {
4344                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4345                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4346                 struct qed_mcp_link_state *p_link;
4347                 struct qed_ptt *p_ptt;
4348
4349                 p_link = &p_lead->mcp_info->link_output;
4350
4351                 p_ptt = qed_ptt_acquire(p_hwfn);
4352                 if (!p_ptt)
4353                         return -EBUSY;
4354
4355                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4356                                                       p_link, min_bw);
4357                 if (rc) {
4358                         qed_ptt_release(p_hwfn, p_ptt);
4359                         return rc;
4360                 }
4361
4362                 if (p_link->min_pf_rate) {
4363                         u32 min_rate = p_link->min_pf_rate;
4364
4365                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
4366                                                                    p_ptt,
4367                                                                    min_rate);
4368                 }
4369
4370                 qed_ptt_release(p_hwfn, p_ptt);
4371         }
4372
4373         return rc;
4374 }
4375
4376 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4377 {
4378         struct qed_mcp_link_state *p_link;
4379
4380         p_link = &p_hwfn->mcp_info->link_output;
4381
4382         if (p_link->min_pf_rate)
4383                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4384                                                p_link->min_pf_rate);
4385
4386         memset(p_hwfn->qm_info.wfq_data, 0,
4387                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4388 }
4389
4390 int qed_device_num_engines(struct qed_dev *cdev)
4391 {
4392         return QED_IS_BB(cdev) ? 2 : 1;
4393 }
4394
4395 static int qed_device_num_ports(struct qed_dev *cdev)
4396 {
4397         /* in CMT always only one port */
4398         if (cdev->num_hwfns > 1)
4399                 return 1;
4400
4401         return cdev->num_ports_in_engine * qed_device_num_engines(cdev);
4402 }
4403
4404 int qed_device_get_port_id(struct qed_dev *cdev)
4405 {
4406         return (QED_LEADING_HWFN(cdev)->abs_pf_id) % qed_device_num_ports(cdev);
4407 }
4408
4409 void qed_set_fw_mac_addr(__le16 *fw_msb,
4410                          __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
4411 {
4412         ((u8 *)fw_msb)[0] = mac[1];
4413         ((u8 *)fw_msb)[1] = mac[0];
4414         ((u8 *)fw_mid)[0] = mac[3];
4415         ((u8 *)fw_mid)[1] = mac[2];
4416         ((u8 *)fw_lsb)[0] = mac[5];
4417         ((u8 *)fw_lsb)[1] = mac[4];
4418 }