1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
9 #include <linux/types.h>
10 #include <asm/byteorder.h>
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/errno.h>
15 #include <linux/kernel.h>
16 #include <linux/mutex.h>
17 #include <linux/pci.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/vmalloc.h>
21 #include <linux/etherdevice.h>
22 #include <linux/qed/qed_chain.h>
23 #include <linux/qed/qed_if.h>
27 #include "qed_dev_api.h"
30 #include "qed_init_ops.h"
34 #include "qed_reg_addr.h"
36 #include "qed_sriov.h"
40 static DEFINE_SPINLOCK(qm_lock);
42 #define QED_MIN_DPIS (4)
43 #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS)
45 /* API common to all protocols */
47 BAR_ID_0, /* used for GRC */
48 BAR_ID_1 /* Used for doorbells */
51 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id)
53 u32 bar_reg = (bar_id == BAR_ID_0 ?
54 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
57 if (IS_VF(p_hwfn->cdev))
60 val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
62 return 1 << (val + 15);
64 /* Old MFW initialized above registered only conditionally */
65 if (p_hwfn->cdev->num_hwfns > 1) {
67 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
68 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
71 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
76 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
80 cdev->dp_level = dp_level;
81 cdev->dp_module = dp_module;
82 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
83 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
85 p_hwfn->dp_level = dp_level;
86 p_hwfn->dp_module = dp_module;
90 void qed_init_struct(struct qed_dev *cdev)
94 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
95 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
99 p_hwfn->b_active = false;
101 mutex_init(&p_hwfn->dmae_info.mutex);
104 /* hwfn 0 is always active */
105 cdev->hwfns[0].b_active = true;
107 /* set the default cache alignment to 128 */
108 cdev->cache_shift = 7;
111 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
113 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
115 kfree(qm_info->qm_pq_params);
116 qm_info->qm_pq_params = NULL;
117 kfree(qm_info->qm_vport_params);
118 qm_info->qm_vport_params = NULL;
119 kfree(qm_info->qm_port_params);
120 qm_info->qm_port_params = NULL;
121 kfree(qm_info->wfq_data);
122 qm_info->wfq_data = NULL;
125 void qed_resc_free(struct qed_dev *cdev)
132 kfree(cdev->fw_data);
133 cdev->fw_data = NULL;
135 kfree(cdev->reset_stats);
137 for_each_hwfn(cdev, i) {
138 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
140 kfree(p_hwfn->p_tx_cids);
141 p_hwfn->p_tx_cids = NULL;
142 kfree(p_hwfn->p_rx_cids);
143 p_hwfn->p_rx_cids = NULL;
146 for_each_hwfn(cdev, i) {
147 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
149 qed_cxt_mngr_free(p_hwfn);
150 qed_qm_info_free(p_hwfn);
151 qed_spq_free(p_hwfn);
152 qed_eq_free(p_hwfn, p_hwfn->p_eq);
153 qed_consq_free(p_hwfn, p_hwfn->p_consq);
154 qed_int_free(p_hwfn);
155 #ifdef CONFIG_QED_LL2
156 qed_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
158 qed_iov_free(p_hwfn);
159 qed_dmae_info_free(p_hwfn);
160 qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
164 static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
166 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0;
167 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
168 struct init_qm_port_params *p_qm_port;
169 bool init_rdma_offload_pq = false;
170 bool init_pure_ack_pq = false;
171 bool init_ooo_pq = false;
172 u16 num_pqs, multi_cos_tcs = 1;
173 u8 pf_wfq = qm_info->pf_wfq;
174 u32 pf_rl = qm_info->pf_rl;
178 #ifdef CONFIG_QED_SRIOV
179 if (p_hwfn->cdev->p_iov_info)
180 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
182 memset(qm_info, 0, sizeof(*qm_info));
184 num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */
185 num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT);
187 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
188 num_pqs++; /* for RoCE queue */
189 init_rdma_offload_pq = true;
190 /* we subtract num_vfs because each require a rate limiter,
191 * and one default rate limiter
193 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn)
194 num_pf_rls = RESC_NUM(p_hwfn, QED_RL) - num_vfs - 1;
196 num_pqs += num_pf_rls;
197 qm_info->num_pf_rls = (u8) num_pf_rls;
200 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
201 num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */
202 init_pure_ack_pq = true;
206 /* Sanity checking that setup requires legal number of resources */
207 if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) {
209 "Need too many Physical queues - 0x%04x when only %04x are available\n",
210 num_pqs, RESC_NUM(p_hwfn, QED_PQ));
214 /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete.
216 qm_info->qm_pq_params = kcalloc(num_pqs,
217 sizeof(struct init_qm_pq_params),
218 b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
219 if (!qm_info->qm_pq_params)
222 qm_info->qm_vport_params = kcalloc(num_vports,
223 sizeof(struct init_qm_vport_params),
224 b_sleepable ? GFP_KERNEL
226 if (!qm_info->qm_vport_params)
229 qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS,
230 sizeof(struct init_qm_port_params),
231 b_sleepable ? GFP_KERNEL
233 if (!qm_info->qm_port_params)
236 qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data),
237 b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
238 if (!qm_info->wfq_data)
241 vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);
243 /* First init rate limited queues */
244 for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
245 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
246 qm_info->qm_pq_params[curr_queue].tc_id =
247 p_hwfn->hw_info.non_offload_tc;
248 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
249 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
252 /* First init per-TC PQs */
253 for (i = 0; i < multi_cos_tcs; i++) {
254 struct init_qm_pq_params *params =
255 &qm_info->qm_pq_params[curr_queue++];
257 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE ||
258 p_hwfn->hw_info.personality == QED_PCI_ETH) {
259 params->vport_id = vport_id;
260 params->tc_id = p_hwfn->hw_info.non_offload_tc;
261 params->wrr_group = 1;
263 params->vport_id = vport_id;
264 params->tc_id = p_hwfn->hw_info.offload_tc;
265 params->wrr_group = 1;
269 /* Then init pure-LB PQ */
270 qm_info->pure_lb_pq = curr_queue;
271 qm_info->qm_pq_params[curr_queue].vport_id =
272 (u8) RESC_START(p_hwfn, QED_VPORT);
273 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
274 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
277 qm_info->offload_pq = 0;
278 if (init_rdma_offload_pq) {
279 qm_info->offload_pq = curr_queue;
280 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
281 qm_info->qm_pq_params[curr_queue].tc_id =
282 p_hwfn->hw_info.offload_tc;
283 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
287 if (init_pure_ack_pq) {
288 qm_info->pure_ack_pq = curr_queue;
289 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
290 qm_info->qm_pq_params[curr_queue].tc_id =
291 p_hwfn->hw_info.offload_tc;
292 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
297 qm_info->ooo_pq = curr_queue;
298 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
299 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
300 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
304 /* Then init per-VF PQs */
305 vf_offset = curr_queue;
306 for (i = 0; i < num_vfs; i++) {
307 /* First vport is used by the PF */
308 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
309 qm_info->qm_pq_params[curr_queue].tc_id =
310 p_hwfn->hw_info.non_offload_tc;
311 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
312 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
316 qm_info->vf_queues_offset = vf_offset;
317 qm_info->num_pqs = num_pqs;
318 qm_info->num_vports = num_vports;
320 /* Initialize qm port parameters */
321 num_ports = p_hwfn->cdev->num_ports_in_engines;
322 for (i = 0; i < num_ports; i++) {
323 p_qm_port = &qm_info->qm_port_params[i];
324 p_qm_port->active = 1;
326 p_qm_port->active_phys_tcs = 0x7;
328 p_qm_port->active_phys_tcs = 0x9f;
329 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
330 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
333 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
335 qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ);
337 qm_info->num_vf_pqs = num_vfs;
338 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
340 for (i = 0; i < qm_info->num_vports; i++)
341 qm_info->qm_vport_params[i].vport_wfq = 1;
343 qm_info->vport_rl_en = 1;
344 qm_info->vport_wfq_en = 1;
345 qm_info->pf_rl = pf_rl;
346 qm_info->pf_wfq = pf_wfq;
351 qed_qm_info_free(p_hwfn);
355 /* This function reconfigures the QM pf on the fly.
356 * For this purpose we:
357 * 1. reconfigure the QM database
358 * 2. set new values to runtime arrat
359 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
360 * 4. activate init tool in QM_PF stage
361 * 5. send an sdm_qm_cmd through rbc interface to release the QM
363 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
365 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
369 /* qm_info is allocated in qed_init_qm_info() which is already called
370 * from qed_resc_alloc() or previous call of qed_qm_reconf().
371 * The allocated size may change each init, so we free it before next
374 qed_qm_info_free(p_hwfn);
376 /* initialize qed's qm data structure */
377 rc = qed_init_qm_info(p_hwfn, false);
381 /* stop PF's qm queues */
382 spin_lock_bh(&qm_lock);
383 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
384 qm_info->start_pq, qm_info->num_pqs);
385 spin_unlock_bh(&qm_lock);
389 /* clear the QM_PF runtime phase leftovers from previous init */
390 qed_init_clear_rt_data(p_hwfn);
392 /* prepare QM portion of runtime array */
393 qed_qm_init_pf(p_hwfn);
395 /* activate init tool on runtime array */
396 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
397 p_hwfn->hw_info.hw_mode);
401 /* start PF's qm queues */
402 spin_lock_bh(&qm_lock);
403 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
404 qm_info->start_pq, qm_info->num_pqs);
405 spin_unlock_bh(&qm_lock);
412 int qed_resc_alloc(struct qed_dev *cdev)
414 #ifdef CONFIG_QED_LL2
415 struct qed_ll2_info *p_ll2_info;
417 struct qed_consq *p_consq;
424 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
428 /* Allocate Memory for the Queue->CID mapping */
429 for_each_hwfn(cdev, i) {
430 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
431 int tx_size = sizeof(struct qed_hw_cid_data) *
432 RESC_NUM(p_hwfn, QED_L2_QUEUE);
433 int rx_size = sizeof(struct qed_hw_cid_data) *
434 RESC_NUM(p_hwfn, QED_L2_QUEUE);
436 p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL);
437 if (!p_hwfn->p_tx_cids)
440 p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL);
441 if (!p_hwfn->p_rx_cids)
445 for_each_hwfn(cdev, i) {
446 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
447 u32 n_eqes, num_cons;
449 /* First allocate the context manager structure */
450 rc = qed_cxt_mngr_alloc(p_hwfn);
454 /* Set the HW cid/tid numbers (in the contest manager)
455 * Must be done prior to any further computations.
457 rc = qed_cxt_set_pf_params(p_hwfn);
461 /* Prepare and process QM requirements */
462 rc = qed_init_qm_info(p_hwfn, true);
466 /* Compute the ILT client partition */
467 rc = qed_cxt_cfg_ilt_compute(p_hwfn);
471 /* CID map / ILT shadow table / T2
472 * The talbes sizes are determined by the computations above
474 rc = qed_cxt_tables_alloc(p_hwfn);
478 /* SPQ, must follow ILT because initializes SPQ context */
479 rc = qed_spq_alloc(p_hwfn);
483 /* SP status block allocation */
484 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
487 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
491 rc = qed_iov_alloc(p_hwfn);
496 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
497 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
498 num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
501 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
502 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
504 qed_cxt_get_proto_cid_count(p_hwfn,
507 n_eqes += 2 * num_cons;
510 if (n_eqes > 0xFFFF) {
512 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
518 p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes);
523 p_consq = qed_consq_alloc(p_hwfn);
526 p_hwfn->p_consq = p_consq;
528 #ifdef CONFIG_QED_LL2
529 if (p_hwfn->using_ll2) {
530 p_ll2_info = qed_ll2_alloc(p_hwfn);
533 p_hwfn->p_ll2_info = p_ll2_info;
537 /* DMA info initialization */
538 rc = qed_dmae_info_alloc(p_hwfn);
542 /* DCBX initialization */
543 rc = qed_dcbx_info_alloc(p_hwfn);
548 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
549 if (!cdev->reset_stats)
561 void qed_resc_setup(struct qed_dev *cdev)
568 for_each_hwfn(cdev, i) {
569 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
571 qed_cxt_mngr_setup(p_hwfn);
572 qed_spq_setup(p_hwfn);
573 qed_eq_setup(p_hwfn, p_hwfn->p_eq);
574 qed_consq_setup(p_hwfn, p_hwfn->p_consq);
576 /* Read shadow of current MFW mailbox */
577 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
578 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
579 p_hwfn->mcp_info->mfw_mb_cur,
580 p_hwfn->mcp_info->mfw_mb_length);
582 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
584 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
585 #ifdef CONFIG_QED_LL2
586 if (p_hwfn->using_ll2)
587 qed_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
592 #define FINAL_CLEANUP_POLL_CNT (100)
593 #define FINAL_CLEANUP_POLL_TIME (10)
594 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
595 struct qed_ptt *p_ptt, u16 id, bool is_vf)
597 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
600 addr = GTT_BAR0_MAP_REG_USDM_RAM +
601 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
606 command |= X_FINAL_CLEANUP_AGG_INT <<
607 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
608 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
609 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
610 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
612 /* Make sure notification is not set before initiating final cleanup */
613 if (REG_RD(p_hwfn, addr)) {
615 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
616 REG_WR(p_hwfn, addr, 0);
619 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
620 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
623 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
625 /* Poll until completion */
626 while (!REG_RD(p_hwfn, addr) && count--)
627 msleep(FINAL_CLEANUP_POLL_TIME);
629 if (REG_RD(p_hwfn, addr))
633 "Failed to receive FW final cleanup notification\n");
635 /* Cleanup afterwards */
636 REG_WR(p_hwfn, addr, 0);
641 static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
645 hw_mode = (1 << MODE_BB_B0);
647 switch (p_hwfn->cdev->num_ports_in_engines) {
649 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
652 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
655 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
658 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
659 p_hwfn->cdev->num_ports_in_engines);
663 switch (p_hwfn->cdev->mf_mode) {
666 hw_mode |= 1 << MODE_MF_SI;
669 hw_mode |= 1 << MODE_MF_SD;
672 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
673 hw_mode |= 1 << MODE_MF_SI;
676 hw_mode |= 1 << MODE_ASIC;
678 if (p_hwfn->cdev->num_hwfns > 1)
679 hw_mode |= 1 << MODE_100G;
681 p_hwfn->hw_info.hw_mode = hw_mode;
683 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
684 "Configuring function for hw_mode: 0x%08x\n",
685 p_hwfn->hw_info.hw_mode);
688 /* Init run time data for all PFs on an engine. */
689 static void qed_init_cau_rt_data(struct qed_dev *cdev)
691 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
694 for_each_hwfn(cdev, i) {
695 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
696 struct qed_igu_info *p_igu_info;
697 struct qed_igu_block *p_block;
698 struct cau_sb_entry sb_entry;
700 p_igu_info = p_hwfn->hw_info.p_igu_info;
702 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev);
704 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
708 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
709 p_block->function_id, 0, 0);
710 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
715 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
716 struct qed_ptt *p_ptt, int hw_mode)
718 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
719 struct qed_qm_common_rt_init_params params;
720 struct qed_dev *cdev = p_hwfn->cdev;
726 qed_init_cau_rt_data(cdev);
728 /* Program GTT windows */
729 qed_gtt_init(p_hwfn);
731 if (p_hwfn->mcp_info) {
732 if (p_hwfn->mcp_info->func_info.bandwidth_max)
733 qm_info->pf_rl_en = 1;
734 if (p_hwfn->mcp_info->func_info.bandwidth_min)
735 qm_info->pf_wfq_en = 1;
738 memset(¶ms, 0, sizeof(params));
739 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines;
740 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
741 params.pf_rl_en = qm_info->pf_rl_en;
742 params.pf_wfq_en = qm_info->pf_wfq_en;
743 params.vport_rl_en = qm_info->vport_rl_en;
744 params.vport_wfq_en = qm_info->vport_wfq_en;
745 params.port_params = qm_info->qm_port_params;
747 qed_qm_common_rt_init(p_hwfn, ¶ms);
749 qed_cxt_hw_init_common(p_hwfn);
751 /* Close gate from NIG to BRB/Storm; By default they are open, but
752 * we close them to prevent NIG from passing data to reset blocks.
753 * Should have been done in the ENGINE phase, but init-tool lacks
754 * proper port-pretend capabilities.
756 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
757 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
758 qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
759 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
760 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
761 qed_port_unpretend(p_hwfn, p_ptt);
763 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
767 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
768 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
770 if (QED_IS_BB(p_hwfn->cdev)) {
771 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
772 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
773 qed_fid_pretend(p_hwfn, p_ptt, pf_id);
774 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
775 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
777 /* pretend to original PF */
778 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
781 for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) {
782 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
783 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
784 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
785 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
786 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
787 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
789 /* pretend to original PF */
790 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
796 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
797 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
799 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
800 u32 dpi_bit_shift, dpi_count;
803 /* Calculate DPI size */
804 dpi_page_size_1 = QED_WID_SIZE * n_cpus;
805 dpi_page_size_2 = max_t(u32, QED_WID_SIZE, PAGE_SIZE);
806 dpi_page_size = max_t(u32, dpi_page_size_1, dpi_page_size_2);
807 dpi_page_size = roundup_pow_of_two(dpi_page_size);
808 dpi_bit_shift = ilog2(dpi_page_size / 4096);
810 dpi_count = pwm_region_size / dpi_page_size;
812 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
813 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
815 p_hwfn->dpi_size = dpi_page_size;
816 p_hwfn->dpi_count = dpi_count;
818 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
820 if (dpi_count < min_dpis)
826 enum QED_ROCE_EDPM_MODE {
827 QED_ROCE_EDPM_MODE_ENABLE = 0,
828 QED_ROCE_EDPM_MODE_FORCE_ON = 1,
829 QED_ROCE_EDPM_MODE_DISABLE = 2,
833 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
835 u32 pwm_regsize, norm_regsize;
836 u32 non_pwm_conn, min_addr_reg1;
837 u32 db_bar_size, n_cpus;
843 db_bar_size = qed_hw_bar_size(p_hwfn, BAR_ID_1);
844 if (p_hwfn->cdev->num_hwfns > 1)
847 /* Calculate doorbell regions */
848 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
849 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
851 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
853 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
854 min_addr_reg1 = norm_regsize / 4096;
855 pwm_regsize = db_bar_size - norm_regsize;
857 /* Check that the normal and PWM sizes are valid */
858 if (db_bar_size < norm_regsize) {
860 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
861 db_bar_size, norm_regsize);
865 if (pwm_regsize < QED_MIN_PWM_REGION) {
867 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
869 QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
873 /* Calculate number of DPIs */
874 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
875 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
876 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
877 /* Either EDPM is mandatory, or we are attempting to allocate a
880 n_cpus = num_present_cpus();
881 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
884 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
885 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
886 if (cond || p_hwfn->dcbx_no_edpm) {
887 /* Either EDPM is disabled from user configuration, or it is
888 * disabled via DCBx, or it is not mandatory and we failed to
889 * allocated a WID per CPU.
892 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
895 qed_rdma_dpm_bar(p_hwfn, p_ptt);
899 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
904 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
905 "disabled" : "enabled");
909 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
911 p_hwfn->pf_params.rdma_pf_params.min_dpis);
915 p_hwfn->dpi_start_offset = norm_regsize;
917 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
918 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
919 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
920 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
925 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
926 struct qed_ptt *p_ptt, int hw_mode)
928 return qed_init_run(p_hwfn, p_ptt, PHASE_PORT,
929 p_hwfn->port_id, hw_mode);
932 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
933 struct qed_ptt *p_ptt,
934 struct qed_tunn_start_params *p_tunn,
937 enum qed_int_mode int_mode,
938 bool allow_npar_tx_switch)
940 u8 rel_pf_id = p_hwfn->rel_pf_id;
943 if (p_hwfn->mcp_info) {
944 struct qed_mcp_function_info *p_info;
946 p_info = &p_hwfn->mcp_info->func_info;
947 if (p_info->bandwidth_min)
948 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
950 /* Update rate limit once we'll actually have a link */
951 p_hwfn->qm_info.pf_rl = 100000;
954 qed_cxt_hw_init_pf(p_hwfn);
956 qed_int_igu_init_rt(p_hwfn);
958 /* Set VLAN in NIG if needed */
959 if (hw_mode & BIT(MODE_MF_SD)) {
960 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
961 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
962 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
963 p_hwfn->hw_info.ovlan);
966 /* Enable classification by MAC if needed */
967 if (hw_mode & BIT(MODE_MF_SI)) {
968 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
969 "Configuring TAGMAC_CLS_TYPE\n");
971 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
974 /* Protocl Configuration */
975 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
976 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
977 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0);
978 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
980 /* Cleanup chip from previous driver if such remains exist */
981 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
985 /* PF Init sequence */
986 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
990 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
991 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
995 /* Pure runtime initializations - directly to the HW */
996 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
998 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1003 /* enable interrupts */
1004 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1006 /* send function start command */
1007 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode,
1008 allow_npar_tx_switch);
1010 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1015 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1016 struct qed_ptt *p_ptt,
1019 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1021 /* Change PF in PXP */
1022 qed_wr(p_hwfn, p_ptt,
1023 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1025 /* wait until value is set - try for 1 second every 50us */
1026 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1027 val = qed_rd(p_hwfn, p_ptt,
1028 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1032 usleep_range(50, 60);
1035 if (val != set_val) {
1037 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1044 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1045 struct qed_ptt *p_main_ptt)
1047 /* Read shadow of current MFW mailbox */
1048 qed_mcp_read_mb(p_hwfn, p_main_ptt);
1049 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1050 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
1053 int qed_hw_init(struct qed_dev *cdev,
1054 struct qed_tunn_start_params *p_tunn,
1056 enum qed_int_mode int_mode,
1057 bool allow_npar_tx_switch,
1058 const u8 *bin_fw_data)
1060 u32 load_code, param;
1063 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
1064 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1069 rc = qed_init_fw_data(cdev, bin_fw_data);
1074 for_each_hwfn(cdev, i) {
1075 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1078 p_hwfn->b_int_enabled = 1;
1082 /* Enable DMAE in PXP */
1083 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1085 qed_calc_hw_mode(p_hwfn);
1087 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1089 DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n");
1093 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1095 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1096 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1099 p_hwfn->first_on_engine = (load_code ==
1100 FW_MSG_CODE_DRV_LOAD_ENGINE);
1102 switch (load_code) {
1103 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1104 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1105 p_hwfn->hw_info.hw_mode);
1109 case FW_MSG_CODE_DRV_LOAD_PORT:
1110 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1111 p_hwfn->hw_info.hw_mode);
1116 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1117 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1118 p_tunn, p_hwfn->hw_info.hw_mode,
1119 b_hw_start, int_mode,
1120 allow_npar_tx_switch);
1129 "init phase failed for loadcode 0x%x (rc %d)\n",
1132 /* ACK mfw regardless of success or failure of initialization */
1133 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1134 DRV_MSG_CODE_LOAD_DONE,
1135 0, &load_code, ¶m);
1139 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1143 /* send DCBX attention request command */
1146 "sending phony dcbx set command to trigger DCBx attention handling\n");
1147 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1148 DRV_MSG_CODE_SET_DCBX,
1149 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1150 &load_code, ¶m);
1153 "Failed to send DCBX attention request\n");
1157 p_hwfn->hw_init_done = true;
1163 #define QED_HW_STOP_RETRY_LIMIT (10)
1164 static void qed_hw_timers_stop(struct qed_dev *cdev,
1165 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1170 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1171 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1173 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1174 if ((!qed_rd(p_hwfn, p_ptt,
1175 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1176 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1179 /* Dependent on number of connection/tasks, possibly
1180 * 1ms sleep is required between polls
1182 usleep_range(1000, 2000);
1185 if (i < QED_HW_STOP_RETRY_LIMIT)
1189 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1190 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1191 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1194 void qed_hw_timers_stop_all(struct qed_dev *cdev)
1198 for_each_hwfn(cdev, j) {
1199 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1200 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1202 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1206 int qed_hw_stop(struct qed_dev *cdev)
1211 for_each_hwfn(cdev, j) {
1212 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1213 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1215 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1218 qed_vf_pf_int_cleanup(p_hwfn);
1222 /* mark the hw as uninitialized... */
1223 p_hwfn->hw_init_done = false;
1225 rc = qed_sp_pf_stop(p_hwfn);
1228 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1230 qed_wr(p_hwfn, p_ptt,
1231 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1233 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1234 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1235 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1236 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1237 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1239 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1241 /* Disable Attention Generation */
1242 qed_int_igu_disable_int(p_hwfn, p_ptt);
1244 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1245 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1247 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1249 /* Need to wait 1ms to guarantee SBs are cleared */
1250 usleep_range(1000, 2000);
1254 /* Disable DMAE in PXP - in CMT, this should only be done for
1255 * first hw-function, and only after all transactions have
1256 * stopped for all active hw-functions.
1258 t_rc = qed_change_pci_hwfn(&cdev->hwfns[0],
1259 cdev->hwfns[0].p_main_ptt, false);
1267 void qed_hw_stop_fastpath(struct qed_dev *cdev)
1271 for_each_hwfn(cdev, j) {
1272 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1273 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1276 qed_vf_pf_int_cleanup(p_hwfn);
1281 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
1283 qed_wr(p_hwfn, p_ptt,
1284 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1286 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1287 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1288 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1289 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1290 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1292 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1294 /* Need to wait 1ms to guarantee SBs are cleared */
1295 usleep_range(1000, 2000);
1299 void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
1301 if (IS_VF(p_hwfn->cdev))
1304 /* Re-open incoming traffic */
1305 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1306 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1309 static int qed_reg_assert(struct qed_hwfn *p_hwfn,
1310 struct qed_ptt *p_ptt, u32 reg, bool expected)
1312 u32 assert_val = qed_rd(p_hwfn, p_ptt, reg);
1314 if (assert_val != expected) {
1315 DP_NOTICE(p_hwfn, "Value at address 0x%08x != 0x%08x\n",
1323 int qed_hw_reset(struct qed_dev *cdev)
1326 u32 unload_resp, unload_param;
1329 for_each_hwfn(cdev, i) {
1330 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1333 rc = qed_vf_pf_reset(p_hwfn);
1339 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n");
1341 /* Check for incorrect states */
1342 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1343 QM_REG_USG_CNT_PF_TX, 0);
1344 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1345 QM_REG_USG_CNT_PF_OTHER, 0);
1347 /* Disable PF in HW blocks */
1348 qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1349 qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1350 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1351 TCFC_REG_STRONG_ENABLE_PF, 0);
1352 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1353 CCFC_REG_STRONG_ENABLE_PF, 0);
1355 /* Send unload command to MCP */
1356 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1357 DRV_MSG_CODE_UNLOAD_REQ,
1358 DRV_MB_PARAM_UNLOAD_WOL_MCP,
1359 &unload_resp, &unload_param);
1361 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n");
1362 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1365 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1366 DRV_MSG_CODE_UNLOAD_DONE,
1367 0, &unload_resp, &unload_param);
1369 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n");
1377 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1378 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1380 qed_ptt_pool_free(p_hwfn);
1381 kfree(p_hwfn->hw_info.p_igu_info);
1384 /* Setup bar access */
1385 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
1387 /* clear indirect access */
1388 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0);
1389 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
1390 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0);
1391 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0);
1393 /* Clean Previous errors if such exist */
1394 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1395 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
1397 /* enable internal target-read */
1398 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1399 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1402 static void get_function_id(struct qed_hwfn *p_hwfn)
1405 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
1406 PXP_PF_ME_OPAQUE_ADDR);
1408 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1410 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1411 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1412 PXP_CONCRETE_FID_PFID);
1413 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1414 PXP_CONCRETE_FID_PORT);
1416 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1417 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
1418 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
1421 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
1423 u32 *feat_num = p_hwfn->hw_info.feat_num;
1424 int num_features = 1;
1426 if (IS_ENABLED(CONFIG_QED_RDMA) &&
1427 p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
1428 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
1429 * the status blocks equally between L2 / RoCE but with
1430 * consideration as to how many l2 queues / cnqs we have.
1434 feat_num[QED_RDMA_CNQ] =
1435 min_t(u32, RESC_NUM(p_hwfn, QED_SB) / num_features,
1436 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
1439 feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) /
1441 RESC_NUM(p_hwfn, QED_L2_QUEUE));
1442 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1443 "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1444 feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB),
1448 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
1450 u8 enabled_func_idx = p_hwfn->enabled_func_idx;
1451 u32 *resc_start = p_hwfn->hw_info.resc_start;
1452 u8 num_funcs = p_hwfn->num_funcs_on_engine;
1453 u32 *resc_num = p_hwfn->hw_info.resc_num;
1454 struct qed_sb_cnt_info sb_cnt_info;
1455 int i, max_vf_vlan_filters;
1457 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
1459 #ifdef CONFIG_QED_SRIOV
1460 max_vf_vlan_filters = QED_ETH_MAX_VF_NUM_VLAN_FILTERS;
1462 max_vf_vlan_filters = 0;
1465 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1467 resc_num[QED_SB] = min_t(u32,
1468 (MAX_SB_PER_PATH_BB / num_funcs),
1469 sb_cnt_info.sb_cnt);
1470 resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs;
1471 resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs;
1472 resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs;
1473 resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs;
1474 resc_num[QED_RL] = min_t(u32, 64, resc_num[QED_VPORT]);
1475 resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
1476 resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) /
1478 resc_num[QED_ILT] = PXP_NUM_ILT_RECORDS_BB / num_funcs;
1479 resc_num[QED_LL2_QUEUE] = MAX_NUM_LL2_RX_QUEUES / num_funcs;
1480 resc_num[QED_RDMA_CNQ_RAM] = NUM_OF_CMDQS_CQS / num_funcs;
1481 resc_num[QED_RDMA_STATS_QUEUE] = RDMA_NUM_STATISTIC_COUNTERS_BB /
1484 for (i = 0; i < QED_MAX_RESC; i++)
1485 resc_start[i] = resc_num[i] * enabled_func_idx;
1487 /* Sanity for ILT */
1488 if (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB) {
1489 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
1490 RESC_START(p_hwfn, QED_ILT),
1491 RESC_END(p_hwfn, QED_ILT) - 1);
1495 qed_hw_set_feat(p_hwfn);
1497 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1498 "The numbers for each resource are:\n"
1499 "SB = %d start = %d\n"
1500 "L2_QUEUE = %d start = %d\n"
1501 "VPORT = %d start = %d\n"
1502 "PQ = %d start = %d\n"
1503 "RL = %d start = %d\n"
1504 "MAC = %d start = %d\n"
1505 "VLAN = %d start = %d\n"
1506 "ILT = %d start = %d\n"
1507 "LL2_QUEUE = %d start = %d\n",
1508 p_hwfn->hw_info.resc_num[QED_SB],
1509 p_hwfn->hw_info.resc_start[QED_SB],
1510 p_hwfn->hw_info.resc_num[QED_L2_QUEUE],
1511 p_hwfn->hw_info.resc_start[QED_L2_QUEUE],
1512 p_hwfn->hw_info.resc_num[QED_VPORT],
1513 p_hwfn->hw_info.resc_start[QED_VPORT],
1514 p_hwfn->hw_info.resc_num[QED_PQ],
1515 p_hwfn->hw_info.resc_start[QED_PQ],
1516 p_hwfn->hw_info.resc_num[QED_RL],
1517 p_hwfn->hw_info.resc_start[QED_RL],
1518 p_hwfn->hw_info.resc_num[QED_MAC],
1519 p_hwfn->hw_info.resc_start[QED_MAC],
1520 p_hwfn->hw_info.resc_num[QED_VLAN],
1521 p_hwfn->hw_info.resc_start[QED_VLAN],
1522 p_hwfn->hw_info.resc_num[QED_ILT],
1523 p_hwfn->hw_info.resc_start[QED_ILT],
1524 RESC_NUM(p_hwfn, QED_LL2_QUEUE),
1525 RESC_START(p_hwfn, QED_LL2_QUEUE));
1530 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1532 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
1533 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
1534 struct qed_mcp_link_params *link;
1536 /* Read global nvm_cfg address */
1537 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1539 /* Verify MCP has initialized it */
1540 if (!nvm_cfg_addr) {
1541 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1545 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
1546 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1548 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1549 offsetof(struct nvm_cfg1, glob) +
1550 offsetof(struct nvm_cfg1_glob, core_cfg);
1552 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
1554 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1555 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
1556 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
1557 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
1559 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
1560 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
1562 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
1563 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
1565 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
1566 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
1568 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
1569 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
1571 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
1572 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
1574 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
1575 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
1577 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
1578 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
1580 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
1581 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
1584 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
1588 /* Read default link configuration */
1589 link = &p_hwfn->mcp_info->link_input;
1590 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1591 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1592 link_temp = qed_rd(p_hwfn, p_ptt,
1594 offsetof(struct nvm_cfg1_port, speed_cap_mask));
1595 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1596 link->speed.advertised_speeds = link_temp;
1598 link_temp = link->speed.advertised_speeds;
1599 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
1601 link_temp = qed_rd(p_hwfn, p_ptt,
1603 offsetof(struct nvm_cfg1_port, link_settings));
1604 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1605 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1606 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1607 link->speed.autoneg = true;
1609 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1610 link->speed.forced_speed = 1000;
1612 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1613 link->speed.forced_speed = 10000;
1615 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1616 link->speed.forced_speed = 25000;
1618 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1619 link->speed.forced_speed = 40000;
1621 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1622 link->speed.forced_speed = 50000;
1624 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
1625 link->speed.forced_speed = 100000;
1628 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
1631 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
1632 link->speed.autoneg;
1634 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1635 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1636 link->pause.autoneg = !!(link_temp &
1637 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1638 link->pause.forced_rx = !!(link_temp &
1639 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1640 link->pause.forced_tx = !!(link_temp &
1641 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1642 link->loopback_mode = 0;
1644 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1645 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
1646 link->speed.forced_speed, link->speed.advertised_speeds,
1647 link->speed.autoneg, link->pause.autoneg);
1649 /* Read Multi-function information from shmem */
1650 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1651 offsetof(struct nvm_cfg1, glob) +
1652 offsetof(struct nvm_cfg1_glob, generic_cont0);
1654 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
1656 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1657 NVM_CFG1_GLOB_MF_MODE_OFFSET;
1660 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
1661 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
1663 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
1664 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
1666 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1667 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
1670 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
1671 p_hwfn->cdev->mf_mode);
1673 /* Read Multi-function information from shmem */
1674 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1675 offsetof(struct nvm_cfg1, glob) +
1676 offsetof(struct nvm_cfg1_glob, device_capabilities);
1678 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
1679 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
1680 __set_bit(QED_DEV_CAP_ETH,
1681 &p_hwfn->hw_info.device_capabilities);
1682 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
1683 __set_bit(QED_DEV_CAP_ISCSI,
1684 &p_hwfn->hw_info.device_capabilities);
1685 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
1686 __set_bit(QED_DEV_CAP_ROCE,
1687 &p_hwfn->hw_info.device_capabilities);
1689 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
1692 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1694 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
1695 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
1697 num_funcs = MAX_NUM_PFS_BB;
1699 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
1700 * in the other bits are selected.
1701 * Bits 1-15 are for functions 1-15, respectively, and their value is
1702 * '0' only for enabled functions (function 0 always exists and
1704 * In case of CMT, only the "even" functions are enabled, and thus the
1705 * number of functions for both hwfns is learnt from the same bits.
1707 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
1709 if (reg_function_hide & 0x1) {
1710 if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) {
1718 /* Get the number of the enabled functions on the engine */
1719 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
1726 /* Get the PF index within the enabled functions */
1727 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
1728 tmp = reg_function_hide & eng_mask & low_pfs_mask;
1736 p_hwfn->num_funcs_on_engine = num_funcs;
1737 p_hwfn->enabled_func_idx = enabled_func_idx;
1741 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
1744 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
1748 qed_get_hw_info(struct qed_hwfn *p_hwfn,
1749 struct qed_ptt *p_ptt,
1750 enum qed_pci_personality personality)
1755 /* Since all information is common, only first hwfns should do this */
1756 if (IS_LEAD_HWFN(p_hwfn)) {
1757 rc = qed_iov_hw_info(p_hwfn);
1762 /* Read the port mode */
1763 port_mode = qed_rd(p_hwfn, p_ptt,
1764 CNIG_REG_NW_PORT_MODE_BB_B0);
1766 if (port_mode < 3) {
1767 p_hwfn->cdev->num_ports_in_engines = 1;
1768 } else if (port_mode <= 5) {
1769 p_hwfn->cdev->num_ports_in_engines = 2;
1771 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
1772 p_hwfn->cdev->num_ports_in_engines);
1774 /* Default num_ports_in_engines to something */
1775 p_hwfn->cdev->num_ports_in_engines = 1;
1778 qed_hw_get_nvm_info(p_hwfn, p_ptt);
1780 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
1784 if (qed_mcp_is_init(p_hwfn))
1785 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
1786 p_hwfn->mcp_info->func_info.mac);
1788 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
1790 if (qed_mcp_is_init(p_hwfn)) {
1791 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
1792 p_hwfn->hw_info.ovlan =
1793 p_hwfn->mcp_info->func_info.ovlan;
1795 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
1798 if (qed_mcp_is_init(p_hwfn)) {
1799 enum qed_pci_personality protocol;
1801 protocol = p_hwfn->mcp_info->func_info.protocol;
1802 p_hwfn->hw_info.personality = protocol;
1805 qed_get_num_funcs(p_hwfn, p_ptt);
1807 return qed_hw_get_resc(p_hwfn);
1810 static int qed_get_dev_info(struct qed_dev *cdev)
1812 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1815 /* Read Vendor Id / Device Id */
1816 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
1817 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
1819 cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1820 MISCS_REG_CHIP_NUM);
1821 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1822 MISCS_REG_CHIP_REV);
1823 MASK_FIELD(CHIP_REV, cdev->chip_rev);
1825 cdev->type = QED_DEV_TYPE_BB;
1826 /* Learn number of HW-functions */
1827 tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1828 MISCS_REG_CMT_ENABLED_FOR_PAIR);
1830 if (tmp & (1 << p_hwfn->rel_pf_id)) {
1831 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
1832 cdev->num_hwfns = 2;
1834 cdev->num_hwfns = 1;
1837 cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1838 MISCS_REG_CHIP_TEST_REG) >> 4;
1839 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
1840 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1841 MISCS_REG_CHIP_METAL);
1842 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
1844 DP_INFO(cdev->hwfns,
1845 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
1846 cdev->chip_num, cdev->chip_rev,
1847 cdev->chip_bond_id, cdev->chip_metal);
1849 if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) {
1850 DP_NOTICE(cdev->hwfns,
1851 "The chip type/rev (BB A0) is not supported!\n");
1858 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
1859 void __iomem *p_regview,
1860 void __iomem *p_doorbells,
1861 enum qed_pci_personality personality)
1865 /* Split PCI bars evenly between hwfns */
1866 p_hwfn->regview = p_regview;
1867 p_hwfn->doorbells = p_doorbells;
1869 if (IS_VF(p_hwfn->cdev))
1870 return qed_vf_hw_prepare(p_hwfn);
1872 /* Validate that chip access is feasible */
1873 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
1875 "Reading the ME register returns all Fs; Preventing further chip access\n");
1879 get_function_id(p_hwfn);
1881 /* Allocate PTT pool */
1882 rc = qed_ptt_pool_alloc(p_hwfn);
1886 /* Allocate the main PTT */
1887 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
1889 /* First hwfn learns basic information, e.g., number of hwfns */
1890 if (!p_hwfn->my_id) {
1891 rc = qed_get_dev_info(p_hwfn->cdev);
1896 qed_hw_hwfn_prepare(p_hwfn);
1898 /* Initialize MCP structure */
1899 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
1901 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
1905 /* Read the device configuration information from the HW and SHMEM */
1906 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
1908 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
1912 /* Allocate the init RT array and initialize the init-ops engine */
1913 rc = qed_init_alloc(p_hwfn);
1919 if (IS_LEAD_HWFN(p_hwfn))
1920 qed_iov_free_hw_info(p_hwfn->cdev);
1921 qed_mcp_free(p_hwfn);
1923 qed_hw_hwfn_free(p_hwfn);
1928 int qed_hw_prepare(struct qed_dev *cdev,
1931 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1934 /* Store the precompiled init data ptrs */
1936 qed_init_iro_array(cdev);
1938 /* Initialize the first hwfn - will learn number of hwfns */
1939 rc = qed_hw_prepare_single(p_hwfn,
1941 cdev->doorbells, personality);
1945 personality = p_hwfn->hw_info.personality;
1947 /* Initialize the rest of the hwfns */
1948 if (cdev->num_hwfns > 1) {
1949 void __iomem *p_regview, *p_doorbell;
1952 /* adjust bar offset for second engine */
1953 addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
1956 /* adjust doorbell bar offset for second engine */
1957 addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
1960 /* prepare second hw function */
1961 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
1962 p_doorbell, personality);
1964 /* in case of error, need to free the previously
1965 * initiliazed hwfn 0.
1969 qed_init_free(p_hwfn);
1970 qed_mcp_free(p_hwfn);
1971 qed_hw_hwfn_free(p_hwfn);
1979 void qed_hw_remove(struct qed_dev *cdev)
1983 for_each_hwfn(cdev, i) {
1984 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1987 qed_vf_pf_release(p_hwfn);
1991 qed_init_free(p_hwfn);
1992 qed_hw_hwfn_free(p_hwfn);
1993 qed_mcp_free(p_hwfn);
1996 qed_iov_free_hw_info(cdev);
1999 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
2000 struct qed_chain *p_chain)
2002 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
2003 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
2004 struct qed_chain_next *p_next;
2010 size = p_chain->elem_size * p_chain->usable_per_page;
2012 for (i = 0; i < p_chain->page_cnt; i++) {
2016 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
2017 p_virt_next = p_next->next_virt;
2018 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
2020 dma_free_coherent(&cdev->pdev->dev,
2021 QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
2023 p_virt = p_virt_next;
2024 p_phys = p_phys_next;
2028 static void qed_chain_free_single(struct qed_dev *cdev,
2029 struct qed_chain *p_chain)
2031 if (!p_chain->p_virt_addr)
2034 dma_free_coherent(&cdev->pdev->dev,
2035 QED_CHAIN_PAGE_SIZE,
2036 p_chain->p_virt_addr, p_chain->p_phys_addr);
2039 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
2041 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
2042 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
2043 u8 *p_pbl_virt = p_chain->pbl.p_virt_table;
2045 if (!pp_virt_addr_tbl)
2048 if (!p_chain->pbl.p_virt_table)
2051 for (i = 0; i < page_cnt; i++) {
2052 if (!pp_virt_addr_tbl[i])
2055 dma_free_coherent(&cdev->pdev->dev,
2056 QED_CHAIN_PAGE_SIZE,
2057 pp_virt_addr_tbl[i],
2058 *(dma_addr_t *)p_pbl_virt);
2060 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
2063 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
2064 dma_free_coherent(&cdev->pdev->dev,
2066 p_chain->pbl.p_virt_table, p_chain->pbl.p_phys_table);
2068 vfree(p_chain->pbl.pp_virt_addr_tbl);
2071 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
2073 switch (p_chain->mode) {
2074 case QED_CHAIN_MODE_NEXT_PTR:
2075 qed_chain_free_next_ptr(cdev, p_chain);
2077 case QED_CHAIN_MODE_SINGLE:
2078 qed_chain_free_single(cdev, p_chain);
2080 case QED_CHAIN_MODE_PBL:
2081 qed_chain_free_pbl(cdev, p_chain);
2087 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
2088 enum qed_chain_cnt_type cnt_type,
2089 size_t elem_size, u32 page_cnt)
2091 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
2093 /* The actual chain size can be larger than the maximal possible value
2094 * after rounding up the requested elements number to pages, and after
2095 * taking into acount the unusuable elements (next-ptr elements).
2096 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
2097 * size/capacity fields are of a u32 type.
2099 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
2100 chain_size > 0x10000) ||
2101 (cnt_type == QED_CHAIN_CNT_TYPE_U32 &&
2102 chain_size > 0x100000000ULL)) {
2104 "The actual chain size (0x%llx) is larger than the maximal possible value\n",
2113 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
2115 void *p_virt = NULL, *p_virt_prev = NULL;
2116 dma_addr_t p_phys = 0;
2119 for (i = 0; i < p_chain->page_cnt; i++) {
2120 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2121 QED_CHAIN_PAGE_SIZE,
2122 &p_phys, GFP_KERNEL);
2127 qed_chain_init_mem(p_chain, p_virt, p_phys);
2128 qed_chain_reset(p_chain);
2130 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2134 p_virt_prev = p_virt;
2136 /* Last page's next element should point to the beginning of the
2139 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2140 p_chain->p_virt_addr,
2141 p_chain->p_phys_addr);
2147 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
2149 dma_addr_t p_phys = 0;
2150 void *p_virt = NULL;
2152 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2153 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
2157 qed_chain_init_mem(p_chain, p_virt, p_phys);
2158 qed_chain_reset(p_chain);
2163 static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
2165 u32 page_cnt = p_chain->page_cnt, size, i;
2166 dma_addr_t p_phys = 0, p_pbl_phys = 0;
2167 void **pp_virt_addr_tbl = NULL;
2168 u8 *p_pbl_virt = NULL;
2169 void *p_virt = NULL;
2171 size = page_cnt * sizeof(*pp_virt_addr_tbl);
2172 pp_virt_addr_tbl = vzalloc(size);
2173 if (!pp_virt_addr_tbl)
2176 /* The allocation of the PBL table is done with its full size, since it
2177 * is expected to be successive.
2178 * qed_chain_init_pbl_mem() is called even in a case of an allocation
2179 * failure, since pp_virt_addr_tbl was previously allocated, and it
2180 * should be saved to allow its freeing during the error flow.
2182 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
2183 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
2184 size, &p_pbl_phys, GFP_KERNEL);
2185 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
2190 for (i = 0; i < page_cnt; i++) {
2191 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2192 QED_CHAIN_PAGE_SIZE,
2193 &p_phys, GFP_KERNEL);
2198 qed_chain_init_mem(p_chain, p_virt, p_phys);
2199 qed_chain_reset(p_chain);
2202 /* Fill the PBL table with the physical address of the page */
2203 *(dma_addr_t *)p_pbl_virt = p_phys;
2204 /* Keep the virtual address of the page */
2205 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
2207 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
2213 int qed_chain_alloc(struct qed_dev *cdev,
2214 enum qed_chain_use_mode intended_use,
2215 enum qed_chain_mode mode,
2216 enum qed_chain_cnt_type cnt_type,
2217 u32 num_elems, size_t elem_size, struct qed_chain *p_chain)
2222 if (mode == QED_CHAIN_MODE_SINGLE)
2225 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
2227 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
2230 "Cannot allocate a chain with the given arguments:\n");
2232 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
2233 intended_use, mode, cnt_type, num_elems, elem_size);
2237 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
2241 case QED_CHAIN_MODE_NEXT_PTR:
2242 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
2244 case QED_CHAIN_MODE_SINGLE:
2245 rc = qed_chain_alloc_single(cdev, p_chain);
2247 case QED_CHAIN_MODE_PBL:
2248 rc = qed_chain_alloc_pbl(cdev, p_chain);
2257 qed_chain_free(cdev, p_chain);
2261 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
2263 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
2266 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
2267 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
2269 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
2275 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
2280 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
2282 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
2285 min = (u8)RESC_START(p_hwfn, QED_VPORT);
2286 max = min + RESC_NUM(p_hwfn, QED_VPORT);
2288 "vport id [%d] is not valid, available indices [%d - %d]\n",
2294 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
2299 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
2301 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
2304 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
2305 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
2307 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
2313 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
2318 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
2321 *p_high = p_filter[1] | (p_filter[0] << 8);
2322 *p_low = p_filter[5] | (p_filter[4] << 8) |
2323 (p_filter[3] << 16) | (p_filter[2] << 24);
2326 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
2327 struct qed_ptt *p_ptt, u8 *p_filter)
2329 u32 high = 0, low = 0, en;
2332 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2335 qed_llh_mac_to_filter(&high, &low, p_filter);
2337 /* Find a free entry and utilize it */
2338 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2339 en = qed_rd(p_hwfn, p_ptt,
2340 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2343 qed_wr(p_hwfn, p_ptt,
2344 NIG_REG_LLH_FUNC_FILTER_VALUE +
2345 2 * i * sizeof(u32), low);
2346 qed_wr(p_hwfn, p_ptt,
2347 NIG_REG_LLH_FUNC_FILTER_VALUE +
2348 (2 * i + 1) * sizeof(u32), high);
2349 qed_wr(p_hwfn, p_ptt,
2350 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
2351 qed_wr(p_hwfn, p_ptt,
2352 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2353 i * sizeof(u32), 0);
2354 qed_wr(p_hwfn, p_ptt,
2355 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2358 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2360 "Failed to find an empty LLH filter to utilize\n");
2364 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2365 "mac: %pM is added at %d\n",
2371 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
2372 struct qed_ptt *p_ptt, u8 *p_filter)
2374 u32 high = 0, low = 0;
2377 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2380 qed_llh_mac_to_filter(&high, &low, p_filter);
2382 /* Find the entry and clean it */
2383 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2384 if (qed_rd(p_hwfn, p_ptt,
2385 NIG_REG_LLH_FUNC_FILTER_VALUE +
2386 2 * i * sizeof(u32)) != low)
2388 if (qed_rd(p_hwfn, p_ptt,
2389 NIG_REG_LLH_FUNC_FILTER_VALUE +
2390 (2 * i + 1) * sizeof(u32)) != high)
2393 qed_wr(p_hwfn, p_ptt,
2394 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2395 qed_wr(p_hwfn, p_ptt,
2396 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
2397 qed_wr(p_hwfn, p_ptt,
2398 NIG_REG_LLH_FUNC_FILTER_VALUE +
2399 (2 * i + 1) * sizeof(u32), 0);
2401 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2402 "mac: %pM is removed from %d\n",
2406 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2407 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
2410 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2411 u32 hw_addr, void *p_eth_qzone,
2412 size_t eth_qzone_size, u8 timeset)
2414 struct coalescing_timeset *p_coal_timeset;
2416 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
2417 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
2421 p_coal_timeset = p_eth_qzone;
2422 memset(p_coal_timeset, 0, eth_qzone_size);
2423 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
2424 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
2425 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
2430 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2431 u16 coalesce, u8 qid, u16 sb_id)
2433 struct ustorm_eth_queue_zone eth_qzone;
2434 u8 timeset, timer_res;
2439 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
2440 if (coalesce <= 0x7F) {
2442 } else if (coalesce <= 0xFF) {
2444 } else if (coalesce <= 0x1FF) {
2447 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
2450 timeset = (u8)(coalesce >> timer_res);
2452 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
2456 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
2460 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
2462 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
2463 sizeof(struct ustorm_eth_queue_zone), timeset);
2467 p_hwfn->cdev->rx_coalesce_usecs = coalesce;
2472 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2473 u16 coalesce, u8 qid, u16 sb_id)
2475 struct xstorm_eth_queue_zone eth_qzone;
2476 u8 timeset, timer_res;
2481 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
2482 if (coalesce <= 0x7F) {
2484 } else if (coalesce <= 0xFF) {
2486 } else if (coalesce <= 0x1FF) {
2489 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
2492 timeset = (u8)(coalesce >> timer_res);
2494 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
2498 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
2502 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
2504 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
2505 sizeof(struct xstorm_eth_queue_zone), timeset);
2509 p_hwfn->cdev->tx_coalesce_usecs = coalesce;
2514 /* Calculate final WFQ values for all vports and configure them.
2515 * After this configuration each vport will have
2516 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
2518 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
2519 struct qed_ptt *p_ptt,
2522 struct init_qm_vport_params *vport_params;
2525 vport_params = p_hwfn->qm_info.qm_vport_params;
2527 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2528 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
2530 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
2532 qed_init_vport_wfq(p_hwfn, p_ptt,
2533 vport_params[i].first_tx_pq_id,
2534 vport_params[i].vport_wfq);
2538 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
2544 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
2545 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
2548 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
2549 struct qed_ptt *p_ptt,
2552 struct init_qm_vport_params *vport_params;
2555 vport_params = p_hwfn->qm_info.qm_vport_params;
2557 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2558 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
2559 qed_init_vport_wfq(p_hwfn, p_ptt,
2560 vport_params[i].first_tx_pq_id,
2561 vport_params[i].vport_wfq);
2565 /* This function performs several validations for WFQ
2566 * configuration and required min rate for a given vport
2567 * 1. req_rate must be greater than one percent of min_pf_rate.
2568 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
2569 * rates to get less than one percent of min_pf_rate.
2570 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
2572 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
2573 u16 vport_id, u32 req_rate, u32 min_pf_rate)
2575 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
2576 int non_requested_count = 0, req_count = 0, i, num_vports;
2578 num_vports = p_hwfn->qm_info.num_vports;
2580 /* Accounting for the vports which are configured for WFQ explicitly */
2581 for (i = 0; i < num_vports; i++) {
2584 if ((i != vport_id) &&
2585 p_hwfn->qm_info.wfq_data[i].configured) {
2587 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
2588 total_req_min_rate += tmp_speed;
2592 /* Include current vport data as well */
2594 total_req_min_rate += req_rate;
2595 non_requested_count = num_vports - req_count;
2597 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
2598 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2599 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
2600 vport_id, req_rate, min_pf_rate);
2604 if (num_vports > QED_WFQ_UNIT) {
2605 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2606 "Number of vports is greater than %d\n",
2611 if (total_req_min_rate > min_pf_rate) {
2612 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2613 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
2614 total_req_min_rate, min_pf_rate);
2618 total_left_rate = min_pf_rate - total_req_min_rate;
2620 left_rate_per_vp = total_left_rate / non_requested_count;
2621 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
2622 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2623 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
2624 left_rate_per_vp, min_pf_rate);
2628 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
2629 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
2631 for (i = 0; i < num_vports; i++) {
2632 if (p_hwfn->qm_info.wfq_data[i].configured)
2635 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
2641 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
2642 struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
2644 struct qed_mcp_link_state *p_link;
2647 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
2649 if (!p_link->min_pf_rate) {
2650 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
2651 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
2655 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
2658 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
2659 p_link->min_pf_rate);
2662 "Validation failed while configuring min rate\n");
2667 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
2668 struct qed_ptt *p_ptt,
2671 bool use_wfq = false;
2675 /* Validate all pre configured vports for wfq */
2676 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2679 if (!p_hwfn->qm_info.wfq_data[i].configured)
2682 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
2685 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
2688 "WFQ validation failed while configuring min rate\n");
2694 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
2696 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
2701 /* Main API for qed clients to configure vport min rate.
2702 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
2703 * rate - Speed in Mbps needs to be assigned to a given vport.
2705 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
2707 int i, rc = -EINVAL;
2709 /* Currently not supported; Might change in future */
2710 if (cdev->num_hwfns > 1) {
2712 "WFQ configuration is not supported for this device\n");
2716 for_each_hwfn(cdev, i) {
2717 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2718 struct qed_ptt *p_ptt;
2720 p_ptt = qed_ptt_acquire(p_hwfn);
2724 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
2727 qed_ptt_release(p_hwfn, p_ptt);
2731 qed_ptt_release(p_hwfn, p_ptt);
2737 /* API to configure WFQ from mcp link change */
2738 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
2739 struct qed_ptt *p_ptt, u32 min_pf_rate)
2743 if (cdev->num_hwfns > 1) {
2746 "WFQ configuration is not supported for this device\n");
2750 for_each_hwfn(cdev, i) {
2751 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2753 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
2758 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
2759 struct qed_ptt *p_ptt,
2760 struct qed_mcp_link_state *p_link,
2765 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
2767 if (!p_link->line_speed && (max_bw != 100))
2770 p_link->speed = (p_link->line_speed * max_bw) / 100;
2771 p_hwfn->qm_info.pf_rl = p_link->speed;
2773 /* Since the limiter also affects Tx-switched traffic, we don't want it
2774 * to limit such traffic in case there's no actual limit.
2775 * In that case, set limit to imaginary high boundary.
2778 p_hwfn->qm_info.pf_rl = 100000;
2780 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
2781 p_hwfn->qm_info.pf_rl);
2783 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2784 "Configured MAX bandwidth to be %08x Mb/sec\n",
2790 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
2791 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
2793 int i, rc = -EINVAL;
2795 if (max_bw < 1 || max_bw > 100) {
2796 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
2800 for_each_hwfn(cdev, i) {
2801 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2802 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
2803 struct qed_mcp_link_state *p_link;
2804 struct qed_ptt *p_ptt;
2806 p_link = &p_lead->mcp_info->link_output;
2808 p_ptt = qed_ptt_acquire(p_hwfn);
2812 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
2815 qed_ptt_release(p_hwfn, p_ptt);
2824 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
2825 struct qed_ptt *p_ptt,
2826 struct qed_mcp_link_state *p_link,
2831 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
2832 p_hwfn->qm_info.pf_wfq = min_bw;
2834 if (!p_link->line_speed)
2837 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
2839 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
2841 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2842 "Configured MIN bandwidth to be %d Mb/sec\n",
2843 p_link->min_pf_rate);
2848 /* Main API to configure PF min bandwidth where bw range is [1-100] */
2849 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
2851 int i, rc = -EINVAL;
2853 if (min_bw < 1 || min_bw > 100) {
2854 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
2858 for_each_hwfn(cdev, i) {
2859 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2860 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
2861 struct qed_mcp_link_state *p_link;
2862 struct qed_ptt *p_ptt;
2864 p_link = &p_lead->mcp_info->link_output;
2866 p_ptt = qed_ptt_acquire(p_hwfn);
2870 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
2873 qed_ptt_release(p_hwfn, p_ptt);
2877 if (p_link->min_pf_rate) {
2878 u32 min_rate = p_link->min_pf_rate;
2880 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
2885 qed_ptt_release(p_hwfn, p_ptt);
2891 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2893 struct qed_mcp_link_state *p_link;
2895 p_link = &p_hwfn->mcp_info->link_output;
2897 if (p_link->min_pf_rate)
2898 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
2899 p_link->min_pf_rate);
2901 memset(p_hwfn->qm_info.wfq_data, 0,
2902 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);