drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/errno.h>
  39 #include <linux/kernel.h>
  40 #include <linux/mutex.h>
  41 #include <linux/pci.h>
  42 #include <linux/slab.h>
  43 #include <linux/string.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/qed/qed_chain.h>
  47 #include <linux/qed/qed_if.h>
  48 #include "qed.h"
  49 #include "qed_cxt.h"
  50 #include "qed_dcbx.h"
  51 #include "qed_dev_api.h"
  52 #include "qed_fcoe.h"
  53 #include "qed_hsi.h"
  54 #include "qed_hw.h"
  55 #include "qed_init_ops.h"
  56 #include "qed_int.h"
  57 #include "qed_iscsi.h"
  58 #include "qed_ll2.h"
  59 #include "qed_mcp.h"
  60 #include "qed_ooo.h"
  61 #include "qed_reg_addr.h"
  62 #include "qed_sp.h"
  63 #include "qed_sriov.h"
  64 #include "qed_vf.h"
  65 #include "qed_rdma.h"
  66
  67 static DEFINE_SPINLOCK(qm_lock);
  68
  69 #define QED_MIN_DPIS            (4)
  70 #define QED_MIN_PWM_REGION      (QED_WID_SIZE * QED_MIN_DPIS)
  71
  72 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
  73                            struct qed_ptt *p_ptt, enum BAR_ID bar_id)
  74 {
  75         u32 bar_reg = (bar_id == BAR_ID_0 ?
  76                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  77         u32 val;
  78
  79         if (IS_VF(p_hwfn->cdev))
  80                 return qed_vf_hw_bar_size(p_hwfn, bar_id);
  81
  82         val = qed_rd(p_hwfn, p_ptt, bar_reg);
  83         if (val)
  84                 return 1 << (val + 15);
  85
  86         /* Old MFW initialized above registered only conditionally */
  87         if (p_hwfn->cdev->num_hwfns > 1) {
  88                 DP_INFO(p_hwfn,
  89                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
  90                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  91         } else {
  92                 DP_INFO(p_hwfn,
  93                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
  94                         return 512 * 1024;
  95         }
  96 }
  97
  98 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
  99 {
 100         u32 i;
 101
 102         cdev->dp_level = dp_level;
 103         cdev->dp_module = dp_module;
 104         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 105                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 106
 107                 p_hwfn->dp_level = dp_level;
 108                 p_hwfn->dp_module = dp_module;
 109         }
 110 }
 111
 112 void qed_init_struct(struct qed_dev *cdev)
 113 {
 114         u8 i;
 115
 116         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 117                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 118
 119                 p_hwfn->cdev = cdev;
 120                 p_hwfn->my_id = i;
 121                 p_hwfn->b_active = false;
 122
 123                 mutex_init(&p_hwfn->dmae_info.mutex);
 124         }
 125
 126         /* hwfn 0 is always active */
 127         cdev->hwfns[0].b_active = true;
 128
 129         /* set the default cache alignment to 128 */
 130         cdev->cache_shift = 7;
 131 }
 132
 133 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
 134 {
 135         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 136
 137         kfree(qm_info->qm_pq_params);
 138         qm_info->qm_pq_params = NULL;
 139         kfree(qm_info->qm_vport_params);
 140         qm_info->qm_vport_params = NULL;
 141         kfree(qm_info->qm_port_params);
 142         qm_info->qm_port_params = NULL;
 143         kfree(qm_info->wfq_data);
 144         qm_info->wfq_data = NULL;
 145 }
 146
 147 void qed_resc_free(struct qed_dev *cdev)
 148 {
 149         int i;
 150
 151         if (IS_VF(cdev)) {
 152                 for_each_hwfn(cdev, i)
 153                         qed_l2_free(&cdev->hwfns[i]);
 154                 return;
 155         }
 156
 157         kfree(cdev->fw_data);
 158         cdev->fw_data = NULL;
 159
 160         kfree(cdev->reset_stats);
 161         cdev->reset_stats = NULL;
 162
 163         for_each_hwfn(cdev, i) {
 164                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 165
 166                 qed_cxt_mngr_free(p_hwfn);
 167                 qed_qm_info_free(p_hwfn);
 168                 qed_spq_free(p_hwfn);
 169                 qed_eq_free(p_hwfn);
 170                 qed_consq_free(p_hwfn);
 171                 qed_int_free(p_hwfn);
 172 #ifdef CONFIG_QED_LL2
 173                 qed_ll2_free(p_hwfn);
 174 #endif
 175                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
 176                         qed_fcoe_free(p_hwfn);
 177
 178                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 179                         qed_iscsi_free(p_hwfn);
 180                         qed_ooo_free(p_hwfn);
 181                 }
 182                 qed_iov_free(p_hwfn);
 183                 qed_l2_free(p_hwfn);
 184                 qed_dmae_info_free(p_hwfn);
 185                 qed_dcbx_info_free(p_hwfn);
 186         }
 187 }
 188
 189 /******************** QM initialization *******************/
 190 #define ACTIVE_TCS_BMAP 0x9f
 191 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 192
 193 /* determines the physical queue flags for a given PF. */
 194 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
 195 {
 196         u32 flags;
 197
 198         /* common flags */
 199         flags = PQ_FLAGS_LB;
 200
 201         /* feature flags */
 202         if (IS_QED_SRIOV(p_hwfn->cdev))
 203                 flags |= PQ_FLAGS_VFS;
 204
 205         /* protocol flags */
 206         switch (p_hwfn->hw_info.personality) {
 207         case QED_PCI_ETH:
 208                 flags |= PQ_FLAGS_MCOS;
 209                 break;
 210         case QED_PCI_FCOE:
 211                 flags |= PQ_FLAGS_OFLD;
 212                 break;
 213         case QED_PCI_ISCSI:
 214                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 215                 break;
 216         case QED_PCI_ETH_ROCE:
 217                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
 218                 break;
 219         case QED_PCI_ETH_IWARP:
 220                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 221                     PQ_FLAGS_OFLD;
 222                 break;
 223         default:
 224                 DP_ERR(p_hwfn,
 225                        "unknown personality %d\n", p_hwfn->hw_info.personality);
 226                 return 0;
 227         }
 228
 229         return flags;
 230 }
 231
 232 /* Getters for resource amounts necessary for qm initialization */
 233 u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
 234 {
 235         return p_hwfn->hw_info.num_hw_tc;
 236 }
 237
 238 u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
 239 {
 240         return IS_QED_SRIOV(p_hwfn->cdev) ?
 241                p_hwfn->cdev->p_iov_info->total_vfs : 0;
 242 }
 243
 244 #define NUM_DEFAULT_RLS 1
 245
 246 u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
 247 {
 248         u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 249
 250         /* num RLs can't exceed resource amount of rls or vports */
 251         num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
 252                                  RESC_NUM(p_hwfn, QED_VPORT));
 253
 254         /* Make sure after we reserve there's something left */
 255         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
 256                 return 0;
 257
 258         /* subtract rls necessary for VFs and one default one for the PF */
 259         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 260
 261         return num_pf_rls;
 262 }
 263
 264 u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
 265 {
 266         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 267
 268         /* all pqs share the same vport, except for vfs and pf_rl pqs */
 269         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 270                qed_init_qm_get_num_pf_rls(p_hwfn) +
 271                (!!(PQ_FLAGS_VFS & pq_flags)) *
 272                qed_init_qm_get_num_vfs(p_hwfn) + 1;
 273 }
 274
 275 /* calc amount of PQs according to the requested flags */
 276 u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
 277 {
 278         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 279
 280         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 281                qed_init_qm_get_num_pf_rls(p_hwfn) +
 282                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 283                qed_init_qm_get_num_tcs(p_hwfn) +
 284                (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
 285                (!!(PQ_FLAGS_ACK & pq_flags)) + (!!(PQ_FLAGS_OFLD & pq_flags)) +
 286                (!!(PQ_FLAGS_LLT & pq_flags)) +
 287                (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
 288 }
 289
 290 /* initialize the top level QM params */
 291 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
 292 {
 293         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 294         bool four_port;
 295
 296         /* pq and vport bases for this PF */
 297         qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
 298         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
 299
 300         /* rate limiting and weighted fair queueing are always enabled */
 301         qm_info->vport_rl_en = 1;
 302         qm_info->vport_wfq_en = 1;
 303
 304         /* TC config is different for AH 4 port */
 305         four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 306
 307         /* in AH 4 port we have fewer TCs per port */
 308         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 309                                                      NUM_OF_PHYS_TCS;
 310
 311         /* unless MFW indicated otherwise, ooo_tc == 3 for
 312          * AH 4-port and 4 otherwise.
 313          */
 314         if (!qm_info->ooo_tc)
 315                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 316                                               DCBX_TCP_OOO_TC;
 317 }
 318
 319 /* initialize qm vport params */
 320 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
 321 {
 322         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 323         u8 i;
 324
 325         /* all vports participate in weighted fair queueing */
 326         for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
 327                 qm_info->qm_vport_params[i].vport_wfq = 1;
 328 }
 329
 330 /* initialize qm port params */
 331 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
 332 {
 333         /* Initialize qm port parameters */
 334         u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
 335
 336         /* indicate how ooo and high pri traffic is dealt with */
 337         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 338                           ACTIVE_TCS_BMAP_4PORT_K2 :
 339                           ACTIVE_TCS_BMAP;
 340
 341         for (i = 0; i < num_ports; i++) {
 342                 struct init_qm_port_params *p_qm_port =
 343                     &p_hwfn->qm_info.qm_port_params[i];
 344
 345                 p_qm_port->active = 1;
 346                 p_qm_port->active_phys_tcs = active_phys_tcs;
 347                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 348                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 349         }
 350 }
 351
 352 /* Reset the params which must be reset for qm init. QM init may be called as
 353  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 354  * params may be affected by the init but would simply recalculate to the same
 355  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 356  * affected as these amounts stay the same.
 357  */
 358 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
 359 {
 360         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 361
 362         qm_info->num_pqs = 0;
 363         qm_info->num_vports = 0;
 364         qm_info->num_pf_rls = 0;
 365         qm_info->num_vf_pqs = 0;
 366         qm_info->first_vf_pq = 0;
 367         qm_info->first_mcos_pq = 0;
 368         qm_info->first_rl_pq = 0;
 369 }
 370
 371 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
 372 {
 373         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 374
 375         qm_info->num_vports++;
 376
 377         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 378                 DP_ERR(p_hwfn,
 379                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 380                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 381 }
 382
 383 /* initialize a single pq and manage qm_info resources accounting.
 384  * The pq_init_flags param determines whether the PQ is rate limited
 385  * (for VF or PF) and whether a new vport is allocated to the pq or not
 386  * (i.e. vport will be shared).
 387  */
 388
 389 /* flags for pq init */
 390 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 391 #define PQ_INIT_PF_RL           (1 << 1)
 392 #define PQ_INIT_VF_RL           (1 << 2)
 393
 394 /* defines for pq init */
 395 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 396 #define PQ_INIT_DEFAULT_TC              0
 397 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 398
 399 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
 400                            struct qed_qm_info *qm_info,
 401                            u8 tc, u32 pq_init_flags)
 402 {
 403         u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
 404
 405         if (pq_idx > max_pq)
 406                 DP_ERR(p_hwfn,
 407                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 408
 409         /* init pq params */
 410         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 411             qm_info->num_vports;
 412         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 413         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 414         qm_info->qm_pq_params[pq_idx].rl_valid =
 415             (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
 416
 417         /* qm params accounting */
 418         qm_info->num_pqs++;
 419         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 420                 qm_info->num_vports++;
 421
 422         if (pq_init_flags & PQ_INIT_PF_RL)
 423                 qm_info->num_pf_rls++;
 424
 425         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 426                 DP_ERR(p_hwfn,
 427                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 428                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 429
 430         if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
 431                 DP_ERR(p_hwfn,
 432                        "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
 433                        qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
 434 }
 435
 436 /* get pq index according to PQ_FLAGS */
 437 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
 438                                            unsigned long pq_flags)
 439 {
 440         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 441
 442         /* Can't have multiple flags set here */
 443         if (bitmap_weight(&pq_flags,
 444                           sizeof(pq_flags) * BITS_PER_BYTE) > 1) {
 445                 DP_ERR(p_hwfn, "requested multiple pq flags 0x%lx\n", pq_flags);
 446                 goto err;
 447         }
 448
 449         if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) {
 450                 DP_ERR(p_hwfn, "pq flag 0x%lx is not set\n", pq_flags);
 451                 goto err;
 452         }
 453
 454         switch (pq_flags) {
 455         case PQ_FLAGS_RLS:
 456                 return &qm_info->first_rl_pq;
 457         case PQ_FLAGS_MCOS:
 458                 return &qm_info->first_mcos_pq;
 459         case PQ_FLAGS_LB:
 460                 return &qm_info->pure_lb_pq;
 461         case PQ_FLAGS_OOO:
 462                 return &qm_info->ooo_pq;
 463         case PQ_FLAGS_ACK:
 464                 return &qm_info->pure_ack_pq;
 465         case PQ_FLAGS_OFLD:
 466                 return &qm_info->offload_pq;
 467         case PQ_FLAGS_LLT:
 468                 return &qm_info->low_latency_pq;
 469         case PQ_FLAGS_VFS:
 470                 return &qm_info->first_vf_pq;
 471         default:
 472                 goto err;
 473         }
 474
 475 err:
 476         return &qm_info->start_pq;
 477 }
 478
 479 /* save pq index in qm info */
 480 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
 481                                 u32 pq_flags, u16 pq_val)
 482 {
 483         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 484
 485         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 486 }
 487
 488 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 489 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
 490 {
 491         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 492
 493         return *base_pq_idx + CM_TX_PQ_BASE;
 494 }
 495
 496 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
 497 {
 498         u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
 499
 500         if (max_tc == 0) {
 501                 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
 502                        PQ_FLAGS_MCOS);
 503                 return p_hwfn->qm_info.start_pq;
 504         }
 505
 506         if (tc > max_tc)
 507                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 508
 509         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
 510 }
 511
 512 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
 513 {
 514         u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
 515
 516         if (max_vf == 0) {
 517                 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
 518                        PQ_FLAGS_VFS);
 519                 return p_hwfn->qm_info.start_pq;
 520         }
 521
 522         if (vf > max_vf)
 523                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 524
 525         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
 526 }
 527
 528 u16 qed_get_cm_pq_idx_rl(struct qed_hwfn *p_hwfn, u8 rl)
 529 {
 530         u16 max_rl = qed_init_qm_get_num_pf_rls(p_hwfn);
 531
 532         if (rl > max_rl)
 533                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 534
 535         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 536 }
 537
 538 /* Functions for creating specific types of pqs */
 539 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
 540 {
 541         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 542
 543         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 544                 return;
 545
 546         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 547         qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 548 }
 549
 550 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
 551 {
 552         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 553
 554         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 555                 return;
 556
 557         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 558         qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 559 }
 560
 561 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
 562 {
 563         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 564
 565         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 566                 return;
 567
 568         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 569         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 570 }
 571
 572 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
 573 {
 574         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 575
 576         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 577                 return;
 578
 579         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 580         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 581 }
 582
 583 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
 584 {
 585         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 586
 587         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
 588                 return;
 589
 590         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
 591         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 592 }
 593
 594 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
 595 {
 596         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 597         u8 tc_idx;
 598
 599         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 600                 return;
 601
 602         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 603         for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 604                 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 605 }
 606
 607 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
 608 {
 609         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 610         u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 611
 612         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 613                 return;
 614
 615         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 616         qm_info->num_vf_pqs = num_vfs;
 617         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 618                 qed_init_qm_pq(p_hwfn,
 619                                qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
 620 }
 621
 622 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
 623 {
 624         u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
 625         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 626
 627         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 628                 return;
 629
 630         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 631         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 632                 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_PF_RL);
 633 }
 634
 635 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
 636 {
 637         /* rate limited pqs, must come first (FW assumption) */
 638         qed_init_qm_rl_pqs(p_hwfn);
 639
 640         /* pqs for multi cos */
 641         qed_init_qm_mcos_pqs(p_hwfn);
 642
 643         /* pure loopback pq */
 644         qed_init_qm_lb_pq(p_hwfn);
 645
 646         /* out of order pq */
 647         qed_init_qm_ooo_pq(p_hwfn);
 648
 649         /* pure ack pq */
 650         qed_init_qm_pure_ack_pq(p_hwfn);
 651
 652         /* pq for offloaded protocol */
 653         qed_init_qm_offload_pq(p_hwfn);
 654
 655         /* low latency pq */
 656         qed_init_qm_low_latency_pq(p_hwfn);
 657
 658         /* done sharing vports */
 659         qed_init_qm_advance_vport(p_hwfn);
 660
 661         /* pqs for vfs */
 662         qed_init_qm_vf_pqs(p_hwfn);
 663 }
 664
 665 /* compare values of getters against resources amounts */
 666 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
 667 {
 668         if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
 669                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 670                 return -EINVAL;
 671         }
 672
 673         if (qed_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, QED_PQ)) {
 674                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 675                 return -EINVAL;
 676         }
 677
 678         return 0;
 679 }
 680
 681 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
 682 {
 683         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 684         struct init_qm_vport_params *vport;
 685         struct init_qm_port_params *port;
 686         struct init_qm_pq_params *pq;
 687         int i, tc;
 688
 689         /* top level params */
 690         DP_VERBOSE(p_hwfn,
 691                    NETIF_MSG_HW,
 692                    "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 693                    qm_info->start_pq,
 694                    qm_info->start_vport,
 695                    qm_info->pure_lb_pq,
 696                    qm_info->offload_pq, qm_info->pure_ack_pq);
 697         DP_VERBOSE(p_hwfn,
 698                    NETIF_MSG_HW,
 699                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
 700                    qm_info->ooo_pq,
 701                    qm_info->first_vf_pq,
 702                    qm_info->num_pqs,
 703                    qm_info->num_vf_pqs,
 704                    qm_info->num_vports, qm_info->max_phys_tcs_per_port);
 705         DP_VERBOSE(p_hwfn,
 706                    NETIF_MSG_HW,
 707                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 708                    qm_info->pf_rl_en,
 709                    qm_info->pf_wfq_en,
 710                    qm_info->vport_rl_en,
 711                    qm_info->vport_wfq_en,
 712                    qm_info->pf_wfq,
 713                    qm_info->pf_rl,
 714                    qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
 715
 716         /* port table */
 717         for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
 718                 port = &(qm_info->qm_port_params[i]);
 719                 DP_VERBOSE(p_hwfn,
 720                            NETIF_MSG_HW,
 721                            "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
 722                            i,
 723                            port->active,
 724                            port->active_phys_tcs,
 725                            port->num_pbf_cmd_lines,
 726                            port->num_btb_blocks, port->reserved);
 727         }
 728
 729         /* vport table */
 730         for (i = 0; i < qm_info->num_vports; i++) {
 731                 vport = &(qm_info->qm_vport_params[i]);
 732                 DP_VERBOSE(p_hwfn,
 733                            NETIF_MSG_HW,
 734                            "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
 735                            qm_info->start_vport + i,
 736                            vport->vport_rl, vport->vport_wfq);
 737                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 738                         DP_VERBOSE(p_hwfn,
 739                                    NETIF_MSG_HW,
 740                                    "%d ", vport->first_tx_pq_id[tc]);
 741                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
 742         }
 743
 744         /* pq table */
 745         for (i = 0; i < qm_info->num_pqs; i++) {
 746                 pq = &(qm_info->qm_pq_params[i]);
 747                 DP_VERBOSE(p_hwfn,
 748                            NETIF_MSG_HW,
 749                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
 750                            qm_info->start_pq + i,
 751                            pq->vport_id,
 752                            pq->tc_id, pq->wrr_group, pq->rl_valid);
 753         }
 754 }
 755
 756 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
 757 {
 758         /* reset params required for init run */
 759         qed_init_qm_reset_params(p_hwfn);
 760
 761         /* init QM top level params */
 762         qed_init_qm_params(p_hwfn);
 763
 764         /* init QM port params */
 765         qed_init_qm_port_params(p_hwfn);
 766
 767         /* init QM vport params */
 768         qed_init_qm_vport_params(p_hwfn);
 769
 770         /* init QM physical queue params */
 771         qed_init_qm_pq_params(p_hwfn);
 772
 773         /* display all that init */
 774         qed_dp_init_qm_params(p_hwfn);
 775 }
 776
 777 /* This function reconfigures the QM pf on the fly.
 778  * For this purpose we:
 779  * 1. reconfigure the QM database
 780  * 2. set new values to runtime arrat
 781  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 782  * 4. activate init tool in QM_PF stage
 783  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 784  */
 785 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 786 {
 787         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 788         bool b_rc;
 789         int rc;
 790
 791         /* initialize qed's qm data structure */
 792         qed_init_qm_info(p_hwfn);
 793
 794         /* stop PF's qm queues */
 795         spin_lock_bh(&qm_lock);
 796         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 797                                     qm_info->start_pq, qm_info->num_pqs);
 798         spin_unlock_bh(&qm_lock);
 799         if (!b_rc)
 800                 return -EINVAL;
 801
 802         /* clear the QM_PF runtime phase leftovers from previous init */
 803         qed_init_clear_rt_data(p_hwfn);
 804
 805         /* prepare QM portion of runtime array */
 806         qed_qm_init_pf(p_hwfn, p_ptt);
 807
 808         /* activate init tool on runtime array */
 809         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 810                           p_hwfn->hw_info.hw_mode);
 811         if (rc)
 812                 return rc;
 813
 814         /* start PF's qm queues */
 815         spin_lock_bh(&qm_lock);
 816         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 817                                     qm_info->start_pq, qm_info->num_pqs);
 818         spin_unlock_bh(&qm_lock);
 819         if (!b_rc)
 820                 return -EINVAL;
 821
 822         return 0;
 823 }
 824
 825 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
 826 {
 827         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 828         int rc;
 829
 830         rc = qed_init_qm_sanity(p_hwfn);
 831         if (rc)
 832                 goto alloc_err;
 833
 834         qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) *
 835                                         qed_init_qm_get_num_pqs(p_hwfn),
 836                                         GFP_KERNEL);
 837         if (!qm_info->qm_pq_params)
 838                 goto alloc_err;
 839
 840         qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) *
 841                                            qed_init_qm_get_num_vports(p_hwfn),
 842                                            GFP_KERNEL);
 843         if (!qm_info->qm_vport_params)
 844                 goto alloc_err;
 845
 846         qm_info->qm_port_params = kzalloc(sizeof(*qm_info->qm_port_params) *
 847                                           p_hwfn->cdev->num_ports_in_engine,
 848                                           GFP_KERNEL);
 849         if (!qm_info->qm_port_params)
 850                 goto alloc_err;
 851
 852         qm_info->wfq_data = kzalloc(sizeof(*qm_info->wfq_data) *
 853                                     qed_init_qm_get_num_vports(p_hwfn),
 854                                     GFP_KERNEL);
 855         if (!qm_info->wfq_data)
 856                 goto alloc_err;
 857
 858         return 0;
 859
 860 alloc_err:
 861         DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
 862         qed_qm_info_free(p_hwfn);
 863         return -ENOMEM;
 864 }
 865
 866 int qed_resc_alloc(struct qed_dev *cdev)
 867 {
 868         u32 rdma_tasks, excess_tasks;
 869         u32 line_count;
 870         int i, rc = 0;
 871
 872         if (IS_VF(cdev)) {
 873                 for_each_hwfn(cdev, i) {
 874                         rc = qed_l2_alloc(&cdev->hwfns[i]);
 875                         if (rc)
 876                                 return rc;
 877                 }
 878                 return rc;
 879         }
 880
 881         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
 882         if (!cdev->fw_data)
 883                 return -ENOMEM;
 884
 885         for_each_hwfn(cdev, i) {
 886                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 887                 u32 n_eqes, num_cons;
 888
 889                 /* First allocate the context manager structure */
 890                 rc = qed_cxt_mngr_alloc(p_hwfn);
 891                 if (rc)
 892                         goto alloc_err;
 893
 894                 /* Set the HW cid/tid numbers (in the contest manager)
 895                  * Must be done prior to any further computations.
 896                  */
 897                 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
 898                 if (rc)
 899                         goto alloc_err;
 900
 901                 rc = qed_alloc_qm_data(p_hwfn);
 902                 if (rc)
 903                         goto alloc_err;
 904
 905                 /* init qm info */
 906                 qed_init_qm_info(p_hwfn);
 907
 908                 /* Compute the ILT client partition */
 909                 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
 910                 if (rc) {
 911                         DP_NOTICE(p_hwfn,
 912                                   "too many ILT lines; re-computing with less lines\n");
 913                         /* In case there are not enough ILT lines we reduce the
 914                          * number of RDMA tasks and re-compute.
 915                          */
 916                         excess_tasks =
 917                             qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
 918                         if (!excess_tasks)
 919                                 goto alloc_err;
 920
 921                         rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
 922                         rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
 923                         if (rc)
 924                                 goto alloc_err;
 925
 926                         rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
 927                         if (rc) {
 928                                 DP_ERR(p_hwfn,
 929                                        "failed ILT compute. Requested too many lines: %u\n",
 930                                        line_count);
 931
 932                                 goto alloc_err;
 933                         }
 934                 }
 935
 936                 /* CID map / ILT shadow table / T2
 937                  * The talbes sizes are determined by the computations above
 938                  */
 939                 rc = qed_cxt_tables_alloc(p_hwfn);
 940                 if (rc)
 941                         goto alloc_err;
 942
 943                 /* SPQ, must follow ILT because initializes SPQ context */
 944                 rc = qed_spq_alloc(p_hwfn);
 945                 if (rc)
 946                         goto alloc_err;
 947
 948                 /* SP status block allocation */
 949                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
 950                                                          RESERVED_PTT_DPC);
 951
 952                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 953                 if (rc)
 954                         goto alloc_err;
 955
 956                 rc = qed_iov_alloc(p_hwfn);
 957                 if (rc)
 958                         goto alloc_err;
 959
 960                 /* EQ */
 961                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
 962                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
 963                         enum protocol_type rdma_proto;
 964
 965                         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
 966                                 rdma_proto = PROTOCOLID_ROCE;
 967                         else
 968                                 rdma_proto = PROTOCOLID_IWARP;
 969
 970                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
 971                                                                rdma_proto,
 972                                                                NULL) * 2;
 973                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 974                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 975                         num_cons =
 976                             qed_cxt_get_proto_cid_count(p_hwfn,
 977                                                         PROTOCOLID_ISCSI,
 978                                                         NULL);
 979                         n_eqes += 2 * num_cons;
 980                 }
 981
 982                 if (n_eqes > 0xFFFF) {
 983                         DP_ERR(p_hwfn,
 984                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
 985                                n_eqes, 0xFFFF);
 986                         goto alloc_no_mem;
 987                 }
 988
 989                 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
 990                 if (rc)
 991                         goto alloc_err;
 992
 993                 rc = qed_consq_alloc(p_hwfn);
 994                 if (rc)
 995                         goto alloc_err;
 996
 997                 rc = qed_l2_alloc(p_hwfn);
 998                 if (rc)
 999                         goto alloc_err;
1000
1001 #ifdef CONFIG_QED_LL2
1002                 if (p_hwfn->using_ll2) {
1003                         rc = qed_ll2_alloc(p_hwfn);
1004                         if (rc)
1005                                 goto alloc_err;
1006                 }
1007 #endif
1008
1009                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1010                         rc = qed_fcoe_alloc(p_hwfn);
1011                         if (rc)
1012                                 goto alloc_err;
1013                 }
1014
1015                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1016                         rc = qed_iscsi_alloc(p_hwfn);
1017                         if (rc)
1018                                 goto alloc_err;
1019                         rc = qed_ooo_alloc(p_hwfn);
1020                         if (rc)
1021                                 goto alloc_err;
1022                 }
1023
1024                 /* DMA info initialization */
1025                 rc = qed_dmae_info_alloc(p_hwfn);
1026                 if (rc)
1027                         goto alloc_err;
1028
1029                 /* DCBX initialization */
1030                 rc = qed_dcbx_info_alloc(p_hwfn);
1031                 if (rc)
1032                         goto alloc_err;
1033         }
1034
1035         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
1036         if (!cdev->reset_stats)
1037                 goto alloc_no_mem;
1038
1039         return 0;
1040
1041 alloc_no_mem:
1042         rc = -ENOMEM;
1043 alloc_err:
1044         qed_resc_free(cdev);
1045         return rc;
1046 }
1047
1048 void qed_resc_setup(struct qed_dev *cdev)
1049 {
1050         int i;
1051
1052         if (IS_VF(cdev)) {
1053                 for_each_hwfn(cdev, i)
1054                         qed_l2_setup(&cdev->hwfns[i]);
1055                 return;
1056         }
1057
1058         for_each_hwfn(cdev, i) {
1059                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1060
1061                 qed_cxt_mngr_setup(p_hwfn);
1062                 qed_spq_setup(p_hwfn);
1063                 qed_eq_setup(p_hwfn);
1064                 qed_consq_setup(p_hwfn);
1065
1066                 /* Read shadow of current MFW mailbox */
1067                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1068                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1069                        p_hwfn->mcp_info->mfw_mb_cur,
1070                        p_hwfn->mcp_info->mfw_mb_length);
1071
1072                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1073
1074                 qed_l2_setup(p_hwfn);
1075                 qed_iov_setup(p_hwfn);
1076 #ifdef CONFIG_QED_LL2
1077                 if (p_hwfn->using_ll2)
1078                         qed_ll2_setup(p_hwfn);
1079 #endif
1080                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1081                         qed_fcoe_setup(p_hwfn);
1082
1083                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1084                         qed_iscsi_setup(p_hwfn);
1085                         qed_ooo_setup(p_hwfn);
1086                 }
1087         }
1088 }
1089
1090 #define FINAL_CLEANUP_POLL_CNT          (100)
1091 #define FINAL_CLEANUP_POLL_TIME         (10)
1092 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
1093                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
1094 {
1095         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1096         int rc = -EBUSY;
1097
1098         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1099                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1100
1101         if (is_vf)
1102                 id += 0x10;
1103
1104         command |= X_FINAL_CLEANUP_AGG_INT <<
1105                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1106         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1107         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1108         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1109
1110         /* Make sure notification is not set before initiating final cleanup */
1111         if (REG_RD(p_hwfn, addr)) {
1112                 DP_NOTICE(p_hwfn,
1113                           "Unexpected; Found final cleanup notification before initiating final cleanup\n");
1114                 REG_WR(p_hwfn, addr, 0);
1115         }
1116
1117         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1118                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1119                    id, command);
1120
1121         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1122
1123         /* Poll until completion */
1124         while (!REG_RD(p_hwfn, addr) && count--)
1125                 msleep(FINAL_CLEANUP_POLL_TIME);
1126
1127         if (REG_RD(p_hwfn, addr))
1128                 rc = 0;
1129         else
1130                 DP_NOTICE(p_hwfn,
1131                           "Failed to receive FW final cleanup notification\n");
1132
1133         /* Cleanup afterwards */
1134         REG_WR(p_hwfn, addr, 0);
1135
1136         return rc;
1137 }
1138
1139 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
1140 {
1141         int hw_mode = 0;
1142
1143         if (QED_IS_BB_B0(p_hwfn->cdev)) {
1144                 hw_mode |= 1 << MODE_BB;
1145         } else if (QED_IS_AH(p_hwfn->cdev)) {
1146                 hw_mode |= 1 << MODE_K2;
1147         } else {
1148                 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1149                           p_hwfn->cdev->type);
1150                 return -EINVAL;
1151         }
1152
1153         switch (p_hwfn->cdev->num_ports_in_engine) {
1154         case 1:
1155                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1156                 break;
1157         case 2:
1158                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1159                 break;
1160         case 4:
1161                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1162                 break;
1163         default:
1164                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
1165                           p_hwfn->cdev->num_ports_in_engine);
1166                 return -EINVAL;
1167         }
1168
1169         switch (p_hwfn->cdev->mf_mode) {
1170         case QED_MF_DEFAULT:
1171         case QED_MF_NPAR:
1172                 hw_mode |= 1 << MODE_MF_SI;
1173                 break;
1174         case QED_MF_OVLAN:
1175                 hw_mode |= 1 << MODE_MF_SD;
1176                 break;
1177         default:
1178                 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
1179                 hw_mode |= 1 << MODE_MF_SI;
1180         }
1181
1182         hw_mode |= 1 << MODE_ASIC;
1183
1184         if (p_hwfn->cdev->num_hwfns > 1)
1185                 hw_mode |= 1 << MODE_100G;
1186
1187         p_hwfn->hw_info.hw_mode = hw_mode;
1188
1189         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1190                    "Configuring function for hw_mode: 0x%08x\n",
1191                    p_hwfn->hw_info.hw_mode);
1192
1193         return 0;
1194 }
1195
1196 /* Init run time data for all PFs on an engine. */
1197 static void qed_init_cau_rt_data(struct qed_dev *cdev)
1198 {
1199         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1200         int i, igu_sb_id;
1201
1202         for_each_hwfn(cdev, i) {
1203                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1204                 struct qed_igu_info *p_igu_info;
1205                 struct qed_igu_block *p_block;
1206                 struct cau_sb_entry sb_entry;
1207
1208                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1209
1210                 for (igu_sb_id = 0;
1211                      igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
1212                         p_block = &p_igu_info->entry[igu_sb_id];
1213
1214                         if (!p_block->is_pf)
1215                                 continue;
1216
1217                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1218                                               p_block->function_id, 0, 0);
1219                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1220                                          sb_entry);
1221                 }
1222         }
1223 }
1224
1225 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
1226                                      struct qed_ptt *p_ptt)
1227 {
1228         u32 val, wr_mbs, cache_line_size;
1229
1230         val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1231         switch (val) {
1232         case 0:
1233                 wr_mbs = 128;
1234                 break;
1235         case 1:
1236                 wr_mbs = 256;
1237                 break;
1238         case 2:
1239                 wr_mbs = 512;
1240                 break;
1241         default:
1242                 DP_INFO(p_hwfn,
1243                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1244                         val);
1245                 return;
1246         }
1247
1248         cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
1249         switch (cache_line_size) {
1250         case 32:
1251                 val = 0;
1252                 break;
1253         case 64:
1254                 val = 1;
1255                 break;
1256         case 128:
1257                 val = 2;
1258                 break;
1259         case 256:
1260                 val = 3;
1261                 break;
1262         default:
1263                 DP_INFO(p_hwfn,
1264                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1265                         cache_line_size);
1266         }
1267
1268         if (L1_CACHE_BYTES > wr_mbs)
1269                 DP_INFO(p_hwfn,
1270                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1271                         L1_CACHE_BYTES, wr_mbs);
1272
1273         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1274         if (val > 0) {
1275                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1276                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1277         }
1278 }
1279
1280 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1281                               struct qed_ptt *p_ptt, int hw_mode)
1282 {
1283         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1284         struct qed_qm_common_rt_init_params params;
1285         struct qed_dev *cdev = p_hwfn->cdev;
1286         u8 vf_id, max_num_vfs;
1287         u16 num_pfs, pf_id;
1288         u32 concrete_fid;
1289         int rc = 0;
1290
1291         qed_init_cau_rt_data(cdev);
1292
1293         /* Program GTT windows */
1294         qed_gtt_init(p_hwfn);
1295
1296         if (p_hwfn->mcp_info) {
1297                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1298                         qm_info->pf_rl_en = 1;
1299                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1300                         qm_info->pf_wfq_en = 1;
1301         }
1302
1303         memset(&params, 0, sizeof(params));
1304         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
1305         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1306         params.pf_rl_en = qm_info->pf_rl_en;
1307         params.pf_wfq_en = qm_info->pf_wfq_en;
1308         params.vport_rl_en = qm_info->vport_rl_en;
1309         params.vport_wfq_en = qm_info->vport_wfq_en;
1310         params.port_params = qm_info->qm_port_params;
1311
1312         qed_qm_common_rt_init(p_hwfn, &params);
1313
1314         qed_cxt_hw_init_common(p_hwfn);
1315
1316         qed_init_cache_line_size(p_hwfn, p_ptt);
1317
1318         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1319         if (rc)
1320                 return rc;
1321
1322         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1323         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1324
1325         if (QED_IS_BB(p_hwfn->cdev)) {
1326                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1327                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1328                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1329                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1330                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1331                 }
1332                 /* pretend to original PF */
1333                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1334         }
1335
1336         max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1337         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1338                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1339                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1340                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1341                 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1342                 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1343                 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1344         }
1345         /* pretend to original PF */
1346         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1347
1348         return rc;
1349 }
1350
1351 static int
1352 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1353                      struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1354 {
1355         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1356         u32 min_dpis;
1357         u32 n_wids;
1358
1359         /* Calculate DPI size */
1360         n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
1361         dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
1362         dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
1363         dpi_bit_shift = ilog2(dpi_page_size / 4096);
1364         dpi_count = pwm_region_size / dpi_page_size;
1365
1366         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1367         min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1368
1369         p_hwfn->dpi_size = dpi_page_size;
1370         p_hwfn->dpi_count = dpi_count;
1371
1372         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1373
1374         if (dpi_count < min_dpis)
1375                 return -EINVAL;
1376
1377         return 0;
1378 }
1379
1380 enum QED_ROCE_EDPM_MODE {
1381         QED_ROCE_EDPM_MODE_ENABLE = 0,
1382         QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1383         QED_ROCE_EDPM_MODE_DISABLE = 2,
1384 };
1385
1386 static int
1387 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1388 {
1389         u32 pwm_regsize, norm_regsize;
1390         u32 non_pwm_conn, min_addr_reg1;
1391         u32 db_bar_size, n_cpus = 1;
1392         u32 roce_edpm_mode;
1393         u32 pf_dems_shift;
1394         int rc = 0;
1395         u8 cond;
1396
1397         db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1398         if (p_hwfn->cdev->num_hwfns > 1)
1399                 db_bar_size /= 2;
1400
1401         /* Calculate doorbell regions */
1402         non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1403                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1404                                                    NULL) +
1405                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1406                                                    NULL);
1407         norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
1408         min_addr_reg1 = norm_regsize / 4096;
1409         pwm_regsize = db_bar_size - norm_regsize;
1410
1411         /* Check that the normal and PWM sizes are valid */
1412         if (db_bar_size < norm_regsize) {
1413                 DP_ERR(p_hwfn->cdev,
1414                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1415                        db_bar_size, norm_regsize);
1416                 return -EINVAL;
1417         }
1418
1419         if (pwm_regsize < QED_MIN_PWM_REGION) {
1420                 DP_ERR(p_hwfn->cdev,
1421                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1422                        pwm_regsize,
1423                        QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1424                 return -EINVAL;
1425         }
1426
1427         /* Calculate number of DPIs */
1428         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1429         if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1430             ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1431                 /* Either EDPM is mandatory, or we are attempting to allocate a
1432                  * WID per CPU.
1433                  */
1434                 n_cpus = num_present_cpus();
1435                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1436         }
1437
1438         cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1439                (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1440         if (cond || p_hwfn->dcbx_no_edpm) {
1441                 /* Either EDPM is disabled from user configuration, or it is
1442                  * disabled via DCBx, or it is not mandatory and we failed to
1443                  * allocated a WID per CPU.
1444                  */
1445                 n_cpus = 1;
1446                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1447
1448                 if (cond)
1449                         qed_rdma_dpm_bar(p_hwfn, p_ptt);
1450         }
1451
1452         p_hwfn->wid_count = (u16) n_cpus;
1453
1454         DP_INFO(p_hwfn,
1455                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1456                 norm_regsize,
1457                 pwm_regsize,
1458                 p_hwfn->dpi_size,
1459                 p_hwfn->dpi_count,
1460                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1461                 "disabled" : "enabled");
1462
1463         if (rc) {
1464                 DP_ERR(p_hwfn,
1465                        "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1466                        p_hwfn->dpi_count,
1467                        p_hwfn->pf_params.rdma_pf_params.min_dpis);
1468                 return -EINVAL;
1469         }
1470
1471         p_hwfn->dpi_start_offset = norm_regsize;
1472
1473         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1474         pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1475         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1476         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1477
1478         return 0;
1479 }
1480
1481 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1482                             struct qed_ptt *p_ptt, int hw_mode)
1483 {
1484         int rc = 0;
1485
1486         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
1487         if (rc)
1488                 return rc;
1489
1490         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
1491
1492         return 0;
1493 }
1494
1495 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1496                           struct qed_ptt *p_ptt,
1497                           struct qed_tunnel_info *p_tunn,
1498                           int hw_mode,
1499                           bool b_hw_start,
1500                           enum qed_int_mode int_mode,
1501                           bool allow_npar_tx_switch)
1502 {
1503         u8 rel_pf_id = p_hwfn->rel_pf_id;
1504         int rc = 0;
1505
1506         if (p_hwfn->mcp_info) {
1507                 struct qed_mcp_function_info *p_info;
1508
1509                 p_info = &p_hwfn->mcp_info->func_info;
1510                 if (p_info->bandwidth_min)
1511                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1512
1513                 /* Update rate limit once we'll actually have a link */
1514                 p_hwfn->qm_info.pf_rl = 100000;
1515         }
1516
1517         qed_cxt_hw_init_pf(p_hwfn, p_ptt);
1518
1519         qed_int_igu_init_rt(p_hwfn);
1520
1521         /* Set VLAN in NIG if needed */
1522         if (hw_mode & BIT(MODE_MF_SD)) {
1523                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1524                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1525                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1526                              p_hwfn->hw_info.ovlan);
1527         }
1528
1529         /* Enable classification by MAC if needed */
1530         if (hw_mode & BIT(MODE_MF_SI)) {
1531                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1532                            "Configuring TAGMAC_CLS_TYPE\n");
1533                 STORE_RT_REG(p_hwfn,
1534                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1535         }
1536
1537         /* Protocl Configuration  */
1538         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1539                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1540         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1541                      (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
1542         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1543
1544         /* Cleanup chip from previous driver if such remains exist */
1545         rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1546         if (rc)
1547                 return rc;
1548
1549         /* PF Init sequence */
1550         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1551         if (rc)
1552                 return rc;
1553
1554         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1555         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1556         if (rc)
1557                 return rc;
1558
1559         /* Pure runtime initializations - directly to the HW  */
1560         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1561
1562         rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1563         if (rc)
1564                 return rc;
1565
1566         if (b_hw_start) {
1567                 /* enable interrupts */
1568                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1569
1570                 /* send function start command */
1571                 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
1572                                      p_hwfn->cdev->mf_mode,
1573                                      allow_npar_tx_switch);
1574                 if (rc) {
1575                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1576                         return rc;
1577                 }
1578                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1579                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1580                         qed_wr(p_hwfn, p_ptt,
1581                                PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1582                                0x100);
1583                 }
1584         }
1585         return rc;
1586 }
1587
1588 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1589                                struct qed_ptt *p_ptt,
1590                                u8 enable)
1591 {
1592         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1593
1594         /* Change PF in PXP */
1595         qed_wr(p_hwfn, p_ptt,
1596                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1597
1598         /* wait until value is set - try for 1 second every 50us */
1599         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1600                 val = qed_rd(p_hwfn, p_ptt,
1601                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1602                 if (val == set_val)
1603                         break;
1604
1605                 usleep_range(50, 60);
1606         }
1607
1608         if (val != set_val) {
1609                 DP_NOTICE(p_hwfn,
1610                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1611                 return -EAGAIN;
1612         }
1613
1614         return 0;
1615 }
1616
1617 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1618                                 struct qed_ptt *p_main_ptt)
1619 {
1620         /* Read shadow of current MFW mailbox */
1621         qed_mcp_read_mb(p_hwfn, p_main_ptt);
1622         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1623                p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
1624 }
1625
1626 static void
1627 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
1628                          struct qed_drv_load_params *p_drv_load)
1629 {
1630         memset(p_load_req, 0, sizeof(*p_load_req));
1631
1632         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1633                                QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
1634         p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
1635         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
1636         p_load_req->override_force_load = p_drv_load->override_force_load;
1637 }
1638
1639 static int qed_vf_start(struct qed_hwfn *p_hwfn,
1640                         struct qed_hw_init_params *p_params)
1641 {
1642         if (p_params->p_tunn) {
1643                 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1644                 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1645         }
1646
1647         p_hwfn->b_int_enabled = 1;
1648
1649         return 0;
1650 }
1651
1652 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
1653 {
1654         struct qed_load_req_params load_req_params;
1655         u32 load_code, param, drv_mb_param;
1656         bool b_default_mtu = true;
1657         struct qed_hwfn *p_hwfn;
1658         int rc = 0, mfw_rc, i;
1659
1660         if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
1661                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1662                 return -EINVAL;
1663         }
1664
1665         if (IS_PF(cdev)) {
1666                 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
1667                 if (rc)
1668                         return rc;
1669         }
1670
1671         for_each_hwfn(cdev, i) {
1672                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1673
1674                 /* If management didn't provide a default, set one of our own */
1675                 if (!p_hwfn->hw_info.mtu) {
1676                         p_hwfn->hw_info.mtu = 1500;
1677                         b_default_mtu = false;
1678                 }
1679
1680                 if (IS_VF(cdev)) {
1681                         qed_vf_start(p_hwfn, p_params);
1682                         continue;
1683                 }
1684
1685                 /* Enable DMAE in PXP */
1686                 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1687
1688                 rc = qed_calc_hw_mode(p_hwfn);
1689                 if (rc)
1690                         return rc;
1691
1692                 qed_fill_load_req_params(&load_req_params,
1693                                          p_params->p_drv_load_params);
1694                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1695                                       &load_req_params);
1696                 if (rc) {
1697                         DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
1698                         return rc;
1699                 }
1700
1701                 load_code = load_req_params.load_code;
1702                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1703                            "Load request was sent. Load code: 0x%x\n",
1704                            load_code);
1705
1706                 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
1707
1708                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1709
1710                 p_hwfn->first_on_engine = (load_code ==
1711                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1712
1713                 switch (load_code) {
1714                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1715                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1716                                                 p_hwfn->hw_info.hw_mode);
1717                         if (rc)
1718                                 break;
1719                 /* Fall into */
1720                 case FW_MSG_CODE_DRV_LOAD_PORT:
1721                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1722                                               p_hwfn->hw_info.hw_mode);
1723                         if (rc)
1724                                 break;
1725
1726                 /* Fall into */
1727                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1728                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1729                                             p_params->p_tunn,
1730                                             p_hwfn->hw_info.hw_mode,
1731                                             p_params->b_hw_start,
1732                                             p_params->int_mode,
1733                                             p_params->allow_npar_tx_switch);
1734                         break;
1735                 default:
1736                         DP_NOTICE(p_hwfn,
1737                                   "Unexpected load code [0x%08x]", load_code);
1738                         rc = -EINVAL;
1739                         break;
1740                 }
1741
1742                 if (rc)
1743                         DP_NOTICE(p_hwfn,
1744                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1745                                    load_code, rc);
1746
1747                 /* ACK mfw regardless of success or failure of initialization */
1748                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1749                                      DRV_MSG_CODE_LOAD_DONE,
1750                                      0, &load_code, &param);
1751                 if (rc)
1752                         return rc;
1753                 if (mfw_rc) {
1754                         DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1755                         return mfw_rc;
1756                 }
1757
1758                 /* Check if there is a DID mismatch between nvm-cfg/efuse */
1759                 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1760                         DP_NOTICE(p_hwfn,
1761                                   "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1762
1763                 /* send DCBX attention request command */
1764                 DP_VERBOSE(p_hwfn,
1765                            QED_MSG_DCB,
1766                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1767                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1768                                      DRV_MSG_CODE_SET_DCBX,
1769                                      1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1770                                      &load_code, &param);
1771                 if (mfw_rc) {
1772                         DP_NOTICE(p_hwfn,
1773                                   "Failed to send DCBX attention request\n");
1774                         return mfw_rc;
1775                 }
1776
1777                 p_hwfn->hw_init_done = true;
1778         }
1779
1780         if (IS_PF(cdev)) {
1781                 p_hwfn = QED_LEADING_HWFN(cdev);
1782                 drv_mb_param = STORM_FW_VERSION;
1783                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1784                                  DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1785                                  drv_mb_param, &load_code, &param);
1786                 if (rc)
1787                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
1788
1789                 if (!b_default_mtu) {
1790                         rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1791                                                    p_hwfn->hw_info.mtu);
1792                         if (rc)
1793                                 DP_INFO(p_hwfn,
1794                                         "Failed to update default mtu\n");
1795                 }
1796
1797                 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1798                                                     p_hwfn->p_main_ptt,
1799                                                   QED_OV_DRIVER_STATE_DISABLED);
1800                 if (rc)
1801                         DP_INFO(p_hwfn, "Failed to update driver state\n");
1802
1803                 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1804                                                QED_OV_ESWITCH_NONE);
1805                 if (rc)
1806                         DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1807         }
1808
1809         return 0;
1810 }
1811
1812 #define QED_HW_STOP_RETRY_LIMIT (10)
1813 static void qed_hw_timers_stop(struct qed_dev *cdev,
1814                                struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1815 {
1816         int i;
1817
1818         /* close timers */
1819         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1820         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1821
1822         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1823                 if ((!qed_rd(p_hwfn, p_ptt,
1824                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1825                     (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1826                         break;
1827
1828                 /* Dependent on number of connection/tasks, possibly
1829                  * 1ms sleep is required between polls
1830                  */
1831                 usleep_range(1000, 2000);
1832         }
1833
1834         if (i < QED_HW_STOP_RETRY_LIMIT)
1835                 return;
1836
1837         DP_NOTICE(p_hwfn,
1838                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1839                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1840                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1841 }
1842
1843 void qed_hw_timers_stop_all(struct qed_dev *cdev)
1844 {
1845         int j;
1846
1847         for_each_hwfn(cdev, j) {
1848                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1849                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1850
1851                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1852         }
1853 }
1854
1855 int qed_hw_stop(struct qed_dev *cdev)
1856 {
1857         struct qed_hwfn *p_hwfn;
1858         struct qed_ptt *p_ptt;
1859         int rc, rc2 = 0;
1860         int j;
1861
1862         for_each_hwfn(cdev, j) {
1863                 p_hwfn = &cdev->hwfns[j];
1864                 p_ptt = p_hwfn->p_main_ptt;
1865
1866                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1867
1868                 if (IS_VF(cdev)) {
1869                         qed_vf_pf_int_cleanup(p_hwfn);
1870                         rc = qed_vf_pf_reset(p_hwfn);
1871                         if (rc) {
1872                                 DP_NOTICE(p_hwfn,
1873                                           "qed_vf_pf_reset failed. rc = %d.\n",
1874                                           rc);
1875                                 rc2 = -EINVAL;
1876                         }
1877                         continue;
1878                 }
1879
1880                 /* mark the hw as uninitialized... */
1881                 p_hwfn->hw_init_done = false;
1882
1883                 /* Send unload command to MCP */
1884                 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
1885                 if (rc) {
1886                         DP_NOTICE(p_hwfn,
1887                                   "Failed sending a UNLOAD_REQ command. rc = %d.\n",
1888                                   rc);
1889                         rc2 = -EINVAL;
1890                 }
1891
1892                 qed_slowpath_irq_sync(p_hwfn);
1893
1894                 /* After this point no MFW attentions are expected, e.g. prevent
1895                  * race between pf stop and dcbx pf update.
1896                  */
1897                 rc = qed_sp_pf_stop(p_hwfn);
1898                 if (rc) {
1899                         DP_NOTICE(p_hwfn,
1900                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
1901                                   rc);
1902                         rc2 = -EINVAL;
1903                 }
1904
1905                 qed_wr(p_hwfn, p_ptt,
1906                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1907
1908                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1909                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1910                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1911                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1912                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1913
1914                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1915
1916                 /* Disable Attention Generation */
1917                 qed_int_igu_disable_int(p_hwfn, p_ptt);
1918
1919                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1920                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1921
1922                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1923
1924                 /* Need to wait 1ms to guarantee SBs are cleared */
1925                 usleep_range(1000, 2000);
1926
1927                 /* Disable PF in HW blocks */
1928                 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1929                 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
1930
1931                 qed_mcp_unload_done(p_hwfn, p_ptt);
1932                 if (rc) {
1933                         DP_NOTICE(p_hwfn,
1934                                   "Failed sending a UNLOAD_DONE command. rc = %d.\n",
1935                                   rc);
1936                         rc2 = -EINVAL;
1937                 }
1938         }
1939
1940         if (IS_PF(cdev)) {
1941                 p_hwfn = QED_LEADING_HWFN(cdev);
1942                 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
1943
1944                 /* Disable DMAE in PXP - in CMT, this should only be done for
1945                  * first hw-function, and only after all transactions have
1946                  * stopped for all active hw-functions.
1947                  */
1948                 rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false);
1949                 if (rc) {
1950                         DP_NOTICE(p_hwfn,
1951                                   "qed_change_pci_hwfn failed. rc = %d.\n", rc);
1952                         rc2 = -EINVAL;
1953                 }
1954         }
1955
1956         return rc2;
1957 }
1958
1959 int qed_hw_stop_fastpath(struct qed_dev *cdev)
1960 {
1961         int j;
1962
1963         for_each_hwfn(cdev, j) {
1964                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1965                 struct qed_ptt *p_ptt;
1966
1967                 if (IS_VF(cdev)) {
1968                         qed_vf_pf_int_cleanup(p_hwfn);
1969                         continue;
1970                 }
1971                 p_ptt = qed_ptt_acquire(p_hwfn);
1972                 if (!p_ptt)
1973                         return -EAGAIN;
1974
1975                 DP_VERBOSE(p_hwfn,
1976                            NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
1977
1978                 qed_wr(p_hwfn, p_ptt,
1979                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1980
1981                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1982                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1983                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1984                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1985                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1986
1987                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1988
1989                 /* Need to wait 1ms to guarantee SBs are cleared */
1990                 usleep_range(1000, 2000);
1991                 qed_ptt_release(p_hwfn, p_ptt);
1992         }
1993
1994         return 0;
1995 }
1996
1997 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
1998 {
1999         struct qed_ptt *p_ptt;
2000
2001         if (IS_VF(p_hwfn->cdev))
2002                 return 0;
2003
2004         p_ptt = qed_ptt_acquire(p_hwfn);
2005         if (!p_ptt)
2006                 return -EAGAIN;
2007
2008         /* If roce info is allocated it means roce is initialized and should
2009          * be enabled in searcher.
2010          */
2011         if (p_hwfn->p_rdma_info &&
2012             p_hwfn->b_rdma_enabled_in_prs)
2013                 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
2014
2015         /* Re-open incoming traffic */
2016         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2017         qed_ptt_release(p_hwfn, p_ptt);
2018
2019         return 0;
2020 }
2021
2022 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2023 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
2024 {
2025         qed_ptt_pool_free(p_hwfn);
2026         kfree(p_hwfn->hw_info.p_igu_info);
2027         p_hwfn->hw_info.p_igu_info = NULL;
2028 }
2029
2030 /* Setup bar access */
2031 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
2032 {
2033         /* clear indirect access */
2034         if (QED_IS_AH(p_hwfn->cdev)) {
2035                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2036                        PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
2037                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2038                        PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
2039                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2040                        PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
2041                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2042                        PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
2043         } else {
2044                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2045                        PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2046                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2047                        PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2048                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2049                        PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2050                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2051                        PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2052         }
2053
2054         /* Clean Previous errors if such exist */
2055         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2056                PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2057
2058         /* enable internal target-read */
2059         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2060                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2061 }
2062
2063 static void get_function_id(struct qed_hwfn *p_hwfn)
2064 {
2065         /* ME Register */
2066         p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
2067                                                   PXP_PF_ME_OPAQUE_ADDR);
2068
2069         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2070
2071         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2072         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2073                                       PXP_CONCRETE_FID_PFID);
2074         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2075                                     PXP_CONCRETE_FID_PORT);
2076
2077         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2078                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2079                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2080 }
2081
2082 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
2083 {
2084         u32 *feat_num = p_hwfn->hw_info.feat_num;
2085         struct qed_sb_cnt_info sb_cnt;
2086         u32 non_l2_sbs = 0;
2087
2088         memset(&sb_cnt, 0, sizeof(sb_cnt));
2089         qed_int_get_num_sbs(p_hwfn, &sb_cnt);
2090
2091         if (IS_ENABLED(CONFIG_QED_RDMA) &&
2092             QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2093                 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
2094                  * the status blocks equally between L2 / RoCE but with
2095                  * consideration as to how many l2 queues / cnqs we have.
2096                  */
2097                 feat_num[QED_RDMA_CNQ] =
2098                         min_t(u32, sb_cnt.cnt / 2,
2099                               RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
2100
2101                 non_l2_sbs = feat_num[QED_RDMA_CNQ];
2102         }
2103         if (QED_IS_L2_PERSONALITY(p_hwfn)) {
2104                 /* Start by allocating VF queues, then PF's */
2105                 feat_num[QED_VF_L2_QUE] = min_t(u32,
2106                                                 RESC_NUM(p_hwfn, QED_L2_QUEUE),
2107                                                 sb_cnt.iov_cnt);
2108                 feat_num[QED_PF_L2_QUE] = min_t(u32,
2109                                                 sb_cnt.cnt - non_l2_sbs,
2110                                                 RESC_NUM(p_hwfn,
2111                                                          QED_L2_QUEUE) -
2112                                                 FEAT_NUM(p_hwfn,
2113                                                          QED_VF_L2_QUE));
2114         }
2115
2116         if (QED_IS_FCOE_PERSONALITY(p_hwfn))
2117                 feat_num[QED_FCOE_CQ] =  min_t(u32, sb_cnt.cnt,
2118                                                RESC_NUM(p_hwfn,
2119                                                         QED_CMDQS_CQS));
2120
2121         if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
2122                 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
2123                                                RESC_NUM(p_hwfn,
2124                                                         QED_CMDQS_CQS));
2125         DP_VERBOSE(p_hwfn,
2126                    NETIF_MSG_PROBE,
2127                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
2128                    (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2129                    (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2130                    (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
2131                    (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
2132                    (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
2133                    (int)sb_cnt.cnt);
2134 }
2135
2136 const char *qed_hw_get_resc_name(enum qed_resources res_id)
2137 {
2138         switch (res_id) {
2139         case QED_L2_QUEUE:
2140                 return "L2_QUEUE";
2141         case QED_VPORT:
2142                 return "VPORT";
2143         case QED_RSS_ENG:
2144                 return "RSS_ENG";
2145         case QED_PQ:
2146                 return "PQ";
2147         case QED_RL:
2148                 return "RL";
2149         case QED_MAC:
2150                 return "MAC";
2151         case QED_VLAN:
2152                 return "VLAN";
2153         case QED_RDMA_CNQ_RAM:
2154                 return "RDMA_CNQ_RAM";
2155         case QED_ILT:
2156                 return "ILT";
2157         case QED_LL2_QUEUE:
2158                 return "LL2_QUEUE";
2159         case QED_CMDQS_CQS:
2160                 return "CMDQS_CQS";
2161         case QED_RDMA_STATS_QUEUE:
2162                 return "RDMA_STATS_QUEUE";
2163         case QED_BDQ:
2164                 return "BDQ";
2165         case QED_SB:
2166                 return "SB";
2167         default:
2168                 return "UNKNOWN_RESOURCE";
2169         }
2170 }
2171
2172 static int
2173 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2174                             struct qed_ptt *p_ptt,
2175                             enum qed_resources res_id,
2176                             u32 resc_max_val, u32 *p_mcp_resp)
2177 {
2178         int rc;
2179
2180         rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2181                                       resc_max_val, p_mcp_resp);
2182         if (rc) {
2183                 DP_NOTICE(p_hwfn,
2184                           "MFW response failure for a max value setting of resource %d [%s]\n",
2185                           res_id, qed_hw_get_resc_name(res_id));
2186                 return rc;
2187         }
2188
2189         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2190                 DP_INFO(p_hwfn,
2191                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2192                         res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2193
2194         return 0;
2195 }
2196
2197 static int
2198 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2199 {
2200         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2201         u32 resc_max_val, mcp_resp;
2202         u8 res_id;
2203         int rc;
2204
2205         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2206                 switch (res_id) {
2207                 case QED_LL2_QUEUE:
2208                         resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2209                         break;
2210                 case QED_RDMA_CNQ_RAM:
2211                         /* No need for a case for QED_CMDQS_CQS since
2212                          * CNQ/CMDQS are the same resource.
2213                          */
2214                         resc_max_val = NUM_OF_CMDQS_CQS;
2215                         break;
2216                 case QED_RDMA_STATS_QUEUE:
2217                         resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2218                             : RDMA_NUM_STATISTIC_COUNTERS_BB;
2219                         break;
2220                 case QED_BDQ:
2221                         resc_max_val = BDQ_NUM_RESOURCES;
2222                         break;
2223                 default:
2224                         continue;
2225                 }
2226
2227                 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2228                                                  resc_max_val, &mcp_resp);
2229                 if (rc)
2230                         return rc;
2231
2232                 /* There's no point to continue to the next resource if the
2233                  * command is not supported by the MFW.
2234                  * We do continue if the command is supported but the resource
2235                  * is unknown to the MFW. Such a resource will be later
2236                  * configured with the default allocation values.
2237                  */
2238                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2239                         return -EINVAL;
2240         }
2241
2242         return 0;
2243 }
2244
2245 static
2246 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2247                          enum qed_resources res_id,
2248                          u32 *p_resc_num, u32 *p_resc_start)
2249 {
2250         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2251         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2252
2253         switch (res_id) {
2254         case QED_L2_QUEUE:
2255                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2256                                MAX_NUM_L2_QUEUES_BB) / num_funcs;
2257                 break;
2258         case QED_VPORT:
2259                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2260                                MAX_NUM_VPORTS_BB) / num_funcs;
2261                 break;
2262         case QED_RSS_ENG:
2263                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2264                                ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2265                 break;
2266         case QED_PQ:
2267                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2268                                MAX_QM_TX_QUEUES_BB) / num_funcs;
2269                 *p_resc_num &= ~0x7;    /* The granularity of the PQs is 8 */
2270                 break;
2271         case QED_RL:
2272                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2273                 break;
2274         case QED_MAC:
2275         case QED_VLAN:
2276                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2277                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2278                 break;
2279         case QED_ILT:
2280                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2281                                PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2282                 break;
2283         case QED_LL2_QUEUE:
2284                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2285                 break;
2286         case QED_RDMA_CNQ_RAM:
2287         case QED_CMDQS_CQS:
2288                 /* CNQ/CMDQS are the same resource */
2289                 *p_resc_num = NUM_OF_CMDQS_CQS / num_funcs;
2290                 break;
2291         case QED_RDMA_STATS_QUEUE:
2292                 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2293                                RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2294                 break;
2295         case QED_BDQ:
2296                 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2297                     p_hwfn->hw_info.personality != QED_PCI_FCOE)
2298                         *p_resc_num = 0;
2299                 else
2300                         *p_resc_num = 1;
2301                 break;
2302         case QED_SB:
2303                 /* Since we want its value to reflect whether MFW supports
2304                  * the new scheme, have a default of 0.
2305                  */
2306                 *p_resc_num = 0;
2307                 break;
2308         default:
2309                 return -EINVAL;
2310         }
2311
2312         switch (res_id) {
2313         case QED_BDQ:
2314                 if (!*p_resc_num)
2315                         *p_resc_start = 0;
2316                 else if (p_hwfn->cdev->num_ports_in_engine == 4)
2317                         *p_resc_start = p_hwfn->port_id;
2318                 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2319                         *p_resc_start = p_hwfn->port_id;
2320                 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2321                         *p_resc_start = p_hwfn->port_id + 2;
2322                 break;
2323         default:
2324                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2325                 break;
2326         }
2327
2328         return 0;
2329 }
2330
2331 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2332                                   enum qed_resources res_id)
2333 {
2334         u32 dflt_resc_num = 0, dflt_resc_start = 0;
2335         u32 mcp_resp, *p_resc_num, *p_resc_start;
2336         int rc;
2337
2338         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2339         p_resc_start = &RESC_START(p_hwfn, res_id);
2340
2341         rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2342                                   &dflt_resc_start);
2343         if (rc) {
2344                 DP_ERR(p_hwfn,
2345                        "Failed to get default amount for resource %d [%s]\n",
2346                        res_id, qed_hw_get_resc_name(res_id));
2347                 return rc;
2348         }
2349
2350         rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2351                                    &mcp_resp, p_resc_num, p_resc_start);
2352         if (rc) {
2353                 DP_NOTICE(p_hwfn,
2354                           "MFW response failure for an allocation request for resource %d [%s]\n",
2355                           res_id, qed_hw_get_resc_name(res_id));
2356                 return rc;
2357         }
2358
2359         /* Default driver values are applied in the following cases:
2360          * - The resource allocation MB command is not supported by the MFW
2361          * - There is an internal error in the MFW while processing the request
2362          * - The resource ID is unknown to the MFW
2363          */
2364         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2365                 DP_INFO(p_hwfn,
2366                         "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2367                         res_id,
2368                         qed_hw_get_resc_name(res_id),
2369                         mcp_resp, dflt_resc_num, dflt_resc_start);
2370                 *p_resc_num = dflt_resc_num;
2371                 *p_resc_start = dflt_resc_start;
2372                 goto out;
2373         }
2374
2375 out:
2376         /* PQs have to divide by 8 [that's the HW granularity].
2377          * Reduce number so it would fit.
2378          */
2379         if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2380                 DP_INFO(p_hwfn,
2381                         "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2382                         *p_resc_num,
2383                         (*p_resc_num) & ~0x7,
2384                         *p_resc_start, (*p_resc_start) & ~0x7);
2385                 *p_resc_num &= ~0x7;
2386                 *p_resc_start &= ~0x7;
2387         }
2388
2389         return 0;
2390 }
2391
2392 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
2393 {
2394         int rc;
2395         u8 res_id;
2396
2397         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2398                 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2399                 if (rc)
2400                         return rc;
2401         }
2402
2403         return 0;
2404 }
2405
2406 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2407 {
2408         struct qed_resc_unlock_params resc_unlock_params;
2409         struct qed_resc_lock_params resc_lock_params;
2410         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2411         u8 res_id;
2412         int rc;
2413
2414         /* Setting the max values of the soft resources and the following
2415          * resources allocation queries should be atomic. Since several PFs can
2416          * run in parallel - a resource lock is needed.
2417          * If either the resource lock or resource set value commands are not
2418          * supported - skip the the max values setting, release the lock if
2419          * needed, and proceed to the queries. Other failures, including a
2420          * failure to acquire the lock, will cause this function to fail.
2421          */
2422         qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
2423                                        QED_RESC_LOCK_RESC_ALLOC, false);
2424
2425         rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2426         if (rc && rc != -EINVAL) {
2427                 return rc;
2428         } else if (rc == -EINVAL) {
2429                 DP_INFO(p_hwfn,
2430                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2431         } else if (!rc && !resc_lock_params.b_granted) {
2432                 DP_NOTICE(p_hwfn,
2433                           "Failed to acquire the resource lock for the resource allocation commands\n");
2434                 return -EBUSY;
2435         } else {
2436                 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2437                 if (rc && rc != -EINVAL) {
2438                         DP_NOTICE(p_hwfn,
2439                                   "Failed to set the max values of the soft resources\n");
2440                         goto unlock_and_exit;
2441                 } else if (rc == -EINVAL) {
2442                         DP_INFO(p_hwfn,
2443                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2444                         rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2445                                                  &resc_unlock_params);
2446                         if (rc)
2447                                 DP_INFO(p_hwfn,
2448                                         "Failed to release the resource lock for the resource allocation commands\n");
2449                 }
2450         }
2451
2452         rc = qed_hw_set_resc_info(p_hwfn);
2453         if (rc)
2454                 goto unlock_and_exit;
2455
2456         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2457                 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2458                 if (rc)
2459                         DP_INFO(p_hwfn,
2460                                 "Failed to release the resource lock for the resource allocation commands\n");
2461         }
2462
2463         /* Sanity for ILT */
2464         if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2465             (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2466                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2467                           RESC_START(p_hwfn, QED_ILT),
2468                           RESC_END(p_hwfn, QED_ILT) - 1);
2469                 return -EINVAL;
2470         }
2471
2472         /* This will also learn the number of SBs from MFW */
2473         if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
2474                 return -EINVAL;
2475
2476         qed_hw_set_feat(p_hwfn);
2477
2478         for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2479                 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2480                            qed_hw_get_resc_name(res_id),
2481                            RESC_NUM(p_hwfn, res_id),
2482                            RESC_START(p_hwfn, res_id));
2483
2484         return 0;
2485
2486 unlock_and_exit:
2487         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2488                 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2489         return rc;
2490 }
2491
2492 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2493 {
2494         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2495         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2496         struct qed_mcp_link_capabilities *p_caps;
2497         struct qed_mcp_link_params *link;
2498
2499         /* Read global nvm_cfg address */
2500         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2501
2502         /* Verify MCP has initialized it */
2503         if (!nvm_cfg_addr) {
2504                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2505                 return -EINVAL;
2506         }
2507
2508         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2509         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2510
2511         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2512                offsetof(struct nvm_cfg1, glob) +
2513                offsetof(struct nvm_cfg1_glob, core_cfg);
2514
2515         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2516
2517         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2518                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2519         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2520                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
2521                 break;
2522         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2523                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
2524                 break;
2525         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2526                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
2527                 break;
2528         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2529                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
2530                 break;
2531         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2532                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
2533                 break;
2534         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2535                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
2536                 break;
2537         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2538                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
2539                 break;
2540         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2541                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
2542                 break;
2543         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2544                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
2545                 break;
2546         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2547                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
2548                 break;
2549         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2550                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
2551                 break;
2552         default:
2553                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
2554                 break;
2555         }
2556
2557         /* Read default link configuration */
2558         link = &p_hwfn->mcp_info->link_input;
2559         p_caps = &p_hwfn->mcp_info->link_capabilities;
2560         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2561                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2562         link_temp = qed_rd(p_hwfn, p_ptt,
2563                            port_cfg_addr +
2564                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
2565         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2566         link->speed.advertised_speeds = link_temp;
2567
2568         link_temp = link->speed.advertised_speeds;
2569         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2570
2571         link_temp = qed_rd(p_hwfn, p_ptt,
2572                            port_cfg_addr +
2573                            offsetof(struct nvm_cfg1_port, link_settings));
2574         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2575                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2576         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2577                 link->speed.autoneg = true;
2578                 break;
2579         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2580                 link->speed.forced_speed = 1000;
2581                 break;
2582         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2583                 link->speed.forced_speed = 10000;
2584                 break;
2585         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2586                 link->speed.forced_speed = 25000;
2587                 break;
2588         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2589                 link->speed.forced_speed = 40000;
2590                 break;
2591         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2592                 link->speed.forced_speed = 50000;
2593                 break;
2594         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2595                 link->speed.forced_speed = 100000;
2596                 break;
2597         default:
2598                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
2599         }
2600
2601         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2602                 link->speed.autoneg;
2603
2604         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2605         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2606         link->pause.autoneg = !!(link_temp &
2607                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2608         link->pause.forced_rx = !!(link_temp &
2609                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2610         link->pause.forced_tx = !!(link_temp &
2611                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2612         link->loopback_mode = 0;
2613
2614         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
2615                 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
2616                                    offsetof(struct nvm_cfg1_port, ext_phy));
2617                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
2618                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
2619                 p_caps->default_eee = QED_MCP_EEE_ENABLED;
2620                 link->eee.enable = true;
2621                 switch (link_temp) {
2622                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
2623                         p_caps->default_eee = QED_MCP_EEE_DISABLED;
2624                         link->eee.enable = false;
2625                         break;
2626                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
2627                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
2628                         break;
2629                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
2630                         p_caps->eee_lpi_timer =
2631                             EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
2632                         break;
2633                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
2634                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
2635                         break;
2636                 }
2637
2638                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
2639                 link->eee.tx_lpi_enable = link->eee.enable;
2640                 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
2641         } else {
2642                 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
2643         }
2644
2645         DP_VERBOSE(p_hwfn,
2646                    NETIF_MSG_LINK,
2647                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
2648                    link->speed.forced_speed,
2649                    link->speed.advertised_speeds,
2650                    link->speed.autoneg,
2651                    link->pause.autoneg,
2652                    p_caps->default_eee, p_caps->eee_lpi_timer);
2653
2654         /* Read Multi-function information from shmem */
2655         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2656                offsetof(struct nvm_cfg1, glob) +
2657                offsetof(struct nvm_cfg1_glob, generic_cont0);
2658
2659         generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
2660
2661         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2662                   NVM_CFG1_GLOB_MF_MODE_OFFSET;
2663
2664         switch (mf_mode) {
2665         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2666                 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
2667                 break;
2668         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2669                 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
2670                 break;
2671         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2672                 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
2673                 break;
2674         }
2675         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2676                 p_hwfn->cdev->mf_mode);
2677
2678         /* Read Multi-function information from shmem */
2679         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2680                 offsetof(struct nvm_cfg1, glob) +
2681                 offsetof(struct nvm_cfg1_glob, device_capabilities);
2682
2683         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
2684         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2685                 __set_bit(QED_DEV_CAP_ETH,
2686                           &p_hwfn->hw_info.device_capabilities);
2687         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2688                 __set_bit(QED_DEV_CAP_FCOE,
2689                           &p_hwfn->hw_info.device_capabilities);
2690         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2691                 __set_bit(QED_DEV_CAP_ISCSI,
2692                           &p_hwfn->hw_info.device_capabilities);
2693         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2694                 __set_bit(QED_DEV_CAP_ROCE,
2695                           &p_hwfn->hw_info.device_capabilities);
2696
2697         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2698 }
2699
2700 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2701 {
2702         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2703         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2704         struct qed_dev *cdev = p_hwfn->cdev;
2705
2706         num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2707
2708         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2709          * in the other bits are selected.
2710          * Bits 1-15 are for functions 1-15, respectively, and their value is
2711          * '0' only for enabled functions (function 0 always exists and
2712          * enabled).
2713          * In case of CMT, only the "even" functions are enabled, and thus the
2714          * number of functions for both hwfns is learnt from the same bits.
2715          */
2716         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2717
2718         if (reg_function_hide & 0x1) {
2719                 if (QED_IS_BB(cdev)) {
2720                         if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
2721                                 num_funcs = 0;
2722                                 eng_mask = 0xaaaa;
2723                         } else {
2724                                 num_funcs = 1;
2725                                 eng_mask = 0x5554;
2726                         }
2727                 } else {
2728                         num_funcs = 1;
2729                         eng_mask = 0xfffe;
2730                 }
2731
2732                 /* Get the number of the enabled functions on the engine */
2733                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2734                 while (tmp) {
2735                         if (tmp & 0x1)
2736                                 num_funcs++;
2737                         tmp >>= 0x1;
2738                 }
2739
2740                 /* Get the PF index within the enabled functions */
2741                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2742                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2743                 while (tmp) {
2744                         if (tmp & 0x1)
2745                                 enabled_func_idx--;
2746                         tmp >>= 0x1;
2747                 }
2748         }
2749
2750         p_hwfn->num_funcs_on_engine = num_funcs;
2751         p_hwfn->enabled_func_idx = enabled_func_idx;
2752
2753         DP_VERBOSE(p_hwfn,
2754                    NETIF_MSG_PROBE,
2755                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2756                    p_hwfn->rel_pf_id,
2757                    p_hwfn->abs_pf_id,
2758                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2759 }
2760
2761 static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
2762                                     struct qed_ptt *p_ptt)
2763 {
2764         u32 port_mode;
2765
2766         port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0);
2767
2768         if (port_mode < 3) {
2769                 p_hwfn->cdev->num_ports_in_engine = 1;
2770         } else if (port_mode <= 5) {
2771                 p_hwfn->cdev->num_ports_in_engine = 2;
2772         } else {
2773                 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
2774                           p_hwfn->cdev->num_ports_in_engine);
2775
2776                 /* Default num_ports_in_engine to something */
2777                 p_hwfn->cdev->num_ports_in_engine = 1;
2778         }
2779 }
2780
2781 static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
2782                                     struct qed_ptt *p_ptt)
2783 {
2784         u32 port;
2785         int i;
2786
2787         p_hwfn->cdev->num_ports_in_engine = 0;
2788
2789         for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2790                 port = qed_rd(p_hwfn, p_ptt,
2791                               CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2792                 if (port & 1)
2793                         p_hwfn->cdev->num_ports_in_engine++;
2794         }
2795
2796         if (!p_hwfn->cdev->num_ports_in_engine) {
2797                 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
2798
2799                 /* Default num_ports_in_engine to something */
2800                 p_hwfn->cdev->num_ports_in_engine = 1;
2801         }
2802 }
2803
2804 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2805 {
2806         if (QED_IS_BB(p_hwfn->cdev))
2807                 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
2808         else
2809                 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
2810 }
2811
2812 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2813 {
2814         struct qed_mcp_link_capabilities *p_caps;
2815         u32 eee_status;
2816
2817         p_caps = &p_hwfn->mcp_info->link_capabilities;
2818         if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
2819                 return;
2820
2821         p_caps->eee_speed_caps = 0;
2822         eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
2823                             offsetof(struct public_port, eee_status));
2824         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
2825                         EEE_SUPPORTED_SPEED_OFFSET;
2826
2827         if (eee_status & EEE_1G_SUPPORTED)
2828                 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
2829         if (eee_status & EEE_10G_ADV)
2830                 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
2831 }
2832
2833 static int
2834 qed_get_hw_info(struct qed_hwfn *p_hwfn,
2835                 struct qed_ptt *p_ptt,
2836                 enum qed_pci_personality personality)
2837 {
2838         int rc;
2839
2840         /* Since all information is common, only first hwfns should do this */
2841         if (IS_LEAD_HWFN(p_hwfn)) {
2842                 rc = qed_iov_hw_info(p_hwfn);
2843                 if (rc)
2844                         return rc;
2845         }
2846
2847         qed_hw_info_port_num(p_hwfn, p_ptt);
2848
2849         qed_mcp_get_capabilities(p_hwfn, p_ptt);
2850
2851         qed_hw_get_nvm_info(p_hwfn, p_ptt);
2852
2853         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
2854         if (rc)
2855                 return rc;
2856
2857         if (qed_mcp_is_init(p_hwfn))
2858                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
2859                                 p_hwfn->mcp_info->func_info.mac);
2860         else
2861                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
2862
2863         if (qed_mcp_is_init(p_hwfn)) {
2864                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
2865                         p_hwfn->hw_info.ovlan =
2866                                 p_hwfn->mcp_info->func_info.ovlan;
2867
2868                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
2869
2870                 qed_get_eee_caps(p_hwfn, p_ptt);
2871         }
2872
2873         if (qed_mcp_is_init(p_hwfn)) {
2874                 enum qed_pci_personality protocol;
2875
2876                 protocol = p_hwfn->mcp_info->func_info.protocol;
2877                 p_hwfn->hw_info.personality = protocol;
2878         }
2879
2880         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2881         p_hwfn->hw_info.num_active_tc = 1;
2882
2883         qed_get_num_funcs(p_hwfn, p_ptt);
2884
2885         if (qed_mcp_is_init(p_hwfn))
2886                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
2887
2888         return qed_hw_get_resc(p_hwfn, p_ptt);
2889 }
2890
2891 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2892 {
2893         struct qed_dev *cdev = p_hwfn->cdev;
2894         u16 device_id_mask;
2895         u32 tmp;
2896
2897         /* Read Vendor Id / Device Id */
2898         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
2899         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
2900
2901         /* Determine type */
2902         device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
2903         switch (device_id_mask) {
2904         case QED_DEV_ID_MASK_BB:
2905                 cdev->type = QED_DEV_TYPE_BB;
2906                 break;
2907         case QED_DEV_ID_MASK_AH:
2908                 cdev->type = QED_DEV_TYPE_AH;
2909                 break;
2910         default:
2911                 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
2912                 return -EBUSY;
2913         }
2914
2915         cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
2916         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
2917
2918         MASK_FIELD(CHIP_REV, cdev->chip_rev);
2919
2920         /* Learn number of HW-functions */
2921         tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
2922
2923         if (tmp & (1 << p_hwfn->rel_pf_id)) {
2924                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
2925                 cdev->num_hwfns = 2;
2926         } else {
2927                 cdev->num_hwfns = 1;
2928         }
2929
2930         cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
2931                                     MISCS_REG_CHIP_TEST_REG) >> 4;
2932         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
2933         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
2934         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
2935
2936         DP_INFO(cdev->hwfns,
2937                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2938                 QED_IS_BB(cdev) ? "BB" : "AH",
2939                 'A' + cdev->chip_rev,
2940                 (int)cdev->chip_metal,
2941                 cdev->chip_num, cdev->chip_rev,
2942                 cdev->chip_bond_id, cdev->chip_metal);
2943
2944         return 0;
2945 }
2946
2947 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
2948                                  void __iomem *p_regview,
2949                                  void __iomem *p_doorbells,
2950                                  u64 db_phys_addr,
2951                                  enum qed_pci_personality personality)
2952 {
2953         int rc = 0;
2954
2955         /* Split PCI bars evenly between hwfns */
2956         p_hwfn->regview = p_regview;
2957         p_hwfn->doorbells = p_doorbells;
2958         p_hwfn->db_phys_addr = db_phys_addr;
2959
2960         if (IS_VF(p_hwfn->cdev))
2961                 return qed_vf_hw_prepare(p_hwfn);
2962
2963         /* Validate that chip access is feasible */
2964         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2965                 DP_ERR(p_hwfn,
2966                        "Reading the ME register returns all Fs; Preventing further chip access\n");
2967                 return -EINVAL;
2968         }
2969
2970         get_function_id(p_hwfn);
2971
2972         /* Allocate PTT pool */
2973         rc = qed_ptt_pool_alloc(p_hwfn);
2974         if (rc)
2975                 goto err0;
2976
2977         /* Allocate the main PTT */
2978         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2979
2980         /* First hwfn learns basic information, e.g., number of hwfns */
2981         if (!p_hwfn->my_id) {
2982                 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
2983                 if (rc)
2984                         goto err1;
2985         }
2986
2987         qed_hw_hwfn_prepare(p_hwfn);
2988
2989         /* Initialize MCP structure */
2990         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2991         if (rc) {
2992                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
2993                 goto err1;
2994         }
2995
2996         /* Read the device configuration information from the HW and SHMEM */
2997         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2998         if (rc) {
2999                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
3000                 goto err2;
3001         }
3002
3003         /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
3004          * is called as it sets the ports number in an engine.
3005          */
3006         if (IS_LEAD_HWFN(p_hwfn)) {
3007                 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3008                 if (rc)
3009                         DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
3010         }
3011
3012         /* Allocate the init RT array and initialize the init-ops engine */
3013         rc = qed_init_alloc(p_hwfn);
3014         if (rc)
3015                 goto err2;
3016
3017         return rc;
3018 err2:
3019         if (IS_LEAD_HWFN(p_hwfn))
3020                 qed_iov_free_hw_info(p_hwfn->cdev);
3021         qed_mcp_free(p_hwfn);
3022 err1:
3023         qed_hw_hwfn_free(p_hwfn);
3024 err0:
3025         return rc;
3026 }
3027
3028 int qed_hw_prepare(struct qed_dev *cdev,
3029                    int personality)
3030 {
3031         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3032         int rc;
3033
3034         /* Store the precompiled init data ptrs */
3035         if (IS_PF(cdev))
3036                 qed_init_iro_array(cdev);
3037
3038         /* Initialize the first hwfn - will learn number of hwfns */
3039         rc = qed_hw_prepare_single(p_hwfn,
3040                                    cdev->regview,
3041                                    cdev->doorbells,
3042                                    cdev->db_phys_addr,
3043                                    personality);
3044         if (rc)
3045                 return rc;
3046
3047         personality = p_hwfn->hw_info.personality;
3048
3049         /* Initialize the rest of the hwfns */
3050         if (cdev->num_hwfns > 1) {
3051                 void __iomem *p_regview, *p_doorbell;
3052                 u64 db_phys_addr;
3053                 u32 offset;
3054
3055                 /* adjust bar offset for second engine */
3056                 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3057                                          BAR_ID_0) / 2;
3058                 p_regview = cdev->regview + offset;
3059
3060                 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3061                                          BAR_ID_1) / 2;
3062
3063                 p_doorbell = cdev->doorbells + offset;
3064
3065                 db_phys_addr = cdev->db_phys_addr + offset;
3066
3067                 /* prepare second hw function */
3068                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
3069                                            p_doorbell, db_phys_addr,
3070                                            personality);
3071
3072                 /* in case of error, need to free the previously
3073                  * initiliazed hwfn 0.
3074                  */
3075                 if (rc) {
3076                         if (IS_PF(cdev)) {
3077                                 qed_init_free(p_hwfn);
3078                                 qed_mcp_free(p_hwfn);
3079                                 qed_hw_hwfn_free(p_hwfn);
3080                         }
3081                 }
3082         }
3083
3084         return rc;
3085 }
3086
3087 void qed_hw_remove(struct qed_dev *cdev)
3088 {
3089         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3090         int i;
3091
3092         if (IS_PF(cdev))
3093                 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3094                                                QED_OV_DRIVER_STATE_NOT_LOADED);
3095
3096         for_each_hwfn(cdev, i) {
3097                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3098
3099                 if (IS_VF(cdev)) {
3100                         qed_vf_pf_release(p_hwfn);
3101                         continue;
3102                 }
3103
3104                 qed_init_free(p_hwfn);
3105                 qed_hw_hwfn_free(p_hwfn);
3106                 qed_mcp_free(p_hwfn);
3107         }
3108
3109         qed_iov_free_hw_info(cdev);
3110 }
3111
3112 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
3113                                     struct qed_chain *p_chain)
3114 {
3115         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
3116         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3117         struct qed_chain_next *p_next;
3118         u32 size, i;
3119
3120         if (!p_virt)
3121                 return;
3122
3123         size = p_chain->elem_size * p_chain->usable_per_page;
3124
3125         for (i = 0; i < p_chain->page_cnt; i++) {
3126                 if (!p_virt)
3127                         break;
3128
3129                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
3130                 p_virt_next = p_next->next_virt;
3131                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3132
3133                 dma_free_coherent(&cdev->pdev->dev,
3134                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
3135
3136                 p_virt = p_virt_next;
3137                 p_phys = p_phys_next;
3138         }
3139 }
3140
3141 static void qed_chain_free_single(struct qed_dev *cdev,
3142                                   struct qed_chain *p_chain)
3143 {
3144         if (!p_chain->p_virt_addr)
3145                 return;
3146
3147         dma_free_coherent(&cdev->pdev->dev,
3148                           QED_CHAIN_PAGE_SIZE,
3149                           p_chain->p_virt_addr, p_chain->p_phys_addr);
3150 }
3151
3152 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3153 {
3154         struct addr_tbl_entry *pp_addr_tbl = p_chain->pbl.pp_addr_tbl;
3155         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3156
3157         if (!pp_addr_tbl)
3158                 return;
3159
3160         for (i = 0; i < page_cnt; i++) {
3161                 if (!pp_addr_tbl[i].virt_addr || !pp_addr_tbl[i].dma_map)
3162                         break;
3163
3164                 dma_free_coherent(&cdev->pdev->dev,
3165                                   QED_CHAIN_PAGE_SIZE,
3166                                   pp_addr_tbl[i].virt_addr,
3167                                   pp_addr_tbl[i].dma_map);
3168         }
3169
3170         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3171
3172         if (!p_chain->b_external_pbl)
3173                 dma_free_coherent(&cdev->pdev->dev,
3174                                   pbl_size,
3175                                   p_chain->pbl_sp.p_virt_table,
3176                                   p_chain->pbl_sp.p_phys_table);
3177
3178         vfree(p_chain->pbl.pp_addr_tbl);
3179         p_chain->pbl.pp_addr_tbl = NULL;
3180 }
3181
3182 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3183 {
3184         switch (p_chain->mode) {
3185         case QED_CHAIN_MODE_NEXT_PTR:
3186                 qed_chain_free_next_ptr(cdev, p_chain);
3187                 break;
3188         case QED_CHAIN_MODE_SINGLE:
3189                 qed_chain_free_single(cdev, p_chain);
3190                 break;
3191         case QED_CHAIN_MODE_PBL:
3192                 qed_chain_free_pbl(cdev, p_chain);
3193                 break;
3194         }
3195 }
3196
3197 static int
3198 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3199                              enum qed_chain_cnt_type cnt_type,
3200                              size_t elem_size, u32 page_cnt)
3201 {
3202         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3203
3204         /* The actual chain size can be larger than the maximal possible value
3205          * after rounding up the requested elements number to pages, and after
3206          * taking into acount the unusuable elements (next-ptr elements).
3207          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3208          * size/capacity fields are of a u32 type.
3209          */
3210         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
3211              chain_size > ((u32)U16_MAX + 1)) ||
3212             (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
3213                 DP_NOTICE(cdev,
3214                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3215                           chain_size);
3216                 return -EINVAL;
3217         }
3218
3219         return 0;
3220 }
3221
3222 static int
3223 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3224 {
3225         void *p_virt = NULL, *p_virt_prev = NULL;
3226         dma_addr_t p_phys = 0;
3227         u32 i;
3228
3229         for (i = 0; i < p_chain->page_cnt; i++) {
3230                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3231                                             QED_CHAIN_PAGE_SIZE,
3232                                             &p_phys, GFP_KERNEL);
3233                 if (!p_virt)
3234                         return -ENOMEM;
3235
3236                 if (i == 0) {
3237                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3238                         qed_chain_reset(p_chain);
3239                 } else {
3240                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3241                                                      p_virt, p_phys);
3242                 }
3243
3244                 p_virt_prev = p_virt;
3245         }
3246         /* Last page's next element should point to the beginning of the
3247          * chain.
3248          */
3249         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3250                                      p_chain->p_virt_addr,
3251                                      p_chain->p_phys_addr);
3252
3253         return 0;
3254 }
3255
3256 static int
3257 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3258 {
3259         dma_addr_t p_phys = 0;
3260         void *p_virt = NULL;
3261
3262         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3263                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
3264         if (!p_virt)
3265                 return -ENOMEM;
3266
3267         qed_chain_init_mem(p_chain, p_virt, p_phys);
3268         qed_chain_reset(p_chain);
3269
3270         return 0;
3271 }
3272
3273 static int
3274 qed_chain_alloc_pbl(struct qed_dev *cdev,
3275                     struct qed_chain *p_chain,
3276                     struct qed_chain_ext_pbl *ext_pbl)
3277 {
3278         u32 page_cnt = p_chain->page_cnt, size, i;
3279         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3280         struct addr_tbl_entry *pp_addr_tbl;
3281         u8 *p_pbl_virt = NULL;
3282         void *p_virt = NULL;
3283
3284         size = page_cnt * sizeof(*pp_addr_tbl);
3285         pp_addr_tbl =  vzalloc(size);
3286         if (!pp_addr_tbl)
3287                 return -ENOMEM;
3288
3289         /* The allocation of the PBL table is done with its full size, since it
3290          * is expected to be successive.
3291          * qed_chain_init_pbl_mem() is called even in a case of an allocation
3292          * failure, since tbl was previously allocated, and it
3293          * should be saved to allow its freeing during the error flow.
3294          */
3295         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3296
3297         if (!ext_pbl) {
3298                 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3299                                                 size, &p_pbl_phys, GFP_KERNEL);
3300         } else {
3301                 p_pbl_virt = ext_pbl->p_pbl_virt;
3302                 p_pbl_phys = ext_pbl->p_pbl_phys;
3303                 p_chain->b_external_pbl = true;
3304         }
3305
3306         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, pp_addr_tbl);
3307         if (!p_pbl_virt)
3308                 return -ENOMEM;
3309
3310         for (i = 0; i < page_cnt; i++) {
3311                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3312                                             QED_CHAIN_PAGE_SIZE,
3313                                             &p_phys, GFP_KERNEL);
3314                 if (!p_virt)
3315                         return -ENOMEM;
3316
3317                 if (i == 0) {
3318                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3319                         qed_chain_reset(p_chain);
3320                 }
3321
3322                 /* Fill the PBL table with the physical address of the page */
3323                 *(dma_addr_t *)p_pbl_virt = p_phys;
3324                 /* Keep the virtual address of the page */
3325                 p_chain->pbl.pp_addr_tbl[i].virt_addr = p_virt;
3326                 p_chain->pbl.pp_addr_tbl[i].dma_map = p_phys;
3327
3328                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3329         }
3330
3331         return 0;
3332 }
3333
3334 int qed_chain_alloc(struct qed_dev *cdev,
3335                     enum qed_chain_use_mode intended_use,
3336                     enum qed_chain_mode mode,
3337                     enum qed_chain_cnt_type cnt_type,
3338                     u32 num_elems,
3339                     size_t elem_size,
3340                     struct qed_chain *p_chain,
3341                     struct qed_chain_ext_pbl *ext_pbl)
3342 {
3343         u32 page_cnt;
3344         int rc = 0;
3345
3346         if (mode == QED_CHAIN_MODE_SINGLE)
3347                 page_cnt = 1;
3348         else
3349                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3350
3351         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3352         if (rc) {
3353                 DP_NOTICE(cdev,
3354                           "Cannot allocate a chain with the given arguments:\n");
3355                 DP_NOTICE(cdev,
3356                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3357                           intended_use, mode, cnt_type, num_elems, elem_size);
3358                 return rc;
3359         }
3360
3361         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3362                               mode, cnt_type);
3363
3364         switch (mode) {
3365         case QED_CHAIN_MODE_NEXT_PTR:
3366                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3367                 break;
3368         case QED_CHAIN_MODE_SINGLE:
3369                 rc = qed_chain_alloc_single(cdev, p_chain);
3370                 break;
3371         case QED_CHAIN_MODE_PBL:
3372                 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
3373                 break;
3374         }
3375         if (rc)
3376                 goto nomem;
3377
3378         return 0;
3379
3380 nomem:
3381         qed_chain_free(cdev, p_chain);
3382         return rc;
3383 }
3384
3385 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
3386 {
3387         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3388                 u16 min, max;
3389
3390                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
3391                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3392                 DP_NOTICE(p_hwfn,
3393                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3394                           src_id, min, max);
3395
3396                 return -EINVAL;
3397         }
3398
3399         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3400
3401         return 0;
3402 }
3403
3404 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3405 {
3406         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3407                 u8 min, max;
3408
3409                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3410                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3411                 DP_NOTICE(p_hwfn,
3412                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3413                           src_id, min, max);
3414
3415                 return -EINVAL;
3416         }
3417
3418         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3419
3420         return 0;
3421 }
3422
3423 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3424 {
3425         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3426                 u8 min, max;
3427
3428                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3429                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3430                 DP_NOTICE(p_hwfn,
3431                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3432                           src_id, min, max);
3433
3434                 return -EINVAL;
3435         }
3436
3437         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3438
3439         return 0;
3440 }
3441
3442 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3443                                   u8 *p_filter)
3444 {
3445         *p_high = p_filter[1] | (p_filter[0] << 8);
3446         *p_low = p_filter[5] | (p_filter[4] << 8) |
3447                  (p_filter[3] << 16) | (p_filter[2] << 24);
3448 }
3449
3450 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3451                            struct qed_ptt *p_ptt, u8 *p_filter)
3452 {
3453         u32 high = 0, low = 0, en;
3454         int i;
3455
3456         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3457                 return 0;
3458
3459         qed_llh_mac_to_filter(&high, &low, p_filter);
3460
3461         /* Find a free entry and utilize it */
3462         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3463                 en = qed_rd(p_hwfn, p_ptt,
3464                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3465                 if (en)
3466                         continue;
3467                 qed_wr(p_hwfn, p_ptt,
3468                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3469                        2 * i * sizeof(u32), low);
3470                 qed_wr(p_hwfn, p_ptt,
3471                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3472                        (2 * i + 1) * sizeof(u32), high);
3473                 qed_wr(p_hwfn, p_ptt,
3474                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3475                 qed_wr(p_hwfn, p_ptt,
3476                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3477                        i * sizeof(u32), 0);
3478                 qed_wr(p_hwfn, p_ptt,
3479                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3480                 break;
3481         }
3482         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3483                 DP_NOTICE(p_hwfn,
3484                           "Failed to find an empty LLH filter to utilize\n");
3485                 return -EINVAL;
3486         }
3487
3488         DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3489                    "mac: %pM is added at %d\n",
3490                    p_filter, i);
3491
3492         return 0;
3493 }
3494
3495 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
3496                                struct qed_ptt *p_ptt, u8 *p_filter)
3497 {
3498         u32 high = 0, low = 0;
3499         int i;
3500
3501         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3502                 return;
3503
3504         qed_llh_mac_to_filter(&high, &low, p_filter);
3505
3506         /* Find the entry and clean it */
3507         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3508                 if (qed_rd(p_hwfn, p_ptt,
3509                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3510                            2 * i * sizeof(u32)) != low)
3511                         continue;
3512                 if (qed_rd(p_hwfn, p_ptt,
3513                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3514                            (2 * i + 1) * sizeof(u32)) != high)
3515                         continue;
3516
3517                 qed_wr(p_hwfn, p_ptt,
3518                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3519                 qed_wr(p_hwfn, p_ptt,
3520                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3521                 qed_wr(p_hwfn, p_ptt,
3522                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3523                        (2 * i + 1) * sizeof(u32), 0);
3524
3525                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3526                            "mac: %pM is removed from %d\n",
3527                            p_filter, i);
3528                 break;
3529         }
3530         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3531                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3532 }
3533
3534 int
3535 qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
3536                             struct qed_ptt *p_ptt,
3537                             u16 source_port_or_eth_type,
3538                             u16 dest_port, enum qed_llh_port_filter_type_t type)
3539 {
3540         u32 high = 0, low = 0, en;
3541         int i;
3542
3543         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3544                 return 0;
3545
3546         switch (type) {
3547         case QED_LLH_FILTER_ETHERTYPE:
3548                 high = source_port_or_eth_type;
3549                 break;
3550         case QED_LLH_FILTER_TCP_SRC_PORT:
3551         case QED_LLH_FILTER_UDP_SRC_PORT:
3552                 low = source_port_or_eth_type << 16;
3553                 break;
3554         case QED_LLH_FILTER_TCP_DEST_PORT:
3555         case QED_LLH_FILTER_UDP_DEST_PORT:
3556                 low = dest_port;
3557                 break;
3558         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3559         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3560                 low = (source_port_or_eth_type << 16) | dest_port;
3561                 break;
3562         default:
3563                 DP_NOTICE(p_hwfn,
3564                           "Non valid LLH protocol filter type %d\n", type);
3565                 return -EINVAL;
3566         }
3567         /* Find a free entry and utilize it */
3568         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3569                 en = qed_rd(p_hwfn, p_ptt,
3570                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3571                 if (en)
3572                         continue;
3573                 qed_wr(p_hwfn, p_ptt,
3574                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3575                        2 * i * sizeof(u32), low);
3576                 qed_wr(p_hwfn, p_ptt,
3577                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3578                        (2 * i + 1) * sizeof(u32), high);
3579                 qed_wr(p_hwfn, p_ptt,
3580                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3581                 qed_wr(p_hwfn, p_ptt,
3582                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3583                        i * sizeof(u32), 1 << type);
3584                 qed_wr(p_hwfn, p_ptt,
3585                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3586                 break;
3587         }
3588         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3589                 DP_NOTICE(p_hwfn,
3590                           "Failed to find an empty LLH filter to utilize\n");
3591                 return -EINVAL;
3592         }
3593         switch (type) {
3594         case QED_LLH_FILTER_ETHERTYPE:
3595                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3596                            "ETH type %x is added at %d\n",
3597                            source_port_or_eth_type, i);
3598                 break;
3599         case QED_LLH_FILTER_TCP_SRC_PORT:
3600                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3601                            "TCP src port %x is added at %d\n",
3602                            source_port_or_eth_type, i);
3603                 break;
3604         case QED_LLH_FILTER_UDP_SRC_PORT:
3605                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3606                            "UDP src port %x is added at %d\n",
3607                            source_port_or_eth_type, i);
3608                 break;
3609         case QED_LLH_FILTER_TCP_DEST_PORT:
3610                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3611                            "TCP dst port %x is added at %d\n", dest_port, i);
3612                 break;
3613         case QED_LLH_FILTER_UDP_DEST_PORT:
3614                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3615                            "UDP dst port %x is added at %d\n", dest_port, i);
3616                 break;
3617         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3618                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3619                            "TCP src/dst ports %x/%x are added at %d\n",
3620                            source_port_or_eth_type, dest_port, i);
3621                 break;
3622         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3623                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3624                            "UDP src/dst ports %x/%x are added at %d\n",
3625                            source_port_or_eth_type, dest_port, i);
3626                 break;
3627         }
3628         return 0;
3629 }
3630
3631 void
3632 qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
3633                                struct qed_ptt *p_ptt,
3634                                u16 source_port_or_eth_type,
3635                                u16 dest_port,
3636                                enum qed_llh_port_filter_type_t type)
3637 {
3638         u32 high = 0, low = 0;
3639         int i;
3640
3641         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3642                 return;
3643
3644         switch (type) {
3645         case QED_LLH_FILTER_ETHERTYPE:
3646                 high = source_port_or_eth_type;
3647                 break;
3648         case QED_LLH_FILTER_TCP_SRC_PORT:
3649         case QED_LLH_FILTER_UDP_SRC_PORT:
3650                 low = source_port_or_eth_type << 16;
3651                 break;
3652         case QED_LLH_FILTER_TCP_DEST_PORT:
3653         case QED_LLH_FILTER_UDP_DEST_PORT:
3654                 low = dest_port;
3655                 break;
3656         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3657         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3658                 low = (source_port_or_eth_type << 16) | dest_port;
3659                 break;
3660         default:
3661                 DP_NOTICE(p_hwfn,
3662                           "Non valid LLH protocol filter type %d\n", type);
3663                 return;
3664         }
3665
3666         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3667                 if (!qed_rd(p_hwfn, p_ptt,
3668                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3669                         continue;
3670                 if (!qed_rd(p_hwfn, p_ptt,
3671                             NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3672                         continue;
3673                 if (!(qed_rd(p_hwfn, p_ptt,
3674                              NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3675                              i * sizeof(u32)) & BIT(type)))
3676                         continue;
3677                 if (qed_rd(p_hwfn, p_ptt,
3678                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3679                            2 * i * sizeof(u32)) != low)
3680                         continue;
3681                 if (qed_rd(p_hwfn, p_ptt,
3682                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3683                            (2 * i + 1) * sizeof(u32)) != high)
3684                         continue;
3685
3686                 qed_wr(p_hwfn, p_ptt,
3687                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3688                 qed_wr(p_hwfn, p_ptt,
3689                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3690                 qed_wr(p_hwfn, p_ptt,
3691                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3692                        i * sizeof(u32), 0);
3693                 qed_wr(p_hwfn, p_ptt,
3694                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3695                 qed_wr(p_hwfn, p_ptt,
3696                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3697                        (2 * i + 1) * sizeof(u32), 0);
3698                 break;
3699         }
3700
3701         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3702                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3703 }
3704
3705 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3706                             u32 hw_addr, void *p_eth_qzone,
3707                             size_t eth_qzone_size, u8 timeset)
3708 {
3709         struct coalescing_timeset *p_coal_timeset;
3710
3711         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
3712                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
3713                 return -EINVAL;
3714         }
3715
3716         p_coal_timeset = p_eth_qzone;
3717         memset(p_eth_qzone, 0, eth_qzone_size);
3718         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3719         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3720         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3721
3722         return 0;
3723 }
3724
3725 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
3726 {
3727         struct qed_queue_cid *p_cid = p_handle;
3728         struct qed_hwfn *p_hwfn;
3729         struct qed_ptt *p_ptt;
3730         int rc = 0;
3731
3732         p_hwfn = p_cid->p_owner;
3733
3734         if (IS_VF(p_hwfn->cdev))
3735                 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
3736
3737         p_ptt = qed_ptt_acquire(p_hwfn);
3738         if (!p_ptt)
3739                 return -EAGAIN;
3740
3741         if (rx_coal) {
3742                 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
3743                 if (rc)
3744                         goto out;
3745                 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
3746         }
3747
3748         if (tx_coal) {
3749                 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
3750                 if (rc)
3751                         goto out;
3752                 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
3753         }
3754 out:
3755         qed_ptt_release(p_hwfn, p_ptt);
3756         return rc;
3757 }
3758
3759 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
3760                          struct qed_ptt *p_ptt,
3761                          u16 coalesce, struct qed_queue_cid *p_cid)
3762 {
3763         struct ustorm_eth_queue_zone eth_qzone;
3764         u8 timeset, timer_res;
3765         u32 address;
3766         int rc;
3767
3768         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3769         if (coalesce <= 0x7F) {
3770                 timer_res = 0;
3771         } else if (coalesce <= 0xFF) {
3772                 timer_res = 1;
3773         } else if (coalesce <= 0x1FF) {
3774                 timer_res = 2;
3775         } else {
3776                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3777                 return -EINVAL;
3778         }
3779         timeset = (u8)(coalesce >> timer_res);
3780
3781         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3782                                    p_cid->sb_igu_id, false);
3783         if (rc)
3784                 goto out;
3785
3786         address = BAR0_MAP_REG_USDM_RAM +
3787                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
3788
3789         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3790                               sizeof(struct ustorm_eth_queue_zone), timeset);
3791         if (rc)
3792                 goto out;
3793
3794 out:
3795         return rc;
3796 }
3797
3798 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
3799                          struct qed_ptt *p_ptt,
3800                          u16 coalesce, struct qed_queue_cid *p_cid)
3801 {
3802         struct xstorm_eth_queue_zone eth_qzone;
3803         u8 timeset, timer_res;
3804         u32 address;
3805         int rc;
3806
3807         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3808         if (coalesce <= 0x7F) {
3809                 timer_res = 0;
3810         } else if (coalesce <= 0xFF) {
3811                 timer_res = 1;
3812         } else if (coalesce <= 0x1FF) {
3813                 timer_res = 2;
3814         } else {
3815                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3816                 return -EINVAL;
3817         }
3818         timeset = (u8)(coalesce >> timer_res);
3819
3820         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3821                                    p_cid->sb_igu_id, true);
3822         if (rc)
3823                 goto out;
3824
3825         address = BAR0_MAP_REG_XSDM_RAM +
3826                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
3827
3828         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3829                               sizeof(struct xstorm_eth_queue_zone), timeset);
3830 out:
3831         return rc;
3832 }
3833
3834 /* Calculate final WFQ values for all vports and configure them.
3835  * After this configuration each vport will have
3836  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
3837  */
3838 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3839                                              struct qed_ptt *p_ptt,
3840                                              u32 min_pf_rate)
3841 {
3842         struct init_qm_vport_params *vport_params;
3843         int i;
3844
3845         vport_params = p_hwfn->qm_info.qm_vport_params;
3846
3847         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3848                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3849
3850                 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
3851                                                 min_pf_rate;
3852                 qed_init_vport_wfq(p_hwfn, p_ptt,
3853                                    vport_params[i].first_tx_pq_id,
3854                                    vport_params[i].vport_wfq);
3855         }
3856 }
3857
3858 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
3859                                        u32 min_pf_rate)
3860
3861 {
3862         int i;
3863
3864         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3865                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3866 }
3867
3868 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3869                                            struct qed_ptt *p_ptt,
3870                                            u32 min_pf_rate)
3871 {
3872         struct init_qm_vport_params *vport_params;
3873         int i;
3874
3875         vport_params = p_hwfn->qm_info.qm_vport_params;
3876
3877         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3878                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
3879                 qed_init_vport_wfq(p_hwfn, p_ptt,
3880                                    vport_params[i].first_tx_pq_id,
3881                                    vport_params[i].vport_wfq);
3882         }
3883 }
3884
3885 /* This function performs several validations for WFQ
3886  * configuration and required min rate for a given vport
3887  * 1. req_rate must be greater than one percent of min_pf_rate.
3888  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3889  *    rates to get less than one percent of min_pf_rate.
3890  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3891  */
3892 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
3893                               u16 vport_id, u32 req_rate, u32 min_pf_rate)
3894 {
3895         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3896         int non_requested_count = 0, req_count = 0, i, num_vports;
3897
3898         num_vports = p_hwfn->qm_info.num_vports;
3899
3900         /* Accounting for the vports which are configured for WFQ explicitly */
3901         for (i = 0; i < num_vports; i++) {
3902                 u32 tmp_speed;
3903
3904                 if ((i != vport_id) &&
3905                     p_hwfn->qm_info.wfq_data[i].configured) {
3906                         req_count++;
3907                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3908                         total_req_min_rate += tmp_speed;
3909                 }
3910         }
3911
3912         /* Include current vport data as well */
3913         req_count++;
3914         total_req_min_rate += req_rate;
3915         non_requested_count = num_vports - req_count;
3916
3917         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
3918                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3919                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3920                            vport_id, req_rate, min_pf_rate);
3921                 return -EINVAL;
3922         }
3923
3924         if (num_vports > QED_WFQ_UNIT) {
3925                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3926                            "Number of vports is greater than %d\n",
3927                            QED_WFQ_UNIT);
3928                 return -EINVAL;
3929         }
3930
3931         if (total_req_min_rate > min_pf_rate) {
3932                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3933                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3934                            total_req_min_rate, min_pf_rate);
3935                 return -EINVAL;
3936         }
3937
3938         total_left_rate = min_pf_rate - total_req_min_rate;
3939
3940         left_rate_per_vp = total_left_rate / non_requested_count;
3941         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
3942                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3943                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3944                            left_rate_per_vp, min_pf_rate);
3945                 return -EINVAL;
3946         }
3947
3948         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3949         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3950
3951         for (i = 0; i < num_vports; i++) {
3952                 if (p_hwfn->qm_info.wfq_data[i].configured)
3953                         continue;
3954
3955                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
3956         }
3957
3958         return 0;
3959 }
3960
3961 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
3962                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
3963 {
3964         struct qed_mcp_link_state *p_link;
3965         int rc = 0;
3966
3967         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
3968
3969         if (!p_link->min_pf_rate) {
3970                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
3971                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
3972                 return rc;
3973         }
3974
3975         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
3976
3977         if (!rc)
3978                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
3979                                                  p_link->min_pf_rate);
3980         else
3981                 DP_NOTICE(p_hwfn,
3982                           "Validation failed while configuring min rate\n");
3983
3984         return rc;
3985 }
3986
3987 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
3988                                                  struct qed_ptt *p_ptt,
3989                                                  u32 min_pf_rate)
3990 {
3991         bool use_wfq = false;
3992         int rc = 0;
3993         u16 i;
3994
3995         /* Validate all pre configured vports for wfq */
3996         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3997                 u32 rate;
3998
3999                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4000                         continue;
4001
4002                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4003                 use_wfq = true;
4004
4005                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4006                 if (rc) {
4007                         DP_NOTICE(p_hwfn,
4008                                   "WFQ validation failed while configuring min rate\n");
4009                         break;
4010                 }
4011         }
4012
4013         if (!rc && use_wfq)
4014                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4015         else
4016                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4017
4018         return rc;
4019 }
4020
4021 /* Main API for qed clients to configure vport min rate.
4022  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4023  * rate - Speed in Mbps needs to be assigned to a given vport.
4024  */
4025 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
4026 {
4027         int i, rc = -EINVAL;
4028
4029         /* Currently not supported; Might change in future */
4030         if (cdev->num_hwfns > 1) {
4031                 DP_NOTICE(cdev,
4032                           "WFQ configuration is not supported for this device\n");
4033                 return rc;
4034         }
4035
4036         for_each_hwfn(cdev, i) {
4037                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4038                 struct qed_ptt *p_ptt;
4039
4040                 p_ptt = qed_ptt_acquire(p_hwfn);
4041                 if (!p_ptt)
4042                         return -EBUSY;
4043
4044                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4045
4046                 if (rc) {
4047                         qed_ptt_release(p_hwfn, p_ptt);
4048                         return rc;
4049                 }
4050
4051                 qed_ptt_release(p_hwfn, p_ptt);
4052         }
4053
4054         return rc;
4055 }
4056
4057 /* API to configure WFQ from mcp link change */
4058 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
4059                                          struct qed_ptt *p_ptt, u32 min_pf_rate)
4060 {
4061         int i;
4062
4063         if (cdev->num_hwfns > 1) {
4064                 DP_VERBOSE(cdev,
4065                            NETIF_MSG_LINK,
4066                            "WFQ configuration is not supported for this device\n");
4067                 return;
4068         }
4069
4070         for_each_hwfn(cdev, i) {
4071                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4072
4073                 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
4074                                                       min_pf_rate);
4075         }
4076 }
4077
4078 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
4079                                      struct qed_ptt *p_ptt,
4080                                      struct qed_mcp_link_state *p_link,
4081                                      u8 max_bw)
4082 {
4083         int rc = 0;
4084
4085         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4086
4087         if (!p_link->line_speed && (max_bw != 100))
4088                 return rc;
4089
4090         p_link->speed = (p_link->line_speed * max_bw) / 100;
4091         p_hwfn->qm_info.pf_rl = p_link->speed;
4092
4093         /* Since the limiter also affects Tx-switched traffic, we don't want it
4094          * to limit such traffic in case there's no actual limit.
4095          * In that case, set limit to imaginary high boundary.
4096          */
4097         if (max_bw == 100)
4098                 p_hwfn->qm_info.pf_rl = 100000;
4099
4100         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4101                             p_hwfn->qm_info.pf_rl);
4102
4103         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4104                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4105                    p_link->speed);
4106
4107         return rc;
4108 }
4109
4110 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4111 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
4112 {
4113         int i, rc = -EINVAL;
4114
4115         if (max_bw < 1 || max_bw > 100) {
4116                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
4117                 return rc;
4118         }
4119
4120         for_each_hwfn(cdev, i) {
4121                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4122                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4123                 struct qed_mcp_link_state *p_link;
4124                 struct qed_ptt *p_ptt;
4125
4126                 p_link = &p_lead->mcp_info->link_output;
4127
4128                 p_ptt = qed_ptt_acquire(p_hwfn);
4129                 if (!p_ptt)
4130                         return -EBUSY;
4131
4132                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4133                                                       p_link, max_bw);
4134
4135                 qed_ptt_release(p_hwfn, p_ptt);
4136
4137                 if (rc)
4138                         break;
4139         }
4140
4141         return rc;
4142 }
4143
4144 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
4145                                      struct qed_ptt *p_ptt,
4146                                      struct qed_mcp_link_state *p_link,
4147                                      u8 min_bw)
4148 {
4149         int rc = 0;
4150
4151         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4152         p_hwfn->qm_info.pf_wfq = min_bw;
4153
4154         if (!p_link->line_speed)
4155                 return rc;
4156
4157         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4158
4159         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4160
4161         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4162                    "Configured MIN bandwidth to be %d Mb/sec\n",
4163                    p_link->min_pf_rate);
4164
4165         return rc;
4166 }
4167
4168 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4169 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
4170 {
4171         int i, rc = -EINVAL;
4172
4173         if (min_bw < 1 || min_bw > 100) {
4174                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
4175                 return rc;
4176         }
4177
4178         for_each_hwfn(cdev, i) {
4179                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4180                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4181                 struct qed_mcp_link_state *p_link;
4182                 struct qed_ptt *p_ptt;
4183
4184                 p_link = &p_lead->mcp_info->link_output;
4185
4186                 p_ptt = qed_ptt_acquire(p_hwfn);
4187                 if (!p_ptt)
4188                         return -EBUSY;
4189
4190                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4191                                                       p_link, min_bw);
4192                 if (rc) {
4193                         qed_ptt_release(p_hwfn, p_ptt);
4194                         return rc;
4195                 }
4196
4197                 if (p_link->min_pf_rate) {
4198                         u32 min_rate = p_link->min_pf_rate;
4199
4200                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
4201                                                                    p_ptt,
4202                                                                    min_rate);
4203                 }
4204
4205                 qed_ptt_release(p_hwfn, p_ptt);
4206         }
4207
4208         return rc;
4209 }
4210
4211 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4212 {
4213         struct qed_mcp_link_state *p_link;
4214
4215         p_link = &p_hwfn->mcp_info->link_output;
4216
4217         if (p_link->min_pf_rate)
4218                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4219                                                p_link->min_pf_rate);
4220
4221         memset(p_hwfn->qm_info.wfq_data, 0,
4222                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4223 }
4224
4225 int qed_device_num_engines(struct qed_dev *cdev)
4226 {
4227         return QED_IS_BB(cdev) ? 2 : 1;
4228 }
4229
4230 static int qed_device_num_ports(struct qed_dev *cdev)
4231 {
4232         /* in CMT always only one port */
4233         if (cdev->num_hwfns > 1)
4234                 return 1;
4235
4236         return cdev->num_ports_in_engine * qed_device_num_engines(cdev);
4237 }
4238
4239 int qed_device_get_port_id(struct qed_dev *cdev)
4240 {
4241         return (QED_LEADING_HWFN(cdev)->abs_pf_id) % qed_device_num_ports(cdev);
4242 }
4243
4244 void qed_set_fw_mac_addr(__le16 *fw_msb,
4245                          __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
4246 {
4247         ((u8 *)fw_msb)[0] = mac[1];
4248         ((u8 *)fw_msb)[1] = mac[0];
4249         ((u8 *)fw_mid)[0] = mac[3];
4250         ((u8 *)fw_mid)[1] = mac[2];
4251         ((u8 *)fw_lsb)[0] = mac[5];
4252         ((u8 *)fw_lsb)[1] = mac[4];
4253 }