drivers/net/ethernet/qlogic/qed/qed_cxt.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #include <linux/types.h>
  10 #include <linux/bitops.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/errno.h>
  13 #include <linux/kernel.h>
  14 #include <linux/list.h>
  15 #include <linux/log2.h>
  16 #include <linux/pci.h>
  17 #include <linux/slab.h>
  18 #include <linux/string.h>
  19 #include <linux/bitops.h>
  20 #include "qed.h"
  21 #include "qed_cxt.h"
  22 #include "qed_dev_api.h"
  23 #include "qed_hsi.h"
  24 #include "qed_hw.h"
  25 #include "qed_init_ops.h"
  26 #include "qed_reg_addr.h"
  27 #include "qed_sriov.h"
  28
  29 /* Max number of connection types in HW (DQ/CDU etc.) */
  30 #define MAX_CONN_TYPES          PROTOCOLID_COMMON
  31 #define NUM_TASK_TYPES          2
  32 #define NUM_TASK_PF_SEGMENTS    4
  33 #define NUM_TASK_VF_SEGMENTS    1
  34
  35 /* QM constants */
  36 #define QM_PQ_ELEMENT_SIZE      4 /* in bytes */
  37
  38 /* Doorbell-Queue constants */
  39 #define DQ_RANGE_SHIFT          4
  40 #define DQ_RANGE_ALIGN          BIT(DQ_RANGE_SHIFT)
  41
  42 /* Searcher constants */
  43 #define SRC_MIN_NUM_ELEMS 256
  44
  45 /* Timers constants */
  46 #define TM_SHIFT        7
  47 #define TM_ALIGN        BIT(TM_SHIFT)
  48 #define TM_ELEM_SIZE    4
  49
  50 /* For RoCE we configure to 64K to cover for RoCE max tasks 256K purpose. */
  51 #define ILT_DEFAULT_HW_P_SIZE   (IS_ENABLED(CONFIG_QED_RDMA) ? 4 : 3)
  52
  53 #define ILT_PAGE_IN_BYTES(hw_p_size)    (1U << ((hw_p_size) + 12))
  54 #define ILT_CFG_REG(cli, reg)   PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET
  55
  56 /* ILT entry structure */
  57 #define ILT_ENTRY_PHY_ADDR_MASK         (~0ULL >> 12)
  58 #define ILT_ENTRY_PHY_ADDR_SHIFT        0
  59 #define ILT_ENTRY_VALID_MASK            0x1ULL
  60 #define ILT_ENTRY_VALID_SHIFT           52
  61 #define ILT_ENTRY_IN_REGS               2
  62 #define ILT_REG_SIZE_IN_BYTES           4
  63
  64 /* connection context union */
  65 union conn_context {
  66         struct core_conn_context core_ctx;
  67         struct eth_conn_context eth_ctx;
  68         struct iscsi_conn_context iscsi_ctx;
  69         struct roce_conn_context roce_ctx;
  70 };
  71
  72 /* TYPE-0 task context - iSCSI */
  73 union type0_task_context {
  74         struct iscsi_task_context iscsi_ctx;
  75 };
  76
  77 /* TYPE-1 task context - ROCE */
  78 union type1_task_context {
  79         struct rdma_task_context roce_ctx;
  80 };
  81
  82 struct src_ent {
  83         u8 opaque[56];
  84         u64 next;
  85 };
  86
  87 #define CDUT_SEG_ALIGNMET 3     /* in 4k chunks */
  88 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
  89
  90 #define CONN_CXT_SIZE(p_hwfn) \
  91         ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
  92
  93 #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context))
  94
  95 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
  96         ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
  97
  98 /* Alignment is inherent to the type1_task_context structure */
  99 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
 100
 101 /* PF per protocl configuration object */
 102 #define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
 103 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
 104
 105 struct qed_tid_seg {
 106         u32 count;
 107         u8 type;
 108         bool has_fl_mem;
 109 };
 110
 111 struct qed_conn_type_cfg {
 112         u32 cid_count;
 113         u32 cid_start;
 114         u32 cids_per_vf;
 115         struct qed_tid_seg tid_seg[TASK_SEGMENTS];
 116 };
 117
 118 /* ILT Client configuration, Per connection type (protocol) resources. */
 119 #define ILT_CLI_PF_BLOCKS       (1 + NUM_TASK_PF_SEGMENTS * 2)
 120 #define ILT_CLI_VF_BLOCKS       (1 + NUM_TASK_VF_SEGMENTS * 2)
 121 #define CDUC_BLK                (0)
 122 #define SRQ_BLK                 (0)
 123 #define CDUT_SEG_BLK(n)         (1 + (u8)(n))
 124 #define CDUT_FL_SEG_BLK(n, X)   (1 + (n) + NUM_TASK_ ## X ## _SEGMENTS)
 125
 126 enum ilt_clients {
 127         ILT_CLI_CDUC,
 128         ILT_CLI_CDUT,
 129         ILT_CLI_QM,
 130         ILT_CLI_TM,
 131         ILT_CLI_SRC,
 132         ILT_CLI_TSDM,
 133         ILT_CLI_MAX
 134 };
 135
 136 struct ilt_cfg_pair {
 137         u32 reg;
 138         u32 val;
 139 };
 140
 141 struct qed_ilt_cli_blk {
 142         u32 total_size; /* 0 means not active */
 143         u32 real_size_in_page;
 144         u32 start_line;
 145         u32 dynamic_line_cnt;
 146 };
 147
 148 struct qed_ilt_client_cfg {
 149         bool active;
 150
 151         /* ILT boundaries */
 152         struct ilt_cfg_pair first;
 153         struct ilt_cfg_pair last;
 154         struct ilt_cfg_pair p_size;
 155
 156         /* ILT client blocks for PF */
 157         struct qed_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
 158         u32 pf_total_lines;
 159
 160         /* ILT client blocks for VFs */
 161         struct qed_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
 162         u32 vf_total_lines;
 163 };
 164
 165 /* Per Path -
 166  *      ILT shadow table
 167  *      Protocol acquired CID lists
 168  *      PF start line in ILT
 169  */
 170 struct qed_dma_mem {
 171         dma_addr_t p_phys;
 172         void *p_virt;
 173         size_t size;
 174 };
 175
 176 struct qed_cid_acquired_map {
 177         u32             start_cid;
 178         u32             max_count;
 179         unsigned long   *cid_map;
 180 };
 181
 182 struct qed_cxt_mngr {
 183         /* Per protocl configuration */
 184         struct qed_conn_type_cfg        conn_cfg[MAX_CONN_TYPES];
 185
 186         /* computed ILT structure */
 187         struct qed_ilt_client_cfg       clients[ILT_CLI_MAX];
 188
 189         /* Task type sizes */
 190         u32 task_type_size[NUM_TASK_TYPES];
 191
 192         /* total number of VFs for this hwfn -
 193          * ALL VFs are symmetric in terms of HW resources
 194          */
 195         u32                             vf_count;
 196
 197         /* total number of SRQ's for this hwfn */
 198         u32 srq_count;
 199
 200         /* Acquired CIDs */
 201         struct qed_cid_acquired_map     acquired[MAX_CONN_TYPES];
 202
 203         /* ILT  shadow table */
 204         struct qed_dma_mem              *ilt_shadow;
 205         u32                             pf_start_line;
 206
 207         /* Mutex for a dynamic ILT allocation */
 208         struct mutex mutex;
 209
 210         /* SRC T2 */
 211         struct qed_dma_mem *t2;
 212         u32 t2_num_pages;
 213         u64 first_free;
 214         u64 last_free;
 215 };
 216 static bool src_proto(enum protocol_type type)
 217 {
 218         return type == PROTOCOLID_ISCSI ||
 219                type == PROTOCOLID_ROCE;
 220 }
 221
 222 static bool tm_cid_proto(enum protocol_type type)
 223 {
 224         return type == PROTOCOLID_ISCSI ||
 225                type == PROTOCOLID_ROCE;
 226 }
 227
 228 /* counts the iids for the CDU/CDUC ILT client configuration */
 229 struct qed_cdu_iids {
 230         u32 pf_cids;
 231         u32 per_vf_cids;
 232 };
 233
 234 static void qed_cxt_cdu_iids(struct qed_cxt_mngr *p_mngr,
 235                              struct qed_cdu_iids *iids)
 236 {
 237         u32 type;
 238
 239         for (type = 0; type < MAX_CONN_TYPES; type++) {
 240                 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
 241                 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 242         }
 243 }
 244
 245 /* counts the iids for the Searcher block configuration */
 246 struct qed_src_iids {
 247         u32 pf_cids;
 248         u32 per_vf_cids;
 249 };
 250
 251 static void qed_cxt_src_iids(struct qed_cxt_mngr *p_mngr,
 252                              struct qed_src_iids *iids)
 253 {
 254         u32 i;
 255
 256         for (i = 0; i < MAX_CONN_TYPES; i++) {
 257                 if (!src_proto(i))
 258                         continue;
 259
 260                 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
 261                 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
 262         }
 263 }
 264
 265 /* counts the iids for the Timers block configuration */
 266 struct qed_tm_iids {
 267         u32 pf_cids;
 268         u32 pf_tids[NUM_TASK_PF_SEGMENTS];      /* per segment */
 269         u32 pf_tids_total;
 270         u32 per_vf_cids;
 271         u32 per_vf_tids;
 272 };
 273
 274 static void qed_cxt_tm_iids(struct qed_hwfn *p_hwfn,
 275                             struct qed_cxt_mngr *p_mngr,
 276                             struct qed_tm_iids *iids)
 277 {
 278         bool tm_vf_required = false;
 279         bool tm_required = false;
 280         int i, j;
 281
 282         /* Timers is a special case -> we don't count how many cids require
 283          * timers but what's the max cid that will be used by the timer block.
 284          * therefore we traverse in reverse order, and once we hit a protocol
 285          * that requires the timers memory, we'll sum all the protocols up
 286          * to that one.
 287          */
 288         for (i = MAX_CONN_TYPES - 1; i >= 0; i--) {
 289                 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
 290
 291                 if (tm_cid_proto(i) || tm_required) {
 292                         if (p_cfg->cid_count)
 293                                 tm_required = true;
 294
 295                         iids->pf_cids += p_cfg->cid_count;
 296                 }
 297
 298                 if (tm_cid_proto(i) || tm_vf_required) {
 299                         if (p_cfg->cids_per_vf)
 300                                 tm_vf_required = true;
 301
 302                         iids->per_vf_cids += p_cfg->cids_per_vf;
 303                 }
 304         }
 305
 306         iids->pf_cids = roundup(iids->pf_cids, TM_ALIGN);
 307         iids->per_vf_cids = roundup(iids->per_vf_cids, TM_ALIGN);
 308         iids->per_vf_tids = roundup(iids->per_vf_tids, TM_ALIGN);
 309
 310         for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
 311                 iids->pf_tids[j] = roundup(iids->pf_tids[j], TM_ALIGN);
 312                 iids->pf_tids_total += iids->pf_tids[j];
 313         }
 314 }
 315
 316 static void qed_cxt_qm_iids(struct qed_hwfn *p_hwfn,
 317                             struct qed_qm_iids *iids)
 318 {
 319         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 320         struct qed_tid_seg *segs;
 321         u32 vf_cids = 0, type, j;
 322         u32 vf_tids = 0;
 323
 324         for (type = 0; type < MAX_CONN_TYPES; type++) {
 325                 iids->cids += p_mngr->conn_cfg[type].cid_count;
 326                 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 327
 328                 segs = p_mngr->conn_cfg[type].tid_seg;
 329                 /* for each segment there is at most one
 330                  * protocol for which count is not 0.
 331                  */
 332                 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 333                         iids->tids += segs[j].count;
 334
 335                 /* The last array elelment is for the VFs. As for PF
 336                  * segments there can be only one protocol for
 337                  * which this value is not 0.
 338                  */
 339                 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 340         }
 341
 342         iids->vf_cids = vf_cids;
 343         iids->tids += vf_tids * p_mngr->vf_count;
 344
 345         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 346                    "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
 347                    iids->cids, iids->vf_cids, iids->tids, vf_tids);
 348 }
 349
 350 static struct qed_tid_seg *qed_cxt_tid_seg_info(struct qed_hwfn *p_hwfn,
 351                                                 u32 seg)
 352 {
 353         struct qed_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
 354         u32 i;
 355
 356         /* Find the protocol with tid count > 0 for this segment.
 357          * Note: there can only be one and this is already validated.
 358          */
 359         for (i = 0; i < MAX_CONN_TYPES; i++)
 360                 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
 361                         return &p_cfg->conn_cfg[i].tid_seg[seg];
 362         return NULL;
 363 }
 364
 365 static void qed_cxt_set_srq_count(struct qed_hwfn *p_hwfn, u32 num_srqs)
 366 {
 367         struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 368
 369         p_mgr->srq_count = num_srqs;
 370 }
 371
 372 static u32 qed_cxt_get_srq_count(struct qed_hwfn *p_hwfn)
 373 {
 374         struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 375
 376         return p_mgr->srq_count;
 377 }
 378
 379 /* set the iids count per protocol */
 380 static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn,
 381                                         enum protocol_type type,
 382                                         u32 cid_count, u32 vf_cid_cnt)
 383 {
 384         struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 385         struct qed_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
 386
 387         p_conn->cid_count = roundup(cid_count, DQ_RANGE_ALIGN);
 388         p_conn->cids_per_vf = roundup(vf_cid_cnt, DQ_RANGE_ALIGN);
 389
 390         if (type == PROTOCOLID_ROCE) {
 391                 u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val;
 392                 u32 cxt_size = CONN_CXT_SIZE(p_hwfn);
 393                 u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
 394                 u32 align = elems_per_page * DQ_RANGE_ALIGN;
 395
 396                 p_conn->cid_count = roundup(p_conn->cid_count, align);
 397         }
 398 }
 399
 400 u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn,
 401                                 enum protocol_type type, u32 *vf_cid)
 402 {
 403         if (vf_cid)
 404                 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
 405
 406         return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
 407 }
 408
 409 u32 qed_cxt_get_proto_cid_start(struct qed_hwfn *p_hwfn,
 410                                 enum protocol_type type)
 411 {
 412         return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
 413 }
 414
 415 u32 qed_cxt_get_proto_tid_count(struct qed_hwfn *p_hwfn,
 416                                 enum protocol_type type)
 417 {
 418         u32 cnt = 0;
 419         int i;
 420
 421         for (i = 0; i < TASK_SEGMENTS; i++)
 422                 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
 423
 424         return cnt;
 425 }
 426
 427 static void qed_cxt_set_proto_tid_count(struct qed_hwfn *p_hwfn,
 428                                         enum protocol_type proto,
 429                                         u8 seg,
 430                                         u8 seg_type, u32 count, bool has_fl)
 431 {
 432         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 433         struct qed_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
 434
 435         p_seg->count = count;
 436         p_seg->has_fl_mem = has_fl;
 437         p_seg->type = seg_type;
 438 }
 439
 440 static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg *p_cli,
 441                                  struct qed_ilt_cli_blk *p_blk,
 442                                  u32 start_line, u32 total_size, u32 elem_size)
 443 {
 444         u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 445
 446         /* verify thatits called only once for each block */
 447         if (p_blk->total_size)
 448                 return;
 449
 450         p_blk->total_size = total_size;
 451         p_blk->real_size_in_page = 0;
 452         if (elem_size)
 453                 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
 454         p_blk->start_line = start_line;
 455 }
 456
 457 static void qed_ilt_cli_adv_line(struct qed_hwfn *p_hwfn,
 458                                  struct qed_ilt_client_cfg *p_cli,
 459                                  struct qed_ilt_cli_blk *p_blk,
 460                                  u32 *p_line, enum ilt_clients client_id)
 461 {
 462         if (!p_blk->total_size)
 463                 return;
 464
 465         if (!p_cli->active)
 466                 p_cli->first.val = *p_line;
 467
 468         p_cli->active = true;
 469         *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
 470         p_cli->last.val = *p_line - 1;
 471
 472         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 473                    "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n",
 474                    client_id, p_cli->first.val,
 475                    p_cli->last.val, p_blk->total_size,
 476                    p_blk->real_size_in_page, p_blk->start_line);
 477 }
 478
 479 static u32 qed_ilt_get_dynamic_line_cnt(struct qed_hwfn *p_hwfn,
 480                                         enum ilt_clients ilt_client)
 481 {
 482         u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
 483         struct qed_ilt_client_cfg *p_cli;
 484         u32 lines_to_skip = 0;
 485         u32 cxts_per_p;
 486
 487         if (ilt_client == ILT_CLI_CDUC) {
 488                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
 489
 490                 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
 491                     (u32) CONN_CXT_SIZE(p_hwfn);
 492
 493                 lines_to_skip = cid_count / cxts_per_p;
 494         }
 495
 496         return lines_to_skip;
 497 }
 498
 499 int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn)
 500 {
 501         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 502         u32 curr_line, total, i, task_size, line;
 503         struct qed_ilt_client_cfg *p_cli;
 504         struct qed_ilt_cli_blk *p_blk;
 505         struct qed_cdu_iids cdu_iids;
 506         struct qed_src_iids src_iids;
 507         struct qed_qm_iids qm_iids;
 508         struct qed_tm_iids tm_iids;
 509         struct qed_tid_seg *p_seg;
 510
 511         memset(&qm_iids, 0, sizeof(qm_iids));
 512         memset(&cdu_iids, 0, sizeof(cdu_iids));
 513         memset(&src_iids, 0, sizeof(src_iids));
 514         memset(&tm_iids, 0, sizeof(tm_iids));
 515
 516         p_mngr->pf_start_line = RESC_START(p_hwfn, QED_ILT);
 517
 518         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 519                    "hwfn [%d] - Set context manager starting line to be 0x%08x\n",
 520                    p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
 521
 522         /* CDUC */
 523         p_cli = &p_mngr->clients[ILT_CLI_CDUC];
 524         curr_line = p_mngr->pf_start_line;
 525
 526         /* CDUC PF */
 527         p_cli->pf_total_lines = 0;
 528
 529         /* get the counters for the CDUC and QM clients  */
 530         qed_cxt_cdu_iids(p_mngr, &cdu_iids);
 531
 532         p_blk = &p_cli->pf_blks[CDUC_BLK];
 533
 534         total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
 535
 536         qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 537                              total, CONN_CXT_SIZE(p_hwfn));
 538
 539         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 540         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 541
 542         p_blk->dynamic_line_cnt = qed_ilt_get_dynamic_line_cnt(p_hwfn,
 543                                                                ILT_CLI_CDUC);
 544
 545         /* CDUC VF */
 546         p_blk = &p_cli->vf_blks[CDUC_BLK];
 547         total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
 548
 549         qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 550                              total, CONN_CXT_SIZE(p_hwfn));
 551
 552         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 553         p_cli->vf_total_lines = curr_line - p_blk->start_line;
 554
 555         for (i = 1; i < p_mngr->vf_count; i++)
 556                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 557                                      ILT_CLI_CDUC);
 558
 559         /* CDUT PF */
 560         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
 561         p_cli->first.val = curr_line;
 562
 563         /* first the 'working' task memory */
 564         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 565                 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
 566                 if (!p_seg || p_seg->count == 0)
 567                         continue;
 568
 569                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
 570                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 571                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
 572                                      p_mngr->task_type_size[p_seg->type]);
 573
 574                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 575                                      ILT_CLI_CDUT);
 576         }
 577
 578         /* next the 'init' task memory (forced load memory) */
 579         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 580                 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
 581                 if (!p_seg || p_seg->count == 0)
 582                         continue;
 583
 584                 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
 585
 586                 if (!p_seg->has_fl_mem) {
 587                         /* The segment is active (total size pf 'working'
 588                          * memory is > 0) but has no FL (forced-load, Init)
 589                          * memory. Thus:
 590                          *
 591                          * 1.   The total-size in the corrsponding FL block of
 592                          *      the ILT client is set to 0 - No ILT line are
 593                          *      provisioned and no ILT memory allocated.
 594                          *
 595                          * 2.   The start-line of said block is set to the
 596                          *      start line of the matching working memory
 597                          *      block in the ILT client. This is later used to
 598                          *      configure the CDU segment offset registers and
 599                          *      results in an FL command for TIDs of this
 600                          *      segement behaves as regular load commands
 601                          *      (loading TIDs from the working memory).
 602                          */
 603                         line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
 604
 605                         qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 606                         continue;
 607                 }
 608                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 609
 610                 qed_ilt_cli_blk_fill(p_cli, p_blk,
 611                                      curr_line, total,
 612                                      p_mngr->task_type_size[p_seg->type]);
 613
 614                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 615                                      ILT_CLI_CDUT);
 616         }
 617         p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
 618
 619         /* CDUT VF */
 620         p_seg = qed_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
 621         if (p_seg && p_seg->count) {
 622                 /* Stricly speaking we need to iterate over all VF
 623                  * task segment types, but a VF has only 1 segment
 624                  */
 625
 626                 /* 'working' memory */
 627                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 628
 629                 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 630                 qed_ilt_cli_blk_fill(p_cli, p_blk,
 631                                      curr_line, total,
 632                                      p_mngr->task_type_size[p_seg->type]);
 633
 634                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 635                                      ILT_CLI_CDUT);
 636
 637                 /* 'init' memory */
 638                 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 639                 if (!p_seg->has_fl_mem) {
 640                         /* see comment above */
 641                         line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
 642                         qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 643                 } else {
 644                         task_size = p_mngr->task_type_size[p_seg->type];
 645                         qed_ilt_cli_blk_fill(p_cli, p_blk,
 646                                              curr_line, total, task_size);
 647                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 648                                              ILT_CLI_CDUT);
 649                 }
 650                 p_cli->vf_total_lines = curr_line -
 651                     p_cli->vf_blks[0].start_line;
 652
 653                 /* Now for the rest of the VFs */
 654                 for (i = 1; i < p_mngr->vf_count; i++) {
 655                         p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 656                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 657                                              ILT_CLI_CDUT);
 658
 659                         p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 660                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 661                                              ILT_CLI_CDUT);
 662                 }
 663         }
 664
 665         /* QM */
 666         p_cli = &p_mngr->clients[ILT_CLI_QM];
 667         p_blk = &p_cli->pf_blks[0];
 668
 669         qed_cxt_qm_iids(p_hwfn, &qm_iids);
 670         total = qed_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
 671                                    qm_iids.vf_cids, qm_iids.tids,
 672                                    p_hwfn->qm_info.num_pqs,
 673                                    p_hwfn->qm_info.num_vf_pqs);
 674
 675         DP_VERBOSE(p_hwfn,
 676                    QED_MSG_ILT,
 677                    "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n",
 678                    qm_iids.cids,
 679                    qm_iids.vf_cids,
 680                    qm_iids.tids,
 681                    p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
 682
 683         qed_ilt_cli_blk_fill(p_cli, p_blk,
 684                              curr_line, total * 0x1000,
 685                              QM_PQ_ELEMENT_SIZE);
 686
 687         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
 688         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 689
 690         /* SRC */
 691         p_cli = &p_mngr->clients[ILT_CLI_SRC];
 692         qed_cxt_src_iids(p_mngr, &src_iids);
 693
 694         /* Both the PF and VFs searcher connections are stored in the per PF
 695          * database. Thus sum the PF searcher cids and all the VFs searcher
 696          * cids.
 697          */
 698         total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 699         if (total) {
 700                 u32 local_max = max_t(u32, total,
 701                                       SRC_MIN_NUM_ELEMS);
 702
 703                 total = roundup_pow_of_two(local_max);
 704
 705                 p_blk = &p_cli->pf_blks[0];
 706                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 707                                      total * sizeof(struct src_ent),
 708                                      sizeof(struct src_ent));
 709
 710                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 711                                      ILT_CLI_SRC);
 712                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 713         }
 714
 715         /* TM PF */
 716         p_cli = &p_mngr->clients[ILT_CLI_TM];
 717         qed_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids);
 718         total = tm_iids.pf_cids + tm_iids.pf_tids_total;
 719         if (total) {
 720                 p_blk = &p_cli->pf_blks[0];
 721                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 722                                      total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 723
 724                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 725                                      ILT_CLI_TM);
 726                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 727         }
 728
 729         /* TM VF */
 730         total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
 731         if (total) {
 732                 p_blk = &p_cli->vf_blks[0];
 733                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 734                                      total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 735
 736                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 737                                      ILT_CLI_TM);
 738                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 739
 740                 for (i = 1; i < p_mngr->vf_count; i++)
 741                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 742                                              ILT_CLI_TM);
 743         }
 744
 745         /* TSDM (SRQ CONTEXT) */
 746         total = qed_cxt_get_srq_count(p_hwfn);
 747
 748         if (total) {
 749                 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
 750                 p_blk = &p_cli->pf_blks[SRQ_BLK];
 751                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 752                                      total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
 753
 754                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 755                                      ILT_CLI_TSDM);
 756                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 757         }
 758
 759         if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
 760             RESC_NUM(p_hwfn, QED_ILT)) {
 761                 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
 762                        curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
 763                 return -EINVAL;
 764         }
 765
 766         return 0;
 767 }
 768
 769 static void qed_cxt_src_t2_free(struct qed_hwfn *p_hwfn)
 770 {
 771         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 772         u32 i;
 773
 774         if (!p_mngr->t2)
 775                 return;
 776
 777         for (i = 0; i < p_mngr->t2_num_pages; i++)
 778                 if (p_mngr->t2[i].p_virt)
 779                         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
 780                                           p_mngr->t2[i].size,
 781                                           p_mngr->t2[i].p_virt,
 782                                           p_mngr->t2[i].p_phys);
 783
 784         kfree(p_mngr->t2);
 785         p_mngr->t2 = NULL;
 786 }
 787
 788 static int qed_cxt_src_t2_alloc(struct qed_hwfn *p_hwfn)
 789 {
 790         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 791         u32 conn_num, total_size, ent_per_page, psz, i;
 792         struct qed_ilt_client_cfg *p_src;
 793         struct qed_src_iids src_iids;
 794         struct qed_dma_mem *p_t2;
 795         int rc;
 796
 797         memset(&src_iids, 0, sizeof(src_iids));
 798
 799         /* if the SRC ILT client is inactive - there are no connection
 800          * requiring the searcer, leave.
 801          */
 802         p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
 803         if (!p_src->active)
 804                 return 0;
 805
 806         qed_cxt_src_iids(p_mngr, &src_iids);
 807         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 808         total_size = conn_num * sizeof(struct src_ent);
 809
 810         /* use the same page size as the SRC ILT client */
 811         psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
 812         p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
 813
 814         /* allocate t2 */
 815         p_mngr->t2 = kcalloc(p_mngr->t2_num_pages, sizeof(struct qed_dma_mem),
 816                              GFP_KERNEL);
 817         if (!p_mngr->t2) {
 818                 rc = -ENOMEM;
 819                 goto t2_fail;
 820         }
 821
 822         /* allocate t2 pages */
 823         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 824                 u32 size = min_t(u32, total_size, psz);
 825                 void **p_virt = &p_mngr->t2[i].p_virt;
 826
 827                 *p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 828                                              size,
 829                                              &p_mngr->t2[i].p_phys, GFP_KERNEL);
 830                 if (!p_mngr->t2[i].p_virt) {
 831                         rc = -ENOMEM;
 832                         goto t2_fail;
 833                 }
 834                 memset(*p_virt, 0, size);
 835                 p_mngr->t2[i].size = size;
 836                 total_size -= size;
 837         }
 838
 839         /* Set the t2 pointers */
 840
 841         /* entries per page - must be a power of two */
 842         ent_per_page = psz / sizeof(struct src_ent);
 843
 844         p_mngr->first_free = (u64) p_mngr->t2[0].p_phys;
 845
 846         p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
 847         p_mngr->last_free = (u64) p_t2->p_phys +
 848             ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
 849
 850         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 851                 u32 ent_num = min_t(u32,
 852                                     ent_per_page,
 853                                     conn_num);
 854                 struct src_ent *entries = p_mngr->t2[i].p_virt;
 855                 u64 p_ent_phys = (u64) p_mngr->t2[i].p_phys, val;
 856                 u32 j;
 857
 858                 for (j = 0; j < ent_num - 1; j++) {
 859                         val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
 860                         entries[j].next = cpu_to_be64(val);
 861                 }
 862
 863                 if (i < p_mngr->t2_num_pages - 1)
 864                         val = (u64) p_mngr->t2[i + 1].p_phys;
 865                 else
 866                         val = 0;
 867                 entries[j].next = cpu_to_be64(val);
 868
 869                 conn_num -= ent_num;
 870         }
 871
 872         return 0;
 873
 874 t2_fail:
 875         qed_cxt_src_t2_free(p_hwfn);
 876         return rc;
 877 }
 878
 879 #define for_each_ilt_valid_client(pos, clients) \
 880         for (pos = 0; pos < ILT_CLI_MAX; pos++) \
 881                 if (!clients[pos].active) {     \
 882                         continue;               \
 883                 } else                          \
 884
 885 /* Total number of ILT lines used by this PF */
 886 static u32 qed_cxt_ilt_shadow_size(struct qed_ilt_client_cfg *ilt_clients)
 887 {
 888         u32 size = 0;
 889         u32 i;
 890
 891         for_each_ilt_valid_client(i, ilt_clients)
 892             size += (ilt_clients[i].last.val - ilt_clients[i].first.val + 1);
 893
 894         return size;
 895 }
 896
 897 static void qed_ilt_shadow_free(struct qed_hwfn *p_hwfn)
 898 {
 899         struct qed_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
 900         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 901         u32 ilt_size, i;
 902
 903         ilt_size = qed_cxt_ilt_shadow_size(p_cli);
 904
 905         for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
 906                 struct qed_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
 907
 908                 if (p_dma->p_virt)
 909                         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
 910                                           p_dma->size, p_dma->p_virt,
 911                                           p_dma->p_phys);
 912                 p_dma->p_virt = NULL;
 913         }
 914         kfree(p_mngr->ilt_shadow);
 915 }
 916
 917 static int qed_ilt_blk_alloc(struct qed_hwfn *p_hwfn,
 918                              struct qed_ilt_cli_blk *p_blk,
 919                              enum ilt_clients ilt_client,
 920                              u32 start_line_offset)
 921 {
 922         struct qed_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
 923         u32 lines, line, sz_left, lines_to_skip = 0;
 924
 925         /* Special handling for RoCE that supports dynamic allocation */
 926         if ((p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) &&
 927             ((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM))
 928                 return 0;
 929
 930         lines_to_skip = p_blk->dynamic_line_cnt;
 931
 932         if (!p_blk->total_size)
 933                 return 0;
 934
 935         sz_left = p_blk->total_size;
 936         lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
 937         line = p_blk->start_line + start_line_offset -
 938             p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
 939
 940         for (; lines; lines--) {
 941                 dma_addr_t p_phys;
 942                 void *p_virt;
 943                 u32 size;
 944
 945                 size = min_t(u32, sz_left, p_blk->real_size_in_page);
 946                 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 947                                             size, &p_phys, GFP_KERNEL);
 948                 if (!p_virt)
 949                         return -ENOMEM;
 950                 memset(p_virt, 0, size);
 951
 952                 ilt_shadow[line].p_phys = p_phys;
 953                 ilt_shadow[line].p_virt = p_virt;
 954                 ilt_shadow[line].size = size;
 955
 956                 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 957                            "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n",
 958                             line, (u64)p_phys, p_virt, size);
 959
 960                 sz_left -= size;
 961                 line++;
 962         }
 963
 964         return 0;
 965 }
 966
 967 static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn)
 968 {
 969         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 970         struct qed_ilt_client_cfg *clients = p_mngr->clients;
 971         struct qed_ilt_cli_blk *p_blk;
 972         u32 size, i, j, k;
 973         int rc;
 974
 975         size = qed_cxt_ilt_shadow_size(clients);
 976         p_mngr->ilt_shadow = kcalloc(size, sizeof(struct qed_dma_mem),
 977                                      GFP_KERNEL);
 978         if (!p_mngr->ilt_shadow) {
 979                 rc = -ENOMEM;
 980                 goto ilt_shadow_fail;
 981         }
 982
 983         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 984                    "Allocated 0x%x bytes for ilt shadow\n",
 985                    (u32)(size * sizeof(struct qed_dma_mem)));
 986
 987         for_each_ilt_valid_client(i, clients) {
 988                 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
 989                         p_blk = &clients[i].pf_blks[j];
 990                         rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
 991                         if (rc)
 992                                 goto ilt_shadow_fail;
 993                 }
 994                 for (k = 0; k < p_mngr->vf_count; k++) {
 995                         for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
 996                                 u32 lines = clients[i].vf_total_lines * k;
 997
 998                                 p_blk = &clients[i].vf_blks[j];
 999                                 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, lines);
1000                                 if (rc)
1001                                         goto ilt_shadow_fail;
1002                         }
1003                 }
1004         }
1005
1006         return 0;
1007
1008 ilt_shadow_fail:
1009         qed_ilt_shadow_free(p_hwfn);
1010         return rc;
1011 }
1012
1013 static void qed_cid_map_free(struct qed_hwfn *p_hwfn)
1014 {
1015         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1016         u32 type;
1017
1018         for (type = 0; type < MAX_CONN_TYPES; type++) {
1019                 kfree(p_mngr->acquired[type].cid_map);
1020                 p_mngr->acquired[type].max_count = 0;
1021                 p_mngr->acquired[type].start_cid = 0;
1022         }
1023 }
1024
1025 static int qed_cid_map_alloc(struct qed_hwfn *p_hwfn)
1026 {
1027         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1028         u32 start_cid = 0;
1029         u32 type;
1030
1031         for (type = 0; type < MAX_CONN_TYPES; type++) {
1032                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1033                 u32 size;
1034
1035                 if (cid_cnt == 0)
1036                         continue;
1037
1038                 size = DIV_ROUND_UP(cid_cnt,
1039                                     sizeof(unsigned long) * BITS_PER_BYTE) *
1040                        sizeof(unsigned long);
1041                 p_mngr->acquired[type].cid_map = kzalloc(size, GFP_KERNEL);
1042                 if (!p_mngr->acquired[type].cid_map)
1043                         goto cid_map_fail;
1044
1045                 p_mngr->acquired[type].max_count = cid_cnt;
1046                 p_mngr->acquired[type].start_cid = start_cid;
1047
1048                 p_hwfn->p_cxt_mngr->conn_cfg[type].cid_start = start_cid;
1049
1050                 DP_VERBOSE(p_hwfn, QED_MSG_CXT,
1051                            "Type %08x start: %08x count %08x\n",
1052                            type, p_mngr->acquired[type].start_cid,
1053                            p_mngr->acquired[type].max_count);
1054                 start_cid += cid_cnt;
1055         }
1056
1057         return 0;
1058
1059 cid_map_fail:
1060         qed_cid_map_free(p_hwfn);
1061         return -ENOMEM;
1062 }
1063
1064 int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn)
1065 {
1066         struct qed_ilt_client_cfg *clients;
1067         struct qed_cxt_mngr *p_mngr;
1068         u32 i;
1069
1070         p_mngr = kzalloc(sizeof(*p_mngr), GFP_KERNEL);
1071         if (!p_mngr)
1072                 return -ENOMEM;
1073
1074         /* Initialize ILT client registers */
1075         clients = p_mngr->clients;
1076         clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1077         clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
1078         clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1079
1080         clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
1081         clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
1082         clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
1083
1084         clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
1085         clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
1086         clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
1087
1088         clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
1089         clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
1090         clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1091
1092         clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1093         clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
1094         clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1095
1096         clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1097         clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
1098         clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1099         /* default ILT page size for all clients is 32K */
1100         for (i = 0; i < ILT_CLI_MAX; i++)
1101                 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1102
1103         /* Initialize task sizes */
1104         p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn);
1105         p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn);
1106
1107         if (p_hwfn->cdev->p_iov_info)
1108                 p_mngr->vf_count = p_hwfn->cdev->p_iov_info->total_vfs;
1109         /* Initialize the dynamic ILT allocation mutex */
1110         mutex_init(&p_mngr->mutex);
1111
1112         /* Set the cxt mangr pointer priori to further allocations */
1113         p_hwfn->p_cxt_mngr = p_mngr;
1114
1115         return 0;
1116 }
1117
1118 int qed_cxt_tables_alloc(struct qed_hwfn *p_hwfn)
1119 {
1120         int rc;
1121
1122         /* Allocate the ILT shadow table */
1123         rc = qed_ilt_shadow_alloc(p_hwfn);
1124         if (rc)
1125                 goto tables_alloc_fail;
1126
1127         /* Allocate the T2  table */
1128         rc = qed_cxt_src_t2_alloc(p_hwfn);
1129         if (rc)
1130                 goto tables_alloc_fail;
1131
1132         /* Allocate and initialize the acquired cids bitmaps */
1133         rc = qed_cid_map_alloc(p_hwfn);
1134         if (rc)
1135                 goto tables_alloc_fail;
1136
1137         return 0;
1138
1139 tables_alloc_fail:
1140         qed_cxt_mngr_free(p_hwfn);
1141         return rc;
1142 }
1143
1144 void qed_cxt_mngr_free(struct qed_hwfn *p_hwfn)
1145 {
1146         if (!p_hwfn->p_cxt_mngr)
1147                 return;
1148
1149         qed_cid_map_free(p_hwfn);
1150         qed_cxt_src_t2_free(p_hwfn);
1151         qed_ilt_shadow_free(p_hwfn);
1152         kfree(p_hwfn->p_cxt_mngr);
1153
1154         p_hwfn->p_cxt_mngr = NULL;
1155 }
1156
1157 void qed_cxt_mngr_setup(struct qed_hwfn *p_hwfn)
1158 {
1159         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1160         int type;
1161
1162         /* Reset acquired cids */
1163         for (type = 0; type < MAX_CONN_TYPES; type++) {
1164                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1165
1166                 if (cid_cnt == 0)
1167                         continue;
1168
1169                 memset(p_mngr->acquired[type].cid_map, 0,
1170                        DIV_ROUND_UP(cid_cnt,
1171                                     sizeof(unsigned long) * BITS_PER_BYTE) *
1172                        sizeof(unsigned long));
1173         }
1174 }
1175
1176 /* CDU Common */
1177 #define CDUC_CXT_SIZE_SHIFT \
1178         CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1179
1180 #define CDUC_CXT_SIZE_MASK \
1181         (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1182
1183 #define CDUC_BLOCK_WASTE_SHIFT \
1184         CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1185
1186 #define CDUC_BLOCK_WASTE_MASK \
1187         (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1188
1189 #define CDUC_NCIB_SHIFT \
1190         CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1191
1192 #define CDUC_NCIB_MASK \
1193         (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1194
1195 #define CDUT_TYPE0_CXT_SIZE_SHIFT \
1196         CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1197
1198 #define CDUT_TYPE0_CXT_SIZE_MASK                \
1199         (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1200          CDUT_TYPE0_CXT_SIZE_SHIFT)
1201
1202 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1203         CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1204
1205 #define CDUT_TYPE0_BLOCK_WASTE_MASK                    \
1206         (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1207          CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1208
1209 #define CDUT_TYPE0_NCIB_SHIFT \
1210         CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1211
1212 #define CDUT_TYPE0_NCIB_MASK                             \
1213         (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1214          CDUT_TYPE0_NCIB_SHIFT)
1215
1216 #define CDUT_TYPE1_CXT_SIZE_SHIFT \
1217         CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1218
1219 #define CDUT_TYPE1_CXT_SIZE_MASK                \
1220         (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1221          CDUT_TYPE1_CXT_SIZE_SHIFT)
1222
1223 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1224         CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1225
1226 #define CDUT_TYPE1_BLOCK_WASTE_MASK                    \
1227         (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1228          CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1229
1230 #define CDUT_TYPE1_NCIB_SHIFT \
1231         CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1232
1233 #define CDUT_TYPE1_NCIB_MASK                             \
1234         (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1235          CDUT_TYPE1_NCIB_SHIFT)
1236
1237 static void qed_cdu_init_common(struct qed_hwfn *p_hwfn)
1238 {
1239         u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1240
1241         /* CDUC - connection configuration */
1242         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1243         cxt_size = CONN_CXT_SIZE(p_hwfn);
1244         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1245         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1246
1247         SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1248         SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1249         SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1250         STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1251
1252         /* CDUT - type-0 tasks configuration */
1253         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1254         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1255         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1256         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1257
1258         /* cxt size and block-waste are multipes of 8 */
1259         cdu_params = 0;
1260         SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1261         SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1262         SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1263         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1264
1265         /* CDUT - type-1 tasks configuration */
1266         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1267         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1268         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1269
1270         /* cxt size and block-waste are multipes of 8 */
1271         cdu_params = 0;
1272         SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1273         SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1274         SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1275         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1276 }
1277
1278 /* CDU PF */
1279 #define CDU_SEG_REG_TYPE_SHIFT          CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1280 #define CDU_SEG_REG_TYPE_MASK           0x1
1281 #define CDU_SEG_REG_OFFSET_SHIFT        0
1282 #define CDU_SEG_REG_OFFSET_MASK         CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1283
1284 static void qed_cdu_init_pf(struct qed_hwfn *p_hwfn)
1285 {
1286         struct qed_ilt_client_cfg *p_cli;
1287         struct qed_tid_seg *p_seg;
1288         u32 cdu_seg_params, offset;
1289         int i;
1290
1291         static const u32 rt_type_offset_arr[] = {
1292                 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1293                 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1294                 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1295                 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1296         };
1297
1298         static const u32 rt_type_offset_fl_arr[] = {
1299                 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1300                 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1301                 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1302                 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1303         };
1304
1305         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1306
1307         /* There are initializations only for CDUT during pf Phase */
1308         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1309                 /* Segment 0 */
1310                 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
1311                 if (!p_seg)
1312                         continue;
1313
1314                 /* Note: start_line is already adjusted for the CDU
1315                  * segment register granularity, so we just need to
1316                  * divide. Adjustment is implicit as we assume ILT
1317                  * Page size is larger than 32K!
1318                  */
1319                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1320                           (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1321                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1322
1323                 cdu_seg_params = 0;
1324                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1325                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1326                 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1327
1328                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1329                           (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1330                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1331
1332                 cdu_seg_params = 0;
1333                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1334                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1335                 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1336         }
1337 }
1338
1339 void qed_qm_init_pf(struct qed_hwfn *p_hwfn)
1340 {
1341         struct qed_qm_pf_rt_init_params params;
1342         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1343         struct qed_qm_iids iids;
1344
1345         memset(&iids, 0, sizeof(iids));
1346         qed_cxt_qm_iids(p_hwfn, &iids);
1347
1348         memset(&params, 0, sizeof(params));
1349         params.port_id = p_hwfn->port_id;
1350         params.pf_id = p_hwfn->rel_pf_id;
1351         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1352         params.is_first_pf = p_hwfn->first_on_engine;
1353         params.num_pf_cids = iids.cids;
1354         params.num_vf_cids = iids.vf_cids;
1355         params.start_pq = qm_info->start_pq;
1356         params.num_pf_pqs = qm_info->num_pqs - qm_info->num_vf_pqs;
1357         params.num_vf_pqs = qm_info->num_vf_pqs;
1358         params.start_vport = qm_info->start_vport;
1359         params.num_vports = qm_info->num_vports;
1360         params.pf_wfq = qm_info->pf_wfq;
1361         params.pf_rl = qm_info->pf_rl;
1362         params.pq_params = qm_info->qm_pq_params;
1363         params.vport_params = qm_info->qm_vport_params;
1364
1365         qed_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, &params);
1366 }
1367
1368 /* CM PF */
1369 static int qed_cm_init_pf(struct qed_hwfn *p_hwfn)
1370 {
1371         union qed_qm_pq_params pq_params;
1372         u16 pq;
1373
1374         /* XCM pure-LB queue */
1375         memset(&pq_params, 0, sizeof(pq_params));
1376         pq_params.core.tc = LB_TC;
1377         pq = qed_get_qm_pq(p_hwfn, PROTOCOLID_CORE, &pq_params);
1378         STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, pq);
1379
1380         return 0;
1381 }
1382
1383 /* DQ PF */
1384 static void qed_dq_init_pf(struct qed_hwfn *p_hwfn)
1385 {
1386         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1387         u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1388
1389         dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1390         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1391
1392         dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1393         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1394
1395         dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1396         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1397
1398         dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1399         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1400
1401         dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1402         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1403
1404         dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1405         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1406
1407         dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1408         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1409
1410         dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1411         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1412
1413         dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1414         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1415
1416         dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1417         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1418
1419         dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1420         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1421
1422         dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1423         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1424
1425         /* Connection types 6 & 7 are not in use, yet they must be configured
1426          * as the highest possible connection. Not configuring them means the
1427          * defaults will be  used, and with a large number of cids a bug may
1428          * occur, if the defaults will be smaller than dq_pf_max_cid /
1429          * dq_vf_max_cid.
1430          */
1431         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1432         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1433
1434         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1435         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1436 }
1437
1438 static void qed_ilt_bounds_init(struct qed_hwfn *p_hwfn)
1439 {
1440         struct qed_ilt_client_cfg *ilt_clients;
1441         int i;
1442
1443         ilt_clients = p_hwfn->p_cxt_mngr->clients;
1444         for_each_ilt_valid_client(i, ilt_clients) {
1445                 STORE_RT_REG(p_hwfn,
1446                              ilt_clients[i].first.reg,
1447                              ilt_clients[i].first.val);
1448                 STORE_RT_REG(p_hwfn,
1449                              ilt_clients[i].last.reg, ilt_clients[i].last.val);
1450                 STORE_RT_REG(p_hwfn,
1451                              ilt_clients[i].p_size.reg,
1452                              ilt_clients[i].p_size.val);
1453         }
1454 }
1455
1456 static void qed_ilt_vf_bounds_init(struct qed_hwfn *p_hwfn)
1457 {
1458         struct qed_ilt_client_cfg *p_cli;
1459         u32 blk_factor;
1460
1461         /* For simplicty  we set the 'block' to be an ILT page */
1462         if (p_hwfn->cdev->p_iov_info) {
1463                 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
1464
1465                 STORE_RT_REG(p_hwfn,
1466                              PSWRQ2_REG_VF_BASE_RT_OFFSET,
1467                              p_iov->first_vf_in_pf);
1468                 STORE_RT_REG(p_hwfn,
1469                              PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1470                              p_iov->first_vf_in_pf + p_iov->total_vfs);
1471         }
1472
1473         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1474         blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1475         if (p_cli->active) {
1476                 STORE_RT_REG(p_hwfn,
1477                              PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1478                              blk_factor);
1479                 STORE_RT_REG(p_hwfn,
1480                              PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1481                              p_cli->pf_total_lines);
1482                 STORE_RT_REG(p_hwfn,
1483                              PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1484                              p_cli->vf_total_lines);
1485         }
1486
1487         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1488         blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1489         if (p_cli->active) {
1490                 STORE_RT_REG(p_hwfn,
1491                              PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1492                              blk_factor);
1493                 STORE_RT_REG(p_hwfn,
1494                              PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1495                              p_cli->pf_total_lines);
1496                 STORE_RT_REG(p_hwfn,
1497                              PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1498                              p_cli->vf_total_lines);
1499         }
1500
1501         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1502         blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1503         if (p_cli->active) {
1504                 STORE_RT_REG(p_hwfn,
1505                              PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1506                 STORE_RT_REG(p_hwfn,
1507                              PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1508                              p_cli->pf_total_lines);
1509                 STORE_RT_REG(p_hwfn,
1510                              PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1511                              p_cli->vf_total_lines);
1512         }
1513 }
1514
1515 /* ILT (PSWRQ2) PF */
1516 static void qed_ilt_init_pf(struct qed_hwfn *p_hwfn)
1517 {
1518         struct qed_ilt_client_cfg *clients;
1519         struct qed_cxt_mngr *p_mngr;
1520         struct qed_dma_mem *p_shdw;
1521         u32 line, rt_offst, i;
1522
1523         qed_ilt_bounds_init(p_hwfn);
1524         qed_ilt_vf_bounds_init(p_hwfn);
1525
1526         p_mngr = p_hwfn->p_cxt_mngr;
1527         p_shdw = p_mngr->ilt_shadow;
1528         clients = p_hwfn->p_cxt_mngr->clients;
1529
1530         for_each_ilt_valid_client(i, clients) {
1531                 /** Client's 1st val and RT array are absolute, ILT shadows'
1532                  *  lines are relative.
1533                  */
1534                 line = clients[i].first.val - p_mngr->pf_start_line;
1535                 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1536                            clients[i].first.val * ILT_ENTRY_IN_REGS;
1537
1538                 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1539                      line++, rt_offst += ILT_ENTRY_IN_REGS) {
1540                         u64 ilt_hw_entry = 0;
1541
1542                         /** p_virt could be NULL incase of dynamic
1543                          *  allocation
1544                          */
1545                         if (p_shdw[line].p_virt) {
1546                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1547                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1548                                           (p_shdw[line].p_phys >> 12));
1549
1550                                 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
1551                                            "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n",
1552                                            rt_offst, line, i,
1553                                            (u64)(p_shdw[line].p_phys >> 12));
1554                         }
1555
1556                         STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1557                 }
1558         }
1559 }
1560
1561 /* SRC (Searcher) PF */
1562 static void qed_src_init_pf(struct qed_hwfn *p_hwfn)
1563 {
1564         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1565         u32 rounded_conn_num, conn_num, conn_max;
1566         struct qed_src_iids src_iids;
1567
1568         memset(&src_iids, 0, sizeof(src_iids));
1569         qed_cxt_src_iids(p_mngr, &src_iids);
1570         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1571         if (!conn_num)
1572                 return;
1573
1574         conn_max = max_t(u32, conn_num, SRC_MIN_NUM_ELEMS);
1575         rounded_conn_num = roundup_pow_of_two(conn_max);
1576
1577         STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1578         STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1579                      ilog2(rounded_conn_num));
1580
1581         STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1582                          p_hwfn->p_cxt_mngr->first_free);
1583         STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1584                          p_hwfn->p_cxt_mngr->last_free);
1585 }
1586
1587 /* Timers PF */
1588 #define TM_CFG_NUM_IDS_SHIFT            0
1589 #define TM_CFG_NUM_IDS_MASK             0xFFFFULL
1590 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT    16
1591 #define TM_CFG_PRE_SCAN_OFFSET_MASK     0x1FFULL
1592 #define TM_CFG_PARENT_PF_SHIFT          25
1593 #define TM_CFG_PARENT_PF_MASK           0x7ULL
1594
1595 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT  30
1596 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK   0x1FFULL
1597
1598 #define TM_CFG_TID_OFFSET_SHIFT         30
1599 #define TM_CFG_TID_OFFSET_MASK          0x7FFFFULL
1600 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT  49
1601 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK   0x1FFULL
1602
1603 static void qed_tm_init_pf(struct qed_hwfn *p_hwfn)
1604 {
1605         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1606         u32 active_seg_mask = 0, tm_offset, rt_reg;
1607         struct qed_tm_iids tm_iids;
1608         u64 cfg_word;
1609         u8 i;
1610
1611         memset(&tm_iids, 0, sizeof(tm_iids));
1612         qed_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids);
1613
1614         /* @@@TBD No pre-scan for now */
1615
1616         /* Note: We assume consecutive VFs for a PF */
1617         for (i = 0; i < p_mngr->vf_count; i++) {
1618                 cfg_word = 0;
1619                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1620                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1621                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1622                 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);
1623                 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1624                     (sizeof(cfg_word) / sizeof(u32)) *
1625                     (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i);
1626                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1627         }
1628
1629         cfg_word = 0;
1630         SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1631         SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1632         SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);       /* n/a for PF */
1633         SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);       /* scan all   */
1634
1635         rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1636             (sizeof(cfg_word) / sizeof(u32)) *
1637             (NUM_OF_VFS(p_hwfn->cdev) + p_hwfn->rel_pf_id);
1638         STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1639
1640         /* enale scan */
1641         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1642                      tm_iids.pf_cids ? 0x1 : 0x0);
1643
1644         /* @@@TBD how to enable the scan for the VFs */
1645
1646         tm_offset = tm_iids.per_vf_cids;
1647
1648         /* Note: We assume consecutive VFs for a PF */
1649         for (i = 0; i < p_mngr->vf_count; i++) {
1650                 cfg_word = 0;
1651                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1652                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1653                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1654                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1655                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0);
1656
1657                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1658                     (sizeof(cfg_word) / sizeof(u32)) *
1659                     (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i);
1660
1661                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1662         }
1663
1664         tm_offset = tm_iids.pf_cids;
1665         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1666                 cfg_word = 0;
1667                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1668                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1669                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1670                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1671                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0);
1672
1673                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1674                     (sizeof(cfg_word) / sizeof(u32)) *
1675                     (NUM_OF_VFS(p_hwfn->cdev) +
1676                      p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1677
1678                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1679                 active_seg_mask |= (tm_iids.pf_tids[i] ? BIT(i) : 0);
1680
1681                 tm_offset += tm_iids.pf_tids[i];
1682         }
1683
1684         if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE)
1685                 active_seg_mask = 0;
1686
1687         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1688
1689         /* @@@TBD how to enable the scan for the VFs */
1690 }
1691
1692 void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn)
1693 {
1694         qed_cdu_init_common(p_hwfn);
1695 }
1696
1697 void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn)
1698 {
1699         qed_qm_init_pf(p_hwfn);
1700         qed_cm_init_pf(p_hwfn);
1701         qed_dq_init_pf(p_hwfn);
1702         qed_cdu_init_pf(p_hwfn);
1703         qed_ilt_init_pf(p_hwfn);
1704         qed_src_init_pf(p_hwfn);
1705         qed_tm_init_pf(p_hwfn);
1706 }
1707
1708 int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,
1709                         enum protocol_type type, u32 *p_cid)
1710 {
1711         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1712         u32 rel_cid;
1713
1714         if (type >= MAX_CONN_TYPES || !p_mngr->acquired[type].cid_map) {
1715                 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type);
1716                 return -EINVAL;
1717         }
1718
1719         rel_cid = find_first_zero_bit(p_mngr->acquired[type].cid_map,
1720                                       p_mngr->acquired[type].max_count);
1721
1722         if (rel_cid >= p_mngr->acquired[type].max_count) {
1723                 DP_NOTICE(p_hwfn, "no CID available for protocol %d\n", type);
1724                 return -EINVAL;
1725         }
1726
1727         __set_bit(rel_cid, p_mngr->acquired[type].cid_map);
1728
1729         *p_cid = rel_cid + p_mngr->acquired[type].start_cid;
1730
1731         return 0;
1732 }
1733
1734 static bool qed_cxt_test_cid_acquired(struct qed_hwfn *p_hwfn,
1735                                       u32 cid, enum protocol_type *p_type)
1736 {
1737         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1738         struct qed_cid_acquired_map *p_map;
1739         enum protocol_type p;
1740         u32 rel_cid;
1741
1742         /* Iterate over protocols and find matching cid range */
1743         for (p = 0; p < MAX_CONN_TYPES; p++) {
1744                 p_map = &p_mngr->acquired[p];
1745
1746                 if (!p_map->cid_map)
1747                         continue;
1748                 if (cid >= p_map->start_cid &&
1749                     cid < p_map->start_cid + p_map->max_count)
1750                         break;
1751         }
1752         *p_type = p;
1753
1754         if (p == MAX_CONN_TYPES) {
1755                 DP_NOTICE(p_hwfn, "Invalid CID %d", cid);
1756                 return false;
1757         }
1758
1759         rel_cid = cid - p_map->start_cid;
1760         if (!test_bit(rel_cid, p_map->cid_map)) {
1761                 DP_NOTICE(p_hwfn, "CID %d not acquired", cid);
1762                 return false;
1763         }
1764         return true;
1765 }
1766
1767 void qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid)
1768 {
1769         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1770         enum protocol_type type;
1771         bool b_acquired;
1772         u32 rel_cid;
1773
1774         /* Test acquired and find matching per-protocol map */
1775         b_acquired = qed_cxt_test_cid_acquired(p_hwfn, cid, &type);
1776
1777         if (!b_acquired)
1778                 return;
1779
1780         rel_cid = cid - p_mngr->acquired[type].start_cid;
1781         __clear_bit(rel_cid, p_mngr->acquired[type].cid_map);
1782 }
1783
1784 int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn, struct qed_cxt_info *p_info)
1785 {
1786         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1787         u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1788         enum protocol_type type;
1789         bool b_acquired;
1790
1791         /* Test acquired and find matching per-protocol map */
1792         b_acquired = qed_cxt_test_cid_acquired(p_hwfn, p_info->iid, &type);
1793
1794         if (!b_acquired)
1795                 return -EINVAL;
1796
1797         /* set the protocl type */
1798         p_info->type = type;
1799
1800         /* compute context virtual pointer */
1801         hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1802
1803         conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1804         cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1805         line = p_info->iid / cxts_per_p;
1806
1807         /* Make sure context is allocated (dynamic allocation) */
1808         if (!p_mngr->ilt_shadow[line].p_virt)
1809                 return -EINVAL;
1810
1811         p_info->p_cxt = p_mngr->ilt_shadow[line].p_virt +
1812                         p_info->iid % cxts_per_p * conn_cxt_size;
1813
1814         DP_VERBOSE(p_hwfn, (QED_MSG_ILT | QED_MSG_CXT),
1815                    "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1816                    p_info->iid / cxts_per_p, p_info->p_cxt, p_info->iid);
1817
1818         return 0;
1819 }
1820
1821 static void qed_rdma_set_pf_params(struct qed_hwfn *p_hwfn,
1822                                    struct qed_rdma_pf_params *p_params)
1823 {
1824         u32 num_cons, num_tasks, num_qps, num_mrs, num_srqs;
1825         enum protocol_type proto;
1826
1827         num_mrs = min_t(u32, RDMA_MAX_TIDS, p_params->num_mrs);
1828         num_tasks = num_mrs;    /* each mr uses a single task id */
1829         num_srqs = min_t(u32, 32 * 1024, p_params->num_srqs);
1830
1831         switch (p_hwfn->hw_info.personality) {
1832         case QED_PCI_ETH_ROCE:
1833                 num_qps = min_t(u32, ROCE_MAX_QPS, p_params->num_qps);
1834                 num_cons = num_qps * 2; /* each QP requires two connections */
1835                 proto = PROTOCOLID_ROCE;
1836                 break;
1837         default:
1838                 return;
1839         }
1840
1841         if (num_cons && num_tasks) {
1842                 qed_cxt_set_proto_cid_count(p_hwfn, proto, num_cons, 0);
1843
1844                 /* Deliberatly passing ROCE for tasks id. This is because
1845                  * iWARP / RoCE share the task id.
1846                  */
1847                 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE,
1848                                             QED_CXT_ROCE_TID_SEG, 1,
1849                                             num_tasks, false);
1850                 qed_cxt_set_srq_count(p_hwfn, num_srqs);
1851         } else {
1852                 DP_INFO(p_hwfn->cdev,
1853                         "RDMA personality used without setting params!\n");
1854         }
1855 }
1856
1857 int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn)
1858 {
1859         /* Set the number of required CORE connections */
1860         u32 core_cids = 1; /* SPQ */
1861
1862         if (p_hwfn->using_ll2)
1863                 core_cids += 4;
1864         qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1865
1866         switch (p_hwfn->hw_info.personality) {
1867         case QED_PCI_ETH_ROCE:
1868         {
1869                 qed_rdma_set_pf_params(p_hwfn,
1870                                        &p_hwfn->
1871                                        pf_params.rdma_pf_params);
1872                 /* no need for break since RoCE coexist with Ethernet */
1873         }
1874         case QED_PCI_ETH:
1875         {
1876                 struct qed_eth_pf_params *p_params =
1877                     &p_hwfn->pf_params.eth_pf_params;
1878
1879                 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1880                                             p_params->num_cons, 1);
1881                 break;
1882         }
1883         case QED_PCI_ISCSI:
1884         {
1885                 struct qed_iscsi_pf_params *p_params;
1886
1887                 p_params = &p_hwfn->pf_params.iscsi_pf_params;
1888
1889                 if (p_params->num_cons && p_params->num_tasks) {
1890                         qed_cxt_set_proto_cid_count(p_hwfn,
1891                                                     PROTOCOLID_ISCSI,
1892                                                     p_params->num_cons,
1893                                                     0);
1894
1895                         qed_cxt_set_proto_tid_count(p_hwfn,
1896                                                     PROTOCOLID_ISCSI,
1897                                                     QED_CXT_ISCSI_TID_SEG,
1898                                                     0,
1899                                                     p_params->num_tasks,
1900                                                     true);
1901                 } else {
1902                         DP_INFO(p_hwfn->cdev,
1903                                 "Iscsi personality used without setting params!\n");
1904                 }
1905                 break;
1906         }
1907         default:
1908                 return -EINVAL;
1909         }
1910
1911         return 0;
1912 }
1913
1914 int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn,
1915                              struct qed_tid_mem *p_info)
1916 {
1917         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1918         u32 proto, seg, total_lines, i, shadow_line;
1919         struct qed_ilt_client_cfg *p_cli;
1920         struct qed_ilt_cli_blk *p_fl_seg;
1921         struct qed_tid_seg *p_seg_info;
1922
1923         /* Verify the personality */
1924         switch (p_hwfn->hw_info.personality) {
1925         case QED_PCI_ISCSI:
1926                 proto = PROTOCOLID_ISCSI;
1927                 seg = QED_CXT_ISCSI_TID_SEG;
1928                 break;
1929         default:
1930                 return -EINVAL;
1931         }
1932
1933         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
1934         if (!p_cli->active)
1935                 return -EINVAL;
1936
1937         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
1938         if (!p_seg_info->has_fl_mem)
1939                 return -EINVAL;
1940
1941         p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
1942         total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
1943                                    p_fl_seg->real_size_in_page);
1944
1945         for (i = 0; i < total_lines; i++) {
1946                 shadow_line = i + p_fl_seg->start_line -
1947                     p_hwfn->p_cxt_mngr->pf_start_line;
1948                 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
1949         }
1950         p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
1951             p_fl_seg->real_size_in_page;
1952         p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
1953         p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
1954             p_info->tid_size;
1955
1956         return 0;
1957 }
1958
1959 /* This function is very RoCE oriented, if another protocol in the future
1960  * will want this feature we'll need to modify the function to be more generic
1961  */
1962 int
1963 qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn,
1964                           enum qed_cxt_elem_type elem_type, u32 iid)
1965 {
1966         u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
1967         struct qed_ilt_client_cfg *p_cli;
1968         struct qed_ilt_cli_blk *p_blk;
1969         struct qed_ptt *p_ptt;
1970         dma_addr_t p_phys;
1971         u64 ilt_hw_entry;
1972         void *p_virt;
1973         int rc = 0;
1974
1975         switch (elem_type) {
1976         case QED_ELEM_CXT:
1977                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1978                 elem_size = CONN_CXT_SIZE(p_hwfn);
1979                 p_blk = &p_cli->pf_blks[CDUC_BLK];
1980                 break;
1981         case QED_ELEM_SRQ:
1982                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
1983                 elem_size = SRQ_CXT_SIZE;
1984                 p_blk = &p_cli->pf_blks[SRQ_BLK];
1985                 break;
1986         case QED_ELEM_TASK:
1987                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1988                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
1989                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)];
1990                 break;
1991         default:
1992                 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type);
1993                 return -EINVAL;
1994         }
1995
1996         /* Calculate line in ilt */
1997         hw_p_size = p_cli->p_size.val;
1998         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
1999         line = p_blk->start_line + (iid / elems_per_p);
2000         shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
2001
2002         /* If line is already allocated, do nothing, otherwise allocate it and
2003          * write it to the PSWRQ2 registers.
2004          * This section can be run in parallel from different contexts and thus
2005          * a mutex protection is needed.
2006          */
2007
2008         mutex_lock(&p_hwfn->p_cxt_mngr->mutex);
2009
2010         if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
2011                 goto out0;
2012
2013         p_ptt = qed_ptt_acquire(p_hwfn);
2014         if (!p_ptt) {
2015                 DP_NOTICE(p_hwfn,
2016                           "QED_TIME_OUT on ptt acquire - dynamic allocation");
2017                 rc = -EBUSY;
2018                 goto out0;
2019         }
2020
2021         p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
2022                                     p_blk->real_size_in_page,
2023                                     &p_phys, GFP_KERNEL);
2024         if (!p_virt) {
2025                 rc = -ENOMEM;
2026                 goto out1;
2027         }
2028         memset(p_virt, 0, p_blk->real_size_in_page);
2029
2030         /* configuration of refTagMask to 0xF is required for RoCE DIF MR only,
2031          * to compensate for a HW bug, but it is configured even if DIF is not
2032          * enabled. This is harmless and allows us to avoid a dedicated API. We
2033          * configure the field for all of the contexts on the newly allocated
2034          * page.
2035          */
2036         if (elem_type == QED_ELEM_TASK) {
2037                 u32 elem_i;
2038                 u8 *elem_start = (u8 *)p_virt;
2039                 union type1_task_context *elem;
2040
2041                 for (elem_i = 0; elem_i < elems_per_p; elem_i++) {
2042                         elem = (union type1_task_context *)elem_start;
2043                         SET_FIELD(elem->roce_ctx.tdif_context.flags1,
2044                                   TDIF_TASK_CONTEXT_REFTAGMASK, 0xf);
2045                         elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn);
2046                 }
2047         }
2048
2049         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2050         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2051         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2052             p_blk->real_size_in_page;
2053
2054         /* compute absolute offset */
2055         reg_offset = PSWRQ2_REG_ILT_MEMORY +
2056             (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2057
2058         ilt_hw_entry = 0;
2059         SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2060         SET_FIELD(ilt_hw_entry,
2061                   ILT_ENTRY_PHY_ADDR,
2062                   (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2063
2064         /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2065         qed_dmae_host2grc(p_hwfn, p_ptt, (u64) (uintptr_t)&ilt_hw_entry,
2066                           reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 0);
2067
2068         if (elem_type == QED_ELEM_CXT) {
2069                 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2070                     elems_per_p;
2071
2072                 /* Update the relevant register in the parser */
2073                 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2074                        last_cid_allocated - 1);
2075
2076                 if (!p_hwfn->b_rdma_enabled_in_prs) {
2077                         /* Enable RoCE search */
2078                         qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2079                         p_hwfn->b_rdma_enabled_in_prs = true;
2080                 }
2081         }
2082
2083 out1:
2084         qed_ptt_release(p_hwfn, p_ptt);
2085 out0:
2086         mutex_unlock(&p_hwfn->p_cxt_mngr->mutex);
2087
2088         return rc;
2089 }
2090
2091 /* This function is very RoCE oriented, if another protocol in the future
2092  * will want this feature we'll need to modify the function to be more generic
2093  */
2094 static int
2095 qed_cxt_free_ilt_range(struct qed_hwfn *p_hwfn,
2096                        enum qed_cxt_elem_type elem_type,
2097                        u32 start_iid, u32 count)
2098 {
2099         u32 start_line, end_line, shadow_start_line, shadow_end_line;
2100         u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2101         struct qed_ilt_client_cfg *p_cli;
2102         struct qed_ilt_cli_blk *p_blk;
2103         u32 end_iid = start_iid + count;
2104         struct qed_ptt *p_ptt;
2105         u64 ilt_hw_entry = 0;
2106         u32 i;
2107
2108         switch (elem_type) {
2109         case QED_ELEM_CXT:
2110                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2111                 elem_size = CONN_CXT_SIZE(p_hwfn);
2112                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2113                 break;
2114         case QED_ELEM_SRQ:
2115                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2116                 elem_size = SRQ_CXT_SIZE;
2117                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2118                 break;
2119         case QED_ELEM_TASK:
2120                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2121                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2122                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)];
2123                 break;
2124         default:
2125                 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type);
2126                 return -EINVAL;
2127         }
2128
2129         /* Calculate line in ilt */
2130         hw_p_size = p_cli->p_size.val;
2131         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2132         start_line = p_blk->start_line + (start_iid / elems_per_p);
2133         end_line = p_blk->start_line + (end_iid / elems_per_p);
2134         if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2135                 end_line--;
2136
2137         shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2138         shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2139
2140         p_ptt = qed_ptt_acquire(p_hwfn);
2141         if (!p_ptt) {
2142                 DP_NOTICE(p_hwfn,
2143                           "QED_TIME_OUT on ptt acquire - dynamic allocation");
2144                 return -EBUSY;
2145         }
2146
2147         for (i = shadow_start_line; i < shadow_end_line; i++) {
2148                 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2149                         continue;
2150
2151                 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
2152                                   p_hwfn->p_cxt_mngr->ilt_shadow[i].size,
2153                                   p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2154                                   p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys);
2155
2156                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = NULL;
2157                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2158                 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2159
2160                 /* compute absolute offset */
2161                 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2162                     ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2163                      ILT_ENTRY_IN_REGS);
2164
2165                 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2166                  * wide-bus.
2167                  */
2168                 qed_dmae_host2grc(p_hwfn, p_ptt,
2169                                   (u64) (uintptr_t) &ilt_hw_entry,
2170                                   reg_offset,
2171                                   sizeof(ilt_hw_entry) / sizeof(u32),
2172                                   0);
2173         }
2174
2175         qed_ptt_release(p_hwfn, p_ptt);
2176
2177         return 0;
2178 }
2179
2180 int qed_cxt_free_proto_ilt(struct qed_hwfn *p_hwfn, enum protocol_type proto)
2181 {
2182         int rc;
2183         u32 cid;
2184
2185         /* Free Connection CXT */
2186         rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_CXT,
2187                                     qed_cxt_get_proto_cid_start(p_hwfn,
2188                                                                 proto),
2189                                     qed_cxt_get_proto_cid_count(p_hwfn,
2190                                                                 proto, &cid));
2191
2192         if (rc)
2193                 return rc;
2194
2195         /* Free Task CXT */
2196         rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_TASK, 0,
2197                                     qed_cxt_get_proto_tid_count(p_hwfn, proto));
2198         if (rc)
2199                 return rc;
2200
2201         /* Free TSDM CXT */
2202         rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_SRQ, 0,
2203                                     qed_cxt_get_srq_count(p_hwfn));
2204
2205         return rc;
2206 }
2207
2208 int qed_cxt_get_task_ctx(struct qed_hwfn *p_hwfn,
2209                          u32 tid, u8 ctx_type, void **pp_task_ctx)
2210 {
2211         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2212         struct qed_ilt_client_cfg *p_cli;
2213         struct qed_ilt_cli_blk *p_seg;
2214         struct qed_tid_seg *p_seg_info;
2215         u32 proto, seg;
2216         u32 total_lines;
2217         u32 tid_size, ilt_idx;
2218         u32 num_tids_per_block;
2219
2220         /* Verify the personality */
2221         switch (p_hwfn->hw_info.personality) {
2222         case QED_PCI_ISCSI:
2223                 proto = PROTOCOLID_ISCSI;
2224                 seg = QED_CXT_ISCSI_TID_SEG;
2225                 break;
2226         default:
2227                 return -EINVAL;
2228         }
2229
2230         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2231         if (!p_cli->active)
2232                 return -EINVAL;
2233
2234         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2235
2236         if (ctx_type == QED_CTX_WORKING_MEM) {
2237                 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
2238         } else if (ctx_type == QED_CTX_FL_MEM) {
2239                 if (!p_seg_info->has_fl_mem)
2240                         return -EINVAL;
2241                 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2242         } else {
2243                 return -EINVAL;
2244         }
2245         total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
2246         tid_size = p_mngr->task_type_size[p_seg_info->type];
2247         num_tids_per_block = p_seg->real_size_in_page / tid_size;
2248
2249         if (total_lines < tid / num_tids_per_block)
2250                 return -EINVAL;
2251
2252         ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2253                   p_mngr->pf_start_line;
2254         *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
2255                        (tid % num_tids_per_block) * tid_size;
2256
2257         return 0;
2258 }