1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
12 #include <linux/types.h>
14 #include <linux/delay.h>
15 #include <linux/firmware.h>
16 #include <linux/interrupt.h>
17 #include <linux/list.h>
18 #include <linux/mutex.h>
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/string.h>
22 #include <linux/workqueue.h>
23 #include <linux/zlib.h>
24 #include <linux/hashtable.h>
25 #include <linux/qed/qed_if.h>
26 #include "qed_debug.h"
29 extern const struct qed_common_ops qed_common_ops_pass;
30 #define DRV_MODULE_VERSION "8.10.9.20"
32 #define MAX_HWFNS_PER_DEVICE (4)
36 #define QED_WFQ_UNIT 100
38 #define QED_WID_SIZE (1024)
39 #define QED_PF_DEMS_SIZE (4)
42 enum qed_coalescing_mode {
43 QED_COAL_MODE_DISABLE,
47 struct qed_eth_cb_ops;
49 union qed_mcp_protocol_stats;
50 enum qed_mcp_protocol_type;
53 static inline u32 qed_db_addr(u32 cid, u32 DEMS)
55 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
56 (cid * QED_PF_DEMS_SIZE);
61 static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS)
63 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
64 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
69 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
70 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
71 ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
73 #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++)
75 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
76 (val == (cond1) ? true1 : \
77 (val == (cond2) ? true2 : def))
83 struct qed_sb_attn_info;
85 struct qed_sb_sp_info;
95 QED_MODE_L2GENEVE_TUNN,
96 QED_MODE_IPGENEVE_TUNN,
103 QED_TUNN_CLSS_MAC_VLAN,
104 QED_TUNN_CLSS_MAC_VNI,
105 QED_TUNN_CLSS_INNER_MAC_VLAN,
106 QED_TUNN_CLSS_INNER_MAC_VNI,
110 struct qed_tunn_start_params {
111 unsigned long tunn_mode;
114 u8 update_vxlan_udp_port;
115 u8 update_geneve_udp_port;
117 u8 tunn_clss_l2geneve;
118 u8 tunn_clss_ipgeneve;
123 struct qed_tunn_update_params {
124 unsigned long tunn_mode_update_mask;
125 unsigned long tunn_mode;
128 u8 update_rx_pf_clss;
129 u8 update_tx_pf_clss;
130 u8 update_vxlan_udp_port;
131 u8 update_geneve_udp_port;
133 u8 tunn_clss_l2geneve;
134 u8 tunn_clss_ipgeneve;
139 /* The PCI personality is not quite synonymous to protocol ID:
140 * 1. All personalities need CORE connections
141 * 2. The Ethernet personality may support also the RoCE protocol
143 enum qed_pci_personality {
147 QED_PCI_DEFAULT /* default in shmem */
150 /* All VFs are symmetric, all counters are PF + all VFs */
169 QED_RDMA_STATS_QUEUE,
181 QED_PORT_MODE_DE_2X40G,
182 QED_PORT_MODE_DE_2X50G,
183 QED_PORT_MODE_DE_1X100G,
184 QED_PORT_MODE_DE_4X10G_F,
185 QED_PORT_MODE_DE_4X10G_E,
186 QED_PORT_MODE_DE_4X20G,
187 QED_PORT_MODE_DE_1X40G,
188 QED_PORT_MODE_DE_2X25G,
189 QED_PORT_MODE_DE_1X25G
199 /* PCI personality */
200 enum qed_pci_personality personality;
202 /* Resource Allocation scheme results */
203 u32 resc_start[QED_MAX_RESC];
204 u32 resc_num[QED_MAX_RESC];
205 u32 feat_num[QED_MAX_FEATURES];
207 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
208 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
209 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
210 RESC_NUM(_p_hwfn, resc))
211 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
222 unsigned char hw_mac_addr[ETH_ALEN];
224 struct qed_igu_info *p_igu_info;
228 unsigned long device_capabilities;
231 struct qed_hw_cid_data {
233 bool b_cid_allocated;
235 /* Additional identifiers */
240 /* maximun size of read/write commands (HW limit) */
241 #define DMAE_MAX_RW_SIZE 0x2000
243 struct qed_dmae_info {
244 /* Mutex for synchronizing access to functions */
249 dma_addr_t completion_word_phys_addr;
251 /* The memory location where the DMAE writes the completion
252 * value when an operation is finished on this context.
254 u32 *p_completion_word;
256 dma_addr_t intermediate_buffer_phys_addr;
258 /* An intermediate buffer for DMAE operations that use virtual
259 * addresses - data is DMA'd to/from this buffer and then
260 * memcpy'd to/from the virtual address
262 u32 *p_intermediate_buffer;
264 dma_addr_t dmae_cmd_phys_addr;
265 struct dmae_cmd *p_dmae_cmd;
268 struct qed_wfq_data {
269 /* when feature is configured for at least 1 vport */
275 struct init_qm_pq_params *qm_pq_params;
276 struct init_qm_vport_params *qm_vport_params;
277 struct init_qm_port_params *qm_port_params;
288 u8 max_phys_tcs_per_port;
295 struct qed_wfq_data *wfq_data;
304 struct qed_storm_stats {
305 struct storm_stats mstats;
306 struct storm_stats pstats;
307 struct storm_stats tstats;
308 struct storm_stats ustats;
312 struct fw_ver_info *fw_ver_info;
313 const u8 *modes_tree_buf;
314 union init_op *init_ops;
319 struct qed_simd_fp_handler {
321 void (*func)(void *);
325 struct qed_dev *cdev;
326 u8 my_id; /* ID inside the PF */
327 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
328 u8 rel_pf_id; /* Relative to engine*/
330 #define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1)
336 char name[NAME_SIZE];
338 bool first_on_engine;
341 u8 num_funcs_on_engine;
345 void __iomem *regview;
346 void __iomem *doorbells;
348 unsigned long db_size;
351 struct qed_ptt_pool *p_ptt_pool;
354 struct qed_hw_info hw_info;
356 /* rt_array (for init-tool) */
357 struct qed_rt_data rt_data;
360 struct qed_spq *p_spq;
366 struct qed_consq *p_consq;
368 /* Slow-Path definitions */
369 struct tasklet_struct *sp_dpc;
370 bool b_sp_dpc_enabled;
372 struct qed_ptt *p_main_ptt;
373 struct qed_ptt *p_dpc_ptt;
375 struct qed_sb_sp_info *p_sp_sb;
376 struct qed_sb_attn_info *p_sb_attn;
378 /* Protocol related */
380 struct qed_ll2_info *p_ll2_info;
381 struct qed_rdma_info *p_rdma_info;
382 struct qed_pf_params pf_params;
384 bool b_rdma_enabled_in_prs;
385 u32 rdma_prs_search_reg;
387 /* Array of sb_info of all status blocks */
388 struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
391 struct qed_cxt_mngr *p_cxt_mngr;
393 /* Flag indicating whether interrupts are enabled or not*/
395 bool b_int_requested;
397 /* True if the driver requests for the link */
398 bool b_drv_link_init;
400 struct qed_vf_iov *vf_iov_info;
401 struct qed_pf_iov *pf_iov_info;
402 struct qed_mcp_info *mcp_info;
404 struct qed_dcbx_info *p_dcbx_info;
406 struct qed_hw_cid_data *p_tx_cids;
407 struct qed_hw_cid_data *p_rx_cids;
409 struct qed_dmae_info dmae_info;
412 struct qed_qm_info qm_info;
413 struct qed_storm_stats storm_stats;
415 /* Buffer for unzipping firmware data */
418 struct dbg_tools_data dbg_info;
420 /* PWM region specific data */
424 /* This is used to calculate the doorbell address */
425 u32 dpi_start_offset;
427 /* If one of the following is set then EDPM shouldn't be used */
431 struct qed_simd_fp_handler simd_proto_handler[64];
433 #ifdef CONFIG_QED_SRIOV
434 struct workqueue_struct *iov_wq;
435 struct delayed_work iov_task;
436 unsigned long iov_task_flags;
439 struct z_stream_s *stream;
440 struct qed_roce_ll2_info *ll2;
446 unsigned long mem_start;
447 unsigned long mem_end;
452 struct qed_int_param {
455 u8 min_msix_cnt; /* for minimal functionality */
458 struct qed_int_params {
459 struct qed_int_param in;
460 struct qed_int_param out;
461 struct msix_entry *msix_table;
469 struct qed_dbg_feature {
470 struct dentry *dentry;
476 struct qed_dbg_params {
477 struct qed_dbg_feature features[DBG_FEATURE_NUM];
485 char name[NAME_SIZE];
488 #define QED_DEV_TYPE_BB (0 << 0)
489 #define QED_DEV_TYPE_AH BIT(0)
490 /* Translate type/revision combo into the proper conditions */
491 #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
492 #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \
494 #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \
496 #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH)
497 #define QED_IS_K2(dev) QED_IS_AH(dev)
499 #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
500 QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
506 #define CHIP_NUM_MASK 0xffff
507 #define CHIP_NUM_SHIFT 16
510 #define CHIP_REV_MASK 0xf
511 #define CHIP_REV_SHIFT 12
512 #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev)
513 #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
516 #define CHIP_METAL_MASK 0xff
517 #define CHIP_METAL_SHIFT 4
520 #define CHIP_BOND_ID_MASK 0xf
521 #define CHIP_BOND_ID_SHIFT 0
524 u8 num_ports_in_engines;
525 u8 num_funcs_in_port;
528 enum qed_mf_mode mf_mode;
529 #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
530 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
531 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
535 u8 ver_str[VER_SIZE];
537 /* Add MF related configuration */
544 enum qed_coalescing_mode int_coalescing_mode;
545 u16 rx_coalesce_usecs;
546 u16 tx_coalesce_usecs;
548 /* Start Bar offset of first hwfn */
549 void __iomem *regview;
550 void __iomem *doorbells;
552 unsigned long db_size;
558 const struct iro *iro_arr;
559 #define IRO (p_hwfn->cdev->iro_arr)
563 struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
566 struct qed_hw_sriov_info *p_iov_info;
567 #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info)
569 unsigned long tunn_mode;
573 struct qed_eth_stats *reset_stats;
574 struct qed_fw_data *fw_data;
578 /* Linux specific here */
579 struct qede_dev *edev;
580 struct pci_dev *pdev;
583 struct pci_params pci_params;
585 struct qed_int_params int_params;
588 #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
590 /* Callbacks to protocol driver */
592 struct qed_common_cb_ops *common;
593 struct qed_eth_cb_ops *eth;
597 struct qed_dbg_params dbg_params;
599 #ifdef CONFIG_QED_LL2
600 struct qed_cb_ll2_info *ll2;
601 u8 ll2_mac_address[ETH_ALEN];
604 const struct firmware *firmware;
608 u32 rdma_max_srq_sge;
611 #define NUM_OF_VFS(dev) MAX_NUM_VFS_BB
612 #define NUM_OF_L2_QUEUES(dev) MAX_NUM_L2_QUEUES_BB
613 #define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB
614 #define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB
617 * @brief qed_concrete_to_sw_fid - get the sw function id from
618 * the concrete value.
620 * @param concrete_fid
624 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
627 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
628 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
629 u8 vf_valid = GET_FIELD(concrete_fid,
630 PXP_CONCRETE_FID_VFVALID);
634 sw_fid = vfid + MAX_NUM_PFS;
644 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
645 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
646 struct qed_ptt *p_ptt,
649 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
650 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
652 /* Other Linux specific common definitions */
653 #define DP_NAME(cdev) ((cdev)->name)
655 #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\
659 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
660 #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
661 #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
663 #define DOORBELL(cdev, db_addr, val) \
664 writel((u32)val, (void __iomem *)((u8 __iomem *)\
665 (cdev->doorbells) + (db_addr)))
668 int qed_fill_dev_info(struct qed_dev *cdev,
669 struct qed_dev_info *dev_info);
670 void qed_link_update(struct qed_hwfn *hwfn);
671 u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
672 u32 input_len, u8 *input_buf,
673 u32 max_size, u8 *unzip_buf);
674 void qed_get_protocol_stats(struct qed_dev *cdev,
675 enum qed_mcp_protocol_type type,
676 union qed_mcp_protocol_stats *stats);
677 int qed_slowpath_irq_req(struct qed_hwfn *hwfn);