1 /* yellowfin.c: A Packet Engines G-NIC ethernet driver for linux. */
3 Written 1997-2001 by Donald Becker.
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
12 This driver is for the Packet Engines G-NIC PCI Gigabit Ethernet adapter.
13 It also supports the Symbios Logic version of the same chip core.
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
20 Support and updates available at
21 http://www.scyld.com/network/yellowfin.html
22 [link no longer provides useful info -jgarzik]
26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28 #define DRV_NAME "yellowfin"
29 #define DRV_VERSION "2.1"
30 #define DRV_RELDATE "Sep 11, 2006"
32 /* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
35 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
37 static int max_interrupt_work = 20;
39 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
40 /* System-wide count of bogus-rx frames. */
42 static int dma_ctrl = 0x004A0263; /* Constrained by errata */
43 static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
44 #elif defined(YF_NEW) /* A future perfect board :->. */
45 static int dma_ctrl = 0x00CAC277; /* Override when loading module! */
46 static int fifo_cfg = 0x0028;
48 static const int dma_ctrl = 0x004A0263; /* Constrained by errata */
49 static const int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
52 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
53 Setting to > 1514 effectively disables this feature. */
54 static int rx_copybreak;
56 /* Used to pass the media type, etc.
57 No media types are currently defined. These exist for driver
60 #define MAX_UNITS 8 /* More are supported, limit only on options */
61 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
62 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
64 /* Do ugly workaround for GX server chipset errata. */
67 /* Operational parameters that are set at compile time. */
69 /* Keep the ring sizes a power of two for efficiency.
70 Making the Tx ring too long decreases the effectiveness of channel
71 bonding and packet priority.
72 There are no ill effects from too-large receive rings. */
73 #define TX_RING_SIZE 16
74 #define TX_QUEUE_SIZE 12 /* Must be > 4 && <= TX_RING_SIZE */
75 #define RX_RING_SIZE 64
76 #define STATUS_TOTAL_SIZE TX_RING_SIZE*sizeof(struct tx_status_words)
77 #define TX_TOTAL_SIZE 2*TX_RING_SIZE*sizeof(struct yellowfin_desc)
78 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct yellowfin_desc)
80 /* Operational parameters that usually are not changed. */
81 /* Time in jiffies before concluding the transmitter is hung. */
82 #define TX_TIMEOUT (2*HZ)
83 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
85 #define yellowfin_debug debug
87 #include <linux/module.h>
88 #include <linux/kernel.h>
89 #include <linux/string.h>
90 #include <linux/timer.h>
91 #include <linux/errno.h>
92 #include <linux/ioport.h>
93 #include <linux/interrupt.h>
94 #include <linux/pci.h>
95 #include <linux/init.h>
96 #include <linux/mii.h>
97 #include <linux/netdevice.h>
98 #include <linux/etherdevice.h>
99 #include <linux/skbuff.h>
100 #include <linux/ethtool.h>
101 #include <linux/crc32.h>
102 #include <linux/bitops.h>
103 #include <linux/uaccess.h>
104 #include <asm/processor.h> /* Processor type for cache alignment. */
105 #include <asm/unaligned.h>
108 /* These identify the driver base version and may not be removed. */
109 static const char version[] =
110 KERN_INFO DRV_NAME ".c:v1.05 1/09/2001 Written by Donald Becker <becker@scyld.com>\n"
111 " (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";
113 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
114 MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver");
115 MODULE_LICENSE("GPL");
117 module_param(max_interrupt_work, int, 0);
118 module_param(mtu, int, 0);
119 module_param(debug, int, 0);
120 module_param(rx_copybreak, int, 0);
121 module_param_array(options, int, NULL, 0);
122 module_param_array(full_duplex, int, NULL, 0);
123 module_param(gx_fix, int, 0);
124 MODULE_PARM_DESC(max_interrupt_work, "G-NIC maximum events handled per interrupt");
125 MODULE_PARM_DESC(mtu, "G-NIC MTU (all boards)");
126 MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)");
127 MODULE_PARM_DESC(rx_copybreak, "G-NIC copy breakpoint for copy-only-tiny-frames");
128 MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex");
129 MODULE_PARM_DESC(full_duplex, "G-NIC full duplex setting(s) (1)");
130 MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)");
135 I. Board Compatibility
137 This device driver is designed for the Packet Engines "Yellowfin" Gigabit
138 Ethernet adapter. The G-NIC 64-bit PCI card is supported, as well as the
139 Symbios 53C885E dual function chip.
141 II. Board-specific settings
143 PCI bus devices are configured by the system at boot time, so no jumpers
144 need to be set on the board. The system BIOS preferably should assign the
145 PCI INTA signal to an otherwise unused system IRQ line.
146 Note: Kernel versions earlier than 1.3.73 do not support shared PCI
149 III. Driver operation
153 The Yellowfin uses the Descriptor Based DMA Architecture specified by Apple.
154 This is a descriptor list scheme similar to that used by the EEPro100 and
155 Tulip. This driver uses two statically allocated fixed-size descriptor lists
156 formed into rings by a branch from the final descriptor to the beginning of
157 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
159 The driver allocates full frame size skbuffs for the Rx ring buffers at
160 open() time and passes the skb->data field to the Yellowfin as receive data
161 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
162 a fresh skbuff is allocated and the frame is copied to the new skbuff.
163 When the incoming frame is larger, the skbuff is passed directly up the
164 protocol stack and replaced by a newly allocated skbuff.
166 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
167 using a full-sized skbuff for small frames vs. the copying costs of larger
168 frames. For small frames the copying cost is negligible (esp. considering
169 that we are pre-loading the cache with immediately useful header
170 information). For large frames the copying cost is non-trivial, and the
171 larger copy might flush the cache of useful data.
173 IIIC. Synchronization
175 The driver runs as two independent, single-threaded flows of control. One
176 is the send-packet routine, which enforces single-threaded use by the
177 dev->tbusy flag. The other thread is the interrupt handler, which is single
178 threaded by the hardware and other software.
180 The send packet thread has partial control over the Tx ring and 'dev->tbusy'
181 flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
182 queue slot is empty, it clears the tbusy flag when finished otherwise it sets
183 the 'yp->tx_full' flag.
185 The interrupt handler has exclusive control over the Rx ring and records stats
186 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
187 empty by incrementing the dirty_tx mark. Iff the 'yp->tx_full' flag is set, it
188 clears both the tx_full and tbusy flags.
192 Thanks to Kim Stearns of Packet Engines for providing a pair of G-NIC boards.
193 Thanks to Bruce Faust of Digitalscape for providing both their SYM53C885 board
194 and an AlphaStation to verifty the Alpha port!
198 Yellowfin Engineering Design Specification, 4/23/97 Preliminary/Confidential
199 Symbios SYM53C885 PCI-SCSI/Fast Ethernet Multifunction Controller Preliminary
201 http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
202 http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
206 See Packet Engines confidential appendix (prototype chips only).
211 enum capability_flags {
212 HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16,
213 HasMACAddrBug=32, /* Only on early revs. */
214 DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */
217 /* The PCI I/O space extent. */
219 YELLOWFIN_SIZE = 0x100,
225 int pci, pci_mask, subsystem, subsystem_mask;
226 int revision, revision_mask; /* Only 8 bits. */
228 int drv_flags; /* Driver use, intended as capability flags. */
231 static const struct pci_id_info pci_id_tbl[] = {
232 {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
233 FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom},
234 {"Symbios SYM83C885", { 0x07011000, 0xffffffff},
235 HasMII | DontUseEeprom },
239 static const struct pci_device_id yellowfin_pci_tbl[] = {
240 { 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
241 { 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
244 MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl);
247 /* Offsets to the Yellowfin registers. Various sizes and alignments. */
248 enum yellowfin_offsets {
249 TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C,
250 TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18,
251 RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C,
252 RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58,
253 EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86,
254 ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94,
255 Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4,
256 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
258 RxDepth=0xB8, FlowCtrl=0xBC,
259 AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8,
260 EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4,
264 /* The Yellowfin Rx and Tx buffer descriptors.
265 Elements are written as 32 bit for endian portability. */
266 struct yellowfin_desc {
270 __le32 result_status;
273 struct tx_status_words {
279 #else /* Little endian chips. */
284 #endif /* __BIG_ENDIAN */
287 /* Bits in yellowfin_desc.cmd */
289 CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000,
290 CMD_NOP=0x60000000, CMD_STOP=0x70000000,
291 BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000,
292 BRANCH_IFTRUE=0x040000,
295 /* Bits in yellowfin_desc.status */
296 enum desc_status_bits { RX_EOP=0x0040, };
298 /* Bits in the interrupt status/mask registers. */
299 enum intr_status_bits {
300 IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08,
301 IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80,
302 IntrEarlyRx=0x100, IntrWakeup=0x200, };
304 #define PRIV_ALIGN 31 /* Required alignment mask */
306 struct yellowfin_private {
307 /* Descriptor rings first for alignment.
308 Tx requires a second descriptor for status. */
309 struct yellowfin_desc *rx_ring;
310 struct yellowfin_desc *tx_ring;
311 struct sk_buff* rx_skbuff[RX_RING_SIZE];
312 struct sk_buff* tx_skbuff[TX_RING_SIZE];
313 dma_addr_t rx_ring_dma;
314 dma_addr_t tx_ring_dma;
316 struct tx_status_words *tx_status;
317 dma_addr_t tx_status_dma;
319 struct timer_list timer; /* Media selection timer. */
320 /* Frequently used and paired value: keep adjacent for cache effect. */
321 int chip_id, drv_flags;
322 struct pci_dev *pci_dev;
323 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
324 unsigned int rx_buf_sz; /* Based on MTU+slack. */
325 struct tx_status_words *tx_tail_desc;
326 unsigned int cur_tx, dirty_tx;
328 unsigned int tx_full:1; /* The Tx queue is full. */
329 unsigned int full_duplex:1; /* Full-duplex operation requested. */
330 unsigned int duplex_lock:1;
331 unsigned int medialock:1; /* Do not sense media. */
332 unsigned int default_port:4; /* Last dev->if_port value. */
333 /* MII transceiver section. */
334 int mii_cnt; /* MII device addresses. */
335 u16 advertising; /* NWay media advertisement */
336 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used */
341 static int read_eeprom(void __iomem *ioaddr, int location);
342 static int mdio_read(void __iomem *ioaddr, int phy_id, int location);
343 static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value);
344 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
345 static int yellowfin_open(struct net_device *dev);
346 static void yellowfin_timer(struct timer_list *t);
347 static void yellowfin_tx_timeout(struct net_device *dev, unsigned int txqueue);
348 static int yellowfin_init_ring(struct net_device *dev);
349 static netdev_tx_t yellowfin_start_xmit(struct sk_buff *skb,
350 struct net_device *dev);
351 static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance);
352 static int yellowfin_rx(struct net_device *dev);
353 static void yellowfin_error(struct net_device *dev, int intr_status);
354 static int yellowfin_close(struct net_device *dev);
355 static void set_rx_mode(struct net_device *dev);
356 static const struct ethtool_ops ethtool_ops;
358 static const struct net_device_ops netdev_ops = {
359 .ndo_open = yellowfin_open,
360 .ndo_stop = yellowfin_close,
361 .ndo_start_xmit = yellowfin_start_xmit,
362 .ndo_set_rx_mode = set_rx_mode,
363 .ndo_validate_addr = eth_validate_addr,
364 .ndo_set_mac_address = eth_mac_addr,
365 .ndo_do_ioctl = netdev_ioctl,
366 .ndo_tx_timeout = yellowfin_tx_timeout,
369 static int yellowfin_init_one(struct pci_dev *pdev,
370 const struct pci_device_id *ent)
372 struct net_device *dev;
373 struct yellowfin_private *np;
375 int chip_idx = ent->driver_data;
377 void __iomem *ioaddr;
378 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
379 int drv_flags = pci_id_tbl[chip_idx].drv_flags;
388 /* when built into the kernel, we only print version if device is found */
390 static int printed_version;
391 if (!printed_version++)
395 i = pci_enable_device(pdev);
398 dev = alloc_etherdev(sizeof(*np));
402 SET_NETDEV_DEV(dev, &pdev->dev);
404 np = netdev_priv(dev);
406 if (pci_request_regions(pdev, DRV_NAME))
407 goto err_out_free_netdev;
409 pci_set_master (pdev);
411 ioaddr = pci_iomap(pdev, bar, YELLOWFIN_SIZE);
413 goto err_out_free_res;
417 if (drv_flags & DontUseEeprom)
418 for (i = 0; i < 6; i++)
419 dev->dev_addr[i] = ioread8(ioaddr + StnAddr + i);
421 int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0);
422 for (i = 0; i < 6; i++)
423 dev->dev_addr[i] = read_eeprom(ioaddr, ee_offset + i);
426 /* Reset the chip. */
427 iowrite32(0x80000000, ioaddr + DMACtrl);
429 pci_set_drvdata(pdev, dev);
430 spin_lock_init(&np->lock);
433 np->chip_id = chip_idx;
434 np->drv_flags = drv_flags;
437 ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE, &ring_dma,
440 goto err_out_cleardev;
441 np->tx_ring = ring_space;
442 np->tx_ring_dma = ring_dma;
444 ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE, &ring_dma,
447 goto err_out_unmap_tx;
448 np->rx_ring = ring_space;
449 np->rx_ring_dma = ring_dma;
451 ring_space = dma_alloc_coherent(&pdev->dev, STATUS_TOTAL_SIZE,
452 &ring_dma, GFP_KERNEL);
454 goto err_out_unmap_rx;
455 np->tx_status = ring_space;
456 np->tx_status_dma = ring_dma;
459 option = dev->mem_start;
461 /* The lower four bits are the media type. */
465 np->default_port = option & 15;
466 if (np->default_port)
469 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
475 /* The Yellowfin-specific entries in the device structure. */
476 dev->netdev_ops = &netdev_ops;
477 dev->ethtool_ops = ðtool_ops;
478 dev->watchdog_timeo = TX_TIMEOUT;
483 i = register_netdev(dev);
485 goto err_out_unmap_status;
487 netdev_info(dev, "%s type %8x at %p, %pM, IRQ %d\n",
488 pci_id_tbl[chip_idx].name,
489 ioread32(ioaddr + ChipRev), ioaddr,
492 if (np->drv_flags & HasMII) {
493 int phy, phy_idx = 0;
494 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
495 int mii_status = mdio_read(ioaddr, phy, 1);
496 if (mii_status != 0xffff && mii_status != 0x0000) {
497 np->phys[phy_idx++] = phy;
498 np->advertising = mdio_read(ioaddr, phy, 4);
499 netdev_info(dev, "MII PHY found at address %d, status 0x%04x advertising %04x\n",
500 phy, mii_status, np->advertising);
503 np->mii_cnt = phy_idx;
510 err_out_unmap_status:
511 dma_free_coherent(&pdev->dev, STATUS_TOTAL_SIZE, np->tx_status,
514 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring,
517 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring,
520 pci_iounmap(pdev, ioaddr);
522 pci_release_regions(pdev);
528 static int read_eeprom(void __iomem *ioaddr, int location)
530 int bogus_cnt = 10000; /* Typical 33Mhz: 1050 ticks */
532 iowrite8(location, ioaddr + EEAddr);
533 iowrite8(0x30 | ((location >> 8) & 7), ioaddr + EECtrl);
534 while ((ioread8(ioaddr + EEStatus) & 0x80) && --bogus_cnt > 0)
536 return ioread8(ioaddr + EERead);
539 /* MII Managemen Data I/O accesses.
540 These routines assume the MDIO controller is idle, and do not exit until
541 the command is finished. */
543 static int mdio_read(void __iomem *ioaddr, int phy_id, int location)
547 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
548 iowrite16(1, ioaddr + MII_Cmd);
549 for (i = 10000; i >= 0; i--)
550 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
552 return ioread16(ioaddr + MII_Rd_Data);
555 static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value)
559 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
560 iowrite16(value, ioaddr + MII_Wr_Data);
562 /* Wait for the command to finish. */
563 for (i = 10000; i >= 0; i--)
564 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
569 static int yellowfin_open(struct net_device *dev)
571 struct yellowfin_private *yp = netdev_priv(dev);
572 const int irq = yp->pci_dev->irq;
573 void __iomem *ioaddr = yp->base;
576 /* Reset the chip. */
577 iowrite32(0x80000000, ioaddr + DMACtrl);
579 rc = request_irq(irq, yellowfin_interrupt, IRQF_SHARED, dev->name, dev);
583 rc = yellowfin_init_ring(dev);
587 iowrite32(yp->rx_ring_dma, ioaddr + RxPtr);
588 iowrite32(yp->tx_ring_dma, ioaddr + TxPtr);
590 for (i = 0; i < 6; i++)
591 iowrite8(dev->dev_addr[i], ioaddr + StnAddr + i);
593 /* Set up various condition 'select' registers.
594 There are no options here. */
595 iowrite32(0x00800080, ioaddr + TxIntrSel); /* Interrupt on Tx abort */
596 iowrite32(0x00800080, ioaddr + TxBranchSel); /* Branch on Tx abort */
597 iowrite32(0x00400040, ioaddr + TxWaitSel); /* Wait on Tx status */
598 iowrite32(0x00400040, ioaddr + RxIntrSel); /* Interrupt on Rx done */
599 iowrite32(0x00400040, ioaddr + RxBranchSel); /* Branch on Rx error */
600 iowrite32(0x00400040, ioaddr + RxWaitSel); /* Wait on Rx done */
602 /* Initialize other registers: with so many this eventually this will
603 converted to an offset/value list. */
604 iowrite32(dma_ctrl, ioaddr + DMACtrl);
605 iowrite16(fifo_cfg, ioaddr + FIFOcfg);
606 /* Enable automatic generation of flow control frames, period 0xffff. */
607 iowrite32(0x0030FFFF, ioaddr + FlowCtrl);
609 yp->tx_threshold = 32;
610 iowrite32(yp->tx_threshold, ioaddr + TxThreshold);
612 if (dev->if_port == 0)
613 dev->if_port = yp->default_port;
615 netif_start_queue(dev);
617 /* Setting the Rx mode will start the Rx process. */
618 if (yp->drv_flags & IsGigabit) {
619 /* We are always in full-duplex mode with gigabit! */
621 iowrite16(0x01CF, ioaddr + Cnfg);
623 iowrite16(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */
624 iowrite16(0x1018, ioaddr + FrameGap1);
625 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
629 /* Enable interrupts by setting the interrupt mask. */
630 iowrite16(0x81ff, ioaddr + IntrEnb); /* See enum intr_status_bits */
631 iowrite16(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
632 iowrite32(0x80008000, ioaddr + RxCtrl); /* Start Rx and Tx channels. */
633 iowrite32(0x80008000, ioaddr + TxCtrl);
635 if (yellowfin_debug > 2) {
636 netdev_printk(KERN_DEBUG, dev, "Done %s()\n", __func__);
639 /* Set the timer to check for link beat. */
640 timer_setup(&yp->timer, yellowfin_timer, 0);
641 yp->timer.expires = jiffies + 3*HZ;
642 add_timer(&yp->timer);
651 static void yellowfin_timer(struct timer_list *t)
653 struct yellowfin_private *yp = from_timer(yp, t, timer);
654 struct net_device *dev = pci_get_drvdata(yp->pci_dev);
655 void __iomem *ioaddr = yp->base;
656 int next_tick = 60*HZ;
658 if (yellowfin_debug > 3) {
659 netdev_printk(KERN_DEBUG, dev, "Yellowfin timer tick, status %08x\n",
660 ioread16(ioaddr + IntrStatus));
664 int bmsr = mdio_read(ioaddr, yp->phys[0], MII_BMSR);
665 int lpa = mdio_read(ioaddr, yp->phys[0], MII_LPA);
666 int negotiated = lpa & yp->advertising;
667 if (yellowfin_debug > 1)
668 netdev_printk(KERN_DEBUG, dev, "MII #%d status register is %04x, link partner capability %04x\n",
669 yp->phys[0], bmsr, lpa);
671 yp->full_duplex = mii_duplex(yp->duplex_lock, negotiated);
673 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
675 if (bmsr & BMSR_LSTATUS)
681 yp->timer.expires = jiffies + next_tick;
682 add_timer(&yp->timer);
685 static void yellowfin_tx_timeout(struct net_device *dev, unsigned int txqueue)
687 struct yellowfin_private *yp = netdev_priv(dev);
688 void __iomem *ioaddr = yp->base;
690 netdev_warn(dev, "Yellowfin transmit timed out at %d/%d Tx status %04x, Rx status %04x, resetting...\n",
691 yp->cur_tx, yp->dirty_tx,
692 ioread32(ioaddr + TxStatus),
693 ioread32(ioaddr + RxStatus));
695 /* Note: these should be KERN_DEBUG. */
696 if (yellowfin_debug) {
698 pr_warn(" Rx ring %p: ", yp->rx_ring);
699 for (i = 0; i < RX_RING_SIZE; i++)
700 pr_cont(" %08x", yp->rx_ring[i].result_status);
702 pr_warn(" Tx ring %p: ", yp->tx_ring);
703 for (i = 0; i < TX_RING_SIZE; i++)
704 pr_cont(" %04x /%08x",
705 yp->tx_status[i].tx_errs,
706 yp->tx_ring[i].result_status);
710 /* If the hardware is found to hang regularly, we will update the code
711 to reinitialize the chip here. */
714 /* Wake the potentially-idle transmit channel. */
715 iowrite32(0x10001000, yp->base + TxCtrl);
716 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
717 netif_wake_queue (dev); /* Typical path */
719 netif_trans_update(dev); /* prevent tx timeout */
720 dev->stats.tx_errors++;
723 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
724 static int yellowfin_init_ring(struct net_device *dev)
726 struct yellowfin_private *yp = netdev_priv(dev);
730 yp->cur_rx = yp->cur_tx = 0;
733 yp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
735 for (i = 0; i < RX_RING_SIZE; i++) {
736 yp->rx_ring[i].dbdma_cmd =
737 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
738 yp->rx_ring[i].branch_addr = cpu_to_le32(yp->rx_ring_dma +
739 ((i+1)%RX_RING_SIZE)*sizeof(struct yellowfin_desc));
742 for (i = 0; i < RX_RING_SIZE; i++) {
743 struct sk_buff *skb = netdev_alloc_skb(dev, yp->rx_buf_sz + 2);
744 yp->rx_skbuff[i] = skb;
747 skb_reserve(skb, 2); /* 16 byte align the IP header. */
748 yp->rx_ring[i].addr = cpu_to_le32(dma_map_single(&yp->pci_dev->dev,
753 if (i != RX_RING_SIZE) {
754 for (j = 0; j < i; j++)
755 dev_kfree_skb(yp->rx_skbuff[j]);
758 yp->rx_ring[i-1].dbdma_cmd = cpu_to_le32(CMD_STOP);
759 yp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
763 /* In this mode the Tx ring needs only a single descriptor. */
764 for (i = 0; i < TX_RING_SIZE; i++) {
765 yp->tx_skbuff[i] = NULL;
766 yp->tx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
767 yp->tx_ring[i].branch_addr = cpu_to_le32(yp->tx_ring_dma +
768 ((i+1)%TX_RING_SIZE)*sizeof(struct yellowfin_desc));
771 yp->tx_ring[--i].dbdma_cmd = cpu_to_le32(CMD_STOP | BRANCH_ALWAYS);
774 /* Tx ring needs a pair of descriptors, the second for the status. */
775 for (i = 0; i < TX_RING_SIZE; i++) {
777 yp->tx_skbuff[i] = 0;
778 /* Branch on Tx error. */
779 yp->tx_ring[j].dbdma_cmd = cpu_to_le32(CMD_STOP);
780 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
781 (j+1)*sizeof(struct yellowfin_desc));
783 if (yp->flags & FullTxStatus) {
784 yp->tx_ring[j].dbdma_cmd =
785 cpu_to_le32(CMD_TXSTATUS | sizeof(*yp->tx_status));
786 yp->tx_ring[j].request_cnt = sizeof(*yp->tx_status);
787 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
788 i*sizeof(struct tx_status_words));
790 /* Symbios chips write only tx_errs word. */
791 yp->tx_ring[j].dbdma_cmd =
792 cpu_to_le32(CMD_TXSTATUS | INTR_ALWAYS | 2);
793 yp->tx_ring[j].request_cnt = 2;
794 /* Om pade ummmmm... */
795 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
796 i*sizeof(struct tx_status_words) +
797 &(yp->tx_status[0].tx_errs) -
798 &(yp->tx_status[0]));
800 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
801 ((j+1)%(2*TX_RING_SIZE))*sizeof(struct yellowfin_desc));
804 yp->tx_ring[++j].dbdma_cmd |= cpu_to_le32(BRANCH_ALWAYS | INTR_ALWAYS);
807 yp->tx_tail_desc = &yp->tx_status[0];
811 static netdev_tx_t yellowfin_start_xmit(struct sk_buff *skb,
812 struct net_device *dev)
814 struct yellowfin_private *yp = netdev_priv(dev);
818 netif_stop_queue (dev);
820 /* Note: Ordering is important here, set the field with the
821 "ownership" bit last, and only then increment cur_tx. */
823 /* Calculate the next Tx descriptor entry. */
824 entry = yp->cur_tx % TX_RING_SIZE;
826 if (gx_fix) { /* Note: only works for paddable protocols e.g. IP. */
827 int cacheline_end = ((unsigned long)skb->data + skb->len) % 32;
828 /* Fix GX chipset errata. */
829 if (cacheline_end > 24 || cacheline_end == 0) {
830 len = skb->len + 32 - cacheline_end + 1;
831 if (skb_padto(skb, len)) {
832 yp->tx_skbuff[entry] = NULL;
833 netif_wake_queue(dev);
838 yp->tx_skbuff[entry] = skb;
841 yp->tx_ring[entry].addr = cpu_to_le32(dma_map_single(&yp->pci_dev->dev,
843 len, DMA_TO_DEVICE));
844 yp->tx_ring[entry].result_status = 0;
845 if (entry >= TX_RING_SIZE-1) {
846 /* New stop command. */
847 yp->tx_ring[0].dbdma_cmd = cpu_to_le32(CMD_STOP);
848 yp->tx_ring[TX_RING_SIZE-1].dbdma_cmd =
849 cpu_to_le32(CMD_TX_PKT|BRANCH_ALWAYS | len);
851 yp->tx_ring[entry+1].dbdma_cmd = cpu_to_le32(CMD_STOP);
852 yp->tx_ring[entry].dbdma_cmd =
853 cpu_to_le32(CMD_TX_PKT | BRANCH_IFTRUE | len);
857 yp->tx_ring[entry<<1].request_cnt = len;
858 yp->tx_ring[entry<<1].addr = cpu_to_le32(dma_map_single(&yp->pci_dev->dev,
860 len, DMA_TO_DEVICE));
861 /* The input_last (status-write) command is constant, but we must
862 rewrite the subsequent 'stop' command. */
866 unsigned next_entry = yp->cur_tx % TX_RING_SIZE;
867 yp->tx_ring[next_entry<<1].dbdma_cmd = cpu_to_le32(CMD_STOP);
869 /* Final step -- overwrite the old 'stop' command. */
871 yp->tx_ring[entry<<1].dbdma_cmd =
872 cpu_to_le32( ((entry % 6) == 0 ? CMD_TX_PKT|INTR_ALWAYS|BRANCH_IFTRUE :
873 CMD_TX_PKT | BRANCH_IFTRUE) | len);
876 /* Non-x86 Todo: explicitly flush cache lines here. */
878 /* Wake the potentially-idle transmit channel. */
879 iowrite32(0x10001000, yp->base + TxCtrl);
881 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
882 netif_start_queue (dev); /* Typical path */
886 if (yellowfin_debug > 4) {
887 netdev_printk(KERN_DEBUG, dev, "Yellowfin transmit frame #%d queued in slot %d\n",
893 /* The interrupt handler does all of the Rx thread work and cleans up
894 after the Tx thread. */
895 static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance)
897 struct net_device *dev = dev_instance;
898 struct yellowfin_private *yp;
899 void __iomem *ioaddr;
900 int boguscnt = max_interrupt_work;
901 unsigned int handled = 0;
903 yp = netdev_priv(dev);
906 spin_lock (&yp->lock);
909 u16 intr_status = ioread16(ioaddr + IntrClear);
911 if (yellowfin_debug > 4)
912 netdev_printk(KERN_DEBUG, dev, "Yellowfin interrupt, status %04x\n",
915 if (intr_status == 0)
919 if (intr_status & (IntrRxDone | IntrEarlyRx)) {
921 iowrite32(0x10001000, ioaddr + RxCtrl); /* Wake Rx engine. */
925 for (; yp->cur_tx - yp->dirty_tx > 0; yp->dirty_tx++) {
926 int entry = yp->dirty_tx % TX_RING_SIZE;
929 if (yp->tx_ring[entry].result_status == 0)
931 skb = yp->tx_skbuff[entry];
932 dev->stats.tx_packets++;
933 dev->stats.tx_bytes += skb->len;
934 /* Free the original skb. */
935 dma_unmap_single(&yp->pci_dev->dev,
936 le32_to_cpu(yp->tx_ring[entry].addr),
937 skb->len, DMA_TO_DEVICE);
938 dev_consume_skb_irq(skb);
939 yp->tx_skbuff[entry] = NULL;
942 yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) {
943 /* The ring is no longer full, clear tbusy. */
945 netif_wake_queue(dev);
948 if ((intr_status & IntrTxDone) || (yp->tx_tail_desc->tx_errs)) {
949 unsigned dirty_tx = yp->dirty_tx;
951 for (dirty_tx = yp->dirty_tx; yp->cur_tx - dirty_tx > 0;
953 /* Todo: optimize this. */
954 int entry = dirty_tx % TX_RING_SIZE;
955 u16 tx_errs = yp->tx_status[entry].tx_errs;
958 #ifndef final_version
959 if (yellowfin_debug > 5)
960 netdev_printk(KERN_DEBUG, dev, "Tx queue %d check, Tx status %04x %04x %04x %04x\n",
962 yp->tx_status[entry].tx_cnt,
963 yp->tx_status[entry].tx_errs,
964 yp->tx_status[entry].total_tx_cnt,
965 yp->tx_status[entry].paused);
968 break; /* It still hasn't been Txed */
969 skb = yp->tx_skbuff[entry];
970 if (tx_errs & 0xF810) {
971 /* There was an major error, log it. */
972 #ifndef final_version
973 if (yellowfin_debug > 1)
974 netdev_printk(KERN_DEBUG, dev, "Transmit error, Tx status %04x\n",
977 dev->stats.tx_errors++;
978 if (tx_errs & 0xF800) dev->stats.tx_aborted_errors++;
979 if (tx_errs & 0x0800) dev->stats.tx_carrier_errors++;
980 if (tx_errs & 0x2000) dev->stats.tx_window_errors++;
981 if (tx_errs & 0x8000) dev->stats.tx_fifo_errors++;
983 #ifndef final_version
984 if (yellowfin_debug > 4)
985 netdev_printk(KERN_DEBUG, dev, "Normal transmit, Tx status %04x\n",
988 dev->stats.tx_bytes += skb->len;
989 dev->stats.collisions += tx_errs & 15;
990 dev->stats.tx_packets++;
992 /* Free the original skb. */
993 dma_unmap_single(&yp->pci_dev->dev,
994 yp->tx_ring[entry << 1].addr,
995 skb->len, DMA_TO_DEVICE);
996 dev_consume_skb_irq(skb);
997 yp->tx_skbuff[entry] = 0;
998 /* Mark status as empty. */
999 yp->tx_status[entry].tx_errs = 0;
1002 #ifndef final_version
1003 if (yp->cur_tx - dirty_tx > TX_RING_SIZE) {
1004 netdev_err(dev, "Out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1005 dirty_tx, yp->cur_tx, yp->tx_full);
1006 dirty_tx += TX_RING_SIZE;
1011 yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) {
1012 /* The ring is no longer full, clear tbusy. */
1014 netif_wake_queue(dev);
1017 yp->dirty_tx = dirty_tx;
1018 yp->tx_tail_desc = &yp->tx_status[dirty_tx % TX_RING_SIZE];
1022 /* Log errors and other uncommon events. */
1023 if (intr_status & 0x2ee) /* Abnormal error summary. */
1024 yellowfin_error(dev, intr_status);
1026 if (--boguscnt < 0) {
1027 netdev_warn(dev, "Too much work at interrupt, status=%#04x\n",
1033 if (yellowfin_debug > 3)
1034 netdev_printk(KERN_DEBUG, dev, "exiting interrupt, status=%#04x\n",
1035 ioread16(ioaddr + IntrStatus));
1037 spin_unlock (&yp->lock);
1038 return IRQ_RETVAL(handled);
1041 /* This routine is logically part of the interrupt handler, but separated
1042 for clarity and better register allocation. */
1043 static int yellowfin_rx(struct net_device *dev)
1045 struct yellowfin_private *yp = netdev_priv(dev);
1046 int entry = yp->cur_rx % RX_RING_SIZE;
1047 int boguscnt = yp->dirty_rx + RX_RING_SIZE - yp->cur_rx;
1049 if (yellowfin_debug > 4) {
1050 printk(KERN_DEBUG " In yellowfin_rx(), entry %d status %08x\n",
1051 entry, yp->rx_ring[entry].result_status);
1052 printk(KERN_DEBUG " #%d desc. %08x %08x %08x\n",
1053 entry, yp->rx_ring[entry].dbdma_cmd, yp->rx_ring[entry].addr,
1054 yp->rx_ring[entry].result_status);
1057 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1059 struct yellowfin_desc *desc = &yp->rx_ring[entry];
1060 struct sk_buff *rx_skb = yp->rx_skbuff[entry];
1063 int data_size, __maybe_unused yf_size;
1066 if(!desc->result_status)
1068 dma_sync_single_for_cpu(&yp->pci_dev->dev,
1069 le32_to_cpu(desc->addr),
1070 yp->rx_buf_sz, DMA_FROM_DEVICE);
1071 desc_status = le32_to_cpu(desc->result_status) >> 16;
1072 buf_addr = rx_skb->data;
1073 data_size = (le32_to_cpu(desc->dbdma_cmd) -
1074 le32_to_cpu(desc->result_status)) & 0xffff;
1075 frame_status = get_unaligned_le16(&(buf_addr[data_size - 2]));
1076 if (yellowfin_debug > 4)
1077 printk(KERN_DEBUG " %s() status was %04x\n",
1078 __func__, frame_status);
1082 yf_size = sizeof(struct yellowfin_desc);
1084 if ( ! (desc_status & RX_EOP)) {
1086 netdev_warn(dev, "Oversized Ethernet frame spanned multiple buffers, status %04x, data_size %d!\n",
1087 desc_status, data_size);
1088 dev->stats.rx_length_errors++;
1089 } else if ((yp->drv_flags & IsGigabit) && (frame_status & 0x0038)) {
1090 /* There was a error. */
1091 if (yellowfin_debug > 3)
1092 printk(KERN_DEBUG " %s() Rx error was %04x\n",
1093 __func__, frame_status);
1094 dev->stats.rx_errors++;
1095 if (frame_status & 0x0060) dev->stats.rx_length_errors++;
1096 if (frame_status & 0x0008) dev->stats.rx_frame_errors++;
1097 if (frame_status & 0x0010) dev->stats.rx_crc_errors++;
1098 if (frame_status < 0) dev->stats.rx_dropped++;
1099 } else if ( !(yp->drv_flags & IsGigabit) &&
1100 ((buf_addr[data_size-1] & 0x85) || buf_addr[data_size-2] & 0xC0)) {
1101 u8 status1 = buf_addr[data_size-2];
1102 u8 status2 = buf_addr[data_size-1];
1103 dev->stats.rx_errors++;
1104 if (status1 & 0xC0) dev->stats.rx_length_errors++;
1105 if (status2 & 0x03) dev->stats.rx_frame_errors++;
1106 if (status2 & 0x04) dev->stats.rx_crc_errors++;
1107 if (status2 & 0x80) dev->stats.rx_dropped++;
1108 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1109 } else if ((yp->flags & HasMACAddrBug) &&
1110 !ether_addr_equal(le32_to_cpu(yp->rx_ring_dma +
1113 !ether_addr_equal(le32_to_cpu(yp->rx_ring_dma +
1115 "\377\377\377\377\377\377")) {
1116 if (bogus_rx++ == 0)
1117 netdev_warn(dev, "Bad frame to %pM\n",
1121 struct sk_buff *skb;
1122 int pkt_len = data_size -
1123 (yp->chip_id ? 7 : 8 + buf_addr[data_size - 8]);
1124 /* To verify: Yellowfin Length should omit the CRC! */
1126 #ifndef final_version
1127 if (yellowfin_debug > 4)
1128 printk(KERN_DEBUG " %s() normal Rx pkt length %d of %d, bogus_cnt %d\n",
1129 __func__, pkt_len, data_size, boguscnt);
1131 /* Check if the packet is long enough to just pass up the skbuff
1132 without copying to a properly sized skbuff. */
1133 if (pkt_len > rx_copybreak) {
1134 skb_put(skb = rx_skb, pkt_len);
1135 dma_unmap_single(&yp->pci_dev->dev,
1136 le32_to_cpu(yp->rx_ring[entry].addr),
1139 yp->rx_skbuff[entry] = NULL;
1141 skb = netdev_alloc_skb(dev, pkt_len + 2);
1144 skb_reserve(skb, 2); /* 16 byte align the IP header */
1145 skb_copy_to_linear_data(skb, rx_skb->data, pkt_len);
1146 skb_put(skb, pkt_len);
1147 dma_sync_single_for_device(&yp->pci_dev->dev,
1148 le32_to_cpu(desc->addr),
1152 skb->protocol = eth_type_trans(skb, dev);
1154 dev->stats.rx_packets++;
1155 dev->stats.rx_bytes += pkt_len;
1157 entry = (++yp->cur_rx) % RX_RING_SIZE;
1160 /* Refill the Rx ring buffers. */
1161 for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) {
1162 entry = yp->dirty_rx % RX_RING_SIZE;
1163 if (yp->rx_skbuff[entry] == NULL) {
1164 struct sk_buff *skb = netdev_alloc_skb(dev, yp->rx_buf_sz + 2);
1166 break; /* Better luck next round. */
1167 yp->rx_skbuff[entry] = skb;
1168 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1169 yp->rx_ring[entry].addr = cpu_to_le32(dma_map_single(&yp->pci_dev->dev,
1174 yp->rx_ring[entry].dbdma_cmd = cpu_to_le32(CMD_STOP);
1175 yp->rx_ring[entry].result_status = 0; /* Clear complete bit. */
1177 yp->rx_ring[entry - 1].dbdma_cmd =
1178 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
1180 yp->rx_ring[RX_RING_SIZE - 1].dbdma_cmd =
1181 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | BRANCH_ALWAYS
1188 static void yellowfin_error(struct net_device *dev, int intr_status)
1190 netdev_err(dev, "Something Wicked happened! %04x\n", intr_status);
1191 /* Hmmmmm, it's not clear what to do here. */
1192 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
1193 dev->stats.tx_errors++;
1194 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
1195 dev->stats.rx_errors++;
1198 static int yellowfin_close(struct net_device *dev)
1200 struct yellowfin_private *yp = netdev_priv(dev);
1201 void __iomem *ioaddr = yp->base;
1204 netif_stop_queue (dev);
1206 if (yellowfin_debug > 1) {
1207 netdev_printk(KERN_DEBUG, dev, "Shutting down ethercard, status was Tx %04x Rx %04x Int %02x\n",
1208 ioread16(ioaddr + TxStatus),
1209 ioread16(ioaddr + RxStatus),
1210 ioread16(ioaddr + IntrStatus));
1211 netdev_printk(KERN_DEBUG, dev, "Queue pointers were Tx %d / %d, Rx %d / %d\n",
1212 yp->cur_tx, yp->dirty_tx,
1213 yp->cur_rx, yp->dirty_rx);
1216 /* Disable interrupts by clearing the interrupt mask. */
1217 iowrite16(0x0000, ioaddr + IntrEnb);
1219 /* Stop the chip's Tx and Rx processes. */
1220 iowrite32(0x80000000, ioaddr + RxCtrl);
1221 iowrite32(0x80000000, ioaddr + TxCtrl);
1223 del_timer(&yp->timer);
1225 #if defined(__i386__)
1226 if (yellowfin_debug > 2) {
1227 printk(KERN_DEBUG " Tx ring at %08llx:\n",
1228 (unsigned long long)yp->tx_ring_dma);
1229 for (i = 0; i < TX_RING_SIZE*2; i++)
1230 printk(KERN_DEBUG " %c #%d desc. %08x %08x %08x %08x\n",
1231 ioread32(ioaddr + TxPtr) == (long)&yp->tx_ring[i] ? '>' : ' ',
1232 i, yp->tx_ring[i].dbdma_cmd, yp->tx_ring[i].addr,
1233 yp->tx_ring[i].branch_addr, yp->tx_ring[i].result_status);
1234 printk(KERN_DEBUG " Tx status %p:\n", yp->tx_status);
1235 for (i = 0; i < TX_RING_SIZE; i++)
1236 printk(KERN_DEBUG " #%d status %04x %04x %04x %04x\n",
1237 i, yp->tx_status[i].tx_cnt, yp->tx_status[i].tx_errs,
1238 yp->tx_status[i].total_tx_cnt, yp->tx_status[i].paused);
1240 printk(KERN_DEBUG " Rx ring %08llx:\n",
1241 (unsigned long long)yp->rx_ring_dma);
1242 for (i = 0; i < RX_RING_SIZE; i++) {
1243 printk(KERN_DEBUG " %c #%d desc. %08x %08x %08x\n",
1244 ioread32(ioaddr + RxPtr) == (long)&yp->rx_ring[i] ? '>' : ' ',
1245 i, yp->rx_ring[i].dbdma_cmd, yp->rx_ring[i].addr,
1246 yp->rx_ring[i].result_status);
1247 if (yellowfin_debug > 6) {
1248 if (get_unaligned((u8*)yp->rx_ring[i].addr) != 0x69) {
1252 for (j = 0; j < 0x50; j++)
1254 get_unaligned(((u16*)yp->rx_ring[i].addr) + j));
1260 #endif /* __i386__ debugging only */
1262 free_irq(yp->pci_dev->irq, dev);
1264 /* Free all the skbuffs in the Rx queue. */
1265 for (i = 0; i < RX_RING_SIZE; i++) {
1266 yp->rx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
1267 yp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1268 if (yp->rx_skbuff[i]) {
1269 dev_kfree_skb(yp->rx_skbuff[i]);
1271 yp->rx_skbuff[i] = NULL;
1273 for (i = 0; i < TX_RING_SIZE; i++) {
1274 dev_kfree_skb(yp->tx_skbuff[i]);
1275 yp->tx_skbuff[i] = NULL;
1278 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1279 if (yellowfin_debug > 0) {
1280 netdev_printk(KERN_DEBUG, dev, "Received %d frames that we should not have\n",
1288 /* Set or clear the multicast filter for this adaptor. */
1290 static void set_rx_mode(struct net_device *dev)
1292 struct yellowfin_private *yp = netdev_priv(dev);
1293 void __iomem *ioaddr = yp->base;
1294 u16 cfg_value = ioread16(ioaddr + Cnfg);
1296 /* Stop the Rx process to change any value. */
1297 iowrite16(cfg_value & ~0x1000, ioaddr + Cnfg);
1298 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1299 iowrite16(0x000F, ioaddr + AddrMode);
1300 } else if ((netdev_mc_count(dev) > 64) ||
1301 (dev->flags & IFF_ALLMULTI)) {
1302 /* Too many to filter well, or accept all multicasts. */
1303 iowrite16(0x000B, ioaddr + AddrMode);
1304 } else if (!netdev_mc_empty(dev)) { /* Must use the multicast hash table. */
1305 struct netdev_hw_addr *ha;
1309 memset(hash_table, 0, sizeof(hash_table));
1310 netdev_for_each_mc_addr(ha, dev) {
1313 /* Due to a bug in the early chip versions, multiple filter
1314 slots must be set for each address. */
1315 if (yp->drv_flags & HasMulticastBug) {
1316 bit = (ether_crc_le(3, ha->addr) >> 3) & 0x3f;
1317 hash_table[bit >> 4] |= (1 << bit);
1318 bit = (ether_crc_le(4, ha->addr) >> 3) & 0x3f;
1319 hash_table[bit >> 4] |= (1 << bit);
1320 bit = (ether_crc_le(5, ha->addr) >> 3) & 0x3f;
1321 hash_table[bit >> 4] |= (1 << bit);
1323 bit = (ether_crc_le(6, ha->addr) >> 3) & 0x3f;
1324 hash_table[bit >> 4] |= (1 << bit);
1326 /* Copy the hash table to the chip. */
1327 for (i = 0; i < 4; i++)
1328 iowrite16(hash_table[i], ioaddr + HashTbl + i*2);
1329 iowrite16(0x0003, ioaddr + AddrMode);
1330 } else { /* Normal, unicast/broadcast-only mode. */
1331 iowrite16(0x0001, ioaddr + AddrMode);
1333 /* Restart the Rx process. */
1334 iowrite16(cfg_value | 0x1000, ioaddr + Cnfg);
1337 static void yellowfin_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1339 struct yellowfin_private *np = netdev_priv(dev);
1341 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1342 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1343 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
1346 static const struct ethtool_ops ethtool_ops = {
1347 .get_drvinfo = yellowfin_get_drvinfo
1350 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1352 struct yellowfin_private *np = netdev_priv(dev);
1353 void __iomem *ioaddr = np->base;
1354 struct mii_ioctl_data *data = if_mii(rq);
1357 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1358 data->phy_id = np->phys[0] & 0x1f;
1361 case SIOCGMIIREG: /* Read MII PHY register. */
1362 data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);
1365 case SIOCSMIIREG: /* Write MII PHY register. */
1366 if (data->phy_id == np->phys[0]) {
1367 u16 value = data->val_in;
1368 switch (data->reg_num) {
1370 /* Check for autonegotiation on or reset. */
1371 np->medialock = (value & 0x9000) ? 0 : 1;
1373 np->full_duplex = (value & 0x0100) ? 1 : 0;
1375 case 4: np->advertising = value; break;
1377 /* Perhaps check_duplex(dev), depending on chip semantics. */
1379 mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1387 static void yellowfin_remove_one(struct pci_dev *pdev)
1389 struct net_device *dev = pci_get_drvdata(pdev);
1390 struct yellowfin_private *np;
1393 np = netdev_priv(dev);
1395 dma_free_coherent(&pdev->dev, STATUS_TOTAL_SIZE, np->tx_status,
1397 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring,
1399 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring,
1401 unregister_netdev (dev);
1403 pci_iounmap(pdev, np->base);
1405 pci_release_regions (pdev);
1411 static struct pci_driver yellowfin_driver = {
1413 .id_table = yellowfin_pci_tbl,
1414 .probe = yellowfin_init_one,
1415 .remove = yellowfin_remove_one,
1419 static int __init yellowfin_init (void)
1421 /* when a module, this is printed whether or not devices are found in probe */
1425 return pci_register_driver(&yellowfin_driver);
1429 static void __exit yellowfin_cleanup (void)
1431 pci_unregister_driver (&yellowfin_driver);
1435 module_init(yellowfin_init);
1436 module_exit(yellowfin_cleanup);