drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c

   1 /*
   2  * Copyright (C) 1999 - 2010 Intel Corporation.
   3  * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD.
   4  *
   5  * This code was derived from the Intel e1000e Linux driver.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "pch_gbe.h"
  21 #include "pch_gbe_api.h"
  22 #include <linux/module.h>
  23 #include <linux/net_tstamp.h>
  24 #include <linux/ptp_classify.h>
  25 #include <linux/gpio.h>
  26
  27 #define DRV_VERSION     "1.01"
  28 const char pch_driver_version[] = DRV_VERSION;
  29
  30 #define PCI_DEVICE_ID_INTEL_IOH1_GBE    0x8802          /* Pci device ID */
  31 #define PCH_GBE_MAR_ENTRIES             16
  32 #define PCH_GBE_SHORT_PKT               64
  33 #define DSC_INIT16                      0xC000
  34 #define PCH_GBE_DMA_ALIGN               0
  35 #define PCH_GBE_DMA_PADDING             2
  36 #define PCH_GBE_WATCHDOG_PERIOD         (5 * HZ)        /* watchdog time */
  37 #define PCH_GBE_COPYBREAK_DEFAULT       256
  38 #define PCH_GBE_PCI_BAR                 1
  39 #define PCH_GBE_RESERVE_MEMORY          0x200000        /* 2MB */
  40
  41 /* Macros for ML7223 */
  42 #define PCI_VENDOR_ID_ROHM                      0x10db
  43 #define PCI_DEVICE_ID_ROHM_ML7223_GBE           0x8013
  44
  45 /* Macros for ML7831 */
  46 #define PCI_DEVICE_ID_ROHM_ML7831_GBE           0x8802
  47
  48 #define PCH_GBE_TX_WEIGHT         64
  49 #define PCH_GBE_RX_WEIGHT         64
  50 #define PCH_GBE_RX_BUFFER_WRITE   16
  51
  52 /* Initialize the wake-on-LAN settings */
  53 #define PCH_GBE_WL_INIT_SETTING    (PCH_GBE_WLC_MP)
  54
  55 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
  56         PCH_GBE_CHIP_TYPE_INTERNAL | \
  57         PCH_GBE_RGMII_MODE_RGMII     \
  58         )
  59
  60 /* Ethertype field values */
  61 #define PCH_GBE_MAX_RX_BUFFER_SIZE      0x2880
  62 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE    10318
  63 #define PCH_GBE_FRAME_SIZE_2048         2048
  64 #define PCH_GBE_FRAME_SIZE_4096         4096
  65 #define PCH_GBE_FRAME_SIZE_8192         8192
  66
  67 #define PCH_GBE_GET_DESC(R, i, type)    (&(((struct type *)((R).desc))[i]))
  68 #define PCH_GBE_RX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
  69 #define PCH_GBE_TX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
  70 #define PCH_GBE_DESC_UNUSED(R) \
  71         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  72         (R)->next_to_clean - (R)->next_to_use - 1)
  73
  74 /* Pause packet value */
  75 #define PCH_GBE_PAUSE_PKT1_VALUE    0x00C28001
  76 #define PCH_GBE_PAUSE_PKT2_VALUE    0x00000100
  77 #define PCH_GBE_PAUSE_PKT4_VALUE    0x01000888
  78 #define PCH_GBE_PAUSE_PKT5_VALUE    0x0000FFFF
  79
  80
  81 /* This defines the bits that are set in the Interrupt Mask
  82  * Set/Read Register.  Each bit is documented below:
  83  *   o RXT0   = Receiver Timer Interrupt (ring 0)
  84  *   o TXDW   = Transmit Descriptor Written Back
  85  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
  86  *   o RXSEQ  = Receive Sequence Error
  87  *   o LSC    = Link Status Change
  88  */
  89 #define PCH_GBE_INT_ENABLE_MASK ( \
  90         PCH_GBE_INT_RX_DMA_CMPLT |    \
  91         PCH_GBE_INT_RX_DSC_EMP   |    \
  92         PCH_GBE_INT_RX_FIFO_ERR  |    \
  93         PCH_GBE_INT_WOL_DET      |    \
  94         PCH_GBE_INT_TX_CMPLT          \
  95         )
  96
  97 #define PCH_GBE_INT_DISABLE_ALL         0
  98
  99 /* Macros for ieee1588 */
 100 /* 0x40 Time Synchronization Channel Control Register Bits */
 101 #define MASTER_MODE   (1<<0)
 102 #define SLAVE_MODE    (0)
 103 #define V2_MODE       (1<<31)
 104 #define CAP_MODE0     (0)
 105 #define CAP_MODE2     (1<<17)
 106
 107 /* 0x44 Time Synchronization Channel Event Register Bits */
 108 #define TX_SNAPSHOT_LOCKED (1<<0)
 109 #define RX_SNAPSHOT_LOCKED (1<<1)
 110
 111 #define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81"
 112 #define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00"
 113
 114 #define MINNOW_PHY_RESET_GPIO           13
 115
 116 static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
 117
 118 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
 119 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
 120                                int data);
 121 static void pch_gbe_set_multi(struct net_device *netdev);
 122
 123 static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
 124 {
 125         u8 *data = skb->data;
 126         unsigned int offset;
 127         u16 hi, id;
 128         u32 lo;
 129
 130         if (ptp_classify_raw(skb) == PTP_CLASS_NONE)
 131                 return 0;
 132
 133         offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
 134
 135         if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
 136                 return 0;
 137
 138         hi = get_unaligned_be16(data + offset + OFF_PTP_SOURCE_UUID + 0);
 139         lo = get_unaligned_be32(data + offset + OFF_PTP_SOURCE_UUID + 2);
 140         id = get_unaligned_be16(data + offset + OFF_PTP_SEQUENCE_ID);
 141
 142         return (uid_hi == hi && uid_lo == lo && seqid == id);
 143 }
 144
 145 static void
 146 pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
 147 {
 148         struct skb_shared_hwtstamps *shhwtstamps;
 149         struct pci_dev *pdev;
 150         u64 ns;
 151         u32 hi, lo, val;
 152
 153         if (!adapter->hwts_rx_en)
 154                 return;
 155
 156         /* Get ieee1588's dev information */
 157         pdev = adapter->ptp_pdev;
 158
 159         val = pch_ch_event_read(pdev);
 160
 161         if (!(val & RX_SNAPSHOT_LOCKED))
 162                 return;
 163
 164         lo = pch_src_uuid_lo_read(pdev);
 165         hi = pch_src_uuid_hi_read(pdev);
 166
 167         if (!pch_ptp_match(skb, hi, lo, hi >> 16))
 168                 goto out;
 169
 170         ns = pch_rx_snap_read(pdev);
 171
 172         shhwtstamps = skb_hwtstamps(skb);
 173         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 174         shhwtstamps->hwtstamp = ns_to_ktime(ns);
 175 out:
 176         pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED);
 177 }
 178
 179 static void
 180 pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
 181 {
 182         struct skb_shared_hwtstamps shhwtstamps;
 183         struct pci_dev *pdev;
 184         struct skb_shared_info *shtx;
 185         u64 ns;
 186         u32 cnt, val;
 187
 188         shtx = skb_shinfo(skb);
 189         if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en)))
 190                 return;
 191
 192         shtx->tx_flags |= SKBTX_IN_PROGRESS;
 193
 194         /* Get ieee1588's dev information */
 195         pdev = adapter->ptp_pdev;
 196
 197         /*
 198          * This really stinks, but we have to poll for the Tx time stamp.
 199          */
 200         for (cnt = 0; cnt < 100; cnt++) {
 201                 val = pch_ch_event_read(pdev);
 202                 if (val & TX_SNAPSHOT_LOCKED)
 203                         break;
 204                 udelay(1);
 205         }
 206         if (!(val & TX_SNAPSHOT_LOCKED)) {
 207                 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
 208                 return;
 209         }
 210
 211         ns = pch_tx_snap_read(pdev);
 212
 213         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 214         shhwtstamps.hwtstamp = ns_to_ktime(ns);
 215         skb_tstamp_tx(skb, &shhwtstamps);
 216
 217         pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED);
 218 }
 219
 220 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
 221 {
 222         struct hwtstamp_config cfg;
 223         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 224         struct pci_dev *pdev;
 225         u8 station[20];
 226
 227         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
 228                 return -EFAULT;
 229
 230         if (cfg.flags) /* reserved for future extensions */
 231                 return -EINVAL;
 232
 233         /* Get ieee1588's dev information */
 234         pdev = adapter->ptp_pdev;
 235
 236         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
 237                 return -ERANGE;
 238
 239         switch (cfg.rx_filter) {
 240         case HWTSTAMP_FILTER_NONE:
 241                 adapter->hwts_rx_en = 0;
 242                 break;
 243         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 244                 adapter->hwts_rx_en = 0;
 245                 pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0);
 246                 break;
 247         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 248                 adapter->hwts_rx_en = 1;
 249                 pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0);
 250                 break;
 251         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 252                 adapter->hwts_rx_en = 1;
 253                 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
 254                 strcpy(station, PTP_L4_MULTICAST_SA);
 255                 pch_set_station_address(station, pdev);
 256                 break;
 257         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 258                 adapter->hwts_rx_en = 1;
 259                 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
 260                 strcpy(station, PTP_L2_MULTICAST_SA);
 261                 pch_set_station_address(station, pdev);
 262                 break;
 263         default:
 264                 return -ERANGE;
 265         }
 266
 267         adapter->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
 268
 269         /* Clear out any old time stamps. */
 270         pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED);
 271
 272         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
 273 }
 274
 275 static inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
 276 {
 277         iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
 278 }
 279
 280 /**
 281  * pch_gbe_mac_read_mac_addr - Read MAC address
 282  * @hw:             Pointer to the HW structure
 283  * Returns:
 284  *      0:                      Successful.
 285  */
 286 s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
 287 {
 288         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 289         u32  adr1a, adr1b;
 290
 291         adr1a = ioread32(&hw->reg->mac_adr[0].high);
 292         adr1b = ioread32(&hw->reg->mac_adr[0].low);
 293
 294         hw->mac.addr[0] = (u8)(adr1a & 0xFF);
 295         hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
 296         hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
 297         hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
 298         hw->mac.addr[4] = (u8)(adr1b & 0xFF);
 299         hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
 300
 301         netdev_dbg(adapter->netdev, "hw->mac.addr : %pM\n", hw->mac.addr);
 302         return 0;
 303 }
 304
 305 /**
 306  * pch_gbe_wait_clr_bit - Wait to clear a bit
 307  * @reg:        Pointer of register
 308  * @busy:       Busy bit
 309  */
 310 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
 311 {
 312         u32 tmp;
 313
 314         /* wait busy */
 315         tmp = 1000;
 316         while ((ioread32(reg) & bit) && --tmp)
 317                 cpu_relax();
 318         if (!tmp)
 319                 pr_err("Error: busy bit is not cleared\n");
 320 }
 321
 322 /**
 323  * pch_gbe_mac_mar_set - Set MAC address register
 324  * @hw:     Pointer to the HW structure
 325  * @addr:   Pointer to the MAC address
 326  * @index:  MAC address array register
 327  */
 328 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
 329 {
 330         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 331         u32 mar_low, mar_high, adrmask;
 332
 333         netdev_dbg(adapter->netdev, "index : 0x%x\n", index);
 334
 335         /*
 336          * HW expects these in little endian so we reverse the byte order
 337          * from network order (big endian) to little endian
 338          */
 339         mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
 340                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 341         mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
 342         /* Stop the MAC Address of index. */
 343         adrmask = ioread32(&hw->reg->ADDR_MASK);
 344         iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
 345         /* wait busy */
 346         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 347         /* Set the MAC address to the MAC address 1A/1B register */
 348         iowrite32(mar_high, &hw->reg->mac_adr[index].high);
 349         iowrite32(mar_low, &hw->reg->mac_adr[index].low);
 350         /* Start the MAC address of index */
 351         iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
 352         /* wait busy */
 353         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 354 }
 355
 356 /**
 357  * pch_gbe_mac_reset_hw - Reset hardware
 358  * @hw: Pointer to the HW structure
 359  */
 360 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
 361 {
 362         /* Read the MAC address. and store to the private data */
 363         pch_gbe_mac_read_mac_addr(hw);
 364         iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
 365 #ifdef PCH_GBE_MAC_IFOP_RGMII
 366         iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
 367 #endif
 368         pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
 369         /* Setup the receive addresses */
 370         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
 371         return;
 372 }
 373
 374 static void pch_gbe_disable_mac_rx(struct pch_gbe_hw *hw)
 375 {
 376         u32 rctl;
 377         /* Disables Receive MAC */
 378         rctl = ioread32(&hw->reg->MAC_RX_EN);
 379         iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
 380 }
 381
 382 static void pch_gbe_enable_mac_rx(struct pch_gbe_hw *hw)
 383 {
 384         u32 rctl;
 385         /* Enables Receive MAC */
 386         rctl = ioread32(&hw->reg->MAC_RX_EN);
 387         iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
 388 }
 389
 390 /**
 391  * pch_gbe_mac_init_rx_addrs - Initialize receive address's
 392  * @hw: Pointer to the HW structure
 393  * @mar_count: Receive address registers
 394  */
 395 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
 396 {
 397         u32 i;
 398
 399         /* Setup the receive address */
 400         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
 401
 402         /* Zero out the other receive addresses */
 403         for (i = 1; i < mar_count; i++) {
 404                 iowrite32(0, &hw->reg->mac_adr[i].high);
 405                 iowrite32(0, &hw->reg->mac_adr[i].low);
 406         }
 407         iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
 408         /* wait busy */
 409         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 410 }
 411
 412
 413 /**
 414  * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
 415  * @hw:             Pointer to the HW structure
 416  * @mc_addr_list:   Array of multicast addresses to program
 417  * @mc_addr_count:  Number of multicast addresses to program
 418  * @mar_used_count: The first MAC Address register free to program
 419  * @mar_total_num:  Total number of supported MAC Address Registers
 420  */
 421 static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
 422                                             u8 *mc_addr_list, u32 mc_addr_count,
 423                                             u32 mar_used_count, u32 mar_total_num)
 424 {
 425         u32 i, adrmask;
 426
 427         /* Load the first set of multicast addresses into the exact
 428          * filters (RAR).  If there are not enough to fill the RAR
 429          * array, clear the filters.
 430          */
 431         for (i = mar_used_count; i < mar_total_num; i++) {
 432                 if (mc_addr_count) {
 433                         pch_gbe_mac_mar_set(hw, mc_addr_list, i);
 434                         mc_addr_count--;
 435                         mc_addr_list += ETH_ALEN;
 436                 } else {
 437                         /* Clear MAC address mask */
 438                         adrmask = ioread32(&hw->reg->ADDR_MASK);
 439                         iowrite32((adrmask | (0x0001 << i)),
 440                                         &hw->reg->ADDR_MASK);
 441                         /* wait busy */
 442                         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 443                         /* Clear MAC address */
 444                         iowrite32(0, &hw->reg->mac_adr[i].high);
 445                         iowrite32(0, &hw->reg->mac_adr[i].low);
 446                 }
 447         }
 448 }
 449
 450 /**
 451  * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
 452  * @hw:             Pointer to the HW structure
 453  * Returns:
 454  *      0:                      Successful.
 455  *      Negative value:         Failed.
 456  */
 457 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
 458 {
 459         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 460         struct pch_gbe_mac_info *mac = &hw->mac;
 461         u32 rx_fctrl;
 462
 463         netdev_dbg(adapter->netdev, "mac->fc = %u\n", mac->fc);
 464
 465         rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
 466
 467         switch (mac->fc) {
 468         case PCH_GBE_FC_NONE:
 469                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 470                 mac->tx_fc_enable = false;
 471                 break;
 472         case PCH_GBE_FC_RX_PAUSE:
 473                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
 474                 mac->tx_fc_enable = false;
 475                 break;
 476         case PCH_GBE_FC_TX_PAUSE:
 477                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 478                 mac->tx_fc_enable = true;
 479                 break;
 480         case PCH_GBE_FC_FULL:
 481                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
 482                 mac->tx_fc_enable = true;
 483                 break;
 484         default:
 485                 netdev_err(adapter->netdev,
 486                            "Flow control param set incorrectly\n");
 487                 return -EINVAL;
 488         }
 489         if (mac->link_duplex == DUPLEX_HALF)
 490                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 491         iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
 492         netdev_dbg(adapter->netdev,
 493                    "RX_FCTRL reg : 0x%08x  mac->tx_fc_enable : %d\n",
 494                    ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
 495         return 0;
 496 }
 497
 498 /**
 499  * pch_gbe_mac_set_wol_event - Set wake-on-lan event
 500  * @hw:     Pointer to the HW structure
 501  * @wu_evt: Wake up event
 502  */
 503 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
 504 {
 505         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 506         u32 addr_mask;
 507
 508         netdev_dbg(adapter->netdev, "wu_evt : 0x%08x  ADDR_MASK reg : 0x%08x\n",
 509                    wu_evt, ioread32(&hw->reg->ADDR_MASK));
 510
 511         if (wu_evt) {
 512                 /* Set Wake-On-Lan address mask */
 513                 addr_mask = ioread32(&hw->reg->ADDR_MASK);
 514                 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
 515                 /* wait busy */
 516                 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
 517                 iowrite32(0, &hw->reg->WOL_ST);
 518                 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
 519                 iowrite32(0x02, &hw->reg->TCPIP_ACC);
 520                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
 521         } else {
 522                 iowrite32(0, &hw->reg->WOL_CTRL);
 523                 iowrite32(0, &hw->reg->WOL_ST);
 524         }
 525         return;
 526 }
 527
 528 /**
 529  * pch_gbe_mac_ctrl_miim - Control MIIM interface
 530  * @hw:   Pointer to the HW structure
 531  * @addr: Address of PHY
 532  * @dir:  Operetion. (Write or Read)
 533  * @reg:  Access register of PHY
 534  * @data: Write data.
 535  *
 536  * Returns: Read date.
 537  */
 538 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
 539                         u16 data)
 540 {
 541         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 542         u32 data_out = 0;
 543         unsigned int i;
 544         unsigned long flags;
 545
 546         spin_lock_irqsave(&hw->miim_lock, flags);
 547
 548         for (i = 100; i; --i) {
 549                 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
 550                         break;
 551                 udelay(20);
 552         }
 553         if (i == 0) {
 554                 netdev_err(adapter->netdev, "pch-gbe.miim won't go Ready\n");
 555                 spin_unlock_irqrestore(&hw->miim_lock, flags);
 556                 return 0;       /* No way to indicate timeout error */
 557         }
 558         iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
 559                   (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
 560                   dir | data), &hw->reg->MIIM);
 561         for (i = 0; i < 100; i++) {
 562                 udelay(20);
 563                 data_out = ioread32(&hw->reg->MIIM);
 564                 if ((data_out & PCH_GBE_MIIM_OPER_READY))
 565                         break;
 566         }
 567         spin_unlock_irqrestore(&hw->miim_lock, flags);
 568
 569         netdev_dbg(adapter->netdev, "PHY %s: reg=%d, data=0x%04X\n",
 570                    dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
 571                    dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
 572         return (u16) data_out;
 573 }
 574
 575 /**
 576  * pch_gbe_mac_set_pause_packet - Set pause packet
 577  * @hw:   Pointer to the HW structure
 578  */
 579 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
 580 {
 581         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 582         unsigned long tmp2, tmp3;
 583
 584         /* Set Pause packet */
 585         tmp2 = hw->mac.addr[1];
 586         tmp2 = (tmp2 << 8) | hw->mac.addr[0];
 587         tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
 588
 589         tmp3 = hw->mac.addr[5];
 590         tmp3 = (tmp3 << 8) | hw->mac.addr[4];
 591         tmp3 = (tmp3 << 8) | hw->mac.addr[3];
 592         tmp3 = (tmp3 << 8) | hw->mac.addr[2];
 593
 594         iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
 595         iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
 596         iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
 597         iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
 598         iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
 599
 600         /* Transmit Pause Packet */
 601         iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
 602
 603         netdev_dbg(adapter->netdev,
 604                    "PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
 605                    ioread32(&hw->reg->PAUSE_PKT1),
 606                    ioread32(&hw->reg->PAUSE_PKT2),
 607                    ioread32(&hw->reg->PAUSE_PKT3),
 608                    ioread32(&hw->reg->PAUSE_PKT4),
 609                    ioread32(&hw->reg->PAUSE_PKT5));
 610
 611         return;
 612 }
 613
 614
 615 /**
 616  * pch_gbe_alloc_queues - Allocate memory for all rings
 617  * @adapter:  Board private structure to initialize
 618  * Returns:
 619  *      0:      Successfully
 620  *      Negative value: Failed
 621  */
 622 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
 623 {
 624         adapter->tx_ring = devm_kzalloc(&adapter->pdev->dev,
 625                                         sizeof(*adapter->tx_ring), GFP_KERNEL);
 626         if (!adapter->tx_ring)
 627                 return -ENOMEM;
 628
 629         adapter->rx_ring = devm_kzalloc(&adapter->pdev->dev,
 630                                         sizeof(*adapter->rx_ring), GFP_KERNEL);
 631         if (!adapter->rx_ring)
 632                 return -ENOMEM;
 633         return 0;
 634 }
 635
 636 /**
 637  * pch_gbe_init_stats - Initialize status
 638  * @adapter:  Board private structure to initialize
 639  */
 640 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
 641 {
 642         memset(&adapter->stats, 0, sizeof(adapter->stats));
 643         return;
 644 }
 645
 646 /**
 647  * pch_gbe_init_phy - Initialize PHY
 648  * @adapter:  Board private structure to initialize
 649  * Returns:
 650  *      0:      Successfully
 651  *      Negative value: Failed
 652  */
 653 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
 654 {
 655         struct net_device *netdev = adapter->netdev;
 656         u32 addr;
 657         u16 bmcr, stat;
 658
 659         /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
 660         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
 661                 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
 662                 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
 663                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
 664                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
 665                 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
 666                         break;
 667         }
 668         adapter->hw.phy.addr = adapter->mii.phy_id;
 669         netdev_dbg(netdev, "phy_addr = %d\n", adapter->mii.phy_id);
 670         if (addr == PCH_GBE_PHY_REGS_LEN)
 671                 return -EAGAIN;
 672         /* Selected the phy and isolate the rest */
 673         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
 674                 if (addr != adapter->mii.phy_id) {
 675                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
 676                                            BMCR_ISOLATE);
 677                 } else {
 678                         bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
 679                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
 680                                            bmcr & ~BMCR_ISOLATE);
 681                 }
 682         }
 683
 684         /* MII setup */
 685         adapter->mii.phy_id_mask = 0x1F;
 686         adapter->mii.reg_num_mask = 0x1F;
 687         adapter->mii.dev = adapter->netdev;
 688         adapter->mii.mdio_read = pch_gbe_mdio_read;
 689         adapter->mii.mdio_write = pch_gbe_mdio_write;
 690         adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
 691         return 0;
 692 }
 693
 694 /**
 695  * pch_gbe_mdio_read - The read function for mii
 696  * @netdev: Network interface device structure
 697  * @addr:   Phy ID
 698  * @reg:    Access location
 699  * Returns:
 700  *      0:      Successfully
 701  *      Negative value: Failed
 702  */
 703 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
 704 {
 705         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 706         struct pch_gbe_hw *hw = &adapter->hw;
 707
 708         return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
 709                                      (u16) 0);
 710 }
 711
 712 /**
 713  * pch_gbe_mdio_write - The write function for mii
 714  * @netdev: Network interface device structure
 715  * @addr:   Phy ID (not used)
 716  * @reg:    Access location
 717  * @data:   Write data
 718  */
 719 static void pch_gbe_mdio_write(struct net_device *netdev,
 720                                int addr, int reg, int data)
 721 {
 722         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 723         struct pch_gbe_hw *hw = &adapter->hw;
 724
 725         pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
 726 }
 727
 728 /**
 729  * pch_gbe_reset_task - Reset processing at the time of transmission timeout
 730  * @work:  Pointer of board private structure
 731  */
 732 static void pch_gbe_reset_task(struct work_struct *work)
 733 {
 734         struct pch_gbe_adapter *adapter;
 735         adapter = container_of(work, struct pch_gbe_adapter, reset_task);
 736
 737         rtnl_lock();
 738         pch_gbe_reinit_locked(adapter);
 739         rtnl_unlock();
 740 }
 741
 742 /**
 743  * pch_gbe_reinit_locked- Re-initialization
 744  * @adapter:  Board private structure
 745  */
 746 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
 747 {
 748         pch_gbe_down(adapter);
 749         pch_gbe_up(adapter);
 750 }
 751
 752 /**
 753  * pch_gbe_reset - Reset GbE
 754  * @adapter:  Board private structure
 755  */
 756 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
 757 {
 758         struct net_device *netdev = adapter->netdev;
 759
 760         pch_gbe_mac_reset_hw(&adapter->hw);
 761         /* reprogram multicast address register after reset */
 762         pch_gbe_set_multi(netdev);
 763         /* Setup the receive address. */
 764         pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
 765         if (pch_gbe_hal_init_hw(&adapter->hw))
 766                 netdev_err(netdev, "Hardware Error\n");
 767 }
 768
 769 /**
 770  * pch_gbe_free_irq - Free an interrupt
 771  * @adapter:  Board private structure
 772  */
 773 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
 774 {
 775         struct net_device *netdev = adapter->netdev;
 776
 777         free_irq(adapter->pdev->irq, netdev);
 778         if (adapter->have_msi) {
 779                 pci_disable_msi(adapter->pdev);
 780                 netdev_dbg(netdev, "call pci_disable_msi\n");
 781         }
 782 }
 783
 784 /**
 785  * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
 786  * @adapter:  Board private structure
 787  */
 788 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
 789 {
 790         struct pch_gbe_hw *hw = &adapter->hw;
 791
 792         atomic_inc(&adapter->irq_sem);
 793         iowrite32(0, &hw->reg->INT_EN);
 794         ioread32(&hw->reg->INT_ST);
 795         synchronize_irq(adapter->pdev->irq);
 796
 797         netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
 798                    ioread32(&hw->reg->INT_EN));
 799 }
 800
 801 /**
 802  * pch_gbe_irq_enable - Enable default interrupt generation settings
 803  * @adapter:  Board private structure
 804  */
 805 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
 806 {
 807         struct pch_gbe_hw *hw = &adapter->hw;
 808
 809         if (likely(atomic_dec_and_test(&adapter->irq_sem)))
 810                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
 811         ioread32(&hw->reg->INT_ST);
 812         netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
 813                    ioread32(&hw->reg->INT_EN));
 814 }
 815
 816
 817
 818 /**
 819  * pch_gbe_setup_tctl - configure the Transmit control registers
 820  * @adapter:  Board private structure
 821  */
 822 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
 823 {
 824         struct pch_gbe_hw *hw = &adapter->hw;
 825         u32 tx_mode, tcpip;
 826
 827         tx_mode = PCH_GBE_TM_LONG_PKT |
 828                 PCH_GBE_TM_ST_AND_FD |
 829                 PCH_GBE_TM_SHORT_PKT |
 830                 PCH_GBE_TM_TH_TX_STRT_8 |
 831                 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
 832
 833         iowrite32(tx_mode, &hw->reg->TX_MODE);
 834
 835         tcpip = ioread32(&hw->reg->TCPIP_ACC);
 836         tcpip |= PCH_GBE_TX_TCPIPACC_EN;
 837         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
 838         return;
 839 }
 840
 841 /**
 842  * pch_gbe_configure_tx - Configure Transmit Unit after Reset
 843  * @adapter:  Board private structure
 844  */
 845 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
 846 {
 847         struct pch_gbe_hw *hw = &adapter->hw;
 848         u32 tdba, tdlen, dctrl;
 849
 850         netdev_dbg(adapter->netdev, "dma addr = 0x%08llx  size = 0x%08x\n",
 851                    (unsigned long long)adapter->tx_ring->dma,
 852                    adapter->tx_ring->size);
 853
 854         /* Setup the HW Tx Head and Tail descriptor pointers */
 855         tdba = adapter->tx_ring->dma;
 856         tdlen = adapter->tx_ring->size - 0x10;
 857         iowrite32(tdba, &hw->reg->TX_DSC_BASE);
 858         iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
 859         iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
 860
 861         /* Enables Transmission DMA */
 862         dctrl = ioread32(&hw->reg->DMA_CTRL);
 863         dctrl |= PCH_GBE_TX_DMA_EN;
 864         iowrite32(dctrl, &hw->reg->DMA_CTRL);
 865 }
 866
 867 /**
 868  * pch_gbe_setup_rctl - Configure the receive control registers
 869  * @adapter:  Board private structure
 870  */
 871 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
 872 {
 873         struct pch_gbe_hw *hw = &adapter->hw;
 874         u32 rx_mode, tcpip;
 875
 876         rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
 877         PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
 878
 879         iowrite32(rx_mode, &hw->reg->RX_MODE);
 880
 881         tcpip = ioread32(&hw->reg->TCPIP_ACC);
 882
 883         tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
 884         tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
 885         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
 886         return;
 887 }
 888
 889 /**
 890  * pch_gbe_configure_rx - Configure Receive Unit after Reset
 891  * @adapter:  Board private structure
 892  */
 893 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
 894 {
 895         struct pch_gbe_hw *hw = &adapter->hw;
 896         u32 rdba, rdlen, rxdma;
 897
 898         netdev_dbg(adapter->netdev, "dma adr = 0x%08llx  size = 0x%08x\n",
 899                    (unsigned long long)adapter->rx_ring->dma,
 900                    adapter->rx_ring->size);
 901
 902         pch_gbe_mac_force_mac_fc(hw);
 903
 904         pch_gbe_disable_mac_rx(hw);
 905
 906         /* Disables Receive DMA */
 907         rxdma = ioread32(&hw->reg->DMA_CTRL);
 908         rxdma &= ~PCH_GBE_RX_DMA_EN;
 909         iowrite32(rxdma, &hw->reg->DMA_CTRL);
 910
 911         netdev_dbg(adapter->netdev,
 912                    "MAC_RX_EN reg = 0x%08x  DMA_CTRL reg = 0x%08x\n",
 913                    ioread32(&hw->reg->MAC_RX_EN),
 914                    ioread32(&hw->reg->DMA_CTRL));
 915
 916         /* Setup the HW Rx Head and Tail Descriptor Pointers and
 917          * the Base and Length of the Rx Descriptor Ring */
 918         rdba = adapter->rx_ring->dma;
 919         rdlen = adapter->rx_ring->size - 0x10;
 920         iowrite32(rdba, &hw->reg->RX_DSC_BASE);
 921         iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
 922         iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
 923 }
 924
 925 /**
 926  * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
 927  * @adapter:     Board private structure
 928  * @buffer_info: Buffer information structure
 929  */
 930 static void pch_gbe_unmap_and_free_tx_resource(
 931         struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
 932 {
 933         if (buffer_info->mapped) {
 934                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
 935                                  buffer_info->length, DMA_TO_DEVICE);
 936                 buffer_info->mapped = false;
 937         }
 938         if (buffer_info->skb) {
 939                 dev_kfree_skb_any(buffer_info->skb);
 940                 buffer_info->skb = NULL;
 941         }
 942 }
 943
 944 /**
 945  * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
 946  * @adapter:      Board private structure
 947  * @buffer_info:  Buffer information structure
 948  */
 949 static void pch_gbe_unmap_and_free_rx_resource(
 950                                         struct pch_gbe_adapter *adapter,
 951                                         struct pch_gbe_buffer *buffer_info)
 952 {
 953         if (buffer_info->mapped) {
 954                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
 955                                  buffer_info->length, DMA_FROM_DEVICE);
 956                 buffer_info->mapped = false;
 957         }
 958         if (buffer_info->skb) {
 959                 dev_kfree_skb_any(buffer_info->skb);
 960                 buffer_info->skb = NULL;
 961         }
 962 }
 963
 964 /**
 965  * pch_gbe_clean_tx_ring - Free Tx Buffers
 966  * @adapter:  Board private structure
 967  * @tx_ring:  Ring to be cleaned
 968  */
 969 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
 970                                    struct pch_gbe_tx_ring *tx_ring)
 971 {
 972         struct pch_gbe_hw *hw = &adapter->hw;
 973         struct pch_gbe_buffer *buffer_info;
 974         unsigned long size;
 975         unsigned int i;
 976
 977         /* Free all the Tx ring sk_buffs */
 978         for (i = 0; i < tx_ring->count; i++) {
 979                 buffer_info = &tx_ring->buffer_info[i];
 980                 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
 981         }
 982         netdev_dbg(adapter->netdev,
 983                    "call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
 984
 985         size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
 986         memset(tx_ring->buffer_info, 0, size);
 987
 988         /* Zero out the descriptor ring */
 989         memset(tx_ring->desc, 0, tx_ring->size);
 990         tx_ring->next_to_use = 0;
 991         tx_ring->next_to_clean = 0;
 992         iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
 993         iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
 994 }
 995
 996 /**
 997  * pch_gbe_clean_rx_ring - Free Rx Buffers
 998  * @adapter:  Board private structure
 999  * @rx_ring:  Ring to free buffers from
1000  */
1001 static void
1002 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
1003                       struct pch_gbe_rx_ring *rx_ring)
1004 {
1005         struct pch_gbe_hw *hw = &adapter->hw;
1006         struct pch_gbe_buffer *buffer_info;
1007         unsigned long size;
1008         unsigned int i;
1009
1010         /* Free all the Rx ring sk_buffs */
1011         for (i = 0; i < rx_ring->count; i++) {
1012                 buffer_info = &rx_ring->buffer_info[i];
1013                 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
1014         }
1015         netdev_dbg(adapter->netdev,
1016                    "call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
1017         size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1018         memset(rx_ring->buffer_info, 0, size);
1019
1020         /* Zero out the descriptor ring */
1021         memset(rx_ring->desc, 0, rx_ring->size);
1022         rx_ring->next_to_clean = 0;
1023         rx_ring->next_to_use = 0;
1024         iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
1025         iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
1026 }
1027
1028 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
1029                                     u16 duplex)
1030 {
1031         struct pch_gbe_hw *hw = &adapter->hw;
1032         unsigned long rgmii = 0;
1033
1034         /* Set the RGMII control. */
1035 #ifdef PCH_GBE_MAC_IFOP_RGMII
1036         switch (speed) {
1037         case SPEED_10:
1038                 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
1039                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
1040                 break;
1041         case SPEED_100:
1042                 rgmii = (PCH_GBE_RGMII_RATE_25M |
1043                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
1044                 break;
1045         case SPEED_1000:
1046                 rgmii = (PCH_GBE_RGMII_RATE_125M |
1047                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
1048                 break;
1049         }
1050         iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1051 #else   /* GMII */
1052         rgmii = 0;
1053         iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1054 #endif
1055 }
1056 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
1057                               u16 duplex)
1058 {
1059         struct net_device *netdev = adapter->netdev;
1060         struct pch_gbe_hw *hw = &adapter->hw;
1061         unsigned long mode = 0;
1062
1063         /* Set the communication mode */
1064         switch (speed) {
1065         case SPEED_10:
1066                 mode = PCH_GBE_MODE_MII_ETHER;
1067                 netdev->tx_queue_len = 10;
1068                 break;
1069         case SPEED_100:
1070                 mode = PCH_GBE_MODE_MII_ETHER;
1071                 netdev->tx_queue_len = 100;
1072                 break;
1073         case SPEED_1000:
1074                 mode = PCH_GBE_MODE_GMII_ETHER;
1075                 break;
1076         }
1077         if (duplex == DUPLEX_FULL)
1078                 mode |= PCH_GBE_MODE_FULL_DUPLEX;
1079         else
1080                 mode |= PCH_GBE_MODE_HALF_DUPLEX;
1081         iowrite32(mode, &hw->reg->MODE);
1082 }
1083
1084 /**
1085  * pch_gbe_watchdog - Watchdog process
1086  * @data:  Board private structure
1087  */
1088 static void pch_gbe_watchdog(unsigned long data)
1089 {
1090         struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
1091         struct net_device *netdev = adapter->netdev;
1092         struct pch_gbe_hw *hw = &adapter->hw;
1093
1094         netdev_dbg(netdev, "right now = %ld\n", jiffies);
1095
1096         pch_gbe_update_stats(adapter);
1097         if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
1098                 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
1099                 netdev->tx_queue_len = adapter->tx_queue_len;
1100                 /* mii library handles link maintenance tasks */
1101                 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
1102                         netdev_err(netdev, "ethtool get setting Error\n");
1103                         mod_timer(&adapter->watchdog_timer,
1104                                   round_jiffies(jiffies +
1105                                                 PCH_GBE_WATCHDOG_PERIOD));
1106                         return;
1107                 }
1108                 hw->mac.link_speed = ethtool_cmd_speed(&cmd);
1109                 hw->mac.link_duplex = cmd.duplex;
1110                 /* Set the RGMII control. */
1111                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
1112                                                 hw->mac.link_duplex);
1113                 /* Set the communication mode */
1114                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
1115                                  hw->mac.link_duplex);
1116                 netdev_dbg(netdev,
1117                            "Link is Up %d Mbps %s-Duplex\n",
1118                            hw->mac.link_speed,
1119                            cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1120                 netif_carrier_on(netdev);
1121                 netif_wake_queue(netdev);
1122         } else if ((!mii_link_ok(&adapter->mii)) &&
1123                    (netif_carrier_ok(netdev))) {
1124                 netdev_dbg(netdev, "NIC Link is Down\n");
1125                 hw->mac.link_speed = SPEED_10;
1126                 hw->mac.link_duplex = DUPLEX_HALF;
1127                 netif_carrier_off(netdev);
1128                 netif_stop_queue(netdev);
1129         }
1130         mod_timer(&adapter->watchdog_timer,
1131                   round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
1132 }
1133
1134 /**
1135  * pch_gbe_tx_queue - Carry out queuing of the transmission data
1136  * @adapter:  Board private structure
1137  * @tx_ring:  Tx descriptor ring structure
1138  * @skb:      Sockt buffer structure
1139  */
1140 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
1141                               struct pch_gbe_tx_ring *tx_ring,
1142                               struct sk_buff *skb)
1143 {
1144         struct pch_gbe_hw *hw = &adapter->hw;
1145         struct pch_gbe_tx_desc *tx_desc;
1146         struct pch_gbe_buffer *buffer_info;
1147         struct sk_buff *tmp_skb;
1148         unsigned int frame_ctrl;
1149         unsigned int ring_num;
1150
1151         /*-- Set frame control --*/
1152         frame_ctrl = 0;
1153         if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
1154                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
1155         if (skb->ip_summed == CHECKSUM_NONE)
1156                 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1157
1158         /* Performs checksum processing */
1159         /*
1160          * It is because the hardware accelerator does not support a checksum,
1161          * when the received data size is less than 64 bytes.
1162          */
1163         if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
1164                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
1165                               PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1166                 if (skb->protocol == htons(ETH_P_IP)) {
1167                         struct iphdr *iph = ip_hdr(skb);
1168                         unsigned int offset;
1169                         offset = skb_transport_offset(skb);
1170                         if (iph->protocol == IPPROTO_TCP) {
1171                                 skb->csum = 0;
1172                                 tcp_hdr(skb)->check = 0;
1173                                 skb->csum = skb_checksum(skb, offset,
1174                                                          skb->len - offset, 0);
1175                                 tcp_hdr(skb)->check =
1176                                         csum_tcpudp_magic(iph->saddr,
1177                                                           iph->daddr,
1178                                                           skb->len - offset,
1179                                                           IPPROTO_TCP,
1180                                                           skb->csum);
1181                         } else if (iph->protocol == IPPROTO_UDP) {
1182                                 skb->csum = 0;
1183                                 udp_hdr(skb)->check = 0;
1184                                 skb->csum =
1185                                         skb_checksum(skb, offset,
1186                                                      skb->len - offset, 0);
1187                                 udp_hdr(skb)->check =
1188                                         csum_tcpudp_magic(iph->saddr,
1189                                                           iph->daddr,
1190                                                           skb->len - offset,
1191                                                           IPPROTO_UDP,
1192                                                           skb->csum);
1193                         }
1194                 }
1195         }
1196
1197         ring_num = tx_ring->next_to_use;
1198         if (unlikely((ring_num + 1) == tx_ring->count))
1199                 tx_ring->next_to_use = 0;
1200         else
1201                 tx_ring->next_to_use = ring_num + 1;
1202
1203
1204         buffer_info = &tx_ring->buffer_info[ring_num];
1205         tmp_skb = buffer_info->skb;
1206
1207         /* [Header:14][payload] ---> [Header:14][paddong:2][payload]    */
1208         memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1209         tmp_skb->data[ETH_HLEN] = 0x00;
1210         tmp_skb->data[ETH_HLEN + 1] = 0x00;
1211         tmp_skb->len = skb->len;
1212         memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1213                (skb->len - ETH_HLEN));
1214         /*-- Set Buffer information --*/
1215         buffer_info->length = tmp_skb->len;
1216         buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1217                                           buffer_info->length,
1218                                           DMA_TO_DEVICE);
1219         if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1220                 netdev_err(adapter->netdev, "TX DMA map failed\n");
1221                 buffer_info->dma = 0;
1222                 buffer_info->time_stamp = 0;
1223                 tx_ring->next_to_use = ring_num;
1224                 return;
1225         }
1226         buffer_info->mapped = true;
1227         buffer_info->time_stamp = jiffies;
1228
1229         /*-- Set Tx descriptor --*/
1230         tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1231         tx_desc->buffer_addr = (buffer_info->dma);
1232         tx_desc->length = (tmp_skb->len);
1233         tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1234         tx_desc->tx_frame_ctrl = (frame_ctrl);
1235         tx_desc->gbec_status = (DSC_INIT16);
1236
1237         if (unlikely(++ring_num == tx_ring->count))
1238                 ring_num = 0;
1239
1240         /* Update software pointer of TX descriptor */
1241         iowrite32(tx_ring->dma +
1242                   (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1243                   &hw->reg->TX_DSC_SW_P);
1244
1245         pch_tx_timestamp(adapter, skb);
1246
1247         dev_kfree_skb_any(skb);
1248 }
1249
1250 /**
1251  * pch_gbe_update_stats - Update the board statistics counters
1252  * @adapter:  Board private structure
1253  */
1254 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1255 {
1256         struct net_device *netdev = adapter->netdev;
1257         struct pci_dev *pdev = adapter->pdev;
1258         struct pch_gbe_hw_stats *stats = &adapter->stats;
1259         unsigned long flags;
1260
1261         /*
1262          * Prevent stats update while adapter is being reset, or if the pci
1263          * connection is down.
1264          */
1265         if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1266                 return;
1267
1268         spin_lock_irqsave(&adapter->stats_lock, flags);
1269
1270         /* Update device status "adapter->stats" */
1271         stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1272         stats->tx_errors = stats->tx_length_errors +
1273             stats->tx_aborted_errors +
1274             stats->tx_carrier_errors + stats->tx_timeout_count;
1275
1276         /* Update network device status "adapter->net_stats" */
1277         netdev->stats.rx_packets = stats->rx_packets;
1278         netdev->stats.rx_bytes = stats->rx_bytes;
1279         netdev->stats.rx_dropped = stats->rx_dropped;
1280         netdev->stats.tx_packets = stats->tx_packets;
1281         netdev->stats.tx_bytes = stats->tx_bytes;
1282         netdev->stats.tx_dropped = stats->tx_dropped;
1283         /* Fill out the OS statistics structure */
1284         netdev->stats.multicast = stats->multicast;
1285         netdev->stats.collisions = stats->collisions;
1286         /* Rx Errors */
1287         netdev->stats.rx_errors = stats->rx_errors;
1288         netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1289         netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1290         /* Tx Errors */
1291         netdev->stats.tx_errors = stats->tx_errors;
1292         netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1293         netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1294
1295         spin_unlock_irqrestore(&adapter->stats_lock, flags);
1296 }
1297
1298 static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw)
1299 {
1300         u32 rxdma;
1301
1302         /* Disable Receive DMA */
1303         rxdma = ioread32(&hw->reg->DMA_CTRL);
1304         rxdma &= ~PCH_GBE_RX_DMA_EN;
1305         iowrite32(rxdma, &hw->reg->DMA_CTRL);
1306 }
1307
1308 static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw)
1309 {
1310         u32 rxdma;
1311
1312         /* Enables Receive DMA */
1313         rxdma = ioread32(&hw->reg->DMA_CTRL);
1314         rxdma |= PCH_GBE_RX_DMA_EN;
1315         iowrite32(rxdma, &hw->reg->DMA_CTRL);
1316 }
1317
1318 /**
1319  * pch_gbe_intr - Interrupt Handler
1320  * @irq:   Interrupt number
1321  * @data:  Pointer to a network interface device structure
1322  * Returns:
1323  *      - IRQ_HANDLED:  Our interrupt
1324  *      - IRQ_NONE:     Not our interrupt
1325  */
1326 static irqreturn_t pch_gbe_intr(int irq, void *data)
1327 {
1328         struct net_device *netdev = data;
1329         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1330         struct pch_gbe_hw *hw = &adapter->hw;
1331         u32 int_st;
1332         u32 int_en;
1333
1334         /* Check request status */
1335         int_st = ioread32(&hw->reg->INT_ST);
1336         int_st = int_st & ioread32(&hw->reg->INT_EN);
1337         /* When request status is no interruption factor */
1338         if (unlikely(!int_st))
1339                 return IRQ_NONE;        /* Not our interrupt. End processing. */
1340         netdev_dbg(netdev, "%s occur int_st = 0x%08x\n", __func__, int_st);
1341         if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1342                 adapter->stats.intr_rx_frame_err_count++;
1343         if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1344                 if (!adapter->rx_stop_flag) {
1345                         adapter->stats.intr_rx_fifo_err_count++;
1346                         netdev_dbg(netdev, "Rx fifo over run\n");
1347                         adapter->rx_stop_flag = true;
1348                         int_en = ioread32(&hw->reg->INT_EN);
1349                         iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
1350                                   &hw->reg->INT_EN);
1351                         pch_gbe_disable_dma_rx(&adapter->hw);
1352                         int_st |= ioread32(&hw->reg->INT_ST);
1353                         int_st = int_st & ioread32(&hw->reg->INT_EN);
1354                 }
1355         if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1356                 adapter->stats.intr_rx_dma_err_count++;
1357         if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1358                 adapter->stats.intr_tx_fifo_err_count++;
1359         if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1360                 adapter->stats.intr_tx_dma_err_count++;
1361         if (int_st & PCH_GBE_INT_TCPIP_ERR)
1362                 adapter->stats.intr_tcpip_err_count++;
1363         /* When Rx descriptor is empty  */
1364         if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1365                 adapter->stats.intr_rx_dsc_empty_count++;
1366                 netdev_dbg(netdev, "Rx descriptor is empty\n");
1367                 int_en = ioread32(&hw->reg->INT_EN);
1368                 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1369                 if (hw->mac.tx_fc_enable) {
1370                         /* Set Pause packet */
1371                         pch_gbe_mac_set_pause_packet(hw);
1372                 }
1373         }
1374
1375         /* When request status is Receive interruption */
1376         if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) ||
1377             (adapter->rx_stop_flag)) {
1378                 if (likely(napi_schedule_prep(&adapter->napi))) {
1379                         /* Enable only Rx Descriptor empty */
1380                         atomic_inc(&adapter->irq_sem);
1381                         int_en = ioread32(&hw->reg->INT_EN);
1382                         int_en &=
1383                             ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1384                         iowrite32(int_en, &hw->reg->INT_EN);
1385                         /* Start polling for NAPI */
1386                         __napi_schedule(&adapter->napi);
1387                 }
1388         }
1389         netdev_dbg(netdev, "return = 0x%08x  INT_EN reg = 0x%08x\n",
1390                    IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1391         return IRQ_HANDLED;
1392 }
1393
1394 /**
1395  * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1396  * @adapter:       Board private structure
1397  * @rx_ring:       Rx descriptor ring
1398  * @cleaned_count: Cleaned count
1399  */
1400 static void
1401 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1402                          struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1403 {
1404         struct net_device *netdev = adapter->netdev;
1405         struct pci_dev *pdev = adapter->pdev;
1406         struct pch_gbe_hw *hw = &adapter->hw;
1407         struct pch_gbe_rx_desc *rx_desc;
1408         struct pch_gbe_buffer *buffer_info;
1409         struct sk_buff *skb;
1410         unsigned int i;
1411         unsigned int bufsz;
1412
1413         bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1414         i = rx_ring->next_to_use;
1415
1416         while ((cleaned_count--)) {
1417                 buffer_info = &rx_ring->buffer_info[i];
1418                 skb = netdev_alloc_skb(netdev, bufsz);
1419                 if (unlikely(!skb)) {
1420                         /* Better luck next round */
1421                         adapter->stats.rx_alloc_buff_failed++;
1422                         break;
1423                 }
1424                 /* align */
1425                 skb_reserve(skb, NET_IP_ALIGN);
1426                 buffer_info->skb = skb;
1427
1428                 buffer_info->dma = dma_map_single(&pdev->dev,
1429                                                   buffer_info->rx_buffer,
1430                                                   buffer_info->length,
1431                                                   DMA_FROM_DEVICE);
1432                 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1433                         dev_kfree_skb(skb);
1434                         buffer_info->skb = NULL;
1435                         buffer_info->dma = 0;
1436                         adapter->stats.rx_alloc_buff_failed++;
1437                         break; /* while !buffer_info->skb */
1438                 }
1439                 buffer_info->mapped = true;
1440                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1441                 rx_desc->buffer_addr = (buffer_info->dma);
1442                 rx_desc->gbec_status = DSC_INIT16;
1443
1444                 netdev_dbg(netdev,
1445                            "i = %d  buffer_info->dma = 0x08%llx  buffer_info->length = 0x%x\n",
1446                            i, (unsigned long long)buffer_info->dma,
1447                            buffer_info->length);
1448
1449                 if (unlikely(++i == rx_ring->count))
1450                         i = 0;
1451         }
1452         if (likely(rx_ring->next_to_use != i)) {
1453                 rx_ring->next_to_use = i;
1454                 if (unlikely(i-- == 0))
1455                         i = (rx_ring->count - 1);
1456                 iowrite32(rx_ring->dma +
1457                           (int)sizeof(struct pch_gbe_rx_desc) * i,
1458                           &hw->reg->RX_DSC_SW_P);
1459         }
1460         return;
1461 }
1462
1463 static int
1464 pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter,
1465                          struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1466 {
1467         struct pci_dev *pdev = adapter->pdev;
1468         struct pch_gbe_buffer *buffer_info;
1469         unsigned int i;
1470         unsigned int bufsz;
1471         unsigned int size;
1472
1473         bufsz = adapter->rx_buffer_len;
1474
1475         size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY;
1476         rx_ring->rx_buff_pool =
1477                 dma_zalloc_coherent(&pdev->dev, size,
1478                                     &rx_ring->rx_buff_pool_logic, GFP_KERNEL);
1479         if (!rx_ring->rx_buff_pool)
1480                 return -ENOMEM;
1481
1482         rx_ring->rx_buff_pool_size = size;
1483         for (i = 0; i < rx_ring->count; i++) {
1484                 buffer_info = &rx_ring->buffer_info[i];
1485                 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i;
1486                 buffer_info->length = bufsz;
1487         }
1488         return 0;
1489 }
1490
1491 /**
1492  * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1493  * @adapter:   Board private structure
1494  * @tx_ring:   Tx descriptor ring
1495  */
1496 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1497                                         struct pch_gbe_tx_ring *tx_ring)
1498 {
1499         struct pch_gbe_buffer *buffer_info;
1500         struct sk_buff *skb;
1501         unsigned int i;
1502         unsigned int bufsz;
1503         struct pch_gbe_tx_desc *tx_desc;
1504
1505         bufsz =
1506             adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1507
1508         for (i = 0; i < tx_ring->count; i++) {
1509                 buffer_info = &tx_ring->buffer_info[i];
1510                 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1511                 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1512                 buffer_info->skb = skb;
1513                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1514                 tx_desc->gbec_status = (DSC_INIT16);
1515         }
1516         return;
1517 }
1518
1519 /**
1520  * pch_gbe_clean_tx - Reclaim resources after transmit completes
1521  * @adapter:   Board private structure
1522  * @tx_ring:   Tx descriptor ring
1523  * Returns:
1524  *      true:  Cleaned the descriptor
1525  *      false: Not cleaned the descriptor
1526  */
1527 static bool
1528 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1529                  struct pch_gbe_tx_ring *tx_ring)
1530 {
1531         struct pch_gbe_tx_desc *tx_desc;
1532         struct pch_gbe_buffer *buffer_info;
1533         struct sk_buff *skb;
1534         unsigned int i;
1535         unsigned int cleaned_count = 0;
1536         bool cleaned = false;
1537         int unused, thresh;
1538
1539         netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1540                    tx_ring->next_to_clean);
1541
1542         i = tx_ring->next_to_clean;
1543         tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1544         netdev_dbg(adapter->netdev, "gbec_status:0x%04x  dma_status:0x%04x\n",
1545                    tx_desc->gbec_status, tx_desc->dma_status);
1546
1547         unused = PCH_GBE_DESC_UNUSED(tx_ring);
1548         thresh = tx_ring->count - PCH_GBE_TX_WEIGHT;
1549         if ((tx_desc->gbec_status == DSC_INIT16) && (unused < thresh))
1550         {  /* current marked clean, tx queue filling up, do extra clean */
1551                 int j, k;
1552                 if (unused < 8) {  /* tx queue nearly full */
1553                         netdev_dbg(adapter->netdev,
1554                                    "clean_tx: transmit queue warning (%x,%x) unused=%d\n",
1555                                    tx_ring->next_to_clean, tx_ring->next_to_use,
1556                                    unused);
1557                 }
1558
1559                 /* current marked clean, scan for more that need cleaning. */
1560                 k = i;
1561                 for (j = 0; j < PCH_GBE_TX_WEIGHT; j++)
1562                 {
1563                         tx_desc = PCH_GBE_TX_DESC(*tx_ring, k);
1564                         if (tx_desc->gbec_status != DSC_INIT16) break; /*found*/
1565                         if (++k >= tx_ring->count) k = 0;  /*increment, wrap*/
1566                 }
1567                 if (j < PCH_GBE_TX_WEIGHT) {
1568                         netdev_dbg(adapter->netdev,
1569                                    "clean_tx: unused=%d loops=%d found tx_desc[%x,%x:%x].gbec_status=%04x\n",
1570                                    unused, j, i, k, tx_ring->next_to_use,
1571                                    tx_desc->gbec_status);
1572                         i = k;  /*found one to clean, usu gbec_status==2000.*/
1573                 }
1574         }
1575
1576         while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1577                 netdev_dbg(adapter->netdev, "gbec_status:0x%04x\n",
1578                            tx_desc->gbec_status);
1579                 buffer_info = &tx_ring->buffer_info[i];
1580                 skb = buffer_info->skb;
1581                 cleaned = true;
1582
1583                 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1584                         adapter->stats.tx_aborted_errors++;
1585                         netdev_err(adapter->netdev, "Transfer Abort Error\n");
1586                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1587                           ) {
1588                         adapter->stats.tx_carrier_errors++;
1589                         netdev_err(adapter->netdev,
1590                                    "Transfer Carrier Sense Error\n");
1591                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1592                           ) {
1593                         adapter->stats.tx_aborted_errors++;
1594                         netdev_err(adapter->netdev,
1595                                    "Transfer Collision Abort Error\n");
1596                 } else if ((tx_desc->gbec_status &
1597                             (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1598                              PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1599                         adapter->stats.collisions++;
1600                         adapter->stats.tx_packets++;
1601                         adapter->stats.tx_bytes += skb->len;
1602                         netdev_dbg(adapter->netdev, "Transfer Collision\n");
1603                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1604                           ) {
1605                         adapter->stats.tx_packets++;
1606                         adapter->stats.tx_bytes += skb->len;
1607                 }
1608                 if (buffer_info->mapped) {
1609                         netdev_dbg(adapter->netdev,
1610                                    "unmap buffer_info->dma : %d\n", i);
1611                         dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1612                                          buffer_info->length, DMA_TO_DEVICE);
1613                         buffer_info->mapped = false;
1614                 }
1615                 if (buffer_info->skb) {
1616                         netdev_dbg(adapter->netdev,
1617                                    "trim buffer_info->skb : %d\n", i);
1618                         skb_trim(buffer_info->skb, 0);
1619                 }
1620                 tx_desc->gbec_status = DSC_INIT16;
1621                 if (unlikely(++i == tx_ring->count))
1622                         i = 0;
1623                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1624
1625                 /* weight of a sort for tx, to avoid endless transmit cleanup */
1626                 if (cleaned_count++ == PCH_GBE_TX_WEIGHT) {
1627                         cleaned = false;
1628                         break;
1629                 }
1630         }
1631         netdev_dbg(adapter->netdev,
1632                    "called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1633                    cleaned_count);
1634         if (cleaned_count > 0)  { /*skip this if nothing cleaned*/
1635                 /* Recover from running out of Tx resources in xmit_frame */
1636                 netif_tx_lock(adapter->netdev);
1637                 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev))))
1638                 {
1639                         netif_wake_queue(adapter->netdev);
1640                         adapter->stats.tx_restart_count++;
1641                         netdev_dbg(adapter->netdev, "Tx wake queue\n");
1642                 }
1643
1644                 tx_ring->next_to_clean = i;
1645
1646                 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1647                            tx_ring->next_to_clean);
1648                 netif_tx_unlock(adapter->netdev);
1649         }
1650         return cleaned;
1651 }
1652
1653 /**
1654  * pch_gbe_clean_rx - Send received data up the network stack; legacy
1655  * @adapter:     Board private structure
1656  * @rx_ring:     Rx descriptor ring
1657  * @work_done:   Completed count
1658  * @work_to_do:  Request count
1659  * Returns:
1660  *      true:  Cleaned the descriptor
1661  *      false: Not cleaned the descriptor
1662  */
1663 static bool
1664 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1665                  struct pch_gbe_rx_ring *rx_ring,
1666                  int *work_done, int work_to_do)
1667 {
1668         struct net_device *netdev = adapter->netdev;
1669         struct pci_dev *pdev = adapter->pdev;
1670         struct pch_gbe_buffer *buffer_info;
1671         struct pch_gbe_rx_desc *rx_desc;
1672         u32 length;
1673         unsigned int i;
1674         unsigned int cleaned_count = 0;
1675         bool cleaned = false;
1676         struct sk_buff *skb;
1677         u8 dma_status;
1678         u16 gbec_status;
1679         u32 tcp_ip_status;
1680
1681         i = rx_ring->next_to_clean;
1682
1683         while (*work_done < work_to_do) {
1684                 /* Check Rx descriptor status */
1685                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1686                 if (rx_desc->gbec_status == DSC_INIT16)
1687                         break;
1688                 cleaned = true;
1689                 cleaned_count++;
1690
1691                 dma_status = rx_desc->dma_status;
1692                 gbec_status = rx_desc->gbec_status;
1693                 tcp_ip_status = rx_desc->tcp_ip_status;
1694                 rx_desc->gbec_status = DSC_INIT16;
1695                 buffer_info = &rx_ring->buffer_info[i];
1696                 skb = buffer_info->skb;
1697                 buffer_info->skb = NULL;
1698
1699                 /* unmap dma */
1700                 dma_unmap_single(&pdev->dev, buffer_info->dma,
1701                                    buffer_info->length, DMA_FROM_DEVICE);
1702                 buffer_info->mapped = false;
1703
1704                 netdev_dbg(netdev,
1705                            "RxDecNo = 0x%04x  Status[DMA:0x%02x GBE:0x%04x TCP:0x%08x]  BufInf = 0x%p\n",
1706                            i, dma_status, gbec_status, tcp_ip_status,
1707                            buffer_info);
1708                 /* Error check */
1709                 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1710                         adapter->stats.rx_frame_errors++;
1711                         netdev_err(netdev, "Receive Not Octal Error\n");
1712                 } else if (unlikely(gbec_status &
1713                                 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1714                         adapter->stats.rx_frame_errors++;
1715                         netdev_err(netdev, "Receive Nibble Error\n");
1716                 } else if (unlikely(gbec_status &
1717                                 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1718                         adapter->stats.rx_crc_errors++;
1719                         netdev_err(netdev, "Receive CRC Error\n");
1720                 } else {
1721                         /* get receive length */
1722                         /* length convert[-3], length includes FCS length */
1723                         length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN;
1724                         if (rx_desc->rx_words_eob & 0x02)
1725                                 length = length - 4;
1726                         /*
1727                          * buffer_info->rx_buffer: [Header:14][payload]
1728                          * skb->data: [Reserve:2][Header:14][payload]
1729                          */
1730                         memcpy(skb->data, buffer_info->rx_buffer, length);
1731
1732                         /* update status of driver */
1733                         adapter->stats.rx_bytes += length;
1734                         adapter->stats.rx_packets++;
1735                         if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1736                                 adapter->stats.multicast++;
1737                         /* Write meta date of skb */
1738                         skb_put(skb, length);
1739
1740                         pch_rx_timestamp(adapter, skb);
1741
1742                         skb->protocol = eth_type_trans(skb, netdev);
1743                         if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
1744                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1745                         else
1746                                 skb->ip_summed = CHECKSUM_NONE;
1747
1748                         napi_gro_receive(&adapter->napi, skb);
1749                         (*work_done)++;
1750                         netdev_dbg(netdev,
1751                                    "Receive skb->ip_summed: %d length: %d\n",
1752                                    skb->ip_summed, length);
1753                 }
1754                 /* return some buffers to hardware, one at a time is too slow */
1755                 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1756                         pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1757                                                  cleaned_count);
1758                         cleaned_count = 0;
1759                 }
1760                 if (++i == rx_ring->count)
1761                         i = 0;
1762         }
1763         rx_ring->next_to_clean = i;
1764         if (cleaned_count)
1765                 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1766         return cleaned;
1767 }
1768
1769 /**
1770  * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1771  * @adapter:  Board private structure
1772  * @tx_ring:  Tx descriptor ring (for a specific queue) to setup
1773  * Returns:
1774  *      0:              Successfully
1775  *      Negative value: Failed
1776  */
1777 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1778                                 struct pch_gbe_tx_ring *tx_ring)
1779 {
1780         struct pci_dev *pdev = adapter->pdev;
1781         struct pch_gbe_tx_desc *tx_desc;
1782         int size;
1783         int desNo;
1784
1785         size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1786         tx_ring->buffer_info = vzalloc(size);
1787         if (!tx_ring->buffer_info)
1788                 return -ENOMEM;
1789
1790         tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1791
1792         tx_ring->desc = dma_zalloc_coherent(&pdev->dev, tx_ring->size,
1793                                             &tx_ring->dma, GFP_KERNEL);
1794         if (!tx_ring->desc) {
1795                 vfree(tx_ring->buffer_info);
1796                 return -ENOMEM;
1797         }
1798
1799         tx_ring->next_to_use = 0;
1800         tx_ring->next_to_clean = 0;
1801
1802         for (desNo = 0; desNo < tx_ring->count; desNo++) {
1803                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1804                 tx_desc->gbec_status = DSC_INIT16;
1805         }
1806         netdev_dbg(adapter->netdev,
1807                    "tx_ring->desc = 0x%p  tx_ring->dma = 0x%08llx next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1808                    tx_ring->desc, (unsigned long long)tx_ring->dma,
1809                    tx_ring->next_to_clean, tx_ring->next_to_use);
1810         return 0;
1811 }
1812
1813 /**
1814  * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1815  * @adapter:  Board private structure
1816  * @rx_ring:  Rx descriptor ring (for a specific queue) to setup
1817  * Returns:
1818  *      0:              Successfully
1819  *      Negative value: Failed
1820  */
1821 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1822                                 struct pch_gbe_rx_ring *rx_ring)
1823 {
1824         struct pci_dev *pdev = adapter->pdev;
1825         struct pch_gbe_rx_desc *rx_desc;
1826         int size;
1827         int desNo;
1828
1829         size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1830         rx_ring->buffer_info = vzalloc(size);
1831         if (!rx_ring->buffer_info)
1832                 return -ENOMEM;
1833
1834         rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1835         rx_ring->desc = dma_zalloc_coherent(&pdev->dev, rx_ring->size,
1836                                             &rx_ring->dma, GFP_KERNEL);
1837         if (!rx_ring->desc) {
1838                 vfree(rx_ring->buffer_info);
1839                 return -ENOMEM;
1840         }
1841         rx_ring->next_to_clean = 0;
1842         rx_ring->next_to_use = 0;
1843         for (desNo = 0; desNo < rx_ring->count; desNo++) {
1844                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1845                 rx_desc->gbec_status = DSC_INIT16;
1846         }
1847         netdev_dbg(adapter->netdev,
1848                    "rx_ring->desc = 0x%p  rx_ring->dma = 0x%08llx next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1849                    rx_ring->desc, (unsigned long long)rx_ring->dma,
1850                    rx_ring->next_to_clean, rx_ring->next_to_use);
1851         return 0;
1852 }
1853
1854 /**
1855  * pch_gbe_free_tx_resources - Free Tx Resources
1856  * @adapter:  Board private structure
1857  * @tx_ring:  Tx descriptor ring for a specific queue
1858  */
1859 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1860                                 struct pch_gbe_tx_ring *tx_ring)
1861 {
1862         struct pci_dev *pdev = adapter->pdev;
1863
1864         pch_gbe_clean_tx_ring(adapter, tx_ring);
1865         vfree(tx_ring->buffer_info);
1866         tx_ring->buffer_info = NULL;
1867         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1868         tx_ring->desc = NULL;
1869 }
1870
1871 /**
1872  * pch_gbe_free_rx_resources - Free Rx Resources
1873  * @adapter:  Board private structure
1874  * @rx_ring:  Ring to clean the resources from
1875  */
1876 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1877                                 struct pch_gbe_rx_ring *rx_ring)
1878 {
1879         struct pci_dev *pdev = adapter->pdev;
1880
1881         pch_gbe_clean_rx_ring(adapter, rx_ring);
1882         vfree(rx_ring->buffer_info);
1883         rx_ring->buffer_info = NULL;
1884         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1885         rx_ring->desc = NULL;
1886 }
1887
1888 /**
1889  * pch_gbe_request_irq - Allocate an interrupt line
1890  * @adapter:  Board private structure
1891  * Returns:
1892  *      0:              Successfully
1893  *      Negative value: Failed
1894  */
1895 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1896 {
1897         struct net_device *netdev = adapter->netdev;
1898         int err;
1899         int flags;
1900
1901         flags = IRQF_SHARED;
1902         adapter->have_msi = false;
1903         err = pci_enable_msi(adapter->pdev);
1904         netdev_dbg(netdev, "call pci_enable_msi\n");
1905         if (err) {
1906                 netdev_dbg(netdev, "call pci_enable_msi - Error: %d\n", err);
1907         } else {
1908                 flags = 0;
1909                 adapter->have_msi = true;
1910         }
1911         err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1912                           flags, netdev->name, netdev);
1913         if (err)
1914                 netdev_err(netdev, "Unable to allocate interrupt Error: %d\n",
1915                            err);
1916         netdev_dbg(netdev,
1917                    "adapter->have_msi : %d  flags : 0x%04x  return : 0x%04x\n",
1918                    adapter->have_msi, flags, err);
1919         return err;
1920 }
1921
1922
1923 /**
1924  * pch_gbe_up - Up GbE network device
1925  * @adapter:  Board private structure
1926  * Returns:
1927  *      0:              Successfully
1928  *      Negative value: Failed
1929  */
1930 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1931 {
1932         struct net_device *netdev = adapter->netdev;
1933         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1934         struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1935         int err = -EINVAL;
1936
1937         /* Ensure we have a valid MAC */
1938         if (!is_valid_ether_addr(adapter->hw.mac.addr)) {
1939                 netdev_err(netdev, "Error: Invalid MAC address\n");
1940                 goto out;
1941         }
1942
1943         /* hardware has been reset, we need to reload some things */
1944         pch_gbe_set_multi(netdev);
1945
1946         pch_gbe_setup_tctl(adapter);
1947         pch_gbe_configure_tx(adapter);
1948         pch_gbe_setup_rctl(adapter);
1949         pch_gbe_configure_rx(adapter);
1950
1951         err = pch_gbe_request_irq(adapter);
1952         if (err) {
1953                 netdev_err(netdev,
1954                            "Error: can't bring device up - irq request failed\n");
1955                 goto out;
1956         }
1957         err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count);
1958         if (err) {
1959                 netdev_err(netdev,
1960                            "Error: can't bring device up - alloc rx buffers pool failed\n");
1961                 goto freeirq;
1962         }
1963         pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1964         pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1965         adapter->tx_queue_len = netdev->tx_queue_len;
1966         pch_gbe_enable_dma_rx(&adapter->hw);
1967         pch_gbe_enable_mac_rx(&adapter->hw);
1968
1969         mod_timer(&adapter->watchdog_timer, jiffies);
1970
1971         napi_enable(&adapter->napi);
1972         pch_gbe_irq_enable(adapter);
1973         netif_start_queue(adapter->netdev);
1974
1975         return 0;
1976
1977 freeirq:
1978         pch_gbe_free_irq(adapter);
1979 out:
1980         return err;
1981 }
1982
1983 /**
1984  * pch_gbe_down - Down GbE network device
1985  * @adapter:  Board private structure
1986  */
1987 void pch_gbe_down(struct pch_gbe_adapter *adapter)
1988 {
1989         struct net_device *netdev = adapter->netdev;
1990         struct pci_dev *pdev = adapter->pdev;
1991         struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1992
1993         /* signal that we're down so the interrupt handler does not
1994          * reschedule our watchdog timer */
1995         napi_disable(&adapter->napi);
1996         atomic_set(&adapter->irq_sem, 0);
1997
1998         pch_gbe_irq_disable(adapter);
1999         pch_gbe_free_irq(adapter);
2000
2001         del_timer_sync(&adapter->watchdog_timer);
2002
2003         netdev->tx_queue_len = adapter->tx_queue_len;
2004         netif_carrier_off(netdev);
2005         netif_stop_queue(netdev);
2006
2007         if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
2008                 pch_gbe_reset(adapter);
2009         pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
2010         pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
2011
2012         pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size,
2013                             rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic);
2014         rx_ring->rx_buff_pool_logic = 0;
2015         rx_ring->rx_buff_pool_size = 0;
2016         rx_ring->rx_buff_pool = NULL;
2017 }
2018
2019 /**
2020  * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
2021  * @adapter:  Board private structure to initialize
2022  * Returns:
2023  *      0:              Successfully
2024  *      Negative value: Failed
2025  */
2026 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
2027 {
2028         struct pch_gbe_hw *hw = &adapter->hw;
2029         struct net_device *netdev = adapter->netdev;
2030
2031         adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2032         hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2033         hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2034
2035         /* Initialize the hardware-specific values */
2036         if (pch_gbe_hal_setup_init_funcs(hw)) {
2037                 netdev_err(netdev, "Hardware Initialization Failure\n");
2038                 return -EIO;
2039         }
2040         if (pch_gbe_alloc_queues(adapter)) {
2041                 netdev_err(netdev, "Unable to allocate memory for queues\n");
2042                 return -ENOMEM;
2043         }
2044         spin_lock_init(&adapter->hw.miim_lock);
2045         spin_lock_init(&adapter->stats_lock);
2046         spin_lock_init(&adapter->ethtool_lock);
2047         atomic_set(&adapter->irq_sem, 0);
2048         pch_gbe_irq_disable(adapter);
2049
2050         pch_gbe_init_stats(adapter);
2051
2052         netdev_dbg(netdev,
2053                    "rx_buffer_len : %d  mac.min_frame_size : %d  mac.max_frame_size : %d\n",
2054                    (u32) adapter->rx_buffer_len,
2055                    hw->mac.min_frame_size, hw->mac.max_frame_size);
2056         return 0;
2057 }
2058
2059 /**
2060  * pch_gbe_open - Called when a network interface is made active
2061  * @netdev:     Network interface device structure
2062  * Returns:
2063  *      0:              Successfully
2064  *      Negative value: Failed
2065  */
2066 static int pch_gbe_open(struct net_device *netdev)
2067 {
2068         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2069         struct pch_gbe_hw *hw = &adapter->hw;
2070         int err;
2071
2072         /* allocate transmit descriptors */
2073         err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
2074         if (err)
2075                 goto err_setup_tx;
2076         /* allocate receive descriptors */
2077         err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
2078         if (err)
2079                 goto err_setup_rx;
2080         pch_gbe_hal_power_up_phy(hw);
2081         err = pch_gbe_up(adapter);
2082         if (err)
2083                 goto err_up;
2084         netdev_dbg(netdev, "Success End\n");
2085         return 0;
2086
2087 err_up:
2088         if (!adapter->wake_up_evt)
2089                 pch_gbe_hal_power_down_phy(hw);
2090         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2091 err_setup_rx:
2092         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2093 err_setup_tx:
2094         pch_gbe_reset(adapter);
2095         netdev_err(netdev, "Error End\n");
2096         return err;
2097 }
2098
2099 /**
2100  * pch_gbe_stop - Disables a network interface
2101  * @netdev:  Network interface device structure
2102  * Returns:
2103  *      0: Successfully
2104  */
2105 static int pch_gbe_stop(struct net_device *netdev)
2106 {
2107         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2108         struct pch_gbe_hw *hw = &adapter->hw;
2109
2110         pch_gbe_down(adapter);
2111         if (!adapter->wake_up_evt)
2112                 pch_gbe_hal_power_down_phy(hw);
2113         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2114         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2115         return 0;
2116 }
2117
2118 /**
2119  * pch_gbe_xmit_frame - Packet transmitting start
2120  * @skb:     Socket buffer structure
2121  * @netdev:  Network interface device structure
2122  * Returns:
2123  *      - NETDEV_TX_OK:   Normal end
2124  *      - NETDEV_TX_BUSY: Error end
2125  */
2126 static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2127 {
2128         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2129         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
2130
2131         if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
2132                 netif_stop_queue(netdev);
2133                 netdev_dbg(netdev,
2134                            "Return : BUSY  next_to use : 0x%08x  next_to clean : 0x%08x\n",
2135                            tx_ring->next_to_use, tx_ring->next_to_clean);
2136                 return NETDEV_TX_BUSY;
2137         }
2138
2139         /* CRC,ITAG no support */
2140         pch_gbe_tx_queue(adapter, tx_ring, skb);
2141         return NETDEV_TX_OK;
2142 }
2143
2144 /**
2145  * pch_gbe_get_stats - Get System Network Statistics
2146  * @netdev:  Network interface device structure
2147  * Returns:  The current stats
2148  */
2149 static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
2150 {
2151         /* only return the current stats */
2152         return &netdev->stats;
2153 }
2154
2155 /**
2156  * pch_gbe_set_multi - Multicast and Promiscuous mode set
2157  * @netdev:   Network interface device structure
2158  */
2159 static void pch_gbe_set_multi(struct net_device *netdev)
2160 {
2161         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2162         struct pch_gbe_hw *hw = &adapter->hw;
2163         struct netdev_hw_addr *ha;
2164         u8 *mta_list;
2165         u32 rctl;
2166         int i;
2167         int mc_count;
2168
2169         netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags);
2170
2171         /* Check for Promiscuous and All Multicast modes */
2172         rctl = ioread32(&hw->reg->RX_MODE);
2173         mc_count = netdev_mc_count(netdev);
2174         if ((netdev->flags & IFF_PROMISC)) {
2175                 rctl &= ~PCH_GBE_ADD_FIL_EN;
2176                 rctl &= ~PCH_GBE_MLT_FIL_EN;
2177         } else if ((netdev->flags & IFF_ALLMULTI)) {
2178                 /* all the multicasting receive permissions */
2179                 rctl |= PCH_GBE_ADD_FIL_EN;
2180                 rctl &= ~PCH_GBE_MLT_FIL_EN;
2181         } else {
2182                 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
2183                         /* all the multicasting receive permissions */
2184                         rctl |= PCH_GBE_ADD_FIL_EN;
2185                         rctl &= ~PCH_GBE_MLT_FIL_EN;
2186                 } else {
2187                         rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
2188                 }
2189         }
2190         iowrite32(rctl, &hw->reg->RX_MODE);
2191
2192         if (mc_count >= PCH_GBE_MAR_ENTRIES)
2193                 return;
2194         mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
2195         if (!mta_list)
2196                 return;
2197
2198         /* The shared function expects a packed array of only addresses. */
2199         i = 0;
2200         netdev_for_each_mc_addr(ha, netdev) {
2201                 if (i == mc_count)
2202                         break;
2203                 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
2204         }
2205         pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
2206                                         PCH_GBE_MAR_ENTRIES);
2207         kfree(mta_list);
2208
2209         netdev_dbg(netdev,
2210                  "RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x  netdev->mc_count : 0x%08x\n",
2211                  ioread32(&hw->reg->RX_MODE), mc_count);
2212 }
2213
2214 /**
2215  * pch_gbe_set_mac - Change the Ethernet Address of the NIC
2216  * @netdev: Network interface device structure
2217  * @addr:   Pointer to an address structure
2218  * Returns:
2219  *      0:              Successfully
2220  *      -EADDRNOTAVAIL: Failed
2221  */
2222 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
2223 {
2224         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2225         struct sockaddr *skaddr = addr;
2226         int ret_val;
2227
2228         if (!is_valid_ether_addr(skaddr->sa_data)) {
2229                 ret_val = -EADDRNOTAVAIL;
2230         } else {
2231                 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
2232                 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
2233                 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2234                 ret_val = 0;
2235         }
2236         netdev_dbg(netdev, "ret_val : 0x%08x\n", ret_val);
2237         netdev_dbg(netdev, "dev_addr : %pM\n", netdev->dev_addr);
2238         netdev_dbg(netdev, "mac_addr : %pM\n", adapter->hw.mac.addr);
2239         netdev_dbg(netdev, "MAC_ADR1AB reg : 0x%08x 0x%08x\n",
2240                    ioread32(&adapter->hw.reg->mac_adr[0].high),
2241                    ioread32(&adapter->hw.reg->mac_adr[0].low));
2242         return ret_val;
2243 }
2244
2245 /**
2246  * pch_gbe_change_mtu - Change the Maximum Transfer Unit
2247  * @netdev:   Network interface device structure
2248  * @new_mtu:  New value for maximum frame size
2249  * Returns:
2250  *      0:              Successfully
2251  *      -EINVAL:        Failed
2252  */
2253 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2254 {
2255         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2256         int max_frame;
2257         unsigned long old_rx_buffer_len = adapter->rx_buffer_len;
2258         int err;
2259
2260         max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2261         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2262                 (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
2263                 netdev_err(netdev, "Invalid MTU setting\n");
2264                 return -EINVAL;
2265         }
2266         if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2267                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2268         else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2269                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2270         else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2271                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2272         else
2273                 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE;
2274
2275         if (netif_running(netdev)) {
2276                 pch_gbe_down(adapter);
2277                 err = pch_gbe_up(adapter);
2278                 if (err) {
2279                         adapter->rx_buffer_len = old_rx_buffer_len;
2280                         pch_gbe_up(adapter);
2281                         return err;
2282                 } else {
2283                         netdev->mtu = new_mtu;
2284                         adapter->hw.mac.max_frame_size = max_frame;
2285                 }
2286         } else {
2287                 pch_gbe_reset(adapter);
2288                 netdev->mtu = new_mtu;
2289                 adapter->hw.mac.max_frame_size = max_frame;
2290         }
2291
2292         netdev_dbg(netdev,
2293                    "max_frame : %d  rx_buffer_len : %d  mtu : %d  max_frame_size : %d\n",
2294                    max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2295                    adapter->hw.mac.max_frame_size);
2296         return 0;
2297 }
2298
2299 /**
2300  * pch_gbe_set_features - Reset device after features changed
2301  * @netdev:   Network interface device structure
2302  * @features:  New features
2303  * Returns:
2304  *      0:              HW state updated successfully
2305  */
2306 static int pch_gbe_set_features(struct net_device *netdev,
2307         netdev_features_t features)
2308 {
2309         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2310         netdev_features_t changed = features ^ netdev->features;
2311
2312         if (!(changed & NETIF_F_RXCSUM))
2313                 return 0;
2314
2315         if (netif_running(netdev))
2316                 pch_gbe_reinit_locked(adapter);
2317         else
2318                 pch_gbe_reset(adapter);
2319
2320         return 0;
2321 }
2322
2323 /**
2324  * pch_gbe_ioctl - Controls register through a MII interface
2325  * @netdev:   Network interface device structure
2326  * @ifr:      Pointer to ifr structure
2327  * @cmd:      Control command
2328  * Returns:
2329  *      0:      Successfully
2330  *      Negative value: Failed
2331  */
2332 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2333 {
2334         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2335
2336         netdev_dbg(netdev, "cmd : 0x%04x\n", cmd);
2337
2338         if (cmd == SIOCSHWTSTAMP)
2339                 return hwtstamp_ioctl(netdev, ifr, cmd);
2340
2341         return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2342 }
2343
2344 /**
2345  * pch_gbe_tx_timeout - Respond to a Tx Hang
2346  * @netdev:   Network interface device structure
2347  */
2348 static void pch_gbe_tx_timeout(struct net_device *netdev)
2349 {
2350         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2351
2352         /* Do the reset outside of interrupt context */
2353         adapter->stats.tx_timeout_count++;
2354         schedule_work(&adapter->reset_task);
2355 }
2356
2357 /**
2358  * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2359  * @napi:    Pointer of polling device struct
2360  * @budget:  The maximum number of a packet
2361  * Returns:
2362  *      false:  Exit the polling mode
2363  *      true:   Continue the polling mode
2364  */
2365 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2366 {
2367         struct pch_gbe_adapter *adapter =
2368             container_of(napi, struct pch_gbe_adapter, napi);
2369         int work_done = 0;
2370         bool poll_end_flag = false;
2371         bool cleaned = false;
2372
2373         netdev_dbg(adapter->netdev, "budget : %d\n", budget);
2374
2375         pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2376         cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2377
2378         if (cleaned)
2379                 work_done = budget;
2380         /* If no Tx and not enough Rx work done,
2381          * exit the polling mode
2382          */
2383         if (work_done < budget)
2384                 poll_end_flag = true;
2385
2386         if (poll_end_flag) {
2387                 napi_complete(napi);
2388                 pch_gbe_irq_enable(adapter);
2389         }
2390
2391         if (adapter->rx_stop_flag) {
2392                 adapter->rx_stop_flag = false;
2393                 pch_gbe_enable_dma_rx(&adapter->hw);
2394         }
2395
2396         netdev_dbg(adapter->netdev,
2397                    "poll_end_flag : %d  work_done : %d  budget : %d\n",
2398                    poll_end_flag, work_done, budget);
2399
2400         return work_done;
2401 }
2402
2403 #ifdef CONFIG_NET_POLL_CONTROLLER
2404 /**
2405  * pch_gbe_netpoll - Used by things like netconsole to send skbs
2406  * @netdev:  Network interface device structure
2407  */
2408 static void pch_gbe_netpoll(struct net_device *netdev)
2409 {
2410         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2411
2412         disable_irq(adapter->pdev->irq);
2413         pch_gbe_intr(adapter->pdev->irq, netdev);
2414         enable_irq(adapter->pdev->irq);
2415 }
2416 #endif
2417
2418 static const struct net_device_ops pch_gbe_netdev_ops = {
2419         .ndo_open = pch_gbe_open,
2420         .ndo_stop = pch_gbe_stop,
2421         .ndo_start_xmit = pch_gbe_xmit_frame,
2422         .ndo_get_stats = pch_gbe_get_stats,
2423         .ndo_set_mac_address = pch_gbe_set_mac,
2424         .ndo_tx_timeout = pch_gbe_tx_timeout,
2425         .ndo_change_mtu = pch_gbe_change_mtu,
2426         .ndo_set_features = pch_gbe_set_features,
2427         .ndo_do_ioctl = pch_gbe_ioctl,
2428         .ndo_set_rx_mode = pch_gbe_set_multi,
2429 #ifdef CONFIG_NET_POLL_CONTROLLER
2430         .ndo_poll_controller = pch_gbe_netpoll,
2431 #endif
2432 };
2433
2434 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2435                                                 pci_channel_state_t state)
2436 {
2437         struct net_device *netdev = pci_get_drvdata(pdev);
2438         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2439
2440         netif_device_detach(netdev);
2441         if (netif_running(netdev))
2442                 pch_gbe_down(adapter);
2443         pci_disable_device(pdev);
2444         /* Request a slot slot reset. */
2445         return PCI_ERS_RESULT_NEED_RESET;
2446 }
2447
2448 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2449 {
2450         struct net_device *netdev = pci_get_drvdata(pdev);
2451         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2452         struct pch_gbe_hw *hw = &adapter->hw;
2453
2454         if (pci_enable_device(pdev)) {
2455                 netdev_err(netdev, "Cannot re-enable PCI device after reset\n");
2456                 return PCI_ERS_RESULT_DISCONNECT;
2457         }
2458         pci_set_master(pdev);
2459         pci_enable_wake(pdev, PCI_D0, 0);
2460         pch_gbe_hal_power_up_phy(hw);
2461         pch_gbe_reset(adapter);
2462         /* Clear wake up status */
2463         pch_gbe_mac_set_wol_event(hw, 0);
2464
2465         return PCI_ERS_RESULT_RECOVERED;
2466 }
2467
2468 static void pch_gbe_io_resume(struct pci_dev *pdev)
2469 {
2470         struct net_device *netdev = pci_get_drvdata(pdev);
2471         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2472
2473         if (netif_running(netdev)) {
2474                 if (pch_gbe_up(adapter)) {
2475                         netdev_dbg(netdev,
2476                                    "can't bring device back up after reset\n");
2477                         return;
2478                 }
2479         }
2480         netif_device_attach(netdev);
2481 }
2482
2483 static int __pch_gbe_suspend(struct pci_dev *pdev)
2484 {
2485         struct net_device *netdev = pci_get_drvdata(pdev);
2486         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2487         struct pch_gbe_hw *hw = &adapter->hw;
2488         u32 wufc = adapter->wake_up_evt;
2489         int retval = 0;
2490
2491         netif_device_detach(netdev);
2492         if (netif_running(netdev))
2493                 pch_gbe_down(adapter);
2494         if (wufc) {
2495                 pch_gbe_set_multi(netdev);
2496                 pch_gbe_setup_rctl(adapter);
2497                 pch_gbe_configure_rx(adapter);
2498                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2499                                         hw->mac.link_duplex);
2500                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2501                                         hw->mac.link_duplex);
2502                 pch_gbe_mac_set_wol_event(hw, wufc);
2503                 pci_disable_device(pdev);
2504         } else {
2505                 pch_gbe_hal_power_down_phy(hw);
2506                 pch_gbe_mac_set_wol_event(hw, wufc);
2507                 pci_disable_device(pdev);
2508         }
2509         return retval;
2510 }
2511
2512 #ifdef CONFIG_PM
2513 static int pch_gbe_suspend(struct device *device)
2514 {
2515         struct pci_dev *pdev = to_pci_dev(device);
2516
2517         return __pch_gbe_suspend(pdev);
2518 }
2519
2520 static int pch_gbe_resume(struct device *device)
2521 {
2522         struct pci_dev *pdev = to_pci_dev(device);
2523         struct net_device *netdev = pci_get_drvdata(pdev);
2524         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2525         struct pch_gbe_hw *hw = &adapter->hw;
2526         u32 err;
2527
2528         err = pci_enable_device(pdev);
2529         if (err) {
2530                 netdev_err(netdev, "Cannot enable PCI device from suspend\n");
2531                 return err;
2532         }
2533         pci_set_master(pdev);
2534         pch_gbe_hal_power_up_phy(hw);
2535         pch_gbe_reset(adapter);
2536         /* Clear wake on lan control and status */
2537         pch_gbe_mac_set_wol_event(hw, 0);
2538
2539         if (netif_running(netdev))
2540                 pch_gbe_up(adapter);
2541         netif_device_attach(netdev);
2542
2543         return 0;
2544 }
2545 #endif /* CONFIG_PM */
2546
2547 static void pch_gbe_shutdown(struct pci_dev *pdev)
2548 {
2549         __pch_gbe_suspend(pdev);
2550         if (system_state == SYSTEM_POWER_OFF) {
2551                 pci_wake_from_d3(pdev, true);
2552                 pci_set_power_state(pdev, PCI_D3hot);
2553         }
2554 }
2555
2556 static void pch_gbe_remove(struct pci_dev *pdev)
2557 {
2558         struct net_device *netdev = pci_get_drvdata(pdev);
2559         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2560
2561         cancel_work_sync(&adapter->reset_task);
2562         unregister_netdev(netdev);
2563
2564         pch_gbe_hal_phy_hw_reset(&adapter->hw);
2565
2566         free_netdev(netdev);
2567 }
2568
2569 static int pch_gbe_probe(struct pci_dev *pdev,
2570                           const struct pci_device_id *pci_id)
2571 {
2572         struct net_device *netdev;
2573         struct pch_gbe_adapter *adapter;
2574         int ret;
2575
2576         ret = pcim_enable_device(pdev);
2577         if (ret)
2578                 return ret;
2579
2580         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2581                 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2582                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2583                 if (ret) {
2584                         ret = pci_set_consistent_dma_mask(pdev,
2585                                                           DMA_BIT_MASK(32));
2586                         if (ret) {
2587                                 dev_err(&pdev->dev, "ERR: No usable DMA "
2588                                         "configuration, aborting\n");
2589                                 return ret;
2590                         }
2591                 }
2592         }
2593
2594         ret = pcim_iomap_regions(pdev, 1 << PCH_GBE_PCI_BAR, pci_name(pdev));
2595         if (ret) {
2596                 dev_err(&pdev->dev,
2597                         "ERR: Can't reserve PCI I/O and memory resources\n");
2598                 return ret;
2599         }
2600         pci_set_master(pdev);
2601
2602         netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2603         if (!netdev)
2604                 return -ENOMEM;
2605         SET_NETDEV_DEV(netdev, &pdev->dev);
2606
2607         pci_set_drvdata(pdev, netdev);
2608         adapter = netdev_priv(netdev);
2609         adapter->netdev = netdev;
2610         adapter->pdev = pdev;
2611         adapter->hw.back = adapter;
2612         adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
2613
2614         adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
2615         if (adapter->pdata && adapter->pdata->platform_init) {
2616                 ret = adapter->pdata->platform_init(pdev);
2617                 if (ret)
2618                         goto err_free_netdev;
2619         }
2620
2621         adapter->ptp_pdev = pci_get_bus_and_slot(adapter->pdev->bus->number,
2622                                                PCI_DEVFN(12, 4));
2623
2624         netdev->netdev_ops = &pch_gbe_netdev_ops;
2625         netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2626         netif_napi_add(netdev, &adapter->napi,
2627                        pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2628         netdev->hw_features = NETIF_F_RXCSUM |
2629                 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2630         netdev->features = netdev->hw_features;
2631         pch_gbe_set_ethtool_ops(netdev);
2632
2633         pch_gbe_mac_load_mac_addr(&adapter->hw);
2634         pch_gbe_mac_reset_hw(&adapter->hw);
2635
2636         /* setup the private structure */
2637         ret = pch_gbe_sw_init(adapter);
2638         if (ret)
2639                 goto err_free_netdev;
2640
2641         /* Initialize PHY */
2642         ret = pch_gbe_init_phy(adapter);
2643         if (ret) {
2644                 dev_err(&pdev->dev, "PHY initialize error\n");
2645                 goto err_free_adapter;
2646         }
2647         pch_gbe_hal_get_bus_info(&adapter->hw);
2648
2649         /* Read the MAC address. and store to the private data */
2650         ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2651         if (ret) {
2652                 dev_err(&pdev->dev, "MAC address Read Error\n");
2653                 goto err_free_adapter;
2654         }
2655
2656         memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2657         if (!is_valid_ether_addr(netdev->dev_addr)) {
2658                 /*
2659                  * If the MAC is invalid (or just missing), display a warning
2660                  * but do not abort setting up the device. pch_gbe_up will
2661                  * prevent the interface from being brought up until a valid MAC
2662                  * is set.
2663                  */
2664                 dev_err(&pdev->dev, "Invalid MAC address, "
2665                                     "interface disabled.\n");
2666         }
2667         setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2668                     (unsigned long)adapter);
2669
2670         INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2671
2672         pch_gbe_check_options(adapter);
2673
2674         /* initialize the wol settings based on the eeprom settings */
2675         adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2676         dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2677
2678         /* reset the hardware with the new settings */
2679         pch_gbe_reset(adapter);
2680
2681         ret = register_netdev(netdev);
2682         if (ret)
2683                 goto err_free_adapter;
2684         /* tell the stack to leave us alone until pch_gbe_open() is called */
2685         netif_carrier_off(netdev);
2686         netif_stop_queue(netdev);
2687
2688         dev_dbg(&pdev->dev, "PCH Network Connection\n");
2689
2690         /* Disable hibernation on certain platforms */
2691         if (adapter->pdata && adapter->pdata->phy_disable_hibernate)
2692                 pch_gbe_phy_disable_hibernate(&adapter->hw);
2693
2694         device_set_wakeup_enable(&pdev->dev, 1);
2695         return 0;
2696
2697 err_free_adapter:
2698         pch_gbe_hal_phy_hw_reset(&adapter->hw);
2699 err_free_netdev:
2700         free_netdev(netdev);
2701         return ret;
2702 }
2703
2704 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
2705  * ensure it is awake for probe and init. Request the line and reset the PHY.
2706  */
2707 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
2708 {
2709         unsigned long flags = GPIOF_OUT_INIT_HIGH;
2710         unsigned gpio = MINNOW_PHY_RESET_GPIO;
2711         int ret;
2712
2713         ret = devm_gpio_request_one(&pdev->dev, gpio, flags,
2714                                     "minnow_phy_reset");
2715         if (ret) {
2716                 dev_err(&pdev->dev,
2717                         "ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
2718                 return ret;
2719         }
2720
2721         gpio_set_value(gpio, 0);
2722         usleep_range(1250, 1500);
2723         gpio_set_value(gpio, 1);
2724         usleep_range(1250, 1500);
2725
2726         return ret;
2727 }
2728
2729 static struct pch_gbe_privdata pch_gbe_minnow_privdata = {
2730         .phy_tx_clk_delay = true,
2731         .phy_disable_hibernate = true,
2732         .platform_init = pch_gbe_minnow_platform_init,
2733 };
2734
2735 static const struct pci_device_id pch_gbe_pcidev_id[] = {
2736         {.vendor = PCI_VENDOR_ID_INTEL,
2737          .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2738          .subvendor = PCI_VENDOR_ID_CIRCUITCO,
2739          .subdevice = PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD,
2740          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2741          .class_mask = (0xFFFF00),
2742          .driver_data = (kernel_ulong_t)&pch_gbe_minnow_privdata
2743          },
2744         {.vendor = PCI_VENDOR_ID_INTEL,
2745          .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2746          .subvendor = PCI_ANY_ID,
2747          .subdevice = PCI_ANY_ID,
2748          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2749          .class_mask = (0xFFFF00)
2750          },
2751         {.vendor = PCI_VENDOR_ID_ROHM,
2752          .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2753          .subvendor = PCI_ANY_ID,
2754          .subdevice = PCI_ANY_ID,
2755          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2756          .class_mask = (0xFFFF00)
2757          },
2758         {.vendor = PCI_VENDOR_ID_ROHM,
2759          .device = PCI_DEVICE_ID_ROHM_ML7831_GBE,
2760          .subvendor = PCI_ANY_ID,
2761          .subdevice = PCI_ANY_ID,
2762          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2763          .class_mask = (0xFFFF00)
2764          },
2765         /* required last entry */
2766         {0}
2767 };
2768
2769 #ifdef CONFIG_PM
2770 static const struct dev_pm_ops pch_gbe_pm_ops = {
2771         .suspend = pch_gbe_suspend,
2772         .resume = pch_gbe_resume,
2773         .freeze = pch_gbe_suspend,
2774         .thaw = pch_gbe_resume,
2775         .poweroff = pch_gbe_suspend,
2776         .restore = pch_gbe_resume,
2777 };
2778 #endif
2779
2780 static const struct pci_error_handlers pch_gbe_err_handler = {
2781         .error_detected = pch_gbe_io_error_detected,
2782         .slot_reset = pch_gbe_io_slot_reset,
2783         .resume = pch_gbe_io_resume
2784 };
2785
2786 static struct pci_driver pch_gbe_driver = {
2787         .name = KBUILD_MODNAME,
2788         .id_table = pch_gbe_pcidev_id,
2789         .probe = pch_gbe_probe,
2790         .remove = pch_gbe_remove,
2791 #ifdef CONFIG_PM
2792         .driver.pm = &pch_gbe_pm_ops,
2793 #endif
2794         .shutdown = pch_gbe_shutdown,
2795         .err_handler = &pch_gbe_err_handler
2796 };
2797
2798
2799 static int __init pch_gbe_init_module(void)
2800 {
2801         int ret;
2802
2803         pr_info("EG20T PCH Gigabit Ethernet Driver - version %s\n",DRV_VERSION);
2804         ret = pci_register_driver(&pch_gbe_driver);
2805         if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2806                 if (copybreak == 0) {
2807                         pr_info("copybreak disabled\n");
2808                 } else {
2809                         pr_info("copybreak enabled for packets <= %u bytes\n",
2810                                 copybreak);
2811                 }
2812         }
2813         return ret;
2814 }
2815
2816 static void __exit pch_gbe_exit_module(void)
2817 {
2818         pci_unregister_driver(&pch_gbe_driver);
2819 }
2820
2821 module_init(pch_gbe_init_module);
2822 module_exit(pch_gbe_exit_module);
2823
2824 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2825 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
2826 MODULE_LICENSE("GPL");
2827 MODULE_VERSION(DRV_VERSION);
2828 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2829
2830 module_param(copybreak, uint, 0644);
2831 MODULE_PARM_DESC(copybreak,
2832         "Maximum size of packet that is copied to a new buffer on receive");
2833
2834 /* pch_gbe_main.c */