drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c

   1 /*
   2  * Copyright (C) 1999 - 2010 Intel Corporation.
   3  * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD.
   4  *
   5  * This code was derived from the Intel e1000e Linux driver.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "pch_gbe.h"
  21 #include "pch_gbe_phy.h"
  22 #include <linux/module.h>
  23 #include <linux/net_tstamp.h>
  24 #include <linux/ptp_classify.h>
  25 #include <linux/gpio.h>
  26
  27 #define DRV_VERSION     "1.01"
  28 const char pch_driver_version[] = DRV_VERSION;
  29
  30 #define PCH_GBE_MAR_ENTRIES             16
  31 #define PCH_GBE_SHORT_PKT               64
  32 #define DSC_INIT16                      0xC000
  33 #define PCH_GBE_DMA_ALIGN               0
  34 #define PCH_GBE_DMA_PADDING             2
  35 #define PCH_GBE_WATCHDOG_PERIOD         (5 * HZ)        /* watchdog time */
  36 #define PCH_GBE_PCI_BAR                 1
  37 #define PCH_GBE_RESERVE_MEMORY          0x200000        /* 2MB */
  38
  39 #define PCI_DEVICE_ID_INTEL_IOH1_GBE            0x8802
  40
  41 #define PCI_DEVICE_ID_ROHM_ML7223_GBE           0x8013
  42 #define PCI_DEVICE_ID_ROHM_ML7831_GBE           0x8802
  43
  44 #define PCH_GBE_TX_WEIGHT         64
  45 #define PCH_GBE_RX_WEIGHT         64
  46 #define PCH_GBE_RX_BUFFER_WRITE   16
  47
  48 /* Initialize the wake-on-LAN settings */
  49 #define PCH_GBE_WL_INIT_SETTING    (PCH_GBE_WLC_MP)
  50
  51 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
  52         PCH_GBE_CHIP_TYPE_INTERNAL | \
  53         PCH_GBE_RGMII_MODE_RGMII     \
  54         )
  55
  56 /* Ethertype field values */
  57 #define PCH_GBE_MAX_RX_BUFFER_SIZE      0x2880
  58 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE    10318
  59 #define PCH_GBE_FRAME_SIZE_2048         2048
  60 #define PCH_GBE_FRAME_SIZE_4096         4096
  61 #define PCH_GBE_FRAME_SIZE_8192         8192
  62
  63 #define PCH_GBE_GET_DESC(R, i, type)    (&(((struct type *)((R).desc))[i]))
  64 #define PCH_GBE_RX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
  65 #define PCH_GBE_TX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
  66 #define PCH_GBE_DESC_UNUSED(R) \
  67         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  68         (R)->next_to_clean - (R)->next_to_use - 1)
  69
  70 /* Pause packet value */
  71 #define PCH_GBE_PAUSE_PKT1_VALUE    0x00C28001
  72 #define PCH_GBE_PAUSE_PKT2_VALUE    0x00000100
  73 #define PCH_GBE_PAUSE_PKT4_VALUE    0x01000888
  74 #define PCH_GBE_PAUSE_PKT5_VALUE    0x0000FFFF
  75
  76
  77 /* This defines the bits that are set in the Interrupt Mask
  78  * Set/Read Register.  Each bit is documented below:
  79  *   o RXT0   = Receiver Timer Interrupt (ring 0)
  80  *   o TXDW   = Transmit Descriptor Written Back
  81  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
  82  *   o RXSEQ  = Receive Sequence Error
  83  *   o LSC    = Link Status Change
  84  */
  85 #define PCH_GBE_INT_ENABLE_MASK ( \
  86         PCH_GBE_INT_RX_DMA_CMPLT |    \
  87         PCH_GBE_INT_RX_DSC_EMP   |    \
  88         PCH_GBE_INT_RX_FIFO_ERR  |    \
  89         PCH_GBE_INT_WOL_DET      |    \
  90         PCH_GBE_INT_TX_CMPLT          \
  91         )
  92
  93 #define PCH_GBE_INT_DISABLE_ALL         0
  94
  95 /* Macros for ieee1588 */
  96 /* 0x40 Time Synchronization Channel Control Register Bits */
  97 #define MASTER_MODE   (1<<0)
  98 #define SLAVE_MODE    (0)
  99 #define V2_MODE       (1<<31)
 100 #define CAP_MODE0     (0)
 101 #define CAP_MODE2     (1<<17)
 102
 103 /* 0x44 Time Synchronization Channel Event Register Bits */
 104 #define TX_SNAPSHOT_LOCKED (1<<0)
 105 #define RX_SNAPSHOT_LOCKED (1<<1)
 106
 107 #define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81"
 108 #define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00"
 109
 110 #define MINNOW_PHY_RESET_GPIO           13
 111
 112 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
 113 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
 114                                int data);
 115 static void pch_gbe_set_multi(struct net_device *netdev);
 116
 117 static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
 118 {
 119         u8 *data = skb->data;
 120         unsigned int offset;
 121         u16 hi, id;
 122         u32 lo;
 123
 124         if (ptp_classify_raw(skb) == PTP_CLASS_NONE)
 125                 return 0;
 126
 127         offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
 128
 129         if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
 130                 return 0;
 131
 132         hi = get_unaligned_be16(data + offset + OFF_PTP_SOURCE_UUID + 0);
 133         lo = get_unaligned_be32(data + offset + OFF_PTP_SOURCE_UUID + 2);
 134         id = get_unaligned_be16(data + offset + OFF_PTP_SEQUENCE_ID);
 135
 136         return (uid_hi == hi && uid_lo == lo && seqid == id);
 137 }
 138
 139 static void
 140 pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
 141 {
 142         struct skb_shared_hwtstamps *shhwtstamps;
 143         struct pci_dev *pdev;
 144         u64 ns;
 145         u32 hi, lo, val;
 146
 147         if (!adapter->hwts_rx_en)
 148                 return;
 149
 150         /* Get ieee1588's dev information */
 151         pdev = adapter->ptp_pdev;
 152
 153         val = pch_ch_event_read(pdev);
 154
 155         if (!(val & RX_SNAPSHOT_LOCKED))
 156                 return;
 157
 158         lo = pch_src_uuid_lo_read(pdev);
 159         hi = pch_src_uuid_hi_read(pdev);
 160
 161         if (!pch_ptp_match(skb, hi, lo, hi >> 16))
 162                 goto out;
 163
 164         ns = pch_rx_snap_read(pdev);
 165
 166         shhwtstamps = skb_hwtstamps(skb);
 167         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 168         shhwtstamps->hwtstamp = ns_to_ktime(ns);
 169 out:
 170         pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED);
 171 }
 172
 173 static void
 174 pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
 175 {
 176         struct skb_shared_hwtstamps shhwtstamps;
 177         struct pci_dev *pdev;
 178         struct skb_shared_info *shtx;
 179         u64 ns;
 180         u32 cnt, val;
 181
 182         shtx = skb_shinfo(skb);
 183         if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en)))
 184                 return;
 185
 186         shtx->tx_flags |= SKBTX_IN_PROGRESS;
 187
 188         /* Get ieee1588's dev information */
 189         pdev = adapter->ptp_pdev;
 190
 191         /*
 192          * This really stinks, but we have to poll for the Tx time stamp.
 193          */
 194         for (cnt = 0; cnt < 100; cnt++) {
 195                 val = pch_ch_event_read(pdev);
 196                 if (val & TX_SNAPSHOT_LOCKED)
 197                         break;
 198                 udelay(1);
 199         }
 200         if (!(val & TX_SNAPSHOT_LOCKED)) {
 201                 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
 202                 return;
 203         }
 204
 205         ns = pch_tx_snap_read(pdev);
 206
 207         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 208         shhwtstamps.hwtstamp = ns_to_ktime(ns);
 209         skb_tstamp_tx(skb, &shhwtstamps);
 210
 211         pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED);
 212 }
 213
 214 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
 215 {
 216         struct hwtstamp_config cfg;
 217         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 218         struct pci_dev *pdev;
 219         u8 station[20];
 220
 221         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
 222                 return -EFAULT;
 223
 224         if (cfg.flags) /* reserved for future extensions */
 225                 return -EINVAL;
 226
 227         /* Get ieee1588's dev information */
 228         pdev = adapter->ptp_pdev;
 229
 230         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
 231                 return -ERANGE;
 232
 233         switch (cfg.rx_filter) {
 234         case HWTSTAMP_FILTER_NONE:
 235                 adapter->hwts_rx_en = 0;
 236                 break;
 237         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 238                 adapter->hwts_rx_en = 0;
 239                 pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0);
 240                 break;
 241         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 242                 adapter->hwts_rx_en = 1;
 243                 pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0);
 244                 break;
 245         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 246                 adapter->hwts_rx_en = 1;
 247                 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
 248                 strcpy(station, PTP_L4_MULTICAST_SA);
 249                 pch_set_station_address(station, pdev);
 250                 break;
 251         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 252                 adapter->hwts_rx_en = 1;
 253                 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
 254                 strcpy(station, PTP_L2_MULTICAST_SA);
 255                 pch_set_station_address(station, pdev);
 256                 break;
 257         default:
 258                 return -ERANGE;
 259         }
 260
 261         adapter->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
 262
 263         /* Clear out any old time stamps. */
 264         pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED);
 265
 266         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
 267 }
 268
 269 static inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
 270 {
 271         iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
 272 }
 273
 274 /**
 275  * pch_gbe_mac_read_mac_addr - Read MAC address
 276  * @hw:             Pointer to the HW structure
 277  * Returns:
 278  *      0:                      Successful.
 279  */
 280 static s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
 281 {
 282         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 283         u32  adr1a, adr1b;
 284
 285         adr1a = ioread32(&hw->reg->mac_adr[0].high);
 286         adr1b = ioread32(&hw->reg->mac_adr[0].low);
 287
 288         hw->mac.addr[0] = (u8)(adr1a & 0xFF);
 289         hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
 290         hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
 291         hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
 292         hw->mac.addr[4] = (u8)(adr1b & 0xFF);
 293         hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
 294
 295         netdev_dbg(adapter->netdev, "hw->mac.addr : %pM\n", hw->mac.addr);
 296         return 0;
 297 }
 298
 299 /**
 300  * pch_gbe_wait_clr_bit - Wait to clear a bit
 301  * @reg:        Pointer of register
 302  * @busy:       Busy bit
 303  */
 304 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
 305 {
 306         u32 tmp;
 307
 308         /* wait busy */
 309         tmp = 1000;
 310         while ((ioread32(reg) & bit) && --tmp)
 311                 cpu_relax();
 312         if (!tmp)
 313                 pr_err("Error: busy bit is not cleared\n");
 314 }
 315
 316 /**
 317  * pch_gbe_mac_mar_set - Set MAC address register
 318  * @hw:     Pointer to the HW structure
 319  * @addr:   Pointer to the MAC address
 320  * @index:  MAC address array register
 321  */
 322 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
 323 {
 324         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 325         u32 mar_low, mar_high, adrmask;
 326
 327         netdev_dbg(adapter->netdev, "index : 0x%x\n", index);
 328
 329         /*
 330          * HW expects these in little endian so we reverse the byte order
 331          * from network order (big endian) to little endian
 332          */
 333         mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
 334                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 335         mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
 336         /* Stop the MAC Address of index. */
 337         adrmask = ioread32(&hw->reg->ADDR_MASK);
 338         iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
 339         /* wait busy */
 340         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 341         /* Set the MAC address to the MAC address 1A/1B register */
 342         iowrite32(mar_high, &hw->reg->mac_adr[index].high);
 343         iowrite32(mar_low, &hw->reg->mac_adr[index].low);
 344         /* Start the MAC address of index */
 345         iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
 346         /* wait busy */
 347         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 348 }
 349
 350 /**
 351  * pch_gbe_mac_reset_hw - Reset hardware
 352  * @hw: Pointer to the HW structure
 353  */
 354 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
 355 {
 356         /* Read the MAC address. and store to the private data */
 357         pch_gbe_mac_read_mac_addr(hw);
 358         iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
 359         iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
 360         pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
 361         /* Setup the receive addresses */
 362         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
 363         return;
 364 }
 365
 366 static void pch_gbe_disable_mac_rx(struct pch_gbe_hw *hw)
 367 {
 368         u32 rctl;
 369         /* Disables Receive MAC */
 370         rctl = ioread32(&hw->reg->MAC_RX_EN);
 371         iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
 372 }
 373
 374 static void pch_gbe_enable_mac_rx(struct pch_gbe_hw *hw)
 375 {
 376         u32 rctl;
 377         /* Enables Receive MAC */
 378         rctl = ioread32(&hw->reg->MAC_RX_EN);
 379         iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
 380 }
 381
 382 /**
 383  * pch_gbe_mac_init_rx_addrs - Initialize receive address's
 384  * @hw: Pointer to the HW structure
 385  * @mar_count: Receive address registers
 386  */
 387 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
 388 {
 389         u32 i;
 390
 391         /* Setup the receive address */
 392         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
 393
 394         /* Zero out the other receive addresses */
 395         for (i = 1; i < mar_count; i++) {
 396                 iowrite32(0, &hw->reg->mac_adr[i].high);
 397                 iowrite32(0, &hw->reg->mac_adr[i].low);
 398         }
 399         iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
 400         /* wait busy */
 401         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 402 }
 403
 404 /**
 405  * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
 406  * @hw:             Pointer to the HW structure
 407  * Returns:
 408  *      0:                      Successful.
 409  *      Negative value:         Failed.
 410  */
 411 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
 412 {
 413         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 414         struct pch_gbe_mac_info *mac = &hw->mac;
 415         u32 rx_fctrl;
 416
 417         netdev_dbg(adapter->netdev, "mac->fc = %u\n", mac->fc);
 418
 419         rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
 420
 421         switch (mac->fc) {
 422         case PCH_GBE_FC_NONE:
 423                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 424                 mac->tx_fc_enable = false;
 425                 break;
 426         case PCH_GBE_FC_RX_PAUSE:
 427                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
 428                 mac->tx_fc_enable = false;
 429                 break;
 430         case PCH_GBE_FC_TX_PAUSE:
 431                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 432                 mac->tx_fc_enable = true;
 433                 break;
 434         case PCH_GBE_FC_FULL:
 435                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
 436                 mac->tx_fc_enable = true;
 437                 break;
 438         default:
 439                 netdev_err(adapter->netdev,
 440                            "Flow control param set incorrectly\n");
 441                 return -EINVAL;
 442         }
 443         if (mac->link_duplex == DUPLEX_HALF)
 444                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 445         iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
 446         netdev_dbg(adapter->netdev,
 447                    "RX_FCTRL reg : 0x%08x  mac->tx_fc_enable : %d\n",
 448                    ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
 449         return 0;
 450 }
 451
 452 /**
 453  * pch_gbe_mac_set_wol_event - Set wake-on-lan event
 454  * @hw:     Pointer to the HW structure
 455  * @wu_evt: Wake up event
 456  */
 457 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
 458 {
 459         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 460         u32 addr_mask;
 461
 462         netdev_dbg(adapter->netdev, "wu_evt : 0x%08x  ADDR_MASK reg : 0x%08x\n",
 463                    wu_evt, ioread32(&hw->reg->ADDR_MASK));
 464
 465         if (wu_evt) {
 466                 /* Set Wake-On-Lan address mask */
 467                 addr_mask = ioread32(&hw->reg->ADDR_MASK);
 468                 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
 469                 /* wait busy */
 470                 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
 471                 iowrite32(0, &hw->reg->WOL_ST);
 472                 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
 473                 iowrite32(0x02, &hw->reg->TCPIP_ACC);
 474                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
 475         } else {
 476                 iowrite32(0, &hw->reg->WOL_CTRL);
 477                 iowrite32(0, &hw->reg->WOL_ST);
 478         }
 479         return;
 480 }
 481
 482 /**
 483  * pch_gbe_mac_ctrl_miim - Control MIIM interface
 484  * @hw:   Pointer to the HW structure
 485  * @addr: Address of PHY
 486  * @dir:  Operetion. (Write or Read)
 487  * @reg:  Access register of PHY
 488  * @data: Write data.
 489  *
 490  * Returns: Read date.
 491  */
 492 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
 493                         u16 data)
 494 {
 495         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 496         u32 data_out = 0;
 497         unsigned int i;
 498         unsigned long flags;
 499
 500         spin_lock_irqsave(&hw->miim_lock, flags);
 501
 502         for (i = 100; i; --i) {
 503                 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
 504                         break;
 505                 udelay(20);
 506         }
 507         if (i == 0) {
 508                 netdev_err(adapter->netdev, "pch-gbe.miim won't go Ready\n");
 509                 spin_unlock_irqrestore(&hw->miim_lock, flags);
 510                 return 0;       /* No way to indicate timeout error */
 511         }
 512         iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
 513                   (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
 514                   dir | data), &hw->reg->MIIM);
 515         for (i = 0; i < 100; i++) {
 516                 udelay(20);
 517                 data_out = ioread32(&hw->reg->MIIM);
 518                 if ((data_out & PCH_GBE_MIIM_OPER_READY))
 519                         break;
 520         }
 521         spin_unlock_irqrestore(&hw->miim_lock, flags);
 522
 523         netdev_dbg(adapter->netdev, "PHY %s: reg=%d, data=0x%04X\n",
 524                    dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
 525                    dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
 526         return (u16) data_out;
 527 }
 528
 529 /**
 530  * pch_gbe_mac_set_pause_packet - Set pause packet
 531  * @hw:   Pointer to the HW structure
 532  */
 533 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
 534 {
 535         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 536         unsigned long tmp2, tmp3;
 537
 538         /* Set Pause packet */
 539         tmp2 = hw->mac.addr[1];
 540         tmp2 = (tmp2 << 8) | hw->mac.addr[0];
 541         tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
 542
 543         tmp3 = hw->mac.addr[5];
 544         tmp3 = (tmp3 << 8) | hw->mac.addr[4];
 545         tmp3 = (tmp3 << 8) | hw->mac.addr[3];
 546         tmp3 = (tmp3 << 8) | hw->mac.addr[2];
 547
 548         iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
 549         iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
 550         iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
 551         iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
 552         iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
 553
 554         /* Transmit Pause Packet */
 555         iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
 556
 557         netdev_dbg(adapter->netdev,
 558                    "PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
 559                    ioread32(&hw->reg->PAUSE_PKT1),
 560                    ioread32(&hw->reg->PAUSE_PKT2),
 561                    ioread32(&hw->reg->PAUSE_PKT3),
 562                    ioread32(&hw->reg->PAUSE_PKT4),
 563                    ioread32(&hw->reg->PAUSE_PKT5));
 564
 565         return;
 566 }
 567
 568
 569 /**
 570  * pch_gbe_alloc_queues - Allocate memory for all rings
 571  * @adapter:  Board private structure to initialize
 572  * Returns:
 573  *      0:      Successfully
 574  *      Negative value: Failed
 575  */
 576 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
 577 {
 578         adapter->tx_ring = devm_kzalloc(&adapter->pdev->dev,
 579                                         sizeof(*adapter->tx_ring), GFP_KERNEL);
 580         if (!adapter->tx_ring)
 581                 return -ENOMEM;
 582
 583         adapter->rx_ring = devm_kzalloc(&adapter->pdev->dev,
 584                                         sizeof(*adapter->rx_ring), GFP_KERNEL);
 585         if (!adapter->rx_ring)
 586                 return -ENOMEM;
 587         return 0;
 588 }
 589
 590 /**
 591  * pch_gbe_init_stats - Initialize status
 592  * @adapter:  Board private structure to initialize
 593  */
 594 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
 595 {
 596         memset(&adapter->stats, 0, sizeof(adapter->stats));
 597         return;
 598 }
 599
 600 /**
 601  * pch_gbe_init_phy - Initialize PHY
 602  * @adapter:  Board private structure to initialize
 603  * Returns:
 604  *      0:      Successfully
 605  *      Negative value: Failed
 606  */
 607 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
 608 {
 609         struct net_device *netdev = adapter->netdev;
 610         u32 addr;
 611         u16 bmcr, stat;
 612
 613         /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
 614         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
 615                 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
 616                 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
 617                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
 618                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
 619                 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
 620                         break;
 621         }
 622         adapter->hw.phy.addr = adapter->mii.phy_id;
 623         netdev_dbg(netdev, "phy_addr = %d\n", adapter->mii.phy_id);
 624         if (addr == PCH_GBE_PHY_REGS_LEN)
 625                 return -EAGAIN;
 626         /* Selected the phy and isolate the rest */
 627         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
 628                 if (addr != adapter->mii.phy_id) {
 629                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
 630                                            BMCR_ISOLATE);
 631                 } else {
 632                         bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
 633                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
 634                                            bmcr & ~BMCR_ISOLATE);
 635                 }
 636         }
 637
 638         /* MII setup */
 639         adapter->mii.phy_id_mask = 0x1F;
 640         adapter->mii.reg_num_mask = 0x1F;
 641         adapter->mii.dev = adapter->netdev;
 642         adapter->mii.mdio_read = pch_gbe_mdio_read;
 643         adapter->mii.mdio_write = pch_gbe_mdio_write;
 644         adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
 645         return 0;
 646 }
 647
 648 /**
 649  * pch_gbe_mdio_read - The read function for mii
 650  * @netdev: Network interface device structure
 651  * @addr:   Phy ID
 652  * @reg:    Access location
 653  * Returns:
 654  *      0:      Successfully
 655  *      Negative value: Failed
 656  */
 657 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
 658 {
 659         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 660         struct pch_gbe_hw *hw = &adapter->hw;
 661
 662         return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
 663                                      (u16) 0);
 664 }
 665
 666 /**
 667  * pch_gbe_mdio_write - The write function for mii
 668  * @netdev: Network interface device structure
 669  * @addr:   Phy ID (not used)
 670  * @reg:    Access location
 671  * @data:   Write data
 672  */
 673 static void pch_gbe_mdio_write(struct net_device *netdev,
 674                                int addr, int reg, int data)
 675 {
 676         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 677         struct pch_gbe_hw *hw = &adapter->hw;
 678
 679         pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
 680 }
 681
 682 /**
 683  * pch_gbe_reset_task - Reset processing at the time of transmission timeout
 684  * @work:  Pointer of board private structure
 685  */
 686 static void pch_gbe_reset_task(struct work_struct *work)
 687 {
 688         struct pch_gbe_adapter *adapter;
 689         adapter = container_of(work, struct pch_gbe_adapter, reset_task);
 690
 691         rtnl_lock();
 692         pch_gbe_reinit_locked(adapter);
 693         rtnl_unlock();
 694 }
 695
 696 /**
 697  * pch_gbe_reinit_locked- Re-initialization
 698  * @adapter:  Board private structure
 699  */
 700 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
 701 {
 702         pch_gbe_down(adapter);
 703         pch_gbe_up(adapter);
 704 }
 705
 706 /**
 707  * pch_gbe_reset - Reset GbE
 708  * @adapter:  Board private structure
 709  */
 710 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
 711 {
 712         struct net_device *netdev = adapter->netdev;
 713         struct pch_gbe_hw *hw = &adapter->hw;
 714         s32 ret_val;
 715
 716         pch_gbe_mac_reset_hw(hw);
 717         /* reprogram multicast address register after reset */
 718         pch_gbe_set_multi(netdev);
 719         /* Setup the receive address. */
 720         pch_gbe_mac_init_rx_addrs(hw, PCH_GBE_MAR_ENTRIES);
 721
 722         ret_val = pch_gbe_phy_get_id(hw);
 723         if (ret_val) {
 724                 netdev_err(adapter->netdev, "pch_gbe_phy_get_id error\n");
 725                 return;
 726         }
 727         pch_gbe_phy_init_setting(hw);
 728         /* Setup Mac interface option RGMII */
 729         pch_gbe_phy_set_rgmii(hw);
 730 }
 731
 732 /**
 733  * pch_gbe_free_irq - Free an interrupt
 734  * @adapter:  Board private structure
 735  */
 736 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
 737 {
 738         struct net_device *netdev = adapter->netdev;
 739
 740         free_irq(adapter->irq, netdev);
 741         pci_free_irq_vectors(adapter->pdev);
 742 }
 743
 744 /**
 745  * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
 746  * @adapter:  Board private structure
 747  */
 748 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
 749 {
 750         struct pch_gbe_hw *hw = &adapter->hw;
 751
 752         atomic_inc(&adapter->irq_sem);
 753         iowrite32(0, &hw->reg->INT_EN);
 754         ioread32(&hw->reg->INT_ST);
 755         synchronize_irq(adapter->irq);
 756
 757         netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
 758                    ioread32(&hw->reg->INT_EN));
 759 }
 760
 761 /**
 762  * pch_gbe_irq_enable - Enable default interrupt generation settings
 763  * @adapter:  Board private structure
 764  */
 765 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
 766 {
 767         struct pch_gbe_hw *hw = &adapter->hw;
 768
 769         if (likely(atomic_dec_and_test(&adapter->irq_sem)))
 770                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
 771         ioread32(&hw->reg->INT_ST);
 772         netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
 773                    ioread32(&hw->reg->INT_EN));
 774 }
 775
 776
 777
 778 /**
 779  * pch_gbe_setup_tctl - configure the Transmit control registers
 780  * @adapter:  Board private structure
 781  */
 782 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
 783 {
 784         struct pch_gbe_hw *hw = &adapter->hw;
 785         u32 tx_mode, tcpip;
 786
 787         tx_mode = PCH_GBE_TM_LONG_PKT |
 788                 PCH_GBE_TM_ST_AND_FD |
 789                 PCH_GBE_TM_SHORT_PKT |
 790                 PCH_GBE_TM_TH_TX_STRT_8 |
 791                 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
 792
 793         iowrite32(tx_mode, &hw->reg->TX_MODE);
 794
 795         tcpip = ioread32(&hw->reg->TCPIP_ACC);
 796         tcpip |= PCH_GBE_TX_TCPIPACC_EN;
 797         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
 798         return;
 799 }
 800
 801 /**
 802  * pch_gbe_configure_tx - Configure Transmit Unit after Reset
 803  * @adapter:  Board private structure
 804  */
 805 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
 806 {
 807         struct pch_gbe_hw *hw = &adapter->hw;
 808         u32 tdba, tdlen, dctrl;
 809
 810         netdev_dbg(adapter->netdev, "dma addr = 0x%08llx  size = 0x%08x\n",
 811                    (unsigned long long)adapter->tx_ring->dma,
 812                    adapter->tx_ring->size);
 813
 814         /* Setup the HW Tx Head and Tail descriptor pointers */
 815         tdba = adapter->tx_ring->dma;
 816         tdlen = adapter->tx_ring->size - 0x10;
 817         iowrite32(tdba, &hw->reg->TX_DSC_BASE);
 818         iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
 819         iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
 820
 821         /* Enables Transmission DMA */
 822         dctrl = ioread32(&hw->reg->DMA_CTRL);
 823         dctrl |= PCH_GBE_TX_DMA_EN;
 824         iowrite32(dctrl, &hw->reg->DMA_CTRL);
 825 }
 826
 827 /**
 828  * pch_gbe_setup_rctl - Configure the receive control registers
 829  * @adapter:  Board private structure
 830  */
 831 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
 832 {
 833         struct pch_gbe_hw *hw = &adapter->hw;
 834         u32 rx_mode, tcpip;
 835
 836         rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
 837         PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
 838
 839         iowrite32(rx_mode, &hw->reg->RX_MODE);
 840
 841         tcpip = ioread32(&hw->reg->TCPIP_ACC);
 842
 843         tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
 844         tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
 845         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
 846         return;
 847 }
 848
 849 /**
 850  * pch_gbe_configure_rx - Configure Receive Unit after Reset
 851  * @adapter:  Board private structure
 852  */
 853 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
 854 {
 855         struct pch_gbe_hw *hw = &adapter->hw;
 856         u32 rdba, rdlen, rxdma;
 857
 858         netdev_dbg(adapter->netdev, "dma adr = 0x%08llx  size = 0x%08x\n",
 859                    (unsigned long long)adapter->rx_ring->dma,
 860                    adapter->rx_ring->size);
 861
 862         pch_gbe_mac_force_mac_fc(hw);
 863
 864         pch_gbe_disable_mac_rx(hw);
 865
 866         /* Disables Receive DMA */
 867         rxdma = ioread32(&hw->reg->DMA_CTRL);
 868         rxdma &= ~PCH_GBE_RX_DMA_EN;
 869         iowrite32(rxdma, &hw->reg->DMA_CTRL);
 870
 871         netdev_dbg(adapter->netdev,
 872                    "MAC_RX_EN reg = 0x%08x  DMA_CTRL reg = 0x%08x\n",
 873                    ioread32(&hw->reg->MAC_RX_EN),
 874                    ioread32(&hw->reg->DMA_CTRL));
 875
 876         /* Setup the HW Rx Head and Tail Descriptor Pointers and
 877          * the Base and Length of the Rx Descriptor Ring */
 878         rdba = adapter->rx_ring->dma;
 879         rdlen = adapter->rx_ring->size - 0x10;
 880         iowrite32(rdba, &hw->reg->RX_DSC_BASE);
 881         iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
 882         iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
 883 }
 884
 885 /**
 886  * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
 887  * @adapter:     Board private structure
 888  * @buffer_info: Buffer information structure
 889  */
 890 static void pch_gbe_unmap_and_free_tx_resource(
 891         struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
 892 {
 893         if (buffer_info->mapped) {
 894                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
 895                                  buffer_info->length, DMA_TO_DEVICE);
 896                 buffer_info->mapped = false;
 897         }
 898         if (buffer_info->skb) {
 899                 dev_kfree_skb_any(buffer_info->skb);
 900                 buffer_info->skb = NULL;
 901         }
 902 }
 903
 904 /**
 905  * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
 906  * @adapter:      Board private structure
 907  * @buffer_info:  Buffer information structure
 908  */
 909 static void pch_gbe_unmap_and_free_rx_resource(
 910                                         struct pch_gbe_adapter *adapter,
 911                                         struct pch_gbe_buffer *buffer_info)
 912 {
 913         if (buffer_info->mapped) {
 914                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
 915                                  buffer_info->length, DMA_FROM_DEVICE);
 916                 buffer_info->mapped = false;
 917         }
 918         if (buffer_info->skb) {
 919                 dev_kfree_skb_any(buffer_info->skb);
 920                 buffer_info->skb = NULL;
 921         }
 922 }
 923
 924 /**
 925  * pch_gbe_clean_tx_ring - Free Tx Buffers
 926  * @adapter:  Board private structure
 927  * @tx_ring:  Ring to be cleaned
 928  */
 929 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
 930                                    struct pch_gbe_tx_ring *tx_ring)
 931 {
 932         struct pch_gbe_hw *hw = &adapter->hw;
 933         struct pch_gbe_buffer *buffer_info;
 934         unsigned long size;
 935         unsigned int i;
 936
 937         /* Free all the Tx ring sk_buffs */
 938         for (i = 0; i < tx_ring->count; i++) {
 939                 buffer_info = &tx_ring->buffer_info[i];
 940                 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
 941         }
 942         netdev_dbg(adapter->netdev,
 943                    "call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
 944
 945         size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
 946         memset(tx_ring->buffer_info, 0, size);
 947
 948         /* Zero out the descriptor ring */
 949         memset(tx_ring->desc, 0, tx_ring->size);
 950         tx_ring->next_to_use = 0;
 951         tx_ring->next_to_clean = 0;
 952         iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
 953         iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
 954 }
 955
 956 /**
 957  * pch_gbe_clean_rx_ring - Free Rx Buffers
 958  * @adapter:  Board private structure
 959  * @rx_ring:  Ring to free buffers from
 960  */
 961 static void
 962 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
 963                       struct pch_gbe_rx_ring *rx_ring)
 964 {
 965         struct pch_gbe_hw *hw = &adapter->hw;
 966         struct pch_gbe_buffer *buffer_info;
 967         unsigned long size;
 968         unsigned int i;
 969
 970         /* Free all the Rx ring sk_buffs */
 971         for (i = 0; i < rx_ring->count; i++) {
 972                 buffer_info = &rx_ring->buffer_info[i];
 973                 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
 974         }
 975         netdev_dbg(adapter->netdev,
 976                    "call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
 977         size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
 978         memset(rx_ring->buffer_info, 0, size);
 979
 980         /* Zero out the descriptor ring */
 981         memset(rx_ring->desc, 0, rx_ring->size);
 982         rx_ring->next_to_clean = 0;
 983         rx_ring->next_to_use = 0;
 984         iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
 985         iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
 986 }
 987
 988 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
 989                                     u16 duplex)
 990 {
 991         struct pch_gbe_hw *hw = &adapter->hw;
 992         unsigned long rgmii = 0;
 993
 994         /* Set the RGMII control. */
 995         switch (speed) {
 996         case SPEED_10:
 997                 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
 998                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
 999                 break;
1000         case SPEED_100:
1001                 rgmii = (PCH_GBE_RGMII_RATE_25M |
1002                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
1003                 break;
1004         case SPEED_1000:
1005                 rgmii = (PCH_GBE_RGMII_RATE_125M |
1006                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
1007                 break;
1008         }
1009         iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1010 }
1011 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
1012                               u16 duplex)
1013 {
1014         struct net_device *netdev = adapter->netdev;
1015         struct pch_gbe_hw *hw = &adapter->hw;
1016         unsigned long mode = 0;
1017
1018         /* Set the communication mode */
1019         switch (speed) {
1020         case SPEED_10:
1021                 mode = PCH_GBE_MODE_MII_ETHER;
1022                 netdev->tx_queue_len = 10;
1023                 break;
1024         case SPEED_100:
1025                 mode = PCH_GBE_MODE_MII_ETHER;
1026                 netdev->tx_queue_len = 100;
1027                 break;
1028         case SPEED_1000:
1029                 mode = PCH_GBE_MODE_GMII_ETHER;
1030                 break;
1031         }
1032         if (duplex == DUPLEX_FULL)
1033                 mode |= PCH_GBE_MODE_FULL_DUPLEX;
1034         else
1035                 mode |= PCH_GBE_MODE_HALF_DUPLEX;
1036         iowrite32(mode, &hw->reg->MODE);
1037 }
1038
1039 /**
1040  * pch_gbe_watchdog - Watchdog process
1041  * @data:  Board private structure
1042  */
1043 static void pch_gbe_watchdog(struct timer_list *t)
1044 {
1045         struct pch_gbe_adapter *adapter = from_timer(adapter, t,
1046                                                      watchdog_timer);
1047         struct net_device *netdev = adapter->netdev;
1048         struct pch_gbe_hw *hw = &adapter->hw;
1049
1050         netdev_dbg(netdev, "right now = %ld\n", jiffies);
1051
1052         pch_gbe_update_stats(adapter);
1053         if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
1054                 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
1055                 netdev->tx_queue_len = adapter->tx_queue_len;
1056                 /* mii library handles link maintenance tasks */
1057                 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
1058                         netdev_err(netdev, "ethtool get setting Error\n");
1059                         mod_timer(&adapter->watchdog_timer,
1060                                   round_jiffies(jiffies +
1061                                                 PCH_GBE_WATCHDOG_PERIOD));
1062                         return;
1063                 }
1064                 hw->mac.link_speed = ethtool_cmd_speed(&cmd);
1065                 hw->mac.link_duplex = cmd.duplex;
1066                 /* Set the RGMII control. */
1067                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
1068                                                 hw->mac.link_duplex);
1069                 /* Set the communication mode */
1070                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
1071                                  hw->mac.link_duplex);
1072                 netdev_dbg(netdev,
1073                            "Link is Up %d Mbps %s-Duplex\n",
1074                            hw->mac.link_speed,
1075                            cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1076                 netif_carrier_on(netdev);
1077                 netif_wake_queue(netdev);
1078         } else if ((!mii_link_ok(&adapter->mii)) &&
1079                    (netif_carrier_ok(netdev))) {
1080                 netdev_dbg(netdev, "NIC Link is Down\n");
1081                 hw->mac.link_speed = SPEED_10;
1082                 hw->mac.link_duplex = DUPLEX_HALF;
1083                 netif_carrier_off(netdev);
1084                 netif_stop_queue(netdev);
1085         }
1086         mod_timer(&adapter->watchdog_timer,
1087                   round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
1088 }
1089
1090 /**
1091  * pch_gbe_tx_queue - Carry out queuing of the transmission data
1092  * @adapter:  Board private structure
1093  * @tx_ring:  Tx descriptor ring structure
1094  * @skb:      Sockt buffer structure
1095  */
1096 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
1097                               struct pch_gbe_tx_ring *tx_ring,
1098                               struct sk_buff *skb)
1099 {
1100         struct pch_gbe_hw *hw = &adapter->hw;
1101         struct pch_gbe_tx_desc *tx_desc;
1102         struct pch_gbe_buffer *buffer_info;
1103         struct sk_buff *tmp_skb;
1104         unsigned int frame_ctrl;
1105         unsigned int ring_num;
1106
1107         /*-- Set frame control --*/
1108         frame_ctrl = 0;
1109         if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
1110                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
1111         if (skb->ip_summed == CHECKSUM_NONE)
1112                 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1113
1114         /* Performs checksum processing */
1115         /*
1116          * It is because the hardware accelerator does not support a checksum,
1117          * when the received data size is less than 64 bytes.
1118          */
1119         if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
1120                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
1121                               PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1122                 if (skb->protocol == htons(ETH_P_IP)) {
1123                         struct iphdr *iph = ip_hdr(skb);
1124                         unsigned int offset;
1125                         offset = skb_transport_offset(skb);
1126                         if (iph->protocol == IPPROTO_TCP) {
1127                                 skb->csum = 0;
1128                                 tcp_hdr(skb)->check = 0;
1129                                 skb->csum = skb_checksum(skb, offset,
1130                                                          skb->len - offset, 0);
1131                                 tcp_hdr(skb)->check =
1132                                         csum_tcpudp_magic(iph->saddr,
1133                                                           iph->daddr,
1134                                                           skb->len - offset,
1135                                                           IPPROTO_TCP,
1136                                                           skb->csum);
1137                         } else if (iph->protocol == IPPROTO_UDP) {
1138                                 skb->csum = 0;
1139                                 udp_hdr(skb)->check = 0;
1140                                 skb->csum =
1141                                         skb_checksum(skb, offset,
1142                                                      skb->len - offset, 0);
1143                                 udp_hdr(skb)->check =
1144                                         csum_tcpudp_magic(iph->saddr,
1145                                                           iph->daddr,
1146                                                           skb->len - offset,
1147                                                           IPPROTO_UDP,
1148                                                           skb->csum);
1149                         }
1150                 }
1151         }
1152
1153         ring_num = tx_ring->next_to_use;
1154         if (unlikely((ring_num + 1) == tx_ring->count))
1155                 tx_ring->next_to_use = 0;
1156         else
1157                 tx_ring->next_to_use = ring_num + 1;
1158
1159
1160         buffer_info = &tx_ring->buffer_info[ring_num];
1161         tmp_skb = buffer_info->skb;
1162
1163         /* [Header:14][payload] ---> [Header:14][paddong:2][payload]    */
1164         memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1165         tmp_skb->data[ETH_HLEN] = 0x00;
1166         tmp_skb->data[ETH_HLEN + 1] = 0x00;
1167         tmp_skb->len = skb->len;
1168         memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1169                (skb->len - ETH_HLEN));
1170         /*-- Set Buffer information --*/
1171         buffer_info->length = tmp_skb->len;
1172         buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1173                                           buffer_info->length,
1174                                           DMA_TO_DEVICE);
1175         if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1176                 netdev_err(adapter->netdev, "TX DMA map failed\n");
1177                 buffer_info->dma = 0;
1178                 buffer_info->time_stamp = 0;
1179                 tx_ring->next_to_use = ring_num;
1180                 return;
1181         }
1182         buffer_info->mapped = true;
1183         buffer_info->time_stamp = jiffies;
1184
1185         /*-- Set Tx descriptor --*/
1186         tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1187         tx_desc->buffer_addr = (buffer_info->dma);
1188         tx_desc->length = (tmp_skb->len);
1189         tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1190         tx_desc->tx_frame_ctrl = (frame_ctrl);
1191         tx_desc->gbec_status = (DSC_INIT16);
1192
1193         if (unlikely(++ring_num == tx_ring->count))
1194                 ring_num = 0;
1195
1196         /* Update software pointer of TX descriptor */
1197         iowrite32(tx_ring->dma +
1198                   (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1199                   &hw->reg->TX_DSC_SW_P);
1200
1201         pch_tx_timestamp(adapter, skb);
1202
1203         dev_kfree_skb_any(skb);
1204 }
1205
1206 /**
1207  * pch_gbe_update_stats - Update the board statistics counters
1208  * @adapter:  Board private structure
1209  */
1210 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1211 {
1212         struct net_device *netdev = adapter->netdev;
1213         struct pci_dev *pdev = adapter->pdev;
1214         struct pch_gbe_hw_stats *stats = &adapter->stats;
1215         unsigned long flags;
1216
1217         /*
1218          * Prevent stats update while adapter is being reset, or if the pci
1219          * connection is down.
1220          */
1221         if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1222                 return;
1223
1224         spin_lock_irqsave(&adapter->stats_lock, flags);
1225
1226         /* Update device status "adapter->stats" */
1227         stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1228         stats->tx_errors = stats->tx_length_errors +
1229             stats->tx_aborted_errors +
1230             stats->tx_carrier_errors + stats->tx_timeout_count;
1231
1232         /* Update network device status "adapter->net_stats" */
1233         netdev->stats.rx_packets = stats->rx_packets;
1234         netdev->stats.rx_bytes = stats->rx_bytes;
1235         netdev->stats.rx_dropped = stats->rx_dropped;
1236         netdev->stats.tx_packets = stats->tx_packets;
1237         netdev->stats.tx_bytes = stats->tx_bytes;
1238         netdev->stats.tx_dropped = stats->tx_dropped;
1239         /* Fill out the OS statistics structure */
1240         netdev->stats.multicast = stats->multicast;
1241         netdev->stats.collisions = stats->collisions;
1242         /* Rx Errors */
1243         netdev->stats.rx_errors = stats->rx_errors;
1244         netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1245         netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1246         /* Tx Errors */
1247         netdev->stats.tx_errors = stats->tx_errors;
1248         netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1249         netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1250
1251         spin_unlock_irqrestore(&adapter->stats_lock, flags);
1252 }
1253
1254 static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw)
1255 {
1256         u32 rxdma;
1257
1258         /* Disable Receive DMA */
1259         rxdma = ioread32(&hw->reg->DMA_CTRL);
1260         rxdma &= ~PCH_GBE_RX_DMA_EN;
1261         iowrite32(rxdma, &hw->reg->DMA_CTRL);
1262 }
1263
1264 static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw)
1265 {
1266         u32 rxdma;
1267
1268         /* Enables Receive DMA */
1269         rxdma = ioread32(&hw->reg->DMA_CTRL);
1270         rxdma |= PCH_GBE_RX_DMA_EN;
1271         iowrite32(rxdma, &hw->reg->DMA_CTRL);
1272 }
1273
1274 /**
1275  * pch_gbe_intr - Interrupt Handler
1276  * @irq:   Interrupt number
1277  * @data:  Pointer to a network interface device structure
1278  * Returns:
1279  *      - IRQ_HANDLED:  Our interrupt
1280  *      - IRQ_NONE:     Not our interrupt
1281  */
1282 static irqreturn_t pch_gbe_intr(int irq, void *data)
1283 {
1284         struct net_device *netdev = data;
1285         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1286         struct pch_gbe_hw *hw = &adapter->hw;
1287         u32 int_st;
1288         u32 int_en;
1289
1290         /* Check request status */
1291         int_st = ioread32(&hw->reg->INT_ST);
1292         int_st = int_st & ioread32(&hw->reg->INT_EN);
1293         /* When request status is no interruption factor */
1294         if (unlikely(!int_st))
1295                 return IRQ_NONE;        /* Not our interrupt. End processing. */
1296         netdev_dbg(netdev, "%s occur int_st = 0x%08x\n", __func__, int_st);
1297         if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1298                 adapter->stats.intr_rx_frame_err_count++;
1299         if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1300                 if (!adapter->rx_stop_flag) {
1301                         adapter->stats.intr_rx_fifo_err_count++;
1302                         netdev_dbg(netdev, "Rx fifo over run\n");
1303                         adapter->rx_stop_flag = true;
1304                         int_en = ioread32(&hw->reg->INT_EN);
1305                         iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
1306                                   &hw->reg->INT_EN);
1307                         pch_gbe_disable_dma_rx(&adapter->hw);
1308                         int_st |= ioread32(&hw->reg->INT_ST);
1309                         int_st = int_st & ioread32(&hw->reg->INT_EN);
1310                 }
1311         if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1312                 adapter->stats.intr_rx_dma_err_count++;
1313         if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1314                 adapter->stats.intr_tx_fifo_err_count++;
1315         if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1316                 adapter->stats.intr_tx_dma_err_count++;
1317         if (int_st & PCH_GBE_INT_TCPIP_ERR)
1318                 adapter->stats.intr_tcpip_err_count++;
1319         /* When Rx descriptor is empty  */
1320         if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1321                 adapter->stats.intr_rx_dsc_empty_count++;
1322                 netdev_dbg(netdev, "Rx descriptor is empty\n");
1323                 int_en = ioread32(&hw->reg->INT_EN);
1324                 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1325                 if (hw->mac.tx_fc_enable) {
1326                         /* Set Pause packet */
1327                         pch_gbe_mac_set_pause_packet(hw);
1328                 }
1329         }
1330
1331         /* When request status is Receive interruption */
1332         if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) ||
1333             (adapter->rx_stop_flag)) {
1334                 if (likely(napi_schedule_prep(&adapter->napi))) {
1335                         /* Enable only Rx Descriptor empty */
1336                         atomic_inc(&adapter->irq_sem);
1337                         int_en = ioread32(&hw->reg->INT_EN);
1338                         int_en &=
1339                             ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1340                         iowrite32(int_en, &hw->reg->INT_EN);
1341                         /* Start polling for NAPI */
1342                         __napi_schedule(&adapter->napi);
1343                 }
1344         }
1345         netdev_dbg(netdev, "return = 0x%08x  INT_EN reg = 0x%08x\n",
1346                    IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1347         return IRQ_HANDLED;
1348 }
1349
1350 /**
1351  * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1352  * @adapter:       Board private structure
1353  * @rx_ring:       Rx descriptor ring
1354  * @cleaned_count: Cleaned count
1355  */
1356 static void
1357 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1358                          struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1359 {
1360         struct net_device *netdev = adapter->netdev;
1361         struct pci_dev *pdev = adapter->pdev;
1362         struct pch_gbe_hw *hw = &adapter->hw;
1363         struct pch_gbe_rx_desc *rx_desc;
1364         struct pch_gbe_buffer *buffer_info;
1365         struct sk_buff *skb;
1366         unsigned int i;
1367         unsigned int bufsz;
1368
1369         bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1370         i = rx_ring->next_to_use;
1371
1372         while ((cleaned_count--)) {
1373                 buffer_info = &rx_ring->buffer_info[i];
1374                 skb = netdev_alloc_skb(netdev, bufsz);
1375                 if (unlikely(!skb)) {
1376                         /* Better luck next round */
1377                         adapter->stats.rx_alloc_buff_failed++;
1378                         break;
1379                 }
1380                 /* align */
1381                 skb_reserve(skb, NET_IP_ALIGN);
1382                 buffer_info->skb = skb;
1383
1384                 buffer_info->dma = dma_map_single(&pdev->dev,
1385                                                   buffer_info->rx_buffer,
1386                                                   buffer_info->length,
1387                                                   DMA_FROM_DEVICE);
1388                 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1389                         dev_kfree_skb(skb);
1390                         buffer_info->skb = NULL;
1391                         buffer_info->dma = 0;
1392                         adapter->stats.rx_alloc_buff_failed++;
1393                         break; /* while !buffer_info->skb */
1394                 }
1395                 buffer_info->mapped = true;
1396                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1397                 rx_desc->buffer_addr = (buffer_info->dma);
1398                 rx_desc->gbec_status = DSC_INIT16;
1399
1400                 netdev_dbg(netdev,
1401                            "i = %d  buffer_info->dma = 0x08%llx  buffer_info->length = 0x%x\n",
1402                            i, (unsigned long long)buffer_info->dma,
1403                            buffer_info->length);
1404
1405                 if (unlikely(++i == rx_ring->count))
1406                         i = 0;
1407         }
1408         if (likely(rx_ring->next_to_use != i)) {
1409                 rx_ring->next_to_use = i;
1410                 if (unlikely(i-- == 0))
1411                         i = (rx_ring->count - 1);
1412                 iowrite32(rx_ring->dma +
1413                           (int)sizeof(struct pch_gbe_rx_desc) * i,
1414                           &hw->reg->RX_DSC_SW_P);
1415         }
1416         return;
1417 }
1418
1419 static int
1420 pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter,
1421                          struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1422 {
1423         struct pci_dev *pdev = adapter->pdev;
1424         struct pch_gbe_buffer *buffer_info;
1425         unsigned int i;
1426         unsigned int bufsz;
1427         unsigned int size;
1428
1429         bufsz = adapter->rx_buffer_len;
1430
1431         size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY;
1432         rx_ring->rx_buff_pool =
1433                 dma_zalloc_coherent(&pdev->dev, size,
1434                                     &rx_ring->rx_buff_pool_logic, GFP_KERNEL);
1435         if (!rx_ring->rx_buff_pool)
1436                 return -ENOMEM;
1437
1438         rx_ring->rx_buff_pool_size = size;
1439         for (i = 0; i < rx_ring->count; i++) {
1440                 buffer_info = &rx_ring->buffer_info[i];
1441                 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i;
1442                 buffer_info->length = bufsz;
1443         }
1444         return 0;
1445 }
1446
1447 /**
1448  * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1449  * @adapter:   Board private structure
1450  * @tx_ring:   Tx descriptor ring
1451  */
1452 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1453                                         struct pch_gbe_tx_ring *tx_ring)
1454 {
1455         struct pch_gbe_buffer *buffer_info;
1456         struct sk_buff *skb;
1457         unsigned int i;
1458         unsigned int bufsz;
1459         struct pch_gbe_tx_desc *tx_desc;
1460
1461         bufsz =
1462             adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1463
1464         for (i = 0; i < tx_ring->count; i++) {
1465                 buffer_info = &tx_ring->buffer_info[i];
1466                 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1467                 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1468                 buffer_info->skb = skb;
1469                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1470                 tx_desc->gbec_status = (DSC_INIT16);
1471         }
1472         return;
1473 }
1474
1475 /**
1476  * pch_gbe_clean_tx - Reclaim resources after transmit completes
1477  * @adapter:   Board private structure
1478  * @tx_ring:   Tx descriptor ring
1479  * Returns:
1480  *      true:  Cleaned the descriptor
1481  *      false: Not cleaned the descriptor
1482  */
1483 static bool
1484 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1485                  struct pch_gbe_tx_ring *tx_ring)
1486 {
1487         struct pch_gbe_tx_desc *tx_desc;
1488         struct pch_gbe_buffer *buffer_info;
1489         struct sk_buff *skb;
1490         unsigned int i;
1491         unsigned int cleaned_count = 0;
1492         bool cleaned = false;
1493         int unused, thresh;
1494
1495         netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1496                    tx_ring->next_to_clean);
1497
1498         i = tx_ring->next_to_clean;
1499         tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1500         netdev_dbg(adapter->netdev, "gbec_status:0x%04x  dma_status:0x%04x\n",
1501                    tx_desc->gbec_status, tx_desc->dma_status);
1502
1503         unused = PCH_GBE_DESC_UNUSED(tx_ring);
1504         thresh = tx_ring->count - PCH_GBE_TX_WEIGHT;
1505         if ((tx_desc->gbec_status == DSC_INIT16) && (unused < thresh))
1506         {  /* current marked clean, tx queue filling up, do extra clean */
1507                 int j, k;
1508                 if (unused < 8) {  /* tx queue nearly full */
1509                         netdev_dbg(adapter->netdev,
1510                                    "clean_tx: transmit queue warning (%x,%x) unused=%d\n",
1511                                    tx_ring->next_to_clean, tx_ring->next_to_use,
1512                                    unused);
1513                 }
1514
1515                 /* current marked clean, scan for more that need cleaning. */
1516                 k = i;
1517                 for (j = 0; j < PCH_GBE_TX_WEIGHT; j++)
1518                 {
1519                         tx_desc = PCH_GBE_TX_DESC(*tx_ring, k);
1520                         if (tx_desc->gbec_status != DSC_INIT16) break; /*found*/
1521                         if (++k >= tx_ring->count) k = 0;  /*increment, wrap*/
1522                 }
1523                 if (j < PCH_GBE_TX_WEIGHT) {
1524                         netdev_dbg(adapter->netdev,
1525                                    "clean_tx: unused=%d loops=%d found tx_desc[%x,%x:%x].gbec_status=%04x\n",
1526                                    unused, j, i, k, tx_ring->next_to_use,
1527                                    tx_desc->gbec_status);
1528                         i = k;  /*found one to clean, usu gbec_status==2000.*/
1529                 }
1530         }
1531
1532         while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1533                 netdev_dbg(adapter->netdev, "gbec_status:0x%04x\n",
1534                            tx_desc->gbec_status);
1535                 buffer_info = &tx_ring->buffer_info[i];
1536                 skb = buffer_info->skb;
1537                 cleaned = true;
1538
1539                 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1540                         adapter->stats.tx_aborted_errors++;
1541                         netdev_err(adapter->netdev, "Transfer Abort Error\n");
1542                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1543                           ) {
1544                         adapter->stats.tx_carrier_errors++;
1545                         netdev_err(adapter->netdev,
1546                                    "Transfer Carrier Sense Error\n");
1547                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1548                           ) {
1549                         adapter->stats.tx_aborted_errors++;
1550                         netdev_err(adapter->netdev,
1551                                    "Transfer Collision Abort Error\n");
1552                 } else if ((tx_desc->gbec_status &
1553                             (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1554                              PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1555                         adapter->stats.collisions++;
1556                         adapter->stats.tx_packets++;
1557                         adapter->stats.tx_bytes += skb->len;
1558                         netdev_dbg(adapter->netdev, "Transfer Collision\n");
1559                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1560                           ) {
1561                         adapter->stats.tx_packets++;
1562                         adapter->stats.tx_bytes += skb->len;
1563                 }
1564                 if (buffer_info->mapped) {
1565                         netdev_dbg(adapter->netdev,
1566                                    "unmap buffer_info->dma : %d\n", i);
1567                         dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1568                                          buffer_info->length, DMA_TO_DEVICE);
1569                         buffer_info->mapped = false;
1570                 }
1571                 if (buffer_info->skb) {
1572                         netdev_dbg(adapter->netdev,
1573                                    "trim buffer_info->skb : %d\n", i);
1574                         skb_trim(buffer_info->skb, 0);
1575                 }
1576                 tx_desc->gbec_status = DSC_INIT16;
1577                 if (unlikely(++i == tx_ring->count))
1578                         i = 0;
1579                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1580
1581                 /* weight of a sort for tx, to avoid endless transmit cleanup */
1582                 if (cleaned_count++ == PCH_GBE_TX_WEIGHT) {
1583                         cleaned = false;
1584                         break;
1585                 }
1586         }
1587         netdev_dbg(adapter->netdev,
1588                    "called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1589                    cleaned_count);
1590         if (cleaned_count > 0)  { /*skip this if nothing cleaned*/
1591                 /* Recover from running out of Tx resources in xmit_frame */
1592                 netif_tx_lock(adapter->netdev);
1593                 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev))))
1594                 {
1595                         netif_wake_queue(adapter->netdev);
1596                         adapter->stats.tx_restart_count++;
1597                         netdev_dbg(adapter->netdev, "Tx wake queue\n");
1598                 }
1599
1600                 tx_ring->next_to_clean = i;
1601
1602                 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1603                            tx_ring->next_to_clean);
1604                 netif_tx_unlock(adapter->netdev);
1605         }
1606         return cleaned;
1607 }
1608
1609 /**
1610  * pch_gbe_clean_rx - Send received data up the network stack; legacy
1611  * @adapter:     Board private structure
1612  * @rx_ring:     Rx descriptor ring
1613  * @work_done:   Completed count
1614  * @work_to_do:  Request count
1615  * Returns:
1616  *      true:  Cleaned the descriptor
1617  *      false: Not cleaned the descriptor
1618  */
1619 static bool
1620 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1621                  struct pch_gbe_rx_ring *rx_ring,
1622                  int *work_done, int work_to_do)
1623 {
1624         struct net_device *netdev = adapter->netdev;
1625         struct pci_dev *pdev = adapter->pdev;
1626         struct pch_gbe_buffer *buffer_info;
1627         struct pch_gbe_rx_desc *rx_desc;
1628         u32 length;
1629         unsigned int i;
1630         unsigned int cleaned_count = 0;
1631         bool cleaned = false;
1632         struct sk_buff *skb;
1633         u8 dma_status;
1634         u16 gbec_status;
1635         u32 tcp_ip_status;
1636
1637         i = rx_ring->next_to_clean;
1638
1639         while (*work_done < work_to_do) {
1640                 /* Check Rx descriptor status */
1641                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1642                 if (rx_desc->gbec_status == DSC_INIT16)
1643                         break;
1644                 cleaned = true;
1645                 cleaned_count++;
1646
1647                 dma_status = rx_desc->dma_status;
1648                 gbec_status = rx_desc->gbec_status;
1649                 tcp_ip_status = rx_desc->tcp_ip_status;
1650                 rx_desc->gbec_status = DSC_INIT16;
1651                 buffer_info = &rx_ring->buffer_info[i];
1652                 skb = buffer_info->skb;
1653                 buffer_info->skb = NULL;
1654
1655                 /* unmap dma */
1656                 dma_unmap_single(&pdev->dev, buffer_info->dma,
1657                                    buffer_info->length, DMA_FROM_DEVICE);
1658                 buffer_info->mapped = false;
1659
1660                 netdev_dbg(netdev,
1661                            "RxDecNo = 0x%04x  Status[DMA:0x%02x GBE:0x%04x TCP:0x%08x]  BufInf = 0x%p\n",
1662                            i, dma_status, gbec_status, tcp_ip_status,
1663                            buffer_info);
1664                 /* Error check */
1665                 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1666                         adapter->stats.rx_frame_errors++;
1667                         netdev_err(netdev, "Receive Not Octal Error\n");
1668                 } else if (unlikely(gbec_status &
1669                                 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1670                         adapter->stats.rx_frame_errors++;
1671                         netdev_err(netdev, "Receive Nibble Error\n");
1672                 } else if (unlikely(gbec_status &
1673                                 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1674                         adapter->stats.rx_crc_errors++;
1675                         netdev_err(netdev, "Receive CRC Error\n");
1676                 } else {
1677                         /* get receive length */
1678                         /* length convert[-3], length includes FCS length */
1679                         length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN;
1680                         if (rx_desc->rx_words_eob & 0x02)
1681                                 length = length - 4;
1682                         /*
1683                          * buffer_info->rx_buffer: [Header:14][payload]
1684                          * skb->data: [Reserve:2][Header:14][payload]
1685                          */
1686                         memcpy(skb->data, buffer_info->rx_buffer, length);
1687
1688                         /* update status of driver */
1689                         adapter->stats.rx_bytes += length;
1690                         adapter->stats.rx_packets++;
1691                         if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1692                                 adapter->stats.multicast++;
1693                         /* Write meta date of skb */
1694                         skb_put(skb, length);
1695
1696                         pch_rx_timestamp(adapter, skb);
1697
1698                         skb->protocol = eth_type_trans(skb, netdev);
1699                         if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
1700                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1701                         else
1702                                 skb->ip_summed = CHECKSUM_NONE;
1703
1704                         napi_gro_receive(&adapter->napi, skb);
1705                         (*work_done)++;
1706                         netdev_dbg(netdev,
1707                                    "Receive skb->ip_summed: %d length: %d\n",
1708                                    skb->ip_summed, length);
1709                 }
1710                 /* return some buffers to hardware, one at a time is too slow */
1711                 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1712                         pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1713                                                  cleaned_count);
1714                         cleaned_count = 0;
1715                 }
1716                 if (++i == rx_ring->count)
1717                         i = 0;
1718         }
1719         rx_ring->next_to_clean = i;
1720         if (cleaned_count)
1721                 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1722         return cleaned;
1723 }
1724
1725 /**
1726  * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1727  * @adapter:  Board private structure
1728  * @tx_ring:  Tx descriptor ring (for a specific queue) to setup
1729  * Returns:
1730  *      0:              Successfully
1731  *      Negative value: Failed
1732  */
1733 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1734                                 struct pch_gbe_tx_ring *tx_ring)
1735 {
1736         struct pci_dev *pdev = adapter->pdev;
1737         struct pch_gbe_tx_desc *tx_desc;
1738         int size;
1739         int desNo;
1740
1741         size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1742         tx_ring->buffer_info = vzalloc(size);
1743         if (!tx_ring->buffer_info)
1744                 return -ENOMEM;
1745
1746         tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1747
1748         tx_ring->desc = dma_zalloc_coherent(&pdev->dev, tx_ring->size,
1749                                             &tx_ring->dma, GFP_KERNEL);
1750         if (!tx_ring->desc) {
1751                 vfree(tx_ring->buffer_info);
1752                 return -ENOMEM;
1753         }
1754
1755         tx_ring->next_to_use = 0;
1756         tx_ring->next_to_clean = 0;
1757
1758         for (desNo = 0; desNo < tx_ring->count; desNo++) {
1759                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1760                 tx_desc->gbec_status = DSC_INIT16;
1761         }
1762         netdev_dbg(adapter->netdev,
1763                    "tx_ring->desc = 0x%p  tx_ring->dma = 0x%08llx next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1764                    tx_ring->desc, (unsigned long long)tx_ring->dma,
1765                    tx_ring->next_to_clean, tx_ring->next_to_use);
1766         return 0;
1767 }
1768
1769 /**
1770  * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1771  * @adapter:  Board private structure
1772  * @rx_ring:  Rx descriptor ring (for a specific queue) to setup
1773  * Returns:
1774  *      0:              Successfully
1775  *      Negative value: Failed
1776  */
1777 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1778                                 struct pch_gbe_rx_ring *rx_ring)
1779 {
1780         struct pci_dev *pdev = adapter->pdev;
1781         struct pch_gbe_rx_desc *rx_desc;
1782         int size;
1783         int desNo;
1784
1785         size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1786         rx_ring->buffer_info = vzalloc(size);
1787         if (!rx_ring->buffer_info)
1788                 return -ENOMEM;
1789
1790         rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1791         rx_ring->desc = dma_zalloc_coherent(&pdev->dev, rx_ring->size,
1792                                             &rx_ring->dma, GFP_KERNEL);
1793         if (!rx_ring->desc) {
1794                 vfree(rx_ring->buffer_info);
1795                 return -ENOMEM;
1796         }
1797         rx_ring->next_to_clean = 0;
1798         rx_ring->next_to_use = 0;
1799         for (desNo = 0; desNo < rx_ring->count; desNo++) {
1800                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1801                 rx_desc->gbec_status = DSC_INIT16;
1802         }
1803         netdev_dbg(adapter->netdev,
1804                    "rx_ring->desc = 0x%p  rx_ring->dma = 0x%08llx next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1805                    rx_ring->desc, (unsigned long long)rx_ring->dma,
1806                    rx_ring->next_to_clean, rx_ring->next_to_use);
1807         return 0;
1808 }
1809
1810 /**
1811  * pch_gbe_free_tx_resources - Free Tx Resources
1812  * @adapter:  Board private structure
1813  * @tx_ring:  Tx descriptor ring for a specific queue
1814  */
1815 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1816                                 struct pch_gbe_tx_ring *tx_ring)
1817 {
1818         struct pci_dev *pdev = adapter->pdev;
1819
1820         pch_gbe_clean_tx_ring(adapter, tx_ring);
1821         vfree(tx_ring->buffer_info);
1822         tx_ring->buffer_info = NULL;
1823         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1824         tx_ring->desc = NULL;
1825 }
1826
1827 /**
1828  * pch_gbe_free_rx_resources - Free Rx Resources
1829  * @adapter:  Board private structure
1830  * @rx_ring:  Ring to clean the resources from
1831  */
1832 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1833                                 struct pch_gbe_rx_ring *rx_ring)
1834 {
1835         struct pci_dev *pdev = adapter->pdev;
1836
1837         pch_gbe_clean_rx_ring(adapter, rx_ring);
1838         vfree(rx_ring->buffer_info);
1839         rx_ring->buffer_info = NULL;
1840         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1841         rx_ring->desc = NULL;
1842 }
1843
1844 /**
1845  * pch_gbe_request_irq - Allocate an interrupt line
1846  * @adapter:  Board private structure
1847  * Returns:
1848  *      0:              Successfully
1849  *      Negative value: Failed
1850  */
1851 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1852 {
1853         struct net_device *netdev = adapter->netdev;
1854         int err;
1855
1856         err = pci_alloc_irq_vectors(adapter->pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1857         if (err < 0)
1858                 return err;
1859
1860         adapter->irq = pci_irq_vector(adapter->pdev, 0);
1861
1862         err = request_irq(adapter->irq, &pch_gbe_intr, IRQF_SHARED,
1863                           netdev->name, netdev);
1864         if (err)
1865                 netdev_err(netdev, "Unable to allocate interrupt Error: %d\n",
1866                            err);
1867         netdev_dbg(netdev, "have_msi : %d  return : 0x%04x\n",
1868                    pci_dev_msi_enabled(adapter->pdev), err);
1869         return err;
1870 }
1871
1872 /**
1873  * pch_gbe_up - Up GbE network device
1874  * @adapter:  Board private structure
1875  * Returns:
1876  *      0:              Successfully
1877  *      Negative value: Failed
1878  */
1879 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1880 {
1881         struct net_device *netdev = adapter->netdev;
1882         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1883         struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1884         int err = -EINVAL;
1885
1886         /* Ensure we have a valid MAC */
1887         if (!is_valid_ether_addr(adapter->hw.mac.addr)) {
1888                 netdev_err(netdev, "Error: Invalid MAC address\n");
1889                 goto out;
1890         }
1891
1892         /* hardware has been reset, we need to reload some things */
1893         pch_gbe_set_multi(netdev);
1894
1895         pch_gbe_setup_tctl(adapter);
1896         pch_gbe_configure_tx(adapter);
1897         pch_gbe_setup_rctl(adapter);
1898         pch_gbe_configure_rx(adapter);
1899
1900         err = pch_gbe_request_irq(adapter);
1901         if (err) {
1902                 netdev_err(netdev,
1903                            "Error: can't bring device up - irq request failed\n");
1904                 goto out;
1905         }
1906         err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count);
1907         if (err) {
1908                 netdev_err(netdev,
1909                            "Error: can't bring device up - alloc rx buffers pool failed\n");
1910                 goto freeirq;
1911         }
1912         pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1913         pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1914         adapter->tx_queue_len = netdev->tx_queue_len;
1915         pch_gbe_enable_dma_rx(&adapter->hw);
1916         pch_gbe_enable_mac_rx(&adapter->hw);
1917
1918         mod_timer(&adapter->watchdog_timer, jiffies);
1919
1920         napi_enable(&adapter->napi);
1921         pch_gbe_irq_enable(adapter);
1922         netif_start_queue(adapter->netdev);
1923
1924         return 0;
1925
1926 freeirq:
1927         pch_gbe_free_irq(adapter);
1928 out:
1929         return err;
1930 }
1931
1932 /**
1933  * pch_gbe_down - Down GbE network device
1934  * @adapter:  Board private structure
1935  */
1936 void pch_gbe_down(struct pch_gbe_adapter *adapter)
1937 {
1938         struct net_device *netdev = adapter->netdev;
1939         struct pci_dev *pdev = adapter->pdev;
1940         struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1941
1942         /* signal that we're down so the interrupt handler does not
1943          * reschedule our watchdog timer */
1944         napi_disable(&adapter->napi);
1945         atomic_set(&adapter->irq_sem, 0);
1946
1947         pch_gbe_irq_disable(adapter);
1948         pch_gbe_free_irq(adapter);
1949
1950         del_timer_sync(&adapter->watchdog_timer);
1951
1952         netdev->tx_queue_len = adapter->tx_queue_len;
1953         netif_carrier_off(netdev);
1954         netif_stop_queue(netdev);
1955
1956         if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1957                 pch_gbe_reset(adapter);
1958         pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
1959         pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
1960
1961         pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size,
1962                             rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic);
1963         rx_ring->rx_buff_pool_logic = 0;
1964         rx_ring->rx_buff_pool_size = 0;
1965         rx_ring->rx_buff_pool = NULL;
1966 }
1967
1968 /**
1969  * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
1970  * @adapter:  Board private structure to initialize
1971  * Returns:
1972  *      0:              Successfully
1973  *      Negative value: Failed
1974  */
1975 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
1976 {
1977         struct pch_gbe_hw *hw = &adapter->hw;
1978         struct net_device *netdev = adapter->netdev;
1979
1980         adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1981         hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1982         hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1983         hw->phy.reset_delay_us = PCH_GBE_PHY_RESET_DELAY_US;
1984
1985         if (pch_gbe_alloc_queues(adapter)) {
1986                 netdev_err(netdev, "Unable to allocate memory for queues\n");
1987                 return -ENOMEM;
1988         }
1989         spin_lock_init(&adapter->hw.miim_lock);
1990         spin_lock_init(&adapter->stats_lock);
1991         spin_lock_init(&adapter->ethtool_lock);
1992         atomic_set(&adapter->irq_sem, 0);
1993         pch_gbe_irq_disable(adapter);
1994
1995         pch_gbe_init_stats(adapter);
1996
1997         netdev_dbg(netdev,
1998                    "rx_buffer_len : %d  mac.min_frame_size : %d  mac.max_frame_size : %d\n",
1999                    (u32) adapter->rx_buffer_len,
2000                    hw->mac.min_frame_size, hw->mac.max_frame_size);
2001         return 0;
2002 }
2003
2004 /**
2005  * pch_gbe_open - Called when a network interface is made active
2006  * @netdev:     Network interface device structure
2007  * Returns:
2008  *      0:              Successfully
2009  *      Negative value: Failed
2010  */
2011 static int pch_gbe_open(struct net_device *netdev)
2012 {
2013         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2014         struct pch_gbe_hw *hw = &adapter->hw;
2015         int err;
2016
2017         /* allocate transmit descriptors */
2018         err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
2019         if (err)
2020                 goto err_setup_tx;
2021         /* allocate receive descriptors */
2022         err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
2023         if (err)
2024                 goto err_setup_rx;
2025         pch_gbe_phy_power_up(hw);
2026         err = pch_gbe_up(adapter);
2027         if (err)
2028                 goto err_up;
2029         netdev_dbg(netdev, "Success End\n");
2030         return 0;
2031
2032 err_up:
2033         if (!adapter->wake_up_evt)
2034                 pch_gbe_phy_power_down(hw);
2035         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2036 err_setup_rx:
2037         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2038 err_setup_tx:
2039         pch_gbe_reset(adapter);
2040         netdev_err(netdev, "Error End\n");
2041         return err;
2042 }
2043
2044 /**
2045  * pch_gbe_stop - Disables a network interface
2046  * @netdev:  Network interface device structure
2047  * Returns:
2048  *      0: Successfully
2049  */
2050 static int pch_gbe_stop(struct net_device *netdev)
2051 {
2052         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2053         struct pch_gbe_hw *hw = &adapter->hw;
2054
2055         pch_gbe_down(adapter);
2056         if (!adapter->wake_up_evt)
2057                 pch_gbe_phy_power_down(hw);
2058         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2059         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2060         return 0;
2061 }
2062
2063 /**
2064  * pch_gbe_xmit_frame - Packet transmitting start
2065  * @skb:     Socket buffer structure
2066  * @netdev:  Network interface device structure
2067  * Returns:
2068  *      - NETDEV_TX_OK:   Normal end
2069  *      - NETDEV_TX_BUSY: Error end
2070  */
2071 static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2072 {
2073         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2074         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
2075
2076         if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
2077                 netif_stop_queue(netdev);
2078                 netdev_dbg(netdev,
2079                            "Return : BUSY  next_to use : 0x%08x  next_to clean : 0x%08x\n",
2080                            tx_ring->next_to_use, tx_ring->next_to_clean);
2081                 return NETDEV_TX_BUSY;
2082         }
2083
2084         /* CRC,ITAG no support */
2085         pch_gbe_tx_queue(adapter, tx_ring, skb);
2086         return NETDEV_TX_OK;
2087 }
2088
2089 /**
2090  * pch_gbe_set_multi - Multicast and Promiscuous mode set
2091  * @netdev:   Network interface device structure
2092  */
2093 static void pch_gbe_set_multi(struct net_device *netdev)
2094 {
2095         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2096         struct pch_gbe_hw *hw = &adapter->hw;
2097         struct netdev_hw_addr *ha;
2098         u32 rctl, adrmask;
2099         int mc_count, i;
2100
2101         netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags);
2102
2103         /* By default enable address & multicast filtering */
2104         rctl = ioread32(&hw->reg->RX_MODE);
2105         rctl |= PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN;
2106
2107         /* Promiscuous mode disables all hardware address filtering */
2108         if (netdev->flags & IFF_PROMISC)
2109                 rctl &= ~(PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
2110
2111         /* If we want to monitor more multicast addresses than the hardware can
2112          * support then disable hardware multicast filtering.
2113          */
2114         mc_count = netdev_mc_count(netdev);
2115         if ((netdev->flags & IFF_ALLMULTI) || mc_count >= PCH_GBE_MAR_ENTRIES)
2116                 rctl &= ~PCH_GBE_MLT_FIL_EN;
2117
2118         iowrite32(rctl, &hw->reg->RX_MODE);
2119
2120         /* If we're not using multicast filtering then there's no point
2121          * configuring the unused MAC address registers.
2122          */
2123         if (!(rctl & PCH_GBE_MLT_FIL_EN))
2124                 return;
2125
2126         /* Load the first set of multicast addresses into MAC address registers
2127          * for use by hardware filtering.
2128          */
2129         i = 1;
2130         netdev_for_each_mc_addr(ha, netdev)
2131                 pch_gbe_mac_mar_set(hw, ha->addr, i++);
2132
2133         /* If there are spare MAC registers, mask & clear them */
2134         for (; i < PCH_GBE_MAR_ENTRIES; i++) {
2135                 /* Clear MAC address mask */
2136                 adrmask = ioread32(&hw->reg->ADDR_MASK);
2137                 iowrite32(adrmask | BIT(i), &hw->reg->ADDR_MASK);
2138                 /* wait busy */
2139                 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
2140                 /* Clear MAC address */
2141                 iowrite32(0, &hw->reg->mac_adr[i].high);
2142                 iowrite32(0, &hw->reg->mac_adr[i].low);
2143         }
2144
2145         netdev_dbg(netdev,
2146                  "RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x  netdev->mc_count : 0x%08x\n",
2147                  ioread32(&hw->reg->RX_MODE), mc_count);
2148 }
2149
2150 /**
2151  * pch_gbe_set_mac - Change the Ethernet Address of the NIC
2152  * @netdev: Network interface device structure
2153  * @addr:   Pointer to an address structure
2154  * Returns:
2155  *      0:              Successfully
2156  *      -EADDRNOTAVAIL: Failed
2157  */
2158 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
2159 {
2160         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2161         struct sockaddr *skaddr = addr;
2162         int ret_val;
2163
2164         if (!is_valid_ether_addr(skaddr->sa_data)) {
2165                 ret_val = -EADDRNOTAVAIL;
2166         } else {
2167                 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
2168                 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
2169                 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2170                 ret_val = 0;
2171         }
2172         netdev_dbg(netdev, "ret_val : 0x%08x\n", ret_val);
2173         netdev_dbg(netdev, "dev_addr : %pM\n", netdev->dev_addr);
2174         netdev_dbg(netdev, "mac_addr : %pM\n", adapter->hw.mac.addr);
2175         netdev_dbg(netdev, "MAC_ADR1AB reg : 0x%08x 0x%08x\n",
2176                    ioread32(&adapter->hw.reg->mac_adr[0].high),
2177                    ioread32(&adapter->hw.reg->mac_adr[0].low));
2178         return ret_val;
2179 }
2180
2181 /**
2182  * pch_gbe_change_mtu - Change the Maximum Transfer Unit
2183  * @netdev:   Network interface device structure
2184  * @new_mtu:  New value for maximum frame size
2185  * Returns:
2186  *      0:              Successfully
2187  *      -EINVAL:        Failed
2188  */
2189 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2190 {
2191         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2192         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2193         unsigned long old_rx_buffer_len = adapter->rx_buffer_len;
2194         int err;
2195
2196         if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2197                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2198         else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2199                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2200         else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2201                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2202         else
2203                 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE;
2204
2205         if (netif_running(netdev)) {
2206                 pch_gbe_down(adapter);
2207                 err = pch_gbe_up(adapter);
2208                 if (err) {
2209                         adapter->rx_buffer_len = old_rx_buffer_len;
2210                         pch_gbe_up(adapter);
2211                         return err;
2212                 } else {
2213                         netdev->mtu = new_mtu;
2214                         adapter->hw.mac.max_frame_size = max_frame;
2215                 }
2216         } else {
2217                 pch_gbe_reset(adapter);
2218                 netdev->mtu = new_mtu;
2219                 adapter->hw.mac.max_frame_size = max_frame;
2220         }
2221
2222         netdev_dbg(netdev,
2223                    "max_frame : %d  rx_buffer_len : %d  mtu : %d  max_frame_size : %d\n",
2224                    max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2225                    adapter->hw.mac.max_frame_size);
2226         return 0;
2227 }
2228
2229 /**
2230  * pch_gbe_set_features - Reset device after features changed
2231  * @netdev:   Network interface device structure
2232  * @features:  New features
2233  * Returns:
2234  *      0:              HW state updated successfully
2235  */
2236 static int pch_gbe_set_features(struct net_device *netdev,
2237         netdev_features_t features)
2238 {
2239         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2240         netdev_features_t changed = features ^ netdev->features;
2241
2242         if (!(changed & NETIF_F_RXCSUM))
2243                 return 0;
2244
2245         if (netif_running(netdev))
2246                 pch_gbe_reinit_locked(adapter);
2247         else
2248                 pch_gbe_reset(adapter);
2249
2250         return 0;
2251 }
2252
2253 /**
2254  * pch_gbe_ioctl - Controls register through a MII interface
2255  * @netdev:   Network interface device structure
2256  * @ifr:      Pointer to ifr structure
2257  * @cmd:      Control command
2258  * Returns:
2259  *      0:      Successfully
2260  *      Negative value: Failed
2261  */
2262 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2263 {
2264         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2265
2266         netdev_dbg(netdev, "cmd : 0x%04x\n", cmd);
2267
2268         if (cmd == SIOCSHWTSTAMP)
2269                 return hwtstamp_ioctl(netdev, ifr, cmd);
2270
2271         return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2272 }
2273
2274 /**
2275  * pch_gbe_tx_timeout - Respond to a Tx Hang
2276  * @netdev:   Network interface device structure
2277  */
2278 static void pch_gbe_tx_timeout(struct net_device *netdev)
2279 {
2280         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2281
2282         /* Do the reset outside of interrupt context */
2283         adapter->stats.tx_timeout_count++;
2284         schedule_work(&adapter->reset_task);
2285 }
2286
2287 /**
2288  * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2289  * @napi:    Pointer of polling device struct
2290  * @budget:  The maximum number of a packet
2291  * Returns:
2292  *      false:  Exit the polling mode
2293  *      true:   Continue the polling mode
2294  */
2295 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2296 {
2297         struct pch_gbe_adapter *adapter =
2298             container_of(napi, struct pch_gbe_adapter, napi);
2299         int work_done = 0;
2300         bool poll_end_flag = false;
2301         bool cleaned = false;
2302
2303         netdev_dbg(adapter->netdev, "budget : %d\n", budget);
2304
2305         pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2306         cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2307
2308         if (cleaned)
2309                 work_done = budget;
2310         /* If no Tx and not enough Rx work done,
2311          * exit the polling mode
2312          */
2313         if (work_done < budget)
2314                 poll_end_flag = true;
2315
2316         if (poll_end_flag) {
2317                 napi_complete_done(napi, work_done);
2318                 pch_gbe_irq_enable(adapter);
2319         }
2320
2321         if (adapter->rx_stop_flag) {
2322                 adapter->rx_stop_flag = false;
2323                 pch_gbe_enable_dma_rx(&adapter->hw);
2324         }
2325
2326         netdev_dbg(adapter->netdev,
2327                    "poll_end_flag : %d  work_done : %d  budget : %d\n",
2328                    poll_end_flag, work_done, budget);
2329
2330         return work_done;
2331 }
2332
2333 #ifdef CONFIG_NET_POLL_CONTROLLER
2334 /**
2335  * pch_gbe_netpoll - Used by things like netconsole to send skbs
2336  * @netdev:  Network interface device structure
2337  */
2338 static void pch_gbe_netpoll(struct net_device *netdev)
2339 {
2340         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2341
2342         disable_irq(adapter->irq);
2343         pch_gbe_intr(adapter->irq, netdev);
2344         enable_irq(adapter->irq);
2345 }
2346 #endif
2347
2348 static const struct net_device_ops pch_gbe_netdev_ops = {
2349         .ndo_open = pch_gbe_open,
2350         .ndo_stop = pch_gbe_stop,
2351         .ndo_start_xmit = pch_gbe_xmit_frame,
2352         .ndo_set_mac_address = pch_gbe_set_mac,
2353         .ndo_tx_timeout = pch_gbe_tx_timeout,
2354         .ndo_change_mtu = pch_gbe_change_mtu,
2355         .ndo_set_features = pch_gbe_set_features,
2356         .ndo_do_ioctl = pch_gbe_ioctl,
2357         .ndo_set_rx_mode = pch_gbe_set_multi,
2358 #ifdef CONFIG_NET_POLL_CONTROLLER
2359         .ndo_poll_controller = pch_gbe_netpoll,
2360 #endif
2361 };
2362
2363 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2364                                                 pci_channel_state_t state)
2365 {
2366         struct net_device *netdev = pci_get_drvdata(pdev);
2367         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2368
2369         netif_device_detach(netdev);
2370         if (netif_running(netdev))
2371                 pch_gbe_down(adapter);
2372         pci_disable_device(pdev);
2373         /* Request a slot slot reset. */
2374         return PCI_ERS_RESULT_NEED_RESET;
2375 }
2376
2377 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2378 {
2379         struct net_device *netdev = pci_get_drvdata(pdev);
2380         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2381         struct pch_gbe_hw *hw = &adapter->hw;
2382
2383         if (pci_enable_device(pdev)) {
2384                 netdev_err(netdev, "Cannot re-enable PCI device after reset\n");
2385                 return PCI_ERS_RESULT_DISCONNECT;
2386         }
2387         pci_set_master(pdev);
2388         pci_enable_wake(pdev, PCI_D0, 0);
2389         pch_gbe_phy_power_up(hw);
2390         pch_gbe_reset(adapter);
2391         /* Clear wake up status */
2392         pch_gbe_mac_set_wol_event(hw, 0);
2393
2394         return PCI_ERS_RESULT_RECOVERED;
2395 }
2396
2397 static void pch_gbe_io_resume(struct pci_dev *pdev)
2398 {
2399         struct net_device *netdev = pci_get_drvdata(pdev);
2400         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2401
2402         if (netif_running(netdev)) {
2403                 if (pch_gbe_up(adapter)) {
2404                         netdev_dbg(netdev,
2405                                    "can't bring device back up after reset\n");
2406                         return;
2407                 }
2408         }
2409         netif_device_attach(netdev);
2410 }
2411
2412 static int __pch_gbe_suspend(struct pci_dev *pdev)
2413 {
2414         struct net_device *netdev = pci_get_drvdata(pdev);
2415         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2416         struct pch_gbe_hw *hw = &adapter->hw;
2417         u32 wufc = adapter->wake_up_evt;
2418         int retval = 0;
2419
2420         netif_device_detach(netdev);
2421         if (netif_running(netdev))
2422                 pch_gbe_down(adapter);
2423         if (wufc) {
2424                 pch_gbe_set_multi(netdev);
2425                 pch_gbe_setup_rctl(adapter);
2426                 pch_gbe_configure_rx(adapter);
2427                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2428                                         hw->mac.link_duplex);
2429                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2430                                         hw->mac.link_duplex);
2431                 pch_gbe_mac_set_wol_event(hw, wufc);
2432                 pci_disable_device(pdev);
2433         } else {
2434                 pch_gbe_phy_power_down(hw);
2435                 pch_gbe_mac_set_wol_event(hw, wufc);
2436                 pci_disable_device(pdev);
2437         }
2438         return retval;
2439 }
2440
2441 #ifdef CONFIG_PM
2442 static int pch_gbe_suspend(struct device *device)
2443 {
2444         struct pci_dev *pdev = to_pci_dev(device);
2445
2446         return __pch_gbe_suspend(pdev);
2447 }
2448
2449 static int pch_gbe_resume(struct device *device)
2450 {
2451         struct pci_dev *pdev = to_pci_dev(device);
2452         struct net_device *netdev = pci_get_drvdata(pdev);
2453         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2454         struct pch_gbe_hw *hw = &adapter->hw;
2455         u32 err;
2456
2457         err = pci_enable_device(pdev);
2458         if (err) {
2459                 netdev_err(netdev, "Cannot enable PCI device from suspend\n");
2460                 return err;
2461         }
2462         pci_set_master(pdev);
2463         pch_gbe_phy_power_up(hw);
2464         pch_gbe_reset(adapter);
2465         /* Clear wake on lan control and status */
2466         pch_gbe_mac_set_wol_event(hw, 0);
2467
2468         if (netif_running(netdev))
2469                 pch_gbe_up(adapter);
2470         netif_device_attach(netdev);
2471
2472         return 0;
2473 }
2474 #endif /* CONFIG_PM */
2475
2476 static void pch_gbe_shutdown(struct pci_dev *pdev)
2477 {
2478         __pch_gbe_suspend(pdev);
2479         if (system_state == SYSTEM_POWER_OFF) {
2480                 pci_wake_from_d3(pdev, true);
2481                 pci_set_power_state(pdev, PCI_D3hot);
2482         }
2483 }
2484
2485 static void pch_gbe_remove(struct pci_dev *pdev)
2486 {
2487         struct net_device *netdev = pci_get_drvdata(pdev);
2488         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2489
2490         cancel_work_sync(&adapter->reset_task);
2491         unregister_netdev(netdev);
2492
2493         pch_gbe_phy_hw_reset(&adapter->hw);
2494
2495         free_netdev(netdev);
2496 }
2497
2498 static int pch_gbe_probe(struct pci_dev *pdev,
2499                           const struct pci_device_id *pci_id)
2500 {
2501         struct net_device *netdev;
2502         struct pch_gbe_adapter *adapter;
2503         int ret;
2504
2505         ret = pcim_enable_device(pdev);
2506         if (ret)
2507                 return ret;
2508
2509         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2510                 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2511                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2512                 if (ret) {
2513                         ret = pci_set_consistent_dma_mask(pdev,
2514                                                           DMA_BIT_MASK(32));
2515                         if (ret) {
2516                                 dev_err(&pdev->dev, "ERR: No usable DMA "
2517                                         "configuration, aborting\n");
2518                                 return ret;
2519                         }
2520                 }
2521         }
2522
2523         ret = pcim_iomap_regions(pdev, 1 << PCH_GBE_PCI_BAR, pci_name(pdev));
2524         if (ret) {
2525                 dev_err(&pdev->dev,
2526                         "ERR: Can't reserve PCI I/O and memory resources\n");
2527                 return ret;
2528         }
2529         pci_set_master(pdev);
2530
2531         netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2532         if (!netdev)
2533                 return -ENOMEM;
2534         SET_NETDEV_DEV(netdev, &pdev->dev);
2535
2536         pci_set_drvdata(pdev, netdev);
2537         adapter = netdev_priv(netdev);
2538         adapter->netdev = netdev;
2539         adapter->pdev = pdev;
2540         adapter->hw.back = adapter;
2541         adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
2542
2543         adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
2544         if (adapter->pdata && adapter->pdata->platform_init) {
2545                 ret = adapter->pdata->platform_init(pdev);
2546                 if (ret)
2547                         goto err_free_netdev;
2548         }
2549
2550         adapter->ptp_pdev =
2551                 pci_get_domain_bus_and_slot(pci_domain_nr(adapter->pdev->bus),
2552                                             adapter->pdev->bus->number,
2553                                             PCI_DEVFN(12, 4));
2554
2555         netdev->netdev_ops = &pch_gbe_netdev_ops;
2556         netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2557         netif_napi_add(netdev, &adapter->napi,
2558                        pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2559         netdev->hw_features = NETIF_F_RXCSUM |
2560                 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2561         netdev->features = netdev->hw_features;
2562         pch_gbe_set_ethtool_ops(netdev);
2563
2564         /* MTU range: 46 - 10300 */
2565         netdev->min_mtu = ETH_ZLEN - ETH_HLEN;
2566         netdev->max_mtu = PCH_GBE_MAX_JUMBO_FRAME_SIZE -
2567                           (ETH_HLEN + ETH_FCS_LEN);
2568
2569         pch_gbe_mac_load_mac_addr(&adapter->hw);
2570         pch_gbe_mac_reset_hw(&adapter->hw);
2571
2572         /* setup the private structure */
2573         ret = pch_gbe_sw_init(adapter);
2574         if (ret)
2575                 goto err_free_netdev;
2576
2577         /* Initialize PHY */
2578         ret = pch_gbe_init_phy(adapter);
2579         if (ret) {
2580                 dev_err(&pdev->dev, "PHY initialize error\n");
2581                 goto err_free_adapter;
2582         }
2583
2584         /* Read the MAC address. and store to the private data */
2585         ret = pch_gbe_mac_read_mac_addr(&adapter->hw);
2586         if (ret) {
2587                 dev_err(&pdev->dev, "MAC address Read Error\n");
2588                 goto err_free_adapter;
2589         }
2590
2591         memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2592         if (!is_valid_ether_addr(netdev->dev_addr)) {
2593                 /*
2594                  * If the MAC is invalid (or just missing), display a warning
2595                  * but do not abort setting up the device. pch_gbe_up will
2596                  * prevent the interface from being brought up until a valid MAC
2597                  * is set.
2598                  */
2599                 dev_err(&pdev->dev, "Invalid MAC address, "
2600                                     "interface disabled.\n");
2601         }
2602         timer_setup(&adapter->watchdog_timer, pch_gbe_watchdog, 0);
2603
2604         INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2605
2606         pch_gbe_check_options(adapter);
2607
2608         /* initialize the wol settings based on the eeprom settings */
2609         adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2610         dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2611
2612         /* reset the hardware with the new settings */
2613         pch_gbe_reset(adapter);
2614
2615         ret = register_netdev(netdev);
2616         if (ret)
2617                 goto err_free_adapter;
2618         /* tell the stack to leave us alone until pch_gbe_open() is called */
2619         netif_carrier_off(netdev);
2620         netif_stop_queue(netdev);
2621
2622         dev_dbg(&pdev->dev, "PCH Network Connection\n");
2623
2624         /* Disable hibernation on certain platforms */
2625         if (adapter->pdata && adapter->pdata->phy_disable_hibernate)
2626                 pch_gbe_phy_disable_hibernate(&adapter->hw);
2627
2628         device_set_wakeup_enable(&pdev->dev, 1);
2629         return 0;
2630
2631 err_free_adapter:
2632         pch_gbe_phy_hw_reset(&adapter->hw);
2633 err_free_netdev:
2634         free_netdev(netdev);
2635         return ret;
2636 }
2637
2638 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
2639  * ensure it is awake for probe and init. Request the line and reset the PHY.
2640  */
2641 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
2642 {
2643         unsigned long flags = GPIOF_OUT_INIT_HIGH;
2644         unsigned gpio = MINNOW_PHY_RESET_GPIO;
2645         int ret;
2646
2647         ret = devm_gpio_request_one(&pdev->dev, gpio, flags,
2648                                     "minnow_phy_reset");
2649         if (ret) {
2650                 dev_err(&pdev->dev,
2651                         "ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
2652                 return ret;
2653         }
2654
2655         gpio_set_value(gpio, 0);
2656         usleep_range(1250, 1500);
2657         gpio_set_value(gpio, 1);
2658         usleep_range(1250, 1500);
2659
2660         return ret;
2661 }
2662
2663 static struct pch_gbe_privdata pch_gbe_minnow_privdata = {
2664         .phy_tx_clk_delay = true,
2665         .phy_disable_hibernate = true,
2666         .platform_init = pch_gbe_minnow_platform_init,
2667 };
2668
2669 static const struct pci_device_id pch_gbe_pcidev_id[] = {
2670         {.vendor = PCI_VENDOR_ID_INTEL,
2671          .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2672          .subvendor = PCI_VENDOR_ID_CIRCUITCO,
2673          .subdevice = PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD,
2674          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2675          .class_mask = (0xFFFF00),
2676          .driver_data = (kernel_ulong_t)&pch_gbe_minnow_privdata
2677          },
2678         {.vendor = PCI_VENDOR_ID_INTEL,
2679          .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2680          .subvendor = PCI_ANY_ID,
2681          .subdevice = PCI_ANY_ID,
2682          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2683          .class_mask = (0xFFFF00)
2684          },
2685         {.vendor = PCI_VENDOR_ID_ROHM,
2686          .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2687          .subvendor = PCI_ANY_ID,
2688          .subdevice = PCI_ANY_ID,
2689          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2690          .class_mask = (0xFFFF00)
2691          },
2692         {.vendor = PCI_VENDOR_ID_ROHM,
2693          .device = PCI_DEVICE_ID_ROHM_ML7831_GBE,
2694          .subvendor = PCI_ANY_ID,
2695          .subdevice = PCI_ANY_ID,
2696          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2697          .class_mask = (0xFFFF00)
2698          },
2699         /* required last entry */
2700         {0}
2701 };
2702
2703 #ifdef CONFIG_PM
2704 static const struct dev_pm_ops pch_gbe_pm_ops = {
2705         .suspend = pch_gbe_suspend,
2706         .resume = pch_gbe_resume,
2707         .freeze = pch_gbe_suspend,
2708         .thaw = pch_gbe_resume,
2709         .poweroff = pch_gbe_suspend,
2710         .restore = pch_gbe_resume,
2711 };
2712 #endif
2713
2714 static const struct pci_error_handlers pch_gbe_err_handler = {
2715         .error_detected = pch_gbe_io_error_detected,
2716         .slot_reset = pch_gbe_io_slot_reset,
2717         .resume = pch_gbe_io_resume
2718 };
2719
2720 static struct pci_driver pch_gbe_driver = {
2721         .name = KBUILD_MODNAME,
2722         .id_table = pch_gbe_pcidev_id,
2723         .probe = pch_gbe_probe,
2724         .remove = pch_gbe_remove,
2725 #ifdef CONFIG_PM
2726         .driver.pm = &pch_gbe_pm_ops,
2727 #endif
2728         .shutdown = pch_gbe_shutdown,
2729         .err_handler = &pch_gbe_err_handler
2730 };
2731 module_pci_driver(pch_gbe_driver);
2732
2733 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2734 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
2735 MODULE_LICENSE("GPL");
2736 MODULE_VERSION(DRV_VERSION);
2737 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2738
2739 /* pch_gbe_main.c */