2 * Copyright (C) 2015-2017 Netronome Systems, Inc.
4 * This software is dual licensed under the GNU General License Version 2,
5 * June 1991 as shown in the file COPYING in the top-level directory of this
6 * source tree or the BSD 2-Clause License provided below. You have the
7 * option to license this software under the complete terms of either license.
9 * The BSD 2-Clause License:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * 1. Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * 2. Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 * CPP Access Width Decoder
37 * Authors: Jakub Kicinski <jakub.kicinski@netronome.com>
38 * Jason McMullan <jason.mcmullan@netronome.com>
39 * Francois H. Theron <francois.theron@netronome.com>
42 #include <linux/bitops.h>
46 #include "nfp6000/nfp6000.h"
51 /* This structure ONLY includes items that can be done with a read or write of
52 * 32-bit or 64-bit words. All others are not listed.
55 #define AT(_action, _token, _pull, _push) \
56 case NFP_CPP_ID(0, (_action), (_token)): \
57 return PUSHPULL((_pull), (_push))
59 static int target_rw(u32 cpp_id, int pp, int start, int len)
61 switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) {
64 AT(NFP_CPP_ACTION_RW, 0, pp, pp);
70 static int nfp6000_nbi_dma(u32 cpp_id)
72 switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) {
73 AT(0, 0, 0, P64); /* ReadNbiDma */
74 AT(1, 0, P64, 0); /* WriteNbiDma */
75 AT(NFP_CPP_ACTION_RW, 0, P64, P64);
81 static int nfp6000_nbi_stats(u32 cpp_id)
83 switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) {
84 AT(0, 0, 0, P32); /* ReadNbiStats */
85 AT(1, 0, P32, 0); /* WriteNbiStats */
86 AT(NFP_CPP_ACTION_RW, 0, P32, P32);
92 static int nfp6000_nbi_tm(u32 cpp_id)
94 switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) {
95 AT(0, 0, 0, P64); /* ReadNbiTM */
96 AT(1, 0, P64, 0); /* WriteNbiTM */
97 AT(NFP_CPP_ACTION_RW, 0, P64, P64);
103 static int nfp6000_nbi_ppc(u32 cpp_id)
105 switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) {
106 AT(0, 0, 0, P64); /* ReadNbiPreclassifier */
107 AT(1, 0, P64, 0); /* WriteNbiPreclassifier */
108 AT(NFP_CPP_ACTION_RW, 0, P64, P64);
114 static int nfp6000_nbi(u32 cpp_id, u64 address)
116 u64 rel_addr = address & 0x3fFFFF;
118 if (rel_addr < (1 << 20))
119 return nfp6000_nbi_dma(cpp_id);
120 if (rel_addr < (2 << 20))
121 return nfp6000_nbi_stats(cpp_id);
122 if (rel_addr < (3 << 20))
123 return nfp6000_nbi_tm(cpp_id);
124 return nfp6000_nbi_ppc(cpp_id);
127 /* This structure ONLY includes items that can be done with a read or write of
128 * 32-bit or 64-bit words. All others are not listed.
130 static int nfp6000_mu_common(u32 cpp_id)
132 switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) {
133 AT(NFP_CPP_ACTION_RW, 0, P64, P64); /* read_be/write_be */
134 AT(NFP_CPP_ACTION_RW, 1, P64, P64); /* read_le/write_le */
135 AT(NFP_CPP_ACTION_RW, 2, P64, P64); /* read_swap_be/write_swap_be */
136 AT(NFP_CPP_ACTION_RW, 3, P64, P64); /* read_swap_le/write_swap_le */
137 AT(0, 0, 0, P64); /* read_be */
138 AT(0, 1, 0, P64); /* read_le */
139 AT(0, 2, 0, P64); /* read_swap_be */
140 AT(0, 3, 0, P64); /* read_swap_le */
141 AT(1, 0, P64, 0); /* write_be */
142 AT(1, 1, P64, 0); /* write_le */
143 AT(1, 2, P64, 0); /* write_swap_be */
144 AT(1, 3, P64, 0); /* write_swap_le */
145 AT(3, 0, 0, P32); /* atomic_read */
146 AT(3, 2, P32, 0); /* mask_compare_write */
147 AT(4, 0, P32, 0); /* atomic_write */
148 AT(4, 2, 0, 0); /* atomic_write_imm */
149 AT(4, 3, 0, P32); /* swap_imm */
150 AT(5, 0, P32, 0); /* set */
151 AT(5, 3, 0, P32); /* test_set_imm */
152 AT(6, 0, P32, 0); /* clr */
153 AT(6, 3, 0, P32); /* test_clr_imm */
154 AT(7, 0, P32, 0); /* add */
155 AT(7, 3, 0, P32); /* test_add_imm */
156 AT(8, 0, P32, 0); /* addsat */
157 AT(8, 3, 0, P32); /* test_subsat_imm */
158 AT(9, 0, P32, 0); /* sub */
159 AT(9, 3, 0, P32); /* test_sub_imm */
160 AT(10, 0, P32, 0); /* subsat */
161 AT(10, 3, 0, P32); /* test_subsat_imm */
162 AT(13, 0, 0, P32); /* microq128_get */
163 AT(13, 1, 0, P32); /* microq128_pop */
164 AT(13, 2, P32, 0); /* microq128_put */
165 AT(15, 0, P32, 0); /* xor */
166 AT(15, 3, 0, P32); /* test_xor_imm */
167 AT(28, 0, 0, P32); /* read32_be */
168 AT(28, 1, 0, P32); /* read32_le */
169 AT(28, 2, 0, P32); /* read32_swap_be */
170 AT(28, 3, 0, P32); /* read32_swap_le */
171 AT(31, 0, P32, 0); /* write32_be */
172 AT(31, 1, P32, 0); /* write32_le */
173 AT(31, 2, P32, 0); /* write32_swap_be */
174 AT(31, 3, P32, 0); /* write32_swap_le */
180 static int nfp6000_mu_ctm(u32 cpp_id)
182 switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) {
183 AT(16, 1, 0, P32); /* packet_read_packet_status */
184 AT(17, 1, 0, P32); /* packet_credit_get */
185 AT(17, 3, 0, P64); /* packet_add_thread */
186 AT(18, 2, 0, P64); /* packet_free_and_return_pointer */
187 AT(18, 3, 0, P64); /* packet_return_pointer */
188 AT(21, 0, 0, P64); /* pe_dma_to_memory_indirect */
189 AT(21, 1, 0, P64); /* pe_dma_to_memory_indirect_swap */
190 AT(21, 2, 0, P64); /* pe_dma_to_memory_indirect_free */
191 AT(21, 3, 0, P64); /* pe_dma_to_memory_indirect_free_swap */
193 return nfp6000_mu_common(cpp_id);
197 static int nfp6000_mu_emu(u32 cpp_id)
199 switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) {
200 AT(18, 0, 0, P32); /* read_queue */
201 AT(18, 1, 0, P32); /* read_queue_ring */
202 AT(18, 2, P32, 0); /* write_queue */
203 AT(18, 3, P32, 0); /* write_queue_ring */
204 AT(20, 2, P32, 0); /* journal */
205 AT(21, 0, 0, P32); /* get */
206 AT(21, 1, 0, P32); /* get_eop */
207 AT(21, 2, 0, P32); /* get_freely */
208 AT(22, 0, 0, P32); /* pop */
209 AT(22, 1, 0, P32); /* pop_eop */
210 AT(22, 2, 0, P32); /* pop_freely */
212 return nfp6000_mu_common(cpp_id);
216 static int nfp6000_mu_imu(u32 cpp_id)
218 return nfp6000_mu_common(cpp_id);
221 static int nfp6000_mu(u32 cpp_id, u64 address)
225 if (address < 0x2000000000ULL)
226 pp = nfp6000_mu_ctm(cpp_id);
227 else if (address < 0x8000000000ULL)
228 pp = nfp6000_mu_emu(cpp_id);
229 else if (address < 0x9800000000ULL)
230 pp = nfp6000_mu_ctm(cpp_id);
231 else if (address < 0x9C00000000ULL)
232 pp = nfp6000_mu_emu(cpp_id);
233 else if (address < 0xA000000000ULL)
234 pp = nfp6000_mu_imu(cpp_id);
236 pp = nfp6000_mu_ctm(cpp_id);
241 static int nfp6000_ila(u32 cpp_id)
243 switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) {
244 AT(0, 1, 0, P32); /* read_check_error */
245 AT(2, 0, 0, P32); /* read_int */
246 AT(3, 0, P32, 0); /* write_int */
248 return target_rw(cpp_id, P32, 48, 4);
252 static int nfp6000_pci(u32 cpp_id)
254 switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) {
258 return target_rw(cpp_id, P32, 4, 4);
262 static int nfp6000_crypto(u32 cpp_id)
264 switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) {
267 return target_rw(cpp_id, P64, 12, 4);
271 static int nfp6000_cap_xpb(u32 cpp_id)
273 switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) {
274 AT(0, 1, 0, P32); /* RingGet */
275 AT(0, 2, P32, 0); /* Interthread Signal */
276 AT(1, 1, P32, 0); /* RingPut */
277 AT(1, 2, P32, 0); /* CTNNWr */
278 AT(2, 0, 0, P32); /* ReflectRd, signal none */
279 AT(2, 1, 0, P32); /* ReflectRd, signal self */
280 AT(2, 2, 0, P32); /* ReflectRd, signal remote */
281 AT(2, 3, 0, P32); /* ReflectRd, signal both */
282 AT(3, 0, P32, 0); /* ReflectWr, signal none */
283 AT(3, 1, P32, 0); /* ReflectWr, signal self */
284 AT(3, 2, P32, 0); /* ReflectWr, signal remote */
285 AT(3, 3, P32, 0); /* ReflectWr, signal both */
286 AT(NFP_CPP_ACTION_RW, 1, P32, P32);
288 return target_rw(cpp_id, P32, 1, 63);
292 static int nfp6000_cls(u32 cpp_id)
294 switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) {
295 AT(0, 3, P32, 0); /* xor */
296 AT(2, 0, P32, 0); /* set */
297 AT(2, 1, P32, 0); /* clr */
298 AT(4, 0, P32, 0); /* add */
299 AT(4, 1, P32, 0); /* add64 */
300 AT(6, 0, P32, 0); /* sub */
301 AT(6, 1, P32, 0); /* sub64 */
302 AT(6, 2, P32, 0); /* subsat */
303 AT(8, 2, P32, 0); /* hash_mask */
304 AT(8, 3, P32, 0); /* hash_clear */
305 AT(9, 0, 0, P32); /* ring_get */
306 AT(9, 1, 0, P32); /* ring_pop */
307 AT(9, 2, 0, P32); /* ring_get_freely */
308 AT(9, 3, 0, P32); /* ring_pop_freely */
309 AT(10, 0, P32, 0); /* ring_put */
310 AT(10, 2, P32, 0); /* ring_journal */
311 AT(14, 0, P32, 0); /* reflect_write_sig_local */
312 AT(15, 1, 0, P32); /* reflect_read_sig_local */
313 AT(17, 2, P32, 0); /* statisic */
314 AT(24, 0, 0, P32); /* ring_read */
315 AT(24, 1, P32, 0); /* ring_write */
316 AT(25, 0, 0, P32); /* ring_workq_add_thread */
317 AT(25, 1, P32, 0); /* ring_workq_add_work */
319 return target_rw(cpp_id, P32, 0, 64);
323 int nfp_target_pushpull(u32 cpp_id, u64 address)
325 switch (NFP_CPP_ID_TARGET_of(cpp_id)) {
326 case NFP_CPP_TARGET_NBI:
327 return nfp6000_nbi(cpp_id, address);
328 case NFP_CPP_TARGET_QDR:
329 return target_rw(cpp_id, P32, 24, 4);
330 case NFP_CPP_TARGET_ILA:
331 return nfp6000_ila(cpp_id);
332 case NFP_CPP_TARGET_MU:
333 return nfp6000_mu(cpp_id, address);
334 case NFP_CPP_TARGET_PCIE:
335 return nfp6000_pci(cpp_id);
336 case NFP_CPP_TARGET_ARM:
337 if (address < 0x10000)
338 return target_rw(cpp_id, P64, 1, 1);
340 return target_rw(cpp_id, P32, 1, 1);
341 case NFP_CPP_TARGET_CRYPTO:
342 return nfp6000_crypto(cpp_id);
343 case NFP_CPP_TARGET_CT_XPB:
344 return nfp6000_cap_xpb(cpp_id);
345 case NFP_CPP_TARGET_CLS:
346 return nfp6000_cls(cpp_id);
348 return target_rw(cpp_id, P32, 4, 4);
358 /* All magic NFP-6xxx IMB 'mode' numbers here are from:
359 * Databook (1 August 2013)
360 * - System Overview and Connectivity
361 * -- Internal Connectivity
362 * --- Distributed Switch Fabric - Command Push/Pull (DSF-CPP) Bus
363 * ---- CPP addressing
364 * ----- Table 3.6. CPP Address Translation Mode Commands
367 #define _NIC_NFP6000_MU_LOCALITY_DIRECT 2
369 static int nfp_decode_basic(u64 addr, int *dest_island, int cpp_tgt,
370 int mode, bool addr40, int isld1, int isld0)
372 int iid_lsb, idx_lsb;
374 /* This function doesn't handle MU or CTXBP */
375 if (cpp_tgt == NFP_CPP_TARGET_MU || cpp_tgt == NFP_CPP_TARGET_CT_XPB)
380 /* For VQDR, in this mode for 32-bit addressing
381 * it would be islands 0, 16, 32 and 48 depending on channel
382 * and upper address bits.
383 * Since those are not all valid islands, most decode
384 * cases would result in bad island IDs, but we do them
385 * anyway since this is decoding an address that is already
386 * assumed to be used as-is to get to sram.
388 iid_lsb = addr40 ? 34 : 26;
389 *dest_island = (addr >> iid_lsb) & 0x3F;
392 /* For VQDR 32-bit, this would decode as:
393 * Channel 0: island#0
394 * Channel 1: island#0
395 * Channel 2: island#1
396 * Channel 3: island#1
397 * That would be valid as long as both islands
398 * have VQDR. Let's allow this.
400 idx_lsb = addr40 ? 39 : 31;
401 if (addr & BIT_ULL(idx_lsb))
402 *dest_island = isld1;
404 *dest_island = isld0;
409 * Channel 0: (island#0 | 0)
410 * Channel 1: (island#0 | 1)
411 * Channel 2: (island#1 | 0)
412 * Channel 3: (island#1 | 1)
414 * Make sure we compare against isldN values
415 * by clearing the LSB.
416 * This is what the silicon does.
421 idx_lsb = addr40 ? 39 : 31;
422 iid_lsb = idx_lsb - 1;
424 if (addr & BIT_ULL(idx_lsb))
425 *dest_island = isld1 | (int)((addr >> iid_lsb) & 1);
427 *dest_island = isld0 | (int)((addr >> iid_lsb) & 1);
431 /* In this mode the data address starts to affect the island ID
432 * so rather not allow it. In some really specific case
433 * one could use this to send the upper half of the
434 * VQDR channel to another MU, but this is getting very
436 * However, as above for mode 0, this is the decoder
437 * and the caller should validate the resulting IID.
438 * This blindly does what the silicon would do.
443 idx_lsb = addr40 ? 39 : 31;
444 iid_lsb = idx_lsb - 2;
446 if (addr & BIT_ULL(idx_lsb))
447 *dest_island = isld1 | (int)((addr >> iid_lsb) & 3);
449 *dest_island = isld0 | (int)((addr >> iid_lsb) & 3);
457 static int nfp_encode_basic_qdr(u64 addr, int dest_island, int cpp_tgt,
458 int mode, bool addr40, int isld1, int isld0)
462 /* Full Island ID and channel bits overlap? */
463 ret = nfp_decode_basic(addr, &v, cpp_tgt, mode, addr40, isld1, isld0);
467 /* The current address won't go where expected? */
468 if (dest_island != -1 && dest_island != v)
471 /* If dest_island was -1, we don't care where it goes. */
475 /* Try each option, take first one that fits.
476 * Not sure if we would want to do some smarter
477 * searching and prefer 0 or non-0 island IDs.
479 static int nfp_encode_basic_search(u64 *addr, int dest_island, int *isld,
480 int iid_lsb, int idx_lsb, int v_max)
484 for (i = 0; i < 2; i++)
485 for (v = 0; v < v_max; v++) {
486 if (dest_island != (isld[i] | v))
489 *addr &= ~GENMASK_ULL(idx_lsb, iid_lsb);
490 *addr |= ((u64)i << idx_lsb);
491 *addr |= ((u64)v << iid_lsb);
498 /* For VQDR, we may not modify the Channel bits, which might overlap
499 * with the Index bit. When it does, we need to ensure that isld0 == isld1.
501 static int nfp_encode_basic(u64 *addr, int dest_island, int cpp_tgt,
502 int mode, bool addr40, int isld1, int isld0)
504 int iid_lsb, idx_lsb;
511 /* This function doesn't handle MU or CTXBP */
512 if (cpp_tgt == NFP_CPP_TARGET_MU || cpp_tgt == NFP_CPP_TARGET_CT_XPB)
517 if (cpp_tgt == NFP_CPP_TARGET_QDR && !addr40)
518 /* In this specific mode we'd rather not modify
519 * the address but we can verify if the existing
520 * contents will point to a valid island.
522 return nfp_encode_basic_qdr(*addr, cpp_tgt, dest_island,
523 mode, addr40, isld1, isld0);
525 iid_lsb = addr40 ? 34 : 26;
526 /* <39:34> or <31:26> */
527 v64 = GENMASK_ULL(iid_lsb + 5, iid_lsb);
529 *addr |= ((u64)dest_island << iid_lsb) & v64;
532 if (cpp_tgt == NFP_CPP_TARGET_QDR && !addr40)
533 return nfp_encode_basic_qdr(*addr, cpp_tgt, dest_island,
534 mode, addr40, isld1, isld0);
536 idx_lsb = addr40 ? 39 : 31;
537 if (dest_island == isld0) {
538 /* Only need to clear the Index bit */
539 *addr &= ~BIT_ULL(idx_lsb);
543 if (dest_island == isld1) {
544 /* Only need to set the Index bit */
545 *addr |= BIT_ULL(idx_lsb);
551 /* iid<0> = addr<30> = channel<0>
552 * channel<1> = addr<31> = Index
554 if (cpp_tgt == NFP_CPP_TARGET_QDR && !addr40)
555 /* Special case where we allow channel bits to
556 * be set before hand and with them select an island.
557 * So we need to confirm that it's at least plausible.
559 return nfp_encode_basic_qdr(*addr, cpp_tgt, dest_island,
560 mode, addr40, isld1, isld0);
562 /* Make sure we compare against isldN values
563 * by clearing the LSB.
564 * This is what the silicon does.
569 idx_lsb = addr40 ? 39 : 31;
570 iid_lsb = idx_lsb - 1;
572 return nfp_encode_basic_search(addr, dest_island, isld,
573 iid_lsb, idx_lsb, 2);
575 if (cpp_tgt == NFP_CPP_TARGET_QDR && !addr40)
576 /* iid<0> = addr<29> = data
577 * iid<1> = addr<30> = channel<0>
578 * channel<1> = addr<31> = Index
580 return nfp_encode_basic_qdr(*addr, cpp_tgt, dest_island,
581 mode, addr40, isld1, isld0);
586 idx_lsb = addr40 ? 39 : 31;
587 iid_lsb = idx_lsb - 2;
589 return nfp_encode_basic_search(addr, dest_island, isld,
590 iid_lsb, idx_lsb, 4);
596 static int nfp_encode_mu(u64 *addr, int dest_island, int mode,
597 bool addr40, int isld1, int isld0)
599 int iid_lsb, idx_lsb, locality_lsb;
606 locality_lsb = nfp_cppat_mu_locality_lsb(mode, addr40);
608 if (((*addr >> locality_lsb) & 3) == _NIC_NFP6000_MU_LOCALITY_DIRECT)
615 iid_lsb = addr40 ? 32 : 24;
616 v64 = GENMASK_ULL(iid_lsb + 5, iid_lsb);
618 *addr |= (((u64)dest_island) << iid_lsb) & v64;
622 iid_lsb = addr40 ? 32 : 24;
623 v64 = GENMASK_ULL(iid_lsb + 5, iid_lsb);
625 *addr |= (((u64)dest_island) << iid_lsb) & v64;
629 idx_lsb = addr40 ? 37 : 29;
630 if (dest_island == isld0) {
631 *addr &= ~BIT_ULL(idx_lsb);
635 if (dest_island == isld1) {
636 *addr |= BIT_ULL(idx_lsb);
643 iid_lsb = addr40 ? 32 : 24;
644 v64 = GENMASK_ULL(iid_lsb + 5, iid_lsb);
646 *addr |= (((u64)dest_island) << iid_lsb) & v64;
650 /* Make sure we compare against isldN values
651 * by clearing the LSB.
652 * This is what the silicon does.
657 idx_lsb = addr40 ? 37 : 29;
658 iid_lsb = idx_lsb - 1;
660 return nfp_encode_basic_search(addr, dest_island, isld,
661 iid_lsb, idx_lsb, 2);
663 /* Only the EMU will use 40 bit addressing. Silently
664 * set the direct locality bit for everyone else.
665 * The SDK toolchain uses dest_island <= 0 to test
666 * for atypical address encodings to support access
667 * to local-island CTM with a 32-but address (high-locality
668 * is effewctively ignored and just used for
669 * routing to island #0).
671 if (dest_island > 0 && (dest_island < 24 || dest_island > 26)) {
672 *addr |= ((u64)_NIC_NFP6000_MU_LOCALITY_DIRECT)
678 iid_lsb = addr40 ? 32 : 24;
679 v64 = GENMASK_ULL(iid_lsb + 5, iid_lsb);
681 *addr |= (((u64)dest_island) << iid_lsb) & v64;
688 idx_lsb = addr40 ? 37 : 29;
689 iid_lsb = idx_lsb - 2;
691 return nfp_encode_basic_search(addr, dest_island, isld,
692 iid_lsb, idx_lsb, 4);
698 static int nfp_cppat_addr_encode(u64 *addr, int dest_island, int cpp_tgt,
699 int mode, bool addr40, int isld1, int isld0)
702 case NFP_CPP_TARGET_NBI:
703 case NFP_CPP_TARGET_QDR:
704 case NFP_CPP_TARGET_ILA:
705 case NFP_CPP_TARGET_PCIE:
706 case NFP_CPP_TARGET_ARM:
707 case NFP_CPP_TARGET_CRYPTO:
708 case NFP_CPP_TARGET_CLS:
709 return nfp_encode_basic(addr, dest_island, cpp_tgt, mode,
710 addr40, isld1, isld0);
712 case NFP_CPP_TARGET_MU:
713 return nfp_encode_mu(addr, dest_island, mode,
714 addr40, isld1, isld0);
716 case NFP_CPP_TARGET_CT_XPB:
717 if (mode != 1 || addr40)
719 *addr &= ~GENMASK_ULL(29, 24);
720 *addr |= ((u64)dest_island << 24) & GENMASK_ULL(29, 24);
727 int nfp_target_cpp(u32 cpp_island_id, u64 cpp_island_address,
728 u32 *cpp_target_id, u64 *cpp_target_address,
729 const u32 *imb_table)
731 const int island = NFP_CPP_ID_ISLAND_of(cpp_island_id);
732 const int target = NFP_CPP_ID_TARGET_of(cpp_island_id);
736 if (target < 0 || target >= 16)
740 /* Already translated */
741 *cpp_target_id = cpp_island_id;
742 *cpp_target_address = cpp_island_address;
746 /* CPP + Island only allowed on systems with IMB tables */
750 imb = imb_table[target];
752 *cpp_target_address = cpp_island_address;
753 err = nfp_cppat_addr_encode(cpp_target_address, island, target,
754 ((imb >> 13) & 7), ((imb >> 12) & 1),
755 ((imb >> 6) & 0x3f), ((imb >> 0) & 0x3f));
759 *cpp_target_id = NFP_CPP_ID(target,
760 NFP_CPP_ID_ACTION_of(cpp_island_id),
761 NFP_CPP_ID_TOKEN_of(cpp_island_id));