1 /* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org>
8 This software may be used and distributed according to the terms of
9 the GNU General Public License (GPL), incorporated herein by reference.
10 Drivers based on or derived from this code fall under the GPL and must
11 retain the authorship, copyright and license notice. This file is not
12 a complete program and may only be used when the entire operating
13 system is licensed under the GPL. License for under other terms may be
14 available. Contact the original author for details.
16 The original author may be reached as becker@scyld.com, or at
17 Scyld Computing Corporation
18 410 Severn Ave., Suite 210
21 Support information and updates available at
22 http://www.scyld.com/network/netsemi.html
23 [link no longer provides useful info -jgarzik]
27 * big endian support with CFG:BEM instead of cpu_to_le32
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/string.h>
33 #include <linux/timer.h>
34 #include <linux/errno.h>
35 #include <linux/ioport.h>
36 #include <linux/slab.h>
37 #include <linux/interrupt.h>
38 #include <linux/pci.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 #include <linux/skbuff.h>
42 #include <linux/init.h>
43 #include <linux/spinlock.h>
44 #include <linux/ethtool.h>
45 #include <linux/delay.h>
46 #include <linux/rtnetlink.h>
47 #include <linux/mii.h>
48 #include <linux/crc32.h>
49 #include <linux/bitops.h>
50 #include <linux/prefetch.h>
51 #include <asm/processor.h> /* Processor type for cache alignment. */
54 #include <linux/uaccess.h>
56 #define DRV_NAME "natsemi"
57 #define DRV_VERSION "2.1"
58 #define DRV_RELDATE "Sept 11, 2006"
62 /* Updated to recommendations in pci-skeleton v2.03. */
64 /* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
67 #define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
72 static int debug = -1;
76 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
77 This chip uses a 512 element hash table based on the Ethernet CRC. */
78 static const int multicast_filter_limit = 100;
80 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
81 Setting to > 1518 effectively disables this feature. */
82 static int rx_copybreak;
84 static int dspcfg_workaround = 1;
86 /* Used to pass the media type, etc.
87 Both 'options[]' and 'full_duplex[]' should exist for driver
89 The media type is usually passed in 'options[]'.
91 #define MAX_UNITS 8 /* More are supported, limit only on options */
92 static int options[MAX_UNITS];
93 static int full_duplex[MAX_UNITS];
95 /* Operational parameters that are set at compile time. */
97 /* Keep the ring sizes a power of two for compile efficiency.
98 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
99 Making the Tx ring too large decreases the effectiveness of channel
100 bonding and packet priority.
101 There are no ill effects from too-large receive rings. */
102 #define TX_RING_SIZE 16
103 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
104 #define RX_RING_SIZE 32
106 /* Operational parameters that usually are not changed. */
107 /* Time in jiffies before concluding the transmitter is hung. */
108 #define TX_TIMEOUT (2*HZ)
110 #define NATSEMI_HW_TIMEOUT 400
111 #define NATSEMI_TIMER_FREQ 5*HZ
112 #define NATSEMI_PG0_NREGS 64
113 #define NATSEMI_RFDR_NREGS 8
114 #define NATSEMI_PG1_NREGS 4
115 #define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
117 #define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
118 #define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
121 * The nic writes 32-bit values, even if the upper bytes of
122 * a 32-bit value are beyond the end of the buffer.
124 #define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
125 #define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
126 #define NATSEMI_LONGPKT 1518 /* limit for normal packets */
127 #define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
129 /* These identify the driver base version and may not be removed. */
130 static const char version[] =
131 KERN_INFO DRV_NAME " dp8381x driver, version "
132 DRV_VERSION ", " DRV_RELDATE "\n"
133 " originally by Donald Becker <becker@scyld.com>\n"
134 " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
136 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
137 MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
138 MODULE_LICENSE("GPL");
140 module_param(mtu, int, 0);
141 module_param(debug, int, 0);
142 module_param(rx_copybreak, int, 0);
143 module_param(dspcfg_workaround, int, 0);
144 module_param_array(options, int, NULL, 0);
145 module_param_array(full_duplex, int, NULL, 0);
146 MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
147 MODULE_PARM_DESC(debug, "DP8381x default debug level");
148 MODULE_PARM_DESC(rx_copybreak,
149 "DP8381x copy breakpoint for copy-only-tiny-frames");
150 MODULE_PARM_DESC(dspcfg_workaround, "DP8381x: control DspCfg workaround");
151 MODULE_PARM_DESC(options,
152 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
153 MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
158 I. Board Compatibility
160 This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
161 It also works with other chips in in the DP83810 series.
163 II. Board-specific settings
165 This driver requires the PCI interrupt line to be valid.
166 It honors the EEPROM-set values.
168 III. Driver operation
172 This driver uses two statically allocated fixed-size descriptor lists
173 formed into rings by a branch from the final descriptor to the beginning of
174 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
175 The NatSemi design uses a 'next descriptor' pointer that the driver forms
178 IIIb/c. Transmit/Receive Structure
180 This driver uses a zero-copy receive and transmit scheme.
181 The driver allocates full frame size skbuffs for the Rx ring buffers at
182 open() time and passes the skb->data field to the chip as receive data
183 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
184 a fresh skbuff is allocated and the frame is copied to the new skbuff.
185 When the incoming frame is larger, the skbuff is passed directly up the
186 protocol stack. Buffers consumed this way are replaced by newly allocated
187 skbuffs in a later phase of receives.
189 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
190 using a full-sized skbuff for small frames vs. the copying costs of larger
191 frames. New boards are typically used in generously configured machines
192 and the underfilled buffers have negligible impact compared to the benefit of
193 a single allocation size, so the default value of zero results in never
194 copying packets. When copying is done, the cost is usually mitigated by using
195 a combined copy/checksum routine. Copying also preloads the cache, which is
196 most useful with small frames.
198 A subtle aspect of the operation is that unaligned buffers are not permitted
199 by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
200 longword aligned for further processing. On copies frames are put into the
201 skbuff at an offset of "+2", 16-byte aligning the IP header.
203 IIId. Synchronization
205 Most operations are synchronized on the np->lock irq spinlock, except the
206 receive and transmit paths which are synchronised using a combination of
207 hardware descriptor ownership, disabling interrupts and NAPI poll scheduling.
211 http://www.scyld.com/expert/100mbps.html
212 http://www.scyld.com/expert/NWay.html
213 Datasheet is available from:
214 http://www.national.com/pf/DP/DP83815.html
224 * Support for fibre connections on Am79C874:
225 * This phy needs a special setup when connected to a fibre cable.
226 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
228 #define PHYID_AM79C874 0x0022561b
231 MII_MCTRL = 0x15, /* mode control register */
232 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
233 MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
237 NATSEMI_FLAG_IGNORE_PHY = 0x1,
240 /* array of board data directly indexed by pci_tbl[x].driver_data */
244 unsigned int eeprom_size;
245 } natsemi_pci_info[] = {
246 { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 },
247 { "NatSemi DP8381[56]", 0, 24 },
250 static const struct pci_device_id natsemi_pci_tbl[] = {
251 { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 },
252 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
253 { } /* terminate list */
255 MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
257 /* Offsets to the device registers.
258 Unlike software-only systems, device drivers interact with complex hardware.
259 It's not useful to define symbolic names for every register bit in the
262 enum register_offsets {
270 IntrHoldoff = 0x1C, /* DP83816 only */
297 /* These are from the spec, around page 78... on a separate table.
298 * The meaning of these registers depend on the value of PGSEL. */
305 /* the values for the 'magic' registers above (PGSEL=1) */
306 #define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
307 #define TSTDAT_VAL 0x0
308 #define DSPCFG_VAL 0x5040
309 #define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
310 #define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
311 #define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
312 #define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
314 /* misc PCI space registers */
315 enum pci_register_offsets {
329 enum ChipConfig_bits {
333 CfgAnegEnable = 0x2000,
335 CfgAnegFull = 0x8000,
336 CfgAnegDone = 0x8000000,
337 CfgFullDuplex = 0x20000000,
338 CfgSpeed100 = 0x40000000,
339 CfgLink = 0x80000000,
345 EE_ChipSelect = 0x08,
352 enum PCIBusCfg_bits {
356 /* Bits in the interrupt status/mask registers. */
357 enum IntrStatus_bits {
361 IntrRxEarly = 0x0008,
363 IntrRxOverrun = 0x0020,
368 IntrTxUnderrun = 0x0400,
373 IntrHighBits = 0x8000,
374 RxStatusFIFOOver = 0x10000,
375 IntrPCIErr = 0xf00000,
376 RxResetDone = 0x1000000,
377 TxResetDone = 0x2000000,
378 IntrAbnormalSummary = 0xCD20,
382 * Default Interrupts:
383 * Rx OK, Rx Packet Error, Rx Overrun,
384 * Tx OK, Tx Packet Error, Tx Underrun,
385 * MIB Service, Phy Interrupt, High Bits,
386 * Rx Status FIFO overrun,
387 * Received Target Abort, Received Master Abort,
388 * Signalled System Error, Received Parity Error
390 #define DEFAULT_INTR 0x00f1cd65
395 TxMxdmaMask = 0x700000,
397 TxMxdma_4 = 0x100000,
398 TxMxdma_8 = 0x200000,
399 TxMxdma_16 = 0x300000,
400 TxMxdma_32 = 0x400000,
401 TxMxdma_64 = 0x500000,
402 TxMxdma_128 = 0x600000,
403 TxMxdma_256 = 0x700000,
404 TxCollRetry = 0x800000,
405 TxAutoPad = 0x10000000,
406 TxMacLoop = 0x20000000,
407 TxHeartIgn = 0x40000000,
408 TxCarrierIgn = 0x80000000
413 * - 256 byte DMA burst length
414 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
415 * - 64 bytes initial drain threshold (i.e. begin actual transmission
416 * when 64 byte are in the fifo)
417 * - on tx underruns, increase drain threshold by 64.
418 * - at most use a drain threshold of 1472 bytes: The sum of the fill
419 * threshold and the drain threshold must be less than 2016 bytes.
422 #define TX_FLTH_VAL ((512/32) << 8)
423 #define TX_DRTH_VAL_START (64/32)
424 #define TX_DRTH_VAL_INC 2
425 #define TX_DRTH_VAL_LIMIT (1472/32)
429 RxMxdmaMask = 0x700000,
431 RxMxdma_4 = 0x100000,
432 RxMxdma_8 = 0x200000,
433 RxMxdma_16 = 0x300000,
434 RxMxdma_32 = 0x400000,
435 RxMxdma_64 = 0x500000,
436 RxMxdma_128 = 0x600000,
437 RxMxdma_256 = 0x700000,
438 RxAcceptLong = 0x8000000,
439 RxAcceptTx = 0x10000000,
440 RxAcceptRunt = 0x40000000,
441 RxAcceptErr = 0x80000000
443 #define RX_DRTH_VAL (128/8)
461 WakeMagicSecure = 0x400,
462 SecureHack = 0x100000,
464 WokeUnicast = 0x800000,
465 WokeMulticast = 0x1000000,
466 WokeBroadcast = 0x2000000,
468 WokePMatch0 = 0x8000000,
469 WokePMatch1 = 0x10000000,
470 WokePMatch2 = 0x20000000,
471 WokePMatch3 = 0x40000000,
472 WokeMagic = 0x80000000,
473 WakeOptsSummary = 0x7ff
476 enum RxFilterAddr_bits {
477 RFCRAddressMask = 0x3ff,
478 AcceptMulticast = 0x00200000,
479 AcceptMyPhys = 0x08000000,
480 AcceptAllPhys = 0x10000000,
481 AcceptAllMulticast = 0x20000000,
482 AcceptBroadcast = 0x40000000,
483 RxFilterEnable = 0x80000000
486 enum StatsCtrl_bits {
493 enum MIntrCtrl_bits {
501 #define PHY_ADDR_NONE 32
502 #define PHY_ADDR_INTERNAL 1
504 /* values we might find in the silicon revision register */
505 #define SRR_DP83815_C 0x0302
506 #define SRR_DP83815_D 0x0403
507 #define SRR_DP83816_A4 0x0504
508 #define SRR_DP83816_A5 0x0505
510 /* The Rx and Tx buffer descriptors. */
511 /* Note that using only 32 bit fields simplifies conversion to big-endian
520 /* Bits in network_desc.status */
521 enum desc_status_bits {
522 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
523 DescNoCRC=0x10000000, DescPktOK=0x08000000,
526 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
527 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
528 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
529 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
531 DescRxAbort=0x04000000, DescRxOver=0x02000000,
532 DescRxDest=0x01800000, DescRxLong=0x00400000,
533 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
534 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
535 DescRxLoop=0x00020000, DesRxColl=0x00010000,
538 struct netdev_private {
539 /* Descriptor rings first for alignment */
541 struct netdev_desc *rx_ring;
542 struct netdev_desc *tx_ring;
543 /* The addresses of receive-in-place skbuffs */
544 struct sk_buff *rx_skbuff[RX_RING_SIZE];
545 dma_addr_t rx_dma[RX_RING_SIZE];
546 /* address of a sent-in-place packet/buffer, for later free() */
547 struct sk_buff *tx_skbuff[TX_RING_SIZE];
548 dma_addr_t tx_dma[TX_RING_SIZE];
549 struct net_device *dev;
550 void __iomem *ioaddr;
551 struct napi_struct napi;
552 /* Media monitoring timer */
553 struct timer_list timer;
554 /* Frequently used values: keep some adjacent for cache effect */
555 struct pci_dev *pci_dev;
556 struct netdev_desc *rx_head_desc;
557 /* Producer/consumer ring indices */
558 unsigned int cur_rx, dirty_rx;
559 unsigned int cur_tx, dirty_tx;
560 /* Based on MTU+slack. */
561 unsigned int rx_buf_sz;
563 /* Interrupt status */
565 /* Do not touch the nic registers */
567 /* Don't pay attention to the reported link state. */
569 /* external phy that is used: only valid if dev->if_port != PORT_TP */
571 int phy_addr_external;
572 unsigned int full_duplex;
576 /* FIFO and PCI burst thresholds */
577 u32 tx_config, rx_config;
578 /* original contents of ClkRun register */
580 /* silicon revision */
582 /* expected DSPCFG value */
584 int dspcfg_workaround;
585 /* parms saved in ethtool format */
586 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
587 u8 duplex; /* Duplex, half or full */
588 u8 autoneg; /* Autonegotiation enabled */
589 /* MII transceiver section */
598 static void move_int_phy(struct net_device *dev, int addr);
599 static int eeprom_read(void __iomem *ioaddr, int location);
600 static int mdio_read(struct net_device *dev, int reg);
601 static void mdio_write(struct net_device *dev, int reg, u16 data);
602 static void init_phy_fixup(struct net_device *dev);
603 static int miiport_read(struct net_device *dev, int phy_id, int reg);
604 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
605 static int find_mii(struct net_device *dev);
606 static void natsemi_reset(struct net_device *dev);
607 static void natsemi_reload_eeprom(struct net_device *dev);
608 static void natsemi_stop_rxtx(struct net_device *dev);
609 static int netdev_open(struct net_device *dev);
610 static void do_cable_magic(struct net_device *dev);
611 static void undo_cable_magic(struct net_device *dev);
612 static void check_link(struct net_device *dev);
613 static void netdev_timer(unsigned long data);
614 static void dump_ring(struct net_device *dev);
615 static void ns_tx_timeout(struct net_device *dev);
616 static int alloc_ring(struct net_device *dev);
617 static void refill_rx(struct net_device *dev);
618 static void init_ring(struct net_device *dev);
619 static void drain_tx(struct net_device *dev);
620 static void drain_ring(struct net_device *dev);
621 static void free_ring(struct net_device *dev);
622 static void reinit_ring(struct net_device *dev);
623 static void init_registers(struct net_device *dev);
624 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
625 static irqreturn_t intr_handler(int irq, void *dev_instance);
626 static void netdev_error(struct net_device *dev, int intr_status);
627 static int natsemi_poll(struct napi_struct *napi, int budget);
628 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
629 static void netdev_tx_done(struct net_device *dev);
630 static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
631 #ifdef CONFIG_NET_POLL_CONTROLLER
632 static void natsemi_poll_controller(struct net_device *dev);
634 static void __set_rx_mode(struct net_device *dev);
635 static void set_rx_mode(struct net_device *dev);
636 static void __get_stats(struct net_device *dev);
637 static struct net_device_stats *get_stats(struct net_device *dev);
638 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
639 static int netdev_set_wol(struct net_device *dev, u32 newval);
640 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
641 static int netdev_set_sopass(struct net_device *dev, u8 *newval);
642 static int netdev_get_sopass(struct net_device *dev, u8 *data);
643 static int netdev_get_ecmd(struct net_device *dev,
644 struct ethtool_link_ksettings *ecmd);
645 static int netdev_set_ecmd(struct net_device *dev,
646 const struct ethtool_link_ksettings *ecmd);
647 static void enable_wol_mode(struct net_device *dev, int enable_intr);
648 static int netdev_close(struct net_device *dev);
649 static int netdev_get_regs(struct net_device *dev, u8 *buf);
650 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
651 static const struct ethtool_ops ethtool_ops;
653 #define NATSEMI_ATTR(_name) \
654 static ssize_t natsemi_show_##_name(struct device *dev, \
655 struct device_attribute *attr, char *buf); \
656 static ssize_t natsemi_set_##_name(struct device *dev, \
657 struct device_attribute *attr, \
658 const char *buf, size_t count); \
659 static DEVICE_ATTR(_name, 0644, natsemi_show_##_name, natsemi_set_##_name)
661 #define NATSEMI_CREATE_FILE(_dev, _name) \
662 device_create_file(&_dev->dev, &dev_attr_##_name)
663 #define NATSEMI_REMOVE_FILE(_dev, _name) \
664 device_remove_file(&_dev->dev, &dev_attr_##_name)
666 NATSEMI_ATTR(dspcfg_workaround);
668 static ssize_t natsemi_show_dspcfg_workaround(struct device *dev,
669 struct device_attribute *attr,
672 struct netdev_private *np = netdev_priv(to_net_dev(dev));
674 return sprintf(buf, "%s\n", np->dspcfg_workaround ? "on" : "off");
677 static ssize_t natsemi_set_dspcfg_workaround(struct device *dev,
678 struct device_attribute *attr,
679 const char *buf, size_t count)
681 struct netdev_private *np = netdev_priv(to_net_dev(dev));
685 /* Find out the new setting */
686 if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1))
688 else if (!strncmp("off", buf, count - 1) ||
689 !strncmp("0", buf, count - 1))
694 spin_lock_irqsave(&np->lock, flags);
696 np->dspcfg_workaround = new_setting;
698 spin_unlock_irqrestore(&np->lock, flags);
703 static inline void __iomem *ns_ioaddr(struct net_device *dev)
705 struct netdev_private *np = netdev_priv(dev);
710 static inline void natsemi_irq_enable(struct net_device *dev)
712 writel(1, ns_ioaddr(dev) + IntrEnable);
713 readl(ns_ioaddr(dev) + IntrEnable);
716 static inline void natsemi_irq_disable(struct net_device *dev)
718 writel(0, ns_ioaddr(dev) + IntrEnable);
719 readl(ns_ioaddr(dev) + IntrEnable);
722 static void move_int_phy(struct net_device *dev, int addr)
724 struct netdev_private *np = netdev_priv(dev);
725 void __iomem *ioaddr = ns_ioaddr(dev);
729 * The internal phy is visible on the external mii bus. Therefore we must
730 * move it away before we can send commands to an external phy.
731 * There are two addresses we must avoid:
732 * - the address on the external phy that is used for transmission.
733 * - the address that we want to access. User space can access phys
734 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independent from the
735 * phy that is used for transmission.
740 if (target == np->phy_addr_external)
742 writew(target, ioaddr + PhyCtrl);
743 readw(ioaddr + PhyCtrl);
747 static void natsemi_init_media(struct net_device *dev)
749 struct netdev_private *np = netdev_priv(dev);
753 netif_carrier_on(dev);
755 netif_carrier_off(dev);
757 /* get the initial settings from hardware */
758 tmp = mdio_read(dev, MII_BMCR);
759 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
760 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
761 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
762 np->advertising= mdio_read(dev, MII_ADVERTISE);
764 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL &&
765 netif_msg_probe(np)) {
766 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
768 pci_name(np->pci_dev),
769 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
770 "enabled, advertise" : "disabled, force",
772 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
775 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
778 if (netif_msg_probe(np))
780 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
781 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
786 static const struct net_device_ops natsemi_netdev_ops = {
787 .ndo_open = netdev_open,
788 .ndo_stop = netdev_close,
789 .ndo_start_xmit = start_tx,
790 .ndo_get_stats = get_stats,
791 .ndo_set_rx_mode = set_rx_mode,
792 .ndo_change_mtu = natsemi_change_mtu,
793 .ndo_do_ioctl = netdev_ioctl,
794 .ndo_tx_timeout = ns_tx_timeout,
795 .ndo_set_mac_address = eth_mac_addr,
796 .ndo_validate_addr = eth_validate_addr,
797 #ifdef CONFIG_NET_POLL_CONTROLLER
798 .ndo_poll_controller = natsemi_poll_controller,
802 static int natsemi_probe1(struct pci_dev *pdev, const struct pci_device_id *ent)
804 struct net_device *dev;
805 struct netdev_private *np;
806 int i, option, irq, chip_idx = ent->driver_data;
807 static int find_cnt = -1;
808 resource_size_t iostart;
809 unsigned long iosize;
810 void __iomem *ioaddr;
811 const int pcibar = 1; /* PCI base address register */
815 /* when built into the kernel, we only print version if device is found */
817 static int printed_version;
818 if (!printed_version++)
822 i = pcim_enable_device(pdev);
825 /* natsemi has a non-standard PM control register
826 * in PCI config space. Some boards apparently need
827 * to be brought to D0 in this manner.
829 pci_read_config_dword(pdev, PCIPM, &tmp);
830 if (tmp & PCI_PM_CTRL_STATE_MASK) {
831 /* D0 state, disable PME assertion */
832 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
833 pci_write_config_dword(pdev, PCIPM, newtmp);
837 iostart = pci_resource_start(pdev, pcibar);
838 iosize = pci_resource_len(pdev, pcibar);
841 pci_set_master(pdev);
843 dev = alloc_etherdev(sizeof (struct netdev_private));
846 SET_NETDEV_DEV(dev, &pdev->dev);
848 i = pci_request_regions(pdev, DRV_NAME);
850 goto err_pci_request_regions;
852 ioaddr = ioremap(iostart, iosize);
855 goto err_pci_request_regions;
858 /* Work around the dropped serial bit. */
859 prev_eedata = eeprom_read(ioaddr, 6);
860 for (i = 0; i < 3; i++) {
861 int eedata = eeprom_read(ioaddr, i + 7);
862 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
863 dev->dev_addr[i*2+1] = eedata >> 7;
864 prev_eedata = eedata;
867 np = netdev_priv(dev);
870 netif_napi_add(dev, &np->napi, natsemi_poll, 64);
874 pci_set_drvdata(pdev, dev);
876 spin_lock_init(&np->lock);
877 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
880 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size;
881 if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY)
885 np->dspcfg_workaround = dspcfg_workaround;
888 * - If configured to ignore the PHY set up for external.
889 * - If the nic was configured to use an external phy and if find_mii
890 * finds a phy: use external port, first phy that replies.
891 * - Otherwise: internal port.
892 * Note that the phy address for the internal phy doesn't matter:
893 * The address would be used to access a phy over the mii bus, but
894 * the internal phy is accessed through mapped registers.
896 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)
897 dev->if_port = PORT_MII;
899 dev->if_port = PORT_TP;
900 /* Reset the chip to erase previous misconfiguration. */
901 natsemi_reload_eeprom(dev);
904 if (dev->if_port != PORT_TP) {
905 np->phy_addr_external = find_mii(dev);
906 /* If we're ignoring the PHY it doesn't matter if we can't
908 if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) {
909 dev->if_port = PORT_TP;
910 np->phy_addr_external = PHY_ADDR_INTERNAL;
913 np->phy_addr_external = PHY_ADDR_INTERNAL;
916 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
917 /* The lower four bits are the media type. */
923 "natsemi %s: ignoring user supplied media type %d",
924 pci_name(np->pci_dev), option & 15);
926 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
929 dev->netdev_ops = &natsemi_netdev_ops;
930 dev->watchdog_timeo = TX_TIMEOUT;
932 dev->ethtool_ops = ðtool_ops;
934 /* MTU range: 64 - 2024 */
935 dev->min_mtu = ETH_ZLEN + ETH_FCS_LEN;
936 dev->max_mtu = NATSEMI_RX_LIMIT - NATSEMI_HEADERS;
941 natsemi_init_media(dev);
943 /* save the silicon revision for later querying */
944 np->srr = readl(ioaddr + SiliconRev);
945 if (netif_msg_hw(np))
946 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
947 pci_name(np->pci_dev), np->srr);
949 i = register_netdev(dev);
951 goto err_register_netdev;
952 i = NATSEMI_CREATE_FILE(pdev, dspcfg_workaround);
954 goto err_create_file;
956 if (netif_msg_drv(np)) {
957 printk(KERN_INFO "natsemi %s: %s at %#08llx "
959 dev->name, natsemi_pci_info[chip_idx].name,
960 (unsigned long long)iostart, pci_name(np->pci_dev),
962 if (dev->if_port == PORT_TP)
963 printk(", port TP.\n");
964 else if (np->ignore_phy)
965 printk(", port MII, ignoring PHY\n");
967 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
972 unregister_netdev(dev);
977 err_pci_request_regions:
983 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
984 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
986 /* Delay between EEPROM clock transitions.
987 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
988 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
989 made udelay() unreliable.
990 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
993 #define eeprom_delay(ee_addr) readl(ee_addr)
995 #define EE_Write0 (EE_ChipSelect)
996 #define EE_Write1 (EE_ChipSelect | EE_DataIn)
998 /* The EEPROM commands include the alway-set leading bit. */
1000 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1003 static int eeprom_read(void __iomem *addr, int location)
1007 void __iomem *ee_addr = addr + EECtrl;
1008 int read_cmd = location | EE_ReadCmd;
1010 writel(EE_Write0, ee_addr);
1012 /* Shift the read command bits out. */
1013 for (i = 10; i >= 0; i--) {
1014 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1015 writel(dataval, ee_addr);
1016 eeprom_delay(ee_addr);
1017 writel(dataval | EE_ShiftClk, ee_addr);
1018 eeprom_delay(ee_addr);
1020 writel(EE_ChipSelect, ee_addr);
1021 eeprom_delay(ee_addr);
1023 for (i = 0; i < 16; i++) {
1024 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1025 eeprom_delay(ee_addr);
1026 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1027 writel(EE_ChipSelect, ee_addr);
1028 eeprom_delay(ee_addr);
1031 /* Terminate the EEPROM access. */
1032 writel(EE_Write0, ee_addr);
1037 /* MII transceiver control section.
1038 * The 83815 series has an internal transceiver, and we present the
1039 * internal management registers as if they were MII connected.
1040 * External Phy registers are referenced through the MII interface.
1043 /* clock transitions >= 20ns (25MHz)
1044 * One readl should be good to PCI @ 100MHz
1046 #define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1048 static int mii_getbit (struct net_device *dev)
1051 void __iomem *ioaddr = ns_ioaddr(dev);
1053 writel(MII_ShiftClk, ioaddr + EECtrl);
1054 data = readl(ioaddr + EECtrl);
1055 writel(0, ioaddr + EECtrl);
1057 return (data & MII_Data)? 1 : 0;
1060 static void mii_send_bits (struct net_device *dev, u32 data, int len)
1063 void __iomem *ioaddr = ns_ioaddr(dev);
1065 for (i = (1 << (len-1)); i; i >>= 1)
1067 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1068 writel(mdio_val, ioaddr + EECtrl);
1070 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1073 writel(0, ioaddr + EECtrl);
1077 static int miiport_read(struct net_device *dev, int phy_id, int reg)
1084 mii_send_bits (dev, 0xffffffff, 32);
1085 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1086 /* ST,OP = 0110'b for read operation */
1087 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1088 mii_send_bits (dev, cmd, 14);
1090 if (mii_getbit (dev))
1093 for (i = 0; i < 16; i++) {
1095 retval |= mii_getbit (dev);
1102 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1107 mii_send_bits (dev, 0xffffffff, 32);
1108 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1109 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1110 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1111 mii_send_bits (dev, cmd, 32);
1116 static int mdio_read(struct net_device *dev, int reg)
1118 struct netdev_private *np = netdev_priv(dev);
1119 void __iomem *ioaddr = ns_ioaddr(dev);
1121 /* The 83815 series has two ports:
1122 * - an internal transceiver
1123 * - an external mii bus
1125 if (dev->if_port == PORT_TP)
1126 return readw(ioaddr+BasicControl+(reg<<2));
1128 return miiport_read(dev, np->phy_addr_external, reg);
1131 static void mdio_write(struct net_device *dev, int reg, u16 data)
1133 struct netdev_private *np = netdev_priv(dev);
1134 void __iomem *ioaddr = ns_ioaddr(dev);
1136 /* The 83815 series has an internal transceiver; handle separately */
1137 if (dev->if_port == PORT_TP)
1138 writew(data, ioaddr+BasicControl+(reg<<2));
1140 miiport_write(dev, np->phy_addr_external, reg, data);
1143 static void init_phy_fixup(struct net_device *dev)
1145 struct netdev_private *np = netdev_priv(dev);
1146 void __iomem *ioaddr = ns_ioaddr(dev);
1151 /* restore stuff lost when power was out */
1152 tmp = mdio_read(dev, MII_BMCR);
1153 if (np->autoneg == AUTONEG_ENABLE) {
1154 /* renegotiate if something changed */
1155 if ((tmp & BMCR_ANENABLE) == 0 ||
1156 np->advertising != mdio_read(dev, MII_ADVERTISE))
1158 /* turn on autonegotiation and force negotiation */
1159 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1160 mdio_write(dev, MII_ADVERTISE, np->advertising);
1163 /* turn off auto negotiation, set speed and duplexity */
1164 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1165 if (np->speed == SPEED_100)
1166 tmp |= BMCR_SPEED100;
1167 if (np->duplex == DUPLEX_FULL)
1168 tmp |= BMCR_FULLDPLX;
1170 * Note: there is no good way to inform the link partner
1171 * that our capabilities changed. The user has to unplug
1172 * and replug the network cable after some changes, e.g.
1173 * after switching from 10HD, autoneg off to 100 HD,
1177 mdio_write(dev, MII_BMCR, tmp);
1178 readl(ioaddr + ChipConfig);
1181 /* find out what phy this is */
1182 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1183 + mdio_read(dev, MII_PHYSID2);
1185 /* handle external phys here */
1187 case PHYID_AM79C874:
1188 /* phy specific configuration for fibre/tp operation */
1189 tmp = mdio_read(dev, MII_MCTRL);
1190 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1191 if (dev->if_port == PORT_FIBRE)
1195 mdio_write(dev, MII_MCTRL, tmp);
1200 cfg = readl(ioaddr + ChipConfig);
1201 if (cfg & CfgExtPhy)
1204 /* On page 78 of the spec, they recommend some settings for "optimum
1205 performance" to be done in sequence. These settings optimize some
1206 of the 100Mbit autodetection circuitry. They say we only want to
1207 do this for rev C of the chip, but engineers at NSC (Bradley
1208 Kennedy) recommends always setting them. If you don't, you get
1209 errors on some autonegotiations that make the device unusable.
1211 It seems that the DSP needs a few usec to reinitialize after
1212 the start of the phy. Just retry writing these values until they
1215 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1218 writew(1, ioaddr + PGSEL);
1219 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1220 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1221 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1222 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1223 writew(np->dspcfg, ioaddr + DSPCFG);
1224 writew(SDCFG_VAL, ioaddr + SDCFG);
1225 writew(0, ioaddr + PGSEL);
1226 readl(ioaddr + ChipConfig);
1229 writew(1, ioaddr + PGSEL);
1230 dspcfg = readw(ioaddr + DSPCFG);
1231 writew(0, ioaddr + PGSEL);
1232 if (np->dspcfg == dspcfg)
1236 if (netif_msg_link(np)) {
1237 if (i==NATSEMI_HW_TIMEOUT) {
1239 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1243 "%s: DSPCFG accepted after %d usec.\n",
1248 * Enable PHY Specific event based interrupts. Link state change
1249 * and Auto-Negotiation Completion are among the affected.
1250 * Read the intr status to clear it (needed for wake events).
1252 readw(ioaddr + MIntrStatus);
1253 writew(MICRIntEn, ioaddr + MIntrCtrl);
1256 static int switch_port_external(struct net_device *dev)
1258 struct netdev_private *np = netdev_priv(dev);
1259 void __iomem *ioaddr = ns_ioaddr(dev);
1262 cfg = readl(ioaddr + ChipConfig);
1263 if (cfg & CfgExtPhy)
1266 if (netif_msg_link(np)) {
1267 printk(KERN_INFO "%s: switching to external transceiver.\n",
1271 /* 1) switch back to external phy */
1272 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1273 readl(ioaddr + ChipConfig);
1276 /* 2) reset the external phy: */
1277 /* resetting the external PHY has been known to cause a hub supplying
1278 * power over Ethernet to kill the power. We don't want to kill
1279 * power to this computer, so we avoid resetting the phy.
1282 /* 3) reinit the phy fixup, it got lost during power down. */
1283 move_int_phy(dev, np->phy_addr_external);
1284 init_phy_fixup(dev);
1289 static int switch_port_internal(struct net_device *dev)
1291 struct netdev_private *np = netdev_priv(dev);
1292 void __iomem *ioaddr = ns_ioaddr(dev);
1297 cfg = readl(ioaddr + ChipConfig);
1298 if (!(cfg &CfgExtPhy))
1301 if (netif_msg_link(np)) {
1302 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1305 /* 1) switch back to internal phy: */
1306 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1307 writel(cfg, ioaddr + ChipConfig);
1308 readl(ioaddr + ChipConfig);
1311 /* 2) reset the internal phy: */
1312 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1313 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1314 readl(ioaddr + ChipConfig);
1316 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1317 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1318 if (!(bmcr & BMCR_RESET))
1322 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1324 "%s: phy reset did not complete in %d usec.\n",
1327 /* 3) reinit the phy fixup, it got lost during power down. */
1328 init_phy_fixup(dev);
1333 /* Scan for a PHY on the external mii bus.
1334 * There are two tricky points:
1335 * - Do not scan while the internal phy is enabled. The internal phy will
1336 * crash: e.g. reads from the DSPCFG register will return odd values and
1337 * the nasty random phy reset code will reset the nic every few seconds.
1338 * - The internal phy must be moved around, an external phy could
1339 * have the same address as the internal phy.
1341 static int find_mii(struct net_device *dev)
1343 struct netdev_private *np = netdev_priv(dev);
1348 /* Switch to external phy */
1349 did_switch = switch_port_external(dev);
1351 /* Scan the possible phy addresses:
1353 * PHY address 0 means that the phy is in isolate mode. Not yet
1354 * supported due to lack of test hardware. User space should
1355 * handle it through ethtool.
1357 for (i = 1; i <= 31; i++) {
1358 move_int_phy(dev, i);
1359 tmp = miiport_read(dev, i, MII_BMSR);
1360 if (tmp != 0xffff && tmp != 0x0000) {
1361 /* found something! */
1362 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1363 + mdio_read(dev, MII_PHYSID2);
1364 if (netif_msg_probe(np)) {
1365 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1366 pci_name(np->pci_dev), np->mii, i);
1371 /* And switch back to internal phy: */
1373 switch_port_internal(dev);
1377 /* CFG bits [13:16] [18:23] */
1378 #define CFG_RESET_SAVE 0xfde000
1379 /* WCSR bits [0:4] [9:10] */
1380 #define WCSR_RESET_SAVE 0x61f
1381 /* RFCR bits [20] [22] [27:31] */
1382 #define RFCR_RESET_SAVE 0xf8500000
1384 static void natsemi_reset(struct net_device *dev)
1392 struct netdev_private *np = netdev_priv(dev);
1393 void __iomem *ioaddr = ns_ioaddr(dev);
1396 * Resetting the chip causes some registers to be lost.
1397 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1398 * we save the state that would have been loaded from EEPROM
1399 * on a normal power-up (see the spec EEPROM map). This assumes
1400 * whoever calls this will follow up with init_registers() eventually.
1404 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1406 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1408 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1410 for (i = 0; i < 3; i++) {
1411 writel(i*2, ioaddr + RxFilterAddr);
1412 pmatch[i] = readw(ioaddr + RxFilterData);
1415 for (i = 0; i < 3; i++) {
1416 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1417 sopass[i] = readw(ioaddr + RxFilterData);
1420 /* now whack the chip */
1421 writel(ChipReset, ioaddr + ChipCmd);
1422 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1423 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1427 if (i==NATSEMI_HW_TIMEOUT) {
1428 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1430 } else if (netif_msg_hw(np)) {
1431 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1436 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1437 /* turn on external phy if it was selected */
1438 if (dev->if_port == PORT_TP)
1439 cfg &= ~(CfgExtPhy | CfgPhyDis);
1441 cfg |= (CfgExtPhy | CfgPhyDis);
1442 writel(cfg, ioaddr + ChipConfig);
1444 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1445 writel(wcsr, ioaddr + WOLCmd);
1447 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1448 /* restore PMATCH */
1449 for (i = 0; i < 3; i++) {
1450 writel(i*2, ioaddr + RxFilterAddr);
1451 writew(pmatch[i], ioaddr + RxFilterData);
1453 for (i = 0; i < 3; i++) {
1454 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1455 writew(sopass[i], ioaddr + RxFilterData);
1458 writel(rfcr, ioaddr + RxFilterAddr);
1461 static void reset_rx(struct net_device *dev)
1464 struct netdev_private *np = netdev_priv(dev);
1465 void __iomem *ioaddr = ns_ioaddr(dev);
1467 np->intr_status &= ~RxResetDone;
1469 writel(RxReset, ioaddr + ChipCmd);
1471 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1472 np->intr_status |= readl(ioaddr + IntrStatus);
1473 if (np->intr_status & RxResetDone)
1477 if (i==NATSEMI_HW_TIMEOUT) {
1478 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n",
1480 } else if (netif_msg_hw(np)) {
1481 printk(KERN_WARNING "%s: RX reset took %d usec.\n",
1486 static void natsemi_reload_eeprom(struct net_device *dev)
1488 struct netdev_private *np = netdev_priv(dev);
1489 void __iomem *ioaddr = ns_ioaddr(dev);
1492 writel(EepromReload, ioaddr + PCIBusCfg);
1493 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1495 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1498 if (i==NATSEMI_HW_TIMEOUT) {
1499 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1500 pci_name(np->pci_dev), i*50);
1501 } else if (netif_msg_hw(np)) {
1502 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1503 pci_name(np->pci_dev), i*50);
1507 static void natsemi_stop_rxtx(struct net_device *dev)
1509 void __iomem * ioaddr = ns_ioaddr(dev);
1510 struct netdev_private *np = netdev_priv(dev);
1513 writel(RxOff | TxOff, ioaddr + ChipCmd);
1514 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1515 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1519 if (i==NATSEMI_HW_TIMEOUT) {
1520 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1522 } else if (netif_msg_hw(np)) {
1523 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1528 static int netdev_open(struct net_device *dev)
1530 struct netdev_private *np = netdev_priv(dev);
1531 void __iomem * ioaddr = ns_ioaddr(dev);
1532 const int irq = np->pci_dev->irq;
1535 /* Reset the chip, just in case. */
1538 i = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev);
1541 if (netif_msg_ifup(np))
1542 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1544 i = alloc_ring(dev);
1549 napi_enable(&np->napi);
1552 spin_lock_irq(&np->lock);
1553 init_registers(dev);
1554 /* now set the MAC address according to dev->dev_addr */
1555 for (i = 0; i < 3; i++) {
1556 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1558 writel(i*2, ioaddr + RxFilterAddr);
1559 writew(mac, ioaddr + RxFilterData);
1561 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1562 spin_unlock_irq(&np->lock);
1564 netif_start_queue(dev);
1566 if (netif_msg_ifup(np))
1567 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1568 dev->name, (int)readl(ioaddr + ChipCmd));
1570 /* Set the timer to check for link beat. */
1571 init_timer(&np->timer);
1572 np->timer.expires = round_jiffies(jiffies + NATSEMI_TIMER_FREQ);
1573 np->timer.data = (unsigned long)dev;
1574 np->timer.function = netdev_timer; /* timer handler */
1575 add_timer(&np->timer);
1580 static void do_cable_magic(struct net_device *dev)
1582 struct netdev_private *np = netdev_priv(dev);
1583 void __iomem *ioaddr = ns_ioaddr(dev);
1585 if (dev->if_port != PORT_TP)
1588 if (np->srr >= SRR_DP83816_A5)
1592 * 100 MBit links with short cables can trip an issue with the chip.
1593 * The problem manifests as lots of CRC errors and/or flickering
1594 * activity LED while idle. This process is based on instructions
1595 * from engineers at National.
1597 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1600 writew(1, ioaddr + PGSEL);
1602 * coefficient visibility should already be enabled via
1605 data = readw(ioaddr + TSTDAT) & 0xff;
1607 * the value must be negative, and within certain values
1608 * (these values all come from National)
1610 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
1611 np = netdev_priv(dev);
1613 /* the bug has been triggered - fix the coefficient */
1614 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1615 /* lock the value */
1616 data = readw(ioaddr + DSPCFG);
1617 np->dspcfg = data | DSPCFG_LOCK;
1618 writew(np->dspcfg, ioaddr + DSPCFG);
1620 writew(0, ioaddr + PGSEL);
1624 static void undo_cable_magic(struct net_device *dev)
1627 struct netdev_private *np = netdev_priv(dev);
1628 void __iomem * ioaddr = ns_ioaddr(dev);
1630 if (dev->if_port != PORT_TP)
1633 if (np->srr >= SRR_DP83816_A5)
1636 writew(1, ioaddr + PGSEL);
1637 /* make sure the lock bit is clear */
1638 data = readw(ioaddr + DSPCFG);
1639 np->dspcfg = data & ~DSPCFG_LOCK;
1640 writew(np->dspcfg, ioaddr + DSPCFG);
1641 writew(0, ioaddr + PGSEL);
1644 static void check_link(struct net_device *dev)
1646 struct netdev_private *np = netdev_priv(dev);
1647 void __iomem * ioaddr = ns_ioaddr(dev);
1648 int duplex = np->duplex;
1651 /* If we are ignoring the PHY then don't try reading it. */
1653 goto propagate_state;
1655 /* The link status field is latched: it remains low after a temporary
1656 * link failure until it's read. We need the current link status,
1659 mdio_read(dev, MII_BMSR);
1660 bmsr = mdio_read(dev, MII_BMSR);
1662 if (!(bmsr & BMSR_LSTATUS)) {
1663 if (netif_carrier_ok(dev)) {
1664 if (netif_msg_link(np))
1665 printk(KERN_NOTICE "%s: link down.\n",
1667 netif_carrier_off(dev);
1668 undo_cable_magic(dev);
1672 if (!netif_carrier_ok(dev)) {
1673 if (netif_msg_link(np))
1674 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1675 netif_carrier_on(dev);
1676 do_cable_magic(dev);
1679 duplex = np->full_duplex;
1681 if (bmsr & BMSR_ANEGCOMPLETE) {
1682 int tmp = mii_nway_result(
1683 np->advertising & mdio_read(dev, MII_LPA));
1684 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1686 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1691 /* if duplex is set then bit 28 must be set, too */
1692 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1693 if (netif_msg_link(np))
1695 "%s: Setting %s-duplex based on negotiated "
1696 "link capability.\n", dev->name,
1697 duplex ? "full" : "half");
1699 np->rx_config |= RxAcceptTx;
1700 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1702 np->rx_config &= ~RxAcceptTx;
1703 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1705 writel(np->tx_config, ioaddr + TxConfig);
1706 writel(np->rx_config, ioaddr + RxConfig);
1710 static void init_registers(struct net_device *dev)
1712 struct netdev_private *np = netdev_priv(dev);
1713 void __iomem * ioaddr = ns_ioaddr(dev);
1715 init_phy_fixup(dev);
1717 /* clear any interrupts that are pending, such as wake events */
1718 readl(ioaddr + IntrStatus);
1720 writel(np->ring_dma, ioaddr + RxRingPtr);
1721 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1722 ioaddr + TxRingPtr);
1724 /* Initialize other registers.
1725 * Configure the PCI bus bursts and FIFO thresholds.
1726 * Configure for standard, in-spec Ethernet.
1727 * Start with half-duplex. check_link will update
1728 * to the correct settings.
1731 /* DRTH: 2: start tx if 64 bytes are in the fifo
1732 * FLTH: 0x10: refill with next packet if 512 bytes are free
1733 * MXDMA: 0: up to 256 byte bursts.
1734 * MXDMA must be <= FLTH
1738 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1739 TX_FLTH_VAL | TX_DRTH_VAL_START;
1740 writel(np->tx_config, ioaddr + TxConfig);
1742 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1743 * MXDMA 0: up to 256 byte bursts
1745 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1746 /* if receive ring now has bigger buffers than normal, enable jumbo */
1747 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1748 np->rx_config |= RxAcceptLong;
1750 writel(np->rx_config, ioaddr + RxConfig);
1753 * The PME bit is initialized from the EEPROM contents.
1754 * PCI cards probably have PME disabled, but motherboard
1755 * implementations may have PME set to enable WakeOnLan.
1756 * With PME set the chip will scan incoming packets but
1757 * nothing will be written to memory. */
1758 np->SavedClkRun = readl(ioaddr + ClkRun);
1759 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1760 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1761 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1762 dev->name, readl(ioaddr + WOLCmd));
1768 /* Enable interrupts by setting the interrupt mask. */
1769 writel(DEFAULT_INTR, ioaddr + IntrMask);
1770 natsemi_irq_enable(dev);
1772 writel(RxOn | TxOn, ioaddr + ChipCmd);
1773 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1779 * 1) check for link changes. Usually they are handled by the MII interrupt
1780 * but it doesn't hurt to check twice.
1781 * 2) check for sudden death of the NIC:
1782 * It seems that a reference set for this chip went out with incorrect info,
1783 * and there exist boards that aren't quite right. An unexpected voltage
1784 * drop can cause the PHY to get itself in a weird state (basically reset).
1785 * NOTE: this only seems to affect revC chips. The user can disable
1786 * this check via dspcfg_workaround sysfs option.
1787 * 3) check of death of the RX path due to OOM
1789 static void netdev_timer(unsigned long data)
1791 struct net_device *dev = (struct net_device *)data;
1792 struct netdev_private *np = netdev_priv(dev);
1793 void __iomem * ioaddr = ns_ioaddr(dev);
1794 int next_tick = NATSEMI_TIMER_FREQ;
1795 const int irq = np->pci_dev->irq;
1797 if (netif_msg_timer(np)) {
1798 /* DO NOT read the IntrStatus register,
1799 * a read clears any pending interrupts.
1801 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1805 if (dev->if_port == PORT_TP) {
1808 spin_lock_irq(&np->lock);
1809 /* check for a nasty random phy-reset - use dspcfg as a flag */
1810 writew(1, ioaddr+PGSEL);
1811 dspcfg = readw(ioaddr+DSPCFG);
1812 writew(0, ioaddr+PGSEL);
1813 if (np->dspcfg_workaround && dspcfg != np->dspcfg) {
1814 if (!netif_queue_stopped(dev)) {
1815 spin_unlock_irq(&np->lock);
1816 if (netif_msg_drv(np))
1817 printk(KERN_NOTICE "%s: possible phy reset: "
1818 "re-initializing\n", dev->name);
1820 spin_lock_irq(&np->lock);
1821 natsemi_stop_rxtx(dev);
1824 init_registers(dev);
1825 spin_unlock_irq(&np->lock);
1830 spin_unlock_irq(&np->lock);
1833 /* init_registers() calls check_link() for the above case */
1835 spin_unlock_irq(&np->lock);
1838 spin_lock_irq(&np->lock);
1840 spin_unlock_irq(&np->lock);
1848 writel(RxOn, ioaddr + ChipCmd);
1855 mod_timer(&np->timer, round_jiffies(jiffies + next_tick));
1857 mod_timer(&np->timer, jiffies + next_tick);
1860 static void dump_ring(struct net_device *dev)
1862 struct netdev_private *np = netdev_priv(dev);
1864 if (netif_msg_pktdata(np)) {
1866 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1867 for (i = 0; i < TX_RING_SIZE; i++) {
1868 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1869 i, np->tx_ring[i].next_desc,
1870 np->tx_ring[i].cmd_status,
1871 np->tx_ring[i].addr);
1873 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1874 for (i = 0; i < RX_RING_SIZE; i++) {
1875 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1876 i, np->rx_ring[i].next_desc,
1877 np->rx_ring[i].cmd_status,
1878 np->rx_ring[i].addr);
1883 static void ns_tx_timeout(struct net_device *dev)
1885 struct netdev_private *np = netdev_priv(dev);
1886 void __iomem * ioaddr = ns_ioaddr(dev);
1887 const int irq = np->pci_dev->irq;
1890 spin_lock_irq(&np->lock);
1891 if (!np->hands_off) {
1892 if (netif_msg_tx_err(np))
1894 "%s: Transmit timed out, status %#08x,"
1896 dev->name, readl(ioaddr + IntrStatus));
1901 init_registers(dev);
1904 "%s: tx_timeout while in hands_off state?\n",
1907 spin_unlock_irq(&np->lock);
1910 netif_trans_update(dev); /* prevent tx timeout */
1911 dev->stats.tx_errors++;
1912 netif_wake_queue(dev);
1915 static int alloc_ring(struct net_device *dev)
1917 struct netdev_private *np = netdev_priv(dev);
1918 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1919 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1923 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1927 static void refill_rx(struct net_device *dev)
1929 struct netdev_private *np = netdev_priv(dev);
1931 /* Refill the Rx ring buffers. */
1932 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1933 struct sk_buff *skb;
1934 int entry = np->dirty_rx % RX_RING_SIZE;
1935 if (np->rx_skbuff[entry] == NULL) {
1936 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1937 skb = netdev_alloc_skb(dev, buflen);
1938 np->rx_skbuff[entry] = skb;
1940 break; /* Better luck next round. */
1941 np->rx_dma[entry] = pci_map_single(np->pci_dev,
1942 skb->data, buflen, PCI_DMA_FROMDEVICE);
1943 if (pci_dma_mapping_error(np->pci_dev,
1944 np->rx_dma[entry])) {
1945 dev_kfree_skb_any(skb);
1946 np->rx_skbuff[entry] = NULL;
1947 break; /* Better luck next round. */
1949 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1951 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1953 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1954 if (netif_msg_rx_err(np))
1955 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1960 static void set_bufsize(struct net_device *dev)
1962 struct netdev_private *np = netdev_priv(dev);
1963 if (dev->mtu <= ETH_DATA_LEN)
1964 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1966 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1969 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1970 static void init_ring(struct net_device *dev)
1972 struct netdev_private *np = netdev_priv(dev);
1976 np->dirty_tx = np->cur_tx = 0;
1977 for (i = 0; i < TX_RING_SIZE; i++) {
1978 np->tx_skbuff[i] = NULL;
1979 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1980 +sizeof(struct netdev_desc)
1981 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1982 np->tx_ring[i].cmd_status = 0;
1987 np->cur_rx = RX_RING_SIZE;
1991 np->rx_head_desc = &np->rx_ring[0];
1993 /* Please be careful before changing this loop - at least gcc-2.95.1
1994 * miscompiles it otherwise.
1996 /* Initialize all Rx descriptors. */
1997 for (i = 0; i < RX_RING_SIZE; i++) {
1998 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1999 +sizeof(struct netdev_desc)
2000 *((i+1)%RX_RING_SIZE));
2001 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2002 np->rx_skbuff[i] = NULL;
2008 static void drain_tx(struct net_device *dev)
2010 struct netdev_private *np = netdev_priv(dev);
2013 for (i = 0; i < TX_RING_SIZE; i++) {
2014 if (np->tx_skbuff[i]) {
2015 pci_unmap_single(np->pci_dev,
2016 np->tx_dma[i], np->tx_skbuff[i]->len,
2018 dev_kfree_skb(np->tx_skbuff[i]);
2019 dev->stats.tx_dropped++;
2021 np->tx_skbuff[i] = NULL;
2025 static void drain_rx(struct net_device *dev)
2027 struct netdev_private *np = netdev_priv(dev);
2028 unsigned int buflen = np->rx_buf_sz;
2031 /* Free all the skbuffs in the Rx queue. */
2032 for (i = 0; i < RX_RING_SIZE; i++) {
2033 np->rx_ring[i].cmd_status = 0;
2034 np->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
2035 if (np->rx_skbuff[i]) {
2036 pci_unmap_single(np->pci_dev, np->rx_dma[i],
2037 buflen + NATSEMI_PADDING,
2038 PCI_DMA_FROMDEVICE);
2039 dev_kfree_skb(np->rx_skbuff[i]);
2041 np->rx_skbuff[i] = NULL;
2045 static void drain_ring(struct net_device *dev)
2051 static void free_ring(struct net_device *dev)
2053 struct netdev_private *np = netdev_priv(dev);
2054 pci_free_consistent(np->pci_dev,
2055 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2056 np->rx_ring, np->ring_dma);
2059 static void reinit_rx(struct net_device *dev)
2061 struct netdev_private *np = netdev_priv(dev);
2066 np->cur_rx = RX_RING_SIZE;
2067 np->rx_head_desc = &np->rx_ring[0];
2068 /* Initialize all Rx descriptors. */
2069 for (i = 0; i < RX_RING_SIZE; i++)
2070 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2075 static void reinit_ring(struct net_device *dev)
2077 struct netdev_private *np = netdev_priv(dev);
2082 np->dirty_tx = np->cur_tx = 0;
2083 for (i=0;i<TX_RING_SIZE;i++)
2084 np->tx_ring[i].cmd_status = 0;
2089 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
2091 struct netdev_private *np = netdev_priv(dev);
2092 void __iomem * ioaddr = ns_ioaddr(dev);
2094 unsigned long flags;
2096 /* Note: Ordering is important here, set the field with the
2097 "ownership" bit last, and only then increment cur_tx. */
2099 /* Calculate the next Tx descriptor entry. */
2100 entry = np->cur_tx % TX_RING_SIZE;
2102 np->tx_skbuff[entry] = skb;
2103 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2104 skb->data,skb->len, PCI_DMA_TODEVICE);
2105 if (pci_dma_mapping_error(np->pci_dev, np->tx_dma[entry])) {
2106 np->tx_skbuff[entry] = NULL;
2107 dev_kfree_skb_irq(skb);
2108 dev->stats.tx_dropped++;
2109 return NETDEV_TX_OK;
2112 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2114 spin_lock_irqsave(&np->lock, flags);
2116 if (!np->hands_off) {
2117 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2118 /* StrongARM: Explicitly cache flush np->tx_ring and
2119 * skb->data,skb->len. */
2122 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2123 netdev_tx_done(dev);
2124 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2125 netif_stop_queue(dev);
2127 /* Wake the potentially-idle transmit channel. */
2128 writel(TxOn, ioaddr + ChipCmd);
2130 dev_kfree_skb_irq(skb);
2131 dev->stats.tx_dropped++;
2133 spin_unlock_irqrestore(&np->lock, flags);
2135 if (netif_msg_tx_queued(np)) {
2136 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2137 dev->name, np->cur_tx, entry);
2139 return NETDEV_TX_OK;
2142 static void netdev_tx_done(struct net_device *dev)
2144 struct netdev_private *np = netdev_priv(dev);
2146 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2147 int entry = np->dirty_tx % TX_RING_SIZE;
2148 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2150 if (netif_msg_tx_done(np))
2152 "%s: tx frame #%d finished, status %#08x.\n",
2153 dev->name, np->dirty_tx,
2154 le32_to_cpu(np->tx_ring[entry].cmd_status));
2155 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2156 dev->stats.tx_packets++;
2157 dev->stats.tx_bytes += np->tx_skbuff[entry]->len;
2158 } else { /* Various Tx errors */
2160 le32_to_cpu(np->tx_ring[entry].cmd_status);
2161 if (tx_status & (DescTxAbort|DescTxExcColl))
2162 dev->stats.tx_aborted_errors++;
2163 if (tx_status & DescTxFIFO)
2164 dev->stats.tx_fifo_errors++;
2165 if (tx_status & DescTxCarrier)
2166 dev->stats.tx_carrier_errors++;
2167 if (tx_status & DescTxOOWCol)
2168 dev->stats.tx_window_errors++;
2169 dev->stats.tx_errors++;
2171 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2172 np->tx_skbuff[entry]->len,
2174 /* Free the original skb. */
2175 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2176 np->tx_skbuff[entry] = NULL;
2178 if (netif_queue_stopped(dev) &&
2179 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
2180 /* The ring is no longer full, wake queue. */
2181 netif_wake_queue(dev);
2185 /* The interrupt handler doesn't actually handle interrupts itself, it
2186 * schedules a NAPI poll if there is anything to do. */
2187 static irqreturn_t intr_handler(int irq, void *dev_instance)
2189 struct net_device *dev = dev_instance;
2190 struct netdev_private *np = netdev_priv(dev);
2191 void __iomem * ioaddr = ns_ioaddr(dev);
2193 /* Reading IntrStatus automatically acknowledges so don't do
2194 * that while interrupts are disabled, (for example, while a
2195 * poll is scheduled). */
2196 if (np->hands_off || !readl(ioaddr + IntrEnable))
2199 np->intr_status = readl(ioaddr + IntrStatus);
2201 if (!np->intr_status)
2204 if (netif_msg_intr(np))
2206 "%s: Interrupt, status %#08x, mask %#08x.\n",
2207 dev->name, np->intr_status,
2208 readl(ioaddr + IntrMask));
2210 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
2212 if (napi_schedule_prep(&np->napi)) {
2213 /* Disable interrupts and register for poll */
2214 natsemi_irq_disable(dev);
2215 __napi_schedule(&np->napi);
2218 "%s: Ignoring interrupt, status %#08x, mask %#08x.\n",
2219 dev->name, np->intr_status,
2220 readl(ioaddr + IntrMask));
2225 /* This is the NAPI poll routine. As well as the standard RX handling
2226 * it also handles all other interrupts that the chip might raise.
2228 static int natsemi_poll(struct napi_struct *napi, int budget)
2230 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
2231 struct net_device *dev = np->dev;
2232 void __iomem * ioaddr = ns_ioaddr(dev);
2236 if (netif_msg_intr(np))
2238 "%s: Poll, status %#08x, mask %#08x.\n",
2239 dev->name, np->intr_status,
2240 readl(ioaddr + IntrMask));
2242 /* netdev_rx() may read IntrStatus again if the RX state
2243 * machine falls over so do it first. */
2244 if (np->intr_status &
2245 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2246 IntrRxErr | IntrRxOverrun)) {
2247 netdev_rx(dev, &work_done, budget);
2250 if (np->intr_status &
2251 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
2252 spin_lock(&np->lock);
2253 netdev_tx_done(dev);
2254 spin_unlock(&np->lock);
2257 /* Abnormal error summary/uncommon events handlers. */
2258 if (np->intr_status & IntrAbnormalSummary)
2259 netdev_error(dev, np->intr_status);
2261 if (work_done >= budget)
2264 np->intr_status = readl(ioaddr + IntrStatus);
2265 } while (np->intr_status);
2267 napi_complete_done(napi, work_done);
2269 /* Reenable interrupts providing nothing is trying to shut
2271 spin_lock(&np->lock);
2273 natsemi_irq_enable(dev);
2274 spin_unlock(&np->lock);
2279 /* This routine is logically part of the interrupt handler, but separated
2280 for clarity and better register allocation. */
2281 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
2283 struct netdev_private *np = netdev_priv(dev);
2284 int entry = np->cur_rx % RX_RING_SIZE;
2285 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2286 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2287 unsigned int buflen = np->rx_buf_sz;
2288 void __iomem * ioaddr = ns_ioaddr(dev);
2290 /* If the driver owns the next entry it's a new packet. Send it up. */
2291 while (desc_status < 0) { /* e.g. & DescOwn */
2293 if (netif_msg_rx_status(np))
2295 " netdev_rx() entry %d status was %#08x.\n",
2296 entry, desc_status);
2300 if (*work_done >= work_to_do)
2305 pkt_len = (desc_status & DescSizeMask) - 4;
2306 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2307 if (desc_status & DescMore) {
2308 unsigned long flags;
2310 if (netif_msg_rx_err(np))
2312 "%s: Oversized(?) Ethernet "
2313 "frame spanned multiple "
2314 "buffers, entry %#08x "
2315 "status %#08x.\n", dev->name,
2316 np->cur_rx, desc_status);
2317 dev->stats.rx_length_errors++;
2319 /* The RX state machine has probably
2320 * locked up beneath us. Follow the
2321 * reset procedure documented in
2324 spin_lock_irqsave(&np->lock, flags);
2327 writel(np->ring_dma, ioaddr + RxRingPtr);
2329 spin_unlock_irqrestore(&np->lock, flags);
2331 /* We'll enable RX on exit from this
2336 /* There was an error. */
2337 dev->stats.rx_errors++;
2338 if (desc_status & (DescRxAbort|DescRxOver))
2339 dev->stats.rx_over_errors++;
2340 if (desc_status & (DescRxLong|DescRxRunt))
2341 dev->stats.rx_length_errors++;
2342 if (desc_status & (DescRxInvalid|DescRxAlign))
2343 dev->stats.rx_frame_errors++;
2344 if (desc_status & DescRxCRC)
2345 dev->stats.rx_crc_errors++;
2347 } else if (pkt_len > np->rx_buf_sz) {
2348 /* if this is the tail of a double buffer
2349 * packet, we've already counted the error
2350 * on the first part. Ignore the second half.
2353 struct sk_buff *skb;
2354 /* Omit CRC size. */
2355 /* Check if the packet is long enough to accept
2356 * without copying to a minimally-sized skbuff. */
2357 if (pkt_len < rx_copybreak &&
2358 (skb = netdev_alloc_skb(dev, pkt_len + RX_OFFSET)) != NULL) {
2359 /* 16 byte align the IP header */
2360 skb_reserve(skb, RX_OFFSET);
2361 pci_dma_sync_single_for_cpu(np->pci_dev,
2364 PCI_DMA_FROMDEVICE);
2365 skb_copy_to_linear_data(skb,
2366 np->rx_skbuff[entry]->data, pkt_len);
2367 skb_put(skb, pkt_len);
2368 pci_dma_sync_single_for_device(np->pci_dev,
2371 PCI_DMA_FROMDEVICE);
2373 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2374 buflen + NATSEMI_PADDING,
2375 PCI_DMA_FROMDEVICE);
2376 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2377 np->rx_skbuff[entry] = NULL;
2379 skb->protocol = eth_type_trans(skb, dev);
2380 netif_receive_skb(skb);
2381 dev->stats.rx_packets++;
2382 dev->stats.rx_bytes += pkt_len;
2384 entry = (++np->cur_rx) % RX_RING_SIZE;
2385 np->rx_head_desc = &np->rx_ring[entry];
2386 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2390 /* Restart Rx engine if stopped. */
2392 mod_timer(&np->timer, jiffies + 1);
2394 writel(RxOn, ioaddr + ChipCmd);
2397 static void netdev_error(struct net_device *dev, int intr_status)
2399 struct netdev_private *np = netdev_priv(dev);
2400 void __iomem * ioaddr = ns_ioaddr(dev);
2402 spin_lock(&np->lock);
2403 if (intr_status & LinkChange) {
2404 u16 lpa = mdio_read(dev, MII_LPA);
2405 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE &&
2406 netif_msg_link(np)) {
2408 "%s: Autonegotiation advertising"
2409 " %#04x partner %#04x.\n", dev->name,
2410 np->advertising, lpa);
2413 /* read MII int status to clear the flag */
2414 readw(ioaddr + MIntrStatus);
2417 if (intr_status & StatsMax) {
2420 if (intr_status & IntrTxUnderrun) {
2421 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2422 np->tx_config += TX_DRTH_VAL_INC;
2423 if (netif_msg_tx_err(np))
2425 "%s: increased tx threshold, txcfg %#08x.\n",
2426 dev->name, np->tx_config);
2428 if (netif_msg_tx_err(np))
2430 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2431 dev->name, np->tx_config);
2433 writel(np->tx_config, ioaddr + TxConfig);
2435 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2436 int wol_status = readl(ioaddr + WOLCmd);
2437 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2438 dev->name, wol_status);
2440 if (intr_status & RxStatusFIFOOver) {
2441 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2442 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2445 dev->stats.rx_fifo_errors++;
2446 dev->stats.rx_errors++;
2448 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2449 if (intr_status & IntrPCIErr) {
2450 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2451 intr_status & IntrPCIErr);
2452 dev->stats.tx_fifo_errors++;
2453 dev->stats.tx_errors++;
2454 dev->stats.rx_fifo_errors++;
2455 dev->stats.rx_errors++;
2457 spin_unlock(&np->lock);
2460 static void __get_stats(struct net_device *dev)
2462 void __iomem * ioaddr = ns_ioaddr(dev);
2464 /* The chip only need report frame silently dropped. */
2465 dev->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2466 dev->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2469 static struct net_device_stats *get_stats(struct net_device *dev)
2471 struct netdev_private *np = netdev_priv(dev);
2473 /* The chip only need report frame silently dropped. */
2474 spin_lock_irq(&np->lock);
2475 if (netif_running(dev) && !np->hands_off)
2477 spin_unlock_irq(&np->lock);
2482 #ifdef CONFIG_NET_POLL_CONTROLLER
2483 static void natsemi_poll_controller(struct net_device *dev)
2485 struct netdev_private *np = netdev_priv(dev);
2486 const int irq = np->pci_dev->irq;
2489 intr_handler(irq, dev);
2494 #define HASH_TABLE 0x200
2495 static void __set_rx_mode(struct net_device *dev)
2497 void __iomem * ioaddr = ns_ioaddr(dev);
2498 struct netdev_private *np = netdev_priv(dev);
2499 u8 mc_filter[64]; /* Multicast hash filter */
2502 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2503 rx_mode = RxFilterEnable | AcceptBroadcast
2504 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
2505 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2506 (dev->flags & IFF_ALLMULTI)) {
2507 rx_mode = RxFilterEnable | AcceptBroadcast
2508 | AcceptAllMulticast | AcceptMyPhys;
2510 struct netdev_hw_addr *ha;
2513 memset(mc_filter, 0, sizeof(mc_filter));
2514 netdev_for_each_mc_addr(ha, dev) {
2515 int b = (ether_crc(ETH_ALEN, ha->addr) >> 23) & 0x1ff;
2516 mc_filter[b/8] |= (1 << (b & 0x07));
2518 rx_mode = RxFilterEnable | AcceptBroadcast
2519 | AcceptMulticast | AcceptMyPhys;
2520 for (i = 0; i < 64; i += 2) {
2521 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2522 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2523 ioaddr + RxFilterData);
2526 writel(rx_mode, ioaddr + RxFilterAddr);
2527 np->cur_rx_mode = rx_mode;
2530 static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2534 /* synchronized against open : rtnl_lock() held by caller */
2535 if (netif_running(dev)) {
2536 struct netdev_private *np = netdev_priv(dev);
2537 void __iomem * ioaddr = ns_ioaddr(dev);
2538 const int irq = np->pci_dev->irq;
2541 spin_lock(&np->lock);
2543 natsemi_stop_rxtx(dev);
2544 /* drain rx queue */
2546 /* change buffers */
2549 writel(np->ring_dma, ioaddr + RxRingPtr);
2550 /* restart engines */
2551 writel(RxOn | TxOn, ioaddr + ChipCmd);
2552 spin_unlock(&np->lock);
2558 static void set_rx_mode(struct net_device *dev)
2560 struct netdev_private *np = netdev_priv(dev);
2561 spin_lock_irq(&np->lock);
2564 spin_unlock_irq(&np->lock);
2567 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2569 struct netdev_private *np = netdev_priv(dev);
2570 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2571 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2572 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
2575 static int get_regs_len(struct net_device *dev)
2577 return NATSEMI_REGS_SIZE;
2580 static int get_eeprom_len(struct net_device *dev)
2582 struct netdev_private *np = netdev_priv(dev);
2583 return np->eeprom_size;
2586 static int get_link_ksettings(struct net_device *dev,
2587 struct ethtool_link_ksettings *ecmd)
2589 struct netdev_private *np = netdev_priv(dev);
2590 spin_lock_irq(&np->lock);
2591 netdev_get_ecmd(dev, ecmd);
2592 spin_unlock_irq(&np->lock);
2596 static int set_link_ksettings(struct net_device *dev,
2597 const struct ethtool_link_ksettings *ecmd)
2599 struct netdev_private *np = netdev_priv(dev);
2601 spin_lock_irq(&np->lock);
2602 res = netdev_set_ecmd(dev, ecmd);
2603 spin_unlock_irq(&np->lock);
2607 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2609 struct netdev_private *np = netdev_priv(dev);
2610 spin_lock_irq(&np->lock);
2611 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2612 netdev_get_sopass(dev, wol->sopass);
2613 spin_unlock_irq(&np->lock);
2616 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2618 struct netdev_private *np = netdev_priv(dev);
2620 spin_lock_irq(&np->lock);
2621 netdev_set_wol(dev, wol->wolopts);
2622 res = netdev_set_sopass(dev, wol->sopass);
2623 spin_unlock_irq(&np->lock);
2627 static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2629 struct netdev_private *np = netdev_priv(dev);
2630 regs->version = NATSEMI_REGS_VER;
2631 spin_lock_irq(&np->lock);
2632 netdev_get_regs(dev, buf);
2633 spin_unlock_irq(&np->lock);
2636 static u32 get_msglevel(struct net_device *dev)
2638 struct netdev_private *np = netdev_priv(dev);
2639 return np->msg_enable;
2642 static void set_msglevel(struct net_device *dev, u32 val)
2644 struct netdev_private *np = netdev_priv(dev);
2645 np->msg_enable = val;
2648 static int nway_reset(struct net_device *dev)
2652 /* if autoneg is off, it's an error */
2653 tmp = mdio_read(dev, MII_BMCR);
2654 if (tmp & BMCR_ANENABLE) {
2655 tmp |= (BMCR_ANRESTART);
2656 mdio_write(dev, MII_BMCR, tmp);
2662 static u32 get_link(struct net_device *dev)
2664 /* LSTATUS is latched low until a read - so read twice */
2665 mdio_read(dev, MII_BMSR);
2666 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2669 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2671 struct netdev_private *np = netdev_priv(dev);
2675 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL);
2679 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2680 spin_lock_irq(&np->lock);
2681 res = netdev_get_eeprom(dev, eebuf);
2682 spin_unlock_irq(&np->lock);
2684 memcpy(data, eebuf+eeprom->offset, eeprom->len);
2689 static const struct ethtool_ops ethtool_ops = {
2690 .get_drvinfo = get_drvinfo,
2691 .get_regs_len = get_regs_len,
2692 .get_eeprom_len = get_eeprom_len,
2695 .get_regs = get_regs,
2696 .get_msglevel = get_msglevel,
2697 .set_msglevel = set_msglevel,
2698 .nway_reset = nway_reset,
2699 .get_link = get_link,
2700 .get_eeprom = get_eeprom,
2701 .get_link_ksettings = get_link_ksettings,
2702 .set_link_ksettings = set_link_ksettings,
2705 static int netdev_set_wol(struct net_device *dev, u32 newval)
2707 struct netdev_private *np = netdev_priv(dev);
2708 void __iomem * ioaddr = ns_ioaddr(dev);
2709 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2711 /* translate to bitmasks this chip understands */
2712 if (newval & WAKE_PHY)
2714 if (newval & WAKE_UCAST)
2715 data |= WakeUnicast;
2716 if (newval & WAKE_MCAST)
2717 data |= WakeMulticast;
2718 if (newval & WAKE_BCAST)
2719 data |= WakeBroadcast;
2720 if (newval & WAKE_ARP)
2722 if (newval & WAKE_MAGIC)
2724 if (np->srr >= SRR_DP83815_D) {
2725 if (newval & WAKE_MAGICSECURE) {
2726 data |= WakeMagicSecure;
2730 writel(data, ioaddr + WOLCmd);
2735 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2737 struct netdev_private *np = netdev_priv(dev);
2738 void __iomem * ioaddr = ns_ioaddr(dev);
2739 u32 regval = readl(ioaddr + WOLCmd);
2741 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2742 | WAKE_ARP | WAKE_MAGIC);
2744 if (np->srr >= SRR_DP83815_D) {
2745 /* SOPASS works on revD and higher */
2746 *supported |= WAKE_MAGICSECURE;
2750 /* translate from chip bitmasks */
2751 if (regval & WakePhy)
2753 if (regval & WakeUnicast)
2755 if (regval & WakeMulticast)
2757 if (regval & WakeBroadcast)
2759 if (regval & WakeArp)
2761 if (regval & WakeMagic)
2763 if (regval & WakeMagicSecure) {
2764 /* this can be on in revC, but it's broken */
2765 *cur |= WAKE_MAGICSECURE;
2771 static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2773 struct netdev_private *np = netdev_priv(dev);
2774 void __iomem * ioaddr = ns_ioaddr(dev);
2775 u16 *sval = (u16 *)newval;
2778 if (np->srr < SRR_DP83815_D) {
2782 /* enable writing to these registers by disabling the RX filter */
2783 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2784 addr &= ~RxFilterEnable;
2785 writel(addr, ioaddr + RxFilterAddr);
2787 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2788 writel(addr | 0xa, ioaddr + RxFilterAddr);
2789 writew(sval[0], ioaddr + RxFilterData);
2791 writel(addr | 0xc, ioaddr + RxFilterAddr);
2792 writew(sval[1], ioaddr + RxFilterData);
2794 writel(addr | 0xe, ioaddr + RxFilterAddr);
2795 writew(sval[2], ioaddr + RxFilterData);
2797 /* re-enable the RX filter */
2798 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2803 static int netdev_get_sopass(struct net_device *dev, u8 *data)
2805 struct netdev_private *np = netdev_priv(dev);
2806 void __iomem * ioaddr = ns_ioaddr(dev);
2807 u16 *sval = (u16 *)data;
2810 if (np->srr < SRR_DP83815_D) {
2811 sval[0] = sval[1] = sval[2] = 0;
2815 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2816 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2818 writel(addr | 0xa, ioaddr + RxFilterAddr);
2819 sval[0] = readw(ioaddr + RxFilterData);
2821 writel(addr | 0xc, ioaddr + RxFilterAddr);
2822 sval[1] = readw(ioaddr + RxFilterData);
2824 writel(addr | 0xe, ioaddr + RxFilterAddr);
2825 sval[2] = readw(ioaddr + RxFilterData);
2827 writel(addr, ioaddr + RxFilterAddr);
2832 static int netdev_get_ecmd(struct net_device *dev,
2833 struct ethtool_link_ksettings *ecmd)
2835 struct netdev_private *np = netdev_priv(dev);
2836 u32 supported, advertising;
2839 ecmd->base.port = dev->if_port;
2840 ecmd->base.speed = np->speed;
2841 ecmd->base.duplex = np->duplex;
2842 ecmd->base.autoneg = np->autoneg;
2845 if (np->advertising & ADVERTISE_10HALF)
2846 advertising |= ADVERTISED_10baseT_Half;
2847 if (np->advertising & ADVERTISE_10FULL)
2848 advertising |= ADVERTISED_10baseT_Full;
2849 if (np->advertising & ADVERTISE_100HALF)
2850 advertising |= ADVERTISED_100baseT_Half;
2851 if (np->advertising & ADVERTISE_100FULL)
2852 advertising |= ADVERTISED_100baseT_Full;
2853 supported = (SUPPORTED_Autoneg |
2854 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2855 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2856 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2857 ecmd->base.phy_address = np->phy_addr_external;
2859 * We intentionally report the phy address of the external
2860 * phy, even if the internal phy is used. This is necessary
2861 * to work around a deficiency of the ethtool interface:
2862 * It's only possible to query the settings of the active
2864 * # ethtool -s ethX port mii
2865 * actually sends an ioctl to switch to port mii with the
2866 * settings that are used for the current active port.
2867 * If we would report a different phy address in this
2869 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2870 * would unintentionally change the phy address.
2872 * Fortunately the phy address doesn't matter with the
2876 /* set information based on active port type */
2877 switch (ecmd->base.port) {
2880 advertising |= ADVERTISED_TP;
2883 advertising |= ADVERTISED_MII;
2886 advertising |= ADVERTISED_FIBRE;
2890 /* if autonegotiation is on, try to return the active speed/duplex */
2891 if (ecmd->base.autoneg == AUTONEG_ENABLE) {
2892 advertising |= ADVERTISED_Autoneg;
2893 tmp = mii_nway_result(
2894 np->advertising & mdio_read(dev, MII_LPA));
2895 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2896 ecmd->base.speed = SPEED_100;
2898 ecmd->base.speed = SPEED_10;
2899 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2900 ecmd->base.duplex = DUPLEX_FULL;
2902 ecmd->base.duplex = DUPLEX_HALF;
2905 /* ignore maxtxpkt, maxrxpkt for now */
2907 ethtool_convert_legacy_u32_to_link_mode(ecmd->link_modes.supported,
2909 ethtool_convert_legacy_u32_to_link_mode(ecmd->link_modes.advertising,
2915 static int netdev_set_ecmd(struct net_device *dev,
2916 const struct ethtool_link_ksettings *ecmd)
2918 struct netdev_private *np = netdev_priv(dev);
2921 ethtool_convert_link_mode_to_legacy_u32(&advertising,
2922 ecmd->link_modes.advertising);
2924 if (ecmd->base.port != PORT_TP &&
2925 ecmd->base.port != PORT_MII &&
2926 ecmd->base.port != PORT_FIBRE)
2928 if (ecmd->base.autoneg == AUTONEG_ENABLE) {
2929 if ((advertising & (ADVERTISED_10baseT_Half |
2930 ADVERTISED_10baseT_Full |
2931 ADVERTISED_100baseT_Half |
2932 ADVERTISED_100baseT_Full)) == 0) {
2935 } else if (ecmd->base.autoneg == AUTONEG_DISABLE) {
2936 u32 speed = ecmd->base.speed;
2937 if (speed != SPEED_10 && speed != SPEED_100)
2939 if (ecmd->base.duplex != DUPLEX_HALF &&
2940 ecmd->base.duplex != DUPLEX_FULL)
2947 * If we're ignoring the PHY then autoneg and the internal
2948 * transceiver are really not going to work so don't let the
2951 if (np->ignore_phy && (ecmd->base.autoneg == AUTONEG_ENABLE ||
2952 ecmd->base.port == PORT_TP))
2956 * maxtxpkt, maxrxpkt: ignored for now.
2959 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2960 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2961 * selects based on ecmd->port.
2963 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2964 * phys that are connected to the mii bus. It's used to apply fibre
2968 /* WHEW! now lets bang some bits */
2970 /* save the parms */
2971 dev->if_port = ecmd->base.port;
2972 np->autoneg = ecmd->base.autoneg;
2973 np->phy_addr_external = ecmd->base.phy_address & PhyAddrMask;
2974 if (np->autoneg == AUTONEG_ENABLE) {
2975 /* advertise only what has been requested */
2976 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2977 if (advertising & ADVERTISED_10baseT_Half)
2978 np->advertising |= ADVERTISE_10HALF;
2979 if (advertising & ADVERTISED_10baseT_Full)
2980 np->advertising |= ADVERTISE_10FULL;
2981 if (advertising & ADVERTISED_100baseT_Half)
2982 np->advertising |= ADVERTISE_100HALF;
2983 if (advertising & ADVERTISED_100baseT_Full)
2984 np->advertising |= ADVERTISE_100FULL;
2986 np->speed = ecmd->base.speed;
2987 np->duplex = ecmd->base.duplex;
2988 /* user overriding the initial full duplex parm? */
2989 if (np->duplex == DUPLEX_HALF)
2990 np->full_duplex = 0;
2993 /* get the right phy enabled */
2994 if (ecmd->base.port == PORT_TP)
2995 switch_port_internal(dev);
2997 switch_port_external(dev);
2999 /* set parms and see how this affected our link status */
3000 init_phy_fixup(dev);
3005 static int netdev_get_regs(struct net_device *dev, u8 *buf)
3010 u32 *rbuf = (u32 *)buf;
3011 void __iomem * ioaddr = ns_ioaddr(dev);
3013 /* read non-mii page 0 of registers */
3014 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
3015 rbuf[i] = readl(ioaddr + i*4);
3018 /* read current mii registers */
3019 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
3020 rbuf[i] = mdio_read(dev, i & 0x1f);
3022 /* read only the 'magic' registers from page 1 */
3023 writew(1, ioaddr + PGSEL);
3024 rbuf[i++] = readw(ioaddr + PMDCSR);
3025 rbuf[i++] = readw(ioaddr + TSTDAT);
3026 rbuf[i++] = readw(ioaddr + DSPCFG);
3027 rbuf[i++] = readw(ioaddr + SDCFG);
3028 writew(0, ioaddr + PGSEL);
3030 /* read RFCR indexed registers */
3031 rfcr = readl(ioaddr + RxFilterAddr);
3032 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
3033 writel(j*2, ioaddr + RxFilterAddr);
3034 rbuf[i++] = readw(ioaddr + RxFilterData);
3036 writel(rfcr, ioaddr + RxFilterAddr);
3038 /* the interrupt status is clear-on-read - see if we missed any */
3039 if (rbuf[4] & rbuf[5]) {
3041 "%s: shoot, we dropped an interrupt (%#08x)\n",
3042 dev->name, rbuf[4] & rbuf[5]);
3048 #define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
3049 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
3050 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
3051 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
3052 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
3053 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
3054 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
3055 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
3057 static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
3060 u16 *ebuf = (u16 *)buf;
3061 void __iomem * ioaddr = ns_ioaddr(dev);
3062 struct netdev_private *np = netdev_priv(dev);
3064 /* eeprom_read reads 16 bits, and indexes by 16 bits */
3065 for (i = 0; i < np->eeprom_size/2; i++) {
3066 ebuf[i] = eeprom_read(ioaddr, i);
3067 /* The EEPROM itself stores data bit-swapped, but eeprom_read
3068 * reads it back "sanely". So we swap it back here in order to
3069 * present it to userland as it is stored. */
3070 ebuf[i] = SWAP_BITS(ebuf[i]);
3075 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3077 struct mii_ioctl_data *data = if_mii(rq);
3078 struct netdev_private *np = netdev_priv(dev);
3081 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
3082 data->phy_id = np->phy_addr_external;
3085 case SIOCGMIIREG: /* Read MII PHY register. */
3086 /* The phy_id is not enough to uniquely identify
3087 * the intended target. Therefore the command is sent to
3088 * the given mii on the current port.
3090 if (dev->if_port == PORT_TP) {
3091 if ((data->phy_id & 0x1f) == np->phy_addr_external)
3092 data->val_out = mdio_read(dev,
3093 data->reg_num & 0x1f);
3097 move_int_phy(dev, data->phy_id & 0x1f);
3098 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
3099 data->reg_num & 0x1f);
3103 case SIOCSMIIREG: /* Write MII PHY register. */
3104 if (dev->if_port == PORT_TP) {
3105 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3106 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3107 np->advertising = data->val_in;
3108 mdio_write(dev, data->reg_num & 0x1f,
3112 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3113 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3114 np->advertising = data->val_in;
3116 move_int_phy(dev, data->phy_id & 0x1f);
3117 miiport_write(dev, data->phy_id & 0x1f,
3118 data->reg_num & 0x1f,
3127 static void enable_wol_mode(struct net_device *dev, int enable_intr)
3129 void __iomem * ioaddr = ns_ioaddr(dev);
3130 struct netdev_private *np = netdev_priv(dev);
3132 if (netif_msg_wol(np))
3133 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3136 /* For WOL we must restart the rx process in silent mode.
3137 * Write NULL to the RxRingPtr. Only possible if
3138 * rx process is stopped
3140 writel(0, ioaddr + RxRingPtr);
3142 /* read WoL status to clear */
3143 readl(ioaddr + WOLCmd);
3145 /* PME on, clear status */
3146 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3148 /* and restart the rx process */
3149 writel(RxOn, ioaddr + ChipCmd);
3152 /* enable the WOL interrupt.
3153 * Could be used to send a netlink message.
3155 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
3156 natsemi_irq_enable(dev);
3160 static int netdev_close(struct net_device *dev)
3162 void __iomem * ioaddr = ns_ioaddr(dev);
3163 struct netdev_private *np = netdev_priv(dev);
3164 const int irq = np->pci_dev->irq;
3166 if (netif_msg_ifdown(np))
3168 "%s: Shutting down ethercard, status was %#04x.\n",
3169 dev->name, (int)readl(ioaddr + ChipCmd));
3170 if (netif_msg_pktdata(np))
3172 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3173 dev->name, np->cur_tx, np->dirty_tx,
3174 np->cur_rx, np->dirty_rx);
3176 napi_disable(&np->napi);
3179 * FIXME: what if someone tries to close a device
3180 * that is suspended?
3181 * Should we reenable the nic to switch to
3182 * the final WOL settings?
3185 del_timer_sync(&np->timer);
3187 spin_lock_irq(&np->lock);
3188 natsemi_irq_disable(dev);
3190 spin_unlock_irq(&np->lock);
3195 /* Interrupt disabled, interrupt handler released,
3196 * queue stopped, timer deleted, rtnl_lock held
3197 * All async codepaths that access the driver are disabled.
3199 spin_lock_irq(&np->lock);
3201 readl(ioaddr + IntrMask);
3202 readw(ioaddr + MIntrStatus);
3205 writel(StatsFreeze, ioaddr + StatsCtrl);
3207 /* Stop the chip's Tx and Rx processes. */
3208 natsemi_stop_rxtx(dev);
3211 spin_unlock_irq(&np->lock);
3213 /* clear the carrier last - an interrupt could reenable it otherwise */
3214 netif_carrier_off(dev);
3215 netif_stop_queue(dev);
3222 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3224 /* restart the NIC in WOL mode.
3225 * The nic must be stopped for this.
3227 enable_wol_mode(dev, 0);
3229 /* Restore PME enable bit unmolested */
3230 writel(np->SavedClkRun, ioaddr + ClkRun);
3237 static void natsemi_remove1(struct pci_dev *pdev)
3239 struct net_device *dev = pci_get_drvdata(pdev);
3240 void __iomem * ioaddr = ns_ioaddr(dev);
3242 NATSEMI_REMOVE_FILE(pdev, dspcfg_workaround);
3243 unregister_netdev (dev);
3251 * The ns83815 chip doesn't have explicit RxStop bits.
3252 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3253 * of the nic, thus this function must be very careful:
3255 * suspend/resume synchronization:
3257 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
3258 * start_tx, ns_tx_timeout
3260 * No function accesses the hardware without checking np->hands_off.
3261 * the check occurs under spin_lock_irq(&np->lock);
3263 * * netdev_ioctl: noncritical access.
3264 * * netdev_open: cannot happen due to the device_detach
3265 * * netdev_close: doesn't hurt.
3266 * * netdev_timer: timer stopped by natsemi_suspend.
3267 * * intr_handler: doesn't acquire the spinlock. suspend calls
3268 * disable_irq() to enforce synchronization.
3269 * * natsemi_poll: checks before reenabling interrupts. suspend
3270 * sets hands_off, disables interrupts and then waits with
3273 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3276 static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3278 struct net_device *dev = pci_get_drvdata (pdev);
3279 struct netdev_private *np = netdev_priv(dev);
3280 void __iomem * ioaddr = ns_ioaddr(dev);
3283 if (netif_running (dev)) {
3284 const int irq = np->pci_dev->irq;
3286 del_timer_sync(&np->timer);
3289 spin_lock_irq(&np->lock);
3291 natsemi_irq_disable(dev);
3293 natsemi_stop_rxtx(dev);
3294 netif_stop_queue(dev);
3296 spin_unlock_irq(&np->lock);
3299 napi_disable(&np->napi);
3301 /* Update the error counts. */
3304 /* pci_power_off(pdev, -1); */
3307 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3308 /* Restore PME enable bit */
3310 /* restart the NIC in WOL mode.
3311 * The nic must be stopped for this.
3312 * FIXME: use the WOL interrupt
3314 enable_wol_mode(dev, 0);
3316 /* Restore PME enable bit unmolested */
3317 writel(np->SavedClkRun, ioaddr + ClkRun);
3321 netif_device_detach(dev);
3327 static int natsemi_resume (struct pci_dev *pdev)
3329 struct net_device *dev = pci_get_drvdata (pdev);
3330 struct netdev_private *np = netdev_priv(dev);
3334 if (netif_device_present(dev))
3336 if (netif_running(dev)) {
3337 const int irq = np->pci_dev->irq;
3339 BUG_ON(!np->hands_off);
3340 ret = pci_enable_device(pdev);
3343 "pci_enable_device() failed: %d\n", ret);
3346 /* pci_power_on(pdev); */
3348 napi_enable(&np->napi);
3353 spin_lock_irq(&np->lock);
3355 init_registers(dev);
3356 netif_device_attach(dev);
3357 spin_unlock_irq(&np->lock);
3360 mod_timer(&np->timer, round_jiffies(jiffies + 1*HZ));
3362 netif_device_attach(dev);
3368 #endif /* CONFIG_PM */
3370 static struct pci_driver natsemi_driver = {
3372 .id_table = natsemi_pci_tbl,
3373 .probe = natsemi_probe1,
3374 .remove = natsemi_remove1,
3376 .suspend = natsemi_suspend,
3377 .resume = natsemi_resume,
3381 static int __init natsemi_init_mod (void)
3383 /* when a module, this is printed whether or not devices are found in probe */
3388 return pci_register_driver(&natsemi_driver);
3391 static void __exit natsemi_exit_mod (void)
3393 pci_unregister_driver (&natsemi_driver);
3396 module_init(natsemi_init_mod);
3397 module_exit(natsemi_exit_mod);