1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
9 static const u32 ocelot_ana_regmap[] = {
10 REG(ANA_ADVLEARN, 0x009000),
11 REG(ANA_VLANMASK, 0x009004),
12 REG(ANA_PORT_B_DOMAIN, 0x009008),
13 REG(ANA_ANAGEFIL, 0x00900c),
14 REG(ANA_ANEVENTS, 0x009010),
15 REG(ANA_STORMLIMIT_BURST, 0x009014),
16 REG(ANA_STORMLIMIT_CFG, 0x009018),
17 REG(ANA_ISOLATED_PORTS, 0x009028),
18 REG(ANA_COMMUNITY_PORTS, 0x00902c),
19 REG(ANA_AUTOAGE, 0x009030),
20 REG(ANA_MACTOPTIONS, 0x009034),
21 REG(ANA_LEARNDISC, 0x009038),
22 REG(ANA_AGENCTRL, 0x00903c),
23 REG(ANA_MIRRORPORTS, 0x009040),
24 REG(ANA_EMIRRORPORTS, 0x009044),
25 REG(ANA_FLOODING, 0x009048),
26 REG(ANA_FLOODING_IPMC, 0x00904c),
27 REG(ANA_SFLOW_CFG, 0x009050),
28 REG(ANA_PORT_MODE, 0x009080),
29 REG(ANA_PGID_PGID, 0x008c00),
30 REG(ANA_TABLES_ANMOVED, 0x008b30),
31 REG(ANA_TABLES_MACHDATA, 0x008b34),
32 REG(ANA_TABLES_MACLDATA, 0x008b38),
33 REG(ANA_TABLES_MACACCESS, 0x008b3c),
34 REG(ANA_TABLES_MACTINDX, 0x008b40),
35 REG(ANA_TABLES_VLANACCESS, 0x008b44),
36 REG(ANA_TABLES_VLANTIDX, 0x008b48),
37 REG(ANA_TABLES_ISDXACCESS, 0x008b4c),
38 REG(ANA_TABLES_ISDXTIDX, 0x008b50),
39 REG(ANA_TABLES_ENTRYLIM, 0x008b00),
40 REG(ANA_TABLES_PTP_ID_HIGH, 0x008b54),
41 REG(ANA_TABLES_PTP_ID_LOW, 0x008b58),
42 REG(ANA_MSTI_STATE, 0x008e00),
43 REG(ANA_PORT_VLAN_CFG, 0x007000),
44 REG(ANA_PORT_DROP_CFG, 0x007004),
45 REG(ANA_PORT_QOS_CFG, 0x007008),
46 REG(ANA_PORT_VCAP_CFG, 0x00700c),
47 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007010),
48 REG(ANA_PORT_VCAP_S2_CFG, 0x00701c),
49 REG(ANA_PORT_PCP_DEI_MAP, 0x007020),
50 REG(ANA_PORT_CPU_FWD_CFG, 0x007060),
51 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007064),
52 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007068),
53 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00706c),
54 REG(ANA_PORT_PORT_CFG, 0x007070),
55 REG(ANA_PORT_POL_CFG, 0x007074),
56 REG(ANA_PORT_PTP_CFG, 0x007078),
57 REG(ANA_PORT_PTP_DLY1_CFG, 0x00707c),
58 REG(ANA_OAM_UPM_LM_CNT, 0x007c00),
59 REG(ANA_PORT_PTP_DLY2_CFG, 0x007080),
60 REG(ANA_PFC_PFC_CFG, 0x008800),
61 REG(ANA_PFC_PFC_TIMER, 0x008804),
62 REG(ANA_IPT_OAM_MEP_CFG, 0x008000),
63 REG(ANA_IPT_IPT, 0x008004),
64 REG(ANA_PPT_PPT, 0x008ac0),
65 REG(ANA_FID_MAP_FID_MAP, 0x000000),
66 REG(ANA_AGGR_CFG, 0x0090b4),
67 REG(ANA_CPUQ_CFG, 0x0090b8),
68 REG(ANA_CPUQ_CFG2, 0x0090bc),
69 REG(ANA_CPUQ_8021_CFG, 0x0090c0),
70 REG(ANA_DSCP_CFG, 0x009100),
71 REG(ANA_DSCP_REWR_CFG, 0x009200),
72 REG(ANA_VCAP_RNG_TYPE_CFG, 0x009240),
73 REG(ANA_VCAP_RNG_VAL_CFG, 0x009260),
74 REG(ANA_VRAP_CFG, 0x009280),
75 REG(ANA_VRAP_HDR_DATA, 0x009284),
76 REG(ANA_VRAP_HDR_MASK, 0x009288),
77 REG(ANA_DISCARD_CFG, 0x00928c),
78 REG(ANA_FID_CFG, 0x009290),
79 REG(ANA_POL_PIR_CFG, 0x004000),
80 REG(ANA_POL_CIR_CFG, 0x004004),
81 REG(ANA_POL_MODE_CFG, 0x004008),
82 REG(ANA_POL_PIR_STATE, 0x00400c),
83 REG(ANA_POL_CIR_STATE, 0x004010),
84 REG(ANA_POL_STATE, 0x004014),
85 REG(ANA_POL_FLOWC, 0x008b80),
86 REG(ANA_POL_HYST, 0x008bec),
87 REG(ANA_POL_MISC_CFG, 0x008bf0),
90 static const u32 ocelot_qs_regmap[] = {
91 REG(QS_XTR_GRP_CFG, 0x000000),
92 REG(QS_XTR_RD, 0x000008),
93 REG(QS_XTR_FRM_PRUNING, 0x000010),
94 REG(QS_XTR_FLUSH, 0x000018),
95 REG(QS_XTR_DATA_PRESENT, 0x00001c),
96 REG(QS_XTR_CFG, 0x000020),
97 REG(QS_INJ_GRP_CFG, 0x000024),
98 REG(QS_INJ_WR, 0x00002c),
99 REG(QS_INJ_CTRL, 0x000034),
100 REG(QS_INJ_STATUS, 0x00003c),
101 REG(QS_INJ_ERR, 0x000040),
102 REG(QS_INH_DBG, 0x000048),
105 static const u32 ocelot_hsio_regmap[] = {
106 REG(HSIO_PLL5G_CFG0, 0x000000),
107 REG(HSIO_PLL5G_CFG1, 0x000004),
108 REG(HSIO_PLL5G_CFG2, 0x000008),
109 REG(HSIO_PLL5G_CFG3, 0x00000c),
110 REG(HSIO_PLL5G_CFG4, 0x000010),
111 REG(HSIO_PLL5G_CFG5, 0x000014),
112 REG(HSIO_PLL5G_CFG6, 0x000018),
113 REG(HSIO_PLL5G_STATUS0, 0x00001c),
114 REG(HSIO_PLL5G_STATUS1, 0x000020),
115 REG(HSIO_PLL5G_BIST_CFG0, 0x000024),
116 REG(HSIO_PLL5G_BIST_CFG1, 0x000028),
117 REG(HSIO_PLL5G_BIST_CFG2, 0x00002c),
118 REG(HSIO_PLL5G_BIST_STAT0, 0x000030),
119 REG(HSIO_PLL5G_BIST_STAT1, 0x000034),
120 REG(HSIO_RCOMP_CFG0, 0x000038),
121 REG(HSIO_RCOMP_STATUS, 0x00003c),
122 REG(HSIO_SYNC_ETH_CFG, 0x000040),
123 REG(HSIO_SYNC_ETH_PLL_CFG, 0x000048),
124 REG(HSIO_S1G_DES_CFG, 0x00004c),
125 REG(HSIO_S1G_IB_CFG, 0x000050),
126 REG(HSIO_S1G_OB_CFG, 0x000054),
127 REG(HSIO_S1G_SER_CFG, 0x000058),
128 REG(HSIO_S1G_COMMON_CFG, 0x00005c),
129 REG(HSIO_S1G_PLL_CFG, 0x000060),
130 REG(HSIO_S1G_PLL_STATUS, 0x000064),
131 REG(HSIO_S1G_DFT_CFG0, 0x000068),
132 REG(HSIO_S1G_DFT_CFG1, 0x00006c),
133 REG(HSIO_S1G_DFT_CFG2, 0x000070),
134 REG(HSIO_S1G_TP_CFG, 0x000074),
135 REG(HSIO_S1G_RC_PLL_BIST_CFG, 0x000078),
136 REG(HSIO_S1G_MISC_CFG, 0x00007c),
137 REG(HSIO_S1G_DFT_STATUS, 0x000080),
138 REG(HSIO_S1G_MISC_STATUS, 0x000084),
139 REG(HSIO_MCB_S1G_ADDR_CFG, 0x000088),
140 REG(HSIO_S6G_DIG_CFG, 0x00008c),
141 REG(HSIO_S6G_DFT_CFG0, 0x000090),
142 REG(HSIO_S6G_DFT_CFG1, 0x000094),
143 REG(HSIO_S6G_DFT_CFG2, 0x000098),
144 REG(HSIO_S6G_TP_CFG0, 0x00009c),
145 REG(HSIO_S6G_TP_CFG1, 0x0000a0),
146 REG(HSIO_S6G_RC_PLL_BIST_CFG, 0x0000a4),
147 REG(HSIO_S6G_MISC_CFG, 0x0000a8),
148 REG(HSIO_S6G_OB_ANEG_CFG, 0x0000ac),
149 REG(HSIO_S6G_DFT_STATUS, 0x0000b0),
150 REG(HSIO_S6G_ERR_CNT, 0x0000b4),
151 REG(HSIO_S6G_MISC_STATUS, 0x0000b8),
152 REG(HSIO_S6G_DES_CFG, 0x0000bc),
153 REG(HSIO_S6G_IB_CFG, 0x0000c0),
154 REG(HSIO_S6G_IB_CFG1, 0x0000c4),
155 REG(HSIO_S6G_IB_CFG2, 0x0000c8),
156 REG(HSIO_S6G_IB_CFG3, 0x0000cc),
157 REG(HSIO_S6G_IB_CFG4, 0x0000d0),
158 REG(HSIO_S6G_IB_CFG5, 0x0000d4),
159 REG(HSIO_S6G_OB_CFG, 0x0000d8),
160 REG(HSIO_S6G_OB_CFG1, 0x0000dc),
161 REG(HSIO_S6G_SER_CFG, 0x0000e0),
162 REG(HSIO_S6G_COMMON_CFG, 0x0000e4),
163 REG(HSIO_S6G_PLL_CFG, 0x0000e8),
164 REG(HSIO_S6G_ACJTAG_CFG, 0x0000ec),
165 REG(HSIO_S6G_GP_CFG, 0x0000f0),
166 REG(HSIO_S6G_IB_STATUS0, 0x0000f4),
167 REG(HSIO_S6G_IB_STATUS1, 0x0000f8),
168 REG(HSIO_S6G_ACJTAG_STATUS, 0x0000fc),
169 REG(HSIO_S6G_PLL_STATUS, 0x000100),
170 REG(HSIO_S6G_REVID, 0x000104),
171 REG(HSIO_MCB_S6G_ADDR_CFG, 0x000108),
172 REG(HSIO_HW_CFG, 0x00010c),
173 REG(HSIO_HW_QSGMII_CFG, 0x000110),
174 REG(HSIO_HW_QSGMII_STAT, 0x000114),
175 REG(HSIO_CLK_CFG, 0x000118),
176 REG(HSIO_TEMP_SENSOR_CTRL, 0x00011c),
177 REG(HSIO_TEMP_SENSOR_CFG, 0x000120),
178 REG(HSIO_TEMP_SENSOR_STAT, 0x000124),
181 static const u32 ocelot_qsys_regmap[] = {
182 REG(QSYS_PORT_MODE, 0x011200),
183 REG(QSYS_SWITCH_PORT_MODE, 0x011234),
184 REG(QSYS_STAT_CNT_CFG, 0x011264),
185 REG(QSYS_EEE_CFG, 0x011268),
186 REG(QSYS_EEE_THRES, 0x011294),
187 REG(QSYS_IGR_NO_SHARING, 0x011298),
188 REG(QSYS_EGR_NO_SHARING, 0x01129c),
189 REG(QSYS_SW_STATUS, 0x0112a0),
190 REG(QSYS_EXT_CPU_CFG, 0x0112d0),
191 REG(QSYS_PAD_CFG, 0x0112d4),
192 REG(QSYS_CPU_GROUP_MAP, 0x0112d8),
193 REG(QSYS_QMAP, 0x0112dc),
194 REG(QSYS_ISDX_SGRP, 0x011400),
195 REG(QSYS_TIMED_FRAME_ENTRY, 0x014000),
196 REG(QSYS_TFRM_MISC, 0x011310),
197 REG(QSYS_TFRM_PORT_DLY, 0x011314),
198 REG(QSYS_TFRM_TIMER_CFG_1, 0x011318),
199 REG(QSYS_TFRM_TIMER_CFG_2, 0x01131c),
200 REG(QSYS_TFRM_TIMER_CFG_3, 0x011320),
201 REG(QSYS_TFRM_TIMER_CFG_4, 0x011324),
202 REG(QSYS_TFRM_TIMER_CFG_5, 0x011328),
203 REG(QSYS_TFRM_TIMER_CFG_6, 0x01132c),
204 REG(QSYS_TFRM_TIMER_CFG_7, 0x011330),
205 REG(QSYS_TFRM_TIMER_CFG_8, 0x011334),
206 REG(QSYS_RED_PROFILE, 0x011338),
207 REG(QSYS_RES_QOS_MODE, 0x011378),
208 REG(QSYS_RES_CFG, 0x012000),
209 REG(QSYS_RES_STAT, 0x012004),
210 REG(QSYS_EGR_DROP_MODE, 0x01137c),
211 REG(QSYS_EQ_CTRL, 0x011380),
212 REG(QSYS_EVENTS_CORE, 0x011384),
213 REG(QSYS_CIR_CFG, 0x000000),
214 REG(QSYS_EIR_CFG, 0x000004),
215 REG(QSYS_SE_CFG, 0x000008),
216 REG(QSYS_SE_DWRR_CFG, 0x00000c),
217 REG(QSYS_SE_CONNECT, 0x00003c),
218 REG(QSYS_SE_DLB_SENSE, 0x000040),
219 REG(QSYS_CIR_STATE, 0x000044),
220 REG(QSYS_EIR_STATE, 0x000048),
221 REG(QSYS_SE_STATE, 0x00004c),
222 REG(QSYS_HSCH_MISC_CFG, 0x011388),
225 static const u32 ocelot_rew_regmap[] = {
226 REG(REW_PORT_VLAN_CFG, 0x000000),
227 REG(REW_TAG_CFG, 0x000004),
228 REG(REW_PORT_CFG, 0x000008),
229 REG(REW_DSCP_CFG, 0x00000c),
230 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010),
231 REG(REW_PTP_CFG, 0x000050),
232 REG(REW_PTP_DLY1_CFG, 0x000054),
233 REG(REW_DSCP_REMAP_DP1_CFG, 0x000690),
234 REG(REW_DSCP_REMAP_CFG, 0x000790),
235 REG(REW_STAT_CFG, 0x000890),
236 REG(REW_PPT, 0x000680),
239 static const u32 ocelot_sys_regmap[] = {
240 REG(SYS_COUNT_RX_OCTETS, 0x000000),
241 REG(SYS_COUNT_RX_UNICAST, 0x000004),
242 REG(SYS_COUNT_RX_MULTICAST, 0x000008),
243 REG(SYS_COUNT_RX_BROADCAST, 0x00000c),
244 REG(SYS_COUNT_RX_SHORTS, 0x000010),
245 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014),
246 REG(SYS_COUNT_RX_JABBERS, 0x000018),
247 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c),
248 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020),
249 REG(SYS_COUNT_RX_64, 0x000024),
250 REG(SYS_COUNT_RX_65_127, 0x000028),
251 REG(SYS_COUNT_RX_128_255, 0x00002c),
252 REG(SYS_COUNT_RX_256_1023, 0x000030),
253 REG(SYS_COUNT_RX_1024_1526, 0x000034),
254 REG(SYS_COUNT_RX_1527_MAX, 0x000038),
255 REG(SYS_COUNT_RX_PAUSE, 0x00003c),
256 REG(SYS_COUNT_RX_CONTROL, 0x000040),
257 REG(SYS_COUNT_RX_LONGS, 0x000044),
258 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x000048),
259 REG(SYS_COUNT_TX_OCTETS, 0x000100),
260 REG(SYS_COUNT_TX_UNICAST, 0x000104),
261 REG(SYS_COUNT_TX_MULTICAST, 0x000108),
262 REG(SYS_COUNT_TX_BROADCAST, 0x00010c),
263 REG(SYS_COUNT_TX_COLLISION, 0x000110),
264 REG(SYS_COUNT_TX_DROPS, 0x000114),
265 REG(SYS_COUNT_TX_PAUSE, 0x000118),
266 REG(SYS_COUNT_TX_64, 0x00011c),
267 REG(SYS_COUNT_TX_65_127, 0x000120),
268 REG(SYS_COUNT_TX_128_511, 0x000124),
269 REG(SYS_COUNT_TX_512_1023, 0x000128),
270 REG(SYS_COUNT_TX_1024_1526, 0x00012c),
271 REG(SYS_COUNT_TX_1527_MAX, 0x000130),
272 REG(SYS_COUNT_TX_AGING, 0x000170),
273 REG(SYS_RESET_CFG, 0x000508),
274 REG(SYS_CMID, 0x00050c),
275 REG(SYS_VLAN_ETYPE_CFG, 0x000510),
276 REG(SYS_PORT_MODE, 0x000514),
277 REG(SYS_FRONT_PORT_MODE, 0x000548),
278 REG(SYS_FRM_AGING, 0x000574),
279 REG(SYS_STAT_CFG, 0x000578),
280 REG(SYS_SW_STATUS, 0x00057c),
281 REG(SYS_MISC_CFG, 0x0005ac),
282 REG(SYS_REW_MAC_HIGH_CFG, 0x0005b0),
283 REG(SYS_REW_MAC_LOW_CFG, 0x0005dc),
284 REG(SYS_CM_ADDR, 0x000500),
285 REG(SYS_CM_DATA, 0x000504),
286 REG(SYS_PAUSE_CFG, 0x000608),
287 REG(SYS_PAUSE_TOT_CFG, 0x000638),
288 REG(SYS_ATOP, 0x00063c),
289 REG(SYS_ATOP_TOT_CFG, 0x00066c),
290 REG(SYS_MAC_FC_CFG, 0x000670),
291 REG(SYS_MMGT, 0x00069c),
292 REG(SYS_MMGT_FAST, 0x0006a0),
293 REG(SYS_EVENTS_DIF, 0x0006a4),
294 REG(SYS_EVENTS_CORE, 0x0006b4),
295 REG(SYS_CNT, 0x000000),
296 REG(SYS_PTP_STATUS, 0x0006b8),
297 REG(SYS_PTP_TXSTAMP, 0x0006bc),
298 REG(SYS_PTP_NXT, 0x0006c0),
299 REG(SYS_PTP_CFG, 0x0006c4),
302 static const u32 *ocelot_regmap[] = {
303 [ANA] = ocelot_ana_regmap,
304 [QS] = ocelot_qs_regmap,
305 [HSIO] = ocelot_hsio_regmap,
306 [QSYS] = ocelot_qsys_regmap,
307 [REW] = ocelot_rew_regmap,
308 [SYS] = ocelot_sys_regmap,
311 static const struct reg_field ocelot_regfields[] = {
312 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11),
313 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10),
314 [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27),
315 [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26),
316 [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25),
317 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24),
318 [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23),
319 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22),
320 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21),
321 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20),
322 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19),
323 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
324 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17),
325 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16),
326 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15),
327 [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14),
328 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13),
329 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12),
330 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
331 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
332 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9),
333 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8),
334 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7),
335 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
336 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
337 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4),
338 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3),
339 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2),
340 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1),
341 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0),
342 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18),
343 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11),
344 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9),
345 [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20),
346 [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19),
347 [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7),
348 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3),
349 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0),
350 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2),
351 [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1),
352 [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0),
355 static const struct ocelot_stat_layout ocelot_stats_layout[] = {
356 { .name = "rx_octets", .offset = 0x00, },
357 { .name = "rx_unicast", .offset = 0x01, },
358 { .name = "rx_multicast", .offset = 0x02, },
359 { .name = "rx_broadcast", .offset = 0x03, },
360 { .name = "rx_shorts", .offset = 0x04, },
361 { .name = "rx_fragments", .offset = 0x05, },
362 { .name = "rx_jabbers", .offset = 0x06, },
363 { .name = "rx_crc_align_errs", .offset = 0x07, },
364 { .name = "rx_sym_errs", .offset = 0x08, },
365 { .name = "rx_frames_below_65_octets", .offset = 0x09, },
366 { .name = "rx_frames_65_to_127_octets", .offset = 0x0A, },
367 { .name = "rx_frames_128_to_255_octets", .offset = 0x0B, },
368 { .name = "rx_frames_256_to_511_octets", .offset = 0x0C, },
369 { .name = "rx_frames_512_to_1023_octets", .offset = 0x0D, },
370 { .name = "rx_frames_1024_to_1526_octets", .offset = 0x0E, },
371 { .name = "rx_frames_over_1526_octets", .offset = 0x0F, },
372 { .name = "rx_pause", .offset = 0x10, },
373 { .name = "rx_control", .offset = 0x11, },
374 { .name = "rx_longs", .offset = 0x12, },
375 { .name = "rx_classified_drops", .offset = 0x13, },
376 { .name = "rx_red_prio_0", .offset = 0x14, },
377 { .name = "rx_red_prio_1", .offset = 0x15, },
378 { .name = "rx_red_prio_2", .offset = 0x16, },
379 { .name = "rx_red_prio_3", .offset = 0x17, },
380 { .name = "rx_red_prio_4", .offset = 0x18, },
381 { .name = "rx_red_prio_5", .offset = 0x19, },
382 { .name = "rx_red_prio_6", .offset = 0x1A, },
383 { .name = "rx_red_prio_7", .offset = 0x1B, },
384 { .name = "rx_yellow_prio_0", .offset = 0x1C, },
385 { .name = "rx_yellow_prio_1", .offset = 0x1D, },
386 { .name = "rx_yellow_prio_2", .offset = 0x1E, },
387 { .name = "rx_yellow_prio_3", .offset = 0x1F, },
388 { .name = "rx_yellow_prio_4", .offset = 0x20, },
389 { .name = "rx_yellow_prio_5", .offset = 0x21, },
390 { .name = "rx_yellow_prio_6", .offset = 0x22, },
391 { .name = "rx_yellow_prio_7", .offset = 0x23, },
392 { .name = "rx_green_prio_0", .offset = 0x24, },
393 { .name = "rx_green_prio_1", .offset = 0x25, },
394 { .name = "rx_green_prio_2", .offset = 0x26, },
395 { .name = "rx_green_prio_3", .offset = 0x27, },
396 { .name = "rx_green_prio_4", .offset = 0x28, },
397 { .name = "rx_green_prio_5", .offset = 0x29, },
398 { .name = "rx_green_prio_6", .offset = 0x2A, },
399 { .name = "rx_green_prio_7", .offset = 0x2B, },
400 { .name = "tx_octets", .offset = 0x40, },
401 { .name = "tx_unicast", .offset = 0x41, },
402 { .name = "tx_multicast", .offset = 0x42, },
403 { .name = "tx_broadcast", .offset = 0x43, },
404 { .name = "tx_collision", .offset = 0x44, },
405 { .name = "tx_drops", .offset = 0x45, },
406 { .name = "tx_pause", .offset = 0x46, },
407 { .name = "tx_frames_below_65_octets", .offset = 0x47, },
408 { .name = "tx_frames_65_to_127_octets", .offset = 0x48, },
409 { .name = "tx_frames_128_255_octets", .offset = 0x49, },
410 { .name = "tx_frames_256_511_octets", .offset = 0x4A, },
411 { .name = "tx_frames_512_1023_octets", .offset = 0x4B, },
412 { .name = "tx_frames_1024_1526_octets", .offset = 0x4C, },
413 { .name = "tx_frames_over_1526_octets", .offset = 0x4D, },
414 { .name = "tx_yellow_prio_0", .offset = 0x4E, },
415 { .name = "tx_yellow_prio_1", .offset = 0x4F, },
416 { .name = "tx_yellow_prio_2", .offset = 0x50, },
417 { .name = "tx_yellow_prio_3", .offset = 0x51, },
418 { .name = "tx_yellow_prio_4", .offset = 0x52, },
419 { .name = "tx_yellow_prio_5", .offset = 0x53, },
420 { .name = "tx_yellow_prio_6", .offset = 0x54, },
421 { .name = "tx_yellow_prio_7", .offset = 0x55, },
422 { .name = "tx_green_prio_0", .offset = 0x56, },
423 { .name = "tx_green_prio_1", .offset = 0x57, },
424 { .name = "tx_green_prio_2", .offset = 0x58, },
425 { .name = "tx_green_prio_3", .offset = 0x59, },
426 { .name = "tx_green_prio_4", .offset = 0x5A, },
427 { .name = "tx_green_prio_5", .offset = 0x5B, },
428 { .name = "tx_green_prio_6", .offset = 0x5C, },
429 { .name = "tx_green_prio_7", .offset = 0x5D, },
430 { .name = "tx_aged", .offset = 0x5E, },
431 { .name = "drop_local", .offset = 0x80, },
432 { .name = "drop_tail", .offset = 0x81, },
433 { .name = "drop_yellow_prio_0", .offset = 0x82, },
434 { .name = "drop_yellow_prio_1", .offset = 0x83, },
435 { .name = "drop_yellow_prio_2", .offset = 0x84, },
436 { .name = "drop_yellow_prio_3", .offset = 0x85, },
437 { .name = "drop_yellow_prio_4", .offset = 0x86, },
438 { .name = "drop_yellow_prio_5", .offset = 0x87, },
439 { .name = "drop_yellow_prio_6", .offset = 0x88, },
440 { .name = "drop_yellow_prio_7", .offset = 0x89, },
441 { .name = "drop_green_prio_0", .offset = 0x8A, },
442 { .name = "drop_green_prio_1", .offset = 0x8B, },
443 { .name = "drop_green_prio_2", .offset = 0x8C, },
444 { .name = "drop_green_prio_3", .offset = 0x8D, },
445 { .name = "drop_green_prio_4", .offset = 0x8E, },
446 { .name = "drop_green_prio_5", .offset = 0x8F, },
447 { .name = "drop_green_prio_6", .offset = 0x90, },
448 { .name = "drop_green_prio_7", .offset = 0x91, },
451 static void ocelot_pll5_init(struct ocelot *ocelot)
453 /* Configure PLL5. This will need a proper CCF driver
454 * The values are coming from the VTSS API for Ocelot
456 ocelot_write(ocelot, HSIO_PLL5G_CFG4_IB_CTRL(0x7600) |
457 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8), HSIO_PLL5G_CFG4);
458 ocelot_write(ocelot, HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) |
459 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) |
460 HSIO_PLL5G_CFG0_ENA_BIAS |
461 HSIO_PLL5G_CFG0_ENA_VCO_BUF |
462 HSIO_PLL5G_CFG0_ENA_CP1 |
463 HSIO_PLL5G_CFG0_SELCPI(2) |
464 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) |
465 HSIO_PLL5G_CFG0_SELBGV820(4) |
466 HSIO_PLL5G_CFG0_DIV4 |
467 HSIO_PLL5G_CFG0_ENA_CLKTREE |
468 HSIO_PLL5G_CFG0_ENA_LANE, HSIO_PLL5G_CFG0);
469 ocelot_write(ocelot, HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET |
470 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN |
471 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) |
472 HSIO_PLL5G_CFG2_ENA_AMPCTRL |
473 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N |
474 HSIO_PLL5G_CFG2_AMPC_SEL(0x10), HSIO_PLL5G_CFG2);
477 int ocelot_chip_init(struct ocelot *ocelot)
481 ocelot->map = ocelot_regmap;
482 ocelot->stats_layout = ocelot_stats_layout;
483 ocelot->num_stats = ARRAY_SIZE(ocelot_stats_layout);
484 ocelot->shared_queue_sz = 224 * 1024;
486 ret = ocelot_regfields_init(ocelot, ocelot_regfields);
490 ocelot_pll5_init(ocelot);
492 eth_random_addr(ocelot->base_mac);
493 ocelot->base_mac[5] &= 0xf0;
497 EXPORT_SYMBOL(ocelot_chip_init);