1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
8 #ifndef _MSCC_OCELOT_H_
9 #define _MSCC_OCELOT_H_
11 #include <linux/bitops.h>
12 #include <linux/etherdevice.h>
13 #include <linux/if_vlan.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
17 #include "ocelot_ana.h"
18 #include "ocelot_dev.h"
19 #include "ocelot_hsio.h"
20 #include "ocelot_qsys.h"
21 #include "ocelot_rew.h"
22 #include "ocelot_sys.h"
23 #include "ocelot_qs.h"
29 #define PGID_CPU (PGID_AGGR - 5)
30 #define PGID_UC (PGID_AGGR - 4)
31 #define PGID_MC (PGID_AGGR - 3)
32 #define PGID_MCIPV4 (PGID_AGGR - 2)
33 #define PGID_MCIPV6 (PGID_AGGR - 1)
35 #define OCELOT_BUFFER_CELL_SZ 60
37 #define OCELOT_STATS_CHECK_DELAY (2 * HZ)
49 #define IFH_INJ_BYPASS BIT(31)
50 #define IFH_INJ_POP_CNT_DISABLE (3 << 28)
52 #define IFH_TAG_TYPE_C 0
53 #define IFH_TAG_TYPE_S 1
55 #define OCELOT_SPEED_2500 0
56 #define OCELOT_SPEED_1000 1
57 #define OCELOT_SPEED_100 2
58 #define OCELOT_SPEED_10 3
60 #define TARGET_OFFSET 24
61 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
62 #define REG(reg, offset) [reg & REG_MASK] = offset
75 ANA_ADVLEARN = ANA << TARGET_OFFSET,
99 ANA_TABLES_STREAMDATA,
100 ANA_TABLES_MACACCESS,
102 ANA_TABLES_VLANACCESS,
104 ANA_TABLES_ISDXACCESS,
107 ANA_TABLES_PTP_ID_HIGH,
108 ANA_TABLES_PTP_ID_LOW,
109 ANA_TABLES_STREAMACCESS,
110 ANA_TABLES_STREAMTIDX,
111 ANA_TABLES_SEQ_HISTORY,
113 ANA_TABLES_SFID_MASK,
114 ANA_TABLES_SFIDACCESS,
124 ANA_SG_GCL_GS_CONFIG,
125 ANA_SG_GCL_TI_CONFIG,
133 ANA_PORT_VCAP_S1_KEY_CFG,
134 ANA_PORT_VCAP_S2_CFG,
135 ANA_PORT_PCP_DEI_MAP,
136 ANA_PORT_CPU_FWD_CFG,
137 ANA_PORT_CPU_FWD_BPDU_CFG,
138 ANA_PORT_CPU_FWD_GARP_CFG,
139 ANA_PORT_CPU_FWD_CCM_CFG,
143 ANA_PORT_PTP_DLY1_CFG,
144 ANA_PORT_PTP_DLY2_CFG,
158 ANA_VCAP_RNG_TYPE_CFG,
159 ANA_VCAP_RNG_VAL_CFG,
174 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
186 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
187 QSYS_SWITCH_PORT_MODE,
199 QSYS_TIMED_FRAME_ENTRY,
202 QSYS_TFRM_TIMER_CFG_1,
203 QSYS_TFRM_TIMER_CFG_2,
204 QSYS_TFRM_TIMER_CFG_3,
205 QSYS_TFRM_TIMER_CFG_4,
206 QSYS_TFRM_TIMER_CFG_5,
207 QSYS_TFRM_TIMER_CFG_6,
208 QSYS_TFRM_TIMER_CFG_7,
209 QSYS_TFRM_TIMER_CFG_8,
237 QSYS_TAS_PARAM_CFG_CTRL,
239 QSYS_PARAM_CFG_REG_1,
240 QSYS_PARAM_CFG_REG_2,
241 QSYS_PARAM_CFG_REG_3,
242 QSYS_PARAM_CFG_REG_4,
243 QSYS_PARAM_CFG_REG_5,
246 QSYS_PARAM_STATUS_REG_1,
247 QSYS_PARAM_STATUS_REG_2,
248 QSYS_PARAM_STATUS_REG_3,
249 QSYS_PARAM_STATUS_REG_4,
250 QSYS_PARAM_STATUS_REG_5,
251 QSYS_PARAM_STATUS_REG_6,
252 QSYS_PARAM_STATUS_REG_7,
253 QSYS_PARAM_STATUS_REG_8,
254 QSYS_PARAM_STATUS_REG_9,
255 QSYS_GCL_STATUS_REG_1,
256 QSYS_GCL_STATUS_REG_2,
257 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
261 REW_PCP_DEI_QOS_MAP_CFG,
265 REW_DSCP_REMAP_DP1_CFG,
270 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
271 SYS_COUNT_RX_UNICAST,
272 SYS_COUNT_RX_MULTICAST,
273 SYS_COUNT_RX_BROADCAST,
275 SYS_COUNT_RX_FRAGMENTS,
276 SYS_COUNT_RX_JABBERS,
277 SYS_COUNT_RX_CRC_ALIGN_ERRS,
278 SYS_COUNT_RX_SYM_ERRS,
281 SYS_COUNT_RX_128_255,
282 SYS_COUNT_RX_256_1023,
283 SYS_COUNT_RX_1024_1526,
284 SYS_COUNT_RX_1527_MAX,
286 SYS_COUNT_RX_CONTROL,
288 SYS_COUNT_RX_CLASSIFIED_DROPS,
290 SYS_COUNT_TX_UNICAST,
291 SYS_COUNT_TX_MULTICAST,
292 SYS_COUNT_TX_BROADCAST,
293 SYS_COUNT_TX_COLLISION,
298 SYS_COUNT_TX_128_511,
299 SYS_COUNT_TX_512_1023,
300 SYS_COUNT_TX_1024_1526,
301 SYS_COUNT_TX_1527_MAX,
312 SYS_REW_MAC_HIGH_CFG,
314 SYS_TIMESTAMP_OFFSET,
336 HSIO_PLL5G_CFG0 = HSIO << TARGET_OFFSET,
345 HSIO_PLL5G_BIST_CFG0,
346 HSIO_PLL5G_BIST_CFG1,
347 HSIO_PLL5G_BIST_CFG2,
348 HSIO_PLL5G_BIST_STAT0,
349 HSIO_PLL5G_BIST_STAT1,
353 HSIO_SYNC_ETH_PLL_CFG,
365 HSIO_S1G_RC_PLL_BIST_CFG,
368 HSIO_S1G_MISC_STATUS,
369 HSIO_MCB_S1G_ADDR_CFG,
376 HSIO_S6G_RC_PLL_BIST_CFG,
378 HSIO_S6G_OB_ANEG_CFG,
381 HSIO_S6G_MISC_STATUS,
398 HSIO_S6G_ACJTAG_STATUS,
401 HSIO_MCB_S6G_ADDR_CFG,
406 HSIO_TEMP_SENSOR_CTRL,
407 HSIO_TEMP_SENSOR_CFG,
408 HSIO_TEMP_SENSOR_STAT,
411 enum ocelot_regfield {
412 ANA_ADVLEARN_VLAN_CHK,
413 ANA_ADVLEARN_LEARN_MIRROR,
414 ANA_ANEVENTS_FLOOD_DISCARD,
415 ANA_ANEVENTS_MSTI_DROP,
416 ANA_ANEVENTS_ACLKILL,
417 ANA_ANEVENTS_ACLUSED,
418 ANA_ANEVENTS_AUTOAGE,
419 ANA_ANEVENTS_VS2TTL1,
420 ANA_ANEVENTS_STORM_DROP,
421 ANA_ANEVENTS_LEARN_DROP,
422 ANA_ANEVENTS_AGED_ENTRY,
423 ANA_ANEVENTS_CPU_LEARN_FAILED,
424 ANA_ANEVENTS_AUTO_LEARN_FAILED,
425 ANA_ANEVENTS_LEARN_REMOVE,
426 ANA_ANEVENTS_AUTO_LEARNED,
427 ANA_ANEVENTS_AUTO_MOVED,
428 ANA_ANEVENTS_DROPPED,
429 ANA_ANEVENTS_CLASSIFIED_DROP,
430 ANA_ANEVENTS_CLASSIFIED_COPY,
431 ANA_ANEVENTS_VLAN_DISCARD,
432 ANA_ANEVENTS_FWD_DISCARD,
433 ANA_ANEVENTS_MULTICAST_FLOOD,
434 ANA_ANEVENTS_UNICAST_FLOOD,
435 ANA_ANEVENTS_DEST_KNOWN,
436 ANA_ANEVENTS_BUCKET3_MATCH,
437 ANA_ANEVENTS_BUCKET2_MATCH,
438 ANA_ANEVENTS_BUCKET1_MATCH,
439 ANA_ANEVENTS_BUCKET0_MATCH,
440 ANA_ANEVENTS_CPU_OPERATION,
441 ANA_ANEVENTS_DMAC_LOOKUP,
442 ANA_ANEVENTS_SMAC_LOOKUP,
443 ANA_ANEVENTS_SEQ_GEN_ERR_0,
444 ANA_ANEVENTS_SEQ_GEN_ERR_1,
445 ANA_TABLES_MACACCESS_B_DOM,
446 ANA_TABLES_MACTINDX_BUCKET,
447 ANA_TABLES_MACTINDX_M_INDEX,
448 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
449 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
450 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
451 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
452 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
453 SYS_RESET_CFG_CORE_ENA,
454 SYS_RESET_CFG_MEM_ENA,
455 SYS_RESET_CFG_MEM_INIT,
459 struct ocelot_multicast {
460 struct list_head list;
461 unsigned char addr[ETH_ALEN];
468 struct ocelot_stat_layout {
470 char name[ETH_GSTRING_LEN];
476 struct regmap *targets[TARGET_MAX];
477 struct regmap_field *regfields[REGFIELD_MAX];
478 const u32 *const *map;
479 const struct ocelot_stat_layout *stats_layout;
480 unsigned int num_stats;
482 u8 base_mac[ETH_ALEN];
484 struct net_device *hw_bridge_dev;
488 struct workqueue_struct *ocelot_owq;
494 struct ocelot_port **ports;
498 /* Keep track of the vlan port masks */
499 u32 vlan_mask[VLAN_N_VID];
501 struct list_head multicast;
503 /* Workqueue to check statistics for overflow with its lock */
504 struct mutex stats_lock;
506 struct delayed_work stats_work;
507 struct workqueue_struct *stats_queue;
511 struct net_device *dev;
512 struct ocelot *ocelot;
513 struct phy_device *phy;
516 /* Keep a track of the mc addresses added to the mac table, so that they
517 * can be removed when needed.
521 /* Ingress default VLAN (pvid) */
524 /* Egress default VLAN (vid) */
532 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
533 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
534 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
535 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
536 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
538 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
539 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
540 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
541 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
542 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
544 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
546 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
547 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
548 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
549 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
551 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
552 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
554 int ocelot_regfields_init(struct ocelot *ocelot,
555 const struct reg_field *const regfields);
556 struct regmap *ocelot_io_platform_init(struct ocelot *ocelot,
557 struct platform_device *pdev,
560 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))
561 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))
563 int ocelot_init(struct ocelot *ocelot);
564 void ocelot_deinit(struct ocelot *ocelot);
565 int ocelot_chip_init(struct ocelot *ocelot);
566 int ocelot_probe_port(struct ocelot *ocelot, u8 port,
568 struct phy_device *phy);
570 extern struct notifier_block ocelot_netdevice_nb;