1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
7 #include <linux/etherdevice.h>
8 #include <linux/ethtool.h>
9 #include <linux/if_bridge.h>
10 #include <linux/if_ether.h>
11 #include <linux/if_vlan.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/netdevice.h>
16 #include <linux/phy.h>
17 #include <linux/skbuff.h>
19 #include <net/netevent.h>
20 #include <net/rtnetlink.h>
21 #include <net/switchdev.h>
25 /* MAC table entry types.
26 * ENTRYTYPE_NORMAL is subject to aging.
27 * ENTRYTYPE_LOCKED is not subject to aging.
28 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
29 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
31 enum macaccess_entry_type {
38 struct ocelot_mact_entry {
41 enum macaccess_entry_type type;
44 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
46 unsigned int val, timeout = 10;
48 /* Wait for the issued mac table command to be completed, or timeout.
49 * When the command read from ANA_TABLES_MACACCESS is
50 * MACACCESS_CMD_IDLE, the issued command completed successfully.
53 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
54 val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M;
55 } while (val != MACACCESS_CMD_IDLE && timeout--);
63 static void ocelot_mact_select(struct ocelot *ocelot,
64 const unsigned char mac[ETH_ALEN],
67 u32 macl = 0, mach = 0;
69 /* Set the MAC address to handle and the vlan associated in a format
70 * understood by the hardware.
80 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
81 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
85 static int ocelot_mact_learn(struct ocelot *ocelot, int port,
86 const unsigned char mac[ETH_ALEN],
88 enum macaccess_entry_type type)
90 ocelot_mact_select(ocelot, mac, vid);
92 /* Issue a write command */
93 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
94 ANA_TABLES_MACACCESS_DEST_IDX(port) |
95 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
96 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
97 ANA_TABLES_MACACCESS);
99 return ocelot_mact_wait_for_completion(ocelot);
102 static int ocelot_mact_forget(struct ocelot *ocelot,
103 const unsigned char mac[ETH_ALEN],
106 ocelot_mact_select(ocelot, mac, vid);
108 /* Issue a forget command */
110 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
111 ANA_TABLES_MACACCESS);
113 return ocelot_mact_wait_for_completion(ocelot);
116 static void ocelot_mact_init(struct ocelot *ocelot)
118 /* Configure the learning mode entries attributes:
119 * - Do not copy the frame to the CPU extraction queues.
120 * - Use the vlan and mac_cpoy for dmac lookup.
122 ocelot_rmw(ocelot, 0,
123 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
124 | ANA_AGENCTRL_LEARN_FWD_KILL
125 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
128 /* Clear the MAC table */
129 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
132 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
134 unsigned int val, timeout = 10;
136 /* Wait for the issued vlan table command to be completed, or timeout.
137 * When the command read from ANA_TABLES_VLANACCESS is
138 * VLANACCESS_CMD_IDLE, the issued command completed successfully.
141 val = ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
142 val &= ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M;
143 } while (val != ANA_TABLES_VLANACCESS_CMD_IDLE && timeout--);
151 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
153 /* Select the VID to configure */
154 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
155 ANA_TABLES_VLANTIDX);
156 /* Set the vlan port members mask and issue a write command */
157 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
158 ANA_TABLES_VLANACCESS_CMD_WRITE,
159 ANA_TABLES_VLANACCESS);
161 return ocelot_vlant_wait_for_completion(ocelot);
164 static void ocelot_vlan_mode(struct ocelot_port *port,
165 netdev_features_t features)
167 struct ocelot *ocelot = port->ocelot;
168 u8 p = port->chip_port;
172 val = ocelot_read(ocelot, ANA_VLANMASK);
173 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
177 ocelot_write(ocelot, val, ANA_VLANMASK);
180 static void ocelot_vlan_port_apply(struct ocelot *ocelot,
181 struct ocelot_port *port)
185 /* Ingress clasification (ANA_PORT_VLAN_CFG) */
186 /* Default vlan to clasify for untagged frames (may be zero) */
187 val = ANA_PORT_VLAN_CFG_VLAN_VID(port->pvid);
188 if (port->vlan_aware)
189 val |= ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
190 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
192 ocelot_rmw_gix(ocelot, val,
193 ANA_PORT_VLAN_CFG_VLAN_VID_M |
194 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
195 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
196 ANA_PORT_VLAN_CFG, port->chip_port);
198 /* Drop frames with multicast source address */
199 val = ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA;
200 if (port->vlan_aware && !port->vid)
201 /* If port is vlan-aware and tagged, drop untagged and priority
204 val |= ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA |
205 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
206 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
207 ocelot_write_gix(ocelot, val, ANA_PORT_DROP_CFG, port->chip_port);
209 /* Egress configuration (REW_TAG_CFG): VLAN tag type to 8021Q. */
210 val = REW_TAG_CFG_TAG_TPID_CFG(0);
212 if (port->vlan_aware) {
214 /* Tag all frames except when VID == DEFAULT_VLAN */
215 val |= REW_TAG_CFG_TAG_CFG(1);
218 val |= REW_TAG_CFG_TAG_CFG(3);
220 ocelot_rmw_gix(ocelot, val,
221 REW_TAG_CFG_TAG_TPID_CFG_M |
222 REW_TAG_CFG_TAG_CFG_M,
223 REW_TAG_CFG, port->chip_port);
225 /* Set default VLAN and tag type to 8021Q. */
226 val = REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q) |
227 REW_PORT_VLAN_CFG_PORT_VID(port->vid);
228 ocelot_rmw_gix(ocelot, val,
229 REW_PORT_VLAN_CFG_PORT_TPID_M |
230 REW_PORT_VLAN_CFG_PORT_VID_M,
231 REW_PORT_VLAN_CFG, port->chip_port);
234 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid,
237 struct ocelot_port *port = netdev_priv(dev);
238 struct ocelot *ocelot = port->ocelot;
241 /* Add the port MAC address to with the right VLAN information */
242 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid,
245 /* Make the port a member of the VLAN */
246 ocelot->vlan_mask[vid] |= BIT(port->chip_port);
247 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
251 /* Default ingress vlan classification */
255 /* Untagged egress vlan clasification */
256 if (untagged && port->vid != vid) {
259 "Port already has a native VLAN: %d\n",
266 ocelot_vlan_port_apply(ocelot, port);
271 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid)
273 struct ocelot_port *port = netdev_priv(dev);
274 struct ocelot *ocelot = port->ocelot;
277 /* 8021q removes VID 0 on module unload for all interfaces
278 * with VLAN filtering feature. We need to keep it to receive
284 /* Del the port MAC address to with the right VLAN information */
285 ocelot_mact_forget(ocelot, dev->dev_addr, vid);
287 /* Stop the port from being a member of the vlan */
288 ocelot->vlan_mask[vid] &= ~BIT(port->chip_port);
289 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
294 if (port->pvid == vid)
298 if (port->vid == vid)
301 ocelot_vlan_port_apply(ocelot, port);
306 static void ocelot_vlan_init(struct ocelot *ocelot)
310 /* Clear VLAN table, by default all ports are members of all VLANs */
311 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
312 ANA_TABLES_VLANACCESS);
313 ocelot_vlant_wait_for_completion(ocelot);
315 /* Configure the port VLAN memberships */
316 for (vid = 1; vid < VLAN_N_VID; vid++) {
317 ocelot->vlan_mask[vid] = 0;
318 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
321 /* Because VLAN filtering is enabled, we need VID 0 to get untagged
322 * traffic. It is added automatically if 8021q module is loaded, but
323 * we can't rely on it since module may be not loaded.
325 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0);
326 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]);
328 /* Configure the CPU port to be VLAN aware */
329 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
330 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
331 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
332 ANA_PORT_VLAN_CFG, ocelot->num_phys_ports);
334 /* Set vlan ingress filter mask to all ports but the CPU port by
337 ocelot_write(ocelot, GENMASK(9, 0), ANA_VLANMASK);
339 for (port = 0; port < ocelot->num_phys_ports; port++) {
340 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
341 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
346 * Bit 8: Unit; 0:1, 1:16
347 * Bit 7-0: Value to be multiplied with unit
349 static u16 ocelot_wm_enc(u16 value)
352 return BIT(8) | (value / 16);
357 static void ocelot_port_adjust_link(struct net_device *dev)
359 struct ocelot_port *port = netdev_priv(dev);
360 struct ocelot *ocelot = port->ocelot;
361 u8 p = port->chip_port;
362 int speed, atop_wm, mode = 0;
364 switch (dev->phydev->speed) {
366 speed = OCELOT_SPEED_10;
369 speed = OCELOT_SPEED_100;
372 speed = OCELOT_SPEED_1000;
373 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
376 speed = OCELOT_SPEED_2500;
377 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
380 netdev_err(dev, "Unsupported PHY speed: %d\n",
385 phy_print_status(dev->phydev);
387 if (!dev->phydev->link)
390 /* Only full duplex supported for now */
391 ocelot_port_writel(port, DEV_MAC_MODE_CFG_FDX_ENA |
392 mode, DEV_MAC_MODE_CFG);
395 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
396 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
398 ocelot_port_writel(port, DEV_MAC_IFG_CFG_TX_IFG(5), DEV_MAC_IFG_CFG);
400 /* Load seed (0) and set MAC HDX late collision */
401 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
402 DEV_MAC_HDX_CFG_SEED_LOAD,
405 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
408 /* Disable HDX fast control */
409 ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC);
411 /* SGMII only for now */
412 ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA, PCS1G_MODE_CFG);
413 ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
416 ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
418 /* No aneg on SGMII */
419 ocelot_port_writel(port, 0, PCS1G_ANEG_CFG);
422 ocelot_port_writel(port, 0, PCS1G_LB_CFG);
424 /* Set Max Length and maximum tags allowed */
425 ocelot_port_writel(port, VLAN_ETH_FRAME_LEN, DEV_MAC_MAXLEN_CFG);
426 ocelot_port_writel(port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
427 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
428 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
431 /* Enable MAC module */
432 ocelot_port_writel(port, DEV_MAC_ENA_CFG_RX_ENA |
433 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
435 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
437 ocelot_port_writel(port, DEV_CLOCK_CFG_LINK_SPEED(speed),
440 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
441 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
442 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_LOW_CFG);
445 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
448 /* Set Pause WM hysteresis
449 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
450 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
452 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
453 SYS_PAUSE_CFG_PAUSE_STOP(101) |
454 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, p);
456 /* Core: Enable port for frame transfer */
457 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
458 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
459 QSYS_SWITCH_PORT_MODE_PORT_ENA,
460 QSYS_SWITCH_PORT_MODE, p);
463 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
464 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA |
465 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
466 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
467 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
469 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, p);
471 /* Tail dropping watermark */
472 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
473 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
475 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
478 static int ocelot_port_open(struct net_device *dev)
480 struct ocelot_port *port = netdev_priv(dev);
481 struct ocelot *ocelot = port->ocelot;
484 /* Enable receiving frames on the port, and activate auto-learning of
487 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
488 ANA_PORT_PORT_CFG_RECV_ENA |
489 ANA_PORT_PORT_CFG_PORTID_VAL(port->chip_port),
490 ANA_PORT_PORT_CFG, port->chip_port);
492 err = phy_connect_direct(dev, port->phy, &ocelot_port_adjust_link,
493 PHY_INTERFACE_MODE_NA);
495 netdev_err(dev, "Could not attach to PHY\n");
499 dev->phydev = port->phy;
501 phy_attached_info(port->phy);
502 phy_start(port->phy);
506 static int ocelot_port_stop(struct net_device *dev)
508 struct ocelot_port *port = netdev_priv(dev);
510 phy_disconnect(port->phy);
514 ocelot_port_writel(port, 0, DEV_MAC_ENA_CFG);
515 ocelot_rmw_rix(port->ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA,
516 QSYS_SWITCH_PORT_MODE, port->chip_port);
520 /* Generate the IFH for frame injection
522 * The IFH is a 128bit-value
523 * bit 127: bypass the analyzer processing
524 * bit 56-67: destination mask
525 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
526 * bit 20-27: cpu extraction queue mask
527 * bit 16: tag type 0: C-tag, 1: S-tag
530 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info)
532 ifh[0] = IFH_INJ_BYPASS;
533 ifh[1] = (0xf00 & info->port) >> 8;
534 ifh[2] = (0xff & info->port) << 24;
535 ifh[3] = (info->tag_type << 16) | info->vid;
540 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev)
542 struct ocelot_port *port = netdev_priv(dev);
543 struct ocelot *ocelot = port->ocelot;
544 u32 val, ifh[IFH_LEN];
545 struct frame_info info = {};
546 u8 grp = 0; /* Send everything on CPU group 0 */
547 unsigned int i, count, last;
549 val = ocelot_read(ocelot, QS_INJ_STATUS);
550 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) ||
551 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))))
552 return NETDEV_TX_BUSY;
554 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
555 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
557 info.port = BIT(port->chip_port);
558 info.tag_type = IFH_TAG_TYPE_C;
559 info.vid = skb_vlan_tag_get(skb);
560 ocelot_gen_ifh(ifh, &info);
562 for (i = 0; i < IFH_LEN; i++)
563 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]),
566 count = (skb->len + 3) / 4;
568 for (i = 0; i < count; i++) {
569 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
573 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
574 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
578 /* Indicate EOF and valid bytes in last word */
579 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
580 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
585 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
586 skb_tx_timestamp(skb);
588 dev->stats.tx_packets++;
589 dev->stats.tx_bytes += skb->len;
590 dev_kfree_skb_any(skb);
595 static void ocelot_mact_mc_reset(struct ocelot_port *port)
597 struct ocelot *ocelot = port->ocelot;
598 struct netdev_hw_addr *ha, *n;
600 /* Free and forget all the MAC addresses stored in the port private mc
601 * list. These are mc addresses that were previously added by calling
602 * ocelot_mact_mc_add().
604 list_for_each_entry_safe(ha, n, &port->mc, list) {
605 ocelot_mact_forget(ocelot, ha->addr, port->pvid);
611 static int ocelot_mact_mc_add(struct ocelot_port *port,
612 struct netdev_hw_addr *hw_addr)
614 struct ocelot *ocelot = port->ocelot;
615 struct netdev_hw_addr *ha = kzalloc(sizeof(*ha), GFP_ATOMIC);
620 memcpy(ha, hw_addr, sizeof(*ha));
621 list_add_tail(&ha->list, &port->mc);
623 ocelot_mact_learn(ocelot, PGID_CPU, ha->addr, port->pvid,
629 static void ocelot_set_rx_mode(struct net_device *dev)
631 struct ocelot_port *port = netdev_priv(dev);
632 struct ocelot *ocelot = port->ocelot;
633 struct netdev_hw_addr *ha;
637 /* This doesn't handle promiscuous mode because the bridge core is
638 * setting IFF_PROMISC on all slave interfaces and all frames would be
639 * forwarded to the CPU port.
641 val = GENMASK(ocelot->num_phys_ports - 1, 0);
642 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++)
643 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
645 /* Handle the device multicast addresses. First remove all the
646 * previously installed addresses and then add the latest ones to the
649 ocelot_mact_mc_reset(port);
650 netdev_for_each_mc_addr(ha, dev)
651 ocelot_mact_mc_add(port, ha);
654 static int ocelot_port_get_phys_port_name(struct net_device *dev,
655 char *buf, size_t len)
657 struct ocelot_port *port = netdev_priv(dev);
660 ret = snprintf(buf, len, "p%d", port->chip_port);
667 static int ocelot_port_set_mac_address(struct net_device *dev, void *p)
669 struct ocelot_port *port = netdev_priv(dev);
670 struct ocelot *ocelot = port->ocelot;
671 const struct sockaddr *addr = p;
673 /* Learn the new net device MAC address in the mac table. */
674 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, port->pvid,
676 /* Then forget the previous one. */
677 ocelot_mact_forget(ocelot, dev->dev_addr, port->pvid);
679 ether_addr_copy(dev->dev_addr, addr->sa_data);
683 static void ocelot_get_stats64(struct net_device *dev,
684 struct rtnl_link_stats64 *stats)
686 struct ocelot_port *port = netdev_priv(dev);
687 struct ocelot *ocelot = port->ocelot;
689 /* Configure the port to read the stats from */
690 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port->chip_port),
694 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS);
695 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) +
696 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) +
697 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) +
698 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) +
699 ocelot_read(ocelot, SYS_COUNT_RX_64) +
700 ocelot_read(ocelot, SYS_COUNT_RX_65_127) +
701 ocelot_read(ocelot, SYS_COUNT_RX_128_255) +
702 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) +
703 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) +
704 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX);
705 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST);
706 stats->rx_dropped = dev->stats.rx_dropped;
709 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS);
710 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) +
711 ocelot_read(ocelot, SYS_COUNT_TX_65_127) +
712 ocelot_read(ocelot, SYS_COUNT_TX_128_511) +
713 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) +
714 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) +
715 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX);
716 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) +
717 ocelot_read(ocelot, SYS_COUNT_TX_AGING);
718 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION);
721 static int ocelot_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
722 struct net_device *dev, const unsigned char *addr,
725 struct ocelot_port *port = netdev_priv(dev);
726 struct ocelot *ocelot = port->ocelot;
729 if (!port->vlan_aware)
730 /* If the bridge is not VLAN aware and no VID was
731 * provided, set it to pvid to ensure the MAC entry
732 * matches incoming untagged packets
736 /* If the bridge is VLAN aware a VID must be provided as
737 * otherwise the learnt entry wouldn't match any frame.
742 return ocelot_mact_learn(ocelot, port->chip_port, addr, vid,
746 static int ocelot_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
747 struct net_device *dev,
748 const unsigned char *addr, u16 vid)
750 struct ocelot_port *port = netdev_priv(dev);
751 struct ocelot *ocelot = port->ocelot;
753 return ocelot_mact_forget(ocelot, addr, vid);
756 struct ocelot_dump_ctx {
757 struct net_device *dev;
759 struct netlink_callback *cb;
763 static int ocelot_fdb_do_dump(struct ocelot_mact_entry *entry,
764 struct ocelot_dump_ctx *dump)
766 u32 portid = NETLINK_CB(dump->cb->skb).portid;
767 u32 seq = dump->cb->nlh->nlmsg_seq;
768 struct nlmsghdr *nlh;
771 if (dump->idx < dump->cb->args[2])
774 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
775 sizeof(*ndm), NLM_F_MULTI);
779 ndm = nlmsg_data(nlh);
780 ndm->ndm_family = AF_BRIDGE;
783 ndm->ndm_flags = NTF_SELF;
785 ndm->ndm_ifindex = dump->dev->ifindex;
786 ndm->ndm_state = NUD_REACHABLE;
788 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, entry->mac))
789 goto nla_put_failure;
791 if (entry->vid && nla_put_u16(dump->skb, NDA_VLAN, entry->vid))
792 goto nla_put_failure;
794 nlmsg_end(dump->skb, nlh);
801 nlmsg_cancel(dump->skb, nlh);
805 static inline int ocelot_mact_read(struct ocelot_port *port, int row, int col,
806 struct ocelot_mact_entry *entry)
808 struct ocelot *ocelot = port->ocelot;
810 u32 val, dst, macl, mach;
812 /* Set row and column to read from */
813 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
814 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
816 /* Issue a read command */
818 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
819 ANA_TABLES_MACACCESS);
821 if (ocelot_mact_wait_for_completion(ocelot))
824 /* Read the entry flags */
825 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
826 if (!(val & ANA_TABLES_MACACCESS_VALID))
829 /* If the entry read has another port configured as its destination,
832 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
833 if (dst != port->chip_port)
836 /* Get the entry's MAC address and VLAN id */
837 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
838 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
840 mac[0] = (mach >> 8) & 0xff;
841 mac[1] = (mach >> 0) & 0xff;
842 mac[2] = (macl >> 24) & 0xff;
843 mac[3] = (macl >> 16) & 0xff;
844 mac[4] = (macl >> 8) & 0xff;
845 mac[5] = (macl >> 0) & 0xff;
847 entry->vid = (mach >> 16) & 0xfff;
848 ether_addr_copy(entry->mac, mac);
853 static int ocelot_fdb_dump(struct sk_buff *skb, struct netlink_callback *cb,
854 struct net_device *dev,
855 struct net_device *filter_dev, int *idx)
857 struct ocelot_port *port = netdev_priv(dev);
859 struct ocelot_dump_ctx dump = {
866 struct ocelot_mact_entry entry;
868 /* Loop through all the mac tables entries. There are 1024 rows of 4
871 for (i = 0; i < 1024; i++) {
872 for (j = 0; j < 4; j++) {
873 ret = ocelot_mact_read(port, i, j, &entry);
874 /* If the entry is invalid (wrong port, invalid...),
882 ret = ocelot_fdb_do_dump(&entry, &dump);
893 static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto,
896 return ocelot_vlan_vid_add(dev, vid, false, false);
899 static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto,
902 return ocelot_vlan_vid_del(dev, vid);
905 static int ocelot_set_features(struct net_device *dev,
906 netdev_features_t features)
908 struct ocelot_port *port = netdev_priv(dev);
909 netdev_features_t changed = dev->features ^ features;
911 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER)
912 ocelot_vlan_mode(port, features);
917 static const struct net_device_ops ocelot_port_netdev_ops = {
918 .ndo_open = ocelot_port_open,
919 .ndo_stop = ocelot_port_stop,
920 .ndo_start_xmit = ocelot_port_xmit,
921 .ndo_set_rx_mode = ocelot_set_rx_mode,
922 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name,
923 .ndo_set_mac_address = ocelot_port_set_mac_address,
924 .ndo_get_stats64 = ocelot_get_stats64,
925 .ndo_fdb_add = ocelot_fdb_add,
926 .ndo_fdb_del = ocelot_fdb_del,
927 .ndo_fdb_dump = ocelot_fdb_dump,
928 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid,
929 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid,
930 .ndo_set_features = ocelot_set_features,
933 static void ocelot_get_strings(struct net_device *netdev, u32 sset, u8 *data)
935 struct ocelot_port *port = netdev_priv(netdev);
936 struct ocelot *ocelot = port->ocelot;
939 if (sset != ETH_SS_STATS)
942 for (i = 0; i < ocelot->num_stats; i++)
943 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
947 static void ocelot_check_stats(struct work_struct *work)
949 struct delayed_work *del_work = to_delayed_work(work);
950 struct ocelot *ocelot = container_of(del_work, struct ocelot, stats_work);
953 mutex_lock(&ocelot->stats_lock);
955 for (i = 0; i < ocelot->num_phys_ports; i++) {
956 /* Configure the port to read the stats from */
957 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG);
959 for (j = 0; j < ocelot->num_stats; j++) {
961 unsigned int idx = i * ocelot->num_stats + j;
963 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS,
964 ocelot->stats_layout[j].offset);
966 if (val < (ocelot->stats[idx] & U32_MAX))
967 ocelot->stats[idx] += (u64)1 << 32;
969 ocelot->stats[idx] = (ocelot->stats[idx] &
970 ~(u64)U32_MAX) + val;
974 cancel_delayed_work(&ocelot->stats_work);
975 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
976 OCELOT_STATS_CHECK_DELAY);
978 mutex_unlock(&ocelot->stats_lock);
981 static void ocelot_get_ethtool_stats(struct net_device *dev,
982 struct ethtool_stats *stats, u64 *data)
984 struct ocelot_port *port = netdev_priv(dev);
985 struct ocelot *ocelot = port->ocelot;
988 /* check and update now */
989 ocelot_check_stats(&ocelot->stats_work.work);
991 /* Copy all counters */
992 for (i = 0; i < ocelot->num_stats; i++)
993 *data++ = ocelot->stats[port->chip_port * ocelot->num_stats + i];
996 static int ocelot_get_sset_count(struct net_device *dev, int sset)
998 struct ocelot_port *port = netdev_priv(dev);
999 struct ocelot *ocelot = port->ocelot;
1001 if (sset != ETH_SS_STATS)
1003 return ocelot->num_stats;
1006 static const struct ethtool_ops ocelot_ethtool_ops = {
1007 .get_strings = ocelot_get_strings,
1008 .get_ethtool_stats = ocelot_get_ethtool_stats,
1009 .get_sset_count = ocelot_get_sset_count,
1010 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1011 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1014 static int ocelot_port_attr_get(struct net_device *dev,
1015 struct switchdev_attr *attr)
1017 struct ocelot_port *ocelot_port = netdev_priv(dev);
1018 struct ocelot *ocelot = ocelot_port->ocelot;
1021 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
1022 attr->u.ppid.id_len = sizeof(ocelot->base_mac);
1023 memcpy(&attr->u.ppid.id, &ocelot->base_mac,
1024 attr->u.ppid.id_len);
1033 static int ocelot_port_attr_stp_state_set(struct ocelot_port *ocelot_port,
1034 struct switchdev_trans *trans,
1037 struct ocelot *ocelot = ocelot_port->ocelot;
1041 if (switchdev_trans_ph_prepare(trans))
1044 if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask))
1047 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG,
1048 ocelot_port->chip_port);
1051 case BR_STATE_FORWARDING:
1052 ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port);
1054 case BR_STATE_LEARNING:
1055 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
1059 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
1060 ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port);
1064 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG,
1065 ocelot_port->chip_port);
1067 /* Apply FWD mask. The loop is needed to add/remove the current port as
1068 * a source for the other ports.
1070 for (port = 0; port < ocelot->num_phys_ports; port++) {
1071 if (ocelot->bridge_fwd_mask & BIT(port)) {
1072 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port);
1074 for (i = 0; i < ocelot->num_phys_ports; i++) {
1075 unsigned long bond_mask = ocelot->lags[i];
1080 if (bond_mask & BIT(port)) {
1086 ocelot_write_rix(ocelot,
1087 BIT(ocelot->num_phys_ports) | mask,
1088 ANA_PGID_PGID, PGID_SRC + port);
1090 /* Only the CPU port, this is compatible with link
1093 ocelot_write_rix(ocelot,
1094 BIT(ocelot->num_phys_ports),
1095 ANA_PGID_PGID, PGID_SRC + port);
1102 static void ocelot_port_attr_ageing_set(struct ocelot_port *ocelot_port,
1103 unsigned long ageing_clock_t)
1105 struct ocelot *ocelot = ocelot_port->ocelot;
1106 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t);
1107 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000;
1109 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(ageing_time / 2),
1113 static void ocelot_port_attr_mc_set(struct ocelot_port *port, bool mc)
1115 struct ocelot *ocelot = port->ocelot;
1116 u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG,
1120 val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
1121 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
1122 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA;
1124 val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
1125 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
1126 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA);
1128 ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port);
1131 static int ocelot_port_attr_set(struct net_device *dev,
1132 const struct switchdev_attr *attr,
1133 struct switchdev_trans *trans)
1135 struct ocelot_port *ocelot_port = netdev_priv(dev);
1139 case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
1140 ocelot_port_attr_stp_state_set(ocelot_port, trans,
1143 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME:
1144 ocelot_port_attr_ageing_set(ocelot_port, attr->u.ageing_time);
1146 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING:
1147 ocelot_port->vlan_aware = attr->u.vlan_filtering;
1148 ocelot_vlan_port_apply(ocelot_port->ocelot, ocelot_port);
1150 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED:
1151 ocelot_port_attr_mc_set(ocelot_port, !attr->u.mc_disabled);
1161 static int ocelot_port_obj_add_vlan(struct net_device *dev,
1162 const struct switchdev_obj_port_vlan *vlan,
1163 struct switchdev_trans *trans)
1168 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
1169 ret = ocelot_vlan_vid_add(dev, vid,
1170 vlan->flags & BRIDGE_VLAN_INFO_PVID,
1171 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED);
1179 static int ocelot_port_vlan_del_vlan(struct net_device *dev,
1180 const struct switchdev_obj_port_vlan *vlan)
1185 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
1186 ret = ocelot_vlan_vid_del(dev, vid);
1195 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
1196 const unsigned char *addr,
1199 struct ocelot_multicast *mc;
1201 list_for_each_entry(mc, &ocelot->multicast, list) {
1202 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
1209 static int ocelot_port_obj_add_mdb(struct net_device *dev,
1210 const struct switchdev_obj_port_mdb *mdb,
1211 struct switchdev_trans *trans)
1213 struct ocelot_port *port = netdev_priv(dev);
1214 struct ocelot *ocelot = port->ocelot;
1215 struct ocelot_multicast *mc;
1216 unsigned char addr[ETH_ALEN];
1223 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1225 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1229 memcpy(mc->addr, mdb->addr, ETH_ALEN);
1232 list_add_tail(&mc->list, &ocelot->multicast);
1236 memcpy(addr, mc->addr, ETH_ALEN);
1240 addr[2] = mc->ports << 0;
1241 addr[1] = mc->ports << 8;
1242 ocelot_mact_forget(ocelot, addr, vid);
1245 mc->ports |= BIT(port->chip_port);
1246 addr[2] = mc->ports << 0;
1247 addr[1] = mc->ports << 8;
1249 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
1252 static int ocelot_port_obj_del_mdb(struct net_device *dev,
1253 const struct switchdev_obj_port_mdb *mdb)
1255 struct ocelot_port *port = netdev_priv(dev);
1256 struct ocelot *ocelot = port->ocelot;
1257 struct ocelot_multicast *mc;
1258 unsigned char addr[ETH_ALEN];
1264 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1268 memcpy(addr, mc->addr, ETH_ALEN);
1269 addr[2] = mc->ports << 0;
1270 addr[1] = mc->ports << 8;
1272 ocelot_mact_forget(ocelot, addr, vid);
1274 mc->ports &= ~BIT(port->chip_port);
1276 list_del(&mc->list);
1277 devm_kfree(ocelot->dev, mc);
1281 addr[2] = mc->ports << 0;
1282 addr[1] = mc->ports << 8;
1284 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
1287 static int ocelot_port_obj_add(struct net_device *dev,
1288 const struct switchdev_obj *obj,
1289 struct switchdev_trans *trans)
1294 case SWITCHDEV_OBJ_ID_PORT_VLAN:
1295 ret = ocelot_port_obj_add_vlan(dev,
1296 SWITCHDEV_OBJ_PORT_VLAN(obj),
1299 case SWITCHDEV_OBJ_ID_PORT_MDB:
1300 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj),
1310 static int ocelot_port_obj_del(struct net_device *dev,
1311 const struct switchdev_obj *obj)
1316 case SWITCHDEV_OBJ_ID_PORT_VLAN:
1317 ret = ocelot_port_vlan_del_vlan(dev,
1318 SWITCHDEV_OBJ_PORT_VLAN(obj));
1320 case SWITCHDEV_OBJ_ID_PORT_MDB:
1321 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj));
1330 static const struct switchdev_ops ocelot_port_switchdev_ops = {
1331 .switchdev_port_attr_get = ocelot_port_attr_get,
1332 .switchdev_port_attr_set = ocelot_port_attr_set,
1333 .switchdev_port_obj_add = ocelot_port_obj_add,
1334 .switchdev_port_obj_del = ocelot_port_obj_del,
1337 static int ocelot_port_bridge_join(struct ocelot_port *ocelot_port,
1338 struct net_device *bridge)
1340 struct ocelot *ocelot = ocelot_port->ocelot;
1342 if (!ocelot->bridge_mask) {
1343 ocelot->hw_bridge_dev = bridge;
1345 if (ocelot->hw_bridge_dev != bridge)
1346 /* This is adding the port to a second bridge, this is
1351 ocelot->bridge_mask |= BIT(ocelot_port->chip_port);
1356 static void ocelot_port_bridge_leave(struct ocelot_port *ocelot_port,
1357 struct net_device *bridge)
1359 struct ocelot *ocelot = ocelot_port->ocelot;
1361 ocelot->bridge_mask &= ~BIT(ocelot_port->chip_port);
1363 if (!ocelot->bridge_mask)
1364 ocelot->hw_bridge_dev = NULL;
1366 /* Clear bridge vlan settings before calling ocelot_vlan_port_apply */
1367 ocelot_port->vlan_aware = 0;
1368 ocelot_port->pvid = 0;
1369 ocelot_port->vid = 0;
1372 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1376 /* Reset destination and aggregation PGIDS */
1377 for (port = 0; port < ocelot->num_phys_ports; port++)
1378 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1380 for (i = PGID_AGGR; i < PGID_SRC; i++)
1381 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
1384 /* Now, set PGIDs for each LAG */
1385 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
1386 unsigned long bond_mask;
1390 bond_mask = ocelot->lags[lag];
1394 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
1396 ocelot_write_rix(ocelot, bond_mask,
1397 ANA_PGID_PGID, port);
1398 aggr_idx[aggr_count] = port;
1402 for (i = PGID_AGGR; i < PGID_SRC; i++) {
1405 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
1407 ac |= BIT(aggr_idx[i % aggr_count]);
1408 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
1413 static void ocelot_setup_lag(struct ocelot *ocelot, int lag)
1415 unsigned long bond_mask = ocelot->lags[lag];
1418 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) {
1419 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p);
1421 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1423 /* Use lag port as logical port for port i */
1424 ocelot_write_gix(ocelot, port_cfg |
1425 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
1426 ANA_PORT_PORT_CFG, p);
1430 static int ocelot_port_lag_join(struct ocelot_port *ocelot_port,
1431 struct net_device *bond)
1433 struct ocelot *ocelot = ocelot_port->ocelot;
1434 int p = ocelot_port->chip_port;
1436 struct net_device *ndev;
1440 for_each_netdev_in_bond_rcu(bond, ndev) {
1441 struct ocelot_port *port = netdev_priv(ndev);
1443 bond_mask |= BIT(port->chip_port);
1447 lp = __ffs(bond_mask);
1449 /* If the new port is the lowest one, use it as the logical port from
1454 ocelot->lags[p] = bond_mask;
1455 bond_mask &= ~BIT(p);
1457 lp = __ffs(bond_mask);
1458 ocelot->lags[lp] = 0;
1462 ocelot->lags[lp] |= BIT(p);
1465 ocelot_setup_lag(ocelot, lag);
1466 ocelot_set_aggr_pgids(ocelot);
1471 static void ocelot_port_lag_leave(struct ocelot_port *ocelot_port,
1472 struct net_device *bond)
1474 struct ocelot *ocelot = ocelot_port->ocelot;
1475 int p = ocelot_port->chip_port;
1479 /* Remove port from any lag */
1480 for (i = 0; i < ocelot->num_phys_ports; i++)
1481 ocelot->lags[i] &= ~BIT(ocelot_port->chip_port);
1483 /* if it was the logical port of the lag, move the lag config to the
1486 if (ocelot->lags[p]) {
1487 int n = __ffs(ocelot->lags[p]);
1489 ocelot->lags[n] = ocelot->lags[p];
1490 ocelot->lags[p] = 0;
1492 ocelot_setup_lag(ocelot, n);
1495 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p);
1496 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1497 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(p),
1498 ANA_PORT_PORT_CFG, p);
1500 ocelot_set_aggr_pgids(ocelot);
1503 /* Checks if the net_device instance given to us originate from our driver. */
1504 static bool ocelot_netdevice_dev_check(const struct net_device *dev)
1506 return dev->netdev_ops == &ocelot_port_netdev_ops;
1509 static int ocelot_netdevice_port_event(struct net_device *dev,
1510 unsigned long event,
1511 struct netdev_notifier_changeupper_info *info)
1513 struct ocelot_port *ocelot_port = netdev_priv(dev);
1517 case NETDEV_CHANGEUPPER:
1518 if (netif_is_bridge_master(info->upper_dev)) {
1520 err = ocelot_port_bridge_join(ocelot_port,
1523 ocelot_port_bridge_leave(ocelot_port,
1526 ocelot_vlan_port_apply(ocelot_port->ocelot,
1529 if (netif_is_lag_master(info->upper_dev)) {
1531 err = ocelot_port_lag_join(ocelot_port,
1534 ocelot_port_lag_leave(ocelot_port,
1545 static int ocelot_netdevice_event(struct notifier_block *unused,
1546 unsigned long event, void *ptr)
1548 struct netdev_notifier_changeupper_info *info = ptr;
1549 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
1552 if (event == NETDEV_PRECHANGEUPPER &&
1553 ocelot_netdevice_dev_check(dev) &&
1554 netif_is_lag_master(info->upper_dev)) {
1555 struct netdev_lag_upper_info *lag_upper_info = info->upper_info;
1556 struct netlink_ext_ack *extack;
1558 if (lag_upper_info &&
1559 lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
1560 extack = netdev_notifier_info_to_extack(&info->info);
1561 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
1568 if (netif_is_lag_master(dev)) {
1569 struct net_device *slave;
1570 struct list_head *iter;
1572 netdev_for_each_lower_dev(dev, slave, iter) {
1573 ret = ocelot_netdevice_port_event(slave, event, info);
1578 ret = ocelot_netdevice_port_event(dev, event, info);
1582 return notifier_from_errno(ret);
1585 struct notifier_block ocelot_netdevice_nb __read_mostly = {
1586 .notifier_call = ocelot_netdevice_event,
1588 EXPORT_SYMBOL(ocelot_netdevice_nb);
1590 int ocelot_probe_port(struct ocelot *ocelot, u8 port,
1592 struct phy_device *phy)
1594 struct ocelot_port *ocelot_port;
1595 struct net_device *dev;
1598 dev = alloc_etherdev(sizeof(struct ocelot_port));
1601 SET_NETDEV_DEV(dev, ocelot->dev);
1602 ocelot_port = netdev_priv(dev);
1603 ocelot_port->dev = dev;
1604 ocelot_port->ocelot = ocelot;
1605 ocelot_port->regs = regs;
1606 ocelot_port->chip_port = port;
1607 ocelot_port->phy = phy;
1608 INIT_LIST_HEAD(&ocelot_port->mc);
1609 ocelot->ports[port] = ocelot_port;
1611 dev->netdev_ops = &ocelot_port_netdev_ops;
1612 dev->ethtool_ops = &ocelot_ethtool_ops;
1613 dev->switchdev_ops = &ocelot_port_switchdev_ops;
1615 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1616 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1618 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN);
1619 dev->dev_addr[ETH_ALEN - 1] += port;
1620 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid,
1623 err = register_netdev(dev);
1625 dev_err(ocelot->dev, "register_netdev failed\n");
1626 goto err_register_netdev;
1629 /* Basic L2 initialization */
1630 ocelot_vlan_port_apply(ocelot, ocelot_port);
1634 err_register_netdev:
1638 EXPORT_SYMBOL(ocelot_probe_port);
1640 int ocelot_init(struct ocelot *ocelot)
1643 int i, cpu = ocelot->num_phys_ports;
1644 char queue_name[32];
1646 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
1647 sizeof(u32), GFP_KERNEL);
1651 ocelot->stats = devm_kcalloc(ocelot->dev,
1652 ocelot->num_phys_ports * ocelot->num_stats,
1653 sizeof(u64), GFP_KERNEL);
1657 mutex_init(&ocelot->stats_lock);
1658 snprintf(queue_name, sizeof(queue_name), "%s-stats",
1659 dev_name(ocelot->dev));
1660 ocelot->stats_queue = create_singlethread_workqueue(queue_name);
1661 if (!ocelot->stats_queue)
1664 ocelot_mact_init(ocelot);
1665 ocelot_vlan_init(ocelot);
1667 for (port = 0; port < ocelot->num_phys_ports; port++) {
1668 /* Clear all counters (5 groups) */
1669 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
1670 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
1674 /* Only use S-Tag */
1675 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
1677 /* Aggregation mode */
1678 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
1679 ANA_AGGR_CFG_AC_DMAC_ENA |
1680 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
1681 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG);
1683 /* Set MAC age time to default value. The entry is aged after
1686 ocelot_write(ocelot,
1687 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
1690 /* Disable learning for frames discarded by VLAN ingress filtering */
1691 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
1693 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
1694 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
1695 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
1697 /* Setup flooding PGIDs */
1698 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
1699 ANA_FLOODING_FLD_BROADCAST(PGID_MC) |
1700 ANA_FLOODING_FLD_UNICAST(PGID_UC),
1702 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
1703 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
1704 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
1705 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
1708 for (port = 0; port < ocelot->num_phys_ports; port++) {
1709 /* Transmit the frame to the local port. */
1710 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1711 /* Do not forward BPDU frames to the front ports. */
1712 ocelot_write_gix(ocelot,
1713 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
1714 ANA_PORT_CPU_FWD_BPDU_CFG,
1716 /* Ensure bridging is disabled */
1717 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
1720 /* Configure and enable the CPU port. */
1721 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
1722 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
1723 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
1724 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
1725 ANA_PORT_PORT_CFG, cpu);
1727 /* Allow broadcast MAC frames. */
1728 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) {
1729 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
1731 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
1733 ocelot_write_rix(ocelot,
1734 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
1735 ANA_PGID_PGID, PGID_MC);
1736 ocelot_write_rix(ocelot,
1737 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
1738 ANA_PGID_PGID, PGID_MCIPV4);
1739 ocelot_write_rix(ocelot,
1740 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
1741 ANA_PGID_PGID, PGID_MCIPV6);
1743 /* CPU port Injection/Extraction configuration */
1744 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
1745 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
1746 QSYS_SWITCH_PORT_MODE_PORT_ENA,
1747 QSYS_SWITCH_PORT_MODE, cpu);
1748 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) |
1749 SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu);
1750 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
1751 * registers endianness.
1753 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
1754 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
1755 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
1756 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
1757 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
1758 ANA_CPUQ_CFG_CPUQ_LRN(2) |
1759 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
1760 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
1761 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
1762 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
1763 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
1764 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
1765 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
1766 for (i = 0; i < 16; i++)
1767 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
1768 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
1769 ANA_CPUQ_8021_CFG, i);
1771 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats);
1772 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
1773 OCELOT_STATS_CHECK_DELAY);
1776 EXPORT_SYMBOL(ocelot_init);
1778 void ocelot_deinit(struct ocelot *ocelot)
1780 cancel_delayed_work(&ocelot->stats_work);
1781 destroy_workqueue(ocelot->stats_queue);
1782 mutex_destroy(&ocelot->stats_lock);
1784 EXPORT_SYMBOL(ocelot_deinit);
1786 MODULE_LICENSE("Dual MIT/GPL");