drivers/net/ethernet/moxa/moxart_ether.c

   1 /* MOXA ART Ethernet (RTL8201CP) driver.
   2  *
   3  * Copyright (C) 2013 Jonas Jensen
   4  *
   5  * Jonas Jensen <jonas.jensen@gmail.com>
   6  *
   7  * Based on code from
   8  * Moxa Technology Co., Ltd. <www.moxa.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/netdevice.h>
  17 #include <linux/etherdevice.h>
  18 #include <linux/skbuff.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/ethtool.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/crc32.h>
  27 #include <linux/crc32c.h>
  28 #include <linux/circ_buf.h>
  29
  30 #include "moxart_ether.h"
  31
  32 static inline void moxart_desc_write(u32 data, u32 *desc)
  33 {
  34         *desc = cpu_to_le32(data);
  35 }
  36
  37 static inline u32 moxart_desc_read(u32 *desc)
  38 {
  39         return le32_to_cpu(*desc);
  40 }
  41
  42 static inline void moxart_emac_write(struct net_device *ndev,
  43                                      unsigned int reg, unsigned long value)
  44 {
  45         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
  46
  47         writel(value, priv->base + reg);
  48 }
  49
  50 static void moxart_update_mac_address(struct net_device *ndev)
  51 {
  52         moxart_emac_write(ndev, REG_MAC_MS_ADDRESS,
  53                           ((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1])));
  54         moxart_emac_write(ndev, REG_MAC_MS_ADDRESS + 4,
  55                           ((ndev->dev_addr[2] << 24) |
  56                            (ndev->dev_addr[3] << 16) |
  57                            (ndev->dev_addr[4] << 8) |
  58                            (ndev->dev_addr[5])));
  59 }
  60
  61 static int moxart_set_mac_address(struct net_device *ndev, void *addr)
  62 {
  63         struct sockaddr *address = addr;
  64
  65         if (!is_valid_ether_addr(address->sa_data))
  66                 return -EADDRNOTAVAIL;
  67
  68         memcpy(ndev->dev_addr, address->sa_data, ndev->addr_len);
  69         moxart_update_mac_address(ndev);
  70
  71         return 0;
  72 }
  73
  74 static void moxart_mac_free_memory(struct net_device *ndev)
  75 {
  76         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
  77
  78         if (priv->tx_desc_base)
  79                 dma_free_coherent(&priv->pdev->dev,
  80                                   TX_REG_DESC_SIZE * TX_DESC_NUM,
  81                                   priv->tx_desc_base, priv->tx_base);
  82
  83         if (priv->rx_desc_base)
  84                 dma_free_coherent(&priv->pdev->dev,
  85                                   RX_REG_DESC_SIZE * RX_DESC_NUM,
  86                                   priv->rx_desc_base, priv->rx_base);
  87
  88         kfree(priv->tx_buf_base);
  89         kfree(priv->rx_buf_base);
  90 }
  91
  92 static void moxart_mac_reset(struct net_device *ndev)
  93 {
  94         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
  95
  96         writel(SW_RST, priv->base + REG_MAC_CTRL);
  97         while (readl(priv->base + REG_MAC_CTRL) & SW_RST)
  98                 mdelay(10);
  99
 100         writel(0, priv->base + REG_INTERRUPT_MASK);
 101
 102         priv->reg_maccr = RX_BROADPKT | FULLDUP | CRC_APD | RX_FTL;
 103 }
 104
 105 static void moxart_mac_enable(struct net_device *ndev)
 106 {
 107         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
 108
 109         writel(0x00001010, priv->base + REG_INT_TIMER_CTRL);
 110         writel(0x00000001, priv->base + REG_APOLL_TIMER_CTRL);
 111         writel(0x00000390, priv->base + REG_DMA_BLEN_CTRL);
 112
 113         priv->reg_imr |= (RPKT_FINISH_M | XPKT_FINISH_M);
 114         writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
 115
 116         priv->reg_maccr |= (RCV_EN | XMT_EN | RDMA_EN | XDMA_EN);
 117         writel(priv->reg_maccr, priv->base + REG_MAC_CTRL);
 118 }
 119
 120 static void moxart_mac_setup_desc_ring(struct net_device *ndev)
 121 {
 122         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
 123         void *desc;
 124         int i;
 125
 126         for (i = 0; i < TX_DESC_NUM; i++) {
 127                 desc = priv->tx_desc_base + i * TX_REG_DESC_SIZE;
 128                 memset(desc, 0, TX_REG_DESC_SIZE);
 129
 130                 priv->tx_buf[i] = priv->tx_buf_base + priv->tx_buf_size * i;
 131         }
 132         moxart_desc_write(TX_DESC1_END, desc + TX_REG_OFFSET_DESC1);
 133
 134         priv->tx_head = 0;
 135         priv->tx_tail = 0;
 136
 137         for (i = 0; i < RX_DESC_NUM; i++) {
 138                 desc = priv->rx_desc_base + i * RX_REG_DESC_SIZE;
 139                 memset(desc, 0, RX_REG_DESC_SIZE);
 140                 moxart_desc_write(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0);
 141                 moxart_desc_write(RX_BUF_SIZE & RX_DESC1_BUF_SIZE_MASK,
 142                        desc + RX_REG_OFFSET_DESC1);
 143
 144                 priv->rx_buf[i] = priv->rx_buf_base + priv->rx_buf_size * i;
 145                 priv->rx_mapping[i] = dma_map_single(&priv->pdev->dev,
 146                                                      priv->rx_buf[i],
 147                                                      priv->rx_buf_size,
 148                                                      DMA_FROM_DEVICE);
 149                 if (dma_mapping_error(&priv->pdev->dev, priv->rx_mapping[i]))
 150                         netdev_err(ndev, "DMA mapping error\n");
 151
 152                 moxart_desc_write(priv->rx_mapping[i],
 153                        desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_PHYS);
 154                 moxart_desc_write((uintptr_t)priv->rx_buf[i],
 155                        desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_VIRT);
 156         }
 157         moxart_desc_write(RX_DESC1_END, desc + RX_REG_OFFSET_DESC1);
 158
 159         priv->rx_head = 0;
 160
 161         /* reset the MAC controller TX/RX descriptor base address */
 162         writel(priv->tx_base, priv->base + REG_TXR_BASE_ADDRESS);
 163         writel(priv->rx_base, priv->base + REG_RXR_BASE_ADDRESS);
 164 }
 165
 166 static int moxart_mac_open(struct net_device *ndev)
 167 {
 168         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
 169
 170         if (!is_valid_ether_addr(ndev->dev_addr))
 171                 return -EADDRNOTAVAIL;
 172
 173         napi_enable(&priv->napi);
 174
 175         moxart_mac_reset(ndev);
 176         moxart_update_mac_address(ndev);
 177         moxart_mac_setup_desc_ring(ndev);
 178         moxart_mac_enable(ndev);
 179         netif_start_queue(ndev);
 180
 181         netdev_dbg(ndev, "%s: IMR=0x%x, MACCR=0x%x\n",
 182                    __func__, readl(priv->base + REG_INTERRUPT_MASK),
 183                    readl(priv->base + REG_MAC_CTRL));
 184
 185         return 0;
 186 }
 187
 188 static int moxart_mac_stop(struct net_device *ndev)
 189 {
 190         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
 191         int i;
 192
 193         napi_disable(&priv->napi);
 194
 195         netif_stop_queue(ndev);
 196
 197         /* disable all interrupts */
 198         writel(0, priv->base + REG_INTERRUPT_MASK);
 199
 200         /* disable all functions */
 201         writel(0, priv->base + REG_MAC_CTRL);
 202
 203         /* unmap areas mapped in moxart_mac_setup_desc_ring() */
 204         for (i = 0; i < RX_DESC_NUM; i++)
 205                 dma_unmap_single(&priv->pdev->dev, priv->rx_mapping[i],
 206                                  priv->rx_buf_size, DMA_FROM_DEVICE);
 207
 208         return 0;
 209 }
 210
 211 static int moxart_rx_poll(struct napi_struct *napi, int budget)
 212 {
 213         struct moxart_mac_priv_t *priv = container_of(napi,
 214                                                       struct moxart_mac_priv_t,
 215                                                       napi);
 216         struct net_device *ndev = priv->ndev;
 217         struct sk_buff *skb;
 218         void *desc;
 219         unsigned int desc0, len;
 220         int rx_head = priv->rx_head;
 221         int rx = 0;
 222
 223         while (rx < budget) {
 224                 desc = priv->rx_desc_base + (RX_REG_DESC_SIZE * rx_head);
 225                 desc0 = moxart_desc_read(desc + RX_REG_OFFSET_DESC0);
 226                 rmb(); /* ensure desc0 is up to date */
 227
 228                 if (desc0 & RX_DESC0_DMA_OWN)
 229                         break;
 230
 231                 if (desc0 & (RX_DESC0_ERR | RX_DESC0_CRC_ERR | RX_DESC0_FTL |
 232                              RX_DESC0_RUNT | RX_DESC0_ODD_NB)) {
 233                         net_dbg_ratelimited("packet error\n");
 234                         ndev->stats.rx_dropped++;
 235                         ndev->stats.rx_errors++;
 236                         goto rx_next;
 237                 }
 238
 239                 len = desc0 & RX_DESC0_FRAME_LEN_MASK;
 240
 241                 if (len > RX_BUF_SIZE)
 242                         len = RX_BUF_SIZE;
 243
 244                 dma_sync_single_for_cpu(&priv->pdev->dev,
 245                                         priv->rx_mapping[rx_head],
 246                                         priv->rx_buf_size, DMA_FROM_DEVICE);
 247                 skb = netdev_alloc_skb_ip_align(ndev, len);
 248
 249                 if (unlikely(!skb)) {
 250                         net_dbg_ratelimited("netdev_alloc_skb_ip_align failed\n");
 251                         ndev->stats.rx_dropped++;
 252                         ndev->stats.rx_errors++;
 253                         goto rx_next;
 254                 }
 255
 256                 memcpy(skb->data, priv->rx_buf[rx_head], len);
 257                 skb_put(skb, len);
 258                 skb->protocol = eth_type_trans(skb, ndev);
 259                 napi_gro_receive(&priv->napi, skb);
 260                 rx++;
 261
 262                 ndev->stats.rx_packets++;
 263                 ndev->stats.rx_bytes += len;
 264                 if (desc0 & RX_DESC0_MULTICAST)
 265                         ndev->stats.multicast++;
 266
 267 rx_next:
 268                 wmb(); /* prevent setting ownership back too early */
 269                 moxart_desc_write(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0);
 270
 271                 rx_head = RX_NEXT(rx_head);
 272                 priv->rx_head = rx_head;
 273         }
 274
 275         if (rx < budget)
 276                 napi_complete_done(napi, rx);
 277
 278         priv->reg_imr |= RPKT_FINISH_M;
 279         writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
 280
 281         return rx;
 282 }
 283
 284 static int moxart_tx_queue_space(struct net_device *ndev)
 285 {
 286         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
 287
 288         return CIRC_SPACE(priv->tx_head, priv->tx_tail, TX_DESC_NUM);
 289 }
 290
 291 static void moxart_tx_finished(struct net_device *ndev)
 292 {
 293         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
 294         unsigned int tx_head = priv->tx_head;
 295         unsigned int tx_tail = priv->tx_tail;
 296
 297         while (tx_tail != tx_head) {
 298                 dma_unmap_single(&priv->pdev->dev, priv->tx_mapping[tx_tail],
 299                                  priv->tx_len[tx_tail], DMA_TO_DEVICE);
 300
 301                 ndev->stats.tx_packets++;
 302                 ndev->stats.tx_bytes += priv->tx_skb[tx_tail]->len;
 303
 304                 dev_consume_skb_irq(priv->tx_skb[tx_tail]);
 305                 priv->tx_skb[tx_tail] = NULL;
 306
 307                 tx_tail = TX_NEXT(tx_tail);
 308         }
 309         priv->tx_tail = tx_tail;
 310         if (netif_queue_stopped(ndev) &&
 311             moxart_tx_queue_space(ndev) >= TX_WAKE_THRESHOLD)
 312                 netif_wake_queue(ndev);
 313 }
 314
 315 static irqreturn_t moxart_mac_interrupt(int irq, void *dev_id)
 316 {
 317         struct net_device *ndev = (struct net_device *)dev_id;
 318         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
 319         unsigned int ists = readl(priv->base + REG_INTERRUPT_STATUS);
 320
 321         if (ists & XPKT_OK_INT_STS)
 322                 moxart_tx_finished(ndev);
 323
 324         if (ists & RPKT_FINISH) {
 325                 if (napi_schedule_prep(&priv->napi)) {
 326                         priv->reg_imr &= ~RPKT_FINISH_M;
 327                         writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
 328                         __napi_schedule(&priv->napi);
 329                 }
 330         }
 331
 332         return IRQ_HANDLED;
 333 }
 334
 335 static netdev_tx_t moxart_mac_start_xmit(struct sk_buff *skb,
 336                                          struct net_device *ndev)
 337 {
 338         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
 339         void *desc;
 340         unsigned int len;
 341         unsigned int tx_head;
 342         u32 txdes1;
 343         netdev_tx_t ret = NETDEV_TX_BUSY;
 344
 345         spin_lock_irq(&priv->txlock);
 346
 347         tx_head = priv->tx_head;
 348         desc = priv->tx_desc_base + (TX_REG_DESC_SIZE * tx_head);
 349
 350         if (moxart_tx_queue_space(ndev) == 1)
 351                 netif_stop_queue(ndev);
 352
 353         if (moxart_desc_read(desc + TX_REG_OFFSET_DESC0) & TX_DESC0_DMA_OWN) {
 354                 net_dbg_ratelimited("no TX space for packet\n");
 355                 ndev->stats.tx_dropped++;
 356                 goto out_unlock;
 357         }
 358         rmb(); /* ensure data is only read that had TX_DESC0_DMA_OWN cleared */
 359
 360         len = skb->len > TX_BUF_SIZE ? TX_BUF_SIZE : skb->len;
 361
 362         priv->tx_mapping[tx_head] = dma_map_single(&priv->pdev->dev, skb->data,
 363                                                    len, DMA_TO_DEVICE);
 364         if (dma_mapping_error(&priv->pdev->dev, priv->tx_mapping[tx_head])) {
 365                 netdev_err(ndev, "DMA mapping error\n");
 366                 goto out_unlock;
 367         }
 368
 369         priv->tx_len[tx_head] = len;
 370         priv->tx_skb[tx_head] = skb;
 371
 372         moxart_desc_write(priv->tx_mapping[tx_head],
 373                desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_PHYS);
 374         moxart_desc_write((uintptr_t)skb->data,
 375                desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_VIRT);
 376
 377         if (skb->len < ETH_ZLEN) {
 378                 memset(&skb->data[skb->len],
 379                        0, ETH_ZLEN - skb->len);
 380                 len = ETH_ZLEN;
 381         }
 382
 383         dma_sync_single_for_device(&priv->pdev->dev, priv->tx_mapping[tx_head],
 384                                    priv->tx_buf_size, DMA_TO_DEVICE);
 385
 386         txdes1 = TX_DESC1_LTS | TX_DESC1_FTS | (len & TX_DESC1_BUF_SIZE_MASK);
 387         if (tx_head == TX_DESC_NUM_MASK)
 388                 txdes1 |= TX_DESC1_END;
 389         moxart_desc_write(txdes1, desc + TX_REG_OFFSET_DESC1);
 390         wmb(); /* flush descriptor before transferring ownership */
 391         moxart_desc_write(TX_DESC0_DMA_OWN, desc + TX_REG_OFFSET_DESC0);
 392
 393         /* start to send packet */
 394         writel(0xffffffff, priv->base + REG_TX_POLL_DEMAND);
 395
 396         priv->tx_head = TX_NEXT(tx_head);
 397
 398         netif_trans_update(ndev);
 399         ret = NETDEV_TX_OK;
 400 out_unlock:
 401         spin_unlock_irq(&priv->txlock);
 402
 403         return ret;
 404 }
 405
 406 static void moxart_mac_setmulticast(struct net_device *ndev)
 407 {
 408         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
 409         struct netdev_hw_addr *ha;
 410         int crc_val;
 411
 412         netdev_for_each_mc_addr(ha, ndev) {
 413                 crc_val = crc32_le(~0, ha->addr, ETH_ALEN);
 414                 crc_val = (crc_val >> 26) & 0x3f;
 415                 if (crc_val >= 32) {
 416                         writel(readl(priv->base + REG_MCAST_HASH_TABLE1) |
 417                                (1UL << (crc_val - 32)),
 418                                priv->base + REG_MCAST_HASH_TABLE1);
 419                 } else {
 420                         writel(readl(priv->base + REG_MCAST_HASH_TABLE0) |
 421                                (1UL << crc_val),
 422                                priv->base + REG_MCAST_HASH_TABLE0);
 423                 }
 424         }
 425 }
 426
 427 static void moxart_mac_set_rx_mode(struct net_device *ndev)
 428 {
 429         struct moxart_mac_priv_t *priv = netdev_priv(ndev);
 430
 431         spin_lock_irq(&priv->txlock);
 432
 433         (ndev->flags & IFF_PROMISC) ? (priv->reg_maccr |= RCV_ALL) :
 434                                       (priv->reg_maccr &= ~RCV_ALL);
 435
 436         (ndev->flags & IFF_ALLMULTI) ? (priv->reg_maccr |= RX_MULTIPKT) :
 437                                        (priv->reg_maccr &= ~RX_MULTIPKT);
 438
 439         if ((ndev->flags & IFF_MULTICAST) && netdev_mc_count(ndev)) {
 440                 priv->reg_maccr |= HT_MULTI_EN;
 441                 moxart_mac_setmulticast(ndev);
 442         } else {
 443                 priv->reg_maccr &= ~HT_MULTI_EN;
 444         }
 445
 446         writel(priv->reg_maccr, priv->base + REG_MAC_CTRL);
 447
 448         spin_unlock_irq(&priv->txlock);
 449 }
 450
 451 static const struct net_device_ops moxart_netdev_ops = {
 452         .ndo_open               = moxart_mac_open,
 453         .ndo_stop               = moxart_mac_stop,
 454         .ndo_start_xmit         = moxart_mac_start_xmit,
 455         .ndo_set_rx_mode        = moxart_mac_set_rx_mode,
 456         .ndo_set_mac_address    = moxart_set_mac_address,
 457         .ndo_validate_addr      = eth_validate_addr,
 458 };
 459
 460 static int moxart_mac_probe(struct platform_device *pdev)
 461 {
 462         struct device *p_dev = &pdev->dev;
 463         struct device_node *node = p_dev->of_node;
 464         struct net_device *ndev;
 465         struct moxart_mac_priv_t *priv;
 466         struct resource *res;
 467         unsigned int irq;
 468         int ret;
 469
 470         ndev = alloc_etherdev(sizeof(struct moxart_mac_priv_t));
 471         if (!ndev)
 472                 return -ENOMEM;
 473
 474         irq = irq_of_parse_and_map(node, 0);
 475         if (irq <= 0) {
 476                 netdev_err(ndev, "irq_of_parse_and_map failed\n");
 477                 ret = -EINVAL;
 478                 goto irq_map_fail;
 479         }
 480
 481         priv = netdev_priv(ndev);
 482         priv->ndev = ndev;
 483         priv->pdev = pdev;
 484
 485         priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 486         if (IS_ERR(priv->base)) {
 487                 dev_err(p_dev, "devm_ioremap_resource failed\n");
 488                 ret = PTR_ERR(priv->base);
 489                 goto init_fail;
 490         }
 491         ndev->base_addr = res->start;
 492
 493         spin_lock_init(&priv->txlock);
 494
 495         priv->tx_buf_size = TX_BUF_SIZE;
 496         priv->rx_buf_size = RX_BUF_SIZE;
 497
 498         priv->tx_desc_base = dma_alloc_coherent(p_dev, TX_REG_DESC_SIZE *
 499                                                 TX_DESC_NUM, &priv->tx_base,
 500                                                 GFP_DMA | GFP_KERNEL);
 501         if (!priv->tx_desc_base) {
 502                 ret = -ENOMEM;
 503                 goto init_fail;
 504         }
 505
 506         priv->rx_desc_base = dma_alloc_coherent(p_dev, RX_REG_DESC_SIZE *
 507                                                 RX_DESC_NUM, &priv->rx_base,
 508                                                 GFP_DMA | GFP_KERNEL);
 509         if (!priv->rx_desc_base) {
 510                 ret = -ENOMEM;
 511                 goto init_fail;
 512         }
 513
 514         priv->tx_buf_base = kmalloc_array(priv->tx_buf_size, TX_DESC_NUM,
 515                                           GFP_ATOMIC);
 516         if (!priv->tx_buf_base) {
 517                 ret = -ENOMEM;
 518                 goto init_fail;
 519         }
 520
 521         priv->rx_buf_base = kmalloc_array(priv->rx_buf_size, RX_DESC_NUM,
 522                                           GFP_ATOMIC);
 523         if (!priv->rx_buf_base) {
 524                 ret = -ENOMEM;
 525                 goto init_fail;
 526         }
 527
 528         platform_set_drvdata(pdev, ndev);
 529
 530         ret = devm_request_irq(p_dev, irq, moxart_mac_interrupt, 0,
 531                                pdev->name, ndev);
 532         if (ret) {
 533                 netdev_err(ndev, "devm_request_irq failed\n");
 534                 goto init_fail;
 535         }
 536
 537         ndev->netdev_ops = &moxart_netdev_ops;
 538         netif_napi_add(ndev, &priv->napi, moxart_rx_poll, RX_DESC_NUM);
 539         ndev->priv_flags |= IFF_UNICAST_FLT;
 540         ndev->irq = irq;
 541
 542         SET_NETDEV_DEV(ndev, &pdev->dev);
 543
 544         ret = register_netdev(ndev);
 545         if (ret)
 546                 goto init_fail;
 547
 548         netdev_dbg(ndev, "%s: IRQ=%d address=%pM\n",
 549                    __func__, ndev->irq, ndev->dev_addr);
 550
 551         return 0;
 552
 553 init_fail:
 554         netdev_err(ndev, "init failed\n");
 555         moxart_mac_free_memory(ndev);
 556 irq_map_fail:
 557         free_netdev(ndev);
 558         return ret;
 559 }
 560
 561 static int moxart_remove(struct platform_device *pdev)
 562 {
 563         struct net_device *ndev = platform_get_drvdata(pdev);
 564
 565         unregister_netdev(ndev);
 566         devm_free_irq(&pdev->dev, ndev->irq, ndev);
 567         moxart_mac_free_memory(ndev);
 568         free_netdev(ndev);
 569
 570         return 0;
 571 }
 572
 573 static const struct of_device_id moxart_mac_match[] = {
 574         { .compatible = "moxa,moxart-mac" },
 575         { }
 576 };
 577 MODULE_DEVICE_TABLE(of, moxart_mac_match);
 578
 579 static struct platform_driver moxart_mac_driver = {
 580         .probe  = moxart_mac_probe,
 581         .remove = moxart_remove,
 582         .driver = {
 583                 .name           = "moxart-ethernet",
 584                 .of_match_table = moxart_mac_match,
 585         },
 586 };
 587 module_platform_driver(moxart_mac_driver);
 588
 589 MODULE_DESCRIPTION("MOXART RTL8201CP Ethernet driver");
 590 MODULE_LICENSE("GPL v2");
 591 MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");