2 * drivers/net/ethernet/micrel/ksx884x.c - Micrel KSZ8841/2 PCI Ethernet driver
4 * Copyright (c) 2009-2010 Micrel, Inc.
5 * Tristram Ha <Tristram.Ha@micrel.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/ioport.h>
24 #include <linux/pci.h>
25 #include <linux/proc_fs.h>
26 #include <linux/mii.h>
27 #include <linux/platform_device.h>
28 #include <linux/ethtool.h>
29 #include <linux/etherdevice.h>
32 #include <linux/if_vlan.h>
33 #include <linux/crc32.h>
34 #include <linux/sched.h>
35 #include <linux/slab.h>
40 #define KS_DMA_TX_CTRL 0x0000
41 #define DMA_TX_ENABLE 0x00000001
42 #define DMA_TX_CRC_ENABLE 0x00000002
43 #define DMA_TX_PAD_ENABLE 0x00000004
44 #define DMA_TX_LOOPBACK 0x00000100
45 #define DMA_TX_FLOW_ENABLE 0x00000200
46 #define DMA_TX_CSUM_IP 0x00010000
47 #define DMA_TX_CSUM_TCP 0x00020000
48 #define DMA_TX_CSUM_UDP 0x00040000
49 #define DMA_TX_BURST_SIZE 0x3F000000
51 #define KS_DMA_RX_CTRL 0x0004
52 #define DMA_RX_ENABLE 0x00000001
53 #define KS884X_DMA_RX_MULTICAST 0x00000002
54 #define DMA_RX_PROMISCUOUS 0x00000004
55 #define DMA_RX_ERROR 0x00000008
56 #define DMA_RX_UNICAST 0x00000010
57 #define DMA_RX_ALL_MULTICAST 0x00000020
58 #define DMA_RX_BROADCAST 0x00000040
59 #define DMA_RX_FLOW_ENABLE 0x00000200
60 #define DMA_RX_CSUM_IP 0x00010000
61 #define DMA_RX_CSUM_TCP 0x00020000
62 #define DMA_RX_CSUM_UDP 0x00040000
63 #define DMA_RX_BURST_SIZE 0x3F000000
65 #define DMA_BURST_SHIFT 24
66 #define DMA_BURST_DEFAULT 8
68 #define KS_DMA_TX_START 0x0008
69 #define KS_DMA_RX_START 0x000C
70 #define DMA_START 0x00000001
72 #define KS_DMA_TX_ADDR 0x0010
73 #define KS_DMA_RX_ADDR 0x0014
75 #define DMA_ADDR_LIST_MASK 0xFFFFFFFC
76 #define DMA_ADDR_LIST_SHIFT 2
79 #define KS884X_MULTICAST_0_OFFSET 0x0020
80 #define KS884X_MULTICAST_1_OFFSET 0x0021
81 #define KS884X_MULTICAST_2_OFFSET 0x0022
82 #define KS884x_MULTICAST_3_OFFSET 0x0023
84 #define KS884X_MULTICAST_4_OFFSET 0x0024
85 #define KS884X_MULTICAST_5_OFFSET 0x0025
86 #define KS884X_MULTICAST_6_OFFSET 0x0026
87 #define KS884X_MULTICAST_7_OFFSET 0x0027
89 /* Interrupt Registers */
92 #define KS884X_INTERRUPTS_ENABLE 0x0028
94 #define KS884X_INTERRUPTS_STATUS 0x002C
96 #define KS884X_INT_RX_STOPPED 0x02000000
97 #define KS884X_INT_TX_STOPPED 0x04000000
98 #define KS884X_INT_RX_OVERRUN 0x08000000
99 #define KS884X_INT_TX_EMPTY 0x10000000
100 #define KS884X_INT_RX 0x20000000
101 #define KS884X_INT_TX 0x40000000
102 #define KS884X_INT_PHY 0x80000000
104 #define KS884X_INT_RX_MASK \
105 (KS884X_INT_RX | KS884X_INT_RX_OVERRUN)
106 #define KS884X_INT_TX_MASK \
107 (KS884X_INT_TX | KS884X_INT_TX_EMPTY)
108 #define KS884X_INT_MASK (KS884X_INT_RX | KS884X_INT_TX | KS884X_INT_PHY)
110 /* MAC Additional Station Address */
113 #define KS_ADD_ADDR_0_LO 0x0080
115 #define KS_ADD_ADDR_0_HI 0x0084
117 #define KS_ADD_ADDR_1_LO 0x0088
119 #define KS_ADD_ADDR_1_HI 0x008C
121 #define KS_ADD_ADDR_2_LO 0x0090
123 #define KS_ADD_ADDR_2_HI 0x0094
125 #define KS_ADD_ADDR_3_LO 0x0098
127 #define KS_ADD_ADDR_3_HI 0x009C
129 #define KS_ADD_ADDR_4_LO 0x00A0
131 #define KS_ADD_ADDR_4_HI 0x00A4
133 #define KS_ADD_ADDR_5_LO 0x00A8
135 #define KS_ADD_ADDR_5_HI 0x00AC
137 #define KS_ADD_ADDR_6_LO 0x00B0
139 #define KS_ADD_ADDR_6_HI 0x00B4
141 #define KS_ADD_ADDR_7_LO 0x00B8
143 #define KS_ADD_ADDR_7_HI 0x00BC
145 #define KS_ADD_ADDR_8_LO 0x00C0
147 #define KS_ADD_ADDR_8_HI 0x00C4
149 #define KS_ADD_ADDR_9_LO 0x00C8
151 #define KS_ADD_ADDR_9_HI 0x00CC
153 #define KS_ADD_ADDR_A_LO 0x00D0
155 #define KS_ADD_ADDR_A_HI 0x00D4
157 #define KS_ADD_ADDR_B_LO 0x00D8
159 #define KS_ADD_ADDR_B_HI 0x00DC
161 #define KS_ADD_ADDR_C_LO 0x00E0
163 #define KS_ADD_ADDR_C_HI 0x00E4
165 #define KS_ADD_ADDR_D_LO 0x00E8
167 #define KS_ADD_ADDR_D_HI 0x00EC
169 #define KS_ADD_ADDR_E_LO 0x00F0
171 #define KS_ADD_ADDR_E_HI 0x00F4
173 #define KS_ADD_ADDR_F_LO 0x00F8
175 #define KS_ADD_ADDR_F_HI 0x00FC
177 #define ADD_ADDR_HI_MASK 0x0000FFFF
178 #define ADD_ADDR_ENABLE 0x80000000
179 #define ADD_ADDR_INCR 8
181 /* Miscellaneous Registers */
184 #define KS884X_ADDR_0_OFFSET 0x0200
185 #define KS884X_ADDR_1_OFFSET 0x0201
187 #define KS884X_ADDR_2_OFFSET 0x0202
188 #define KS884X_ADDR_3_OFFSET 0x0203
190 #define KS884X_ADDR_4_OFFSET 0x0204
191 #define KS884X_ADDR_5_OFFSET 0x0205
194 #define KS884X_BUS_CTRL_OFFSET 0x0210
196 #define BUS_SPEED_125_MHZ 0x0000
197 #define BUS_SPEED_62_5_MHZ 0x0001
198 #define BUS_SPEED_41_66_MHZ 0x0002
199 #define BUS_SPEED_25_MHZ 0x0003
202 #define KS884X_EEPROM_CTRL_OFFSET 0x0212
204 #define EEPROM_CHIP_SELECT 0x0001
205 #define EEPROM_SERIAL_CLOCK 0x0002
206 #define EEPROM_DATA_OUT 0x0004
207 #define EEPROM_DATA_IN 0x0008
208 #define EEPROM_ACCESS_ENABLE 0x0010
211 #define KS884X_MEM_INFO_OFFSET 0x0214
213 #define RX_MEM_TEST_FAILED 0x0008
214 #define RX_MEM_TEST_FINISHED 0x0010
215 #define TX_MEM_TEST_FAILED 0x0800
216 #define TX_MEM_TEST_FINISHED 0x1000
219 #define KS884X_GLOBAL_CTRL_OFFSET 0x0216
220 #define GLOBAL_SOFTWARE_RESET 0x0001
222 #define KS8841_POWER_MANAGE_OFFSET 0x0218
225 #define KS8841_WOL_CTRL_OFFSET 0x021A
226 #define KS8841_WOL_MAGIC_ENABLE 0x0080
227 #define KS8841_WOL_FRAME3_ENABLE 0x0008
228 #define KS8841_WOL_FRAME2_ENABLE 0x0004
229 #define KS8841_WOL_FRAME1_ENABLE 0x0002
230 #define KS8841_WOL_FRAME0_ENABLE 0x0001
233 #define KS8841_WOL_FRAME_CRC_OFFSET 0x0220
234 #define KS8841_WOL_FRAME_BYTE0_OFFSET 0x0224
235 #define KS8841_WOL_FRAME_BYTE2_OFFSET 0x0228
238 #define KS884X_IACR_P 0x04A0
239 #define KS884X_IACR_OFFSET KS884X_IACR_P
242 #define KS884X_IADR1_P 0x04A2
243 #define KS884X_IADR2_P 0x04A4
244 #define KS884X_IADR3_P 0x04A6
245 #define KS884X_IADR4_P 0x04A8
246 #define KS884X_IADR5_P 0x04AA
248 #define KS884X_ACC_CTRL_SEL_OFFSET KS884X_IACR_P
249 #define KS884X_ACC_CTRL_INDEX_OFFSET (KS884X_ACC_CTRL_SEL_OFFSET + 1)
251 #define KS884X_ACC_DATA_0_OFFSET KS884X_IADR4_P
252 #define KS884X_ACC_DATA_1_OFFSET (KS884X_ACC_DATA_0_OFFSET + 1)
253 #define KS884X_ACC_DATA_2_OFFSET KS884X_IADR5_P
254 #define KS884X_ACC_DATA_3_OFFSET (KS884X_ACC_DATA_2_OFFSET + 1)
255 #define KS884X_ACC_DATA_4_OFFSET KS884X_IADR2_P
256 #define KS884X_ACC_DATA_5_OFFSET (KS884X_ACC_DATA_4_OFFSET + 1)
257 #define KS884X_ACC_DATA_6_OFFSET KS884X_IADR3_P
258 #define KS884X_ACC_DATA_7_OFFSET (KS884X_ACC_DATA_6_OFFSET + 1)
259 #define KS884X_ACC_DATA_8_OFFSET KS884X_IADR1_P
262 #define KS884X_P1MBCR_P 0x04D0
263 #define KS884X_P1MBSR_P 0x04D2
264 #define KS884X_PHY1ILR_P 0x04D4
265 #define KS884X_PHY1IHR_P 0x04D6
266 #define KS884X_P1ANAR_P 0x04D8
267 #define KS884X_P1ANLPR_P 0x04DA
270 #define KS884X_P2MBCR_P 0x04E0
271 #define KS884X_P2MBSR_P 0x04E2
272 #define KS884X_PHY2ILR_P 0x04E4
273 #define KS884X_PHY2IHR_P 0x04E6
274 #define KS884X_P2ANAR_P 0x04E8
275 #define KS884X_P2ANLPR_P 0x04EA
277 #define KS884X_PHY_1_CTRL_OFFSET KS884X_P1MBCR_P
278 #define PHY_CTRL_INTERVAL (KS884X_P2MBCR_P - KS884X_P1MBCR_P)
280 #define KS884X_PHY_CTRL_OFFSET 0x00
282 /* Mode Control Register */
283 #define PHY_REG_CTRL 0
285 #define PHY_RESET 0x8000
286 #define PHY_LOOPBACK 0x4000
287 #define PHY_SPEED_100MBIT 0x2000
288 #define PHY_AUTO_NEG_ENABLE 0x1000
289 #define PHY_POWER_DOWN 0x0800
290 #define PHY_MII_DISABLE 0x0400
291 #define PHY_AUTO_NEG_RESTART 0x0200
292 #define PHY_FULL_DUPLEX 0x0100
293 #define PHY_COLLISION_TEST 0x0080
294 #define PHY_HP_MDIX 0x0020
295 #define PHY_FORCE_MDIX 0x0010
296 #define PHY_AUTO_MDIX_DISABLE 0x0008
297 #define PHY_REMOTE_FAULT_DISABLE 0x0004
298 #define PHY_TRANSMIT_DISABLE 0x0002
299 #define PHY_LED_DISABLE 0x0001
301 #define KS884X_PHY_STATUS_OFFSET 0x02
303 /* Mode Status Register */
304 #define PHY_REG_STATUS 1
306 #define PHY_100BT4_CAPABLE 0x8000
307 #define PHY_100BTX_FD_CAPABLE 0x4000
308 #define PHY_100BTX_CAPABLE 0x2000
309 #define PHY_10BT_FD_CAPABLE 0x1000
310 #define PHY_10BT_CAPABLE 0x0800
311 #define PHY_MII_SUPPRESS_CAPABLE 0x0040
312 #define PHY_AUTO_NEG_ACKNOWLEDGE 0x0020
313 #define PHY_REMOTE_FAULT 0x0010
314 #define PHY_AUTO_NEG_CAPABLE 0x0008
315 #define PHY_LINK_STATUS 0x0004
316 #define PHY_JABBER_DETECT 0x0002
317 #define PHY_EXTENDED_CAPABILITY 0x0001
319 #define KS884X_PHY_ID_1_OFFSET 0x04
320 #define KS884X_PHY_ID_2_OFFSET 0x06
322 /* PHY Identifier Registers */
323 #define PHY_REG_ID_1 2
324 #define PHY_REG_ID_2 3
326 #define KS884X_PHY_AUTO_NEG_OFFSET 0x08
328 /* Auto-Negotiation Advertisement Register */
329 #define PHY_REG_AUTO_NEGOTIATION 4
331 #define PHY_AUTO_NEG_NEXT_PAGE 0x8000
332 #define PHY_AUTO_NEG_REMOTE_FAULT 0x2000
334 #define PHY_AUTO_NEG_ASYM_PAUSE 0x0800
335 #define PHY_AUTO_NEG_SYM_PAUSE 0x0400
336 #define PHY_AUTO_NEG_100BT4 0x0200
337 #define PHY_AUTO_NEG_100BTX_FD 0x0100
338 #define PHY_AUTO_NEG_100BTX 0x0080
339 #define PHY_AUTO_NEG_10BT_FD 0x0040
340 #define PHY_AUTO_NEG_10BT 0x0020
341 #define PHY_AUTO_NEG_SELECTOR 0x001F
342 #define PHY_AUTO_NEG_802_3 0x0001
344 #define PHY_AUTO_NEG_PAUSE (PHY_AUTO_NEG_SYM_PAUSE | PHY_AUTO_NEG_ASYM_PAUSE)
346 #define KS884X_PHY_REMOTE_CAP_OFFSET 0x0A
348 /* Auto-Negotiation Link Partner Ability Register */
349 #define PHY_REG_REMOTE_CAPABILITY 5
351 #define PHY_REMOTE_NEXT_PAGE 0x8000
352 #define PHY_REMOTE_ACKNOWLEDGE 0x4000
353 #define PHY_REMOTE_REMOTE_FAULT 0x2000
354 #define PHY_REMOTE_SYM_PAUSE 0x0400
355 #define PHY_REMOTE_100BTX_FD 0x0100
356 #define PHY_REMOTE_100BTX 0x0080
357 #define PHY_REMOTE_10BT_FD 0x0040
358 #define PHY_REMOTE_10BT 0x0020
361 #define KS884X_P1VCT_P 0x04F0
362 #define KS884X_P1PHYCTRL_P 0x04F2
365 #define KS884X_P2VCT_P 0x04F4
366 #define KS884X_P2PHYCTRL_P 0x04F6
368 #define KS884X_PHY_SPECIAL_OFFSET KS884X_P1VCT_P
369 #define PHY_SPECIAL_INTERVAL (KS884X_P2VCT_P - KS884X_P1VCT_P)
371 #define KS884X_PHY_LINK_MD_OFFSET 0x00
373 #define PHY_START_CABLE_DIAG 0x8000
374 #define PHY_CABLE_DIAG_RESULT 0x6000
375 #define PHY_CABLE_STAT_NORMAL 0x0000
376 #define PHY_CABLE_STAT_OPEN 0x2000
377 #define PHY_CABLE_STAT_SHORT 0x4000
378 #define PHY_CABLE_STAT_FAILED 0x6000
379 #define PHY_CABLE_10M_SHORT 0x1000
380 #define PHY_CABLE_FAULT_COUNTER 0x01FF
382 #define KS884X_PHY_PHY_CTRL_OFFSET 0x02
384 #define PHY_STAT_REVERSED_POLARITY 0x0020
385 #define PHY_STAT_MDIX 0x0010
386 #define PHY_FORCE_LINK 0x0008
387 #define PHY_POWER_SAVING_DISABLE 0x0004
388 #define PHY_REMOTE_LOOPBACK 0x0002
391 #define KS884X_SIDER_P 0x0400
392 #define KS884X_CHIP_ID_OFFSET KS884X_SIDER_P
393 #define KS884X_FAMILY_ID_OFFSET (KS884X_CHIP_ID_OFFSET + 1)
395 #define REG_FAMILY_ID 0x88
397 #define REG_CHIP_ID_41 0x8810
398 #define REG_CHIP_ID_42 0x8800
400 #define KS884X_CHIP_ID_MASK_41 0xFF10
401 #define KS884X_CHIP_ID_MASK 0xFFF0
402 #define KS884X_CHIP_ID_SHIFT 4
403 #define KS884X_REVISION_MASK 0x000E
404 #define KS884X_REVISION_SHIFT 1
405 #define KS8842_START 0x0001
407 #define CHIP_IP_41_M 0x8810
408 #define CHIP_IP_42_M 0x8800
409 #define CHIP_IP_61_M 0x8890
410 #define CHIP_IP_62_M 0x8880
412 #define CHIP_IP_41_P 0x8850
413 #define CHIP_IP_42_P 0x8840
414 #define CHIP_IP_61_P 0x88D0
415 #define CHIP_IP_62_P 0x88C0
418 #define KS8842_SGCR1_P 0x0402
419 #define KS8842_SWITCH_CTRL_1_OFFSET KS8842_SGCR1_P
421 #define SWITCH_PASS_ALL 0x8000
422 #define SWITCH_TX_FLOW_CTRL 0x2000
423 #define SWITCH_RX_FLOW_CTRL 0x1000
424 #define SWITCH_CHECK_LENGTH 0x0800
425 #define SWITCH_AGING_ENABLE 0x0400
426 #define SWITCH_FAST_AGING 0x0200
427 #define SWITCH_AGGR_BACKOFF 0x0100
428 #define SWITCH_PASS_PAUSE 0x0008
429 #define SWITCH_LINK_AUTO_AGING 0x0001
432 #define KS8842_SGCR2_P 0x0404
433 #define KS8842_SWITCH_CTRL_2_OFFSET KS8842_SGCR2_P
435 #define SWITCH_VLAN_ENABLE 0x8000
436 #define SWITCH_IGMP_SNOOP 0x4000
437 #define IPV6_MLD_SNOOP_ENABLE 0x2000
438 #define IPV6_MLD_SNOOP_OPTION 0x1000
439 #define PRIORITY_SCHEME_SELECT 0x0800
440 #define SWITCH_MIRROR_RX_TX 0x0100
441 #define UNICAST_VLAN_BOUNDARY 0x0080
442 #define MULTICAST_STORM_DISABLE 0x0040
443 #define SWITCH_BACK_PRESSURE 0x0020
444 #define FAIR_FLOW_CTRL 0x0010
445 #define NO_EXC_COLLISION_DROP 0x0008
446 #define SWITCH_HUGE_PACKET 0x0004
447 #define SWITCH_LEGAL_PACKET 0x0002
448 #define SWITCH_BUF_RESERVE 0x0001
451 #define KS8842_SGCR3_P 0x0406
452 #define KS8842_SWITCH_CTRL_3_OFFSET KS8842_SGCR3_P
454 #define BROADCAST_STORM_RATE_LO 0xFF00
455 #define SWITCH_REPEATER 0x0080
456 #define SWITCH_HALF_DUPLEX 0x0040
457 #define SWITCH_FLOW_CTRL 0x0020
458 #define SWITCH_10_MBIT 0x0010
459 #define SWITCH_REPLACE_NULL_VID 0x0008
460 #define BROADCAST_STORM_RATE_HI 0x0007
462 #define BROADCAST_STORM_RATE 0x07FF
465 #define KS8842_SGCR4_P 0x0408
468 #define KS8842_SGCR5_P 0x040A
469 #define KS8842_SWITCH_CTRL_5_OFFSET KS8842_SGCR5_P
471 #define LED_MODE 0x8200
472 #define LED_SPEED_DUPLEX_ACT 0x0000
473 #define LED_SPEED_DUPLEX_LINK_ACT 0x8000
474 #define LED_DUPLEX_10_100 0x0200
477 #define KS8842_SGCR6_P 0x0410
478 #define KS8842_SWITCH_CTRL_6_OFFSET KS8842_SGCR6_P
480 #define KS8842_PRIORITY_MASK 3
481 #define KS8842_PRIORITY_SHIFT 2
484 #define KS8842_SGCR7_P 0x0412
485 #define KS8842_SWITCH_CTRL_7_OFFSET KS8842_SGCR7_P
487 #define SWITCH_UNK_DEF_PORT_ENABLE 0x0008
488 #define SWITCH_UNK_DEF_PORT_3 0x0004
489 #define SWITCH_UNK_DEF_PORT_2 0x0002
490 #define SWITCH_UNK_DEF_PORT_1 0x0001
493 #define KS8842_MACAR1_P 0x0470
494 #define KS8842_MACAR2_P 0x0472
495 #define KS8842_MACAR3_P 0x0474
496 #define KS8842_MAC_ADDR_1_OFFSET KS8842_MACAR1_P
497 #define KS8842_MAC_ADDR_0_OFFSET (KS8842_MAC_ADDR_1_OFFSET + 1)
498 #define KS8842_MAC_ADDR_3_OFFSET KS8842_MACAR2_P
499 #define KS8842_MAC_ADDR_2_OFFSET (KS8842_MAC_ADDR_3_OFFSET + 1)
500 #define KS8842_MAC_ADDR_5_OFFSET KS8842_MACAR3_P
501 #define KS8842_MAC_ADDR_4_OFFSET (KS8842_MAC_ADDR_5_OFFSET + 1)
504 #define KS8842_TOSR1_P 0x0480
505 #define KS8842_TOSR2_P 0x0482
506 #define KS8842_TOSR3_P 0x0484
507 #define KS8842_TOSR4_P 0x0486
508 #define KS8842_TOSR5_P 0x0488
509 #define KS8842_TOSR6_P 0x048A
510 #define KS8842_TOSR7_P 0x0490
511 #define KS8842_TOSR8_P 0x0492
512 #define KS8842_TOS_1_OFFSET KS8842_TOSR1_P
513 #define KS8842_TOS_2_OFFSET KS8842_TOSR2_P
514 #define KS8842_TOS_3_OFFSET KS8842_TOSR3_P
515 #define KS8842_TOS_4_OFFSET KS8842_TOSR4_P
516 #define KS8842_TOS_5_OFFSET KS8842_TOSR5_P
517 #define KS8842_TOS_6_OFFSET KS8842_TOSR6_P
519 #define KS8842_TOS_7_OFFSET KS8842_TOSR7_P
520 #define KS8842_TOS_8_OFFSET KS8842_TOSR8_P
523 #define KS8842_P1CR1_P 0x0500
524 #define KS8842_P1CR2_P 0x0502
525 #define KS8842_P1VIDR_P 0x0504
526 #define KS8842_P1CR3_P 0x0506
527 #define KS8842_P1IRCR_P 0x0508
528 #define KS8842_P1ERCR_P 0x050A
529 #define KS884X_P1SCSLMD_P 0x0510
530 #define KS884X_P1CR4_P 0x0512
531 #define KS884X_P1SR_P 0x0514
534 #define KS8842_P2CR1_P 0x0520
535 #define KS8842_P2CR2_P 0x0522
536 #define KS8842_P2VIDR_P 0x0524
537 #define KS8842_P2CR3_P 0x0526
538 #define KS8842_P2IRCR_P 0x0528
539 #define KS8842_P2ERCR_P 0x052A
540 #define KS884X_P2SCSLMD_P 0x0530
541 #define KS884X_P2CR4_P 0x0532
542 #define KS884X_P2SR_P 0x0534
545 #define KS8842_P3CR1_P 0x0540
546 #define KS8842_P3CR2_P 0x0542
547 #define KS8842_P3VIDR_P 0x0544
548 #define KS8842_P3CR3_P 0x0546
549 #define KS8842_P3IRCR_P 0x0548
550 #define KS8842_P3ERCR_P 0x054A
552 #define KS8842_PORT_1_CTRL_1 KS8842_P1CR1_P
553 #define KS8842_PORT_2_CTRL_1 KS8842_P2CR1_P
554 #define KS8842_PORT_3_CTRL_1 KS8842_P3CR1_P
556 #define PORT_CTRL_ADDR(port, addr) \
557 (addr = KS8842_PORT_1_CTRL_1 + (port) * \
558 (KS8842_PORT_2_CTRL_1 - KS8842_PORT_1_CTRL_1))
560 #define KS8842_PORT_CTRL_1_OFFSET 0x00
562 #define PORT_BROADCAST_STORM 0x0080
563 #define PORT_DIFFSERV_ENABLE 0x0040
564 #define PORT_802_1P_ENABLE 0x0020
565 #define PORT_BASED_PRIORITY_MASK 0x0018
566 #define PORT_BASED_PRIORITY_BASE 0x0003
567 #define PORT_BASED_PRIORITY_SHIFT 3
568 #define PORT_BASED_PRIORITY_0 0x0000
569 #define PORT_BASED_PRIORITY_1 0x0008
570 #define PORT_BASED_PRIORITY_2 0x0010
571 #define PORT_BASED_PRIORITY_3 0x0018
572 #define PORT_INSERT_TAG 0x0004
573 #define PORT_REMOVE_TAG 0x0002
574 #define PORT_PRIO_QUEUE_ENABLE 0x0001
576 #define KS8842_PORT_CTRL_2_OFFSET 0x02
578 #define PORT_INGRESS_VLAN_FILTER 0x4000
579 #define PORT_DISCARD_NON_VID 0x2000
580 #define PORT_FORCE_FLOW_CTRL 0x1000
581 #define PORT_BACK_PRESSURE 0x0800
582 #define PORT_TX_ENABLE 0x0400
583 #define PORT_RX_ENABLE 0x0200
584 #define PORT_LEARN_DISABLE 0x0100
585 #define PORT_MIRROR_SNIFFER 0x0080
586 #define PORT_MIRROR_RX 0x0040
587 #define PORT_MIRROR_TX 0x0020
588 #define PORT_USER_PRIORITY_CEILING 0x0008
589 #define PORT_VLAN_MEMBERSHIP 0x0007
591 #define KS8842_PORT_CTRL_VID_OFFSET 0x04
593 #define PORT_DEFAULT_VID 0x0001
595 #define KS8842_PORT_CTRL_3_OFFSET 0x06
597 #define PORT_INGRESS_LIMIT_MODE 0x000C
598 #define PORT_INGRESS_ALL 0x0000
599 #define PORT_INGRESS_UNICAST 0x0004
600 #define PORT_INGRESS_MULTICAST 0x0008
601 #define PORT_INGRESS_BROADCAST 0x000C
602 #define PORT_COUNT_IFG 0x0002
603 #define PORT_COUNT_PREAMBLE 0x0001
605 #define KS8842_PORT_IN_RATE_OFFSET 0x08
606 #define KS8842_PORT_OUT_RATE_OFFSET 0x0A
608 #define PORT_PRIORITY_RATE 0x0F
609 #define PORT_PRIORITY_RATE_SHIFT 4
611 #define KS884X_PORT_LINK_MD 0x10
613 #define PORT_CABLE_10M_SHORT 0x8000
614 #define PORT_CABLE_DIAG_RESULT 0x6000
615 #define PORT_CABLE_STAT_NORMAL 0x0000
616 #define PORT_CABLE_STAT_OPEN 0x2000
617 #define PORT_CABLE_STAT_SHORT 0x4000
618 #define PORT_CABLE_STAT_FAILED 0x6000
619 #define PORT_START_CABLE_DIAG 0x1000
620 #define PORT_FORCE_LINK 0x0800
621 #define PORT_POWER_SAVING_DISABLE 0x0400
622 #define PORT_PHY_REMOTE_LOOPBACK 0x0200
623 #define PORT_CABLE_FAULT_COUNTER 0x01FF
625 #define KS884X_PORT_CTRL_4_OFFSET 0x12
627 #define PORT_LED_OFF 0x8000
628 #define PORT_TX_DISABLE 0x4000
629 #define PORT_AUTO_NEG_RESTART 0x2000
630 #define PORT_REMOTE_FAULT_DISABLE 0x1000
631 #define PORT_POWER_DOWN 0x0800
632 #define PORT_AUTO_MDIX_DISABLE 0x0400
633 #define PORT_FORCE_MDIX 0x0200
634 #define PORT_LOOPBACK 0x0100
635 #define PORT_AUTO_NEG_ENABLE 0x0080
636 #define PORT_FORCE_100_MBIT 0x0040
637 #define PORT_FORCE_FULL_DUPLEX 0x0020
638 #define PORT_AUTO_NEG_SYM_PAUSE 0x0010
639 #define PORT_AUTO_NEG_100BTX_FD 0x0008
640 #define PORT_AUTO_NEG_100BTX 0x0004
641 #define PORT_AUTO_NEG_10BT_FD 0x0002
642 #define PORT_AUTO_NEG_10BT 0x0001
644 #define KS884X_PORT_STATUS_OFFSET 0x14
646 #define PORT_HP_MDIX 0x8000
647 #define PORT_REVERSED_POLARITY 0x2000
648 #define PORT_RX_FLOW_CTRL 0x0800
649 #define PORT_TX_FLOW_CTRL 0x1000
650 #define PORT_STATUS_SPEED_100MBIT 0x0400
651 #define PORT_STATUS_FULL_DUPLEX 0x0200
652 #define PORT_REMOTE_FAULT 0x0100
653 #define PORT_MDIX_STATUS 0x0080
654 #define PORT_AUTO_NEG_COMPLETE 0x0040
655 #define PORT_STATUS_LINK_GOOD 0x0020
656 #define PORT_REMOTE_SYM_PAUSE 0x0010
657 #define PORT_REMOTE_100BTX_FD 0x0008
658 #define PORT_REMOTE_100BTX 0x0004
659 #define PORT_REMOTE_10BT_FD 0x0002
660 #define PORT_REMOTE_10BT 0x0001
663 #define STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
664 #define STATIC_MAC_TABLE_FWD_PORTS 00-00070000-00000000
665 #define STATIC_MAC_TABLE_VALID 00-00080000-00000000
666 #define STATIC_MAC_TABLE_OVERRIDE 00-00100000-00000000
667 #define STATIC_MAC_TABLE_USE_FID 00-00200000-00000000
668 #define STATIC_MAC_TABLE_FID 00-03C00000-00000000
671 #define STATIC_MAC_TABLE_ADDR 0x0000FFFF
672 #define STATIC_MAC_TABLE_FWD_PORTS 0x00070000
673 #define STATIC_MAC_TABLE_VALID 0x00080000
674 #define STATIC_MAC_TABLE_OVERRIDE 0x00100000
675 #define STATIC_MAC_TABLE_USE_FID 0x00200000
676 #define STATIC_MAC_TABLE_FID 0x03C00000
678 #define STATIC_MAC_FWD_PORTS_SHIFT 16
679 #define STATIC_MAC_FID_SHIFT 22
682 #define VLAN_TABLE_VID 00-00000000-00000FFF
683 #define VLAN_TABLE_FID 00-00000000-0000F000
684 #define VLAN_TABLE_MEMBERSHIP 00-00000000-00070000
685 #define VLAN_TABLE_VALID 00-00000000-00080000
688 #define VLAN_TABLE_VID 0x00000FFF
689 #define VLAN_TABLE_FID 0x0000F000
690 #define VLAN_TABLE_MEMBERSHIP 0x00070000
691 #define VLAN_TABLE_VALID 0x00080000
693 #define VLAN_TABLE_FID_SHIFT 12
694 #define VLAN_TABLE_MEMBERSHIP_SHIFT 16
697 #define DYNAMIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
698 #define DYNAMIC_MAC_TABLE_FID 00-000F0000-00000000
699 #define DYNAMIC_MAC_TABLE_SRC_PORT 00-00300000-00000000
700 #define DYNAMIC_MAC_TABLE_TIMESTAMP 00-00C00000-00000000
701 #define DYNAMIC_MAC_TABLE_ENTRIES 03-FF000000-00000000
702 #define DYNAMIC_MAC_TABLE_MAC_EMPTY 04-00000000-00000000
703 #define DYNAMIC_MAC_TABLE_RESERVED 78-00000000-00000000
704 #define DYNAMIC_MAC_TABLE_NOT_READY 80-00000000-00000000
707 #define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF
708 #define DYNAMIC_MAC_TABLE_FID 0x000F0000
709 #define DYNAMIC_MAC_TABLE_SRC_PORT 0x00300000
710 #define DYNAMIC_MAC_TABLE_TIMESTAMP 0x00C00000
711 #define DYNAMIC_MAC_TABLE_ENTRIES 0xFF000000
713 #define DYNAMIC_MAC_TABLE_ENTRIES_H 0x03
714 #define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x04
715 #define DYNAMIC_MAC_TABLE_RESERVED 0x78
716 #define DYNAMIC_MAC_TABLE_NOT_READY 0x80
718 #define DYNAMIC_MAC_FID_SHIFT 16
719 #define DYNAMIC_MAC_SRC_PORT_SHIFT 20
720 #define DYNAMIC_MAC_TIMESTAMP_SHIFT 22
721 #define DYNAMIC_MAC_ENTRIES_SHIFT 24
722 #define DYNAMIC_MAC_ENTRIES_H_SHIFT 8
725 #define MIB_COUNTER_VALUE 00-00000000-3FFFFFFF
726 #define MIB_COUNTER_VALID 00-00000000-40000000
727 #define MIB_COUNTER_OVERFLOW 00-00000000-80000000
730 #define MIB_COUNTER_VALUE 0x3FFFFFFF
731 #define MIB_COUNTER_VALID 0x40000000
732 #define MIB_COUNTER_OVERFLOW 0x80000000
734 #define MIB_PACKET_DROPPED 0x0000FFFF
736 #define KS_MIB_PACKET_DROPPED_TX_0 0x100
737 #define KS_MIB_PACKET_DROPPED_TX_1 0x101
738 #define KS_MIB_PACKET_DROPPED_TX 0x102
739 #define KS_MIB_PACKET_DROPPED_RX_0 0x103
740 #define KS_MIB_PACKET_DROPPED_RX_1 0x104
741 #define KS_MIB_PACKET_DROPPED_RX 0x105
743 /* Change default LED mode. */
744 #define SET_DEFAULT_LED LED_SPEED_DUPLEX_ACT
746 #define MAC_ADDR_ORDER(i) (ETH_ALEN - 1 - (i))
748 #define MAX_ETHERNET_BODY_SIZE 1500
749 #define ETHERNET_HEADER_SIZE (14 + VLAN_HLEN)
751 #define MAX_ETHERNET_PACKET_SIZE \
752 (MAX_ETHERNET_BODY_SIZE + ETHERNET_HEADER_SIZE)
754 #define REGULAR_RX_BUF_SIZE (MAX_ETHERNET_PACKET_SIZE + 4)
755 #define MAX_RX_BUF_SIZE (1912 + 4)
757 #define ADDITIONAL_ENTRIES 16
758 #define MAX_MULTICAST_LIST 32
760 #define HW_MULTICAST_SIZE 8
762 #define HW_TO_DEV_PORT(port) (port - 1)
774 /* total transmit errors */
775 OID_COUNTER_XMIT_ERROR,
777 /* total receive errors */
778 OID_COUNTER_RCV_ERROR,
784 * Hardware descriptor definitions
787 #define DESC_ALIGNMENT 16
788 #define BUFFER_ALIGNMENT 8
790 #define NUM_OF_RX_DESC 64
791 #define NUM_OF_TX_DESC 64
793 #define KS_DESC_RX_FRAME_LEN 0x000007FF
794 #define KS_DESC_RX_FRAME_TYPE 0x00008000
795 #define KS_DESC_RX_ERROR_CRC 0x00010000
796 #define KS_DESC_RX_ERROR_RUNT 0x00020000
797 #define KS_DESC_RX_ERROR_TOO_LONG 0x00040000
798 #define KS_DESC_RX_ERROR_PHY 0x00080000
799 #define KS884X_DESC_RX_PORT_MASK 0x00300000
800 #define KS_DESC_RX_MULTICAST 0x01000000
801 #define KS_DESC_RX_ERROR 0x02000000
802 #define KS_DESC_RX_ERROR_CSUM_UDP 0x04000000
803 #define KS_DESC_RX_ERROR_CSUM_TCP 0x08000000
804 #define KS_DESC_RX_ERROR_CSUM_IP 0x10000000
805 #define KS_DESC_RX_LAST 0x20000000
806 #define KS_DESC_RX_FIRST 0x40000000
807 #define KS_DESC_RX_ERROR_COND \
808 (KS_DESC_RX_ERROR_CRC | \
809 KS_DESC_RX_ERROR_RUNT | \
810 KS_DESC_RX_ERROR_PHY | \
811 KS_DESC_RX_ERROR_TOO_LONG)
813 #define KS_DESC_HW_OWNED 0x80000000
815 #define KS_DESC_BUF_SIZE 0x000007FF
816 #define KS884X_DESC_TX_PORT_MASK 0x00300000
817 #define KS_DESC_END_OF_RING 0x02000000
818 #define KS_DESC_TX_CSUM_GEN_UDP 0x04000000
819 #define KS_DESC_TX_CSUM_GEN_TCP 0x08000000
820 #define KS_DESC_TX_CSUM_GEN_IP 0x10000000
821 #define KS_DESC_TX_LAST 0x20000000
822 #define KS_DESC_TX_FIRST 0x40000000
823 #define KS_DESC_TX_INTERRUPT 0x80000000
825 #define KS_DESC_PORT_SHIFT 20
827 #define KS_DESC_RX_MASK (KS_DESC_BUF_SIZE)
829 #define KS_DESC_TX_MASK \
830 (KS_DESC_TX_INTERRUPT | \
833 KS_DESC_TX_CSUM_GEN_IP | \
834 KS_DESC_TX_CSUM_GEN_TCP | \
835 KS_DESC_TX_CSUM_GEN_UDP | \
838 struct ksz_desc_rx_stat {
839 #ifdef __BIG_ENDIAN_BITFIELD
876 struct ksz_desc_tx_stat {
877 #ifdef __BIG_ENDIAN_BITFIELD
886 struct ksz_desc_rx_buf {
887 #ifdef __BIG_ENDIAN_BITFIELD
900 struct ksz_desc_tx_buf {
901 #ifdef __BIG_ENDIAN_BITFIELD
929 struct ksz_desc_rx_stat rx;
930 struct ksz_desc_tx_stat tx;
935 struct ksz_desc_rx_buf rx;
936 struct ksz_desc_tx_buf tx;
941 * struct ksz_hw_desc - Hardware descriptor data structure
942 * @ctrl: Descriptor control value.
943 * @buf: Descriptor buffer value.
944 * @addr: Physical address of memory buffer.
945 * @next: Pointer to next hardware descriptor.
948 union desc_stat ctrl;
955 * struct ksz_sw_desc - Software descriptor data structure
956 * @ctrl: Descriptor control value.
957 * @buf: Descriptor buffer value.
958 * @buf_size: Current buffers size value in hardware descriptor.
961 union desc_stat ctrl;
967 * struct ksz_dma_buf - OS dependent DMA buffer data structure
968 * @skb: Associated socket buffer.
969 * @dma: Associated physical DMA address.
970 * len: Actual len used.
979 * struct ksz_desc - Descriptor structure
980 * @phw: Hardware descriptor pointer to uncached physical memory.
981 * @sw: Cached memory to hold hardware descriptor values for
983 * @dma_buf: Operating system dependent data structure to hold physical
984 * memory buffer allocation information.
987 struct ksz_hw_desc *phw;
988 struct ksz_sw_desc sw;
989 struct ksz_dma_buf dma_buf;
992 #define DMA_BUFFER(desc) ((struct ksz_dma_buf *)(&(desc)->dma_buf))
995 * struct ksz_desc_info - Descriptor information data structure
996 * @ring: First descriptor in the ring.
997 * @cur: Current descriptor being manipulated.
998 * @ring_virt: First hardware descriptor in the ring.
999 * @ring_phys: The physical address of the first descriptor of the ring.
1000 * @size: Size of hardware descriptor.
1001 * @alloc: Number of descriptors allocated.
1002 * @avail: Number of descriptors available for use.
1003 * @last: Index for last descriptor released to hardware.
1004 * @next: Index for next descriptor available for use.
1005 * @mask: Mask for index wrapping.
1007 struct ksz_desc_info {
1008 struct ksz_desc *ring;
1009 struct ksz_desc *cur;
1010 struct ksz_hw_desc *ring_virt;
1021 * KSZ8842 switch definitions
1025 TABLE_STATIC_MAC = 0,
1031 #define LEARNED_MAC_TABLE_ENTRIES 1024
1032 #define STATIC_MAC_TABLE_ENTRIES 8
1035 * struct ksz_mac_table - Static MAC table data structure
1036 * @mac_addr: MAC address to filter.
1039 * @ports: Port membership.
1040 * @override: Override setting.
1041 * @use_fid: FID use setting.
1042 * @valid: Valid setting indicating the entry is being used.
1044 struct ksz_mac_table {
1045 u8 mac_addr[ETH_ALEN];
1054 #define VLAN_TABLE_ENTRIES 16
1057 * struct ksz_vlan_table - VLAN table data structure
1060 * @member: Port membership.
1062 struct ksz_vlan_table {
1068 #define DIFFSERV_ENTRIES 64
1069 #define PRIO_802_1P_ENTRIES 8
1070 #define PRIO_QUEUES 4
1072 #define SWITCH_PORT_NUM 2
1073 #define TOTAL_PORT_NUM (SWITCH_PORT_NUM + 1)
1074 #define HOST_MASK (1 << SWITCH_PORT_NUM)
1078 #define OTHER_PORT 1
1079 #define HOST_PORT SWITCH_PORT_NUM
1081 #define PORT_COUNTER_NUM 0x20
1082 #define TOTAL_PORT_COUNTER_NUM (PORT_COUNTER_NUM + 2)
1084 #define MIB_COUNTER_RX_LO_PRIORITY 0x00
1085 #define MIB_COUNTER_RX_HI_PRIORITY 0x01
1086 #define MIB_COUNTER_RX_UNDERSIZE 0x02
1087 #define MIB_COUNTER_RX_FRAGMENT 0x03
1088 #define MIB_COUNTER_RX_OVERSIZE 0x04
1089 #define MIB_COUNTER_RX_JABBER 0x05
1090 #define MIB_COUNTER_RX_SYMBOL_ERR 0x06
1091 #define MIB_COUNTER_RX_CRC_ERR 0x07
1092 #define MIB_COUNTER_RX_ALIGNMENT_ERR 0x08
1093 #define MIB_COUNTER_RX_CTRL_8808 0x09
1094 #define MIB_COUNTER_RX_PAUSE 0x0A
1095 #define MIB_COUNTER_RX_BROADCAST 0x0B
1096 #define MIB_COUNTER_RX_MULTICAST 0x0C
1097 #define MIB_COUNTER_RX_UNICAST 0x0D
1098 #define MIB_COUNTER_RX_OCTET_64 0x0E
1099 #define MIB_COUNTER_RX_OCTET_65_127 0x0F
1100 #define MIB_COUNTER_RX_OCTET_128_255 0x10
1101 #define MIB_COUNTER_RX_OCTET_256_511 0x11
1102 #define MIB_COUNTER_RX_OCTET_512_1023 0x12
1103 #define MIB_COUNTER_RX_OCTET_1024_1522 0x13
1104 #define MIB_COUNTER_TX_LO_PRIORITY 0x14
1105 #define MIB_COUNTER_TX_HI_PRIORITY 0x15
1106 #define MIB_COUNTER_TX_LATE_COLLISION 0x16
1107 #define MIB_COUNTER_TX_PAUSE 0x17
1108 #define MIB_COUNTER_TX_BROADCAST 0x18
1109 #define MIB_COUNTER_TX_MULTICAST 0x19
1110 #define MIB_COUNTER_TX_UNICAST 0x1A
1111 #define MIB_COUNTER_TX_DEFERRED 0x1B
1112 #define MIB_COUNTER_TX_TOTAL_COLLISION 0x1C
1113 #define MIB_COUNTER_TX_EXCESS_COLLISION 0x1D
1114 #define MIB_COUNTER_TX_SINGLE_COLLISION 0x1E
1115 #define MIB_COUNTER_TX_MULTI_COLLISION 0x1F
1117 #define MIB_COUNTER_RX_DROPPED_PACKET 0x20
1118 #define MIB_COUNTER_TX_DROPPED_PACKET 0x21
1121 * struct ksz_port_mib - Port MIB data structure
1122 * @cnt_ptr: Current pointer to MIB counter index.
1123 * @link_down: Indication the link has just gone down.
1124 * @state: Connection status of the port.
1125 * @mib_start: The starting counter index. Some ports do not start at 0.
1126 * @counter: 64-bit MIB counter value.
1127 * @dropped: Temporary buffer to remember last read packet dropped values.
1129 * MIB counters needs to be read periodically so that counters do not get
1130 * overflowed and give incorrect values. A right balance is needed to
1131 * satisfy this condition and not waste too much CPU time.
1133 * It is pointless to read MIB counters when the port is disconnected. The
1134 * @state provides the connection status so that MIB counters are read only
1135 * when the port is connected. The @link_down indicates the port is just
1136 * disconnected so that all MIB counters are read one last time to update the
1139 struct ksz_port_mib {
1145 u64 counter[TOTAL_PORT_COUNTER_NUM];
1150 * struct ksz_port_cfg - Port configuration data structure
1152 * @member: Port membership.
1153 * @port_prio: Port priority.
1154 * @rx_rate: Receive priority rate.
1155 * @tx_rate: Transmit priority rate.
1156 * @stp_state: Current Spanning Tree Protocol state.
1158 struct ksz_port_cfg {
1162 u32 rx_rate[PRIO_QUEUES];
1163 u32 tx_rate[PRIO_QUEUES];
1168 * struct ksz_switch - KSZ8842 switch data structure
1169 * @mac_table: MAC table entries information.
1170 * @vlan_table: VLAN table entries information.
1171 * @port_cfg: Port configuration information.
1172 * @diffserv: DiffServ priority settings. Possible values from 6-bit of ToS
1173 * (bit7 ~ bit2) field.
1174 * @p_802_1p: 802.1P priority settings. Possible values from 3-bit of 802.1p
1175 * Tag priority field.
1176 * @br_addr: Bridge address. Used for STP.
1177 * @other_addr: Other MAC address. Used for multiple network device mode.
1178 * @broad_per: Broadcast storm percentage.
1179 * @member: Current port membership. Used for STP.
1182 struct ksz_mac_table mac_table[STATIC_MAC_TABLE_ENTRIES];
1183 struct ksz_vlan_table vlan_table[VLAN_TABLE_ENTRIES];
1184 struct ksz_port_cfg port_cfg[TOTAL_PORT_NUM];
1186 u8 diffserv[DIFFSERV_ENTRIES];
1187 u8 p_802_1p[PRIO_802_1P_ENTRIES];
1189 u8 br_addr[ETH_ALEN];
1190 u8 other_addr[ETH_ALEN];
1196 #define TX_RATE_UNIT 10000
1199 * struct ksz_port_info - Port information data structure
1200 * @state: Connection status of the port.
1201 * @tx_rate: Transmit rate divided by 10000 to get Mbit.
1202 * @duplex: Duplex mode.
1203 * @advertised: Advertised auto-negotiation setting. Used to determine link.
1204 * @partner: Auto-negotiation partner setting. Used to determine link.
1205 * @port_id: Port index to access actual hardware register.
1206 * @pdev: Pointer to OS dependent network device.
1208 struct ksz_port_info {
1218 #define MAX_TX_HELD_SIZE 52000
1220 /* Hardware features and bug fixes. */
1221 #define LINK_INT_WORKING (1 << 0)
1222 #define SMALL_PACKET_TX_BUG (1 << 1)
1223 #define HALF_DUPLEX_SIGNAL_BUG (1 << 2)
1224 #define RX_HUGE_FRAME (1 << 4)
1225 #define STP_SUPPORT (1 << 8)
1227 /* Software overrides. */
1228 #define PAUSE_FLOW_CTRL (1 << 0)
1229 #define FAST_AGING (1 << 1)
1232 * struct ksz_hw - KSZ884X hardware data structure
1233 * @io: Virtual address assigned.
1234 * @ksz_switch: Pointer to KSZ8842 switch.
1235 * @port_info: Port information.
1236 * @port_mib: Port MIB information.
1237 * @dev_count: Number of network devices this hardware supports.
1238 * @dst_ports: Destination ports in switch for transmission.
1239 * @id: Hardware ID. Used for display only.
1240 * @mib_cnt: Number of MIB counters this hardware has.
1241 * @mib_port_cnt: Number of ports with MIB counters.
1242 * @tx_cfg: Cached transmit control settings.
1243 * @rx_cfg: Cached receive control settings.
1244 * @intr_mask: Current interrupt mask.
1245 * @intr_set: Current interrup set.
1246 * @intr_blocked: Interrupt blocked.
1247 * @rx_desc_info: Receive descriptor information.
1248 * @tx_desc_info: Transmit descriptor information.
1249 * @tx_int_cnt: Transmit interrupt count. Used for TX optimization.
1250 * @tx_int_mask: Transmit interrupt mask. Used for TX optimization.
1251 * @tx_size: Transmit data size. Used for TX optimization.
1252 * The maximum is defined by MAX_TX_HELD_SIZE.
1253 * @perm_addr: Permanent MAC address.
1254 * @override_addr: Overridden MAC address.
1255 * @address: Additional MAC address entries.
1256 * @addr_list_size: Additional MAC address list size.
1257 * @mac_override: Indication of MAC address overridden.
1258 * @promiscuous: Counter to keep track of promiscuous mode set.
1259 * @all_multi: Counter to keep track of all multicast mode set.
1260 * @multi_list: Multicast address entries.
1261 * @multi_bits: Cached multicast hash table settings.
1262 * @multi_list_size: Multicast address list size.
1263 * @enabled: Indication of hardware enabled.
1264 * @rx_stop: Indication of receive process stop.
1265 * @features: Hardware features to enable.
1266 * @overrides: Hardware features to override.
1267 * @parent: Pointer to parent, network device private structure.
1272 struct ksz_switch *ksz_switch;
1273 struct ksz_port_info port_info[SWITCH_PORT_NUM];
1274 struct ksz_port_mib port_mib[TOTAL_PORT_NUM];
1287 struct ksz_desc_info rx_desc_info;
1288 struct ksz_desc_info tx_desc_info;
1294 u8 perm_addr[ETH_ALEN];
1295 u8 override_addr[ETH_ALEN];
1296 u8 address[ADDITIONAL_ENTRIES][ETH_ALEN];
1301 u8 multi_list[MAX_MULTICAST_LIST][ETH_ALEN];
1302 u8 multi_bits[HW_MULTICAST_SIZE];
1323 * struct ksz_port - Virtual port data structure
1324 * @duplex: Duplex mode setting. 1 for half duplex, 2 for full
1325 * duplex, and 0 for auto, which normally results in full
1327 * @speed: Speed setting. 10 for 10 Mbit, 100 for 100 Mbit, and
1328 * 0 for auto, which normally results in 100 Mbit.
1329 * @force_link: Force link setting. 0 for auto-negotiation, and 1 for
1331 * @flow_ctrl: Flow control setting. PHY_NO_FLOW_CTRL for no flow
1332 * control, and PHY_FLOW_CTRL for flow control.
1333 * PHY_TX_ONLY and PHY_RX_ONLY are not supported for 100
1335 * @first_port: Index of first port this port supports.
1336 * @mib_port_cnt: Number of ports with MIB counters.
1337 * @port_cnt: Number of ports this port supports.
1338 * @counter: Port statistics counter.
1339 * @hw: Pointer to hardware structure.
1340 * @linked: Pointer to port information linked to this port.
1351 u64 counter[OID_COUNTER_LAST];
1354 struct ksz_port_info *linked;
1358 * struct ksz_timer_info - Timer information data structure
1359 * @timer: Kernel timer.
1360 * @cnt: Running timer counter.
1361 * @max: Number of times to run timer; -1 for infinity.
1362 * @period: Timer period in jiffies.
1364 struct ksz_timer_info {
1365 struct timer_list timer;
1372 * struct ksz_shared_mem - OS dependent shared memory data structure
1373 * @dma_addr: Physical DMA address allocated.
1374 * @alloc_size: Allocation size.
1375 * @phys: Actual physical address used.
1376 * @alloc_virt: Virtual address allocated.
1377 * @virt: Actual virtual address used.
1379 struct ksz_shared_mem {
1380 dma_addr_t dma_addr;
1388 * struct ksz_counter_info - OS dependent counter information data structure
1389 * @counter: Wait queue to wakeup after counters are read.
1390 * @time: Next time in jiffies to read counter.
1391 * @read: Indication of counters read in full or not.
1393 struct ksz_counter_info {
1394 wait_queue_head_t counter;
1400 * struct dev_info - Network device information data structure
1401 * @dev: Pointer to network device.
1402 * @pdev: Pointer to PCI device.
1403 * @hw: Hardware structure.
1404 * @desc_pool: Physical memory used for descriptor pool.
1405 * @hwlock: Spinlock to prevent hardware from accessing.
1406 * @lock: Mutex lock to prevent device from accessing.
1407 * @dev_rcv: Receive process function used.
1408 * @last_skb: Socket buffer allocated for descriptor rx fragments.
1409 * @skb_index: Buffer index for receiving fragments.
1410 * @skb_len: Buffer length for receiving fragments.
1411 * @mib_read: Workqueue to read MIB counters.
1412 * @mib_timer_info: Timer to read MIB counters.
1413 * @counter: Used for MIB reading.
1414 * @mtu: Current MTU used. The default is REGULAR_RX_BUF_SIZE;
1415 * the maximum is MAX_RX_BUF_SIZE.
1416 * @opened: Counter to keep track of device open.
1417 * @rx_tasklet: Receive processing tasklet.
1418 * @tx_tasklet: Transmit processing tasklet.
1419 * @wol_enable: Wake-on-LAN enable set by ethtool.
1420 * @wol_support: Wake-on-LAN support used by ethtool.
1421 * @pme_wait: Used for KSZ8841 power management.
1424 struct net_device *dev;
1425 struct pci_dev *pdev;
1428 struct ksz_shared_mem desc_pool;
1433 int (*dev_rcv)(struct dev_info *);
1435 struct sk_buff *last_skb;
1439 struct work_struct mib_read;
1440 struct ksz_timer_info mib_timer_info;
1441 struct ksz_counter_info counter[TOTAL_PORT_NUM];
1446 struct tasklet_struct rx_tasklet;
1447 struct tasklet_struct tx_tasklet;
1451 unsigned long pme_wait;
1455 * struct dev_priv - Network device private data structure
1456 * @adapter: Adapter device information.
1457 * @port: Port information.
1458 * @monitor_time_info: Timer to monitor ports.
1459 * @proc_sem: Semaphore for proc accessing.
1461 * @mii_if: MII interface information.
1462 * @advertising: Temporary variable to store advertised settings.
1463 * @msg_enable: The message flags controlling driver output.
1464 * @media_state: The connection status of the device.
1465 * @multicast: The all multicast state of the device.
1466 * @promiscuous: The promiscuous state of the device.
1469 struct dev_info *adapter;
1470 struct ksz_port port;
1471 struct ksz_timer_info monitor_timer_info;
1473 struct semaphore proc_sem;
1476 struct mii_if_info mii_if;
1485 #define DRV_NAME "KSZ884X PCI"
1486 #define DEVICE_NAME "KSZ884x PCI"
1487 #define DRV_VERSION "1.0.0"
1488 #define DRV_RELDATE "Feb 8, 2010"
1490 static char version[] =
1491 "Micrel " DEVICE_NAME " " DRV_VERSION " (" DRV_RELDATE ")";
1493 static u8 DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x88, 0x42, 0x01 };
1496 * Interrupt processing primary routines
1499 static inline void hw_ack_intr(struct ksz_hw *hw, uint interrupt)
1501 writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS);
1504 static inline void hw_dis_intr(struct ksz_hw *hw)
1506 hw->intr_blocked = hw->intr_mask;
1507 writel(0, hw->io + KS884X_INTERRUPTS_ENABLE);
1508 hw->intr_set = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1511 static inline void hw_set_intr(struct ksz_hw *hw, uint interrupt)
1513 hw->intr_set = interrupt;
1514 writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE);
1517 static inline void hw_ena_intr(struct ksz_hw *hw)
1519 hw->intr_blocked = 0;
1520 hw_set_intr(hw, hw->intr_mask);
1523 static inline void hw_dis_intr_bit(struct ksz_hw *hw, uint bit)
1525 hw->intr_mask &= ~(bit);
1528 static inline void hw_turn_off_intr(struct ksz_hw *hw, uint interrupt)
1532 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1533 hw->intr_set = read_intr & ~interrupt;
1534 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1535 hw_dis_intr_bit(hw, interrupt);
1539 * hw_turn_on_intr - turn on specified interrupts
1540 * @hw: The hardware instance.
1541 * @bit: The interrupt bits to be on.
1543 * This routine turns on the specified interrupts in the interrupt mask so that
1544 * those interrupts will be enabled.
1546 static void hw_turn_on_intr(struct ksz_hw *hw, u32 bit)
1548 hw->intr_mask |= bit;
1550 if (!hw->intr_blocked)
1551 hw_set_intr(hw, hw->intr_mask);
1554 static inline void hw_ena_intr_bit(struct ksz_hw *hw, uint interrupt)
1558 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1559 hw->intr_set = read_intr | interrupt;
1560 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1563 static inline void hw_read_intr(struct ksz_hw *hw, uint *status)
1565 *status = readl(hw->io + KS884X_INTERRUPTS_STATUS);
1566 *status = *status & hw->intr_set;
1569 static inline void hw_restore_intr(struct ksz_hw *hw, uint interrupt)
1576 * hw_block_intr - block hardware interrupts
1578 * This function blocks all interrupts of the hardware and returns the current
1579 * interrupt enable mask so that interrupts can be restored later.
1581 * Return the current interrupt enable mask.
1583 static uint hw_block_intr(struct ksz_hw *hw)
1587 if (!hw->intr_blocked) {
1589 interrupt = hw->intr_blocked;
1595 * Hardware descriptor routines
1598 static inline void reset_desc(struct ksz_desc *desc, union desc_stat status)
1600 status.rx.hw_owned = 0;
1601 desc->phw->ctrl.data = cpu_to_le32(status.data);
1604 static inline void release_desc(struct ksz_desc *desc)
1606 desc->sw.ctrl.tx.hw_owned = 1;
1607 if (desc->sw.buf_size != desc->sw.buf.data) {
1608 desc->sw.buf_size = desc->sw.buf.data;
1609 desc->phw->buf.data = cpu_to_le32(desc->sw.buf.data);
1611 desc->phw->ctrl.data = cpu_to_le32(desc->sw.ctrl.data);
1614 static void get_rx_pkt(struct ksz_desc_info *info, struct ksz_desc **desc)
1616 *desc = &info->ring[info->last];
1618 info->last &= info->mask;
1620 (*desc)->sw.buf.data &= ~KS_DESC_RX_MASK;
1623 static inline void set_rx_buf(struct ksz_desc *desc, u32 addr)
1625 desc->phw->addr = cpu_to_le32(addr);
1628 static inline void set_rx_len(struct ksz_desc *desc, u32 len)
1630 desc->sw.buf.rx.buf_size = len;
1633 static inline void get_tx_pkt(struct ksz_desc_info *info,
1634 struct ksz_desc **desc)
1636 *desc = &info->ring[info->next];
1638 info->next &= info->mask;
1640 (*desc)->sw.buf.data &= ~KS_DESC_TX_MASK;
1643 static inline void set_tx_buf(struct ksz_desc *desc, u32 addr)
1645 desc->phw->addr = cpu_to_le32(addr);
1648 static inline void set_tx_len(struct ksz_desc *desc, u32 len)
1650 desc->sw.buf.tx.buf_size = len;
1653 /* Switch functions */
1655 #define TABLE_READ 0x10
1656 #define TABLE_SEL_SHIFT 2
1658 #define HW_DELAY(hw, reg) \
1660 readw(hw->io + reg); \
1664 * sw_r_table - read 4 bytes of data from switch table
1665 * @hw: The hardware instance.
1666 * @table: The table selector.
1667 * @addr: The address of the table entry.
1668 * @data: Buffer to store the read data.
1670 * This routine reads 4 bytes of data from the table of the switch.
1671 * Hardware interrupts are disabled to minimize corruption of read data.
1673 static void sw_r_table(struct ksz_hw *hw, int table, u16 addr, u32 *data)
1678 ctrl_addr = (((table << TABLE_SEL_SHIFT) | TABLE_READ) << 8) | addr;
1680 interrupt = hw_block_intr(hw);
1682 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1683 HW_DELAY(hw, KS884X_IACR_OFFSET);
1684 *data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1686 hw_restore_intr(hw, interrupt);
1690 * sw_w_table_64 - write 8 bytes of data to the switch table
1691 * @hw: The hardware instance.
1692 * @table: The table selector.
1693 * @addr: The address of the table entry.
1694 * @data_hi: The high part of data to be written (bit63 ~ bit32).
1695 * @data_lo: The low part of data to be written (bit31 ~ bit0).
1697 * This routine writes 8 bytes of data to the table of the switch.
1698 * Hardware interrupts are disabled to minimize corruption of written data.
1700 static void sw_w_table_64(struct ksz_hw *hw, int table, u16 addr, u32 data_hi,
1706 ctrl_addr = ((table << TABLE_SEL_SHIFT) << 8) | addr;
1708 interrupt = hw_block_intr(hw);
1710 writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET);
1711 writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET);
1713 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1714 HW_DELAY(hw, KS884X_IACR_OFFSET);
1716 hw_restore_intr(hw, interrupt);
1720 * sw_w_sta_mac_table - write to the static MAC table
1721 * @hw: The hardware instance.
1722 * @addr: The address of the table entry.
1723 * @mac_addr: The MAC address.
1724 * @ports: The port members.
1725 * @override: The flag to override the port receive/transmit settings.
1726 * @valid: The flag to indicate entry is valid.
1727 * @use_fid: The flag to indicate the FID is valid.
1728 * @fid: The FID value.
1730 * This routine writes an entry of the static MAC table of the switch. It
1731 * calls sw_w_table_64() to write the data.
1733 static void sw_w_sta_mac_table(struct ksz_hw *hw, u16 addr, u8 *mac_addr,
1734 u8 ports, int override, int valid, int use_fid, u8 fid)
1739 data_lo = ((u32) mac_addr[2] << 24) |
1740 ((u32) mac_addr[3] << 16) |
1741 ((u32) mac_addr[4] << 8) | mac_addr[5];
1742 data_hi = ((u32) mac_addr[0] << 8) | mac_addr[1];
1743 data_hi |= (u32) ports << STATIC_MAC_FWD_PORTS_SHIFT;
1746 data_hi |= STATIC_MAC_TABLE_OVERRIDE;
1748 data_hi |= STATIC_MAC_TABLE_USE_FID;
1749 data_hi |= (u32) fid << STATIC_MAC_FID_SHIFT;
1752 data_hi |= STATIC_MAC_TABLE_VALID;
1754 sw_w_table_64(hw, TABLE_STATIC_MAC, addr, data_hi, data_lo);
1758 * sw_r_vlan_table - read from the VLAN table
1759 * @hw: The hardware instance.
1760 * @addr: The address of the table entry.
1761 * @vid: Buffer to store the VID.
1762 * @fid: Buffer to store the VID.
1763 * @member: Buffer to store the port membership.
1765 * This function reads an entry of the VLAN table of the switch. It calls
1766 * sw_r_table() to get the data.
1768 * Return 0 if the entry is valid; otherwise -1.
1770 static int sw_r_vlan_table(struct ksz_hw *hw, u16 addr, u16 *vid, u8 *fid,
1775 sw_r_table(hw, TABLE_VLAN, addr, &data);
1776 if (data & VLAN_TABLE_VALID) {
1777 *vid = (u16)(data & VLAN_TABLE_VID);
1778 *fid = (u8)((data & VLAN_TABLE_FID) >> VLAN_TABLE_FID_SHIFT);
1779 *member = (u8)((data & VLAN_TABLE_MEMBERSHIP) >>
1780 VLAN_TABLE_MEMBERSHIP_SHIFT);
1787 * port_r_mib_cnt - read MIB counter
1788 * @hw: The hardware instance.
1789 * @port: The port index.
1790 * @addr: The address of the counter.
1791 * @cnt: Buffer to store the counter.
1793 * This routine reads a MIB counter of the port.
1794 * Hardware interrupts are disabled to minimize corruption of read data.
1796 static void port_r_mib_cnt(struct ksz_hw *hw, int port, u16 addr, u64 *cnt)
1803 ctrl_addr = addr + PORT_COUNTER_NUM * port;
1805 interrupt = hw_block_intr(hw);
1807 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ) << 8);
1808 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1809 HW_DELAY(hw, KS884X_IACR_OFFSET);
1811 for (timeout = 100; timeout > 0; timeout--) {
1812 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1814 if (data & MIB_COUNTER_VALID) {
1815 if (data & MIB_COUNTER_OVERFLOW)
1816 *cnt += MIB_COUNTER_VALUE + 1;
1817 *cnt += data & MIB_COUNTER_VALUE;
1822 hw_restore_intr(hw, interrupt);
1826 * port_r_mib_pkt - read dropped packet counts
1827 * @hw: The hardware instance.
1828 * @port: The port index.
1829 * @cnt: Buffer to store the receive and transmit dropped packet counts.
1831 * This routine reads the dropped packet counts of the port.
1832 * Hardware interrupts are disabled to minimize corruption of read data.
1834 static void port_r_mib_pkt(struct ksz_hw *hw, int port, u32 *last, u64 *cnt)
1842 index = KS_MIB_PACKET_DROPPED_RX_0 + port;
1844 interrupt = hw_block_intr(hw);
1846 ctrl_addr = (u16) index;
1847 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ)
1849 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1850 HW_DELAY(hw, KS884X_IACR_OFFSET);
1851 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1853 hw_restore_intr(hw, interrupt);
1855 data &= MIB_PACKET_DROPPED;
1860 data += MIB_PACKET_DROPPED + 1;
1866 index -= KS_MIB_PACKET_DROPPED_TX -
1867 KS_MIB_PACKET_DROPPED_TX_0 + 1;
1868 } while (index >= KS_MIB_PACKET_DROPPED_TX_0 + port);
1872 * port_r_cnt - read MIB counters periodically
1873 * @hw: The hardware instance.
1874 * @port: The port index.
1876 * This routine is used to read the counters of the port periodically to avoid
1877 * counter overflow. The hardware should be acquired first before calling this
1880 * Return non-zero when not all counters not read.
1882 static int port_r_cnt(struct ksz_hw *hw, int port)
1884 struct ksz_port_mib *mib = &hw->port_mib[port];
1886 if (mib->mib_start < PORT_COUNTER_NUM)
1887 while (mib->cnt_ptr < PORT_COUNTER_NUM) {
1888 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1889 &mib->counter[mib->cnt_ptr]);
1892 if (hw->mib_cnt > PORT_COUNTER_NUM)
1893 port_r_mib_pkt(hw, port, mib->dropped,
1894 &mib->counter[PORT_COUNTER_NUM]);
1900 * port_init_cnt - initialize MIB counter values
1901 * @hw: The hardware instance.
1902 * @port: The port index.
1904 * This routine is used to initialize all counters to zero if the hardware
1905 * cannot do it after reset.
1907 static void port_init_cnt(struct ksz_hw *hw, int port)
1909 struct ksz_port_mib *mib = &hw->port_mib[port];
1912 if (mib->mib_start < PORT_COUNTER_NUM)
1914 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1915 &mib->counter[mib->cnt_ptr]);
1917 } while (mib->cnt_ptr < PORT_COUNTER_NUM);
1918 if (hw->mib_cnt > PORT_COUNTER_NUM)
1919 port_r_mib_pkt(hw, port, mib->dropped,
1920 &mib->counter[PORT_COUNTER_NUM]);
1921 memset((void *) mib->counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
1930 * port_chk - check port register bits
1931 * @hw: The hardware instance.
1932 * @port: The port index.
1933 * @offset: The offset of the port register.
1934 * @bits: The data bits to check.
1936 * This function checks whether the specified bits of the port register are set
1939 * Return 0 if the bits are not set.
1941 static int port_chk(struct ksz_hw *hw, int port, int offset, u16 bits)
1946 PORT_CTRL_ADDR(port, addr);
1948 data = readw(hw->io + addr);
1949 return (data & bits) == bits;
1953 * port_cfg - set port register bits
1954 * @hw: The hardware instance.
1955 * @port: The port index.
1956 * @offset: The offset of the port register.
1957 * @bits: The data bits to set.
1958 * @set: The flag indicating whether the bits are to be set or not.
1960 * This routine sets or resets the specified bits of the port register.
1962 static void port_cfg(struct ksz_hw *hw, int port, int offset, u16 bits,
1968 PORT_CTRL_ADDR(port, addr);
1970 data = readw(hw->io + addr);
1975 writew(data, hw->io + addr);
1979 * port_chk_shift - check port bit
1980 * @hw: The hardware instance.
1981 * @port: The port index.
1982 * @offset: The offset of the register.
1983 * @shift: Number of bits to shift.
1985 * This function checks whether the specified port is set in the register or
1988 * Return 0 if the port is not set.
1990 static int port_chk_shift(struct ksz_hw *hw, int port, u32 addr, int shift)
1993 u16 bit = 1 << port;
1995 data = readw(hw->io + addr);
1997 return (data & bit) == bit;
2001 * port_cfg_shift - set port bit
2002 * @hw: The hardware instance.
2003 * @port: The port index.
2004 * @offset: The offset of the register.
2005 * @shift: Number of bits to shift.
2006 * @set: The flag indicating whether the port is to be set or not.
2008 * This routine sets or resets the specified port in the register.
2010 static void port_cfg_shift(struct ksz_hw *hw, int port, u32 addr, int shift,
2014 u16 bits = 1 << port;
2016 data = readw(hw->io + addr);
2022 writew(data, hw->io + addr);
2026 * port_r8 - read byte from port register
2027 * @hw: The hardware instance.
2028 * @port: The port index.
2029 * @offset: The offset of the port register.
2030 * @data: Buffer to store the data.
2032 * This routine reads a byte from the port register.
2034 static void port_r8(struct ksz_hw *hw, int port, int offset, u8 *data)
2038 PORT_CTRL_ADDR(port, addr);
2040 *data = readb(hw->io + addr);
2044 * port_r16 - read word from port register.
2045 * @hw: The hardware instance.
2046 * @port: The port index.
2047 * @offset: The offset of the port register.
2048 * @data: Buffer to store the data.
2050 * This routine reads a word from the port register.
2052 static void port_r16(struct ksz_hw *hw, int port, int offset, u16 *data)
2056 PORT_CTRL_ADDR(port, addr);
2058 *data = readw(hw->io + addr);
2062 * port_w16 - write word to port register.
2063 * @hw: The hardware instance.
2064 * @port: The port index.
2065 * @offset: The offset of the port register.
2066 * @data: Data to write.
2068 * This routine writes a word to the port register.
2070 static void port_w16(struct ksz_hw *hw, int port, int offset, u16 data)
2074 PORT_CTRL_ADDR(port, addr);
2076 writew(data, hw->io + addr);
2080 * sw_chk - check switch register bits
2081 * @hw: The hardware instance.
2082 * @addr: The address of the switch register.
2083 * @bits: The data bits to check.
2085 * This function checks whether the specified bits of the switch register are
2088 * Return 0 if the bits are not set.
2090 static int sw_chk(struct ksz_hw *hw, u32 addr, u16 bits)
2094 data = readw(hw->io + addr);
2095 return (data & bits) == bits;
2099 * sw_cfg - set switch register bits
2100 * @hw: The hardware instance.
2101 * @addr: The address of the switch register.
2102 * @bits: The data bits to set.
2103 * @set: The flag indicating whether the bits are to be set or not.
2105 * This function sets or resets the specified bits of the switch register.
2107 static void sw_cfg(struct ksz_hw *hw, u32 addr, u16 bits, int set)
2111 data = readw(hw->io + addr);
2116 writew(data, hw->io + addr);
2121 static inline void port_cfg_broad_storm(struct ksz_hw *hw, int p, int set)
2124 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM, set);
2127 static inline int port_chk_broad_storm(struct ksz_hw *hw, int p)
2129 return port_chk(hw, p,
2130 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM);
2133 /* Driver set switch broadcast storm protection at 10% rate. */
2134 #define BROADCAST_STORM_PROTECTION_RATE 10
2136 /* 148,800 frames * 67 ms / 100 */
2137 #define BROADCAST_STORM_VALUE 9969
2140 * sw_cfg_broad_storm - configure broadcast storm threshold
2141 * @hw: The hardware instance.
2142 * @percent: Broadcast storm threshold in percent of transmit rate.
2144 * This routine configures the broadcast storm threshold of the switch.
2146 static void sw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2149 u32 value = ((u32) BROADCAST_STORM_VALUE * (u32) percent / 100);
2151 if (value > BROADCAST_STORM_RATE)
2152 value = BROADCAST_STORM_RATE;
2154 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2155 data &= ~(BROADCAST_STORM_RATE_LO | BROADCAST_STORM_RATE_HI);
2156 data |= ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8);
2157 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2161 * sw_get_board_storm - get broadcast storm threshold
2162 * @hw: The hardware instance.
2163 * @percent: Buffer to store the broadcast storm threshold percentage.
2165 * This routine retrieves the broadcast storm threshold of the switch.
2167 static void sw_get_broad_storm(struct ksz_hw *hw, u8 *percent)
2172 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2173 num = (data & BROADCAST_STORM_RATE_HI);
2175 num |= (data & BROADCAST_STORM_RATE_LO) >> 8;
2176 num = (num * 100 + BROADCAST_STORM_VALUE / 2) / BROADCAST_STORM_VALUE;
2177 *percent = (u8) num;
2181 * sw_dis_broad_storm - disable broadstorm
2182 * @hw: The hardware instance.
2183 * @port: The port index.
2185 * This routine disables the broadcast storm limit function of the switch.
2187 static void sw_dis_broad_storm(struct ksz_hw *hw, int port)
2189 port_cfg_broad_storm(hw, port, 0);
2193 * sw_ena_broad_storm - enable broadcast storm
2194 * @hw: The hardware instance.
2195 * @port: The port index.
2197 * This routine enables the broadcast storm limit function of the switch.
2199 static void sw_ena_broad_storm(struct ksz_hw *hw, int port)
2201 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2202 port_cfg_broad_storm(hw, port, 1);
2206 * sw_init_broad_storm - initialize broadcast storm
2207 * @hw: The hardware instance.
2209 * This routine initializes the broadcast storm limit function of the switch.
2211 static void sw_init_broad_storm(struct ksz_hw *hw)
2215 hw->ksz_switch->broad_per = 1;
2216 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2217 for (port = 0; port < TOTAL_PORT_NUM; port++)
2218 sw_dis_broad_storm(hw, port);
2219 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, MULTICAST_STORM_DISABLE, 1);
2223 * hw_cfg_broad_storm - configure broadcast storm
2224 * @hw: The hardware instance.
2225 * @percent: Broadcast storm threshold in percent of transmit rate.
2227 * This routine configures the broadcast storm threshold of the switch.
2228 * It is called by user functions. The hardware should be acquired first.
2230 static void hw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2235 sw_cfg_broad_storm(hw, percent);
2236 sw_get_broad_storm(hw, &percent);
2237 hw->ksz_switch->broad_per = percent;
2241 * sw_dis_prio_rate - disable switch priority rate
2242 * @hw: The hardware instance.
2243 * @port: The port index.
2245 * This routine disables the priority rate function of the switch.
2247 static void sw_dis_prio_rate(struct ksz_hw *hw, int port)
2251 PORT_CTRL_ADDR(port, addr);
2252 addr += KS8842_PORT_IN_RATE_OFFSET;
2253 writel(0, hw->io + addr);
2257 * sw_init_prio_rate - initialize switch prioirty rate
2258 * @hw: The hardware instance.
2260 * This routine initializes the priority rate function of the switch.
2262 static void sw_init_prio_rate(struct ksz_hw *hw)
2266 struct ksz_switch *sw = hw->ksz_switch;
2268 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2269 for (prio = 0; prio < PRIO_QUEUES; prio++) {
2270 sw->port_cfg[port].rx_rate[prio] =
2271 sw->port_cfg[port].tx_rate[prio] = 0;
2273 sw_dis_prio_rate(hw, port);
2279 static inline void port_cfg_back_pressure(struct ksz_hw *hw, int p, int set)
2282 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE, set);
2285 static inline void port_cfg_force_flow_ctrl(struct ksz_hw *hw, int p, int set)
2288 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL, set);
2291 static inline int port_chk_back_pressure(struct ksz_hw *hw, int p)
2293 return port_chk(hw, p,
2294 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE);
2297 static inline int port_chk_force_flow_ctrl(struct ksz_hw *hw, int p)
2299 return port_chk(hw, p,
2300 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL);
2305 static inline void port_cfg_rx(struct ksz_hw *hw, int p, int set)
2308 KS8842_PORT_CTRL_2_OFFSET, PORT_RX_ENABLE, set);
2311 static inline void port_cfg_tx(struct ksz_hw *hw, int p, int set)
2314 KS8842_PORT_CTRL_2_OFFSET, PORT_TX_ENABLE, set);
2317 static inline void sw_cfg_fast_aging(struct ksz_hw *hw, int set)
2319 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, SWITCH_FAST_AGING, set);
2322 static inline void sw_flush_dyn_mac_table(struct ksz_hw *hw)
2324 if (!(hw->overrides & FAST_AGING)) {
2325 sw_cfg_fast_aging(hw, 1);
2327 sw_cfg_fast_aging(hw, 0);
2333 static inline void port_cfg_ins_tag(struct ksz_hw *hw, int p, int insert)
2336 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG, insert);
2339 static inline void port_cfg_rmv_tag(struct ksz_hw *hw, int p, int remove)
2342 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG, remove);
2345 static inline int port_chk_ins_tag(struct ksz_hw *hw, int p)
2347 return port_chk(hw, p,
2348 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG);
2351 static inline int port_chk_rmv_tag(struct ksz_hw *hw, int p)
2353 return port_chk(hw, p,
2354 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG);
2357 static inline void port_cfg_dis_non_vid(struct ksz_hw *hw, int p, int set)
2360 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID, set);
2363 static inline void port_cfg_in_filter(struct ksz_hw *hw, int p, int set)
2366 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER, set);
2369 static inline int port_chk_dis_non_vid(struct ksz_hw *hw, int p)
2371 return port_chk(hw, p,
2372 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID);
2375 static inline int port_chk_in_filter(struct ksz_hw *hw, int p)
2377 return port_chk(hw, p,
2378 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER);
2383 static inline void port_cfg_mirror_sniffer(struct ksz_hw *hw, int p, int set)
2386 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_SNIFFER, set);
2389 static inline void port_cfg_mirror_rx(struct ksz_hw *hw, int p, int set)
2392 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_RX, set);
2395 static inline void port_cfg_mirror_tx(struct ksz_hw *hw, int p, int set)
2398 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_TX, set);
2401 static inline void sw_cfg_mirror_rx_tx(struct ksz_hw *hw, int set)
2403 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, SWITCH_MIRROR_RX_TX, set);
2406 static void sw_init_mirror(struct ksz_hw *hw)
2410 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2411 port_cfg_mirror_sniffer(hw, port, 0);
2412 port_cfg_mirror_rx(hw, port, 0);
2413 port_cfg_mirror_tx(hw, port, 0);
2415 sw_cfg_mirror_rx_tx(hw, 0);
2418 static inline void sw_cfg_unk_def_deliver(struct ksz_hw *hw, int set)
2420 sw_cfg(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2421 SWITCH_UNK_DEF_PORT_ENABLE, set);
2424 static inline int sw_cfg_chk_unk_def_deliver(struct ksz_hw *hw)
2426 return sw_chk(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2427 SWITCH_UNK_DEF_PORT_ENABLE);
2430 static inline void sw_cfg_unk_def_port(struct ksz_hw *hw, int port, int set)
2432 port_cfg_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0, set);
2435 static inline int sw_chk_unk_def_port(struct ksz_hw *hw, int port)
2437 return port_chk_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0);
2442 static inline void port_cfg_diffserv(struct ksz_hw *hw, int p, int set)
2445 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE, set);
2448 static inline void port_cfg_802_1p(struct ksz_hw *hw, int p, int set)
2451 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE, set);
2454 static inline void port_cfg_replace_vid(struct ksz_hw *hw, int p, int set)
2457 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING, set);
2460 static inline void port_cfg_prio(struct ksz_hw *hw, int p, int set)
2463 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE, set);
2466 static inline int port_chk_diffserv(struct ksz_hw *hw, int p)
2468 return port_chk(hw, p,
2469 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE);
2472 static inline int port_chk_802_1p(struct ksz_hw *hw, int p)
2474 return port_chk(hw, p,
2475 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE);
2478 static inline int port_chk_replace_vid(struct ksz_hw *hw, int p)
2480 return port_chk(hw, p,
2481 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING);
2484 static inline int port_chk_prio(struct ksz_hw *hw, int p)
2486 return port_chk(hw, p,
2487 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE);
2491 * sw_dis_diffserv - disable switch DiffServ priority
2492 * @hw: The hardware instance.
2493 * @port: The port index.
2495 * This routine disables the DiffServ priority function of the switch.
2497 static void sw_dis_diffserv(struct ksz_hw *hw, int port)
2499 port_cfg_diffserv(hw, port, 0);
2503 * sw_dis_802_1p - disable switch 802.1p priority
2504 * @hw: The hardware instance.
2505 * @port: The port index.
2507 * This routine disables the 802.1p priority function of the switch.
2509 static void sw_dis_802_1p(struct ksz_hw *hw, int port)
2511 port_cfg_802_1p(hw, port, 0);
2515 * sw_cfg_replace_null_vid -
2516 * @hw: The hardware instance.
2517 * @set: The flag to disable or enable.
2520 static void sw_cfg_replace_null_vid(struct ksz_hw *hw, int set)
2522 sw_cfg(hw, KS8842_SWITCH_CTRL_3_OFFSET, SWITCH_REPLACE_NULL_VID, set);
2526 * sw_cfg_replace_vid - enable switch 802.10 priority re-mapping
2527 * @hw: The hardware instance.
2528 * @port: The port index.
2529 * @set: The flag to disable or enable.
2531 * This routine enables the 802.1p priority re-mapping function of the switch.
2532 * That allows 802.1p priority field to be replaced with the port's default
2533 * tag's priority value if the ingress packet's 802.1p priority has a higher
2534 * priority than port's default tag's priority.
2536 static void sw_cfg_replace_vid(struct ksz_hw *hw, int port, int set)
2538 port_cfg_replace_vid(hw, port, set);
2542 * sw_cfg_port_based - configure switch port based priority
2543 * @hw: The hardware instance.
2544 * @port: The port index.
2545 * @prio: The priority to set.
2547 * This routine configures the port based priority of the switch.
2549 static void sw_cfg_port_based(struct ksz_hw *hw, int port, u8 prio)
2553 if (prio > PORT_BASED_PRIORITY_BASE)
2554 prio = PORT_BASED_PRIORITY_BASE;
2556 hw->ksz_switch->port_cfg[port].port_prio = prio;
2558 port_r16(hw, port, KS8842_PORT_CTRL_1_OFFSET, &data);
2559 data &= ~PORT_BASED_PRIORITY_MASK;
2560 data |= prio << PORT_BASED_PRIORITY_SHIFT;
2561 port_w16(hw, port, KS8842_PORT_CTRL_1_OFFSET, data);
2565 * sw_dis_multi_queue - disable transmit multiple queues
2566 * @hw: The hardware instance.
2567 * @port: The port index.
2569 * This routine disables the transmit multiple queues selection of the switch
2570 * port. Only single transmit queue on the port.
2572 static void sw_dis_multi_queue(struct ksz_hw *hw, int port)
2574 port_cfg_prio(hw, port, 0);
2578 * sw_init_prio - initialize switch priority
2579 * @hw: The hardware instance.
2581 * This routine initializes the switch QoS priority functions.
2583 static void sw_init_prio(struct ksz_hw *hw)
2587 struct ksz_switch *sw = hw->ksz_switch;
2590 * Init all the 802.1p tag priority value to be assigned to different
2593 sw->p_802_1p[0] = 0;
2594 sw->p_802_1p[1] = 0;
2595 sw->p_802_1p[2] = 1;
2596 sw->p_802_1p[3] = 1;
2597 sw->p_802_1p[4] = 2;
2598 sw->p_802_1p[5] = 2;
2599 sw->p_802_1p[6] = 3;
2600 sw->p_802_1p[7] = 3;
2603 * Init all the DiffServ priority value to be assigned to priority
2606 for (tos = 0; tos < DIFFSERV_ENTRIES; tos++)
2607 sw->diffserv[tos] = 0;
2609 /* All QoS functions disabled. */
2610 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2611 sw_dis_multi_queue(hw, port);
2612 sw_dis_diffserv(hw, port);
2613 sw_dis_802_1p(hw, port);
2614 sw_cfg_replace_vid(hw, port, 0);
2616 sw->port_cfg[port].port_prio = 0;
2617 sw_cfg_port_based(hw, port, sw->port_cfg[port].port_prio);
2619 sw_cfg_replace_null_vid(hw, 0);
2623 * port_get_def_vid - get port default VID.
2624 * @hw: The hardware instance.
2625 * @port: The port index.
2626 * @vid: Buffer to store the VID.
2628 * This routine retrieves the default VID of the port.
2630 static void port_get_def_vid(struct ksz_hw *hw, int port, u16 *vid)
2634 PORT_CTRL_ADDR(port, addr);
2635 addr += KS8842_PORT_CTRL_VID_OFFSET;
2636 *vid = readw(hw->io + addr);
2640 * sw_init_vlan - initialize switch VLAN
2641 * @hw: The hardware instance.
2643 * This routine initializes the VLAN function of the switch.
2645 static void sw_init_vlan(struct ksz_hw *hw)
2649 struct ksz_switch *sw = hw->ksz_switch;
2651 /* Read 16 VLAN entries from device's VLAN table. */
2652 for (entry = 0; entry < VLAN_TABLE_ENTRIES; entry++) {
2653 sw_r_vlan_table(hw, entry,
2654 &sw->vlan_table[entry].vid,
2655 &sw->vlan_table[entry].fid,
2656 &sw->vlan_table[entry].member);
2659 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2660 port_get_def_vid(hw, port, &sw->port_cfg[port].vid);
2661 sw->port_cfg[port].member = PORT_MASK;
2666 * sw_cfg_port_base_vlan - configure port-based VLAN membership
2667 * @hw: The hardware instance.
2668 * @port: The port index.
2669 * @member: The port-based VLAN membership.
2671 * This routine configures the port-based VLAN membership of the port.
2673 static void sw_cfg_port_base_vlan(struct ksz_hw *hw, int port, u8 member)
2678 PORT_CTRL_ADDR(port, addr);
2679 addr += KS8842_PORT_CTRL_2_OFFSET;
2681 data = readb(hw->io + addr);
2682 data &= ~PORT_VLAN_MEMBERSHIP;
2683 data |= (member & PORT_MASK);
2684 writeb(data, hw->io + addr);
2686 hw->ksz_switch->port_cfg[port].member = member;
2690 * sw_get_addr - get the switch MAC address.
2691 * @hw: The hardware instance.
2692 * @mac_addr: Buffer to store the MAC address.
2694 * This function retrieves the MAC address of the switch.
2696 static inline void sw_get_addr(struct ksz_hw *hw, u8 *mac_addr)
2700 for (i = 0; i < 6; i += 2) {
2701 mac_addr[i] = readb(hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2702 mac_addr[1 + i] = readb(hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2707 * sw_set_addr - configure switch MAC address
2708 * @hw: The hardware instance.
2709 * @mac_addr: The MAC address.
2711 * This function configures the MAC address of the switch.
2713 static void sw_set_addr(struct ksz_hw *hw, u8 *mac_addr)
2717 for (i = 0; i < 6; i += 2) {
2718 writeb(mac_addr[i], hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2719 writeb(mac_addr[1 + i], hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2724 * sw_set_global_ctrl - set switch global control
2725 * @hw: The hardware instance.
2727 * This routine sets the global control of the switch function.
2729 static void sw_set_global_ctrl(struct ksz_hw *hw)
2733 /* Enable switch MII flow control. */
2734 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2735 data |= SWITCH_FLOW_CTRL;
2736 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2738 data = readw(hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2740 /* Enable aggressive back off algorithm in half duplex mode. */
2741 data |= SWITCH_AGGR_BACKOFF;
2743 /* Enable automatic fast aging when link changed detected. */
2744 data |= SWITCH_AGING_ENABLE;
2745 data |= SWITCH_LINK_AUTO_AGING;
2747 if (hw->overrides & FAST_AGING)
2748 data |= SWITCH_FAST_AGING;
2750 data &= ~SWITCH_FAST_AGING;
2751 writew(data, hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2753 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2755 /* Enable no excessive collision drop. */
2756 data |= NO_EXC_COLLISION_DROP;
2757 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2761 STP_STATE_DISABLED = 0,
2762 STP_STATE_LISTENING,
2764 STP_STATE_FORWARDING,
2770 * port_set_stp_state - configure port spanning tree state
2771 * @hw: The hardware instance.
2772 * @port: The port index.
2773 * @state: The spanning tree state.
2775 * This routine configures the spanning tree state of the port.
2777 static void port_set_stp_state(struct ksz_hw *hw, int port, int state)
2781 port_r16(hw, port, KS8842_PORT_CTRL_2_OFFSET, &data);
2783 case STP_STATE_DISABLED:
2784 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2785 data |= PORT_LEARN_DISABLE;
2787 case STP_STATE_LISTENING:
2789 * No need to turn on transmit because of port direct mode.
2790 * Turning on receive is required if static MAC table is not setup.
2792 data &= ~PORT_TX_ENABLE;
2793 data |= PORT_RX_ENABLE;
2794 data |= PORT_LEARN_DISABLE;
2796 case STP_STATE_LEARNING:
2797 data &= ~PORT_TX_ENABLE;
2798 data |= PORT_RX_ENABLE;
2799 data &= ~PORT_LEARN_DISABLE;
2801 case STP_STATE_FORWARDING:
2802 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2803 data &= ~PORT_LEARN_DISABLE;
2805 case STP_STATE_BLOCKED:
2807 * Need to setup static MAC table with override to keep receiving BPDU
2808 * messages. See sw_init_stp routine.
2810 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2811 data |= PORT_LEARN_DISABLE;
2813 case STP_STATE_SIMPLE:
2814 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2815 data |= PORT_LEARN_DISABLE;
2818 port_w16(hw, port, KS8842_PORT_CTRL_2_OFFSET, data);
2819 hw->ksz_switch->port_cfg[port].stp_state = state;
2823 #define BROADCAST_ENTRY 1
2824 #define BRIDGE_ADDR_ENTRY 2
2825 #define IPV6_ADDR_ENTRY 3
2828 * sw_clr_sta_mac_table - clear static MAC table
2829 * @hw: The hardware instance.
2831 * This routine clears the static MAC table.
2833 static void sw_clr_sta_mac_table(struct ksz_hw *hw)
2835 struct ksz_mac_table *entry;
2838 for (i = 0; i < STATIC_MAC_TABLE_ENTRIES; i++) {
2839 entry = &hw->ksz_switch->mac_table[i];
2840 sw_w_sta_mac_table(hw, i,
2841 entry->mac_addr, entry->ports,
2843 entry->use_fid, entry->fid);
2848 * sw_init_stp - initialize switch spanning tree support
2849 * @hw: The hardware instance.
2851 * This routine initializes the spanning tree support of the switch.
2853 static void sw_init_stp(struct ksz_hw *hw)
2855 struct ksz_mac_table *entry;
2857 entry = &hw->ksz_switch->mac_table[STP_ENTRY];
2858 entry->mac_addr[0] = 0x01;
2859 entry->mac_addr[1] = 0x80;
2860 entry->mac_addr[2] = 0xC2;
2861 entry->mac_addr[3] = 0x00;
2862 entry->mac_addr[4] = 0x00;
2863 entry->mac_addr[5] = 0x00;
2864 entry->ports = HOST_MASK;
2865 entry->override = 1;
2867 sw_w_sta_mac_table(hw, STP_ENTRY,
2868 entry->mac_addr, entry->ports,
2869 entry->override, entry->valid,
2870 entry->use_fid, entry->fid);
2874 * sw_block_addr - block certain packets from the host port
2875 * @hw: The hardware instance.
2877 * This routine blocks certain packets from reaching to the host port.
2879 static void sw_block_addr(struct ksz_hw *hw)
2881 struct ksz_mac_table *entry;
2884 for (i = BROADCAST_ENTRY; i <= IPV6_ADDR_ENTRY; i++) {
2885 entry = &hw->ksz_switch->mac_table[i];
2887 sw_w_sta_mac_table(hw, i,
2888 entry->mac_addr, entry->ports,
2889 entry->override, entry->valid,
2890 entry->use_fid, entry->fid);
2894 #define PHY_LINK_SUPPORT \
2895 (PHY_AUTO_NEG_ASYM_PAUSE | \
2896 PHY_AUTO_NEG_SYM_PAUSE | \
2897 PHY_AUTO_NEG_100BT4 | \
2898 PHY_AUTO_NEG_100BTX_FD | \
2899 PHY_AUTO_NEG_100BTX | \
2900 PHY_AUTO_NEG_10BT_FD | \
2903 static inline void hw_r_phy_ctrl(struct ksz_hw *hw, int phy, u16 *data)
2905 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2908 static inline void hw_w_phy_ctrl(struct ksz_hw *hw, int phy, u16 data)
2910 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2913 static inline void hw_r_phy_link_stat(struct ksz_hw *hw, int phy, u16 *data)
2915 *data = readw(hw->io + phy + KS884X_PHY_STATUS_OFFSET);
2918 static inline void hw_r_phy_auto_neg(struct ksz_hw *hw, int phy, u16 *data)
2920 *data = readw(hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2923 static inline void hw_w_phy_auto_neg(struct ksz_hw *hw, int phy, u16 data)
2925 writew(data, hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2928 static inline void hw_r_phy_rem_cap(struct ksz_hw *hw, int phy, u16 *data)
2930 *data = readw(hw->io + phy + KS884X_PHY_REMOTE_CAP_OFFSET);
2933 static inline void hw_r_phy_crossover(struct ksz_hw *hw, int phy, u16 *data)
2935 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2938 static inline void hw_w_phy_crossover(struct ksz_hw *hw, int phy, u16 data)
2940 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2943 static inline void hw_r_phy_polarity(struct ksz_hw *hw, int phy, u16 *data)
2945 *data = readw(hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2948 static inline void hw_w_phy_polarity(struct ksz_hw *hw, int phy, u16 data)
2950 writew(data, hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2953 static inline void hw_r_phy_link_md(struct ksz_hw *hw, int phy, u16 *data)
2955 *data = readw(hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2958 static inline void hw_w_phy_link_md(struct ksz_hw *hw, int phy, u16 data)
2960 writew(data, hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2964 * hw_r_phy - read data from PHY register
2965 * @hw: The hardware instance.
2966 * @port: Port to read.
2967 * @reg: PHY register to read.
2968 * @val: Buffer to store the read data.
2970 * This routine reads data from the PHY register.
2972 static void hw_r_phy(struct ksz_hw *hw, int port, u16 reg, u16 *val)
2976 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
2977 *val = readw(hw->io + phy);
2981 * port_w_phy - write data to PHY register
2982 * @hw: The hardware instance.
2983 * @port: Port to write.
2984 * @reg: PHY register to write.
2985 * @val: Word data to write.
2987 * This routine writes data to the PHY register.
2989 static void hw_w_phy(struct ksz_hw *hw, int port, u16 reg, u16 val)
2993 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
2994 writew(val, hw->io + phy);
2998 * EEPROM access functions
3001 #define AT93C_CODE 0
3002 #define AT93C_WR_OFF 0x00
3003 #define AT93C_WR_ALL 0x10
3004 #define AT93C_ER_ALL 0x20
3005 #define AT93C_WR_ON 0x30
3007 #define AT93C_WRITE 1
3008 #define AT93C_READ 2
3009 #define AT93C_ERASE 3
3011 #define EEPROM_DELAY 4
3013 static inline void drop_gpio(struct ksz_hw *hw, u8 gpio)
3017 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3019 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3022 static inline void raise_gpio(struct ksz_hw *hw, u8 gpio)
3026 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3028 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3031 static inline u8 state_gpio(struct ksz_hw *hw, u8 gpio)
3035 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3036 return (u8)(data & gpio);
3039 static void eeprom_clk(struct ksz_hw *hw)
3041 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
3042 udelay(EEPROM_DELAY);
3043 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
3044 udelay(EEPROM_DELAY);
3047 static u16 spi_r(struct ksz_hw *hw)
3052 for (i = 15; i >= 0; i--) {
3053 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
3054 udelay(EEPROM_DELAY);
3056 temp |= (state_gpio(hw, EEPROM_DATA_IN)) ? 1 << i : 0;
3058 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
3059 udelay(EEPROM_DELAY);
3064 static void spi_w(struct ksz_hw *hw, u16 data)
3068 for (i = 15; i >= 0; i--) {
3069 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3070 drop_gpio(hw, EEPROM_DATA_OUT);
3075 static void spi_reg(struct ksz_hw *hw, u8 data, u8 reg)
3079 /* Initial start bit */
3080 raise_gpio(hw, EEPROM_DATA_OUT);
3083 /* AT93C operation */
3084 for (i = 1; i >= 0; i--) {
3085 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3086 drop_gpio(hw, EEPROM_DATA_OUT);
3090 /* Address location */
3091 for (i = 5; i >= 0; i--) {
3092 (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3093 drop_gpio(hw, EEPROM_DATA_OUT);
3098 #define EEPROM_DATA_RESERVED 0
3099 #define EEPROM_DATA_MAC_ADDR_0 1
3100 #define EEPROM_DATA_MAC_ADDR_1 2
3101 #define EEPROM_DATA_MAC_ADDR_2 3
3102 #define EEPROM_DATA_SUBSYS_ID 4
3103 #define EEPROM_DATA_SUBSYS_VEN_ID 5
3104 #define EEPROM_DATA_PM_CAP 6
3106 /* User defined EEPROM data */
3107 #define EEPROM_DATA_OTHER_MAC_ADDR 9
3110 * eeprom_read - read from AT93C46 EEPROM
3111 * @hw: The hardware instance.
3112 * @reg: The register offset.
3114 * This function reads a word from the AT93C46 EEPROM.
3116 * Return the data value.
3118 static u16 eeprom_read(struct ksz_hw *hw, u8 reg)
3122 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3124 spi_reg(hw, AT93C_READ, reg);
3127 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3133 * eeprom_write - write to AT93C46 EEPROM
3134 * @hw: The hardware instance.
3135 * @reg: The register offset.
3136 * @data: The data value.
3138 * This procedure writes a word to the AT93C46 EEPROM.
3140 static void eeprom_write(struct ksz_hw *hw, u8 reg, u16 data)
3144 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3147 spi_reg(hw, AT93C_CODE, AT93C_WR_ON);
3148 drop_gpio(hw, EEPROM_CHIP_SELECT);
3151 /* Erase the register. */
3152 raise_gpio(hw, EEPROM_CHIP_SELECT);
3153 spi_reg(hw, AT93C_ERASE, reg);
3154 drop_gpio(hw, EEPROM_CHIP_SELECT);
3157 /* Check operation complete. */
3158 raise_gpio(hw, EEPROM_CHIP_SELECT);
3163 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3164 drop_gpio(hw, EEPROM_CHIP_SELECT);
3167 /* Write the register. */
3168 raise_gpio(hw, EEPROM_CHIP_SELECT);
3169 spi_reg(hw, AT93C_WRITE, reg);
3171 drop_gpio(hw, EEPROM_CHIP_SELECT);
3174 /* Check operation complete. */
3175 raise_gpio(hw, EEPROM_CHIP_SELECT);
3180 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3181 drop_gpio(hw, EEPROM_CHIP_SELECT);
3184 /* Disable write. */
3185 raise_gpio(hw, EEPROM_CHIP_SELECT);
3186 spi_reg(hw, AT93C_CODE, AT93C_WR_OFF);
3188 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3192 * Link detection routines
3195 static u16 advertised_flow_ctrl(struct ksz_port *port, u16 ctrl)
3197 ctrl &= ~PORT_AUTO_NEG_SYM_PAUSE;
3198 switch (port->flow_ctrl) {
3200 ctrl |= PORT_AUTO_NEG_SYM_PAUSE;
3202 /* Not supported. */
3211 static void set_flow_ctrl(struct ksz_hw *hw, int rx, int tx)
3216 rx_cfg = hw->rx_cfg;
3217 tx_cfg = hw->tx_cfg;
3219 hw->rx_cfg |= DMA_RX_FLOW_ENABLE;
3221 hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE;
3223 hw->tx_cfg |= DMA_TX_FLOW_ENABLE;
3225 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3227 if (rx_cfg != hw->rx_cfg)
3228 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3229 if (tx_cfg != hw->tx_cfg)
3230 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3234 static void determine_flow_ctrl(struct ksz_hw *hw, struct ksz_port *port,
3235 u16 local, u16 remote)
3240 if (hw->overrides & PAUSE_FLOW_CTRL)
3244 if (port->force_link)
3246 if (remote & PHY_AUTO_NEG_SYM_PAUSE) {
3247 if (local & PHY_AUTO_NEG_SYM_PAUSE) {
3249 } else if ((remote & PHY_AUTO_NEG_ASYM_PAUSE) &&
3250 (local & PHY_AUTO_NEG_PAUSE) ==
3251 PHY_AUTO_NEG_ASYM_PAUSE) {
3254 } else if (remote & PHY_AUTO_NEG_ASYM_PAUSE) {
3255 if ((local & PHY_AUTO_NEG_PAUSE) == PHY_AUTO_NEG_PAUSE)
3258 if (!hw->ksz_switch)
3259 set_flow_ctrl(hw, rx, tx);
3262 static inline void port_cfg_change(struct ksz_hw *hw, struct ksz_port *port,
3263 struct ksz_port_info *info, u16 link_status)
3265 if ((hw->features & HALF_DUPLEX_SIGNAL_BUG) &&
3266 !(hw->overrides & PAUSE_FLOW_CTRL)) {
3267 u32 cfg = hw->tx_cfg;
3269 /* Disable flow control in the half duplex mode. */
3270 if (1 == info->duplex)
3271 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3272 if (hw->enabled && cfg != hw->tx_cfg)
3273 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3278 * port_get_link_speed - get current link status
3279 * @port: The port instance.
3281 * This routine reads PHY registers to determine the current link status of the
3284 static void port_get_link_speed(struct ksz_port *port)
3287 struct ksz_port_info *info;
3288 struct ksz_port_info *linked = NULL;
3289 struct ksz_hw *hw = port->hw;
3298 interrupt = hw_block_intr(hw);
3300 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3301 info = &hw->port_info[p];
3302 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3303 port_r16(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3306 * Link status is changing all the time even when there is no
3309 remote = status & (PORT_AUTO_NEG_COMPLETE |
3310 PORT_STATUS_LINK_GOOD);
3313 /* No change to status. */
3314 if (local == info->advertised && remote == info->partner)
3317 info->advertised = local;
3318 info->partner = remote;
3319 if (status & PORT_STATUS_LINK_GOOD) {
3321 /* Remember the first linked port. */
3325 info->tx_rate = 10 * TX_RATE_UNIT;
3326 if (status & PORT_STATUS_SPEED_100MBIT)
3327 info->tx_rate = 100 * TX_RATE_UNIT;
3330 if (status & PORT_STATUS_FULL_DUPLEX)
3333 if (media_connected != info->state) {
3334 hw_r_phy(hw, p, KS884X_PHY_AUTO_NEG_OFFSET,
3336 hw_r_phy(hw, p, KS884X_PHY_REMOTE_CAP_OFFSET,
3338 determine_flow_ctrl(hw, port, data, status);
3339 if (hw->ksz_switch) {
3340 port_cfg_back_pressure(hw, p,
3341 (1 == info->duplex));
3344 port_cfg_change(hw, port, info, status);
3346 info->state = media_connected;
3348 if (media_disconnected != info->state) {
3351 /* Indicate the link just goes down. */
3352 hw->port_mib[p].link_down = 1;
3354 info->state = media_disconnected;
3356 hw->port_mib[p].state = (u8) info->state;
3359 if (linked && media_disconnected == port->linked->state)
3360 port->linked = linked;
3362 hw_restore_intr(hw, interrupt);
3365 #define PHY_RESET_TIMEOUT 10
3368 * port_set_link_speed - set port speed
3369 * @port: The port instance.
3371 * This routine sets the link speed of the switch ports.
3373 static void port_set_link_speed(struct ksz_port *port)
3375 struct ksz_port_info *info;
3376 struct ksz_hw *hw = port->hw;
3383 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3384 info = &hw->port_info[p];
3386 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3387 port_r8(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3390 if (status & PORT_STATUS_LINK_GOOD)
3393 data |= PORT_AUTO_NEG_ENABLE;
3394 data = advertised_flow_ctrl(port, data);
3396 data |= PORT_AUTO_NEG_100BTX_FD | PORT_AUTO_NEG_100BTX |
3397 PORT_AUTO_NEG_10BT_FD | PORT_AUTO_NEG_10BT;
3399 /* Check if manual configuration is specified by the user. */
3400 if (port->speed || port->duplex) {
3401 if (10 == port->speed)
3402 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3403 PORT_AUTO_NEG_100BTX);
3404 else if (100 == port->speed)
3405 data &= ~(PORT_AUTO_NEG_10BT_FD |
3406 PORT_AUTO_NEG_10BT);
3407 if (1 == port->duplex)
3408 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3409 PORT_AUTO_NEG_10BT_FD);
3410 else if (2 == port->duplex)
3411 data &= ~(PORT_AUTO_NEG_100BTX |
3412 PORT_AUTO_NEG_10BT);
3415 data |= PORT_AUTO_NEG_RESTART;
3416 port_w16(hw, p, KS884X_PORT_CTRL_4_OFFSET, data);
3422 * port_force_link_speed - force port speed
3423 * @port: The port instance.
3425 * This routine forces the link speed of the switch ports.
3427 static void port_force_link_speed(struct ksz_port *port)
3429 struct ksz_hw *hw = port->hw;
3435 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3436 phy = KS884X_PHY_1_CTRL_OFFSET + p * PHY_CTRL_INTERVAL;
3437 hw_r_phy_ctrl(hw, phy, &data);
3439 data &= ~PHY_AUTO_NEG_ENABLE;
3441 if (10 == port->speed)
3442 data &= ~PHY_SPEED_100MBIT;
3443 else if (100 == port->speed)
3444 data |= PHY_SPEED_100MBIT;
3445 if (1 == port->duplex)
3446 data &= ~PHY_FULL_DUPLEX;
3447 else if (2 == port->duplex)
3448 data |= PHY_FULL_DUPLEX;
3449 hw_w_phy_ctrl(hw, phy, data);
3453 static void port_set_power_saving(struct ksz_port *port, int enable)
3455 struct ksz_hw *hw = port->hw;
3459 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++)
3461 KS884X_PORT_CTRL_4_OFFSET, PORT_POWER_DOWN, enable);
3465 * KSZ8841 power management functions
3469 * hw_chk_wol_pme_status - check PMEN pin
3470 * @hw: The hardware instance.
3472 * This function is used to check PMEN pin is asserted.
3474 * Return 1 if PMEN pin is asserted; otherwise, 0.
3476 static int hw_chk_wol_pme_status(struct ksz_hw *hw)
3478 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3479 struct pci_dev *pdev = hw_priv->pdev;
3484 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3485 return (data & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS;
3489 * hw_clr_wol_pme_status - clear PMEN pin
3490 * @hw: The hardware instance.
3492 * This routine is used to clear PME_Status to deassert PMEN pin.
3494 static void hw_clr_wol_pme_status(struct ksz_hw *hw)
3496 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3497 struct pci_dev *pdev = hw_priv->pdev;
3503 /* Clear PME_Status to deassert PMEN pin. */
3504 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3505 data |= PCI_PM_CTRL_PME_STATUS;
3506 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3510 * hw_cfg_wol_pme - enable or disable Wake-on-LAN
3511 * @hw: The hardware instance.
3512 * @set: The flag indicating whether to enable or disable.
3514 * This routine is used to enable or disable Wake-on-LAN.
3516 static void hw_cfg_wol_pme(struct ksz_hw *hw, int set)
3518 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3519 struct pci_dev *pdev = hw_priv->pdev;
3524 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3525 data &= ~PCI_PM_CTRL_STATE_MASK;
3527 data |= PCI_PM_CTRL_PME_ENABLE | PCI_D3hot;
3529 data &= ~PCI_PM_CTRL_PME_ENABLE;
3530 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3534 * hw_cfg_wol - configure Wake-on-LAN features
3535 * @hw: The hardware instance.
3536 * @frame: The pattern frame bit.
3537 * @set: The flag indicating whether to enable or disable.
3539 * This routine is used to enable or disable certain Wake-on-LAN features.
3541 static void hw_cfg_wol(struct ksz_hw *hw, u16 frame, int set)
3545 data = readw(hw->io + KS8841_WOL_CTRL_OFFSET);
3550 writew(data, hw->io + KS8841_WOL_CTRL_OFFSET);
3554 * hw_set_wol_frame - program Wake-on-LAN pattern
3555 * @hw: The hardware instance.
3556 * @i: The frame index.
3557 * @mask_size: The size of the mask.
3558 * @mask: Mask to ignore certain bytes in the pattern.
3559 * @frame_size: The size of the frame.
3560 * @pattern: The frame data.
3562 * This routine is used to program Wake-on-LAN pattern.
3564 static void hw_set_wol_frame(struct ksz_hw *hw, int i, uint mask_size,
3565 const u8 *mask, uint frame_size, const u8 *pattern)
3575 if (frame_size > mask_size * 8)
3576 frame_size = mask_size * 8;
3577 if (frame_size > 64)
3581 writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i);
3582 writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i);
3584 bits = len = from = to = 0;
3588 data[to++] = pattern[from];
3594 writeb(val, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i
3602 } while (from < (int) frame_size);
3604 bits = mask[len - 1];
3607 writeb(bits, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i + len -
3610 crc = ether_crc(to, data);
3611 writel(crc, hw->io + KS8841_WOL_FRAME_CRC_OFFSET + i);
3615 * hw_add_wol_arp - add ARP pattern
3616 * @hw: The hardware instance.
3617 * @ip_addr: The IPv4 address assigned to the device.
3619 * This routine is used to add ARP pattern for waking up the host.
3621 static void hw_add_wol_arp(struct ksz_hw *hw, const u8 *ip_addr)
3623 static const u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 };
3625 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
3626 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3628 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01,
3629 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3630 0x00, 0x00, 0x00, 0x00,
3631 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3632 0x00, 0x00, 0x00, 0x00 };
3634 memcpy(&pattern[38], ip_addr, 4);
3635 hw_set_wol_frame(hw, 3, 6, mask, 42, pattern);
3639 * hw_add_wol_bcast - add broadcast pattern
3640 * @hw: The hardware instance.
3642 * This routine is used to add broadcast pattern for waking up the host.
3644 static void hw_add_wol_bcast(struct ksz_hw *hw)
3646 static const u8 mask[] = { 0x3F };
3647 static const u8 pattern[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3649 hw_set_wol_frame(hw, 2, 1, mask, ETH_ALEN, pattern);
3653 * hw_add_wol_mcast - add multicast pattern
3654 * @hw: The hardware instance.
3656 * This routine is used to add multicast pattern for waking up the host.
3658 * It is assumed the multicast packet is the ICMPv6 neighbor solicitation used
3659 * by IPv6 ping command. Note that multicast packets are filtred through the
3660 * multicast hash table, so not all multicast packets can wake up the host.
3662 static void hw_add_wol_mcast(struct ksz_hw *hw)
3664 static const u8 mask[] = { 0x3F };
3665 u8 pattern[] = { 0x33, 0x33, 0xFF, 0x00, 0x00, 0x00 };
3667 memcpy(&pattern[3], &hw->override_addr[3], 3);
3668 hw_set_wol_frame(hw, 1, 1, mask, 6, pattern);
3672 * hw_add_wol_ucast - add unicast pattern
3673 * @hw: The hardware instance.
3675 * This routine is used to add unicast pattern to wakeup the host.
3677 * It is assumed the unicast packet is directed to the device, as the hardware
3678 * can only receive them in normal case.
3680 static void hw_add_wol_ucast(struct ksz_hw *hw)
3682 static const u8 mask[] = { 0x3F };
3684 hw_set_wol_frame(hw, 0, 1, mask, ETH_ALEN, hw->override_addr);
3688 * hw_enable_wol - enable Wake-on-LAN
3689 * @hw: The hardware instance.
3690 * @wol_enable: The Wake-on-LAN settings.
3691 * @net_addr: The IPv4 address assigned to the device.
3693 * This routine is used to enable Wake-on-LAN depending on driver settings.
3695 static void hw_enable_wol(struct ksz_hw *hw, u32 wol_enable, const u8 *net_addr)
3697 hw_cfg_wol(hw, KS8841_WOL_MAGIC_ENABLE, (wol_enable & WAKE_MAGIC));
3698 hw_cfg_wol(hw, KS8841_WOL_FRAME0_ENABLE, (wol_enable & WAKE_UCAST));
3699 hw_add_wol_ucast(hw);
3700 hw_cfg_wol(hw, KS8841_WOL_FRAME1_ENABLE, (wol_enable & WAKE_MCAST));
3701 hw_add_wol_mcast(hw);
3702 hw_cfg_wol(hw, KS8841_WOL_FRAME2_ENABLE, (wol_enable & WAKE_BCAST));
3703 hw_cfg_wol(hw, KS8841_WOL_FRAME3_ENABLE, (wol_enable & WAKE_ARP));
3704 hw_add_wol_arp(hw, net_addr);
3708 * hw_init - check driver is correct for the hardware
3709 * @hw: The hardware instance.
3711 * This function checks the hardware is correct for this driver and sets the
3712 * hardware up for proper initialization.
3714 * Return number of ports or 0 if not right.
3716 static int hw_init(struct ksz_hw *hw)
3722 /* Set bus speed to 125MHz. */
3723 writew(BUS_SPEED_125_MHZ, hw->io + KS884X_BUS_CTRL_OFFSET);
3725 /* Check KSZ884x chip ID. */
3726 data = readw(hw->io + KS884X_CHIP_ID_OFFSET);
3728 revision = (data & KS884X_REVISION_MASK) >> KS884X_REVISION_SHIFT;
3729 data &= KS884X_CHIP_ID_MASK_41;
3730 if (REG_CHIP_ID_41 == data)
3732 else if (REG_CHIP_ID_42 == data)
3737 /* Setup hardware features or bug workarounds. */
3738 if (revision <= 1) {
3739 hw->features |= SMALL_PACKET_TX_BUG;
3741 hw->features |= HALF_DUPLEX_SIGNAL_BUG;
3747 * hw_reset - reset the hardware
3748 * @hw: The hardware instance.
3750 * This routine resets the hardware.
3752 static void hw_reset(struct ksz_hw *hw)
3754 writew(GLOBAL_SOFTWARE_RESET, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3756 /* Wait for device to reset. */
3759 /* Write 0 to clear device reset. */
3760 writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3764 * hw_setup - setup the hardware
3765 * @hw: The hardware instance.
3767 * This routine setup the hardware for proper operation.
3769 static void hw_setup(struct ksz_hw *hw)
3774 /* Change default LED mode. */
3775 data = readw(hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3777 data |= SET_DEFAULT_LED;
3778 writew(data, hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3781 /* Setup transmit control. */
3782 hw->tx_cfg = (DMA_TX_PAD_ENABLE | DMA_TX_CRC_ENABLE |
3783 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_TX_ENABLE);
3785 /* Setup receive control. */
3786 hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST |
3787 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_RX_ENABLE);
3788 hw->rx_cfg |= KS884X_DMA_RX_MULTICAST;
3790 /* Hardware cannot handle UDP packet in IP fragments. */
3791 hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
3794 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
3795 if (hw->promiscuous)
3796 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
3800 * hw_setup_intr - setup interrupt mask
3801 * @hw: The hardware instance.
3803 * This routine setup the interrupt mask for proper operation.
3805 static void hw_setup_intr(struct ksz_hw *hw)
3807 hw->intr_mask = KS884X_INT_MASK | KS884X_INT_RX_OVERRUN;
3810 static void ksz_check_desc_num(struct ksz_desc_info *info)
3812 #define MIN_DESC_SHIFT 2
3814 int alloc = info->alloc;
3818 while (!(alloc & 1)) {
3822 if (alloc != 1 || shift < MIN_DESC_SHIFT) {
3823 pr_alert("Hardware descriptor numbers not right!\n");
3828 if (shift < MIN_DESC_SHIFT)
3829 shift = MIN_DESC_SHIFT;
3831 info->alloc = alloc;
3833 info->mask = info->alloc - 1;
3836 static void hw_init_desc(struct ksz_desc_info *desc_info, int transmit)
3839 u32 phys = desc_info->ring_phys;
3840 struct ksz_hw_desc *desc = desc_info->ring_virt;
3841 struct ksz_desc *cur = desc_info->ring;
3842 struct ksz_desc *previous = NULL;
3844 for (i = 0; i < desc_info->alloc; i++) {
3846 phys += desc_info->size;
3848 previous->phw->next = cpu_to_le32(phys);
3850 previous->phw->next = cpu_to_le32(desc_info->ring_phys);
3851 previous->sw.buf.rx.end_of_ring = 1;
3852 previous->phw->buf.data = cpu_to_le32(previous->sw.buf.data);
3854 desc_info->avail = desc_info->alloc;
3855 desc_info->last = desc_info->next = 0;
3857 desc_info->cur = desc_info->ring;
3861 * hw_set_desc_base - set descriptor base addresses
3862 * @hw: The hardware instance.
3863 * @tx_addr: The transmit descriptor base.
3864 * @rx_addr: The receive descriptor base.
3866 * This routine programs the descriptor base addresses after reset.
3868 static void hw_set_desc_base(struct ksz_hw *hw, u32 tx_addr, u32 rx_addr)
3870 /* Set base address of Tx/Rx descriptors. */
3871 writel(tx_addr, hw->io + KS_DMA_TX_ADDR);
3872 writel(rx_addr, hw->io + KS_DMA_RX_ADDR);
3875 static void hw_reset_pkts(struct ksz_desc_info *info)
3877 info->cur = info->ring;
3878 info->avail = info->alloc;
3879 info->last = info->next = 0;
3882 static inline void hw_resume_rx(struct ksz_hw *hw)
3884 writel(DMA_START, hw->io + KS_DMA_RX_START);
3888 * hw_start_rx - start receiving
3889 * @hw: The hardware instance.
3891 * This routine starts the receive function of the hardware.
3893 static void hw_start_rx(struct ksz_hw *hw)
3895 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3897 /* Notify when the receive stops. */
3898 hw->intr_mask |= KS884X_INT_RX_STOPPED;
3900 writel(DMA_START, hw->io + KS_DMA_RX_START);
3901 hw_ack_intr(hw, KS884X_INT_RX_STOPPED);
3904 /* Variable overflows. */
3905 if (0 == hw->rx_stop)
3910 * hw_stop_rx - stop receiving
3911 * @hw: The hardware instance.
3913 * This routine stops the receive function of the hardware.
3915 static void hw_stop_rx(struct ksz_hw *hw)
3918 hw_turn_off_intr(hw, KS884X_INT_RX_STOPPED);
3919 writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL);
3923 * hw_start_tx - start transmitting
3924 * @hw: The hardware instance.
3926 * This routine starts the transmit function of the hardware.
3928 static void hw_start_tx(struct ksz_hw *hw)
3930 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3934 * hw_stop_tx - stop transmitting
3935 * @hw: The hardware instance.
3937 * This routine stops the transmit function of the hardware.
3939 static void hw_stop_tx(struct ksz_hw *hw)
3941 writel((hw->tx_cfg & ~DMA_TX_ENABLE), hw->io + KS_DMA_TX_CTRL);
3945 * hw_disable - disable hardware
3946 * @hw: The hardware instance.
3948 * This routine disables the hardware.
3950 static void hw_disable(struct ksz_hw *hw)
3958 * hw_enable - enable hardware
3959 * @hw: The hardware instance.
3961 * This routine enables the hardware.
3963 static void hw_enable(struct ksz_hw *hw)
3971 * hw_alloc_pkt - allocate enough descriptors for transmission
3972 * @hw: The hardware instance.
3973 * @length: The length of the packet.
3974 * @physical: Number of descriptors required.
3976 * This function allocates descriptors for transmission.
3978 * Return 0 if not successful; 1 for buffer copy; or number of descriptors.
3980 static int hw_alloc_pkt(struct ksz_hw *hw, int length, int physical)
3982 /* Always leave one descriptor free. */
3983 if (hw->tx_desc_info.avail <= 1)
3986 /* Allocate a descriptor for transmission and mark it current. */
3987 get_tx_pkt(&hw->tx_desc_info, &hw->tx_desc_info.cur);
3988 hw->tx_desc_info.cur->sw.buf.tx.first_seg = 1;
3990 /* Keep track of number of transmit descriptors used so far. */
3992 hw->tx_size += length;
3994 /* Cannot hold on too much data. */
3995 if (hw->tx_size >= MAX_TX_HELD_SIZE)
3996 hw->tx_int_cnt = hw->tx_int_mask + 1;
3998 if (physical > hw->tx_desc_info.avail)
4001 return hw->tx_desc_info.avail;
4005 * hw_send_pkt - mark packet for transmission
4006 * @hw: The hardware instance.
4008 * This routine marks the packet for transmission in PCI version.
4010 static void hw_send_pkt(struct ksz_hw *hw)
4012 struct ksz_desc *cur = hw->tx_desc_info.cur;
4014 cur->sw.buf.tx.last_seg = 1;
4016 /* Interrupt only after specified number of descriptors used. */
4017 if (hw->tx_int_cnt > hw->tx_int_mask) {
4018 cur->sw.buf.tx.intr = 1;
4023 /* KSZ8842 supports port directed transmission. */
4024 cur->sw.buf.tx.dest_port = hw->dst_ports;
4028 writel(0, hw->io + KS_DMA_TX_START);
4031 static int empty_addr(u8 *addr)
4033 u32 *addr1 = (u32 *) addr;
4034 u16 *addr2 = (u16 *) &addr[4];
4036 return 0 == *addr1 && 0 == *addr2;
4040 * hw_set_addr - set MAC address
4041 * @hw: The hardware instance.
4043 * This routine programs the MAC address of the hardware when the address is
4046 static void hw_set_addr(struct ksz_hw *hw)
4050 for (i = 0; i < ETH_ALEN; i++)
4051 writeb(hw->override_addr[MAC_ADDR_ORDER(i)],
4052 hw->io + KS884X_ADDR_0_OFFSET + i);
4054 sw_set_addr(hw, hw->override_addr);
4058 * hw_read_addr - read MAC address
4059 * @hw: The hardware instance.
4061 * This routine retrieves the MAC address of the hardware.
4063 static void hw_read_addr(struct ksz_hw *hw)
4067 for (i = 0; i < ETH_ALEN; i++)
4068 hw->perm_addr[MAC_ADDR_ORDER(i)] = readb(hw->io +
4069 KS884X_ADDR_0_OFFSET + i);
4071 if (!hw->mac_override) {
4072 memcpy(hw->override_addr, hw->perm_addr, ETH_ALEN);
4073 if (empty_addr(hw->override_addr)) {
4074 memcpy(hw->perm_addr, DEFAULT_MAC_ADDRESS, ETH_ALEN);
4075 memcpy(hw->override_addr, DEFAULT_MAC_ADDRESS,
4077 hw->override_addr[5] += hw->id;
4083 static void hw_ena_add_addr(struct ksz_hw *hw, int index, u8 *mac_addr)
4090 for (i = 0; i < 2; i++) {
4092 mac_addr_hi |= mac_addr[i];
4094 mac_addr_hi |= ADD_ADDR_ENABLE;
4096 for (i = 2; i < 6; i++) {
4098 mac_addr_lo |= mac_addr[i];
4100 index *= ADD_ADDR_INCR;
4102 writel(mac_addr_lo, hw->io + index + KS_ADD_ADDR_0_LO);
4103 writel(mac_addr_hi, hw->io + index + KS_ADD_ADDR_0_HI);
4106 static void hw_set_add_addr(struct ksz_hw *hw)
4110 for (i = 0; i < ADDITIONAL_ENTRIES; i++) {
4111 if (empty_addr(hw->address[i]))
4112 writel(0, hw->io + ADD_ADDR_INCR * i +
4115 hw_ena_add_addr(hw, i, hw->address[i]);
4119 static int hw_add_addr(struct ksz_hw *hw, u8 *mac_addr)
4122 int j = ADDITIONAL_ENTRIES;
4124 if (ether_addr_equal(hw->override_addr, mac_addr))
4126 for (i = 0; i < hw->addr_list_size; i++) {
4127 if (ether_addr_equal(hw->address[i], mac_addr))
4129 if (ADDITIONAL_ENTRIES == j && empty_addr(hw->address[i]))
4132 if (j < ADDITIONAL_ENTRIES) {
4133 memcpy(hw->address[j], mac_addr, ETH_ALEN);
4134 hw_ena_add_addr(hw, j, hw->address[j]);
4140 static int hw_del_addr(struct ksz_hw *hw, u8 *mac_addr)
4144 for (i = 0; i < hw->addr_list_size; i++) {
4145 if (ether_addr_equal(hw->address[i], mac_addr)) {
4146 eth_zero_addr(hw->address[i]);
4147 writel(0, hw->io + ADD_ADDR_INCR * i +
4156 * hw_clr_multicast - clear multicast addresses
4157 * @hw: The hardware instance.
4159 * This routine removes all multicast addresses set in the hardware.
4161 static void hw_clr_multicast(struct ksz_hw *hw)
4165 for (i = 0; i < HW_MULTICAST_SIZE; i++) {
4166 hw->multi_bits[i] = 0;
4168 writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i);
4173 * hw_set_grp_addr - set multicast addresses
4174 * @hw: The hardware instance.
4176 * This routine programs multicast addresses for the hardware to accept those
4179 static void hw_set_grp_addr(struct ksz_hw *hw)
4186 memset(hw->multi_bits, 0, sizeof(u8) * HW_MULTICAST_SIZE);
4188 for (i = 0; i < hw->multi_list_size; i++) {
4189 position = (ether_crc(6, hw->multi_list[i]) >> 26) & 0x3f;
4190 index = position >> 3;
4191 value = 1 << (position & 7);
4192 hw->multi_bits[index] |= (u8) value;
4195 for (i = 0; i < HW_MULTICAST_SIZE; i++)
4196 writeb(hw->multi_bits[i], hw->io + KS884X_MULTICAST_0_OFFSET +
4201 * hw_set_multicast - enable or disable all multicast receiving
4202 * @hw: The hardware instance.
4203 * @multicast: To turn on or off the all multicast feature.
4205 * This routine enables/disables the hardware to accept all multicast packets.
4207 static void hw_set_multicast(struct ksz_hw *hw, u8 multicast)
4209 /* Stop receiving for reconfiguration. */
4213 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
4215 hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST;
4222 * hw_set_promiscuous - enable or disable promiscuous receiving
4223 * @hw: The hardware instance.
4224 * @prom: To turn on or off the promiscuous feature.
4226 * This routine enables/disables the hardware to accept all packets.
4228 static void hw_set_promiscuous(struct ksz_hw *hw, u8 prom)
4230 /* Stop receiving for reconfiguration. */
4234 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
4236 hw->rx_cfg &= ~DMA_RX_PROMISCUOUS;
4243 * sw_enable - enable the switch
4244 * @hw: The hardware instance.
4245 * @enable: The flag to enable or disable the switch
4247 * This routine is used to enable/disable the switch in KSZ8842.
4249 static void sw_enable(struct ksz_hw *hw, int enable)
4253 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4254 if (hw->dev_count > 1) {
4255 /* Set port-base vlan membership with host port. */
4256 sw_cfg_port_base_vlan(hw, port,
4257 HOST_MASK | (1 << port));
4258 port_set_stp_state(hw, port, STP_STATE_DISABLED);
4260 sw_cfg_port_base_vlan(hw, port, PORT_MASK);
4261 port_set_stp_state(hw, port, STP_STATE_FORWARDING);
4264 if (hw->dev_count > 1)
4265 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
4267 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_FORWARDING);
4270 enable = KS8842_START;
4271 writew(enable, hw->io + KS884X_CHIP_ID_OFFSET);
4275 * sw_setup - setup the switch
4276 * @hw: The hardware instance.
4278 * This routine setup the hardware switch engine for default operation.
4280 static void sw_setup(struct ksz_hw *hw)
4284 sw_set_global_ctrl(hw);
4286 /* Enable switch broadcast storm protection at 10% percent rate. */
4287 sw_init_broad_storm(hw);
4288 hw_cfg_broad_storm(hw, BROADCAST_STORM_PROTECTION_RATE);
4289 for (port = 0; port < SWITCH_PORT_NUM; port++)
4290 sw_ena_broad_storm(hw, port);
4296 sw_init_prio_rate(hw);
4300 if (hw->features & STP_SUPPORT)
4302 if (!sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
4303 SWITCH_TX_FLOW_CTRL | SWITCH_RX_FLOW_CTRL))
4304 hw->overrides |= PAUSE_FLOW_CTRL;
4309 * ksz_start_timer - start kernel timer
4310 * @info: Kernel timer information.
4311 * @time: The time tick.
4313 * This routine starts the kernel timer after the specified time tick.
4315 static void ksz_start_timer(struct ksz_timer_info *info, int time)
4318 info->timer.expires = jiffies + time;
4319 add_timer(&info->timer);
4326 * ksz_stop_timer - stop kernel timer
4327 * @info: Kernel timer information.
4329 * This routine stops the kernel timer.
4331 static void ksz_stop_timer(struct ksz_timer_info *info)
4335 del_timer_sync(&info->timer);
4339 static void ksz_init_timer(struct ksz_timer_info *info, int period,
4340 void (*function)(unsigned long), void *data)
4343 info->period = period;
4344 setup_timer(&info->timer, function, (unsigned long)data);
4347 static void ksz_update_timer(struct ksz_timer_info *info)
4350 if (info->max > 0) {
4351 if (info->cnt < info->max) {
4352 info->timer.expires = jiffies + info->period;
4353 add_timer(&info->timer);
4356 } else if (info->max < 0) {
4357 info->timer.expires = jiffies + info->period;
4358 add_timer(&info->timer);
4363 * ksz_alloc_soft_desc - allocate software descriptors
4364 * @desc_info: Descriptor information structure.
4365 * @transmit: Indication that descriptors are for transmit.
4367 * This local function allocates software descriptors for manipulation in
4370 * Return 0 if successful.
4372 static int ksz_alloc_soft_desc(struct ksz_desc_info *desc_info, int transmit)
4374 desc_info->ring = kzalloc(sizeof(struct ksz_desc) * desc_info->alloc,
4376 if (!desc_info->ring)
4378 hw_init_desc(desc_info, transmit);
4383 * ksz_alloc_desc - allocate hardware descriptors
4384 * @adapter: Adapter information structure.
4386 * This local function allocates hardware descriptors for receiving and
4389 * Return 0 if successful.
4391 static int ksz_alloc_desc(struct dev_info *adapter)
4393 struct ksz_hw *hw = &adapter->hw;
4396 /* Allocate memory for RX & TX descriptors. */
4397 adapter->desc_pool.alloc_size =
4398 hw->rx_desc_info.size * hw->rx_desc_info.alloc +
4399 hw->tx_desc_info.size * hw->tx_desc_info.alloc +
4402 adapter->desc_pool.alloc_virt =
4403 pci_zalloc_consistent(adapter->pdev,
4404 adapter->desc_pool.alloc_size,
4405 &adapter->desc_pool.dma_addr);
4406 if (adapter->desc_pool.alloc_virt == NULL) {
4407 adapter->desc_pool.alloc_size = 0;
4411 /* Align to the next cache line boundary. */
4412 offset = (((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT) ?
4414 ((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT)) : 0);
4415 adapter->desc_pool.virt = adapter->desc_pool.alloc_virt + offset;
4416 adapter->desc_pool.phys = adapter->desc_pool.dma_addr + offset;
4418 /* Allocate receive/transmit descriptors. */
4419 hw->rx_desc_info.ring_virt = (struct ksz_hw_desc *)
4420 adapter->desc_pool.virt;
4421 hw->rx_desc_info.ring_phys = adapter->desc_pool.phys;
4422 offset = hw->rx_desc_info.alloc * hw->rx_desc_info.size;
4423 hw->tx_desc_info.ring_virt = (struct ksz_hw_desc *)
4424 (adapter->desc_pool.virt + offset);
4425 hw->tx_desc_info.ring_phys = adapter->desc_pool.phys + offset;
4427 if (ksz_alloc_soft_desc(&hw->rx_desc_info, 0))
4429 if (ksz_alloc_soft_desc(&hw->tx_desc_info, 1))
4436 * free_dma_buf - release DMA buffer resources
4437 * @adapter: Adapter information structure.
4439 * This routine is just a helper function to release the DMA buffer resources.
4441 static void free_dma_buf(struct dev_info *adapter, struct ksz_dma_buf *dma_buf,
4444 pci_unmap_single(adapter->pdev, dma_buf->dma, dma_buf->len, direction);
4445 dev_kfree_skb(dma_buf->skb);
4446 dma_buf->skb = NULL;
4451 * ksz_init_rx_buffers - initialize receive descriptors
4452 * @adapter: Adapter information structure.
4454 * This routine initializes DMA buffers for receiving.
4456 static void ksz_init_rx_buffers(struct dev_info *adapter)
4459 struct ksz_desc *desc;
4460 struct ksz_dma_buf *dma_buf;
4461 struct ksz_hw *hw = &adapter->hw;
4462 struct ksz_desc_info *info = &hw->rx_desc_info;
4464 for (i = 0; i < hw->rx_desc_info.alloc; i++) {
4465 get_rx_pkt(info, &desc);
4467 dma_buf = DMA_BUFFER(desc);
4468 if (dma_buf->skb && dma_buf->len != adapter->mtu)
4469 free_dma_buf(adapter, dma_buf, PCI_DMA_FROMDEVICE);
4470 dma_buf->len = adapter->mtu;
4472 dma_buf->skb = alloc_skb(dma_buf->len, GFP_ATOMIC);
4473 if (dma_buf->skb && !dma_buf->dma)
4474 dma_buf->dma = pci_map_single(
4476 skb_tail_pointer(dma_buf->skb),
4478 PCI_DMA_FROMDEVICE);
4480 /* Set descriptor. */
4481 set_rx_buf(desc, dma_buf->dma);
4482 set_rx_len(desc, dma_buf->len);
4488 * ksz_alloc_mem - allocate memory for hardware descriptors
4489 * @adapter: Adapter information structure.
4491 * This function allocates memory for use by hardware descriptors for receiving
4494 * Return 0 if successful.
4496 static int ksz_alloc_mem(struct dev_info *adapter)
4498 struct ksz_hw *hw = &adapter->hw;
4500 /* Determine the number of receive and transmit descriptors. */
4501 hw->rx_desc_info.alloc = NUM_OF_RX_DESC;
4502 hw->tx_desc_info.alloc = NUM_OF_TX_DESC;
4504 /* Determine how many descriptors to skip transmit interrupt. */
4506 hw->tx_int_mask = NUM_OF_TX_DESC / 4;
4507 if (hw->tx_int_mask > 8)
4508 hw->tx_int_mask = 8;
4509 while (hw->tx_int_mask) {
4511 hw->tx_int_mask >>= 1;
4513 if (hw->tx_int_cnt) {
4514 hw->tx_int_mask = (1 << (hw->tx_int_cnt - 1)) - 1;
4518 /* Determine the descriptor size. */
4519 hw->rx_desc_info.size =
4520 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4521 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4522 hw->tx_desc_info.size =
4523 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4524 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4525 if (hw->rx_desc_info.size != sizeof(struct ksz_hw_desc))
4526 pr_alert("Hardware descriptor size not right!\n");
4527 ksz_check_desc_num(&hw->rx_desc_info);
4528 ksz_check_desc_num(&hw->tx_desc_info);
4530 /* Allocate descriptors. */
4531 if (ksz_alloc_desc(adapter))
4538 * ksz_free_desc - free software and hardware descriptors
4539 * @adapter: Adapter information structure.
4541 * This local routine frees the software and hardware descriptors allocated by
4544 static void ksz_free_desc(struct dev_info *adapter)
4546 struct ksz_hw *hw = &adapter->hw;
4548 /* Reset descriptor. */
4549 hw->rx_desc_info.ring_virt = NULL;
4550 hw->tx_desc_info.ring_virt = NULL;
4551 hw->rx_desc_info.ring_phys = 0;
4552 hw->tx_desc_info.ring_phys = 0;
4555 if (adapter->desc_pool.alloc_virt)
4556 pci_free_consistent(
4558 adapter->desc_pool.alloc_size,
4559 adapter->desc_pool.alloc_virt,
4560 adapter->desc_pool.dma_addr);
4562 /* Reset resource pool. */
4563 adapter->desc_pool.alloc_size = 0;
4564 adapter->desc_pool.alloc_virt = NULL;
4566 kfree(hw->rx_desc_info.ring);
4567 hw->rx_desc_info.ring = NULL;
4568 kfree(hw->tx_desc_info.ring);
4569 hw->tx_desc_info.ring = NULL;
4573 * ksz_free_buffers - free buffers used in the descriptors
4574 * @adapter: Adapter information structure.
4575 * @desc_info: Descriptor information structure.
4577 * This local routine frees buffers used in the DMA buffers.
4579 static void ksz_free_buffers(struct dev_info *adapter,
4580 struct ksz_desc_info *desc_info, int direction)
4583 struct ksz_dma_buf *dma_buf;
4584 struct ksz_desc *desc = desc_info->ring;
4586 for (i = 0; i < desc_info->alloc; i++) {
4587 dma_buf = DMA_BUFFER(desc);
4589 free_dma_buf(adapter, dma_buf, direction);
4595 * ksz_free_mem - free all resources used by descriptors
4596 * @adapter: Adapter information structure.
4598 * This local routine frees all the resources allocated by ksz_alloc_mem().
4600 static void ksz_free_mem(struct dev_info *adapter)
4602 /* Free transmit buffers. */
4603 ksz_free_buffers(adapter, &adapter->hw.tx_desc_info,
4606 /* Free receive buffers. */
4607 ksz_free_buffers(adapter, &adapter->hw.rx_desc_info,
4608 PCI_DMA_FROMDEVICE);
4610 /* Free descriptors. */
4611 ksz_free_desc(adapter);
4614 static void get_mib_counters(struct ksz_hw *hw, int first, int cnt,
4620 struct ksz_port_mib *port_mib;
4622 memset(counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
4623 for (i = 0, port = first; i < cnt; i++, port++) {
4624 port_mib = &hw->port_mib[port];
4625 for (mib = port_mib->mib_start; mib < hw->mib_cnt; mib++)
4626 counter[mib] += port_mib->counter[mib];
4631 * send_packet - send packet
4632 * @skb: Socket buffer.
4633 * @dev: Network device.
4635 * This routine is used to send a packet out to the network.
4637 static void send_packet(struct sk_buff *skb, struct net_device *dev)
4639 struct ksz_desc *desc;
4640 struct ksz_desc *first;
4641 struct dev_priv *priv = netdev_priv(dev);
4642 struct dev_info *hw_priv = priv->adapter;
4643 struct ksz_hw *hw = &hw_priv->hw;
4644 struct ksz_desc_info *info = &hw->tx_desc_info;
4645 struct ksz_dma_buf *dma_buf;
4647 int last_frag = skb_shinfo(skb)->nr_frags;
4650 * KSZ8842 with multiple device interfaces needs to be told which port
4653 if (hw->dev_count > 1)
4654 hw->dst_ports = 1 << priv->port.first_port;
4656 /* Hardware will pad the length to 60. */
4659 /* Remember the very first descriptor. */
4663 dma_buf = DMA_BUFFER(desc);
4666 skb_frag_t *this_frag;
4668 dma_buf->len = skb_headlen(skb);
4670 dma_buf->dma = pci_map_single(
4671 hw_priv->pdev, skb->data, dma_buf->len,
4673 set_tx_buf(desc, dma_buf->dma);
4674 set_tx_len(desc, dma_buf->len);
4678 this_frag = &skb_shinfo(skb)->frags[frag];
4680 /* Get a new descriptor. */
4681 get_tx_pkt(info, &desc);
4683 /* Keep track of descriptors used so far. */
4686 dma_buf = DMA_BUFFER(desc);
4687 dma_buf->len = skb_frag_size(this_frag);
4689 dma_buf->dma = pci_map_single(
4691 skb_frag_address(this_frag),
4694 set_tx_buf(desc, dma_buf->dma);
4695 set_tx_len(desc, dma_buf->len);
4698 if (frag == last_frag)
4701 /* Do not release the last descriptor here. */
4705 /* current points to the last descriptor. */
4708 /* Release the first descriptor. */
4709 release_desc(first);
4713 dma_buf->dma = pci_map_single(
4714 hw_priv->pdev, skb->data, dma_buf->len,
4716 set_tx_buf(desc, dma_buf->dma);
4717 set_tx_len(desc, dma_buf->len);
4720 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4721 (desc)->sw.buf.tx.csum_gen_tcp = 1;
4722 (desc)->sw.buf.tx.csum_gen_udp = 1;
4726 * The last descriptor holds the packet so that it can be returned to
4727 * network subsystem after all descriptors are transmitted.
4733 /* Update transmit statistics. */
4734 dev->stats.tx_packets++;
4735 dev->stats.tx_bytes += len;
4739 * transmit_cleanup - clean up transmit descriptors
4740 * @dev: Network device.
4742 * This routine is called to clean up the transmitted buffers.
4744 static void transmit_cleanup(struct dev_info *hw_priv, int normal)
4747 union desc_stat status;
4748 struct ksz_hw *hw = &hw_priv->hw;
4749 struct ksz_desc_info *info = &hw->tx_desc_info;
4750 struct ksz_desc *desc;
4751 struct ksz_dma_buf *dma_buf;
4752 struct net_device *dev = NULL;
4754 spin_lock_irq(&hw_priv->hwlock);
4757 while (info->avail < info->alloc) {
4758 /* Get next descriptor which is not hardware owned. */
4759 desc = &info->ring[last];
4760 status.data = le32_to_cpu(desc->phw->ctrl.data);
4761 if (status.tx.hw_owned) {
4765 reset_desc(desc, status);
4768 dma_buf = DMA_BUFFER(desc);
4770 hw_priv->pdev, dma_buf->dma, dma_buf->len,
4773 /* This descriptor contains the last buffer in the packet. */
4775 dev = dma_buf->skb->dev;
4777 /* Release the packet back to network subsystem. */
4778 dev_kfree_skb_irq(dma_buf->skb);
4779 dma_buf->skb = NULL;
4782 /* Free the transmitted descriptor. */
4788 spin_unlock_irq(&hw_priv->hwlock);
4790 /* Notify the network subsystem that the packet has been sent. */
4792 netif_trans_update(dev);
4796 * transmit_done - transmit done processing
4797 * @dev: Network device.
4799 * This routine is called when the transmit interrupt is triggered, indicating
4800 * either a packet is sent successfully or there are transmit errors.
4802 static void tx_done(struct dev_info *hw_priv)
4804 struct ksz_hw *hw = &hw_priv->hw;
4807 transmit_cleanup(hw_priv, 1);
4809 for (port = 0; port < hw->dev_count; port++) {
4810 struct net_device *dev = hw->port_info[port].pdev;
4812 if (netif_running(dev) && netif_queue_stopped(dev))
4813 netif_wake_queue(dev);
4817 static inline void copy_old_skb(struct sk_buff *old, struct sk_buff *skb)
4819 skb->dev = old->dev;
4820 skb->protocol = old->protocol;
4821 skb->ip_summed = old->ip_summed;
4822 skb->csum = old->csum;
4823 skb_set_network_header(skb, ETH_HLEN);
4825 dev_consume_skb_any(old);
4829 * netdev_tx - send out packet
4830 * @skb: Socket buffer.
4831 * @dev: Network device.
4833 * This function is used by the upper network layer to send out a packet.
4835 * Return 0 if successful; otherwise an error code indicating failure.
4837 static netdev_tx_t netdev_tx(struct sk_buff *skb, struct net_device *dev)
4839 struct dev_priv *priv = netdev_priv(dev);
4840 struct dev_info *hw_priv = priv->adapter;
4841 struct ksz_hw *hw = &hw_priv->hw;
4846 if (hw->features & SMALL_PACKET_TX_BUG) {
4847 struct sk_buff *org_skb = skb;
4849 if (skb->len <= 48) {
4850 if (skb_end_pointer(skb) - skb->data >= 50) {
4851 memset(&skb->data[skb->len], 0, 50 - skb->len);
4854 skb = netdev_alloc_skb(dev, 50);
4856 return NETDEV_TX_BUSY;
4857 memcpy(skb->data, org_skb->data, org_skb->len);
4858 memset(&skb->data[org_skb->len], 0,
4861 copy_old_skb(org_skb, skb);
4866 spin_lock_irq(&hw_priv->hwlock);
4868 num = skb_shinfo(skb)->nr_frags + 1;
4869 left = hw_alloc_pkt(hw, skb->len, num);
4872 (CHECKSUM_PARTIAL == skb->ip_summed &&
4873 skb->protocol == htons(ETH_P_IPV6))) {
4874 struct sk_buff *org_skb = skb;
4876 skb = netdev_alloc_skb(dev, org_skb->len);
4878 rc = NETDEV_TX_BUSY;
4881 skb_copy_and_csum_dev(org_skb, skb->data);
4882 org_skb->ip_summed = CHECKSUM_NONE;
4883 skb->len = org_skb->len;
4884 copy_old_skb(org_skb, skb);
4886 send_packet(skb, dev);
4888 netif_stop_queue(dev);
4890 /* Stop the transmit queue until packet is allocated. */
4891 netif_stop_queue(dev);
4892 rc = NETDEV_TX_BUSY;
4895 spin_unlock_irq(&hw_priv->hwlock);
4901 * netdev_tx_timeout - transmit timeout processing
4902 * @dev: Network device.
4904 * This routine is called when the transmit timer expires. That indicates the
4905 * hardware is not running correctly because transmit interrupts are not
4906 * triggered to free up resources so that the transmit routine can continue
4907 * sending out packets. The hardware is reset to correct the problem.
4909 static void netdev_tx_timeout(struct net_device *dev)
4911 static unsigned long last_reset;
4913 struct dev_priv *priv = netdev_priv(dev);
4914 struct dev_info *hw_priv = priv->adapter;
4915 struct ksz_hw *hw = &hw_priv->hw;
4918 if (hw->dev_count > 1) {
4920 * Only reset the hardware if time between calls is long
4923 if (time_before_eq(jiffies, last_reset + dev->watchdog_timeo))
4927 last_reset = jiffies;
4932 transmit_cleanup(hw_priv, 0);
4933 hw_reset_pkts(&hw->rx_desc_info);
4934 hw_reset_pkts(&hw->tx_desc_info);
4935 ksz_init_rx_buffers(hw_priv);
4939 hw_set_desc_base(hw,
4940 hw->tx_desc_info.ring_phys,
4941 hw->rx_desc_info.ring_phys);
4944 hw_set_multicast(hw, hw->all_multi);
4945 else if (hw->multi_list_size)
4946 hw_set_grp_addr(hw);
4948 if (hw->dev_count > 1) {
4949 hw_set_add_addr(hw);
4950 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4951 struct net_device *port_dev;
4953 port_set_stp_state(hw, port,
4954 STP_STATE_DISABLED);
4956 port_dev = hw->port_info[port].pdev;
4957 if (netif_running(port_dev))
4958 port_set_stp_state(hw, port,
4967 netif_trans_update(dev);
4968 netif_wake_queue(dev);
4971 static inline void csum_verified(struct sk_buff *skb)
4973 unsigned short protocol;
4976 protocol = skb->protocol;
4977 skb_reset_network_header(skb);
4978 iph = (struct iphdr *) skb_network_header(skb);
4979 if (protocol == htons(ETH_P_8021Q)) {
4980 protocol = iph->tot_len;
4981 skb_set_network_header(skb, VLAN_HLEN);
4982 iph = (struct iphdr *) skb_network_header(skb);
4984 if (protocol == htons(ETH_P_IP)) {
4985 if (iph->protocol == IPPROTO_TCP)
4986 skb->ip_summed = CHECKSUM_UNNECESSARY;
4990 static inline int rx_proc(struct net_device *dev, struct ksz_hw* hw,
4991 struct ksz_desc *desc, union desc_stat status)
4994 struct dev_priv *priv = netdev_priv(dev);
4995 struct dev_info *hw_priv = priv->adapter;
4996 struct ksz_dma_buf *dma_buf;
4997 struct sk_buff *skb;
5000 /* Received length includes 4-byte CRC. */
5001 packet_len = status.rx.frame_len - 4;
5003 dma_buf = DMA_BUFFER(desc);
5004 pci_dma_sync_single_for_cpu(
5005 hw_priv->pdev, dma_buf->dma, packet_len + 4,
5006 PCI_DMA_FROMDEVICE);
5009 /* skb->data != skb->head */
5010 skb = netdev_alloc_skb(dev, packet_len + 2);
5012 dev->stats.rx_dropped++;
5017 * Align socket buffer in 4-byte boundary for better
5020 skb_reserve(skb, 2);
5022 skb_put_data(skb, dma_buf->skb->data, packet_len);
5025 skb->protocol = eth_type_trans(skb, dev);
5027 if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP))
5030 /* Update receive statistics. */
5031 dev->stats.rx_packets++;
5032 dev->stats.rx_bytes += packet_len;
5034 /* Notify upper layer for received packet. */
5035 rx_status = netif_rx(skb);
5040 static int dev_rcv_packets(struct dev_info *hw_priv)
5043 union desc_stat status;
5044 struct ksz_hw *hw = &hw_priv->hw;
5045 struct net_device *dev = hw->port_info[0].pdev;
5046 struct ksz_desc_info *info = &hw->rx_desc_info;
5047 int left = info->alloc;
5048 struct ksz_desc *desc;
5053 /* Get next descriptor which is not hardware owned. */
5054 desc = &info->ring[next];
5055 status.data = le32_to_cpu(desc->phw->ctrl.data);
5056 if (status.rx.hw_owned)
5059 /* Status valid only when last descriptor bit is set. */
5060 if (status.rx.last_desc && status.rx.first_desc) {
5061 if (rx_proc(dev, hw, desc, status))
5062 goto release_packet;
5076 static int port_rcv_packets(struct dev_info *hw_priv)
5079 union desc_stat status;
5080 struct ksz_hw *hw = &hw_priv->hw;
5081 struct net_device *dev = hw->port_info[0].pdev;
5082 struct ksz_desc_info *info = &hw->rx_desc_info;
5083 int left = info->alloc;
5084 struct ksz_desc *desc;
5089 /* Get next descriptor which is not hardware owned. */
5090 desc = &info->ring[next];
5091 status.data = le32_to_cpu(desc->phw->ctrl.data);
5092 if (status.rx.hw_owned)
5095 if (hw->dev_count > 1) {
5096 /* Get received port number. */
5097 int p = HW_TO_DEV_PORT(status.rx.src_port);
5099 dev = hw->port_info[p].pdev;
5100 if (!netif_running(dev))
5101 goto release_packet;
5104 /* Status valid only when last descriptor bit is set. */
5105 if (status.rx.last_desc && status.rx.first_desc) {
5106 if (rx_proc(dev, hw, desc, status))
5107 goto release_packet;
5121 static int dev_rcv_special(struct dev_info *hw_priv)
5124 union desc_stat status;
5125 struct ksz_hw *hw = &hw_priv->hw;
5126 struct net_device *dev = hw->port_info[0].pdev;
5127 struct ksz_desc_info *info = &hw->rx_desc_info;
5128 int left = info->alloc;
5129 struct ksz_desc *desc;
5134 /* Get next descriptor which is not hardware owned. */
5135 desc = &info->ring[next];
5136 status.data = le32_to_cpu(desc->phw->ctrl.data);
5137 if (status.rx.hw_owned)
5140 if (hw->dev_count > 1) {
5141 /* Get received port number. */
5142 int p = HW_TO_DEV_PORT(status.rx.src_port);
5144 dev = hw->port_info[p].pdev;
5145 if (!netif_running(dev))
5146 goto release_packet;
5149 /* Status valid only when last descriptor bit is set. */
5150 if (status.rx.last_desc && status.rx.first_desc) {
5152 * Receive without error. With receive errors
5153 * disabled, packets with receive errors will be
5154 * dropped, so no need to check the error bit.
5156 if (!status.rx.error || (status.data &
5157 KS_DESC_RX_ERROR_COND) ==
5158 KS_DESC_RX_ERROR_TOO_LONG) {
5159 if (rx_proc(dev, hw, desc, status))
5160 goto release_packet;
5163 struct dev_priv *priv = netdev_priv(dev);
5165 /* Update receive error statistics. */
5166 priv->port.counter[OID_COUNTER_RCV_ERROR]++;
5180 static void rx_proc_task(unsigned long data)
5182 struct dev_info *hw_priv = (struct dev_info *) data;
5183 struct ksz_hw *hw = &hw_priv->hw;
5187 if (unlikely(!hw_priv->dev_rcv(hw_priv))) {
5189 /* In case receive process is suspended because of overrun. */
5192 /* tasklets are interruptible. */
5193 spin_lock_irq(&hw_priv->hwlock);
5194 hw_turn_on_intr(hw, KS884X_INT_RX_MASK);
5195 spin_unlock_irq(&hw_priv->hwlock);
5197 hw_ack_intr(hw, KS884X_INT_RX);
5198 tasklet_schedule(&hw_priv->rx_tasklet);
5202 static void tx_proc_task(unsigned long data)
5204 struct dev_info *hw_priv = (struct dev_info *) data;
5205 struct ksz_hw *hw = &hw_priv->hw;
5207 hw_ack_intr(hw, KS884X_INT_TX_MASK);
5211 /* tasklets are interruptible. */
5212 spin_lock_irq(&hw_priv->hwlock);
5213 hw_turn_on_intr(hw, KS884X_INT_TX);
5214 spin_unlock_irq(&hw_priv->hwlock);
5217 static inline void handle_rx_stop(struct ksz_hw *hw)
5219 /* Receive just has been stopped. */
5220 if (0 == hw->rx_stop)
5221 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5222 else if (hw->rx_stop > 1) {
5223 if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) {
5226 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5230 /* Receive just has been started. */
5235 * netdev_intr - interrupt handling
5236 * @irq: Interrupt number.
5237 * @dev_id: Network device.
5239 * This function is called by upper network layer to signal interrupt.
5241 * Return IRQ_HANDLED if interrupt is handled.
5243 static irqreturn_t netdev_intr(int irq, void *dev_id)
5245 uint int_enable = 0;
5246 struct net_device *dev = (struct net_device *) dev_id;
5247 struct dev_priv *priv = netdev_priv(dev);
5248 struct dev_info *hw_priv = priv->adapter;
5249 struct ksz_hw *hw = &hw_priv->hw;
5251 spin_lock(&hw_priv->hwlock);
5253 hw_read_intr(hw, &int_enable);
5255 /* Not our interrupt! */
5257 spin_unlock(&hw_priv->hwlock);
5262 hw_ack_intr(hw, int_enable);
5263 int_enable &= hw->intr_mask;
5265 if (unlikely(int_enable & KS884X_INT_TX_MASK)) {
5266 hw_dis_intr_bit(hw, KS884X_INT_TX_MASK);
5267 tasklet_schedule(&hw_priv->tx_tasklet);
5270 if (likely(int_enable & KS884X_INT_RX)) {
5271 hw_dis_intr_bit(hw, KS884X_INT_RX);
5272 tasklet_schedule(&hw_priv->rx_tasklet);
5275 if (unlikely(int_enable & KS884X_INT_RX_OVERRUN)) {
5276 dev->stats.rx_fifo_errors++;
5280 if (unlikely(int_enable & KS884X_INT_PHY)) {
5281 struct ksz_port *port = &priv->port;
5283 hw->features |= LINK_INT_WORKING;
5284 port_get_link_speed(port);
5287 if (unlikely(int_enable & KS884X_INT_RX_STOPPED)) {
5292 if (unlikely(int_enable & KS884X_INT_TX_STOPPED)) {
5295 hw->intr_mask &= ~KS884X_INT_TX_STOPPED;
5296 pr_info("Tx stopped\n");
5297 data = readl(hw->io + KS_DMA_TX_CTRL);
5298 if (!(data & DMA_TX_ENABLE))
5299 pr_info("Tx disabled\n");
5306 spin_unlock(&hw_priv->hwlock);
5312 * Linux network device functions
5315 static unsigned long next_jiffies;
5317 #ifdef CONFIG_NET_POLL_CONTROLLER
5318 static void netdev_netpoll(struct net_device *dev)
5320 struct dev_priv *priv = netdev_priv(dev);
5321 struct dev_info *hw_priv = priv->adapter;
5323 hw_dis_intr(&hw_priv->hw);
5324 netdev_intr(dev->irq, dev);
5328 static void bridge_change(struct ksz_hw *hw)
5332 struct ksz_switch *sw = hw->ksz_switch;
5334 /* No ports in forwarding state. */
5336 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
5339 for (port = 0; port < SWITCH_PORT_NUM; port++) {
5340 if (STP_STATE_FORWARDING == sw->port_cfg[port].stp_state)
5341 member = HOST_MASK | sw->member;
5343 member = HOST_MASK | (1 << port);
5344 if (member != sw->port_cfg[port].member)
5345 sw_cfg_port_base_vlan(hw, port, member);
5350 * netdev_close - close network device
5351 * @dev: Network device.
5353 * This function process the close operation of network device. This is caused
5354 * by the user command "ifconfig ethX down."
5356 * Return 0 if successful; otherwise an error code indicating failure.
5358 static int netdev_close(struct net_device *dev)
5360 struct dev_priv *priv = netdev_priv(dev);
5361 struct dev_info *hw_priv = priv->adapter;
5362 struct ksz_port *port = &priv->port;
5363 struct ksz_hw *hw = &hw_priv->hw;
5366 netif_stop_queue(dev);
5368 ksz_stop_timer(&priv->monitor_timer_info);
5370 /* Need to shut the port manually in multiple device interfaces mode. */
5371 if (hw->dev_count > 1) {
5372 port_set_stp_state(hw, port->first_port, STP_STATE_DISABLED);
5374 /* Port is closed. Need to change bridge setting. */
5375 if (hw->features & STP_SUPPORT) {
5376 pi = 1 << port->first_port;
5377 if (hw->ksz_switch->member & pi) {
5378 hw->ksz_switch->member &= ~pi;
5383 if (port->first_port > 0)
5384 hw_del_addr(hw, dev->dev_addr);
5385 if (!hw_priv->wol_enable)
5386 port_set_power_saving(port, true);
5388 if (priv->multicast)
5390 if (priv->promiscuous)
5394 if (!(hw_priv->opened)) {
5395 ksz_stop_timer(&hw_priv->mib_timer_info);
5396 flush_work(&hw_priv->mib_read);
5400 hw_clr_multicast(hw);
5402 /* Delay for receive task to stop scheduling itself. */
5405 tasklet_kill(&hw_priv->rx_tasklet);
5406 tasklet_kill(&hw_priv->tx_tasklet);
5407 free_irq(dev->irq, hw_priv->dev);
5409 transmit_cleanup(hw_priv, 0);
5410 hw_reset_pkts(&hw->rx_desc_info);
5411 hw_reset_pkts(&hw->tx_desc_info);
5413 /* Clean out static MAC table when the switch is shutdown. */
5414 if (hw->features & STP_SUPPORT)
5415 sw_clr_sta_mac_table(hw);
5421 static void hw_cfg_huge_frame(struct dev_info *hw_priv, struct ksz_hw *hw)
5423 if (hw->ksz_switch) {
5426 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5427 if (hw->features & RX_HUGE_FRAME)
5428 data |= SWITCH_HUGE_PACKET;
5430 data &= ~SWITCH_HUGE_PACKET;
5431 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5433 if (hw->features & RX_HUGE_FRAME) {
5434 hw->rx_cfg |= DMA_RX_ERROR;
5435 hw_priv->dev_rcv = dev_rcv_special;
5437 hw->rx_cfg &= ~DMA_RX_ERROR;
5438 if (hw->dev_count > 1)
5439 hw_priv->dev_rcv = port_rcv_packets;
5441 hw_priv->dev_rcv = dev_rcv_packets;
5445 static int prepare_hardware(struct net_device *dev)
5447 struct dev_priv *priv = netdev_priv(dev);
5448 struct dev_info *hw_priv = priv->adapter;
5449 struct ksz_hw *hw = &hw_priv->hw;
5452 /* Remember the network device that requests interrupts. */
5454 rc = request_irq(dev->irq, netdev_intr, IRQF_SHARED, dev->name, dev);
5457 tasklet_init(&hw_priv->rx_tasklet, rx_proc_task,
5458 (unsigned long) hw_priv);
5459 tasklet_init(&hw_priv->tx_tasklet, tx_proc_task,
5460 (unsigned long) hw_priv);
5462 hw->promiscuous = 0;
5464 hw->multi_list_size = 0;
5468 hw_set_desc_base(hw,
5469 hw->tx_desc_info.ring_phys, hw->rx_desc_info.ring_phys);
5471 hw_cfg_huge_frame(hw_priv, hw);
5472 ksz_init_rx_buffers(hw_priv);
5476 static void set_media_state(struct net_device *dev, int media_state)
5478 struct dev_priv *priv = netdev_priv(dev);
5480 if (media_state == priv->media_state)
5481 netif_carrier_on(dev);
5483 netif_carrier_off(dev);
5484 netif_info(priv, link, dev, "link %s\n",
5485 media_state == priv->media_state ? "on" : "off");
5489 * netdev_open - open network device
5490 * @dev: Network device.
5492 * This function process the open operation of network device. This is caused
5493 * by the user command "ifconfig ethX up."
5495 * Return 0 if successful; otherwise an error code indicating failure.
5497 static int netdev_open(struct net_device *dev)
5499 struct dev_priv *priv = netdev_priv(dev);
5500 struct dev_info *hw_priv = priv->adapter;
5501 struct ksz_hw *hw = &hw_priv->hw;
5502 struct ksz_port *port = &priv->port;
5507 priv->multicast = 0;
5508 priv->promiscuous = 0;
5510 /* Reset device statistics. */
5511 memset(&dev->stats, 0, sizeof(struct net_device_stats));
5512 memset((void *) port->counter, 0,
5513 (sizeof(u64) * OID_COUNTER_LAST));
5515 if (!(hw_priv->opened)) {
5516 rc = prepare_hardware(dev);
5519 for (i = 0; i < hw->mib_port_cnt; i++) {
5520 if (next_jiffies < jiffies)
5521 next_jiffies = jiffies + HZ * 2;
5523 next_jiffies += HZ * 1;
5524 hw_priv->counter[i].time = next_jiffies;
5525 hw->port_mib[i].state = media_disconnected;
5526 port_init_cnt(hw, i);
5529 hw->port_mib[HOST_PORT].state = media_connected;
5531 hw_add_wol_bcast(hw);
5532 hw_cfg_wol_pme(hw, 0);
5533 hw_clr_wol_pme_status(&hw_priv->hw);
5536 port_set_power_saving(port, false);
5538 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
5540 * Initialize to invalid value so that link detection
5543 hw->port_info[p].partner = 0xFF;
5544 hw->port_info[p].state = media_disconnected;
5547 /* Need to open the port in multiple device interfaces mode. */
5548 if (hw->dev_count > 1) {
5549 port_set_stp_state(hw, port->first_port, STP_STATE_SIMPLE);
5550 if (port->first_port > 0)
5551 hw_add_addr(hw, dev->dev_addr);
5554 port_get_link_speed(port);
5555 if (port->force_link)
5556 port_force_link_speed(port);
5558 port_set_link_speed(port);
5560 if (!(hw_priv->opened)) {
5565 if (hw->mib_port_cnt)
5566 ksz_start_timer(&hw_priv->mib_timer_info,
5567 hw_priv->mib_timer_info.period);
5572 ksz_start_timer(&priv->monitor_timer_info,
5573 priv->monitor_timer_info.period);
5575 priv->media_state = port->linked->state;
5577 set_media_state(dev, media_connected);
5578 netif_start_queue(dev);
5583 /* RX errors = rx_errors */
5584 /* RX dropped = rx_dropped */
5585 /* RX overruns = rx_fifo_errors */
5586 /* RX frame = rx_crc_errors + rx_frame_errors + rx_length_errors */
5587 /* TX errors = tx_errors */
5588 /* TX dropped = tx_dropped */
5589 /* TX overruns = tx_fifo_errors */
5590 /* TX carrier = tx_aborted_errors + tx_carrier_errors + tx_window_errors */
5591 /* collisions = collisions */
5594 * netdev_query_statistics - query network device statistics
5595 * @dev: Network device.
5597 * This function returns the statistics of the network device. The device
5598 * needs not be opened.
5600 * Return network device statistics.
5602 static struct net_device_stats *netdev_query_statistics(struct net_device *dev)
5604 struct dev_priv *priv = netdev_priv(dev);
5605 struct ksz_port *port = &priv->port;
5606 struct ksz_hw *hw = &priv->adapter->hw;
5607 struct ksz_port_mib *mib;
5611 dev->stats.rx_errors = port->counter[OID_COUNTER_RCV_ERROR];
5612 dev->stats.tx_errors = port->counter[OID_COUNTER_XMIT_ERROR];
5614 /* Reset to zero to add count later. */
5615 dev->stats.multicast = 0;
5616 dev->stats.collisions = 0;
5617 dev->stats.rx_length_errors = 0;
5618 dev->stats.rx_crc_errors = 0;
5619 dev->stats.rx_frame_errors = 0;
5620 dev->stats.tx_window_errors = 0;
5622 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
5623 mib = &hw->port_mib[p];
5625 dev->stats.multicast += (unsigned long)
5626 mib->counter[MIB_COUNTER_RX_MULTICAST];
5628 dev->stats.collisions += (unsigned long)
5629 mib->counter[MIB_COUNTER_TX_TOTAL_COLLISION];
5631 dev->stats.rx_length_errors += (unsigned long)(
5632 mib->counter[MIB_COUNTER_RX_UNDERSIZE] +
5633 mib->counter[MIB_COUNTER_RX_FRAGMENT] +
5634 mib->counter[MIB_COUNTER_RX_OVERSIZE] +
5635 mib->counter[MIB_COUNTER_RX_JABBER]);
5636 dev->stats.rx_crc_errors += (unsigned long)
5637 mib->counter[MIB_COUNTER_RX_CRC_ERR];
5638 dev->stats.rx_frame_errors += (unsigned long)(
5639 mib->counter[MIB_COUNTER_RX_ALIGNMENT_ERR] +
5640 mib->counter[MIB_COUNTER_RX_SYMBOL_ERR]);
5642 dev->stats.tx_window_errors += (unsigned long)
5643 mib->counter[MIB_COUNTER_TX_LATE_COLLISION];
5650 * netdev_set_mac_address - set network device MAC address
5651 * @dev: Network device.
5652 * @addr: Buffer of MAC address.
5654 * This function is used to set the MAC address of the network device.
5656 * Return 0 to indicate success.
5658 static int netdev_set_mac_address(struct net_device *dev, void *addr)
5660 struct dev_priv *priv = netdev_priv(dev);
5661 struct dev_info *hw_priv = priv->adapter;
5662 struct ksz_hw *hw = &hw_priv->hw;
5663 struct sockaddr *mac = addr;
5666 if (priv->port.first_port > 0)
5667 hw_del_addr(hw, dev->dev_addr);
5669 hw->mac_override = 1;
5670 memcpy(hw->override_addr, mac->sa_data, ETH_ALEN);
5673 memcpy(dev->dev_addr, mac->sa_data, ETH_ALEN);
5675 interrupt = hw_block_intr(hw);
5677 if (priv->port.first_port > 0)
5678 hw_add_addr(hw, dev->dev_addr);
5681 hw_restore_intr(hw, interrupt);
5686 static void dev_set_promiscuous(struct net_device *dev, struct dev_priv *priv,
5687 struct ksz_hw *hw, int promiscuous)
5689 if (promiscuous != priv->promiscuous) {
5690 u8 prev_state = hw->promiscuous;
5696 priv->promiscuous = promiscuous;
5698 /* Turn on/off promiscuous mode. */
5699 if (hw->promiscuous <= 1 && prev_state <= 1)
5700 hw_set_promiscuous(hw, hw->promiscuous);
5703 * Port is not in promiscuous mode, meaning it is released
5706 if ((hw->features & STP_SUPPORT) && !promiscuous &&
5707 (dev->priv_flags & IFF_BRIDGE_PORT)) {
5708 struct ksz_switch *sw = hw->ksz_switch;
5709 int port = priv->port.first_port;
5711 port_set_stp_state(hw, port, STP_STATE_DISABLED);
5713 if (sw->member & port) {
5714 sw->member &= ~port;
5721 static void dev_set_multicast(struct dev_priv *priv, struct ksz_hw *hw,
5724 if (multicast != priv->multicast) {
5725 u8 all_multi = hw->all_multi;
5731 priv->multicast = multicast;
5733 /* Turn on/off all multicast mode. */
5734 if (hw->all_multi <= 1 && all_multi <= 1)
5735 hw_set_multicast(hw, hw->all_multi);
5740 * netdev_set_rx_mode
5741 * @dev: Network device.
5743 * This routine is used to set multicast addresses or put the network device
5744 * into promiscuous mode.
5746 static void netdev_set_rx_mode(struct net_device *dev)
5748 struct dev_priv *priv = netdev_priv(dev);
5749 struct dev_info *hw_priv = priv->adapter;
5750 struct ksz_hw *hw = &hw_priv->hw;
5751 struct netdev_hw_addr *ha;
5752 int multicast = (dev->flags & IFF_ALLMULTI);
5754 dev_set_promiscuous(dev, priv, hw, (dev->flags & IFF_PROMISC));
5756 if (hw_priv->hw.dev_count > 1)
5757 multicast |= (dev->flags & IFF_MULTICAST);
5758 dev_set_multicast(priv, hw, multicast);
5760 /* Cannot use different hashes in multiple device interfaces mode. */
5761 if (hw_priv->hw.dev_count > 1)
5764 if ((dev->flags & IFF_MULTICAST) && !netdev_mc_empty(dev)) {
5767 /* List too big to support so turn on all multicast mode. */
5768 if (netdev_mc_count(dev) > MAX_MULTICAST_LIST) {
5769 if (MAX_MULTICAST_LIST != hw->multi_list_size) {
5770 hw->multi_list_size = MAX_MULTICAST_LIST;
5772 hw_set_multicast(hw, hw->all_multi);
5777 netdev_for_each_mc_addr(ha, dev) {
5778 if (i >= MAX_MULTICAST_LIST)
5780 memcpy(hw->multi_list[i++], ha->addr, ETH_ALEN);
5782 hw->multi_list_size = (u8) i;
5783 hw_set_grp_addr(hw);
5785 if (MAX_MULTICAST_LIST == hw->multi_list_size) {
5787 hw_set_multicast(hw, hw->all_multi);
5789 hw->multi_list_size = 0;
5790 hw_clr_multicast(hw);
5794 static int netdev_change_mtu(struct net_device *dev, int new_mtu)
5796 struct dev_priv *priv = netdev_priv(dev);
5797 struct dev_info *hw_priv = priv->adapter;
5798 struct ksz_hw *hw = &hw_priv->hw;
5801 if (netif_running(dev))
5804 /* Cannot use different MTU in multiple device interfaces mode. */
5805 if (hw->dev_count > 1)
5806 if (dev != hw_priv->dev)
5809 hw_mtu = new_mtu + ETHERNET_HEADER_SIZE + 4;
5810 if (hw_mtu > REGULAR_RX_BUF_SIZE) {
5811 hw->features |= RX_HUGE_FRAME;
5812 hw_mtu = MAX_RX_BUF_SIZE;
5814 hw->features &= ~RX_HUGE_FRAME;
5815 hw_mtu = REGULAR_RX_BUF_SIZE;
5817 hw_mtu = (hw_mtu + 3) & ~3;
5818 hw_priv->mtu = hw_mtu;
5825 * netdev_ioctl - I/O control processing
5826 * @dev: Network device.
5827 * @ifr: Interface request structure.
5828 * @cmd: I/O control code.
5830 * This function is used to process I/O control calls.
5832 * Return 0 to indicate success.
5834 static int netdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5836 struct dev_priv *priv = netdev_priv(dev);
5837 struct dev_info *hw_priv = priv->adapter;
5838 struct ksz_hw *hw = &hw_priv->hw;
5839 struct ksz_port *port = &priv->port;
5841 struct mii_ioctl_data *data = if_mii(ifr);
5843 if (down_interruptible(&priv->proc_sem))
5844 return -ERESTARTSYS;
5847 /* Get address of MII PHY in use. */
5849 data->phy_id = priv->id;
5851 /* Fallthrough... */
5853 /* Read MII PHY register. */
5855 if (data->phy_id != priv->id || data->reg_num >= 6)
5858 hw_r_phy(hw, port->linked->port_id, data->reg_num,
5862 /* Write MII PHY register. */
5864 if (!capable(CAP_NET_ADMIN))
5866 else if (data->phy_id != priv->id || data->reg_num >= 6)
5869 hw_w_phy(hw, port->linked->port_id, data->reg_num,
5874 result = -EOPNOTSUPP;
5877 up(&priv->proc_sem);
5887 * mdio_read - read PHY register
5888 * @dev: Network device.
5889 * @phy_id: The PHY id.
5890 * @reg_num: The register number.
5892 * This function returns the PHY register value.
5894 * Return the register value.
5896 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
5898 struct dev_priv *priv = netdev_priv(dev);
5899 struct ksz_port *port = &priv->port;
5900 struct ksz_hw *hw = port->hw;
5903 hw_r_phy(hw, port->linked->port_id, reg_num << 1, &val_out);
5908 * mdio_write - set PHY register
5909 * @dev: Network device.
5910 * @phy_id: The PHY id.
5911 * @reg_num: The register number.
5912 * @val: The register value.
5914 * This procedure sets the PHY register value.
5916 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
5918 struct dev_priv *priv = netdev_priv(dev);
5919 struct ksz_port *port = &priv->port;
5920 struct ksz_hw *hw = port->hw;
5924 for (i = 0, pi = port->first_port; i < port->port_cnt; i++, pi++)
5925 hw_w_phy(hw, pi, reg_num << 1, val);
5932 #define EEPROM_SIZE 0x40
5934 static u16 eeprom_data[EEPROM_SIZE] = { 0 };
5936 #define ADVERTISED_ALL \
5937 (ADVERTISED_10baseT_Half | \
5938 ADVERTISED_10baseT_Full | \
5939 ADVERTISED_100baseT_Half | \
5940 ADVERTISED_100baseT_Full)
5942 /* These functions use the MII functions in mii.c. */
5945 * netdev_get_link_ksettings - get network device settings
5946 * @dev: Network device.
5947 * @cmd: Ethtool command.
5949 * This function queries the PHY and returns its state in the ethtool command.
5951 * Return 0 if successful; otherwise an error code.
5953 static int netdev_get_link_ksettings(struct net_device *dev,
5954 struct ethtool_link_ksettings *cmd)
5956 struct dev_priv *priv = netdev_priv(dev);
5957 struct dev_info *hw_priv = priv->adapter;
5959 mutex_lock(&hw_priv->lock);
5960 mii_ethtool_get_link_ksettings(&priv->mii_if, cmd);
5961 ethtool_link_ksettings_add_link_mode(cmd, advertising, TP);
5962 mutex_unlock(&hw_priv->lock);
5964 /* Save advertised settings for workaround in next function. */
5965 ethtool_convert_link_mode_to_legacy_u32(&priv->advertising,
5966 cmd->link_modes.advertising);
5972 * netdev_set_link_ksettings - set network device settings
5973 * @dev: Network device.
5974 * @cmd: Ethtool command.
5976 * This function sets the PHY according to the ethtool command.
5978 * Return 0 if successful; otherwise an error code.
5980 static int netdev_set_link_ksettings(struct net_device *dev,
5981 const struct ethtool_link_ksettings *cmd)
5983 struct dev_priv *priv = netdev_priv(dev);
5984 struct dev_info *hw_priv = priv->adapter;
5985 struct ksz_port *port = &priv->port;
5986 struct ethtool_link_ksettings copy_cmd;
5987 u32 speed = cmd->base.speed;
5991 ethtool_convert_link_mode_to_legacy_u32(&advertising,
5992 cmd->link_modes.advertising);
5995 * ethtool utility does not change advertised setting if auto
5996 * negotiation is not specified explicitly.
5998 if (cmd->base.autoneg && priv->advertising == advertising) {
5999 advertising |= ADVERTISED_ALL;
6002 ~(ADVERTISED_100baseT_Full |
6003 ADVERTISED_100baseT_Half);
6004 else if (100 == speed)
6006 ~(ADVERTISED_10baseT_Full |
6007 ADVERTISED_10baseT_Half);
6008 if (0 == cmd->base.duplex)
6010 ~(ADVERTISED_100baseT_Full |
6011 ADVERTISED_10baseT_Full);
6012 else if (1 == cmd->base.duplex)
6014 ~(ADVERTISED_100baseT_Half |
6015 ADVERTISED_10baseT_Half);
6017 mutex_lock(&hw_priv->lock);
6018 if (cmd->base.autoneg &&
6019 (advertising & ADVERTISED_ALL) == ADVERTISED_ALL) {
6022 port->force_link = 0;
6024 port->duplex = cmd->base.duplex + 1;
6026 port->speed = speed;
6027 if (cmd->base.autoneg)
6028 port->force_link = 0;
6030 port->force_link = 1;
6033 memcpy(©_cmd, cmd, sizeof(copy_cmd));
6034 ethtool_convert_legacy_u32_to_link_mode(copy_cmd.link_modes.advertising,
6036 rc = mii_ethtool_set_link_ksettings(
6038 (const struct ethtool_link_ksettings *)©_cmd);
6039 mutex_unlock(&hw_priv->lock);
6044 * netdev_nway_reset - restart auto-negotiation
6045 * @dev: Network device.
6047 * This function restarts the PHY for auto-negotiation.
6049 * Return 0 if successful; otherwise an error code.
6051 static int netdev_nway_reset(struct net_device *dev)
6053 struct dev_priv *priv = netdev_priv(dev);
6054 struct dev_info *hw_priv = priv->adapter;
6057 mutex_lock(&hw_priv->lock);
6058 rc = mii_nway_restart(&priv->mii_if);
6059 mutex_unlock(&hw_priv->lock);
6064 * netdev_get_link - get network device link status
6065 * @dev: Network device.
6067 * This function gets the link status from the PHY.
6069 * Return true if PHY is linked and false otherwise.
6071 static u32 netdev_get_link(struct net_device *dev)
6073 struct dev_priv *priv = netdev_priv(dev);
6076 rc = mii_link_ok(&priv->mii_if);
6081 * netdev_get_drvinfo - get network driver information
6082 * @dev: Network device.
6083 * @info: Ethtool driver info data structure.
6085 * This procedure returns the driver information.
6087 static void netdev_get_drvinfo(struct net_device *dev,
6088 struct ethtool_drvinfo *info)
6090 struct dev_priv *priv = netdev_priv(dev);
6091 struct dev_info *hw_priv = priv->adapter;
6093 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
6094 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
6095 strlcpy(info->bus_info, pci_name(hw_priv->pdev),
6096 sizeof(info->bus_info));
6100 * netdev_get_regs_len - get length of register dump
6101 * @dev: Network device.
6103 * This function returns the length of the register dump.
6105 * Return length of the register dump.
6107 static struct hw_regs {
6110 } hw_regs_range[] = {
6111 { KS_DMA_TX_CTRL, KS884X_INTERRUPTS_STATUS },
6112 { KS_ADD_ADDR_0_LO, KS_ADD_ADDR_F_HI },
6113 { KS884X_ADDR_0_OFFSET, KS8841_WOL_FRAME_BYTE2_OFFSET },
6114 { KS884X_SIDER_P, KS8842_SGCR7_P },
6115 { KS8842_MACAR1_P, KS8842_TOSR8_P },
6116 { KS884X_P1MBCR_P, KS8842_P3ERCR_P },
6120 static int netdev_get_regs_len(struct net_device *dev)
6122 struct hw_regs *range = hw_regs_range;
6123 int regs_len = 0x10 * sizeof(u32);
6125 while (range->end > range->start) {
6126 regs_len += (range->end - range->start + 3) / 4 * 4;
6133 * netdev_get_regs - get register dump
6134 * @dev: Network device.
6135 * @regs: Ethtool registers data structure.
6136 * @ptr: Buffer to store the register values.
6138 * This procedure dumps the register values in the provided buffer.
6140 static void netdev_get_regs(struct net_device *dev, struct ethtool_regs *regs,
6143 struct dev_priv *priv = netdev_priv(dev);
6144 struct dev_info *hw_priv = priv->adapter;
6145 struct ksz_hw *hw = &hw_priv->hw;
6146 int *buf = (int *) ptr;
6147 struct hw_regs *range = hw_regs_range;
6150 mutex_lock(&hw_priv->lock);
6152 for (len = 0; len < 0x40; len += 4) {
6153 pci_read_config_dword(hw_priv->pdev, len, buf);
6156 while (range->end > range->start) {
6157 for (len = range->start; len < range->end; len += 4) {
6158 *buf = readl(hw->io + len);
6163 mutex_unlock(&hw_priv->lock);
6166 #define WOL_SUPPORT \
6167 (WAKE_PHY | WAKE_MAGIC | \
6168 WAKE_UCAST | WAKE_MCAST | \
6169 WAKE_BCAST | WAKE_ARP)
6172 * netdev_get_wol - get Wake-on-LAN support
6173 * @dev: Network device.
6174 * @wol: Ethtool Wake-on-LAN data structure.
6176 * This procedure returns Wake-on-LAN support.
6178 static void netdev_get_wol(struct net_device *dev,
6179 struct ethtool_wolinfo *wol)
6181 struct dev_priv *priv = netdev_priv(dev);
6182 struct dev_info *hw_priv = priv->adapter;
6184 wol->supported = hw_priv->wol_support;
6185 wol->wolopts = hw_priv->wol_enable;
6186 memset(&wol->sopass, 0, sizeof(wol->sopass));
6190 * netdev_set_wol - set Wake-on-LAN support
6191 * @dev: Network device.
6192 * @wol: Ethtool Wake-on-LAN data structure.
6194 * This function sets Wake-on-LAN support.
6196 * Return 0 if successful; otherwise an error code.
6198 static int netdev_set_wol(struct net_device *dev,
6199 struct ethtool_wolinfo *wol)
6201 struct dev_priv *priv = netdev_priv(dev);
6202 struct dev_info *hw_priv = priv->adapter;
6204 /* Need to find a way to retrieve the device IP address. */
6205 static const u8 net_addr[] = { 192, 168, 1, 1 };
6207 if (wol->wolopts & ~hw_priv->wol_support)
6210 hw_priv->wol_enable = wol->wolopts;
6212 /* Link wakeup cannot really be disabled. */
6214 hw_priv->wol_enable |= WAKE_PHY;
6215 hw_enable_wol(&hw_priv->hw, hw_priv->wol_enable, net_addr);
6220 * netdev_get_msglevel - get debug message level
6221 * @dev: Network device.
6223 * This function returns current debug message level.
6225 * Return current debug message flags.
6227 static u32 netdev_get_msglevel(struct net_device *dev)
6229 struct dev_priv *priv = netdev_priv(dev);
6231 return priv->msg_enable;
6235 * netdev_set_msglevel - set debug message level
6236 * @dev: Network device.
6237 * @value: Debug message flags.
6239 * This procedure sets debug message level.
6241 static void netdev_set_msglevel(struct net_device *dev, u32 value)
6243 struct dev_priv *priv = netdev_priv(dev);
6245 priv->msg_enable = value;
6249 * netdev_get_eeprom_len - get EEPROM length
6250 * @dev: Network device.
6252 * This function returns the length of the EEPROM.
6254 * Return length of the EEPROM.
6256 static int netdev_get_eeprom_len(struct net_device *dev)
6258 return EEPROM_SIZE * 2;
6262 * netdev_get_eeprom - get EEPROM data
6263 * @dev: Network device.
6264 * @eeprom: Ethtool EEPROM data structure.
6265 * @data: Buffer to store the EEPROM data.
6267 * This function dumps the EEPROM data in the provided buffer.
6269 * Return 0 if successful; otherwise an error code.
6271 #define EEPROM_MAGIC 0x10A18842
6273 static int netdev_get_eeprom(struct net_device *dev,
6274 struct ethtool_eeprom *eeprom, u8 *data)
6276 struct dev_priv *priv = netdev_priv(dev);
6277 struct dev_info *hw_priv = priv->adapter;
6278 u8 *eeprom_byte = (u8 *) eeprom_data;
6282 len = (eeprom->offset + eeprom->len + 1) / 2;
6283 for (i = eeprom->offset / 2; i < len; i++)
6284 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6285 eeprom->magic = EEPROM_MAGIC;
6286 memcpy(data, &eeprom_byte[eeprom->offset], eeprom->len);
6292 * netdev_set_eeprom - write EEPROM data
6293 * @dev: Network device.
6294 * @eeprom: Ethtool EEPROM data structure.
6295 * @data: Data buffer.
6297 * This function modifies the EEPROM data one byte at a time.
6299 * Return 0 if successful; otherwise an error code.
6301 static int netdev_set_eeprom(struct net_device *dev,
6302 struct ethtool_eeprom *eeprom, u8 *data)
6304 struct dev_priv *priv = netdev_priv(dev);
6305 struct dev_info *hw_priv = priv->adapter;
6306 u16 eeprom_word[EEPROM_SIZE];
6307 u8 *eeprom_byte = (u8 *) eeprom_word;
6311 if (eeprom->magic != EEPROM_MAGIC)
6314 len = (eeprom->offset + eeprom->len + 1) / 2;
6315 for (i = eeprom->offset / 2; i < len; i++)
6316 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6317 memcpy(eeprom_word, eeprom_data, EEPROM_SIZE * 2);
6318 memcpy(&eeprom_byte[eeprom->offset], data, eeprom->len);
6319 for (i = 0; i < EEPROM_SIZE; i++)
6320 if (eeprom_word[i] != eeprom_data[i]) {
6321 eeprom_data[i] = eeprom_word[i];
6322 eeprom_write(&hw_priv->hw, i, eeprom_data[i]);
6329 * netdev_get_pauseparam - get flow control parameters
6330 * @dev: Network device.
6331 * @pause: Ethtool PAUSE settings data structure.
6333 * This procedure returns the PAUSE control flow settings.
6335 static void netdev_get_pauseparam(struct net_device *dev,
6336 struct ethtool_pauseparam *pause)
6338 struct dev_priv *priv = netdev_priv(dev);
6339 struct dev_info *hw_priv = priv->adapter;
6340 struct ksz_hw *hw = &hw_priv->hw;
6342 pause->autoneg = (hw->overrides & PAUSE_FLOW_CTRL) ? 0 : 1;
6343 if (!hw->ksz_switch) {
6345 (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0;
6347 (hw->tx_cfg & DMA_TX_FLOW_ENABLE) ? 1 : 0;
6350 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6351 SWITCH_RX_FLOW_CTRL)) ? 1 : 0;
6353 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6354 SWITCH_TX_FLOW_CTRL)) ? 1 : 0;
6359 * netdev_set_pauseparam - set flow control parameters
6360 * @dev: Network device.
6361 * @pause: Ethtool PAUSE settings data structure.
6363 * This function sets the PAUSE control flow settings.
6364 * Not implemented yet.
6366 * Return 0 if successful; otherwise an error code.
6368 static int netdev_set_pauseparam(struct net_device *dev,
6369 struct ethtool_pauseparam *pause)
6371 struct dev_priv *priv = netdev_priv(dev);
6372 struct dev_info *hw_priv = priv->adapter;
6373 struct ksz_hw *hw = &hw_priv->hw;
6374 struct ksz_port *port = &priv->port;
6376 mutex_lock(&hw_priv->lock);
6377 if (pause->autoneg) {
6378 if (!pause->rx_pause && !pause->tx_pause)
6379 port->flow_ctrl = PHY_NO_FLOW_CTRL;
6381 port->flow_ctrl = PHY_FLOW_CTRL;
6382 hw->overrides &= ~PAUSE_FLOW_CTRL;
6383 port->force_link = 0;
6384 if (hw->ksz_switch) {
6385 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6386 SWITCH_RX_FLOW_CTRL, 1);
6387 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6388 SWITCH_TX_FLOW_CTRL, 1);
6390 port_set_link_speed(port);
6392 hw->overrides |= PAUSE_FLOW_CTRL;
6393 if (hw->ksz_switch) {
6394 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6395 SWITCH_RX_FLOW_CTRL, pause->rx_pause);
6396 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6397 SWITCH_TX_FLOW_CTRL, pause->tx_pause);
6399 set_flow_ctrl(hw, pause->rx_pause, pause->tx_pause);
6401 mutex_unlock(&hw_priv->lock);
6407 * netdev_get_ringparam - get tx/rx ring parameters
6408 * @dev: Network device.
6409 * @pause: Ethtool RING settings data structure.
6411 * This procedure returns the TX/RX ring settings.
6413 static void netdev_get_ringparam(struct net_device *dev,
6414 struct ethtool_ringparam *ring)
6416 struct dev_priv *priv = netdev_priv(dev);
6417 struct dev_info *hw_priv = priv->adapter;
6418 struct ksz_hw *hw = &hw_priv->hw;
6420 ring->tx_max_pending = (1 << 9);
6421 ring->tx_pending = hw->tx_desc_info.alloc;
6422 ring->rx_max_pending = (1 << 9);
6423 ring->rx_pending = hw->rx_desc_info.alloc;
6426 #define STATS_LEN (TOTAL_PORT_COUNTER_NUM)
6429 char string[ETH_GSTRING_LEN];
6430 } ethtool_stats_keys[STATS_LEN] = {
6431 { "rx_lo_priority_octets" },
6432 { "rx_hi_priority_octets" },
6433 { "rx_undersize_packets" },
6435 { "rx_oversize_packets" },
6437 { "rx_symbol_errors" },
6438 { "rx_crc_errors" },
6439 { "rx_align_errors" },
6440 { "rx_mac_ctrl_packets" },
6441 { "rx_pause_packets" },
6442 { "rx_bcast_packets" },
6443 { "rx_mcast_packets" },
6444 { "rx_ucast_packets" },
6445 { "rx_64_or_less_octet_packets" },
6446 { "rx_65_to_127_octet_packets" },
6447 { "rx_128_to_255_octet_packets" },
6448 { "rx_256_to_511_octet_packets" },
6449 { "rx_512_to_1023_octet_packets" },
6450 { "rx_1024_to_1522_octet_packets" },
6452 { "tx_lo_priority_octets" },
6453 { "tx_hi_priority_octets" },
6454 { "tx_late_collisions" },
6455 { "tx_pause_packets" },
6456 { "tx_bcast_packets" },
6457 { "tx_mcast_packets" },
6458 { "tx_ucast_packets" },
6460 { "tx_total_collisions" },
6461 { "tx_excessive_collisions" },
6462 { "tx_single_collisions" },
6463 { "tx_mult_collisions" },
6470 * netdev_get_strings - get statistics identity strings
6471 * @dev: Network device.
6472 * @stringset: String set identifier.
6473 * @buf: Buffer to store the strings.
6475 * This procedure returns the strings used to identify the statistics.
6477 static void netdev_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6479 struct dev_priv *priv = netdev_priv(dev);
6480 struct dev_info *hw_priv = priv->adapter;
6481 struct ksz_hw *hw = &hw_priv->hw;
6483 if (ETH_SS_STATS == stringset)
6484 memcpy(buf, ðtool_stats_keys,
6485 ETH_GSTRING_LEN * hw->mib_cnt);
6489 * netdev_get_sset_count - get statistics size
6490 * @dev: Network device.
6491 * @sset: The statistics set number.
6493 * This function returns the size of the statistics to be reported.
6495 * Return size of the statistics to be reported.
6497 static int netdev_get_sset_count(struct net_device *dev, int sset)
6499 struct dev_priv *priv = netdev_priv(dev);
6500 struct dev_info *hw_priv = priv->adapter;
6501 struct ksz_hw *hw = &hw_priv->hw;
6512 * netdev_get_ethtool_stats - get network device statistics
6513 * @dev: Network device.
6514 * @stats: Ethtool statistics data structure.
6515 * @data: Buffer to store the statistics.
6517 * This procedure returns the statistics.
6519 static void netdev_get_ethtool_stats(struct net_device *dev,
6520 struct ethtool_stats *stats, u64 *data)
6522 struct dev_priv *priv = netdev_priv(dev);
6523 struct dev_info *hw_priv = priv->adapter;
6524 struct ksz_hw *hw = &hw_priv->hw;
6525 struct ksz_port *port = &priv->port;
6526 int n_stats = stats->n_stats;
6531 u64 counter[TOTAL_PORT_COUNTER_NUM];
6533 mutex_lock(&hw_priv->lock);
6534 n = SWITCH_PORT_NUM;
6535 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
6536 if (media_connected == hw->port_mib[p].state) {
6537 hw_priv->counter[p].read = 1;
6539 /* Remember first port that requests read. */
6540 if (n == SWITCH_PORT_NUM)
6544 mutex_unlock(&hw_priv->lock);
6546 if (n < SWITCH_PORT_NUM)
6547 schedule_work(&hw_priv->mib_read);
6549 if (1 == port->mib_port_cnt && n < SWITCH_PORT_NUM) {
6551 rc = wait_event_interruptible_timeout(
6552 hw_priv->counter[p].counter,
6553 2 == hw_priv->counter[p].read,
6556 for (i = 0, p = n; i < port->mib_port_cnt - n; i++, p++) {
6558 rc = wait_event_interruptible_timeout(
6559 hw_priv->counter[p].counter,
6560 2 == hw_priv->counter[p].read,
6562 } else if (hw->port_mib[p].cnt_ptr) {
6563 rc = wait_event_interruptible_timeout(
6564 hw_priv->counter[p].counter,
6565 2 == hw_priv->counter[p].read,
6570 get_mib_counters(hw, port->first_port, port->mib_port_cnt, counter);
6575 for (i = 0; i < n; i++)
6576 *data++ = counter[i];
6580 * netdev_set_features - set receive checksum support
6581 * @dev: Network device.
6582 * @features: New device features (offloads).
6584 * This function sets receive checksum support setting.
6586 * Return 0 if successful; otherwise an error code.
6588 static int netdev_set_features(struct net_device *dev,
6589 netdev_features_t features)
6591 struct dev_priv *priv = netdev_priv(dev);
6592 struct dev_info *hw_priv = priv->adapter;
6593 struct ksz_hw *hw = &hw_priv->hw;
6595 mutex_lock(&hw_priv->lock);
6597 /* see note in hw_setup() */
6598 if (features & NETIF_F_RXCSUM)
6599 hw->rx_cfg |= DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP;
6601 hw->rx_cfg &= ~(DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
6604 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
6606 mutex_unlock(&hw_priv->lock);
6611 static const struct ethtool_ops netdev_ethtool_ops = {
6612 .nway_reset = netdev_nway_reset,
6613 .get_link = netdev_get_link,
6614 .get_drvinfo = netdev_get_drvinfo,
6615 .get_regs_len = netdev_get_regs_len,
6616 .get_regs = netdev_get_regs,
6617 .get_wol = netdev_get_wol,
6618 .set_wol = netdev_set_wol,
6619 .get_msglevel = netdev_get_msglevel,
6620 .set_msglevel = netdev_set_msglevel,
6621 .get_eeprom_len = netdev_get_eeprom_len,
6622 .get_eeprom = netdev_get_eeprom,
6623 .set_eeprom = netdev_set_eeprom,
6624 .get_pauseparam = netdev_get_pauseparam,
6625 .set_pauseparam = netdev_set_pauseparam,
6626 .get_ringparam = netdev_get_ringparam,
6627 .get_strings = netdev_get_strings,
6628 .get_sset_count = netdev_get_sset_count,
6629 .get_ethtool_stats = netdev_get_ethtool_stats,
6630 .get_link_ksettings = netdev_get_link_ksettings,
6631 .set_link_ksettings = netdev_set_link_ksettings,
6635 * Hardware monitoring
6638 static void update_link(struct net_device *dev, struct dev_priv *priv,
6639 struct ksz_port *port)
6641 if (priv->media_state != port->linked->state) {
6642 priv->media_state = port->linked->state;
6643 if (netif_running(dev))
6644 set_media_state(dev, media_connected);
6648 static void mib_read_work(struct work_struct *work)
6650 struct dev_info *hw_priv =
6651 container_of(work, struct dev_info, mib_read);
6652 struct ksz_hw *hw = &hw_priv->hw;
6653 struct ksz_port_mib *mib;
6656 next_jiffies = jiffies;
6657 for (i = 0; i < hw->mib_port_cnt; i++) {
6658 mib = &hw->port_mib[i];
6660 /* Reading MIB counters or requested to read. */
6661 if (mib->cnt_ptr || 1 == hw_priv->counter[i].read) {
6663 /* Need to process receive interrupt. */
6664 if (port_r_cnt(hw, i))
6666 hw_priv->counter[i].read = 0;
6668 /* Finish reading counters. */
6669 if (0 == mib->cnt_ptr) {
6670 hw_priv->counter[i].read = 2;
6671 wake_up_interruptible(
6672 &hw_priv->counter[i].counter);
6674 } else if (time_after_eq(jiffies, hw_priv->counter[i].time)) {
6675 /* Only read MIB counters when the port is connected. */
6676 if (media_connected == mib->state)
6677 hw_priv->counter[i].read = 1;
6678 next_jiffies += HZ * 1 * hw->mib_port_cnt;
6679 hw_priv->counter[i].time = next_jiffies;
6681 /* Port is just disconnected. */
6682 } else if (mib->link_down) {
6685 /* Read counters one last time after link is lost. */
6686 hw_priv->counter[i].read = 1;
6691 static void mib_monitor(unsigned long ptr)
6693 struct dev_info *hw_priv = (struct dev_info *) ptr;
6695 mib_read_work(&hw_priv->mib_read);
6697 /* This is used to verify Wake-on-LAN is working. */
6698 if (hw_priv->pme_wait) {
6699 if (time_is_before_eq_jiffies(hw_priv->pme_wait)) {
6700 hw_clr_wol_pme_status(&hw_priv->hw);
6701 hw_priv->pme_wait = 0;
6703 } else if (hw_chk_wol_pme_status(&hw_priv->hw)) {
6705 /* PME is asserted. Wait 2 seconds to clear it. */
6706 hw_priv->pme_wait = jiffies + HZ * 2;
6709 ksz_update_timer(&hw_priv->mib_timer_info);
6713 * dev_monitor - periodic monitoring
6714 * @ptr: Network device pointer.
6716 * This routine is run in a kernel timer to monitor the network device.
6718 static void dev_monitor(unsigned long ptr)
6720 struct net_device *dev = (struct net_device *) ptr;
6721 struct dev_priv *priv = netdev_priv(dev);
6722 struct dev_info *hw_priv = priv->adapter;
6723 struct ksz_hw *hw = &hw_priv->hw;
6724 struct ksz_port *port = &priv->port;
6726 if (!(hw->features & LINK_INT_WORKING))
6727 port_get_link_speed(port);
6728 update_link(dev, priv, port);
6730 ksz_update_timer(&priv->monitor_timer_info);
6734 * Linux network device interface functions
6737 /* Driver exported variables */
6739 static int msg_enable;
6741 static char *macaddr = ":";
6742 static char *mac1addr = ":";
6745 * This enables multiple network device mode for KSZ8842, which contains a
6746 * switch with two physical ports. Some users like to take control of the
6747 * ports for running Spanning Tree Protocol. The driver will create an
6748 * additional eth? device for the other port.
6750 * Some limitations are the network devices cannot have different MTU and
6751 * multicast hash tables.
6753 static int multi_dev;
6756 * As most users select multiple network device mode to use Spanning Tree
6757 * Protocol, this enables a feature in which most unicast and multicast packets
6758 * are forwarded inside the switch and not passed to the host. Only packets
6759 * that need the host's attention are passed to it. This prevents the host
6760 * wasting CPU time to examine each and every incoming packets and do the
6761 * forwarding itself.
6763 * As the hack requires the private bridge header, the driver cannot compile
6764 * with just the kernel headers.
6766 * Enabling STP support also turns on multiple network device mode.
6771 * This enables fast aging in the KSZ8842 switch. Not sure what situation
6772 * needs that. However, fast aging is used to flush the dynamic MAC table when
6773 * STP support is enabled.
6775 static int fast_aging;
6778 * netdev_init - initialize network device.
6779 * @dev: Network device.
6781 * This function initializes the network device.
6783 * Return 0 if successful; otherwise an error code indicating failure.
6785 static int __init netdev_init(struct net_device *dev)
6787 struct dev_priv *priv = netdev_priv(dev);
6789 /* 500 ms timeout */
6790 ksz_init_timer(&priv->monitor_timer_info, 500 * HZ / 1000,
6793 /* 500 ms timeout */
6794 dev->watchdog_timeo = HZ / 2;
6796 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_RXCSUM;
6799 * Hardware does not really support IPv6 checksum generation, but
6800 * driver actually runs faster with this on.
6802 dev->hw_features |= NETIF_F_IPV6_CSUM;
6804 dev->features |= dev->hw_features;
6806 sema_init(&priv->proc_sem, 1);
6808 priv->mii_if.phy_id_mask = 0x1;
6809 priv->mii_if.reg_num_mask = 0x7;
6810 priv->mii_if.dev = dev;
6811 priv->mii_if.mdio_read = mdio_read;
6812 priv->mii_if.mdio_write = mdio_write;
6813 priv->mii_if.phy_id = priv->port.first_port + 1;
6815 priv->msg_enable = netif_msg_init(msg_enable,
6816 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK));
6821 static const struct net_device_ops netdev_ops = {
6822 .ndo_init = netdev_init,
6823 .ndo_open = netdev_open,
6824 .ndo_stop = netdev_close,
6825 .ndo_get_stats = netdev_query_statistics,
6826 .ndo_start_xmit = netdev_tx,
6827 .ndo_tx_timeout = netdev_tx_timeout,
6828 .ndo_change_mtu = netdev_change_mtu,
6829 .ndo_set_features = netdev_set_features,
6830 .ndo_set_mac_address = netdev_set_mac_address,
6831 .ndo_validate_addr = eth_validate_addr,
6832 .ndo_do_ioctl = netdev_ioctl,
6833 .ndo_set_rx_mode = netdev_set_rx_mode,
6834 #ifdef CONFIG_NET_POLL_CONTROLLER
6835 .ndo_poll_controller = netdev_netpoll,
6839 static void netdev_free(struct net_device *dev)
6841 if (dev->watchdog_timeo)
6842 unregister_netdev(dev);
6847 struct platform_info {
6848 struct dev_info dev_info;
6849 struct net_device *netdev[SWITCH_PORT_NUM];
6852 static int net_device_present;
6854 static void get_mac_addr(struct dev_info *hw_priv, u8 *macaddr, int port)
6861 i = j = num = got_num = 0;
6862 while (j < ETH_ALEN) {
6867 digit = hex_to_bin(macaddr[i]);
6869 num = num * 16 + digit;
6870 else if (':' == macaddr[i])
6879 if (MAIN_PORT == port) {
6880 hw_priv->hw.override_addr[j++] = (u8) num;
6881 hw_priv->hw.override_addr[5] +=
6884 hw_priv->hw.ksz_switch->other_addr[j++] =
6886 hw_priv->hw.ksz_switch->other_addr[5] +=
6893 if (ETH_ALEN == j) {
6894 if (MAIN_PORT == port)
6895 hw_priv->hw.mac_override = 1;
6899 #define KS884X_DMA_MASK (~0x0UL)
6901 static void read_other_addr(struct ksz_hw *hw)
6905 struct ksz_switch *sw = hw->ksz_switch;
6907 for (i = 0; i < 3; i++)
6908 data[i] = eeprom_read(hw, i + EEPROM_DATA_OTHER_MAC_ADDR);
6909 if ((data[0] || data[1] || data[2]) && data[0] != 0xffff) {
6910 sw->other_addr[5] = (u8) data[0];
6911 sw->other_addr[4] = (u8)(data[0] >> 8);
6912 sw->other_addr[3] = (u8) data[1];
6913 sw->other_addr[2] = (u8)(data[1] >> 8);
6914 sw->other_addr[1] = (u8) data[2];
6915 sw->other_addr[0] = (u8)(data[2] >> 8);
6919 #ifndef PCI_VENDOR_ID_MICREL_KS
6920 #define PCI_VENDOR_ID_MICREL_KS 0x16c6
6923 static int pcidev_init(struct pci_dev *pdev, const struct pci_device_id *id)
6925 struct net_device *dev;
6926 struct dev_priv *priv;
6927 struct dev_info *hw_priv;
6929 struct platform_info *info;
6930 struct ksz_port *port;
6931 unsigned long reg_base;
6932 unsigned long reg_len;
6939 char banner[sizeof(version)];
6940 struct ksz_switch *sw = NULL;
6942 result = pci_enable_device(pdev);
6948 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
6949 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
6952 reg_base = pci_resource_start(pdev, 0);
6953 reg_len = pci_resource_len(pdev, 0);
6954 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0)
6957 if (!request_mem_region(reg_base, reg_len, DRV_NAME))
6959 pci_set_master(pdev);
6963 info = kzalloc(sizeof(struct platform_info), GFP_KERNEL);
6965 goto pcidev_init_dev_err;
6967 hw_priv = &info->dev_info;
6968 hw_priv->pdev = pdev;
6972 hw->io = ioremap(reg_base, reg_len);
6974 goto pcidev_init_io_err;
6978 if (msg_enable & NETIF_MSG_PROBE)
6979 pr_alert("chip not detected\n");
6981 goto pcidev_init_alloc_err;
6984 snprintf(banner, sizeof(banner), "%s", version);
6985 banner[13] = cnt + '0'; /* Replace x in "Micrel KSZ884x" */
6986 dev_info(&hw_priv->pdev->dev, "%s\n", banner);
6987 dev_dbg(&hw_priv->pdev->dev, "Mem = %p; IRQ = %d\n", hw->io, pdev->irq);
6989 /* Assume device is KSZ8841. */
6993 hw->addr_list_size = 0;
6994 hw->mib_cnt = PORT_COUNTER_NUM;
6995 hw->mib_port_cnt = 1;
6997 /* KSZ8842 has a switch with multiple ports. */
7000 hw->overrides |= FAST_AGING;
7002 hw->mib_cnt = TOTAL_PORT_COUNTER_NUM;
7004 /* Multiple network device interfaces are required. */
7006 hw->dev_count = SWITCH_PORT_NUM;
7007 hw->addr_list_size = SWITCH_PORT_NUM - 1;
7010 /* Single network device has multiple ports. */
7011 if (1 == hw->dev_count) {
7012 port_count = SWITCH_PORT_NUM;
7013 mib_port_count = SWITCH_PORT_NUM;
7015 hw->mib_port_cnt = TOTAL_PORT_NUM;
7016 hw->ksz_switch = kzalloc(sizeof(struct ksz_switch), GFP_KERNEL);
7017 if (!hw->ksz_switch)
7018 goto pcidev_init_alloc_err;
7020 sw = hw->ksz_switch;
7022 for (i = 0; i < hw->mib_port_cnt; i++)
7023 hw->port_mib[i].mib_start = 0;
7025 hw->parent = hw_priv;
7027 /* Default MTU is 1500. */
7028 hw_priv->mtu = (REGULAR_RX_BUF_SIZE + 3) & ~3;
7030 if (ksz_alloc_mem(hw_priv))
7031 goto pcidev_init_mem_err;
7033 hw_priv->hw.id = net_device_present;
7035 spin_lock_init(&hw_priv->hwlock);
7036 mutex_init(&hw_priv->lock);
7038 for (i = 0; i < TOTAL_PORT_NUM; i++)
7039 init_waitqueue_head(&hw_priv->counter[i].counter);
7041 if (macaddr[0] != ':')
7042 get_mac_addr(hw_priv, macaddr, MAIN_PORT);
7044 /* Read MAC address and initialize override address if not overridden. */
7047 /* Multiple device interfaces mode requires a second MAC address. */
7048 if (hw->dev_count > 1) {
7049 memcpy(sw->other_addr, hw->override_addr, ETH_ALEN);
7050 read_other_addr(hw);
7051 if (mac1addr[0] != ':')
7052 get_mac_addr(hw_priv, mac1addr, OTHER_PORT);
7059 hw_priv->wol_support = WOL_SUPPORT;
7060 hw_priv->wol_enable = 0;
7063 INIT_WORK(&hw_priv->mib_read, mib_read_work);
7065 /* 500 ms timeout */
7066 ksz_init_timer(&hw_priv->mib_timer_info, 500 * HZ / 1000,
7067 mib_monitor, hw_priv);
7069 for (i = 0; i < hw->dev_count; i++) {
7070 dev = alloc_etherdev(sizeof(struct dev_priv));
7072 goto pcidev_init_reg_err;
7073 SET_NETDEV_DEV(dev, &pdev->dev);
7074 info->netdev[i] = dev;
7076 priv = netdev_priv(dev);
7077 priv->adapter = hw_priv;
7078 priv->id = net_device_present++;
7081 port->port_cnt = port_count;
7082 port->mib_port_cnt = mib_port_count;
7083 port->first_port = i;
7084 port->flow_ctrl = PHY_FLOW_CTRL;
7087 port->linked = &hw->port_info[port->first_port];
7089 for (cnt = 0, pi = i; cnt < port_count; cnt++, pi++) {
7090 hw->port_info[pi].port_id = pi;
7091 hw->port_info[pi].pdev = dev;
7092 hw->port_info[pi].state = media_disconnected;
7095 dev->mem_start = (unsigned long) hw->io;
7096 dev->mem_end = dev->mem_start + reg_len - 1;
7097 dev->irq = pdev->irq;
7099 memcpy(dev->dev_addr, hw_priv->hw.override_addr,
7102 memcpy(dev->dev_addr, sw->other_addr, ETH_ALEN);
7103 if (ether_addr_equal(sw->other_addr, hw->override_addr))
7104 dev->dev_addr[5] += port->first_port;
7107 dev->netdev_ops = &netdev_ops;
7108 dev->ethtool_ops = &netdev_ethtool_ops;
7110 /* MTU range: 60 - 1894 */
7111 dev->min_mtu = ETH_ZLEN;
7112 dev->max_mtu = MAX_RX_BUF_SIZE -
7113 (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7115 if (register_netdev(dev))
7116 goto pcidev_init_reg_err;
7117 port_set_power_saving(port, true);
7120 pci_dev_get(hw_priv->pdev);
7121 pci_set_drvdata(pdev, info);
7124 pcidev_init_reg_err:
7125 for (i = 0; i < hw->dev_count; i++) {
7126 if (info->netdev[i]) {
7127 netdev_free(info->netdev[i]);
7128 info->netdev[i] = NULL;
7132 pcidev_init_mem_err:
7133 ksz_free_mem(hw_priv);
7134 kfree(hw->ksz_switch);
7136 pcidev_init_alloc_err:
7142 pcidev_init_dev_err:
7143 release_mem_region(reg_base, reg_len);
7148 static void pcidev_exit(struct pci_dev *pdev)
7151 struct platform_info *info = pci_get_drvdata(pdev);
7152 struct dev_info *hw_priv = &info->dev_info;
7154 release_mem_region(pci_resource_start(pdev, 0),
7155 pci_resource_len(pdev, 0));
7156 for (i = 0; i < hw_priv->hw.dev_count; i++) {
7157 if (info->netdev[i])
7158 netdev_free(info->netdev[i]);
7161 iounmap(hw_priv->hw.io);
7162 ksz_free_mem(hw_priv);
7163 kfree(hw_priv->hw.ksz_switch);
7164 pci_dev_put(hw_priv->pdev);
7169 static int pcidev_resume(struct pci_dev *pdev)
7172 struct platform_info *info = pci_get_drvdata(pdev);
7173 struct dev_info *hw_priv = &info->dev_info;
7174 struct ksz_hw *hw = &hw_priv->hw;
7176 pci_set_power_state(pdev, PCI_D0);
7177 pci_restore_state(pdev);
7178 pci_enable_wake(pdev, PCI_D0, 0);
7180 if (hw_priv->wol_enable)
7181 hw_cfg_wol_pme(hw, 0);
7182 for (i = 0; i < hw->dev_count; i++) {
7183 if (info->netdev[i]) {
7184 struct net_device *dev = info->netdev[i];
7186 if (netif_running(dev)) {
7188 netif_device_attach(dev);
7195 static int pcidev_suspend(struct pci_dev *pdev, pm_message_t state)
7198 struct platform_info *info = pci_get_drvdata(pdev);
7199 struct dev_info *hw_priv = &info->dev_info;
7200 struct ksz_hw *hw = &hw_priv->hw;
7202 /* Need to find a way to retrieve the device IP address. */
7203 static const u8 net_addr[] = { 192, 168, 1, 1 };
7205 for (i = 0; i < hw->dev_count; i++) {
7206 if (info->netdev[i]) {
7207 struct net_device *dev = info->netdev[i];
7209 if (netif_running(dev)) {
7210 netif_device_detach(dev);
7215 if (hw_priv->wol_enable) {
7216 hw_enable_wol(hw, hw_priv->wol_enable, net_addr);
7217 hw_cfg_wol_pme(hw, 1);
7220 pci_save_state(pdev);
7221 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
7222 pci_set_power_state(pdev, pci_choose_state(pdev, state));
7227 static char pcidev_name[] = "ksz884xp";
7229 static const struct pci_device_id pcidev_table[] = {
7230 { PCI_VENDOR_ID_MICREL_KS, 0x8841,
7231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7232 { PCI_VENDOR_ID_MICREL_KS, 0x8842,
7233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7237 MODULE_DEVICE_TABLE(pci, pcidev_table);
7239 static struct pci_driver pci_device_driver = {
7241 .suspend = pcidev_suspend,
7242 .resume = pcidev_resume,
7244 .name = pcidev_name,
7245 .id_table = pcidev_table,
7246 .probe = pcidev_init,
7247 .remove = pcidev_exit
7250 module_pci_driver(pci_device_driver);
7252 MODULE_DESCRIPTION("KSZ8841/2 PCI network driver");
7253 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@micrel.com>");
7254 MODULE_LICENSE("GPL");
7256 module_param_named(message, msg_enable, int, 0);
7257 MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");
7259 module_param(macaddr, charp, 0);
7260 module_param(mac1addr, charp, 0);
7261 module_param(fast_aging, int, 0);
7262 module_param(multi_dev, int, 0);
7263 module_param(stp, int, 0);
7264 MODULE_PARM_DESC(macaddr, "MAC address");
7265 MODULE_PARM_DESC(mac1addr, "Second MAC address");
7266 MODULE_PARM_DESC(fast_aging, "Fast aging");
7267 MODULE_PARM_DESC(multi_dev, "Multiple device interfaces");
7268 MODULE_PARM_DESC(stp, "STP support");