2 * drivers/net/ethernet/micrel/ks8851_mll.c
3 * Copyright (c) 2009 Micrel Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 * KS8851 16bit MLL chip from Micrel Inc.
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25 #include <linux/interrupt.h>
26 #include <linux/module.h>
27 #include <linux/kernel.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/cache.h>
32 #include <linux/crc32.h>
33 #include <linux/mii.h>
34 #include <linux/platform_device.h>
35 #include <linux/delay.h>
36 #include <linux/slab.h>
37 #include <linux/ks8851_mll.h>
39 #include <linux/of_device.h>
40 #include <linux/of_net.h>
42 #define DRV_NAME "ks8851_mll"
44 static u8 KS_DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x86, 0x95, 0x11 };
45 #define MAX_RECV_FRAMES 255
46 #define MAX_BUF_SIZE 2048
47 #define TX_BUF_SIZE 2000
48 #define RX_BUF_SIZE 2000
51 #define CCR_EEPROM (1 << 9)
52 #define CCR_SPI (1 << 8)
53 #define CCR_8BIT (1 << 7)
54 #define CCR_16BIT (1 << 6)
55 #define CCR_32BIT (1 << 5)
56 #define CCR_SHARED (1 << 4)
57 #define CCR_32PIN (1 << 0)
59 /* MAC address registers */
65 #define OBCR_ODS_16MA (1 << 6)
68 #define EEPCR_EESA (1 << 4)
69 #define EEPCR_EESB (1 << 3)
70 #define EEPCR_EEDO (1 << 2)
71 #define EEPCR_EESCK (1 << 1)
72 #define EEPCR_EECS (1 << 0)
75 #define MBIR_TXMBF (1 << 12)
76 #define MBIR_TXMBFA (1 << 11)
77 #define MBIR_RXMBF (1 << 4)
78 #define MBIR_RXMBFA (1 << 3)
81 #define GRR_QMU (1 << 1)
82 #define GRR_GSR (1 << 0)
85 #define WFCR_MPRXE (1 << 7)
86 #define WFCR_WF3E (1 << 3)
87 #define WFCR_WF2E (1 << 2)
88 #define WFCR_WF1E (1 << 1)
89 #define WFCR_WF0E (1 << 0)
91 #define KS_WF0CRC0 0x30
92 #define KS_WF0CRC1 0x32
93 #define KS_WF0BM0 0x34
94 #define KS_WF0BM1 0x36
95 #define KS_WF0BM2 0x38
96 #define KS_WF0BM3 0x3A
98 #define KS_WF1CRC0 0x40
99 #define KS_WF1CRC1 0x42
100 #define KS_WF1BM0 0x44
101 #define KS_WF1BM1 0x46
102 #define KS_WF1BM2 0x48
103 #define KS_WF1BM3 0x4A
105 #define KS_WF2CRC0 0x50
106 #define KS_WF2CRC1 0x52
107 #define KS_WF2BM0 0x54
108 #define KS_WF2BM1 0x56
109 #define KS_WF2BM2 0x58
110 #define KS_WF2BM3 0x5A
112 #define KS_WF3CRC0 0x60
113 #define KS_WF3CRC1 0x62
114 #define KS_WF3BM0 0x64
115 #define KS_WF3BM1 0x66
116 #define KS_WF3BM2 0x68
117 #define KS_WF3BM3 0x6A
120 #define TXCR_TCGICMP (1 << 8)
121 #define TXCR_TCGUDP (1 << 7)
122 #define TXCR_TCGTCP (1 << 6)
123 #define TXCR_TCGIP (1 << 5)
124 #define TXCR_FTXQ (1 << 4)
125 #define TXCR_TXFCE (1 << 3)
126 #define TXCR_TXPE (1 << 2)
127 #define TXCR_TXCRC (1 << 1)
128 #define TXCR_TXE (1 << 0)
131 #define TXSR_TXLC (1 << 13)
132 #define TXSR_TXMC (1 << 12)
133 #define TXSR_TXFID_MASK (0x3f << 0)
134 #define TXSR_TXFID_SHIFT (0)
135 #define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
138 #define KS_RXCR1 0x74
139 #define RXCR1_FRXQ (1 << 15)
140 #define RXCR1_RXUDPFCC (1 << 14)
141 #define RXCR1_RXTCPFCC (1 << 13)
142 #define RXCR1_RXIPFCC (1 << 12)
143 #define RXCR1_RXPAFMA (1 << 11)
144 #define RXCR1_RXFCE (1 << 10)
145 #define RXCR1_RXEFE (1 << 9)
146 #define RXCR1_RXMAFMA (1 << 8)
147 #define RXCR1_RXBE (1 << 7)
148 #define RXCR1_RXME (1 << 6)
149 #define RXCR1_RXUE (1 << 5)
150 #define RXCR1_RXAE (1 << 4)
151 #define RXCR1_RXINVF (1 << 1)
152 #define RXCR1_RXE (1 << 0)
153 #define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \
154 RXCR1_RXMAFMA | RXCR1_RXPAFMA)
156 #define KS_RXCR2 0x76
157 #define RXCR2_SRDBL_MASK (0x7 << 5)
158 #define RXCR2_SRDBL_SHIFT (5)
159 #define RXCR2_SRDBL_4B (0x0 << 5)
160 #define RXCR2_SRDBL_8B (0x1 << 5)
161 #define RXCR2_SRDBL_16B (0x2 << 5)
162 #define RXCR2_SRDBL_32B (0x3 << 5)
163 /* #define RXCR2_SRDBL_FRAME (0x4 << 5) */
164 #define RXCR2_IUFFP (1 << 4)
165 #define RXCR2_RXIUFCEZ (1 << 3)
166 #define RXCR2_UDPLFE (1 << 2)
167 #define RXCR2_RXICMPFCC (1 << 1)
168 #define RXCR2_RXSAF (1 << 0)
170 #define KS_TXMIR 0x78
172 #define KS_RXFHSR 0x7C
173 #define RXFSHR_RXFV (1 << 15)
174 #define RXFSHR_RXICMPFCS (1 << 13)
175 #define RXFSHR_RXIPFCS (1 << 12)
176 #define RXFSHR_RXTCPFCS (1 << 11)
177 #define RXFSHR_RXUDPFCS (1 << 10)
178 #define RXFSHR_RXBF (1 << 7)
179 #define RXFSHR_RXMF (1 << 6)
180 #define RXFSHR_RXUF (1 << 5)
181 #define RXFSHR_RXMR (1 << 4)
182 #define RXFSHR_RXFT (1 << 3)
183 #define RXFSHR_RXFTL (1 << 2)
184 #define RXFSHR_RXRF (1 << 1)
185 #define RXFSHR_RXCE (1 << 0)
186 #define RXFSHR_ERR (RXFSHR_RXCE | RXFSHR_RXRF |\
187 RXFSHR_RXFTL | RXFSHR_RXMR |\
188 RXFSHR_RXICMPFCS | RXFSHR_RXIPFCS |\
190 #define KS_RXFHBCR 0x7E
191 #define RXFHBCR_CNT_MASK 0x0FFF
193 #define KS_TXQCR 0x80
194 #define TXQCR_AETFE (1 << 2)
195 #define TXQCR_TXQMAM (1 << 1)
196 #define TXQCR_METFE (1 << 0)
198 #define KS_RXQCR 0x82
199 #define RXQCR_RXDTTS (1 << 12)
200 #define RXQCR_RXDBCTS (1 << 11)
201 #define RXQCR_RXFCTS (1 << 10)
202 #define RXQCR_RXIPHTOE (1 << 9)
203 #define RXQCR_RXDTTE (1 << 7)
204 #define RXQCR_RXDBCTE (1 << 6)
205 #define RXQCR_RXFCTE (1 << 5)
206 #define RXQCR_ADRFE (1 << 4)
207 #define RXQCR_SDA (1 << 3)
208 #define RXQCR_RRXEF (1 << 0)
209 #define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE)
211 #define KS_TXFDPR 0x84
212 #define TXFDPR_TXFPAI (1 << 14)
213 #define TXFDPR_TXFP_MASK (0x7ff << 0)
214 #define TXFDPR_TXFP_SHIFT (0)
216 #define KS_RXFDPR 0x86
217 #define RXFDPR_RXFPAI (1 << 14)
219 #define KS_RXDTTR 0x8C
220 #define KS_RXDBCTR 0x8E
224 #define IRQ_LCI (1 << 15)
225 #define IRQ_TXI (1 << 14)
226 #define IRQ_RXI (1 << 13)
227 #define IRQ_RXOI (1 << 11)
228 #define IRQ_TXPSI (1 << 9)
229 #define IRQ_RXPSI (1 << 8)
230 #define IRQ_TXSAI (1 << 6)
231 #define IRQ_RXWFDI (1 << 5)
232 #define IRQ_RXMPDI (1 << 4)
233 #define IRQ_LDI (1 << 3)
234 #define IRQ_EDI (1 << 2)
235 #define IRQ_SPIBEI (1 << 1)
236 #define IRQ_DEDI (1 << 0)
238 #define KS_RXFCTR 0x9C
239 #define RXFCTR_THRESHOLD_MASK 0x00FF
242 #define RXFCTR_RXFC_MASK (0xff << 8)
243 #define RXFCTR_RXFC_SHIFT (8)
244 #define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff)
245 #define RXFCTR_RXFCT_MASK (0xff << 0)
246 #define RXFCTR_RXFCT_SHIFT (0)
248 #define KS_TXNTFSR 0x9E
250 #define KS_MAHTR0 0xA0
251 #define KS_MAHTR1 0xA2
252 #define KS_MAHTR2 0xA4
253 #define KS_MAHTR3 0xA6
255 #define KS_FCLWR 0xB0
256 #define KS_FCHWR 0xB2
257 #define KS_FCOWR 0xB4
259 #define KS_CIDER 0xC0
260 #define CIDER_ID 0x8870
261 #define CIDER_REV_MASK (0x7 << 1)
262 #define CIDER_REV_SHIFT (1)
263 #define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
267 #define IACR_RDEN (1 << 12)
268 #define IACR_TSEL_MASK (0x3 << 10)
269 #define IACR_TSEL_SHIFT (10)
270 #define IACR_TSEL_MIB (0x3 << 10)
271 #define IACR_ADDR_MASK (0x1f << 0)
272 #define IACR_ADDR_SHIFT (0)
274 #define KS_IADLR 0xD0
275 #define KS_IAHDR 0xD2
277 #define KS_PMECR 0xD4
278 #define PMECR_PME_DELAY (1 << 14)
279 #define PMECR_PME_POL (1 << 12)
280 #define PMECR_WOL_WAKEUP (1 << 11)
281 #define PMECR_WOL_MAGICPKT (1 << 10)
282 #define PMECR_WOL_LINKUP (1 << 9)
283 #define PMECR_WOL_ENERGY (1 << 8)
284 #define PMECR_AUTO_WAKE_EN (1 << 7)
285 #define PMECR_WAKEUP_NORMAL (1 << 6)
286 #define PMECR_WKEVT_MASK (0xf << 2)
287 #define PMECR_WKEVT_SHIFT (2)
288 #define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf)
289 #define PMECR_WKEVT_ENERGY (0x1 << 2)
290 #define PMECR_WKEVT_LINK (0x2 << 2)
291 #define PMECR_WKEVT_MAGICPKT (0x4 << 2)
292 #define PMECR_WKEVT_FRAME (0x8 << 2)
293 #define PMECR_PM_MASK (0x3 << 0)
294 #define PMECR_PM_SHIFT (0)
295 #define PMECR_PM_NORMAL (0x0 << 0)
296 #define PMECR_PM_ENERGY (0x1 << 0)
297 #define PMECR_PM_SOFTDOWN (0x2 << 0)
298 #define PMECR_PM_POWERSAVE (0x3 << 0)
300 /* Standard MII PHY data */
301 #define KS_P1MBCR 0xE4
302 #define P1MBCR_FORCE_FDX (1 << 8)
304 #define KS_P1MBSR 0xE6
305 #define P1MBSR_AN_COMPLETE (1 << 5)
306 #define P1MBSR_AN_CAPABLE (1 << 3)
307 #define P1MBSR_LINK_UP (1 << 2)
309 #define KS_PHY1ILR 0xE8
310 #define KS_PHY1IHR 0xEA
311 #define KS_P1ANAR 0xEC
312 #define KS_P1ANLPR 0xEE
314 #define KS_P1SCLMD 0xF4
315 #define P1SCLMD_LEDOFF (1 << 15)
316 #define P1SCLMD_TXIDS (1 << 14)
317 #define P1SCLMD_RESTARTAN (1 << 13)
318 #define P1SCLMD_DISAUTOMDIX (1 << 10)
319 #define P1SCLMD_FORCEMDIX (1 << 9)
320 #define P1SCLMD_AUTONEGEN (1 << 7)
321 #define P1SCLMD_FORCE100 (1 << 6)
322 #define P1SCLMD_FORCEFDX (1 << 5)
323 #define P1SCLMD_ADV_FLOW (1 << 4)
324 #define P1SCLMD_ADV_100BT_FDX (1 << 3)
325 #define P1SCLMD_ADV_100BT_HDX (1 << 2)
326 #define P1SCLMD_ADV_10BT_FDX (1 << 1)
327 #define P1SCLMD_ADV_10BT_HDX (1 << 0)
330 #define P1CR_HP_MDIX (1 << 15)
331 #define P1CR_REV_POL (1 << 13)
332 #define P1CR_OP_100M (1 << 10)
333 #define P1CR_OP_FDX (1 << 9)
334 #define P1CR_OP_MDI (1 << 7)
335 #define P1CR_AN_DONE (1 << 6)
336 #define P1CR_LINK_GOOD (1 << 5)
337 #define P1CR_PNTR_FLOW (1 << 4)
338 #define P1CR_PNTR_100BT_FDX (1 << 3)
339 #define P1CR_PNTR_100BT_HDX (1 << 2)
340 #define P1CR_PNTR_10BT_FDX (1 << 1)
341 #define P1CR_PNTR_10BT_HDX (1 << 0)
343 /* TX Frame control */
345 #define TXFR_TXIC (1 << 15)
346 #define TXFR_TXFID_MASK (0x3f << 0)
347 #define TXFR_TXFID_SHIFT (0)
350 #define P1SR_HP_MDIX (1 << 15)
351 #define P1SR_REV_POL (1 << 13)
352 #define P1SR_OP_100M (1 << 10)
353 #define P1SR_OP_FDX (1 << 9)
354 #define P1SR_OP_MDI (1 << 7)
355 #define P1SR_AN_DONE (1 << 6)
356 #define P1SR_LINK_GOOD (1 << 5)
357 #define P1SR_PNTR_FLOW (1 << 4)
358 #define P1SR_PNTR_100BT_FDX (1 << 3)
359 #define P1SR_PNTR_100BT_HDX (1 << 2)
360 #define P1SR_PNTR_10BT_FDX (1 << 1)
361 #define P1SR_PNTR_10BT_HDX (1 << 0)
363 #define ENUM_BUS_NONE 0
364 #define ENUM_BUS_8BIT 1
365 #define ENUM_BUS_16BIT 2
366 #define ENUM_BUS_32BIT 3
368 #define MAX_MCAST_LST 32
369 #define HW_MCAST_SIZE 8
372 * union ks_tx_hdr - tx header data
373 * @txb: The header as bytes
374 * @txw: The header as 16bit, little-endian words
376 * A dual representation of the tx header data to allow
377 * access to individual bytes, and to allow 16bit accesses
378 * with 16bit alignment.
386 * struct ks_net - KS8851 driver private data
387 * @net_device : The network device we're bound to
388 * @hw_addr : start address of data register.
389 * @hw_addr_cmd : start address of command register.
390 * @txh : temporaly buffer to save status/length.
391 * @lock : Lock to ensure that the device is not accessed when busy.
392 * @pdev : Pointer to platform device.
393 * @mii : The MII state information for the mii calls.
394 * @frame_head_info : frame header information for multi-pkt rx.
395 * @statelock : Lock on this structure for tx list.
396 * @msg_enable : The message flags controlling driver output (see ethtool).
397 * @frame_cnt : number of frames received.
398 * @bus_width : i/o bus width.
399 * @rc_rxqcr : Cached copy of KS_RXQCR.
400 * @rc_txcr : Cached copy of KS_TXCR.
401 * @rc_ier : Cached copy of KS_IER.
402 * @sharedbus : Multipex(addr and data bus) mode indicator.
403 * @cmd_reg_cache : command register cached.
404 * @cmd_reg_cache_int : command register cached. Used in the irq handler.
405 * @promiscuous : promiscuous mode indicator.
406 * @all_mcast : mutlicast indicator.
407 * @mcast_lst_size : size of multicast list.
408 * @mcast_lst : multicast list.
409 * @mcast_bits : multicast enabed.
410 * @mac_addr : MAC address assigned to this device.
412 * @extra_byte : number of extra byte prepended rx pkt.
413 * @enabled : indicator this device works.
415 * The @lock ensures that the chip is protected when certain operations are
416 * in progress. When the read or write packet transfer is in progress, most
417 * of the chip registers are not accessible until the transfer is finished and
418 * the DMA has been de-asserted.
420 * The @statelock is used to protect information in the structure which may
421 * need to be accessed via several sources, such as the network driver layer
422 * or one of the work queues.
426 /* Receive multiplex framer header info */
427 struct type_frame_head {
428 u16 sts; /* Frame status */
429 u16 len; /* Byte count */
433 struct net_device *netdev;
434 void __iomem *hw_addr;
435 void __iomem *hw_addr_cmd;
436 union ks_tx_hdr txh ____cacheline_aligned;
437 struct mutex lock; /* spinlock to be interrupt safe */
438 struct platform_device *pdev;
439 struct mii_if_info mii;
440 struct type_frame_head *frame_head_info;
441 spinlock_t statelock;
451 u16 cmd_reg_cache_int;
455 u8 mcast_lst[MAX_MCAST_LST][ETH_ALEN];
456 u8 mcast_bits[HW_MCAST_SIZE];
463 static int msg_enable;
465 #define BE3 0x8000 /* Byte Enable 3 */
466 #define BE2 0x4000 /* Byte Enable 2 */
467 #define BE1 0x2000 /* Byte Enable 1 */
468 #define BE0 0x1000 /* Byte Enable 0 */
470 /* register read/write calls.
472 * All these calls issue transactions to access the chip's registers. They
473 * all require that the necessary lock is held to prevent accesses when the
474 * chip is busy transferring packet data (RX/TX FIFO accesses).
478 * ks_check_endian - Check whether endianness of the bus is correct
479 * @ks : The chip information
481 * The KS8851-16MLL EESK pin allows selecting the endianness of the 16bit
482 * bus. To maintain optimum performance, the bus endianness should be set
483 * such that it matches the endianness of the CPU.
486 static int ks_check_endian(struct ks_net *ks)
491 * Read CIDER register first, however read it the "wrong" way around.
492 * If the endian strap on the KS8851-16MLL in incorrect and the chip
493 * is operating in different endianness than the CPU, then the meaning
494 * of BE[3:0] byte-enable bits is also swapped such that:
495 * BE[3,2,1,0] becomes BE[1,0,3,2]
497 * Luckily for us, the byte-enable bits are the top four MSbits of
498 * the address register and the CIDER register is at offset 0xc0.
499 * Hence, by reading address 0xc0c0, which is not impacted by endian
500 * swapping, we assert either BE[3:2] or BE[1:0] while reading the
503 * If the bus configuration is correct, reading 0xc0c0 asserts
504 * BE[3:2] and this read returns 0x0000, because to read register
505 * with bottom two LSbits of address set to 0, BE[1:0] must be
508 * If the bus configuration is NOT correct, reading 0xc0c0 asserts
509 * BE[1:0] and this read returns non-zero 0x8872 value.
511 iowrite16(BE3 | BE2 | KS_CIDER, ks->hw_addr_cmd);
512 cider = ioread16(ks->hw_addr);
516 netdev_err(ks->netdev, "incorrect EESK endian strap setting\n");
522 * ks_rdreg16 - read 16 bit register from device
523 * @ks : The chip information
524 * @offset: The register address
526 * Read a 16bit register from the chip, returning the result
529 static u16 ks_rdreg16(struct ks_net *ks, int offset)
531 ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02));
532 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
533 return ioread16(ks->hw_addr);
537 * ks_wrreg16 - write 16bit register value to chip
538 * @ks: The chip information
539 * @offset: The register address
540 * @value: The value to write
544 static void ks_wrreg16(struct ks_net *ks, int offset, u16 value)
546 ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02));
547 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
548 iowrite16(value, ks->hw_addr);
552 * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode enabled.
553 * @ks: The chip state
554 * @wptr: buffer address to save data
555 * @len: length in byte to read
558 static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len)
562 *wptr++ = (u16)ioread16(ks->hw_addr);
566 * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
567 * @ks: The chip information
568 * @wptr: buffer address
569 * @len: length in byte to write
572 static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len)
576 iowrite16(*wptr++, ks->hw_addr);
579 static void ks_disable_int(struct ks_net *ks)
581 ks_wrreg16(ks, KS_IER, 0x0000);
582 } /* ks_disable_int */
584 static void ks_enable_int(struct ks_net *ks)
586 ks_wrreg16(ks, KS_IER, ks->rc_ier);
587 } /* ks_enable_int */
590 * ks_tx_fifo_space - return the available hardware buffer size.
591 * @ks: The chip information
594 static inline u16 ks_tx_fifo_space(struct ks_net *ks)
596 return ks_rdreg16(ks, KS_TXMIR) & 0x1fff;
600 * ks_save_cmd_reg - save the command register from the cache.
601 * @ks: The chip information
604 static inline void ks_save_cmd_reg(struct ks_net *ks)
606 /*ks8851 MLL has a bug to read back the command register.
607 * So rely on software to save the content of command register.
609 ks->cmd_reg_cache_int = ks->cmd_reg_cache;
613 * ks_restore_cmd_reg - restore the command register from the cache and
614 * write to hardware register.
615 * @ks: The chip information
618 static inline void ks_restore_cmd_reg(struct ks_net *ks)
620 ks->cmd_reg_cache = ks->cmd_reg_cache_int;
621 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
625 * ks_set_powermode - set power mode of the device
626 * @ks: The chip information
627 * @pwrmode: The power mode value to write to KS_PMECR.
629 * Change the power mode of the chip.
631 static void ks_set_powermode(struct ks_net *ks, unsigned pwrmode)
635 netif_dbg(ks, hw, ks->netdev, "setting power mode %d\n", pwrmode);
637 ks_rdreg16(ks, KS_GRR);
638 pmecr = ks_rdreg16(ks, KS_PMECR);
639 pmecr &= ~PMECR_PM_MASK;
642 ks_wrreg16(ks, KS_PMECR, pmecr);
646 * ks_read_config - read chip configuration of bus width.
647 * @ks: The chip information
650 static void ks_read_config(struct ks_net *ks)
654 /* Regardless of bus width, 8 bit read should always work.*/
655 reg_data = ks_rdreg16(ks, KS_CCR);
657 /* addr/data bus are multiplexed */
658 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
660 /* There are garbage data when reading data from QMU,
661 depending on bus-width.
664 if (reg_data & CCR_8BIT) {
665 ks->bus_width = ENUM_BUS_8BIT;
667 } else if (reg_data & CCR_16BIT) {
668 ks->bus_width = ENUM_BUS_16BIT;
671 ks->bus_width = ENUM_BUS_32BIT;
677 * ks_soft_reset - issue one of the soft reset to the device
678 * @ks: The device state.
679 * @op: The bit(s) to set in the GRR
681 * Issue the relevant soft-reset command to the device's GRR register
684 * Note, the delays are in there as a caution to ensure that the reset
685 * has time to take effect and then complete. Since the datasheet does
686 * not currently specify the exact sequence, we have chosen something
687 * that seems to work with our device.
689 static void ks_soft_reset(struct ks_net *ks, unsigned op)
691 /* Disable interrupt first */
692 ks_wrreg16(ks, KS_IER, 0x0000);
693 ks_wrreg16(ks, KS_GRR, op);
694 mdelay(10); /* wait a short time to effect reset */
695 ks_wrreg16(ks, KS_GRR, 0);
696 mdelay(1); /* wait for condition to clear */
700 static void ks_enable_qmu(struct ks_net *ks)
704 w = ks_rdreg16(ks, KS_TXCR);
705 /* Enables QMU Transmit (TXCR). */
706 ks_wrreg16(ks, KS_TXCR, w | TXCR_TXE);
709 * RX Frame Count Threshold Enable and Auto-Dequeue RXQ Frame
713 w = ks_rdreg16(ks, KS_RXQCR);
714 ks_wrreg16(ks, KS_RXQCR, w | RXQCR_RXFCTE);
716 /* Enables QMU Receive (RXCR1). */
717 w = ks_rdreg16(ks, KS_RXCR1);
718 ks_wrreg16(ks, KS_RXCR1, w | RXCR1_RXE);
720 } /* ks_enable_qmu */
722 static void ks_disable_qmu(struct ks_net *ks)
726 w = ks_rdreg16(ks, KS_TXCR);
728 /* Disables QMU Transmit (TXCR). */
730 ks_wrreg16(ks, KS_TXCR, w);
732 /* Disables QMU Receive (RXCR1). */
733 w = ks_rdreg16(ks, KS_RXCR1);
735 ks_wrreg16(ks, KS_RXCR1, w);
739 } /* ks_disable_qmu */
742 * ks_read_qmu - read 1 pkt data from the QMU.
743 * @ks: The chip information
744 * @buf: buffer address to save 1 pkt
746 * Here is the sequence to read 1 pkt:
747 * 1. set sudo DMA mode
748 * 2. read prepend data
750 * 4. reset sudo DMA Mode
752 static inline void ks_read_qmu(struct ks_net *ks, u16 *buf, u32 len)
754 u32 r = ks->extra_byte & 0x1 ;
755 u32 w = ks->extra_byte - r;
757 /* 1. set sudo DMA mode */
758 ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
759 ks_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr | RXQCR_SDA);
761 /* 2. read prepend data */
763 * read 4 + extra bytes and discard them.
764 * extra bytes for dummy, 2 for status, 2 for len
767 /* use likely(r) for 8 bit access for performance */
769 ioread8(ks->hw_addr);
770 ks_inblk(ks, buf, w + 2 + 2);
772 /* 3. read pkt data */
773 ks_inblk(ks, buf, ALIGN(len, 4));
775 /* 4. reset sudo DMA Mode */
776 ks_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr);
780 * ks_rcv - read multiple pkts data from the QMU.
781 * @ks: The chip information
782 * @netdev: The network device being opened.
784 * Read all of header information before reading pkt content.
785 * It is not allowed only port of pkts in QMU after issuing
788 static void ks_rcv(struct ks_net *ks, struct net_device *netdev)
791 struct type_frame_head *frame_hdr = ks->frame_head_info;
794 ks->frame_cnt = ks_rdreg16(ks, KS_RXFCTR) >> 8;
796 /* read all header information */
797 for (i = 0; i < ks->frame_cnt; i++) {
798 /* Checking Received packet status */
799 frame_hdr->sts = ks_rdreg16(ks, KS_RXFHSR);
800 /* Get packet len from hardware */
801 frame_hdr->len = ks_rdreg16(ks, KS_RXFHBCR);
805 frame_hdr = ks->frame_head_info;
806 while (ks->frame_cnt--) {
807 if (unlikely(!(frame_hdr->sts & RXFSHR_RXFV) ||
808 frame_hdr->len >= RX_BUF_SIZE ||
809 frame_hdr->len <= 0)) {
811 /* discard an invalid packet */
812 ks_wrreg16(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF));
813 netdev->stats.rx_dropped++;
814 if (!(frame_hdr->sts & RXFSHR_RXFV))
815 netdev->stats.rx_frame_errors++;
817 netdev->stats.rx_length_errors++;
822 skb = netdev_alloc_skb(netdev, frame_hdr->len + 16);
825 /* read data block including CRC 4 bytes */
826 ks_read_qmu(ks, (u16 *)skb->data, frame_hdr->len);
827 skb_put(skb, frame_hdr->len - 4);
828 skb->protocol = eth_type_trans(skb, netdev);
830 /* exclude CRC size */
831 netdev->stats.rx_bytes += frame_hdr->len - 4;
832 netdev->stats.rx_packets++;
834 ks_wrreg16(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF));
835 netdev->stats.rx_dropped++;
842 * ks_update_link_status - link status update.
843 * @netdev: The network device being opened.
844 * @ks: The chip information
848 static void ks_update_link_status(struct net_device *netdev, struct ks_net *ks)
850 /* check the status of the link */
852 if (ks_rdreg16(ks, KS_P1SR) & P1SR_LINK_GOOD) {
853 netif_carrier_on(netdev);
854 link_up_status = true;
856 netif_carrier_off(netdev);
857 link_up_status = false;
859 netif_dbg(ks, link, ks->netdev,
860 "%s: %s\n", __func__, link_up_status ? "UP" : "DOWN");
864 * ks_irq - device interrupt handler
865 * @irq: Interrupt number passed from the IRQ handler.
866 * @pw: The private word passed to register_irq(), our struct ks_net.
868 * This is the handler invoked to find out what happened
870 * Read the interrupt status, work out what needs to be done and then clear
871 * any of the interrupts that are not needed.
874 static irqreturn_t ks_irq(int irq, void *pw)
876 struct net_device *netdev = pw;
877 struct ks_net *ks = netdev_priv(netdev);
881 spin_lock_irqsave(&ks->statelock, flags);
882 /*this should be the first in IRQ handler */
885 status = ks_rdreg16(ks, KS_ISR);
886 if (unlikely(!status)) {
887 ks_restore_cmd_reg(ks);
888 spin_unlock_irqrestore(&ks->statelock, flags);
892 ks_wrreg16(ks, KS_ISR, status);
894 if (likely(status & IRQ_RXI))
897 if (unlikely(status & IRQ_LCI))
898 ks_update_link_status(netdev, ks);
900 if (unlikely(status & IRQ_TXI))
901 netif_wake_queue(netdev);
903 if (unlikely(status & IRQ_LDI)) {
905 u16 pmecr = ks_rdreg16(ks, KS_PMECR);
906 pmecr &= ~PMECR_WKEVT_MASK;
907 ks_wrreg16(ks, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
910 if (unlikely(status & IRQ_RXOI))
911 ks->netdev->stats.rx_over_errors++;
912 /* this should be the last in IRQ handler*/
913 ks_restore_cmd_reg(ks);
914 spin_unlock_irqrestore(&ks->statelock, flags);
920 * ks_net_open - open network device
921 * @netdev: The network device being opened.
923 * Called when the network device is marked active, such as a user executing
924 * 'ifconfig up' on the device.
926 static int ks_net_open(struct net_device *netdev)
928 struct ks_net *ks = netdev_priv(netdev);
931 #define KS_INT_FLAGS IRQF_TRIGGER_LOW
932 /* lock the card, even if we may not actually do anything
933 * else at the moment.
936 netif_dbg(ks, ifup, ks->netdev, "%s - entry\n", __func__);
939 err = request_irq(netdev->irq, ks_irq, KS_INT_FLAGS, DRV_NAME, netdev);
942 pr_err("Failed to request IRQ: %d: %d\n", netdev->irq, err);
946 /* wake up powermode to normal mode */
947 ks_set_powermode(ks, PMECR_PM_NORMAL);
948 mdelay(1); /* wait for normal mode to take effect */
950 ks_wrreg16(ks, KS_ISR, 0xffff);
953 netif_start_queue(ks->netdev);
955 netif_dbg(ks, ifup, ks->netdev, "network device up\n");
961 * ks_net_stop - close network device
962 * @netdev: The device being closed.
964 * Called to close down a network device which has been active. Cancell any
965 * work, shutdown the RX and TX process and then place the chip into a low
966 * power state whilst it is not being used.
968 static int ks_net_stop(struct net_device *netdev)
970 struct ks_net *ks = netdev_priv(netdev);
972 netif_info(ks, ifdown, netdev, "shutting down\n");
974 netif_stop_queue(netdev);
976 mutex_lock(&ks->lock);
978 /* turn off the IRQs and ack any outstanding */
979 ks_wrreg16(ks, KS_IER, 0x0000);
980 ks_wrreg16(ks, KS_ISR, 0xffff);
982 /* shutdown RX/TX QMU */
986 /* set powermode to soft power down to save power */
987 ks_set_powermode(ks, PMECR_PM_SOFTDOWN);
988 free_irq(netdev->irq, netdev);
989 mutex_unlock(&ks->lock);
995 * ks_write_qmu - write 1 pkt data to the QMU.
996 * @ks: The chip information
997 * @pdata: buffer address to save 1 pkt
998 * @len: Pkt length in byte
999 * Here is the sequence to write 1 pkt:
1000 * 1. set sudo DMA mode
1001 * 2. write status/length
1003 * 4. reset sudo DMA Mode
1004 * 5. reset sudo DMA mode
1005 * 6. Wait until pkt is out
1007 static void ks_write_qmu(struct ks_net *ks, u8 *pdata, u16 len)
1009 /* start header at txb[0] to align txw entries */
1011 ks->txh.txw[1] = cpu_to_le16(len);
1013 /* 1. set sudo-DMA mode */
1014 ks_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr | RXQCR_SDA);
1015 /* 2. write status/lenth info */
1016 ks_outblk(ks, ks->txh.txw, 4);
1017 /* 3. write pkt data */
1018 ks_outblk(ks, (u16 *)pdata, ALIGN(len, 4));
1019 /* 4. reset sudo-DMA mode */
1020 ks_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr);
1021 /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
1022 ks_wrreg16(ks, KS_TXQCR, TXQCR_METFE);
1023 /* 6. wait until TXQCR_METFE is auto-cleared */
1024 while (ks_rdreg16(ks, KS_TXQCR) & TXQCR_METFE)
1029 * ks_start_xmit - transmit packet
1030 * @skb : The buffer to transmit
1031 * @netdev : The device used to transmit the packet.
1033 * Called by the network layer to transmit the @skb.
1034 * spin_lock_irqsave is required because tx and rx should be mutual exclusive.
1035 * So while tx is in-progress, prevent IRQ interrupt from happenning.
1037 static netdev_tx_t ks_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1039 netdev_tx_t retv = NETDEV_TX_OK;
1040 struct ks_net *ks = netdev_priv(netdev);
1041 unsigned long flags;
1043 spin_lock_irqsave(&ks->statelock, flags);
1045 /* Extra space are required:
1046 * 4 byte for alignment, 4 for status/length, 4 for CRC
1049 if (likely(ks_tx_fifo_space(ks) >= skb->len + 12)) {
1050 ks_write_qmu(ks, skb->data, skb->len);
1051 /* add tx statistics */
1052 netdev->stats.tx_bytes += skb->len;
1053 netdev->stats.tx_packets++;
1056 retv = NETDEV_TX_BUSY;
1057 spin_unlock_irqrestore(&ks->statelock, flags);
1062 * ks_start_rx - ready to serve pkts
1063 * @ks : The chip information
1066 static void ks_start_rx(struct ks_net *ks)
1070 /* Enables QMU Receive (RXCR1). */
1071 cntl = ks_rdreg16(ks, KS_RXCR1);
1073 ks_wrreg16(ks, KS_RXCR1, cntl);
1077 * ks_stop_rx - stop to serve pkts
1078 * @ks : The chip information
1081 static void ks_stop_rx(struct ks_net *ks)
1085 /* Disables QMU Receive (RXCR1). */
1086 cntl = ks_rdreg16(ks, KS_RXCR1);
1087 cntl &= ~RXCR1_RXE ;
1088 ks_wrreg16(ks, KS_RXCR1, cntl);
1092 static unsigned long const ethernet_polynomial = 0x04c11db7U;
1094 static unsigned long ether_gen_crc(int length, u8 *data)
1097 while (--length >= 0) {
1098 u8 current_octet = *data++;
1101 for (bit = 0; bit < 8; bit++, current_octet >>= 1) {
1103 ((crc < 0) ^ (current_octet & 1) ?
1104 ethernet_polynomial : 0);
1107 return (unsigned long)crc;
1108 } /* ether_gen_crc */
1111 * ks_set_grpaddr - set multicast information
1112 * @ks : The chip information
1115 static void ks_set_grpaddr(struct ks_net *ks)
1118 u32 index, position, value;
1120 memset(ks->mcast_bits, 0, sizeof(u8) * HW_MCAST_SIZE);
1122 for (i = 0; i < ks->mcast_lst_size; i++) {
1123 position = (ether_gen_crc(6, ks->mcast_lst[i]) >> 26) & 0x3f;
1124 index = position >> 3;
1125 value = 1 << (position & 7);
1126 ks->mcast_bits[index] |= (u8)value;
1129 for (i = 0; i < HW_MCAST_SIZE; i++) {
1131 ks_wrreg16(ks, (u16)((KS_MAHTR0 + i) & ~1),
1132 (ks->mcast_bits[i] << 8) |
1133 ks->mcast_bits[i - 1]);
1136 } /* ks_set_grpaddr */
1139 * ks_clear_mcast - clear multicast information
1141 * @ks : The chip information
1142 * This routine removes all mcast addresses set in the hardware.
1145 static void ks_clear_mcast(struct ks_net *ks)
1148 for (i = 0; i < HW_MCAST_SIZE; i++)
1149 ks->mcast_bits[i] = 0;
1151 mcast_size = HW_MCAST_SIZE >> 2;
1152 for (i = 0; i < mcast_size; i++)
1153 ks_wrreg16(ks, KS_MAHTR0 + (2*i), 0);
1156 static void ks_set_promis(struct ks_net *ks, u16 promiscuous_mode)
1159 ks->promiscuous = promiscuous_mode;
1160 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
1161 cntl = ks_rdreg16(ks, KS_RXCR1);
1163 cntl &= ~RXCR1_FILTER_MASK;
1164 if (promiscuous_mode)
1165 /* Enable Promiscuous mode */
1166 cntl |= RXCR1_RXAE | RXCR1_RXINVF;
1168 /* Disable Promiscuous mode (default normal mode) */
1169 cntl |= RXCR1_RXPAFMA;
1171 ks_wrreg16(ks, KS_RXCR1, cntl);
1176 } /* ks_set_promis */
1178 static void ks_set_mcast(struct ks_net *ks, u16 mcast)
1182 ks->all_mcast = mcast;
1183 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
1184 cntl = ks_rdreg16(ks, KS_RXCR1);
1185 cntl &= ~RXCR1_FILTER_MASK;
1187 /* Enable "Perfect with Multicast address passed mode" */
1188 cntl |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA);
1191 * Disable "Perfect with Multicast address passed
1192 * mode" (normal mode).
1194 cntl |= RXCR1_RXPAFMA;
1196 ks_wrreg16(ks, KS_RXCR1, cntl);
1200 } /* ks_set_mcast */
1202 static void ks_set_rx_mode(struct net_device *netdev)
1204 struct ks_net *ks = netdev_priv(netdev);
1205 struct netdev_hw_addr *ha;
1207 /* Turn on/off promiscuous mode. */
1208 if ((netdev->flags & IFF_PROMISC) == IFF_PROMISC)
1210 (u16)((netdev->flags & IFF_PROMISC) == IFF_PROMISC));
1211 /* Turn on/off all mcast mode. */
1212 else if ((netdev->flags & IFF_ALLMULTI) == IFF_ALLMULTI)
1214 (u16)((netdev->flags & IFF_ALLMULTI) == IFF_ALLMULTI));
1216 ks_set_promis(ks, false);
1218 if ((netdev->flags & IFF_MULTICAST) && netdev_mc_count(netdev)) {
1219 if (netdev_mc_count(netdev) <= MAX_MCAST_LST) {
1222 netdev_for_each_mc_addr(ha, netdev) {
1223 if (i >= MAX_MCAST_LST)
1225 memcpy(ks->mcast_lst[i++], ha->addr, ETH_ALEN);
1227 ks->mcast_lst_size = (u8)i;
1231 * List too big to support so
1232 * turn on all mcast mode.
1234 ks->mcast_lst_size = MAX_MCAST_LST;
1235 ks_set_mcast(ks, true);
1238 ks->mcast_lst_size = 0;
1241 } /* ks_set_rx_mode */
1243 static void ks_set_mac(struct ks_net *ks, u8 *data)
1245 u16 *pw = (u16 *)data;
1248 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
1251 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
1252 ks_wrreg16(ks, KS_MARH, w);
1255 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
1256 ks_wrreg16(ks, KS_MARM, w);
1259 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
1260 ks_wrreg16(ks, KS_MARL, w);
1262 memcpy(ks->mac_addr, data, ETH_ALEN);
1268 static int ks_set_mac_address(struct net_device *netdev, void *paddr)
1270 struct ks_net *ks = netdev_priv(netdev);
1271 struct sockaddr *addr = paddr;
1274 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1276 da = (u8 *)netdev->dev_addr;
1282 static int ks_net_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
1284 struct ks_net *ks = netdev_priv(netdev);
1286 if (!netif_running(netdev))
1289 return generic_mii_ioctl(&ks->mii, if_mii(req), cmd, NULL);
1292 static const struct net_device_ops ks_netdev_ops = {
1293 .ndo_open = ks_net_open,
1294 .ndo_stop = ks_net_stop,
1295 .ndo_do_ioctl = ks_net_ioctl,
1296 .ndo_start_xmit = ks_start_xmit,
1297 .ndo_set_mac_address = ks_set_mac_address,
1298 .ndo_set_rx_mode = ks_set_rx_mode,
1299 .ndo_validate_addr = eth_validate_addr,
1302 /* ethtool support */
1304 static void ks_get_drvinfo(struct net_device *netdev,
1305 struct ethtool_drvinfo *di)
1307 strlcpy(di->driver, DRV_NAME, sizeof(di->driver));
1308 strlcpy(di->version, "1.00", sizeof(di->version));
1309 strlcpy(di->bus_info, dev_name(netdev->dev.parent),
1310 sizeof(di->bus_info));
1313 static u32 ks_get_msglevel(struct net_device *netdev)
1315 struct ks_net *ks = netdev_priv(netdev);
1316 return ks->msg_enable;
1319 static void ks_set_msglevel(struct net_device *netdev, u32 to)
1321 struct ks_net *ks = netdev_priv(netdev);
1322 ks->msg_enable = to;
1325 static int ks_get_link_ksettings(struct net_device *netdev,
1326 struct ethtool_link_ksettings *cmd)
1328 struct ks_net *ks = netdev_priv(netdev);
1330 mii_ethtool_get_link_ksettings(&ks->mii, cmd);
1335 static int ks_set_link_ksettings(struct net_device *netdev,
1336 const struct ethtool_link_ksettings *cmd)
1338 struct ks_net *ks = netdev_priv(netdev);
1339 return mii_ethtool_set_link_ksettings(&ks->mii, cmd);
1342 static u32 ks_get_link(struct net_device *netdev)
1344 struct ks_net *ks = netdev_priv(netdev);
1345 return mii_link_ok(&ks->mii);
1348 static int ks_nway_reset(struct net_device *netdev)
1350 struct ks_net *ks = netdev_priv(netdev);
1351 return mii_nway_restart(&ks->mii);
1354 static const struct ethtool_ops ks_ethtool_ops = {
1355 .get_drvinfo = ks_get_drvinfo,
1356 .get_msglevel = ks_get_msglevel,
1357 .set_msglevel = ks_set_msglevel,
1358 .get_link = ks_get_link,
1359 .nway_reset = ks_nway_reset,
1360 .get_link_ksettings = ks_get_link_ksettings,
1361 .set_link_ksettings = ks_set_link_ksettings,
1364 /* MII interface controls */
1367 * ks_phy_reg - convert MII register into a KS8851 register
1368 * @reg: MII register number.
1370 * Return the KS8851 register number for the corresponding MII PHY register
1371 * if possible. Return zero if the MII register has no direct mapping to the
1372 * KS8851 register set.
1374 static int ks_phy_reg(int reg)
1395 * ks_phy_read - MII interface PHY register read.
1396 * @netdev: The network device the PHY is on.
1397 * @phy_addr: Address of PHY (ignored as we only have one)
1398 * @reg: The register to read.
1400 * This call reads data from the PHY register specified in @reg. Since the
1401 * device does not support all the MII registers, the non-existent values
1402 * are always returned as zero.
1404 * We return zero for unsupported registers as the MII code does not check
1405 * the value returned for any error status, and simply returns it to the
1406 * caller. The mii-tool that the driver was tested with takes any -ve error
1407 * as real PHY capabilities, thus displaying incorrect data to the user.
1409 static int ks_phy_read(struct net_device *netdev, int phy_addr, int reg)
1411 struct ks_net *ks = netdev_priv(netdev);
1415 ksreg = ks_phy_reg(reg);
1417 return 0x0; /* no error return allowed, so use zero */
1419 mutex_lock(&ks->lock);
1420 result = ks_rdreg16(ks, ksreg);
1421 mutex_unlock(&ks->lock);
1426 static void ks_phy_write(struct net_device *netdev,
1427 int phy, int reg, int value)
1429 struct ks_net *ks = netdev_priv(netdev);
1432 ksreg = ks_phy_reg(reg);
1434 mutex_lock(&ks->lock);
1435 ks_wrreg16(ks, ksreg, value);
1436 mutex_unlock(&ks->lock);
1441 * ks_read_selftest - read the selftest memory info.
1442 * @ks: The device state
1444 * Read and check the TX/RX memory selftest information.
1446 static int ks_read_selftest(struct ks_net *ks)
1448 unsigned both_done = MBIR_TXMBF | MBIR_RXMBF;
1452 rd = ks_rdreg16(ks, KS_MBIR);
1454 if ((rd & both_done) != both_done) {
1455 netdev_warn(ks->netdev, "Memory selftest not finished\n");
1459 if (rd & MBIR_TXMBFA) {
1460 netdev_err(ks->netdev, "TX memory selftest fails\n");
1464 if (rd & MBIR_RXMBFA) {
1465 netdev_err(ks->netdev, "RX memory selftest fails\n");
1469 netdev_info(ks->netdev, "the selftest passes\n");
1473 static void ks_setup(struct ks_net *ks)
1478 * Configure QMU Transmit
1481 /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
1482 ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
1484 /* Setup Receive Frame Data Pointer Auto-Increment */
1485 ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
1487 /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
1488 ks_wrreg16(ks, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
1490 /* Setup RxQ Command Control (RXQCR) */
1491 ks->rc_rxqcr = RXQCR_CMD_CNTL;
1492 ks_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr);
1495 * set the force mode to half duplex, default is full duplex
1496 * because if the auto-negotiation fails, most switch uses
1500 w = ks_rdreg16(ks, KS_P1MBCR);
1501 w &= ~P1MBCR_FORCE_FDX;
1502 ks_wrreg16(ks, KS_P1MBCR, w);
1504 w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
1505 ks_wrreg16(ks, KS_TXCR, w);
1507 w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
1509 if (ks->promiscuous) /* bPromiscuous */
1510 w |= (RXCR1_RXAE | RXCR1_RXINVF);
1511 else if (ks->all_mcast) /* Multicast address passed mode */
1512 w |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA);
1513 else /* Normal mode */
1516 ks_wrreg16(ks, KS_RXCR1, w);
1520 static void ks_setup_int(struct ks_net *ks)
1523 /* Clear the interrupts status of the hardware. */
1524 ks_wrreg16(ks, KS_ISR, 0xffff);
1526 /* Enables the interrupts of the hardware. */
1527 ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI);
1528 } /* ks_setup_int */
1530 static int ks_hw_init(struct ks_net *ks)
1532 #define MHEADER_SIZE (sizeof(struct type_frame_head) * MAX_RECV_FRAMES)
1533 ks->promiscuous = 0;
1535 ks->mcast_lst_size = 0;
1537 ks->frame_head_info = devm_kmalloc(&ks->pdev->dev, MHEADER_SIZE,
1539 if (!ks->frame_head_info)
1542 ks_set_mac(ks, KS_DEFAULT_MAC_ADDRESS);
1546 #if defined(CONFIG_OF)
1547 static const struct of_device_id ks8851_ml_dt_ids[] = {
1548 { .compatible = "micrel,ks8851-mll" },
1551 MODULE_DEVICE_TABLE(of, ks8851_ml_dt_ids);
1554 static int ks8851_probe(struct platform_device *pdev)
1557 struct resource *io_d, *io_c;
1558 struct net_device *netdev;
1563 netdev = alloc_etherdev(sizeof(struct ks_net));
1567 SET_NETDEV_DEV(netdev, &pdev->dev);
1569 ks = netdev_priv(netdev);
1570 ks->netdev = netdev;
1572 io_d = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1573 ks->hw_addr = devm_ioremap_resource(&pdev->dev, io_d);
1574 if (IS_ERR(ks->hw_addr)) {
1575 err = PTR_ERR(ks->hw_addr);
1579 io_c = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1580 ks->hw_addr_cmd = devm_ioremap_resource(&pdev->dev, io_c);
1581 if (IS_ERR(ks->hw_addr_cmd)) {
1582 err = PTR_ERR(ks->hw_addr_cmd);
1586 err = ks_check_endian(ks);
1590 netdev->irq = platform_get_irq(pdev, 0);
1592 if ((int)netdev->irq < 0) {
1599 mutex_init(&ks->lock);
1600 spin_lock_init(&ks->statelock);
1602 netdev->netdev_ops = &ks_netdev_ops;
1603 netdev->ethtool_ops = &ks_ethtool_ops;
1605 /* setup mii state */
1606 ks->mii.dev = netdev;
1608 ks->mii.phy_id_mask = 1;
1609 ks->mii.reg_num_mask = 0xf;
1610 ks->mii.mdio_read = ks_phy_read;
1611 ks->mii.mdio_write = ks_phy_write;
1613 netdev_info(netdev, "message enable is %d\n", msg_enable);
1614 /* set the default message enable */
1615 ks->msg_enable = netif_msg_init(msg_enable, (NETIF_MSG_DRV |
1620 /* simple check for a valid chip being connected to the bus */
1621 if ((ks_rdreg16(ks, KS_CIDER) & ~CIDER_REV_MASK) != CIDER_ID) {
1622 netdev_err(netdev, "failed to read device ID\n");
1627 if (ks_read_selftest(ks)) {
1628 netdev_err(netdev, "failed to read device ID\n");
1633 err = register_netdev(netdev);
1637 platform_set_drvdata(pdev, netdev);
1639 ks_soft_reset(ks, GRR_GSR);
1645 data = ks_rdreg16(ks, KS_OBCR);
1646 ks_wrreg16(ks, KS_OBCR, data | OBCR_ODS_16MA);
1648 /* overwriting the default MAC address */
1649 if (pdev->dev.of_node) {
1650 mac = of_get_mac_address(pdev->dev.of_node);
1652 memcpy(ks->mac_addr, mac, ETH_ALEN);
1654 struct ks8851_mll_platform_data *pdata;
1656 pdata = dev_get_platdata(&pdev->dev);
1658 netdev_err(netdev, "No platform data\n");
1662 memcpy(ks->mac_addr, pdata->mac_addr, ETH_ALEN);
1664 if (!is_valid_ether_addr(ks->mac_addr)) {
1665 /* Use random MAC address if none passed */
1666 eth_random_addr(ks->mac_addr);
1667 netdev_info(netdev, "Using random mac address\n");
1669 netdev_info(netdev, "Mac address is: %pM\n", ks->mac_addr);
1671 memcpy(netdev->dev_addr, ks->mac_addr, ETH_ALEN);
1673 ks_set_mac(ks, netdev->dev_addr);
1675 id = ks_rdreg16(ks, KS_CIDER);
1677 netdev_info(netdev, "Found chip, family: 0x%x, id: 0x%x, rev: 0x%x\n",
1678 (id >> 8) & 0xff, (id >> 4) & 0xf, (id >> 1) & 0x7);
1682 unregister_netdev(netdev);
1684 free_netdev(netdev);
1688 static int ks8851_remove(struct platform_device *pdev)
1690 struct net_device *netdev = platform_get_drvdata(pdev);
1692 unregister_netdev(netdev);
1693 free_netdev(netdev);
1698 static struct platform_driver ks8851_platform_driver = {
1701 .of_match_table = of_match_ptr(ks8851_ml_dt_ids),
1703 .probe = ks8851_probe,
1704 .remove = ks8851_remove,
1707 module_platform_driver(ks8851_platform_driver);
1709 MODULE_DESCRIPTION("KS8851 MLL Network driver");
1710 MODULE_AUTHOR("David Choi <david.choi@micrel.com>");
1711 MODULE_LICENSE("GPL");
1712 module_param_named(message, msg_enable, int, 0);
1713 MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");