1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
4 #include <linux/netdevice.h>
5 #include <linux/string.h>
6 #include <linux/bitops.h>
12 static u8 mlxsw_sp_dcbnl_getdcbx(struct net_device __always_unused *dev)
14 return DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
17 static u8 mlxsw_sp_dcbnl_setdcbx(struct net_device __always_unused *dev,
20 return (mode != (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE)) ? 1 : 0;
23 static int mlxsw_sp_dcbnl_ieee_getets(struct net_device *dev,
26 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
28 memcpy(ets, mlxsw_sp_port->dcb.ets, sizeof(*ets));
33 static int mlxsw_sp_port_ets_validate(struct mlxsw_sp_port *mlxsw_sp_port,
36 struct net_device *dev = mlxsw_sp_port->dev;
37 bool has_ets_tc = false;
40 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
41 switch (ets->tc_tsa[i]) {
42 case IEEE_8021QAZ_TSA_STRICT:
44 case IEEE_8021QAZ_TSA_ETS:
46 tx_bw_sum += ets->tc_tx_bw[i];
49 netdev_err(dev, "Only strict priority and ETS are supported\n");
53 if (ets->prio_tc[i] >= IEEE_8021QAZ_MAX_TCS) {
54 netdev_err(dev, "Invalid TC\n");
59 if (has_ets_tc && tx_bw_sum != 100) {
60 netdev_err(dev, "Total ETS bandwidth should equal 100\n");
67 static int mlxsw_sp_port_pg_prio_map(struct mlxsw_sp_port *mlxsw_sp_port,
70 char pptb_pl[MLXSW_REG_PPTB_LEN];
73 mlxsw_reg_pptb_pack(pptb_pl, mlxsw_sp_port->local_port);
74 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
75 mlxsw_reg_pptb_prio_to_buff_pack(pptb_pl, i, prio_tc[i]);
77 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pptb),
81 static bool mlxsw_sp_ets_has_pg(u8 *prio_tc, u8 pg)
85 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
91 static int mlxsw_sp_port_pg_destroy(struct mlxsw_sp_port *mlxsw_sp_port,
92 u8 *old_prio_tc, u8 *new_prio_tc)
94 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
95 char pbmc_pl[MLXSW_REG_PBMC_LEN];
98 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
99 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
103 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
104 u8 pg = old_prio_tc[i];
106 if (!mlxsw_sp_ets_has_pg(new_prio_tc, pg))
107 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg, 0);
110 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
113 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
114 struct ieee_ets *ets)
116 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
117 struct ieee_ets *my_ets = mlxsw_sp_port->dcb.ets;
118 struct net_device *dev = mlxsw_sp_port->dev;
121 /* Create the required PGs, but don't destroy existing ones, as
122 * traffic is still directed to them.
124 err = __mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu,
125 ets->prio_tc, pause_en,
126 mlxsw_sp_port->dcb.pfc);
128 netdev_err(dev, "Failed to configure port's headroom\n");
132 err = mlxsw_sp_port_pg_prio_map(mlxsw_sp_port, ets->prio_tc);
134 netdev_err(dev, "Failed to set PG-priority mapping\n");
135 goto err_port_prio_pg_map;
138 err = mlxsw_sp_port_pg_destroy(mlxsw_sp_port, my_ets->prio_tc,
141 netdev_warn(dev, "Failed to remove ununsed PGs\n");
145 err_port_prio_pg_map:
146 mlxsw_sp_port_pg_destroy(mlxsw_sp_port, ets->prio_tc, my_ets->prio_tc);
150 static int __mlxsw_sp_dcbnl_ieee_setets(struct mlxsw_sp_port *mlxsw_sp_port,
151 struct ieee_ets *ets)
153 struct ieee_ets *my_ets = mlxsw_sp_port->dcb.ets;
154 struct net_device *dev = mlxsw_sp_port->dev;
157 /* Egress configuration. */
158 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
159 bool dwrr = ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS;
160 u8 weight = ets->tc_tx_bw[i];
162 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
163 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
166 netdev_err(dev, "Failed to link subgroup ETS element %d to group\n",
168 goto err_port_ets_set;
172 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
173 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i,
176 netdev_err(dev, "Failed to map prio %d to TC %d\n", i,
178 goto err_port_prio_tc_set;
182 /* Ingress configuration. */
183 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, ets);
185 goto err_port_headroom_set;
189 err_port_headroom_set:
190 i = IEEE_8021QAZ_MAX_TCS;
191 err_port_prio_tc_set:
192 for (i--; i >= 0; i--)
193 mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, my_ets->prio_tc[i]);
194 i = IEEE_8021QAZ_MAX_TCS;
196 for (i--; i >= 0; i--) {
197 bool dwrr = my_ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS;
198 u8 weight = my_ets->tc_tx_bw[i];
200 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
201 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
207 static int mlxsw_sp_dcbnl_ieee_setets(struct net_device *dev,
208 struct ieee_ets *ets)
210 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
213 err = mlxsw_sp_port_ets_validate(mlxsw_sp_port, ets);
217 err = __mlxsw_sp_dcbnl_ieee_setets(mlxsw_sp_port, ets);
221 memcpy(mlxsw_sp_port->dcb.ets, ets, sizeof(*ets));
222 mlxsw_sp_port->dcb.ets->ets_cap = IEEE_8021QAZ_MAX_TCS;
227 static int mlxsw_sp_dcbnl_app_validate(struct net_device *dev,
230 if (app->priority >= IEEE_8021QAZ_MAX_TCS) {
231 netdev_err(dev, "APP entry with priority value %u is invalid\n",
236 switch (app->selector) {
237 case IEEE_8021QAZ_APP_SEL_DSCP:
238 if (app->protocol >= 64) {
239 netdev_err(dev, "DSCP APP entry with protocol value %u is invalid\n",
245 case IEEE_8021QAZ_APP_SEL_ETHERTYPE:
247 netdev_err(dev, "EtherType APP entries with protocol value != 0 not supported\n");
253 netdev_err(dev, "APP entries with selector %u not supported\n",
262 mlxsw_sp_port_dcb_app_default_prio(struct mlxsw_sp_port *mlxsw_sp_port)
266 prio_mask = dcb_ieee_getapp_default_prio_mask(mlxsw_sp_port->dev);
268 /* Take the highest configured priority. */
269 return fls(prio_mask) - 1;
275 mlxsw_sp_port_dcb_app_dscp_prio_map(struct mlxsw_sp_port *mlxsw_sp_port,
277 struct dcb_ieee_app_dscp_map *map)
281 dcb_ieee_getapp_dscp_prio_mask_map(mlxsw_sp_port->dev, map);
282 for (i = 0; i < ARRAY_SIZE(map->map); ++i) {
284 map->map[i] = fls(map->map[i]) - 1;
286 map->map[i] = default_prio;
291 mlxsw_sp_port_dcb_app_prio_dscp_map(struct mlxsw_sp_port *mlxsw_sp_port,
292 struct dcb_ieee_app_prio_map *map)
294 bool have_dscp = false;
297 dcb_ieee_getapp_prio_dscp_mask_map(mlxsw_sp_port->dev, map);
298 for (i = 0; i < ARRAY_SIZE(map->map); ++i) {
300 map->map[i] = fls64(map->map[i]) - 1;
309 mlxsw_sp_port_dcb_app_update_qpts(struct mlxsw_sp_port *mlxsw_sp_port,
310 enum mlxsw_reg_qpts_trust_state ts)
312 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
313 char qpts_pl[MLXSW_REG_QPTS_LEN];
315 mlxsw_reg_qpts_pack(qpts_pl, mlxsw_sp_port->local_port, ts);
316 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qpts), qpts_pl);
320 mlxsw_sp_port_dcb_app_update_qrwe(struct mlxsw_sp_port *mlxsw_sp_port,
323 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
324 char qrwe_pl[MLXSW_REG_QRWE_LEN];
326 mlxsw_reg_qrwe_pack(qrwe_pl, mlxsw_sp_port->local_port,
327 false, rewrite_dscp);
328 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qrwe), qrwe_pl);
332 mlxsw_sp_port_dcb_toggle_trust(struct mlxsw_sp_port *mlxsw_sp_port,
333 enum mlxsw_reg_qpts_trust_state ts)
335 bool rewrite_dscp = ts == MLXSW_REG_QPTS_TRUST_STATE_DSCP;
338 if (mlxsw_sp_port->dcb.trust_state == ts)
341 err = mlxsw_sp_port_dcb_app_update_qpts(mlxsw_sp_port, ts);
345 err = mlxsw_sp_port_dcb_app_update_qrwe(mlxsw_sp_port, rewrite_dscp);
347 goto err_update_qrwe;
349 mlxsw_sp_port->dcb.trust_state = ts;
353 mlxsw_sp_port_dcb_app_update_qpts(mlxsw_sp_port,
354 mlxsw_sp_port->dcb.trust_state);
359 mlxsw_sp_port_dcb_app_update_qpdpm(struct mlxsw_sp_port *mlxsw_sp_port,
360 struct dcb_ieee_app_dscp_map *map)
362 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
363 char qpdpm_pl[MLXSW_REG_QPDPM_LEN];
366 mlxsw_reg_qpdpm_pack(qpdpm_pl, mlxsw_sp_port->local_port);
367 for (i = 0; i < ARRAY_SIZE(map->map); ++i)
368 mlxsw_reg_qpdpm_dscp_pack(qpdpm_pl, i, map->map[i]);
369 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qpdpm), qpdpm_pl);
373 mlxsw_sp_port_dcb_app_update_qpdsm(struct mlxsw_sp_port *mlxsw_sp_port,
374 struct dcb_ieee_app_prio_map *map)
376 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
377 char qpdsm_pl[MLXSW_REG_QPDSM_LEN];
380 mlxsw_reg_qpdsm_pack(qpdsm_pl, mlxsw_sp_port->local_port);
381 for (i = 0; i < ARRAY_SIZE(map->map); ++i)
382 mlxsw_reg_qpdsm_prio_pack(qpdsm_pl, i, map->map[i]);
383 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qpdsm), qpdsm_pl);
386 static int mlxsw_sp_port_dcb_app_update(struct mlxsw_sp_port *mlxsw_sp_port)
388 struct dcb_ieee_app_prio_map prio_map;
389 struct dcb_ieee_app_dscp_map dscp_map;
394 default_prio = mlxsw_sp_port_dcb_app_default_prio(mlxsw_sp_port);
395 have_dscp = mlxsw_sp_port_dcb_app_prio_dscp_map(mlxsw_sp_port,
398 mlxsw_sp_port_dcb_app_dscp_prio_map(mlxsw_sp_port, default_prio,
400 err = mlxsw_sp_port_dcb_app_update_qpdpm(mlxsw_sp_port,
403 netdev_err(mlxsw_sp_port->dev, "Couldn't configure priority map\n");
407 err = mlxsw_sp_port_dcb_app_update_qpdsm(mlxsw_sp_port,
410 netdev_err(mlxsw_sp_port->dev, "Couldn't configure DSCP rewrite map\n");
415 err = mlxsw_sp_port_dcb_toggle_trust(mlxsw_sp_port,
416 MLXSW_REG_QPTS_TRUST_STATE_PCP);
418 netdev_err(mlxsw_sp_port->dev, "Couldn't switch to trust L2\n");
422 err = mlxsw_sp_port_dcb_toggle_trust(mlxsw_sp_port,
423 MLXSW_REG_QPTS_TRUST_STATE_DSCP);
425 /* A failure to set trust DSCP means that the QPDPM and QPDSM
426 * maps installed above are not in effect. And since we are here
427 * attempting to set trust DSCP, we couldn't have attempted to
428 * switch trust to PCP. Thus no cleanup is necessary.
430 netdev_err(mlxsw_sp_port->dev, "Couldn't switch to trust L3\n");
437 static int mlxsw_sp_dcbnl_ieee_setapp(struct net_device *dev,
440 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
443 err = mlxsw_sp_dcbnl_app_validate(dev, app);
447 err = dcb_ieee_setapp(dev, app);
451 err = mlxsw_sp_port_dcb_app_update(mlxsw_sp_port);
458 dcb_ieee_delapp(dev, app);
462 static int mlxsw_sp_dcbnl_ieee_delapp(struct net_device *dev,
465 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
468 err = dcb_ieee_delapp(dev, app);
472 err = mlxsw_sp_port_dcb_app_update(mlxsw_sp_port);
474 netdev_err(dev, "Failed to update DCB APP configuration\n");
478 static int mlxsw_sp_dcbnl_ieee_getmaxrate(struct net_device *dev,
479 struct ieee_maxrate *maxrate)
481 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
483 memcpy(maxrate, mlxsw_sp_port->dcb.maxrate, sizeof(*maxrate));
488 static int mlxsw_sp_dcbnl_ieee_setmaxrate(struct net_device *dev,
489 struct ieee_maxrate *maxrate)
491 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
492 struct ieee_maxrate *my_maxrate = mlxsw_sp_port->dcb.maxrate;
495 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
496 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
497 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
499 maxrate->tc_maxrate[i]);
501 netdev_err(dev, "Failed to set maxrate for TC %d\n", i);
502 goto err_port_ets_maxrate_set;
506 memcpy(mlxsw_sp_port->dcb.maxrate, maxrate, sizeof(*maxrate));
510 err_port_ets_maxrate_set:
511 for (i--; i >= 0; i--)
512 mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
513 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
514 i, 0, my_maxrate->tc_maxrate[i]);
518 static int mlxsw_sp_port_pfc_cnt_get(struct mlxsw_sp_port *mlxsw_sp_port,
521 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
522 struct ieee_pfc *my_pfc = mlxsw_sp_port->dcb.pfc;
523 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
526 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port,
527 MLXSW_REG_PPCNT_PRIO_CNT, prio);
528 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
532 my_pfc->requests[prio] = mlxsw_reg_ppcnt_tx_pause_get(ppcnt_pl);
533 my_pfc->indications[prio] = mlxsw_reg_ppcnt_rx_pause_get(ppcnt_pl);
538 static int mlxsw_sp_dcbnl_ieee_getpfc(struct net_device *dev,
539 struct ieee_pfc *pfc)
541 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
544 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
545 err = mlxsw_sp_port_pfc_cnt_get(mlxsw_sp_port, i);
547 netdev_err(dev, "Failed to get PFC count for priority %d\n",
553 memcpy(pfc, mlxsw_sp_port->dcb.pfc, sizeof(*pfc));
558 static int mlxsw_sp_port_pfc_set(struct mlxsw_sp_port *mlxsw_sp_port,
559 struct ieee_pfc *pfc)
561 char pfcc_pl[MLXSW_REG_PFCC_LEN];
563 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
564 mlxsw_reg_pfcc_pprx_set(pfcc_pl, mlxsw_sp_port->link.rx_pause);
565 mlxsw_reg_pfcc_pptx_set(pfcc_pl, mlxsw_sp_port->link.tx_pause);
566 mlxsw_reg_pfcc_prio_pack(pfcc_pl, pfc->pfc_en);
568 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
572 static int mlxsw_sp_dcbnl_ieee_setpfc(struct net_device *dev,
573 struct ieee_pfc *pfc)
575 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
576 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
579 if (pause_en && pfc->pfc_en) {
580 netdev_err(dev, "PAUSE frames already enabled on port\n");
584 err = __mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu,
585 mlxsw_sp_port->dcb.ets->prio_tc,
588 netdev_err(dev, "Failed to configure port's headroom for PFC\n");
592 err = mlxsw_sp_port_pfc_set(mlxsw_sp_port, pfc);
594 netdev_err(dev, "Failed to configure PFC\n");
595 goto err_port_pfc_set;
598 memcpy(mlxsw_sp_port->dcb.pfc, pfc, sizeof(*pfc));
599 mlxsw_sp_port->dcb.pfc->pfc_cap = IEEE_8021QAZ_MAX_TCS;
604 __mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu,
605 mlxsw_sp_port->dcb.ets->prio_tc, pause_en,
606 mlxsw_sp_port->dcb.pfc);
610 static const struct dcbnl_rtnl_ops mlxsw_sp_dcbnl_ops = {
611 .ieee_getets = mlxsw_sp_dcbnl_ieee_getets,
612 .ieee_setets = mlxsw_sp_dcbnl_ieee_setets,
613 .ieee_getmaxrate = mlxsw_sp_dcbnl_ieee_getmaxrate,
614 .ieee_setmaxrate = mlxsw_sp_dcbnl_ieee_setmaxrate,
615 .ieee_getpfc = mlxsw_sp_dcbnl_ieee_getpfc,
616 .ieee_setpfc = mlxsw_sp_dcbnl_ieee_setpfc,
617 .ieee_setapp = mlxsw_sp_dcbnl_ieee_setapp,
618 .ieee_delapp = mlxsw_sp_dcbnl_ieee_delapp,
620 .getdcbx = mlxsw_sp_dcbnl_getdcbx,
621 .setdcbx = mlxsw_sp_dcbnl_setdcbx,
624 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
626 mlxsw_sp_port->dcb.ets = kzalloc(sizeof(*mlxsw_sp_port->dcb.ets),
628 if (!mlxsw_sp_port->dcb.ets)
631 mlxsw_sp_port->dcb.ets->ets_cap = IEEE_8021QAZ_MAX_TCS;
636 static void mlxsw_sp_port_ets_fini(struct mlxsw_sp_port *mlxsw_sp_port)
638 kfree(mlxsw_sp_port->dcb.ets);
641 static int mlxsw_sp_port_maxrate_init(struct mlxsw_sp_port *mlxsw_sp_port)
645 mlxsw_sp_port->dcb.maxrate = kmalloc(sizeof(*mlxsw_sp_port->dcb.maxrate),
647 if (!mlxsw_sp_port->dcb.maxrate)
650 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
651 mlxsw_sp_port->dcb.maxrate->tc_maxrate[i] = MLXSW_REG_QEEC_MAS_DIS;
656 static void mlxsw_sp_port_maxrate_fini(struct mlxsw_sp_port *mlxsw_sp_port)
658 kfree(mlxsw_sp_port->dcb.maxrate);
661 static int mlxsw_sp_port_pfc_init(struct mlxsw_sp_port *mlxsw_sp_port)
663 mlxsw_sp_port->dcb.pfc = kzalloc(sizeof(*mlxsw_sp_port->dcb.pfc),
665 if (!mlxsw_sp_port->dcb.pfc)
668 mlxsw_sp_port->dcb.pfc->pfc_cap = IEEE_8021QAZ_MAX_TCS;
673 static void mlxsw_sp_port_pfc_fini(struct mlxsw_sp_port *mlxsw_sp_port)
675 kfree(mlxsw_sp_port->dcb.pfc);
678 int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port)
682 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
685 err = mlxsw_sp_port_maxrate_init(mlxsw_sp_port);
687 goto err_port_maxrate_init;
688 err = mlxsw_sp_port_pfc_init(mlxsw_sp_port);
690 goto err_port_pfc_init;
692 mlxsw_sp_port->dcb.trust_state = MLXSW_REG_QPTS_TRUST_STATE_PCP;
693 mlxsw_sp_port->dev->dcbnl_ops = &mlxsw_sp_dcbnl_ops;
698 mlxsw_sp_port_maxrate_fini(mlxsw_sp_port);
699 err_port_maxrate_init:
700 mlxsw_sp_port_ets_fini(mlxsw_sp_port);
704 void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port)
706 mlxsw_sp_port_pfc_fini(mlxsw_sp_port);
707 mlxsw_sp_port_maxrate_fini(mlxsw_sp_port);
708 mlxsw_sp_port_ets_fini(mlxsw_sp_port);