1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
4 #include <linux/netdevice.h>
5 #include <linux/string.h>
6 #include <linux/bitops.h>
12 static u8 mlxsw_sp_dcbnl_getdcbx(struct net_device __always_unused *dev)
14 return DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
17 static u8 mlxsw_sp_dcbnl_setdcbx(struct net_device __always_unused *dev,
20 return (mode != (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE)) ? 1 : 0;
23 static int mlxsw_sp_dcbnl_ieee_getets(struct net_device *dev,
26 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
28 memcpy(ets, mlxsw_sp_port->dcb.ets, sizeof(*ets));
33 static int mlxsw_sp_port_ets_validate(struct mlxsw_sp_port *mlxsw_sp_port,
36 struct net_device *dev = mlxsw_sp_port->dev;
37 bool has_ets_tc = false;
40 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
41 switch (ets->tc_tsa[i]) {
42 case IEEE_8021QAZ_TSA_STRICT:
44 case IEEE_8021QAZ_TSA_ETS:
46 tx_bw_sum += ets->tc_tx_bw[i];
49 netdev_err(dev, "Only strict priority and ETS are supported\n");
53 if (ets->prio_tc[i] >= IEEE_8021QAZ_MAX_TCS) {
54 netdev_err(dev, "Invalid TC\n");
59 if (has_ets_tc && tx_bw_sum != 100) {
60 netdev_err(dev, "Total ETS bandwidth should equal 100\n");
67 static int mlxsw_sp_port_headroom_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
70 struct net_device *dev = mlxsw_sp_port->dev;
71 struct mlxsw_sp_hdroom hdroom;
75 hdroom = *mlxsw_sp_port->hdroom;
76 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++)
77 hdroom.prios.prio[prio].ets_buf_idx = ets->prio_tc[prio];
78 mlxsw_sp_hdroom_prios_reset_buf_idx(&hdroom);
79 mlxsw_sp_hdroom_bufs_reset_lossiness(&hdroom);
80 mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom);
82 err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom);
84 netdev_err(dev, "Failed to configure port's headroom\n");
91 static int __mlxsw_sp_dcbnl_ieee_setets(struct mlxsw_sp_port *mlxsw_sp_port,
94 struct ieee_ets *my_ets = mlxsw_sp_port->dcb.ets;
95 struct net_device *dev = mlxsw_sp_port->dev;
98 /* Egress configuration. */
99 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
100 bool dwrr = ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS;
101 u8 weight = ets->tc_tx_bw[i];
103 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
104 MLXSW_REG_QEEC_HR_SUBGROUP, i,
107 netdev_err(dev, "Failed to link subgroup ETS element %d to group\n",
109 goto err_port_ets_set;
113 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
114 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i,
117 netdev_err(dev, "Failed to map prio %d to TC %d\n", i,
119 goto err_port_prio_tc_set;
123 /* Ingress configuration. */
124 err = mlxsw_sp_port_headroom_ets_set(mlxsw_sp_port, ets);
126 goto err_port_headroom_set;
130 err_port_headroom_set:
131 i = IEEE_8021QAZ_MAX_TCS;
132 err_port_prio_tc_set:
133 for (i--; i >= 0; i--)
134 mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, my_ets->prio_tc[i]);
135 i = IEEE_8021QAZ_MAX_TCS;
137 for (i--; i >= 0; i--) {
138 bool dwrr = my_ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS;
139 u8 weight = my_ets->tc_tx_bw[i];
141 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
142 MLXSW_REG_QEEC_HR_SUBGROUP, i,
148 static int mlxsw_sp_dcbnl_ieee_setets(struct net_device *dev,
149 struct ieee_ets *ets)
151 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
154 err = mlxsw_sp_port_ets_validate(mlxsw_sp_port, ets);
158 err = __mlxsw_sp_dcbnl_ieee_setets(mlxsw_sp_port, ets);
162 memcpy(mlxsw_sp_port->dcb.ets, ets, sizeof(*ets));
163 mlxsw_sp_port->dcb.ets->ets_cap = IEEE_8021QAZ_MAX_TCS;
168 static int mlxsw_sp_dcbnl_app_validate(struct net_device *dev,
171 if (app->priority >= IEEE_8021QAZ_MAX_TCS) {
172 netdev_err(dev, "APP entry with priority value %u is invalid\n",
177 switch (app->selector) {
178 case IEEE_8021QAZ_APP_SEL_DSCP:
179 if (app->protocol >= 64) {
180 netdev_err(dev, "DSCP APP entry with protocol value %u is invalid\n",
186 case IEEE_8021QAZ_APP_SEL_ETHERTYPE:
188 netdev_err(dev, "EtherType APP entries with protocol value != 0 not supported\n");
194 netdev_err(dev, "APP entries with selector %u not supported\n",
203 mlxsw_sp_port_dcb_app_default_prio(struct mlxsw_sp_port *mlxsw_sp_port)
207 prio_mask = dcb_ieee_getapp_default_prio_mask(mlxsw_sp_port->dev);
209 /* Take the highest configured priority. */
210 return fls(prio_mask) - 1;
216 mlxsw_sp_port_dcb_app_dscp_prio_map(struct mlxsw_sp_port *mlxsw_sp_port,
218 struct dcb_ieee_app_dscp_map *map)
222 dcb_ieee_getapp_dscp_prio_mask_map(mlxsw_sp_port->dev, map);
223 for (i = 0; i < ARRAY_SIZE(map->map); ++i) {
225 map->map[i] = fls(map->map[i]) - 1;
227 map->map[i] = default_prio;
232 mlxsw_sp_port_dcb_app_prio_dscp_map(struct mlxsw_sp_port *mlxsw_sp_port,
233 struct dcb_ieee_app_prio_map *map)
235 bool have_dscp = false;
238 dcb_ieee_getapp_prio_dscp_mask_map(mlxsw_sp_port->dev, map);
239 for (i = 0; i < ARRAY_SIZE(map->map); ++i) {
241 map->map[i] = fls64(map->map[i]) - 1;
250 mlxsw_sp_port_dcb_app_update_qpts(struct mlxsw_sp_port *mlxsw_sp_port,
251 enum mlxsw_reg_qpts_trust_state ts)
253 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
254 char qpts_pl[MLXSW_REG_QPTS_LEN];
256 mlxsw_reg_qpts_pack(qpts_pl, mlxsw_sp_port->local_port, ts);
257 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qpts), qpts_pl);
261 mlxsw_sp_port_dcb_app_update_qrwe(struct mlxsw_sp_port *mlxsw_sp_port,
264 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
265 char qrwe_pl[MLXSW_REG_QRWE_LEN];
267 mlxsw_reg_qrwe_pack(qrwe_pl, mlxsw_sp_port->local_port,
268 false, rewrite_dscp);
269 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qrwe), qrwe_pl);
273 mlxsw_sp_port_dcb_toggle_trust(struct mlxsw_sp_port *mlxsw_sp_port,
274 enum mlxsw_reg_qpts_trust_state ts)
276 bool rewrite_dscp = ts == MLXSW_REG_QPTS_TRUST_STATE_DSCP;
279 if (mlxsw_sp_port->dcb.trust_state == ts)
282 err = mlxsw_sp_port_dcb_app_update_qpts(mlxsw_sp_port, ts);
286 err = mlxsw_sp_port_dcb_app_update_qrwe(mlxsw_sp_port, rewrite_dscp);
288 goto err_update_qrwe;
290 mlxsw_sp_port->dcb.trust_state = ts;
294 mlxsw_sp_port_dcb_app_update_qpts(mlxsw_sp_port,
295 mlxsw_sp_port->dcb.trust_state);
300 mlxsw_sp_port_dcb_app_update_qpdp(struct mlxsw_sp_port *mlxsw_sp_port,
303 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
304 char qpdp_pl[MLXSW_REG_QPDP_LEN];
306 mlxsw_reg_qpdp_pack(qpdp_pl, mlxsw_sp_port->local_port, default_prio);
307 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qpdp), qpdp_pl);
311 mlxsw_sp_port_dcb_app_update_qpdpm(struct mlxsw_sp_port *mlxsw_sp_port,
312 struct dcb_ieee_app_dscp_map *map)
314 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
315 char qpdpm_pl[MLXSW_REG_QPDPM_LEN];
318 mlxsw_reg_qpdpm_pack(qpdpm_pl, mlxsw_sp_port->local_port);
319 for (i = 0; i < ARRAY_SIZE(map->map); ++i)
320 mlxsw_reg_qpdpm_dscp_pack(qpdpm_pl, i, map->map[i]);
321 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qpdpm), qpdpm_pl);
325 mlxsw_sp_port_dcb_app_update_qpdsm(struct mlxsw_sp_port *mlxsw_sp_port,
326 struct dcb_ieee_app_prio_map *map)
328 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
329 char qpdsm_pl[MLXSW_REG_QPDSM_LEN];
332 mlxsw_reg_qpdsm_pack(qpdsm_pl, mlxsw_sp_port->local_port);
333 for (i = 0; i < ARRAY_SIZE(map->map); ++i)
334 mlxsw_reg_qpdsm_prio_pack(qpdsm_pl, i, map->map[i]);
335 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qpdsm), qpdsm_pl);
338 static int mlxsw_sp_port_dcb_app_update(struct mlxsw_sp_port *mlxsw_sp_port)
340 struct dcb_ieee_app_prio_map prio_map;
341 struct dcb_ieee_app_dscp_map dscp_map;
346 default_prio = mlxsw_sp_port_dcb_app_default_prio(mlxsw_sp_port);
347 err = mlxsw_sp_port_dcb_app_update_qpdp(mlxsw_sp_port, default_prio);
349 netdev_err(mlxsw_sp_port->dev, "Couldn't configure port default priority\n");
353 have_dscp = mlxsw_sp_port_dcb_app_prio_dscp_map(mlxsw_sp_port,
356 mlxsw_sp_port_dcb_app_dscp_prio_map(mlxsw_sp_port, default_prio,
358 err = mlxsw_sp_port_dcb_app_update_qpdpm(mlxsw_sp_port,
361 netdev_err(mlxsw_sp_port->dev, "Couldn't configure priority map\n");
365 err = mlxsw_sp_port_dcb_app_update_qpdsm(mlxsw_sp_port,
368 netdev_err(mlxsw_sp_port->dev, "Couldn't configure DSCP rewrite map\n");
373 err = mlxsw_sp_port_dcb_toggle_trust(mlxsw_sp_port,
374 MLXSW_REG_QPTS_TRUST_STATE_PCP);
376 netdev_err(mlxsw_sp_port->dev, "Couldn't switch to trust L2\n");
380 err = mlxsw_sp_port_dcb_toggle_trust(mlxsw_sp_port,
381 MLXSW_REG_QPTS_TRUST_STATE_DSCP);
383 /* A failure to set trust DSCP means that the QPDPM and QPDSM
384 * maps installed above are not in effect. And since we are here
385 * attempting to set trust DSCP, we couldn't have attempted to
386 * switch trust to PCP. Thus no cleanup is necessary.
388 netdev_err(mlxsw_sp_port->dev, "Couldn't switch to trust L3\n");
395 static int mlxsw_sp_dcbnl_ieee_setapp(struct net_device *dev,
398 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
401 err = mlxsw_sp_dcbnl_app_validate(dev, app);
405 err = dcb_ieee_setapp(dev, app);
409 err = mlxsw_sp_port_dcb_app_update(mlxsw_sp_port);
416 dcb_ieee_delapp(dev, app);
420 static int mlxsw_sp_dcbnl_ieee_delapp(struct net_device *dev,
423 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
426 err = dcb_ieee_delapp(dev, app);
430 err = mlxsw_sp_port_dcb_app_update(mlxsw_sp_port);
432 netdev_err(dev, "Failed to update DCB APP configuration\n");
436 static int mlxsw_sp_dcbnl_ieee_getmaxrate(struct net_device *dev,
437 struct ieee_maxrate *maxrate)
439 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
441 memcpy(maxrate, mlxsw_sp_port->dcb.maxrate, sizeof(*maxrate));
446 static int mlxsw_sp_dcbnl_ieee_setmaxrate(struct net_device *dev,
447 struct ieee_maxrate *maxrate)
449 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
450 struct ieee_maxrate *my_maxrate = mlxsw_sp_port->dcb.maxrate;
453 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
454 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
455 MLXSW_REG_QEEC_HR_SUBGROUP,
457 maxrate->tc_maxrate[i], 0);
459 netdev_err(dev, "Failed to set maxrate for TC %d\n", i);
460 goto err_port_ets_maxrate_set;
464 memcpy(mlxsw_sp_port->dcb.maxrate, maxrate, sizeof(*maxrate));
468 err_port_ets_maxrate_set:
469 for (i--; i >= 0; i--)
470 mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
471 MLXSW_REG_QEEC_HR_SUBGROUP,
473 my_maxrate->tc_maxrate[i], 0);
477 static int mlxsw_sp_port_pfc_cnt_get(struct mlxsw_sp_port *mlxsw_sp_port,
480 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
481 struct ieee_pfc *my_pfc = mlxsw_sp_port->dcb.pfc;
482 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
485 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port,
486 MLXSW_REG_PPCNT_PRIO_CNT, prio);
487 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
491 my_pfc->requests[prio] = mlxsw_reg_ppcnt_tx_pause_get(ppcnt_pl);
492 my_pfc->indications[prio] = mlxsw_reg_ppcnt_rx_pause_get(ppcnt_pl);
497 static int mlxsw_sp_dcbnl_ieee_getpfc(struct net_device *dev,
498 struct ieee_pfc *pfc)
500 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
503 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
504 err = mlxsw_sp_port_pfc_cnt_get(mlxsw_sp_port, i);
506 netdev_err(dev, "Failed to get PFC count for priority %d\n",
512 memcpy(pfc, mlxsw_sp_port->dcb.pfc, sizeof(*pfc));
517 static int mlxsw_sp_port_pfc_set(struct mlxsw_sp_port *mlxsw_sp_port,
518 struct ieee_pfc *pfc)
520 char pfcc_pl[MLXSW_REG_PFCC_LEN];
522 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
523 mlxsw_reg_pfcc_pprx_set(pfcc_pl, mlxsw_sp_port->link.rx_pause);
524 mlxsw_reg_pfcc_pptx_set(pfcc_pl, mlxsw_sp_port->link.tx_pause);
525 mlxsw_reg_pfcc_prio_pack(pfcc_pl, pfc->pfc_en);
527 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
531 static int mlxsw_sp_dcbnl_ieee_setpfc(struct net_device *dev,
532 struct ieee_pfc *pfc)
534 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
535 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
536 struct mlxsw_sp_hdroom orig_hdroom;
537 struct mlxsw_sp_hdroom hdroom;
541 if (pause_en && pfc->pfc_en) {
542 netdev_err(dev, "PAUSE frames already enabled on port\n");
546 orig_hdroom = *mlxsw_sp_port->hdroom;
548 hdroom = orig_hdroom;
550 hdroom.delay_bytes = DIV_ROUND_UP(pfc->delay, BITS_PER_BYTE);
552 hdroom.delay_bytes = 0;
554 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++)
555 hdroom.prios.prio[prio].lossy = !(pfc->pfc_en & BIT(prio));
557 mlxsw_sp_hdroom_bufs_reset_lossiness(&hdroom);
558 mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom);
560 err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom);
562 netdev_err(dev, "Failed to configure port's headroom for PFC\n");
566 err = mlxsw_sp_port_pfc_set(mlxsw_sp_port, pfc);
568 netdev_err(dev, "Failed to configure PFC\n");
569 goto err_port_pfc_set;
572 memcpy(mlxsw_sp_port->dcb.pfc, pfc, sizeof(*pfc));
573 mlxsw_sp_port->dcb.pfc->pfc_cap = IEEE_8021QAZ_MAX_TCS;
578 mlxsw_sp_hdroom_configure(mlxsw_sp_port, &orig_hdroom);
582 static int mlxsw_sp_dcbnl_getbuffer(struct net_device *dev, struct dcbnl_buffer *buf)
584 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
585 struct mlxsw_sp_hdroom *hdroom = mlxsw_sp_port->hdroom;
586 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
592 BUILD_BUG_ON(DCBX_MAX_BUFFERS > MLXSW_SP_PB_COUNT);
593 for (i = 0; i < MLXSW_SP_PB_COUNT; i++) {
594 u32 bytes = mlxsw_sp_cells_bytes(mlxsw_sp, hdroom->bufs.buf[i].size_cells);
596 if (i < DCBX_MAX_BUFFERS)
597 buf->buffer_size[i] = bytes;
598 buf->total_size += bytes;
601 buf->total_size += mlxsw_sp_cells_bytes(mlxsw_sp, hdroom->int_buf.size_cells);
603 for (prio = 0; prio < IEEE_8021Q_MAX_PRIORITIES; prio++)
604 buf->prio2buffer[prio] = hdroom->prios.prio[prio].buf_idx;
609 static int mlxsw_sp_dcbnl_setbuffer(struct net_device *dev, struct dcbnl_buffer *buf)
611 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
612 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
613 struct mlxsw_sp_hdroom hdroom;
617 hdroom = *mlxsw_sp_port->hdroom;
619 if (hdroom.mode != MLXSW_SP_HDROOM_MODE_TC) {
620 netdev_err(dev, "The use of dcbnl_setbuffer is only allowed if egress is configured using TC\n");
624 for (prio = 0; prio < IEEE_8021Q_MAX_PRIORITIES; prio++)
625 hdroom.prios.prio[prio].set_buf_idx = buf->prio2buffer[prio];
627 BUILD_BUG_ON(DCBX_MAX_BUFFERS > MLXSW_SP_PB_COUNT);
628 for (i = 0; i < DCBX_MAX_BUFFERS; i++)
629 hdroom.bufs.buf[i].set_size_cells = mlxsw_sp_bytes_cells(mlxsw_sp,
630 buf->buffer_size[i]);
632 mlxsw_sp_hdroom_prios_reset_buf_idx(&hdroom);
633 mlxsw_sp_hdroom_bufs_reset_lossiness(&hdroom);
634 mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom);
635 return mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom);
638 static const struct dcbnl_rtnl_ops mlxsw_sp_dcbnl_ops = {
639 .ieee_getets = mlxsw_sp_dcbnl_ieee_getets,
640 .ieee_setets = mlxsw_sp_dcbnl_ieee_setets,
641 .ieee_getmaxrate = mlxsw_sp_dcbnl_ieee_getmaxrate,
642 .ieee_setmaxrate = mlxsw_sp_dcbnl_ieee_setmaxrate,
643 .ieee_getpfc = mlxsw_sp_dcbnl_ieee_getpfc,
644 .ieee_setpfc = mlxsw_sp_dcbnl_ieee_setpfc,
645 .ieee_setapp = mlxsw_sp_dcbnl_ieee_setapp,
646 .ieee_delapp = mlxsw_sp_dcbnl_ieee_delapp,
648 .getdcbx = mlxsw_sp_dcbnl_getdcbx,
649 .setdcbx = mlxsw_sp_dcbnl_setdcbx,
651 .dcbnl_getbuffer = mlxsw_sp_dcbnl_getbuffer,
652 .dcbnl_setbuffer = mlxsw_sp_dcbnl_setbuffer,
655 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
657 mlxsw_sp_port->dcb.ets = kzalloc(sizeof(*mlxsw_sp_port->dcb.ets),
659 if (!mlxsw_sp_port->dcb.ets)
662 mlxsw_sp_port->dcb.ets->ets_cap = IEEE_8021QAZ_MAX_TCS;
667 static void mlxsw_sp_port_ets_fini(struct mlxsw_sp_port *mlxsw_sp_port)
669 kfree(mlxsw_sp_port->dcb.ets);
672 static int mlxsw_sp_port_maxrate_init(struct mlxsw_sp_port *mlxsw_sp_port)
676 mlxsw_sp_port->dcb.maxrate = kmalloc(sizeof(*mlxsw_sp_port->dcb.maxrate),
678 if (!mlxsw_sp_port->dcb.maxrate)
681 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
682 mlxsw_sp_port->dcb.maxrate->tc_maxrate[i] = MLXSW_REG_QEEC_MAS_DIS;
687 static void mlxsw_sp_port_maxrate_fini(struct mlxsw_sp_port *mlxsw_sp_port)
689 kfree(mlxsw_sp_port->dcb.maxrate);
692 static int mlxsw_sp_port_pfc_init(struct mlxsw_sp_port *mlxsw_sp_port)
694 mlxsw_sp_port->dcb.pfc = kzalloc(sizeof(*mlxsw_sp_port->dcb.pfc),
696 if (!mlxsw_sp_port->dcb.pfc)
699 mlxsw_sp_port->dcb.pfc->pfc_cap = IEEE_8021QAZ_MAX_TCS;
704 static void mlxsw_sp_port_pfc_fini(struct mlxsw_sp_port *mlxsw_sp_port)
706 kfree(mlxsw_sp_port->dcb.pfc);
709 int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port)
713 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
716 err = mlxsw_sp_port_maxrate_init(mlxsw_sp_port);
718 goto err_port_maxrate_init;
719 err = mlxsw_sp_port_pfc_init(mlxsw_sp_port);
721 goto err_port_pfc_init;
723 mlxsw_sp_port->dcb.trust_state = MLXSW_REG_QPTS_TRUST_STATE_PCP;
724 mlxsw_sp_port->dev->dcbnl_ops = &mlxsw_sp_dcbnl_ops;
729 mlxsw_sp_port_maxrate_fini(mlxsw_sp_port);
730 err_port_maxrate_init:
731 mlxsw_sp_port_ets_fini(mlxsw_sp_port);
735 void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port)
737 mlxsw_sp_port_pfc_fini(mlxsw_sp_port);
738 mlxsw_sp_port_maxrate_fini(mlxsw_sp_port);
739 mlxsw_sp_port_ets_fini(mlxsw_sp_port);