2 * drivers/net/ethernet/mellanox/mlxsw/cmd.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the names of the copyright holders nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
41 #define MLXSW_CMD_MBOX_SIZE 4096
43 static inline char *mlxsw_cmd_mbox_alloc(void)
45 return kzalloc(MLXSW_CMD_MBOX_SIZE, GFP_KERNEL);
48 static inline void mlxsw_cmd_mbox_free(char *mbox)
53 static inline void mlxsw_cmd_mbox_zero(char *mbox)
55 memset(mbox, 0, MLXSW_CMD_MBOX_SIZE);
60 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod,
61 u32 in_mod, bool out_mbox_direct,
62 char *in_mbox, size_t in_mbox_size,
63 char *out_mbox, size_t out_mbox_size);
65 static inline int mlxsw_cmd_exec_in(struct mlxsw_core *mlxsw_core, u16 opcode,
66 u8 opcode_mod, u32 in_mod, char *in_mbox,
69 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false,
70 in_mbox, in_mbox_size, NULL, 0);
73 static inline int mlxsw_cmd_exec_out(struct mlxsw_core *mlxsw_core, u16 opcode,
74 u8 opcode_mod, u32 in_mod,
76 char *out_mbox, size_t out_mbox_size)
78 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod,
79 out_mbox_direct, NULL, 0,
80 out_mbox, out_mbox_size);
83 static inline int mlxsw_cmd_exec_none(struct mlxsw_core *mlxsw_core, u16 opcode,
84 u8 opcode_mod, u32 in_mod)
86 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false,
90 enum mlxsw_cmd_opcode {
91 MLXSW_CMD_OPCODE_QUERY_FW = 0x004,
92 MLXSW_CMD_OPCODE_QUERY_BOARDINFO = 0x006,
93 MLXSW_CMD_OPCODE_QUERY_AQ_CAP = 0x003,
94 MLXSW_CMD_OPCODE_MAP_FA = 0xFFF,
95 MLXSW_CMD_OPCODE_UNMAP_FA = 0xFFE,
96 MLXSW_CMD_OPCODE_CONFIG_PROFILE = 0x100,
97 MLXSW_CMD_OPCODE_ACCESS_REG = 0x040,
98 MLXSW_CMD_OPCODE_SW2HW_DQ = 0x201,
99 MLXSW_CMD_OPCODE_HW2SW_DQ = 0x202,
100 MLXSW_CMD_OPCODE_2ERR_DQ = 0x01E,
101 MLXSW_CMD_OPCODE_QUERY_DQ = 0x022,
102 MLXSW_CMD_OPCODE_SW2HW_CQ = 0x016,
103 MLXSW_CMD_OPCODE_HW2SW_CQ = 0x017,
104 MLXSW_CMD_OPCODE_QUERY_CQ = 0x018,
105 MLXSW_CMD_OPCODE_SW2HW_EQ = 0x013,
106 MLXSW_CMD_OPCODE_HW2SW_EQ = 0x014,
107 MLXSW_CMD_OPCODE_QUERY_EQ = 0x015,
108 MLXSW_CMD_OPCODE_QUERY_RESOURCES = 0x101,
111 static inline const char *mlxsw_cmd_opcode_str(u16 opcode)
114 case MLXSW_CMD_OPCODE_QUERY_FW:
116 case MLXSW_CMD_OPCODE_QUERY_BOARDINFO:
117 return "QUERY_BOARDINFO";
118 case MLXSW_CMD_OPCODE_QUERY_AQ_CAP:
119 return "QUERY_AQ_CAP";
120 case MLXSW_CMD_OPCODE_MAP_FA:
122 case MLXSW_CMD_OPCODE_UNMAP_FA:
124 case MLXSW_CMD_OPCODE_CONFIG_PROFILE:
125 return "CONFIG_PROFILE";
126 case MLXSW_CMD_OPCODE_ACCESS_REG:
128 case MLXSW_CMD_OPCODE_SW2HW_DQ:
130 case MLXSW_CMD_OPCODE_HW2SW_DQ:
132 case MLXSW_CMD_OPCODE_2ERR_DQ:
134 case MLXSW_CMD_OPCODE_QUERY_DQ:
136 case MLXSW_CMD_OPCODE_SW2HW_CQ:
138 case MLXSW_CMD_OPCODE_HW2SW_CQ:
140 case MLXSW_CMD_OPCODE_QUERY_CQ:
142 case MLXSW_CMD_OPCODE_SW2HW_EQ:
144 case MLXSW_CMD_OPCODE_HW2SW_EQ:
146 case MLXSW_CMD_OPCODE_QUERY_EQ:
148 case MLXSW_CMD_OPCODE_QUERY_RESOURCES:
149 return "QUERY_RESOURCES";
155 enum mlxsw_cmd_status {
156 /* Command execution succeeded. */
157 MLXSW_CMD_STATUS_OK = 0x00,
158 /* Internal error (e.g. bus error) occurred while processing command. */
159 MLXSW_CMD_STATUS_INTERNAL_ERR = 0x01,
160 /* Operation/command not supported or opcode modifier not supported. */
161 MLXSW_CMD_STATUS_BAD_OP = 0x02,
162 /* Parameter not supported, parameter out of range. */
163 MLXSW_CMD_STATUS_BAD_PARAM = 0x03,
164 /* System was not enabled or bad system state. */
165 MLXSW_CMD_STATUS_BAD_SYS_STATE = 0x04,
166 /* Attempt to access reserved or unallocated resource, or resource in
167 * inappropriate ownership.
169 MLXSW_CMD_STATUS_BAD_RESOURCE = 0x05,
170 /* Requested resource is currently executing a command. */
171 MLXSW_CMD_STATUS_RESOURCE_BUSY = 0x06,
172 /* Required capability exceeds device limits. */
173 MLXSW_CMD_STATUS_EXCEED_LIM = 0x08,
174 /* Resource is not in the appropriate state or ownership. */
175 MLXSW_CMD_STATUS_BAD_RES_STATE = 0x09,
176 /* Index out of range (might be beyond table size or attempt to
177 * access a reserved resource).
179 MLXSW_CMD_STATUS_BAD_INDEX = 0x0A,
180 /* NVMEM checksum/CRC failed. */
181 MLXSW_CMD_STATUS_BAD_NVMEM = 0x0B,
182 /* Bad management packet (silently discarded). */
183 MLXSW_CMD_STATUS_BAD_PKT = 0x30,
186 static inline const char *mlxsw_cmd_status_str(u8 status)
189 case MLXSW_CMD_STATUS_OK:
191 case MLXSW_CMD_STATUS_INTERNAL_ERR:
192 return "INTERNAL_ERR";
193 case MLXSW_CMD_STATUS_BAD_OP:
195 case MLXSW_CMD_STATUS_BAD_PARAM:
197 case MLXSW_CMD_STATUS_BAD_SYS_STATE:
198 return "BAD_SYS_STATE";
199 case MLXSW_CMD_STATUS_BAD_RESOURCE:
200 return "BAD_RESOURCE";
201 case MLXSW_CMD_STATUS_RESOURCE_BUSY:
202 return "RESOURCE_BUSY";
203 case MLXSW_CMD_STATUS_EXCEED_LIM:
205 case MLXSW_CMD_STATUS_BAD_RES_STATE:
206 return "BAD_RES_STATE";
207 case MLXSW_CMD_STATUS_BAD_INDEX:
209 case MLXSW_CMD_STATUS_BAD_NVMEM:
211 case MLXSW_CMD_STATUS_BAD_PKT:
218 /* QUERY_FW - Query Firmware
219 * -------------------------
220 * OpMod == 0, INMmod == 0
221 * -----------------------
222 * The QUERY_FW command retrieves information related to firmware, command
223 * interface version and the amount of resources that should be allocated to
227 static inline int mlxsw_cmd_query_fw(struct mlxsw_core *mlxsw_core,
230 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_FW,
231 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE);
234 /* cmd_mbox_query_fw_fw_pages
235 * Amount of physical memory to be allocatedfor firmware usage in 4KB pages.
237 MLXSW_ITEM32(cmd_mbox, query_fw, fw_pages, 0x00, 16, 16);
239 /* cmd_mbox_query_fw_fw_rev_major
240 * Firmware Revision - Major
242 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_major, 0x00, 0, 16);
244 /* cmd_mbox_query_fw_fw_rev_subminor
245 * Firmware Sub-minor version (Patch level)
247 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_subminor, 0x04, 16, 16);
249 /* cmd_mbox_query_fw_fw_rev_minor
250 * Firmware Revision - Minor
252 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_minor, 0x04, 0, 16);
254 /* cmd_mbox_query_fw_core_clk
255 * Internal Clock Frequency (in MHz)
257 MLXSW_ITEM32(cmd_mbox, query_fw, core_clk, 0x08, 16, 16);
259 /* cmd_mbox_query_fw_cmd_interface_rev
260 * Command Interface Interpreter Revision ID. This number is bumped up
261 * every time a non-backward-compatible change is done for the command
262 * interface. The current cmd_interface_rev is 1.
264 MLXSW_ITEM32(cmd_mbox, query_fw, cmd_interface_rev, 0x08, 0, 16);
266 /* cmd_mbox_query_fw_dt
267 * If set, Debug Trace is supported
269 MLXSW_ITEM32(cmd_mbox, query_fw, dt, 0x0C, 31, 1);
271 /* cmd_mbox_query_fw_api_version
272 * Indicates the version of the API, to enable software querying
273 * for compatibility. The current api_version is 1.
275 MLXSW_ITEM32(cmd_mbox, query_fw, api_version, 0x0C, 0, 16);
277 /* cmd_mbox_query_fw_fw_hour
278 * Firmware timestamp - hour
280 MLXSW_ITEM32(cmd_mbox, query_fw, fw_hour, 0x10, 24, 8);
282 /* cmd_mbox_query_fw_fw_minutes
283 * Firmware timestamp - minutes
285 MLXSW_ITEM32(cmd_mbox, query_fw, fw_minutes, 0x10, 16, 8);
287 /* cmd_mbox_query_fw_fw_seconds
288 * Firmware timestamp - seconds
290 MLXSW_ITEM32(cmd_mbox, query_fw, fw_seconds, 0x10, 8, 8);
292 /* cmd_mbox_query_fw_fw_year
293 * Firmware timestamp - year
295 MLXSW_ITEM32(cmd_mbox, query_fw, fw_year, 0x14, 16, 16);
297 /* cmd_mbox_query_fw_fw_month
298 * Firmware timestamp - month
300 MLXSW_ITEM32(cmd_mbox, query_fw, fw_month, 0x14, 8, 8);
302 /* cmd_mbox_query_fw_fw_day
303 * Firmware timestamp - day
305 MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8);
307 /* cmd_mbox_query_fw_clr_int_base_offset
308 * Clear Interrupt register's offset from clr_int_bar register
309 * in PCI address space.
311 MLXSW_ITEM64(cmd_mbox, query_fw, clr_int_base_offset, 0x20, 0, 64);
313 /* cmd_mbox_query_fw_clr_int_bar
314 * PCI base address register (BAR) where clr_int register is located.
315 * 00 - BAR 0-1 (64 bit BAR)
317 MLXSW_ITEM32(cmd_mbox, query_fw, clr_int_bar, 0x28, 30, 2);
319 /* cmd_mbox_query_fw_error_buf_offset
320 * Read Only buffer for internal error reports of offset
321 * from error_buf_bar register in PCI address space).
323 MLXSW_ITEM64(cmd_mbox, query_fw, error_buf_offset, 0x30, 0, 64);
325 /* cmd_mbox_query_fw_error_buf_size
326 * Internal error buffer size in DWORDs
328 MLXSW_ITEM32(cmd_mbox, query_fw, error_buf_size, 0x38, 0, 32);
330 /* cmd_mbox_query_fw_error_int_bar
331 * PCI base address register (BAR) where error buffer
332 * register is located.
333 * 00 - BAR 0-1 (64 bit BAR)
335 MLXSW_ITEM32(cmd_mbox, query_fw, error_int_bar, 0x3C, 30, 2);
337 /* cmd_mbox_query_fw_doorbell_page_offset
338 * Offset of the doorbell page
340 MLXSW_ITEM64(cmd_mbox, query_fw, doorbell_page_offset, 0x40, 0, 64);
342 /* cmd_mbox_query_fw_doorbell_page_bar
343 * PCI base address register (BAR) of the doorbell page
344 * 00 - BAR 0-1 (64 bit BAR)
346 MLXSW_ITEM32(cmd_mbox, query_fw, doorbell_page_bar, 0x48, 30, 2);
348 /* QUERY_BOARDINFO - Query Board Information
349 * -----------------------------------------
350 * OpMod == 0 (N/A), INMmod == 0 (N/A)
351 * -----------------------------------
352 * The QUERY_BOARDINFO command retrieves adapter specific parameters.
355 static inline int mlxsw_cmd_boardinfo(struct mlxsw_core *mlxsw_core,
358 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_BOARDINFO,
359 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE);
362 /* cmd_mbox_boardinfo_intapin
363 * When PCIe interrupt messages are being used, this value is used for clearing
364 * an interrupt. When using MSI-X, this register is not used.
366 MLXSW_ITEM32(cmd_mbox, boardinfo, intapin, 0x10, 24, 8);
368 /* cmd_mbox_boardinfo_vsd_vendor_id
369 * PCISIG Vendor ID (www.pcisig.com/membership/vid_search) of the vendor
370 * specifying/formatting the VSD. The vsd_vendor_id identifies the management
371 * domain of the VSD/PSID data. Different vendors may choose different VSD/PSID
372 * format and encoding as long as they use their assigned vsd_vendor_id.
374 MLXSW_ITEM32(cmd_mbox, boardinfo, vsd_vendor_id, 0x1C, 0, 16);
376 /* cmd_mbox_boardinfo_vsd
377 * Vendor Specific Data. The VSD string that is burnt to the Flash
380 #define MLXSW_CMD_BOARDINFO_VSD_LEN 208
381 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, vsd, 0x20, MLXSW_CMD_BOARDINFO_VSD_LEN);
383 /* cmd_mbox_boardinfo_psid
384 * The PSID field is a 16-ascii (byte) character string which acts as
385 * the board ID. The PSID format is used in conjunction with
386 * Mellanox vsd_vendor_id (15B3h).
388 #define MLXSW_CMD_BOARDINFO_PSID_LEN 16
389 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, psid, 0xF0, MLXSW_CMD_BOARDINFO_PSID_LEN);
391 /* QUERY_AQ_CAP - Query Asynchronous Queues Capabilities
392 * -----------------------------------------------------
393 * OpMod == 0 (N/A), INMmod == 0 (N/A)
394 * -----------------------------------
395 * The QUERY_AQ_CAP command returns the device asynchronous queues
396 * capabilities supported.
399 static inline int mlxsw_cmd_query_aq_cap(struct mlxsw_core *mlxsw_core,
402 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_AQ_CAP,
403 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE);
406 /* cmd_mbox_query_aq_cap_log_max_sdq_sz
407 * Log (base 2) of max WQEs allowed on SDQ.
409 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_sdq_sz, 0x00, 24, 8);
411 /* cmd_mbox_query_aq_cap_max_num_sdqs
412 * Maximum number of SDQs.
414 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_sdqs, 0x00, 0, 8);
416 /* cmd_mbox_query_aq_cap_log_max_rdq_sz
417 * Log (base 2) of max WQEs allowed on RDQ.
419 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_rdq_sz, 0x04, 24, 8);
421 /* cmd_mbox_query_aq_cap_max_num_rdqs
422 * Maximum number of RDQs.
424 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_rdqs, 0x04, 0, 8);
426 /* cmd_mbox_query_aq_cap_log_max_cq_sz
427 * Log (base 2) of max CQEs allowed on CQ.
429 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cq_sz, 0x08, 24, 8);
431 /* cmd_mbox_query_aq_cap_max_num_cqs
432 * Maximum number of CQs.
434 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_cqs, 0x08, 0, 8);
436 /* cmd_mbox_query_aq_cap_log_max_eq_sz
437 * Log (base 2) of max EQEs allowed on EQ.
439 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_eq_sz, 0x0C, 24, 8);
441 /* cmd_mbox_query_aq_cap_max_num_eqs
442 * Maximum number of EQs.
444 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_eqs, 0x0C, 0, 8);
446 /* cmd_mbox_query_aq_cap_max_sg_sq
447 * The maximum S/G list elements in an DSQ. DSQ must not contain
448 * more S/G entries than indicated here.
450 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_sq, 0x10, 8, 8);
452 /* cmd_mbox_query_aq_cap_
453 * The maximum S/G list elements in an DRQ. DRQ must not contain
454 * more S/G entries than indicated here.
456 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_rq, 0x10, 0, 8);
458 /* MAP_FA - Map Firmware Area
459 * --------------------------
460 * OpMod == 0 (N/A), INMmod == Number of VPM entries
461 * -------------------------------------------------
462 * The MAP_FA command passes physical pages to the switch. These pages
463 * are used to store the device firmware. MAP_FA can be executed multiple
464 * times until all the firmware area is mapped (the size that should be
465 * mapped is retrieved through the QUERY_FW command). All required pages
466 * must be mapped to finish the initialization phase. Physical memory
467 * passed in this command must be pinned.
470 #define MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX 32
472 static inline int mlxsw_cmd_map_fa(struct mlxsw_core *mlxsw_core,
473 char *in_mbox, u32 vpm_entries_count)
475 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_MAP_FA,
476 0, vpm_entries_count,
477 in_mbox, MLXSW_CMD_MBOX_SIZE);
480 /* cmd_mbox_map_fa_pa
483 MLXSW_ITEM64_INDEXED(cmd_mbox, map_fa, pa, 0x00, 12, 52, 0x08, 0x00, true);
485 /* cmd_mbox_map_fa_log2size
486 * Log (base 2) of the size in 4KB pages of the physical and contiguous memory
487 * that starts at PA_L/H.
489 MLXSW_ITEM32_INDEXED(cmd_mbox, map_fa, log2size, 0x00, 0, 5, 0x08, 0x04, false);
491 /* UNMAP_FA - Unmap Firmware Area
492 * ------------------------------
493 * OpMod == 0 (N/A), INMmod == 0 (N/A)
494 * -----------------------------------
495 * The UNMAP_FA command unload the firmware and unmaps all the
496 * firmware area. After this command is completed the device will not access
497 * the pages that were mapped to the firmware area. After executing UNMAP_FA
498 * command, software reset must be done prior to execution of MAP_FW command.
501 static inline int mlxsw_cmd_unmap_fa(struct mlxsw_core *mlxsw_core)
503 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_UNMAP_FA, 0, 0);
506 /* QUERY_RESOURCES - Query chip resources
507 * --------------------------------------
508 * OpMod == 0 (N/A) , INMmod is index
509 * ----------------------------------
510 * The QUERY_RESOURCES command retrieves information related to chip resources
511 * by resource ID. Every command returns 32 entries. INmod is being use as base.
512 * for example, index 1 will return entries 32-63. When the tables end and there
513 * are no more sources in the table, will return resource id 0xFFF to indicate
516 static inline int mlxsw_cmd_query_resources(struct mlxsw_core *mlxsw_core,
517 char *out_mbox, int index)
519 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_RESOURCES,
520 0, index, false, out_mbox,
521 MLXSW_CMD_MBOX_SIZE);
524 /* cmd_mbox_query_resource_id
525 * The resource id. 0xFFFF indicates table's end.
527 MLXSW_ITEM32_INDEXED(cmd_mbox, query_resource, id, 0x00, 16, 16, 0x8, 0, false);
529 /* cmd_mbox_query_resource_data
532 MLXSW_ITEM64_INDEXED(cmd_mbox, query_resource, data,
533 0x00, 0, 40, 0x8, 0, false);
535 /* CONFIG_PROFILE (Set) - Configure Switch Profile
536 * ------------------------------
537 * OpMod == 1 (Set), INMmod == 0 (N/A)
538 * -----------------------------------
539 * The CONFIG_PROFILE command sets the switch profile. The command can be
540 * executed on the device only once at startup in order to allocate and
541 * configure all switch resources and prepare it for operational mode.
542 * It is not possible to change the device profile after the chip is
543 * in operational mode.
544 * Failure of the CONFIG_PROFILE command leaves the hardware in an indeterminate
545 * state therefore it is required to perform software reset to the device
546 * following an unsuccessful completion of the command. It is required
547 * to perform software reset to the device to change an existing profile.
550 static inline int mlxsw_cmd_config_profile_set(struct mlxsw_core *mlxsw_core,
553 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_CONFIG_PROFILE,
554 1, 0, in_mbox, MLXSW_CMD_MBOX_SIZE);
557 /* cmd_mbox_config_profile_set_max_vepa_channels
558 * Capability bit. Setting a bit to 1 configures the profile
559 * according to the mailbox contents.
561 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vepa_channels, 0x0C, 0, 1);
563 /* cmd_mbox_config_profile_set_max_lag
564 * Capability bit. Setting a bit to 1 configures the profile
565 * according to the mailbox contents.
567 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_lag, 0x0C, 1, 1);
569 /* cmd_mbox_config_profile_set_max_port_per_lag
570 * Capability bit. Setting a bit to 1 configures the profile
571 * according to the mailbox contents.
573 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_port_per_lag, 0x0C, 2, 1);
575 /* cmd_mbox_config_profile_set_max_mid
576 * Capability bit. Setting a bit to 1 configures the profile
577 * according to the mailbox contents.
579 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_mid, 0x0C, 3, 1);
581 /* cmd_mbox_config_profile_set_max_pgt
582 * Capability bit. Setting a bit to 1 configures the profile
583 * according to the mailbox contents.
585 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pgt, 0x0C, 4, 1);
587 /* cmd_mbox_config_profile_set_max_system_port
588 * Capability bit. Setting a bit to 1 configures the profile
589 * according to the mailbox contents.
591 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_system_port, 0x0C, 5, 1);
593 /* cmd_mbox_config_profile_set_max_vlan_groups
594 * Capability bit. Setting a bit to 1 configures the profile
595 * according to the mailbox contents.
597 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vlan_groups, 0x0C, 6, 1);
599 /* cmd_mbox_config_profile_set_max_regions
600 * Capability bit. Setting a bit to 1 configures the profile
601 * according to the mailbox contents.
603 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_regions, 0x0C, 7, 1);
605 /* cmd_mbox_config_profile_set_flood_mode
606 * Capability bit. Setting a bit to 1 configures the profile
607 * according to the mailbox contents.
609 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_mode, 0x0C, 8, 1);
611 /* cmd_mbox_config_profile_set_max_flood_tables
612 * Capability bit. Setting a bit to 1 configures the profile
613 * according to the mailbox contents.
615 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_tables, 0x0C, 9, 1);
617 /* cmd_mbox_config_profile_set_max_ib_mc
618 * Capability bit. Setting a bit to 1 configures the profile
619 * according to the mailbox contents.
621 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_ib_mc, 0x0C, 12, 1);
623 /* cmd_mbox_config_profile_set_max_pkey
624 * Capability bit. Setting a bit to 1 configures the profile
625 * according to the mailbox contents.
627 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pkey, 0x0C, 13, 1);
629 /* cmd_mbox_config_profile_set_adaptive_routing_group_cap
630 * Capability bit. Setting a bit to 1 configures the profile
631 * according to the mailbox contents.
633 MLXSW_ITEM32(cmd_mbox, config_profile,
634 set_adaptive_routing_group_cap, 0x0C, 14, 1);
636 /* cmd_mbox_config_profile_set_ar_sec
637 * Capability bit. Setting a bit to 1 configures the profile
638 * according to the mailbox contents.
640 MLXSW_ITEM32(cmd_mbox, config_profile, set_ar_sec, 0x0C, 15, 1);
642 /* cmd_mbox_config_set_kvd_linear_size
643 * Capability bit. Setting a bit to 1 configures the profile
644 * according to the mailbox contents.
646 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_linear_size, 0x0C, 24, 1);
648 /* cmd_mbox_config_set_kvd_hash_single_size
649 * Capability bit. Setting a bit to 1 configures the profile
650 * according to the mailbox contents.
652 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_single_size, 0x0C, 25, 1);
654 /* cmd_mbox_config_set_kvd_hash_double_size
655 * Capability bit. Setting a bit to 1 configures the profile
656 * according to the mailbox contents.
658 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_double_size, 0x0C, 26, 1);
660 /* cmd_mbox_config_profile_max_vepa_channels
661 * Maximum number of VEPA channels per port (0 through 16)
662 * 0 - multi-channel VEPA is disabled
664 MLXSW_ITEM32(cmd_mbox, config_profile, max_vepa_channels, 0x10, 0, 8);
666 /* cmd_mbox_config_profile_max_lag
667 * Maximum number of LAG IDs requested.
669 MLXSW_ITEM32(cmd_mbox, config_profile, max_lag, 0x14, 0, 16);
671 /* cmd_mbox_config_profile_max_port_per_lag
672 * Maximum number of ports per LAG requested.
674 MLXSW_ITEM32(cmd_mbox, config_profile, max_port_per_lag, 0x18, 0, 16);
676 /* cmd_mbox_config_profile_max_mid
677 * Maximum Multicast IDs.
678 * Multicast IDs are allocated from 0 to max_mid-1
680 MLXSW_ITEM32(cmd_mbox, config_profile, max_mid, 0x1C, 0, 16);
682 /* cmd_mbox_config_profile_max_pgt
683 * Maximum records in the Port Group Table per Switch Partition.
684 * Port Group Table indexes are from 0 to max_pgt-1
686 MLXSW_ITEM32(cmd_mbox, config_profile, max_pgt, 0x20, 0, 16);
688 /* cmd_mbox_config_profile_max_system_port
689 * The maximum number of system ports that can be allocated.
691 MLXSW_ITEM32(cmd_mbox, config_profile, max_system_port, 0x24, 0, 16);
693 /* cmd_mbox_config_profile_max_vlan_groups
694 * Maximum number VLAN Groups for VLAN binding.
696 MLXSW_ITEM32(cmd_mbox, config_profile, max_vlan_groups, 0x28, 0, 12);
698 /* cmd_mbox_config_profile_max_regions
699 * Maximum number of TCAM Regions.
701 MLXSW_ITEM32(cmd_mbox, config_profile, max_regions, 0x2C, 0, 16);
703 /* cmd_mbox_config_profile_max_flood_tables
704 * Maximum number of single-entry flooding tables. Different flooding tables
705 * can be associated with different packet types.
707 MLXSW_ITEM32(cmd_mbox, config_profile, max_flood_tables, 0x30, 16, 4);
709 /* cmd_mbox_config_profile_max_vid_flood_tables
710 * Maximum number of per-vid flooding tables. Flooding tables are associated
711 * to the different packet types for the different switch partitions.
712 * Table size is 4K entries covering all VID space.
714 MLXSW_ITEM32(cmd_mbox, config_profile, max_vid_flood_tables, 0x30, 8, 4);
716 /* cmd_mbox_config_profile_flood_mode
717 * Flooding mode to use.
718 * 0-2 - Backward compatible modes for SwitchX devices.
719 * 3 - Mixed mode, where:
720 * max_flood_tables indicates the number of single-entry tables.
721 * max_vid_flood_tables indicates the number of per-VID tables.
722 * max_fid_offset_flood_tables indicates the number of FID-offset tables.
723 * max_fid_flood_tables indicates the number of per-FID tables.
725 MLXSW_ITEM32(cmd_mbox, config_profile, flood_mode, 0x30, 0, 2);
727 /* cmd_mbox_config_profile_max_fid_offset_flood_tables
728 * Maximum number of FID-offset flooding tables.
730 MLXSW_ITEM32(cmd_mbox, config_profile,
731 max_fid_offset_flood_tables, 0x34, 24, 4);
733 /* cmd_mbox_config_profile_fid_offset_flood_table_size
734 * The size (number of entries) of each FID-offset flood table.
736 MLXSW_ITEM32(cmd_mbox, config_profile,
737 fid_offset_flood_table_size, 0x34, 0, 16);
739 /* cmd_mbox_config_profile_max_fid_flood_tables
740 * Maximum number of per-FID flooding tables.
742 * Note: This flooding tables cover special FIDs only (vFIDs), starting at
743 * FID value 4K and higher.
745 MLXSW_ITEM32(cmd_mbox, config_profile, max_fid_flood_tables, 0x38, 24, 4);
747 /* cmd_mbox_config_profile_fid_flood_table_size
748 * The size (number of entries) of each per-FID table.
750 MLXSW_ITEM32(cmd_mbox, config_profile, fid_flood_table_size, 0x38, 0, 16);
752 /* cmd_mbox_config_profile_max_ib_mc
753 * Maximum number of multicast FDB records for InfiniBand
754 * FDB (in 512 chunks) per InfiniBand switch partition.
756 MLXSW_ITEM32(cmd_mbox, config_profile, max_ib_mc, 0x40, 0, 15);
758 /* cmd_mbox_config_profile_max_pkey
759 * Maximum per port PKEY table size (for PKEY enforcement)
761 MLXSW_ITEM32(cmd_mbox, config_profile, max_pkey, 0x44, 0, 15);
763 /* cmd_mbox_config_profile_ar_sec
764 * Primary/secondary capability
765 * Describes the number of adaptive routing sub-groups
766 * 0 - disable primary/secondary (single group)
767 * 1 - enable primary/secondary (2 sub-groups)
768 * 2 - 3 sub-groups: Not supported in SwitchX, SwitchX-2
769 * 3 - 4 sub-groups: Not supported in SwitchX, SwitchX-2
771 MLXSW_ITEM32(cmd_mbox, config_profile, ar_sec, 0x4C, 24, 2);
773 /* cmd_mbox_config_profile_adaptive_routing_group_cap
774 * Adaptive Routing Group Capability. Indicates the number of AR groups
775 * supported. Note that when Primary/secondary is enabled, each
776 * primary/secondary couple consumes 2 adaptive routing entries.
778 MLXSW_ITEM32(cmd_mbox, config_profile, adaptive_routing_group_cap, 0x4C, 0, 16);
780 /* cmd_mbox_config_profile_arn
781 * Adaptive Routing Notification Enable
782 * Not supported in SwitchX, SwitchX-2
784 MLXSW_ITEM32(cmd_mbox, config_profile, arn, 0x50, 31, 1);
786 /* cmd_mbox_config_kvd_linear_size
788 * Valid for Spectrum only
789 * Allowed values are 128*N where N=0 or higher
791 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_linear_size, 0x54, 0, 24);
793 /* cmd_mbox_config_kvd_hash_single_size
794 * KVD Hash single-entries size
795 * Valid for Spectrum only
796 * Allowed values are 128*N where N=0 or higher
797 * Must be greater or equal to cap_min_kvd_hash_single_size
798 * Must be smaller or equal to cap_kvd_size - kvd_linear_size
800 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_single_size, 0x58, 0, 24);
802 /* cmd_mbox_config_kvd_hash_double_size
803 * KVD Hash double-entries size (units of single-size entries)
804 * Valid for Spectrum only
805 * Allowed values are 128*N where N=0 or higher
806 * Must be either 0 or greater or equal to cap_min_kvd_hash_double_size
807 * Must be smaller or equal to cap_kvd_size - kvd_linear_size
809 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_double_size, 0x5C, 0, 24);
811 /* cmd_mbox_config_profile_swid_config_mask
812 * Modify Switch Partition Configuration mask. When set, the configu-
813 * ration value for the Switch Partition are taken from the mailbox.
814 * When clear, the current configuration values are used.
819 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_mask,
820 0x60, 24, 8, 0x08, 0x00, false);
822 /* cmd_mbox_config_profile_swid_config_type
823 * Switch Partition type.
824 * 0000 - disabled (Switch Partition does not exist)
827 * 1000 - router port (SwitchX-2 only)
830 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_type,
831 0x60, 20, 4, 0x08, 0x00, false);
833 /* cmd_mbox_config_profile_swid_config_properties
834 * Switch Partition properties.
836 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_properties,
837 0x60, 0, 8, 0x08, 0x00, false);
839 /* ACCESS_REG - Access EMAD Supported Register
840 * ----------------------------------
841 * OpMod == 0 (N/A), INMmod == 0 (N/A)
842 * -------------------------------------
843 * The ACCESS_REG command supports accessing device registers. This access
844 * is mainly used for bootstrapping.
847 static inline int mlxsw_cmd_access_reg(struct mlxsw_core *mlxsw_core,
848 char *in_mbox, char *out_mbox)
850 return mlxsw_cmd_exec(mlxsw_core, MLXSW_CMD_OPCODE_ACCESS_REG,
851 0, 0, false, in_mbox, MLXSW_CMD_MBOX_SIZE,
852 out_mbox, MLXSW_CMD_MBOX_SIZE);
855 /* SW2HW_DQ - Software to Hardware DQ
856 * ----------------------------------
857 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ)
858 * INMmod == DQ number
859 * ----------------------------------------------
860 * The SW2HW_DQ command transitions a descriptor queue from software to
861 * hardware ownership. The command enables posting WQEs and ringing DoorBells
862 * on the descriptor queue.
865 static inline int __mlxsw_cmd_sw2hw_dq(struct mlxsw_core *mlxsw_core,
866 char *in_mbox, u32 dq_number,
869 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_DQ,
870 opcode_mod, dq_number,
871 in_mbox, MLXSW_CMD_MBOX_SIZE);
875 MLXSW_CMD_OPCODE_MOD_SDQ = 0,
876 MLXSW_CMD_OPCODE_MOD_RDQ = 1,
879 static inline int mlxsw_cmd_sw2hw_sdq(struct mlxsw_core *mlxsw_core,
880 char *in_mbox, u32 dq_number)
882 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number,
883 MLXSW_CMD_OPCODE_MOD_SDQ);
886 static inline int mlxsw_cmd_sw2hw_rdq(struct mlxsw_core *mlxsw_core,
887 char *in_mbox, u32 dq_number)
889 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number,
890 MLXSW_CMD_OPCODE_MOD_RDQ);
893 /* cmd_mbox_sw2hw_dq_cq
894 * Number of the CQ that this Descriptor Queue reports completions to.
896 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, cq, 0x00, 24, 8);
898 /* cmd_mbox_sw2hw_dq_sdq_tclass
899 * SDQ: CPU Egress TClass
902 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, sdq_tclass, 0x00, 16, 6);
904 /* cmd_mbox_sw2hw_dq_log2_dq_sz
905 * Log (base 2) of the Descriptor Queue size in 4KB pages.
907 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, log2_dq_sz, 0x00, 0, 6);
909 /* cmd_mbox_sw2hw_dq_pa
912 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_dq, pa, 0x10, 12, 52, 0x08, 0x00, true);
914 /* HW2SW_DQ - Hardware to Software DQ
915 * ----------------------------------
916 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ)
917 * INMmod == DQ number
918 * ----------------------------------------------
919 * The HW2SW_DQ command transitions a descriptor queue from hardware to
920 * software ownership. Incoming packets on the DQ are silently discarded,
921 * SW should not post descriptors on nonoperational DQs.
924 static inline int __mlxsw_cmd_hw2sw_dq(struct mlxsw_core *mlxsw_core,
925 u32 dq_number, u8 opcode_mod)
927 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_DQ,
928 opcode_mod, dq_number);
931 static inline int mlxsw_cmd_hw2sw_sdq(struct mlxsw_core *mlxsw_core,
934 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number,
935 MLXSW_CMD_OPCODE_MOD_SDQ);
938 static inline int mlxsw_cmd_hw2sw_rdq(struct mlxsw_core *mlxsw_core,
941 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number,
942 MLXSW_CMD_OPCODE_MOD_RDQ);
945 /* 2ERR_DQ - To Error DQ
946 * ---------------------
947 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ)
948 * INMmod == DQ number
949 * ----------------------------------------------
950 * The 2ERR_DQ command transitions the DQ into the error state from the state
951 * in which it has been. While the command is executed, some in-process
952 * descriptors may complete. Once the DQ transitions into the error state,
953 * if there are posted descriptors on the RDQ/SDQ, the hardware writes
954 * a completion with error (flushed) for all descriptors posted in the RDQ/SDQ.
955 * When the command is completed successfully, the DQ is already in
959 static inline int __mlxsw_cmd_2err_dq(struct mlxsw_core *mlxsw_core,
960 u32 dq_number, u8 opcode_mod)
962 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ,
963 opcode_mod, dq_number);
966 static inline int mlxsw_cmd_2err_sdq(struct mlxsw_core *mlxsw_core,
969 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number,
970 MLXSW_CMD_OPCODE_MOD_SDQ);
973 static inline int mlxsw_cmd_2err_rdq(struct mlxsw_core *mlxsw_core,
976 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number,
977 MLXSW_CMD_OPCODE_MOD_RDQ);
980 /* QUERY_DQ - Query DQ
981 * ---------------------
982 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ)
983 * INMmod == DQ number
984 * ----------------------------------------------
985 * The QUERY_DQ command retrieves a snapshot of DQ parameters from the hardware.
987 * Note: Output mailbox has the same format as SW2HW_DQ.
990 static inline int __mlxsw_cmd_query_dq(struct mlxsw_core *mlxsw_core,
991 char *out_mbox, u32 dq_number,
994 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ,
995 opcode_mod, dq_number, false,
996 out_mbox, MLXSW_CMD_MBOX_SIZE);
999 static inline int mlxsw_cmd_query_sdq(struct mlxsw_core *mlxsw_core,
1000 char *out_mbox, u32 dq_number)
1002 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number,
1003 MLXSW_CMD_OPCODE_MOD_SDQ);
1006 static inline int mlxsw_cmd_query_rdq(struct mlxsw_core *mlxsw_core,
1007 char *out_mbox, u32 dq_number)
1009 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number,
1010 MLXSW_CMD_OPCODE_MOD_RDQ);
1013 /* SW2HW_CQ - Software to Hardware CQ
1014 * ----------------------------------
1015 * OpMod == 0 (N/A), INMmod == CQ number
1016 * -------------------------------------
1017 * The SW2HW_CQ command transfers ownership of a CQ context entry from software
1018 * to hardware. The command takes the CQ context entry from the input mailbox
1019 * and stores it in the CQC in the ownership of the hardware. The command fails
1020 * if the requested CQC entry is already in the ownership of the hardware.
1023 static inline int mlxsw_cmd_sw2hw_cq(struct mlxsw_core *mlxsw_core,
1024 char *in_mbox, u32 cq_number)
1026 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_CQ,
1027 0, cq_number, in_mbox, MLXSW_CMD_MBOX_SIZE);
1030 /* cmd_mbox_sw2hw_cq_cv
1032 * 0 - CQE Version 0, 1 - CQE Version 1
1034 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, cv, 0x00, 28, 4);
1036 /* cmd_mbox_sw2hw_cq_c_eqn
1037 * Event Queue this CQ reports completion events to.
1039 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, c_eqn, 0x00, 24, 1);
1041 /* cmd_mbox_sw2hw_cq_oi
1042 * When set, overrun ignore is enabled. When set, updates of
1043 * CQ consumer counter (poll for completion) or Request completion
1044 * notifications (Arm CQ) DoorBells should not be rung on that CQ.
1046 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, oi, 0x00, 12, 1);
1048 /* cmd_mbox_sw2hw_cq_st
1049 * Event delivery state machine
1051 * 0x1 - ARMED (Request for Notification)
1053 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, st, 0x00, 8, 1);
1055 /* cmd_mbox_sw2hw_cq_log_cq_size
1056 * Log (base 2) of the CQ size (in entries).
1058 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, log_cq_size, 0x00, 0, 4);
1060 /* cmd_mbox_sw2hw_cq_producer_counter
1061 * Producer Counter. The counter is incremented for each CQE that is
1062 * written by the HW to the CQ.
1063 * Maintained by HW (valid for the QUERY_CQ command only)
1065 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, producer_counter, 0x04, 0, 16);
1067 /* cmd_mbox_sw2hw_cq_pa
1070 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_cq, pa, 0x10, 11, 53, 0x08, 0x00, true);
1072 /* HW2SW_CQ - Hardware to Software CQ
1073 * ----------------------------------
1074 * OpMod == 0 (N/A), INMmod == CQ number
1075 * -------------------------------------
1076 * The HW2SW_CQ command transfers ownership of a CQ context entry from hardware
1077 * to software. The CQC entry is invalidated as a result of this command.
1080 static inline int mlxsw_cmd_hw2sw_cq(struct mlxsw_core *mlxsw_core,
1083 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_CQ,
1087 /* QUERY_CQ - Query CQ
1088 * ----------------------------------
1089 * OpMod == 0 (N/A), INMmod == CQ number
1090 * -------------------------------------
1091 * The QUERY_CQ command retrieves a snapshot of the current CQ context entry.
1092 * The command stores the snapshot in the output mailbox in the software format.
1093 * Note that the CQ context state and values are not affected by the QUERY_CQ
1094 * command. The QUERY_CQ command is for debug purposes only.
1096 * Note: Output mailbox has the same format as SW2HW_CQ.
1099 static inline int mlxsw_cmd_query_cq(struct mlxsw_core *mlxsw_core,
1100 char *out_mbox, u32 cq_number)
1102 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_CQ,
1103 0, cq_number, false,
1104 out_mbox, MLXSW_CMD_MBOX_SIZE);
1107 /* SW2HW_EQ - Software to Hardware EQ
1108 * ----------------------------------
1109 * OpMod == 0 (N/A), INMmod == EQ number
1110 * -------------------------------------
1111 * The SW2HW_EQ command transfers ownership of an EQ context entry from software
1112 * to hardware. The command takes the EQ context entry from the input mailbox
1113 * and stores it in the EQC in the ownership of the hardware. The command fails
1114 * if the requested EQC entry is already in the ownership of the hardware.
1117 static inline int mlxsw_cmd_sw2hw_eq(struct mlxsw_core *mlxsw_core,
1118 char *in_mbox, u32 eq_number)
1120 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_EQ,
1121 0, eq_number, in_mbox, MLXSW_CMD_MBOX_SIZE);
1124 /* cmd_mbox_sw2hw_eq_int_msix
1125 * When set, MSI-X cycles will be generated by this EQ.
1126 * When cleared, an interrupt will be generated by this EQ.
1128 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, int_msix, 0x00, 24, 1);
1130 /* cmd_mbox_sw2hw_eq_int_oi
1131 * When set, overrun ignore is enabled.
1133 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, oi, 0x00, 12, 1);
1135 /* cmd_mbox_sw2hw_eq_int_st
1136 * Event delivery state machine
1138 * 0x1 - ARMED (Request for Notification)
1139 * 0x11 - Always ARMED
1142 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, st, 0x00, 8, 2);
1144 /* cmd_mbox_sw2hw_eq_int_log_eq_size
1145 * Log (base 2) of the EQ size (in entries).
1147 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, log_eq_size, 0x00, 0, 4);
1149 /* cmd_mbox_sw2hw_eq_int_producer_counter
1150 * Producer Counter. The counter is incremented for each EQE that is written
1151 * by the HW to the EQ.
1152 * Maintained by HW (valid for the QUERY_EQ command only)
1154 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, producer_counter, 0x04, 0, 16);
1156 /* cmd_mbox_sw2hw_eq_int_pa
1159 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_eq, pa, 0x10, 11, 53, 0x08, 0x00, true);
1161 /* HW2SW_EQ - Hardware to Software EQ
1162 * ----------------------------------
1163 * OpMod == 0 (N/A), INMmod == EQ number
1164 * -------------------------------------
1167 static inline int mlxsw_cmd_hw2sw_eq(struct mlxsw_core *mlxsw_core,
1170 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_EQ,
1174 /* QUERY_EQ - Query EQ
1175 * ----------------------------------
1176 * OpMod == 0 (N/A), INMmod == EQ number
1177 * -------------------------------------
1179 * Note: Output mailbox has the same format as SW2HW_EQ.
1182 static inline int mlxsw_cmd_query_eq(struct mlxsw_core *mlxsw_core,
1183 char *out_mbox, u32 eq_number)
1185 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_EQ,
1186 0, eq_number, false,
1187 out_mbox, MLXSW_CMD_MBOX_SIZE);