2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/mlx5/mlx5_ifc.h>
50 #include <linux/mlx5/vport.h>
51 #ifdef CONFIG_RFS_ACCEL
52 #include <linux/cpu_rmap.h>
54 #include <linux/version.h>
55 #include <net/devlink.h>
56 #include "mlx5_core.h"
61 #include "fpga/core.h"
62 #include "fpga/ipsec.h"
63 #include "accel/ipsec.h"
64 #include "accel/tls.h"
65 #include "lib/clock.h"
66 #include "lib/vxlan.h"
67 #include "diag/fw_tracer.h"
69 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
70 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
71 MODULE_LICENSE("Dual BSD/GPL");
72 MODULE_VERSION(DRIVER_VERSION);
74 unsigned int mlx5_core_debug_mask;
75 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
76 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
78 #define MLX5_DEFAULT_PROF 2
79 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
80 module_param_named(prof_sel, prof_sel, uint, 0444);
81 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
83 static u32 sw_owner_id[4];
86 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
87 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
90 static struct mlx5_profile profile[] = {
95 .mask = MLX5_PROF_MASK_QP_SIZE,
99 .mask = MLX5_PROF_MASK_QP_SIZE |
100 MLX5_PROF_MASK_MR_CACHE,
169 #define FW_INIT_TIMEOUT_MILI 2000
170 #define FW_INIT_WAIT_MS 2
171 #define FW_PRE_INIT_TIMEOUT_MILI 10000
173 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
175 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
178 while (fw_initializing(dev)) {
179 if (time_after(jiffies, end)) {
183 msleep(FW_INIT_WAIT_MS);
189 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
191 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
193 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
194 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
195 int remaining_size = driver_ver_sz;
198 if (!MLX5_CAP_GEN(dev, driver_version))
201 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
203 strncpy(string, "Linux", remaining_size);
205 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
206 strncat(string, ",", remaining_size);
208 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
209 strncat(string, DRIVER_NAME, remaining_size);
211 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
212 strncat(string, ",", remaining_size);
214 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
216 snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
217 (u8)((LINUX_VERSION_CODE >> 16) & 0xff), (u8)((LINUX_VERSION_CODE >> 8) & 0xff),
218 (u16)(LINUX_VERSION_CODE & 0xffff));
221 MLX5_SET(set_driver_version_in, in, opcode,
222 MLX5_CMD_OP_SET_DRIVER_VERSION);
224 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
227 static int set_dma_caps(struct pci_dev *pdev)
231 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
233 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
234 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
236 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
241 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
244 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
245 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
248 "Can't set consistent PCI DMA mask, aborting\n");
253 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
257 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
259 struct pci_dev *pdev = dev->pdev;
262 mutex_lock(&dev->pci_status_mutex);
263 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
264 err = pci_enable_device(pdev);
266 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
268 mutex_unlock(&dev->pci_status_mutex);
273 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
275 struct pci_dev *pdev = dev->pdev;
277 mutex_lock(&dev->pci_status_mutex);
278 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
279 pci_disable_device(pdev);
280 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
282 mutex_unlock(&dev->pci_status_mutex);
285 static int request_bar(struct pci_dev *pdev)
289 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
290 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
294 err = pci_request_regions(pdev, DRIVER_NAME);
296 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
301 static void release_bar(struct pci_dev *pdev)
303 pci_release_regions(pdev);
306 static int mlx5_alloc_irq_vectors(struct mlx5_core_dev *dev)
308 struct mlx5_priv *priv = &dev->priv;
309 struct mlx5_eq_table *table = &priv->eq_table;
310 int num_eqs = MLX5_CAP_GEN(dev, max_num_eqs) ?
311 MLX5_CAP_GEN(dev, max_num_eqs) :
312 1 << MLX5_CAP_GEN(dev, log_max_eq);
316 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
317 MLX5_EQ_VEC_COMP_BASE;
318 nvec = min_t(int, nvec, num_eqs);
319 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
322 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
326 nvec = pci_alloc_irq_vectors(dev->pdev,
327 MLX5_EQ_VEC_COMP_BASE + 1, nvec,
331 goto err_free_irq_info;
334 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
339 kfree(priv->irq_info);
343 static void mlx5_free_irq_vectors(struct mlx5_core_dev *dev)
345 struct mlx5_priv *priv = &dev->priv;
347 pci_free_irq_vectors(dev->pdev);
348 kfree(priv->irq_info);
351 struct mlx5_reg_host_endianness {
356 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
359 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
360 MLX5_DEV_CAP_FLAG_DCT,
363 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
379 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
384 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
385 enum mlx5_cap_type cap_type,
386 enum mlx5_cap_mode cap_mode)
388 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
389 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
390 void *out, *hca_caps;
391 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
394 memset(in, 0, sizeof(in));
395 out = kzalloc(out_sz, GFP_KERNEL);
399 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
400 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
401 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
404 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
405 cap_type, cap_mode, err);
409 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
412 case HCA_CAP_OPMOD_GET_MAX:
413 memcpy(dev->caps.hca_max[cap_type], hca_caps,
414 MLX5_UN_SZ_BYTES(hca_cap_union));
416 case HCA_CAP_OPMOD_GET_CUR:
417 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
418 MLX5_UN_SZ_BYTES(hca_cap_union));
422 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
432 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
436 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
439 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
442 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
444 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
446 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
447 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
448 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
451 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
455 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
459 if (MLX5_CAP_GEN(dev, atomic)) {
460 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
469 supported_atomic_req_8B_endianness_mode_1);
471 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
474 set_ctx = kzalloc(set_sz, GFP_KERNEL);
478 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
480 /* Set requestor to host endianness */
481 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
482 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
484 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
490 static int handle_hca_cap(struct mlx5_core_dev *dev)
492 void *set_ctx = NULL;
493 struct mlx5_profile *prof = dev->profile;
495 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
498 set_ctx = kzalloc(set_sz, GFP_KERNEL);
502 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
506 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
508 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
509 MLX5_ST_SZ_BYTES(cmd_hca_cap));
511 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
512 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
514 /* we limit the size of the pkey table to 128 entries for now */
515 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
516 to_fw_pkey_sz(dev, 128));
518 /* Check log_max_qp from HCA caps to set in current profile */
519 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
520 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
521 profile[prof_sel].log_max_qp,
522 MLX5_CAP_GEN_MAX(dev, log_max_qp));
523 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
525 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
526 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
529 /* disable cmdif checksum */
530 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
532 /* Enable 4K UAR only when HCA supports it and page size is bigger
535 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
536 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
538 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
540 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
541 MLX5_SET(cmd_hca_cap,
544 cache_line_size() >= 128 ? 1 : 0);
546 if (MLX5_CAP_GEN_MAX(dev, dct))
547 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
549 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
550 MLX5_SET(cmd_hca_cap,
553 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
555 err = set_caps(dev, set_ctx, set_sz,
556 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
563 static int set_hca_ctrl(struct mlx5_core_dev *dev)
565 struct mlx5_reg_host_endianness he_in;
566 struct mlx5_reg_host_endianness he_out;
569 if (!mlx5_core_is_pf(dev))
572 memset(&he_in, 0, sizeof(he_in));
573 he_in.he = MLX5_SET_HOST_ENDIANNESS;
574 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
575 &he_out, sizeof(he_out),
576 MLX5_REG_HOST_ENDIANNESS, 0, 1);
580 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
584 /* Disable local_lb by default */
585 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
586 ret = mlx5_nic_vport_update_local_lb(dev, false);
591 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
593 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
594 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
596 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
597 MLX5_SET(enable_hca_in, in, function_id, func_id);
598 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
601 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
603 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
604 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
606 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
607 MLX5_SET(disable_hca_in, in, function_id, func_id);
608 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
611 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev)
613 u32 timer_h, timer_h1, timer_l;
615 timer_h = ioread32be(&dev->iseg->internal_timer_h);
616 timer_l = ioread32be(&dev->iseg->internal_timer_l);
617 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
618 if (timer_h != timer_h1) /* wrap around */
619 timer_l = ioread32be(&dev->iseg->internal_timer_l);
621 return (u64)timer_l | (u64)timer_h1 << 32;
624 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
626 struct mlx5_priv *priv = &mdev->priv;
627 int vecidx = MLX5_EQ_VEC_COMP_BASE + i;
628 int irq = pci_irq_vector(mdev->pdev, vecidx);
630 if (!zalloc_cpumask_var(&priv->irq_info[vecidx].mask, GFP_KERNEL)) {
631 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
635 cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node),
636 priv->irq_info[vecidx].mask);
638 if (IS_ENABLED(CONFIG_SMP) &&
639 irq_set_affinity_hint(irq, priv->irq_info[vecidx].mask))
640 mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq);
645 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
647 int vecidx = MLX5_EQ_VEC_COMP_BASE + i;
648 struct mlx5_priv *priv = &mdev->priv;
649 int irq = pci_irq_vector(mdev->pdev, vecidx);
651 irq_set_affinity_hint(irq, NULL);
652 free_cpumask_var(priv->irq_info[vecidx].mask);
655 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
660 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
661 err = mlx5_irq_set_affinity_hint(mdev, i);
669 for (i--; i >= 0; i--)
670 mlx5_irq_clear_affinity_hint(mdev, i);
675 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
679 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
680 mlx5_irq_clear_affinity_hint(mdev, i);
683 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
686 struct mlx5_eq_table *table = &dev->priv.eq_table;
687 struct mlx5_eq *eq, *n;
690 spin_lock(&table->lock);
691 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
692 if (eq->index == vector) {
699 spin_unlock(&table->lock);
703 EXPORT_SYMBOL(mlx5_vector2eqn);
705 struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
707 struct mlx5_eq_table *table = &dev->priv.eq_table;
710 spin_lock(&table->lock);
711 list_for_each_entry(eq, &table->comp_eqs_list, list)
712 if (eq->eqn == eqn) {
713 spin_unlock(&table->lock);
717 spin_unlock(&table->lock);
719 return ERR_PTR(-ENOENT);
722 static void free_comp_eqs(struct mlx5_core_dev *dev)
724 struct mlx5_eq_table *table = &dev->priv.eq_table;
725 struct mlx5_eq *eq, *n;
727 #ifdef CONFIG_RFS_ACCEL
729 free_irq_cpu_rmap(dev->rmap);
733 spin_lock(&table->lock);
734 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
736 spin_unlock(&table->lock);
737 if (mlx5_destroy_unmap_eq(dev, eq))
738 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
741 spin_lock(&table->lock);
743 spin_unlock(&table->lock);
746 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
748 struct mlx5_eq_table *table = &dev->priv.eq_table;
749 char name[MLX5_MAX_IRQ_NAME];
756 INIT_LIST_HEAD(&table->comp_eqs_list);
757 ncomp_vec = table->num_comp_vectors;
758 nent = MLX5_COMP_EQ_SIZE;
759 #ifdef CONFIG_RFS_ACCEL
760 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
764 for (i = 0; i < ncomp_vec; i++) {
765 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
771 #ifdef CONFIG_RFS_ACCEL
772 irq_cpu_rmap_add(dev->rmap, pci_irq_vector(dev->pdev,
773 MLX5_EQ_VEC_COMP_BASE + i));
775 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
776 err = mlx5_create_map_eq(dev, eq,
777 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
778 name, MLX5_EQ_TYPE_COMP);
783 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
785 spin_lock(&table->lock);
786 list_add_tail(&eq->list, &table->comp_eqs_list);
787 spin_unlock(&table->lock);
797 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
799 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
800 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
804 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
805 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
806 query_out, sizeof(query_out));
811 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
812 if (!status || syndrome == MLX5_DRIVER_SYND) {
813 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
814 err, status, syndrome);
818 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
823 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
825 if (sup_issi & (1 << 1)) {
826 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
827 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
829 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
830 MLX5_SET(set_issi_in, set_in, current_issi, 1);
831 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
832 set_out, sizeof(set_out));
834 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
842 } else if (sup_issi & (1 << 0) || !sup_issi) {
849 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
851 struct pci_dev *pdev = dev->pdev;
854 pci_set_drvdata(dev->pdev, dev);
855 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
856 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
858 mutex_init(&priv->pgdir_mutex);
859 INIT_LIST_HEAD(&priv->pgdir_list);
860 spin_lock_init(&priv->mkey_lock);
862 mutex_init(&priv->alloc_mutex);
864 priv->numa_node = dev_to_node(&dev->pdev->dev);
866 if (mlx5_debugfs_root)
868 debugfs_create_dir(pci_name(pdev), mlx5_debugfs_root);
870 err = mlx5_pci_enable_device(dev);
872 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
876 err = request_bar(pdev);
878 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
882 pci_set_master(pdev);
884 err = set_dma_caps(pdev);
886 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
890 dev->iseg_base = pci_resource_start(dev->pdev, 0);
891 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
894 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
901 pci_clear_master(dev->pdev);
902 release_bar(dev->pdev);
904 mlx5_pci_disable_device(dev);
907 debugfs_remove(priv->dbg_root);
911 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
914 pci_clear_master(dev->pdev);
915 release_bar(dev->pdev);
916 mlx5_pci_disable_device(dev);
917 debugfs_remove_recursive(priv->dbg_root);
920 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
922 struct pci_dev *pdev = dev->pdev;
925 err = mlx5_query_board_id(dev);
927 dev_err(&pdev->dev, "query board id failed\n");
931 err = mlx5_eq_init(dev);
933 dev_err(&pdev->dev, "failed to initialize eq\n");
937 err = mlx5_cq_debugfs_init(dev);
939 dev_err(&pdev->dev, "failed to initialize cq debugfs\n");
943 mlx5_init_qp_table(dev);
945 mlx5_init_srq_table(dev);
947 mlx5_init_mkey_table(dev);
949 mlx5_init_reserved_gids(dev);
951 mlx5_init_clock(dev);
953 dev->vxlan = mlx5_vxlan_create(dev);
955 err = mlx5_init_rl_table(dev);
957 dev_err(&pdev->dev, "Failed to init rate limiting\n");
958 goto err_tables_cleanup;
961 err = mlx5_mpfs_init(dev);
963 dev_err(&pdev->dev, "Failed to init l2 table %d\n", err);
967 err = mlx5_eswitch_init(dev);
969 dev_err(&pdev->dev, "Failed to init eswitch %d\n", err);
970 goto err_mpfs_cleanup;
973 err = mlx5_sriov_init(dev);
975 dev_err(&pdev->dev, "Failed to init sriov %d\n", err);
976 goto err_eswitch_cleanup;
979 err = mlx5_fpga_init(dev);
981 dev_err(&pdev->dev, "Failed to init fpga device %d\n", err);
982 goto err_sriov_cleanup;
985 dev->tracer = mlx5_fw_tracer_create(dev);
990 mlx5_sriov_cleanup(dev);
992 mlx5_eswitch_cleanup(dev->priv.eswitch);
994 mlx5_mpfs_cleanup(dev);
996 mlx5_cleanup_rl_table(dev);
998 mlx5_vxlan_destroy(dev->vxlan);
999 mlx5_cleanup_mkey_table(dev);
1000 mlx5_cleanup_srq_table(dev);
1001 mlx5_cleanup_qp_table(dev);
1002 mlx5_cq_debugfs_cleanup(dev);
1005 mlx5_eq_cleanup(dev);
1011 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1013 mlx5_fw_tracer_destroy(dev->tracer);
1014 mlx5_fpga_cleanup(dev);
1015 mlx5_sriov_cleanup(dev);
1016 mlx5_eswitch_cleanup(dev->priv.eswitch);
1017 mlx5_mpfs_cleanup(dev);
1018 mlx5_cleanup_rl_table(dev);
1019 mlx5_vxlan_destroy(dev->vxlan);
1020 mlx5_cleanup_clock(dev);
1021 mlx5_cleanup_reserved_gids(dev);
1022 mlx5_cleanup_mkey_table(dev);
1023 mlx5_cleanup_srq_table(dev);
1024 mlx5_cleanup_qp_table(dev);
1025 mlx5_cq_debugfs_cleanup(dev);
1026 mlx5_eq_cleanup(dev);
1029 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1032 struct pci_dev *pdev = dev->pdev;
1035 mutex_lock(&dev->intf_state_mutex);
1036 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1037 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
1042 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1043 fw_rev_min(dev), fw_rev_sub(dev));
1045 /* Only PFs hold the relevant PCIe information for this query */
1046 if (mlx5_core_is_pf(dev))
1047 pcie_print_link_status(dev->pdev);
1049 /* on load removing any previous indication of internal error, device is
1052 dev->state = MLX5_DEVICE_STATE_UP;
1054 /* wait for firmware to accept initialization segments configurations
1056 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI);
1058 dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n",
1059 FW_PRE_INIT_TIMEOUT_MILI);
1063 err = mlx5_cmd_init(dev);
1065 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
1069 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1071 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1072 FW_INIT_TIMEOUT_MILI);
1073 goto err_cmd_cleanup;
1076 err = mlx5_core_enable_hca(dev, 0);
1078 dev_err(&pdev->dev, "enable hca failed\n");
1079 goto err_cmd_cleanup;
1082 err = mlx5_core_set_issi(dev);
1084 dev_err(&pdev->dev, "failed to set issi\n");
1085 goto err_disable_hca;
1088 err = mlx5_satisfy_startup_pages(dev, 1);
1090 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1091 goto err_disable_hca;
1094 err = set_hca_ctrl(dev);
1096 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
1097 goto reclaim_boot_pages;
1100 err = handle_hca_cap(dev);
1102 dev_err(&pdev->dev, "handle_hca_cap failed\n");
1103 goto reclaim_boot_pages;
1106 err = handle_hca_cap_atomic(dev);
1108 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1109 goto reclaim_boot_pages;
1112 err = mlx5_satisfy_startup_pages(dev, 0);
1114 dev_err(&pdev->dev, "failed to allocate init pages\n");
1115 goto reclaim_boot_pages;
1118 err = mlx5_pagealloc_start(dev);
1120 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
1121 goto reclaim_boot_pages;
1124 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1126 dev_err(&pdev->dev, "init hca failed\n");
1127 goto err_pagealloc_stop;
1130 mlx5_set_driver_version(dev);
1132 mlx5_start_health_poll(dev);
1134 err = mlx5_query_hca_caps(dev);
1136 dev_err(&pdev->dev, "query hca failed\n");
1141 err = mlx5_init_once(dev, priv);
1143 dev_err(&pdev->dev, "sw objs init failed\n");
1148 err = mlx5_alloc_irq_vectors(dev);
1150 dev_err(&pdev->dev, "alloc irq vectors failed\n");
1151 goto err_cleanup_once;
1154 dev->priv.uar = mlx5_get_uars_page(dev);
1155 if (IS_ERR(dev->priv.uar)) {
1156 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1157 err = PTR_ERR(dev->priv.uar);
1158 goto err_disable_msix;
1161 err = mlx5_start_eqs(dev);
1163 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1167 err = mlx5_fw_tracer_init(dev->tracer);
1169 dev_err(&pdev->dev, "Failed to init FW tracer\n");
1173 err = alloc_comp_eqs(dev);
1175 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1179 err = mlx5_irq_set_affinity_hints(dev);
1181 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1182 goto err_affinity_hints;
1185 err = mlx5_fpga_device_start(dev);
1187 dev_err(&pdev->dev, "fpga device start failed %d\n", err);
1188 goto err_fpga_start;
1191 err = mlx5_accel_ipsec_init(dev);
1193 dev_err(&pdev->dev, "IPSec device start failed %d\n", err);
1194 goto err_ipsec_start;
1197 err = mlx5_accel_tls_init(dev);
1199 dev_err(&pdev->dev, "TLS device start failed %d\n", err);
1203 err = mlx5_init_fs(dev);
1205 dev_err(&pdev->dev, "Failed to init flow steering\n");
1209 err = mlx5_core_set_hca_defaults(dev);
1211 dev_err(&pdev->dev, "Failed to set hca defaults\n");
1215 err = mlx5_sriov_attach(dev);
1217 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1221 if (mlx5_device_registered(dev)) {
1222 mlx5_attach_device(dev);
1224 err = mlx5_register_device(dev);
1226 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1231 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1233 mutex_unlock(&dev->intf_state_mutex);
1238 mlx5_sriov_detach(dev);
1241 mlx5_cleanup_fs(dev);
1244 mlx5_accel_tls_cleanup(dev);
1247 mlx5_accel_ipsec_cleanup(dev);
1250 mlx5_fpga_device_stop(dev);
1253 mlx5_irq_clear_affinity_hints(dev);
1259 mlx5_fw_tracer_cleanup(dev->tracer);
1265 mlx5_put_uars_page(dev, priv->uar);
1268 mlx5_free_irq_vectors(dev);
1272 mlx5_cleanup_once(dev);
1275 mlx5_stop_health_poll(dev, boot);
1276 if (mlx5_cmd_teardown_hca(dev)) {
1277 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1282 mlx5_pagealloc_stop(dev);
1285 mlx5_reclaim_startup_pages(dev);
1288 mlx5_core_disable_hca(dev, 0);
1291 mlx5_cmd_cleanup(dev);
1294 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1295 mutex_unlock(&dev->intf_state_mutex);
1300 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1306 mlx5_drain_health_recovery(dev);
1308 mutex_lock(&dev->intf_state_mutex);
1309 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1310 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1313 mlx5_cleanup_once(dev);
1317 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1319 if (mlx5_device_registered(dev))
1320 mlx5_detach_device(dev);
1322 mlx5_sriov_detach(dev);
1323 mlx5_cleanup_fs(dev);
1324 mlx5_accel_ipsec_cleanup(dev);
1325 mlx5_accel_tls_cleanup(dev);
1326 mlx5_fpga_device_stop(dev);
1327 mlx5_irq_clear_affinity_hints(dev);
1329 mlx5_fw_tracer_cleanup(dev->tracer);
1331 mlx5_put_uars_page(dev, priv->uar);
1332 mlx5_free_irq_vectors(dev);
1334 mlx5_cleanup_once(dev);
1335 mlx5_stop_health_poll(dev, cleanup);
1336 err = mlx5_cmd_teardown_hca(dev);
1338 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1341 mlx5_pagealloc_stop(dev);
1342 mlx5_reclaim_startup_pages(dev);
1343 mlx5_core_disable_hca(dev, 0);
1344 mlx5_cmd_cleanup(dev);
1347 mutex_unlock(&dev->intf_state_mutex);
1351 struct mlx5_core_event_handler {
1352 void (*event)(struct mlx5_core_dev *dev,
1353 enum mlx5_dev_event event,
1357 static const struct devlink_ops mlx5_devlink_ops = {
1358 #ifdef CONFIG_MLX5_ESWITCH
1359 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1360 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1361 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
1362 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
1363 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
1364 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
1368 #define MLX5_IB_MOD "mlx5_ib"
1369 static int init_one(struct pci_dev *pdev,
1370 const struct pci_device_id *id)
1372 struct mlx5_core_dev *dev;
1373 struct devlink *devlink;
1374 struct mlx5_priv *priv;
1377 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1379 dev_err(&pdev->dev, "kzalloc failed\n");
1383 dev = devlink_priv(devlink);
1385 priv->pci_dev_data = id->driver_data;
1387 pci_set_drvdata(pdev, dev);
1390 dev->event = mlx5_core_event;
1391 dev->profile = &profile[prof_sel];
1393 INIT_LIST_HEAD(&priv->ctx_list);
1394 spin_lock_init(&priv->ctx_lock);
1395 mutex_init(&dev->pci_status_mutex);
1396 mutex_init(&dev->intf_state_mutex);
1398 INIT_LIST_HEAD(&priv->waiting_events_list);
1399 priv->is_accum_events = false;
1401 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1402 err = init_srcu_struct(&priv->pfault_srcu);
1404 dev_err(&pdev->dev, "init_srcu_struct failed with error code %d\n",
1409 mutex_init(&priv->bfregs.reg_head.lock);
1410 mutex_init(&priv->bfregs.wc_head.lock);
1411 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1412 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1414 err = mlx5_pci_init(dev, priv);
1416 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1420 err = mlx5_health_init(dev);
1422 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1426 mlx5_pagealloc_init(dev);
1428 err = mlx5_load_one(dev, priv, true);
1430 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1434 request_module_nowait(MLX5_IB_MOD);
1436 err = devlink_register(devlink, &pdev->dev);
1440 pci_save_state(pdev);
1444 mlx5_unload_one(dev, priv, true);
1446 mlx5_pagealloc_cleanup(dev);
1447 mlx5_health_cleanup(dev);
1449 mlx5_pci_close(dev, priv);
1451 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1452 cleanup_srcu_struct(&priv->pfault_srcu);
1455 devlink_free(devlink);
1460 static void remove_one(struct pci_dev *pdev)
1462 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1463 struct devlink *devlink = priv_to_devlink(dev);
1464 struct mlx5_priv *priv = &dev->priv;
1466 devlink_unregister(devlink);
1467 mlx5_unregister_device(dev);
1469 if (mlx5_unload_one(dev, priv, true)) {
1470 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1471 mlx5_health_cleanup(dev);
1475 mlx5_pagealloc_cleanup(dev);
1476 mlx5_health_cleanup(dev);
1477 mlx5_pci_close(dev, priv);
1478 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1479 cleanup_srcu_struct(&priv->pfault_srcu);
1481 devlink_free(devlink);
1484 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1485 pci_channel_state_t state)
1487 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1488 struct mlx5_priv *priv = &dev->priv;
1490 dev_info(&pdev->dev, "%s was called\n", __func__);
1492 mlx5_enter_error_state(dev, false);
1493 mlx5_unload_one(dev, priv, false);
1494 /* In case of kernel call drain the health wq */
1496 mlx5_drain_health_wq(dev);
1497 mlx5_pci_disable_device(dev);
1500 return state == pci_channel_io_perm_failure ?
1501 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1504 /* wait for the device to show vital signs by waiting
1505 * for the health counter to start counting.
1507 static int wait_vital(struct pci_dev *pdev)
1509 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1510 struct mlx5_core_health *health = &dev->priv.health;
1511 const int niter = 100;
1516 for (i = 0; i < niter; i++) {
1517 count = ioread32be(health->health_counter);
1518 if (count && count != 0xffffffff) {
1519 if (last_count && last_count != count) {
1520 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1531 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1533 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1536 dev_info(&pdev->dev, "%s was called\n", __func__);
1538 err = mlx5_pci_enable_device(dev);
1540 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1542 return PCI_ERS_RESULT_DISCONNECT;
1545 pci_set_master(pdev);
1546 pci_restore_state(pdev);
1547 pci_save_state(pdev);
1549 if (wait_vital(pdev)) {
1550 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1551 return PCI_ERS_RESULT_DISCONNECT;
1554 return PCI_ERS_RESULT_RECOVERED;
1557 static void mlx5_pci_resume(struct pci_dev *pdev)
1559 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1560 struct mlx5_priv *priv = &dev->priv;
1563 dev_info(&pdev->dev, "%s was called\n", __func__);
1565 err = mlx5_load_one(dev, priv, false);
1567 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1570 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1573 static const struct pci_error_handlers mlx5_err_handler = {
1574 .error_detected = mlx5_pci_err_detected,
1575 .slot_reset = mlx5_pci_slot_reset,
1576 .resume = mlx5_pci_resume
1579 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1583 if (!MLX5_CAP_GEN(dev, force_teardown)) {
1584 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
1588 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1589 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1593 /* Panic tear down fw command will stop the PCI bus communication
1594 * with the HCA, so the health polll is no longer needed.
1596 mlx5_drain_health_wq(dev);
1597 mlx5_stop_health_poll(dev, false);
1599 ret = mlx5_cmd_force_teardown_hca(dev);
1601 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1602 mlx5_start_health_poll(dev);
1606 mlx5_enter_error_state(dev, true);
1608 /* Some platforms requiring freeing the IRQ's in the shutdown
1609 * flow. If they aren't freed they can't be allocated after
1610 * kexec. There is no need to cleanup the mlx5_core software
1613 mlx5_irq_clear_affinity_hints(dev);
1614 mlx5_core_eq_free_irqs(dev);
1619 static void shutdown(struct pci_dev *pdev)
1621 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1622 struct mlx5_priv *priv = &dev->priv;
1625 dev_info(&pdev->dev, "Shutdown was called\n");
1626 err = mlx5_try_fast_unload(dev);
1628 mlx5_unload_one(dev, priv, false);
1629 mlx5_pci_disable_device(dev);
1632 static const struct pci_device_id mlx5_core_pci_table[] = {
1633 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1634 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1635 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1636 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1637 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1638 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1639 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1640 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1641 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1642 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1643 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1644 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1645 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1646 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1647 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1651 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1653 void mlx5_disable_device(struct mlx5_core_dev *dev)
1655 mlx5_pci_err_detected(dev->pdev, 0);
1658 void mlx5_recover_device(struct mlx5_core_dev *dev)
1660 mlx5_pci_disable_device(dev);
1661 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1662 mlx5_pci_resume(dev->pdev);
1665 static struct pci_driver mlx5_core_driver = {
1666 .name = DRIVER_NAME,
1667 .id_table = mlx5_core_pci_table,
1669 .remove = remove_one,
1670 .shutdown = shutdown,
1671 .err_handler = &mlx5_err_handler,
1672 .sriov_configure = mlx5_core_sriov_configure,
1675 static void mlx5_core_verify_params(void)
1677 if (prof_sel >= ARRAY_SIZE(profile)) {
1678 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1680 ARRAY_SIZE(profile) - 1,
1682 prof_sel = MLX5_DEFAULT_PROF;
1686 static int __init init(void)
1690 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1692 mlx5_core_verify_params();
1693 mlx5_fpga_ipsec_build_fs_cmds();
1694 mlx5_register_debugfs();
1696 err = pci_register_driver(&mlx5_core_driver);
1700 #ifdef CONFIG_MLX5_CORE_EN
1707 mlx5_unregister_debugfs();
1711 static void __exit cleanup(void)
1713 #ifdef CONFIG_MLX5_CORE_EN
1716 pci_unregister_driver(&mlx5_core_driver);
1717 mlx5_unregister_debugfs();
1721 module_exit(cleanup);