2 * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/rhashtable.h>
35 #include <linux/mlx5/driver.h>
36 #include <linux/mlx5/fs_helpers.h>
37 #include <linux/mlx5/fs.h>
38 #include <linux/rbtree.h>
40 #include "mlx5_core.h"
42 #include "fpga/ipsec.h"
44 #include "fpga/core.h"
46 enum mlx5_fpga_ipsec_cmd_status {
47 MLX5_FPGA_IPSEC_CMD_PENDING,
48 MLX5_FPGA_IPSEC_CMD_SEND_FAIL,
49 MLX5_FPGA_IPSEC_CMD_COMPLETE,
52 struct mlx5_fpga_ipsec_cmd_context {
53 struct mlx5_fpga_dma_buf buf;
54 enum mlx5_fpga_ipsec_cmd_status status;
55 struct mlx5_ifc_fpga_ipsec_cmd_resp resp;
57 struct completion complete;
58 struct mlx5_fpga_device *dev;
59 struct list_head list; /* Item in pending_cmds */
63 struct mlx5_fpga_esp_xfrm;
65 struct mlx5_fpga_ipsec_sa_ctx {
66 struct rhash_head hash;
67 struct mlx5_ifc_fpga_ipsec_sa hw_sa;
68 struct mlx5_core_dev *dev;
69 struct mlx5_fpga_esp_xfrm *fpga_xfrm;
72 struct mlx5_fpga_esp_xfrm {
73 unsigned int num_rules;
74 struct mlx5_fpga_ipsec_sa_ctx *sa_ctx;
75 struct mutex lock; /* xfrm lock */
76 struct mlx5_accel_esp_xfrm accel_xfrm;
79 struct mlx5_fpga_ipsec_rule {
82 struct mlx5_fpga_ipsec_sa_ctx *ctx;
85 static const struct rhashtable_params rhash_sa = {
86 /* Keep out "cmd" field from the key as it's
87 * value is not constant during the lifetime
90 .key_len = FIELD_SIZEOF(struct mlx5_fpga_ipsec_sa_ctx, hw_sa) -
91 FIELD_SIZEOF(struct mlx5_ifc_fpga_ipsec_sa_v1, cmd),
92 .key_offset = offsetof(struct mlx5_fpga_ipsec_sa_ctx, hw_sa) +
93 FIELD_SIZEOF(struct mlx5_ifc_fpga_ipsec_sa_v1, cmd),
94 .head_offset = offsetof(struct mlx5_fpga_ipsec_sa_ctx, hash),
95 .automatic_shrinking = true,
99 struct mlx5_fpga_ipsec {
100 struct mlx5_fpga_device *fdev;
101 struct list_head pending_cmds;
102 spinlock_t pending_cmds_lock; /* Protects pending_cmds */
103 u32 caps[MLX5_ST_SZ_DW(ipsec_extended_cap)];
104 struct mlx5_fpga_conn *conn;
106 struct notifier_block fs_notifier_ingress_bypass;
107 struct notifier_block fs_notifier_egress;
109 /* Map hardware SA --> SA context
110 * (mlx5_fpga_ipsec_sa) (mlx5_fpga_ipsec_sa_ctx)
111 * We will use this hash to avoid SAs duplication in fpga which
114 struct rhashtable sa_hash; /* hw_sa -> mlx5_fpga_ipsec_sa_ctx */
115 struct mutex sa_hash_lock;
117 /* Tree holding all rules for this fpga device
118 * Key for searching a rule (mlx5_fpga_ipsec_rule) is (ft, id)
120 struct rb_root rules_rb;
121 struct mutex rules_rb_lock; /* rules lock */
124 static bool mlx5_fpga_is_ipsec_device(struct mlx5_core_dev *mdev)
126 if (!mdev->fpga || !MLX5_CAP_GEN(mdev, fpga))
129 if (MLX5_CAP_FPGA(mdev, ieee_vendor_id) !=
130 MLX5_FPGA_CAP_SANDBOX_VENDOR_ID_MLNX)
133 if (MLX5_CAP_FPGA(mdev, sandbox_product_id) !=
134 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_IPSEC)
140 static void mlx5_fpga_ipsec_send_complete(struct mlx5_fpga_conn *conn,
141 struct mlx5_fpga_device *fdev,
142 struct mlx5_fpga_dma_buf *buf,
145 struct mlx5_fpga_ipsec_cmd_context *context;
148 context = container_of(buf, struct mlx5_fpga_ipsec_cmd_context,
150 mlx5_fpga_warn(fdev, "IPSec command send failed with status %u\n",
152 context->status = MLX5_FPGA_IPSEC_CMD_SEND_FAIL;
153 complete(&context->complete);
158 int syndrome_to_errno(enum mlx5_ifc_fpga_ipsec_response_syndrome syndrome)
161 case MLX5_FPGA_IPSEC_RESPONSE_SUCCESS:
163 case MLX5_FPGA_IPSEC_RESPONSE_SADB_ISSUE:
165 case MLX5_FPGA_IPSEC_RESPONSE_ILLEGAL_REQUEST:
167 case MLX5_FPGA_IPSEC_RESPONSE_WRITE_RESPONSE_ISSUE:
173 static void mlx5_fpga_ipsec_recv(void *cb_arg, struct mlx5_fpga_dma_buf *buf)
175 struct mlx5_ifc_fpga_ipsec_cmd_resp *resp = buf->sg[0].data;
176 struct mlx5_fpga_ipsec_cmd_context *context;
177 enum mlx5_ifc_fpga_ipsec_response_syndrome syndrome;
178 struct mlx5_fpga_device *fdev = cb_arg;
181 if (buf->sg[0].size < sizeof(*resp)) {
182 mlx5_fpga_warn(fdev, "Short receive from FPGA IPSec: %u < %zu bytes\n",
183 buf->sg[0].size, sizeof(*resp));
187 mlx5_fpga_dbg(fdev, "mlx5_ipsec recv_cb syndrome %08x\n",
188 ntohl(resp->syndrome));
190 spin_lock_irqsave(&fdev->ipsec->pending_cmds_lock, flags);
191 context = list_first_entry_or_null(&fdev->ipsec->pending_cmds,
192 struct mlx5_fpga_ipsec_cmd_context,
195 list_del(&context->list);
196 spin_unlock_irqrestore(&fdev->ipsec->pending_cmds_lock, flags);
199 mlx5_fpga_warn(fdev, "Received IPSec offload response without pending command request\n");
202 mlx5_fpga_dbg(fdev, "Handling response for %p\n", context);
204 syndrome = ntohl(resp->syndrome);
205 context->status_code = syndrome_to_errno(syndrome);
206 context->status = MLX5_FPGA_IPSEC_CMD_COMPLETE;
207 memcpy(&context->resp, resp, sizeof(*resp));
209 if (context->status_code)
210 mlx5_fpga_warn(fdev, "IPSec command failed with syndrome %08x\n",
213 complete(&context->complete);
216 static void *mlx5_fpga_ipsec_cmd_exec(struct mlx5_core_dev *mdev,
217 const void *cmd, int cmd_size)
219 struct mlx5_fpga_ipsec_cmd_context *context;
220 struct mlx5_fpga_device *fdev = mdev->fpga;
224 if (!fdev || !fdev->ipsec)
225 return ERR_PTR(-EOPNOTSUPP);
228 return ERR_PTR(-EINVAL);
230 context = kzalloc(sizeof(*context) + cmd_size, GFP_ATOMIC);
232 return ERR_PTR(-ENOMEM);
234 context->status = MLX5_FPGA_IPSEC_CMD_PENDING;
236 context->buf.complete = mlx5_fpga_ipsec_send_complete;
237 init_completion(&context->complete);
238 memcpy(&context->command, cmd, cmd_size);
239 context->buf.sg[0].size = cmd_size;
240 context->buf.sg[0].data = &context->command;
242 spin_lock_irqsave(&fdev->ipsec->pending_cmds_lock, flags);
243 res = mlx5_fpga_sbu_conn_sendmsg(fdev->ipsec->conn, &context->buf);
245 list_add_tail(&context->list, &fdev->ipsec->pending_cmds);
246 spin_unlock_irqrestore(&fdev->ipsec->pending_cmds_lock, flags);
249 mlx5_fpga_warn(fdev, "Failed to send IPSec command: %d\n", res);
254 /* Context should be freed by the caller after completion. */
258 static int mlx5_fpga_ipsec_cmd_wait(void *ctx)
260 struct mlx5_fpga_ipsec_cmd_context *context = ctx;
261 unsigned long timeout =
262 msecs_to_jiffies(MLX5_FPGA_CMD_TIMEOUT_MSEC);
265 res = wait_for_completion_timeout(&context->complete, timeout);
267 mlx5_fpga_warn(context->dev, "Failure waiting for IPSec command response\n");
271 if (context->status == MLX5_FPGA_IPSEC_CMD_COMPLETE)
272 res = context->status_code;
279 static inline bool is_v2_sadb_supported(struct mlx5_fpga_ipsec *fipsec)
281 if (MLX5_GET(ipsec_extended_cap, fipsec->caps, v2_command))
286 static int mlx5_fpga_ipsec_update_hw_sa(struct mlx5_fpga_device *fdev,
287 struct mlx5_ifc_fpga_ipsec_sa *hw_sa,
290 struct mlx5_core_dev *dev = fdev->mdev;
291 struct mlx5_ifc_fpga_ipsec_sa *sa;
292 struct mlx5_fpga_ipsec_cmd_context *cmd_context;
296 hw_sa->ipsec_sa_v1.cmd = htonl(opcode);
297 if (is_v2_sadb_supported(fdev->ipsec))
298 sa_cmd_size = sizeof(*hw_sa);
300 sa_cmd_size = sizeof(hw_sa->ipsec_sa_v1);
302 cmd_context = (struct mlx5_fpga_ipsec_cmd_context *)
303 mlx5_fpga_ipsec_cmd_exec(dev, hw_sa, sa_cmd_size);
304 if (IS_ERR(cmd_context))
305 return PTR_ERR(cmd_context);
307 err = mlx5_fpga_ipsec_cmd_wait(cmd_context);
311 sa = (struct mlx5_ifc_fpga_ipsec_sa *)&cmd_context->command;
312 if (sa->ipsec_sa_v1.sw_sa_handle != cmd_context->resp.sw_sa_handle) {
313 mlx5_fpga_err(fdev, "mismatch SA handle. cmd 0x%08x vs resp 0x%08x\n",
314 ntohl(sa->ipsec_sa_v1.sw_sa_handle),
315 ntohl(cmd_context->resp.sw_sa_handle));
324 u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev)
326 struct mlx5_fpga_device *fdev = mdev->fpga;
329 if (mlx5_fpga_is_ipsec_device(mdev)) {
330 ret |= MLX5_ACCEL_IPSEC_CAP_DEVICE;
331 ret |= MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA;
339 if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, esp))
340 ret |= MLX5_ACCEL_IPSEC_CAP_ESP;
342 if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, ipv6))
343 ret |= MLX5_ACCEL_IPSEC_CAP_IPV6;
345 if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, lso))
346 ret |= MLX5_ACCEL_IPSEC_CAP_LSO;
348 if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, rx_no_trailer))
349 ret |= MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER;
351 if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, esn)) {
352 ret |= MLX5_ACCEL_IPSEC_CAP_ESN;
353 ret |= MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN;
359 unsigned int mlx5_fpga_ipsec_counters_count(struct mlx5_core_dev *mdev)
361 struct mlx5_fpga_device *fdev = mdev->fpga;
363 if (!fdev || !fdev->ipsec)
366 return MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps,
367 number_of_ipsec_counters);
370 int mlx5_fpga_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
371 unsigned int counters_count)
373 struct mlx5_fpga_device *fdev = mdev->fpga;
380 if (!fdev || !fdev->ipsec)
383 addr = (u64)MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps,
384 ipsec_counters_addr_low) +
385 ((u64)MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps,
386 ipsec_counters_addr_high) << 32);
388 count = mlx5_fpga_ipsec_counters_count(mdev);
390 data = kzalloc(array3_size(sizeof(*data), count, 2), GFP_KERNEL);
396 ret = mlx5_fpga_mem_read(fdev, count * sizeof(u64), addr, data,
397 MLX5_FPGA_ACCESS_TYPE_DONTCARE);
399 mlx5_fpga_err(fdev, "Failed to read IPSec counters from HW: %d\n",
405 if (count > counters_count)
406 count = counters_count;
408 /* Each counter is low word, then high. But each word is big-endian */
409 for (i = 0; i < count; i++)
410 counters[i] = (u64)ntohl(data[i * 2]) |
411 ((u64)ntohl(data[i * 2 + 1]) << 32);
418 static int mlx5_fpga_ipsec_set_caps(struct mlx5_core_dev *mdev, u32 flags)
420 struct mlx5_fpga_ipsec_cmd_context *context;
421 struct mlx5_ifc_fpga_ipsec_cmd_cap cmd = {0};
424 cmd.cmd = htonl(MLX5_FPGA_IPSEC_CMD_OP_SET_CAP);
425 cmd.flags = htonl(flags);
426 context = mlx5_fpga_ipsec_cmd_exec(mdev, &cmd, sizeof(cmd));
428 return PTR_ERR(context);
430 err = mlx5_fpga_ipsec_cmd_wait(context);
434 if ((context->resp.flags & cmd.flags) != cmd.flags) {
435 mlx5_fpga_err(context->dev, "Failed to set capabilities. cmd 0x%08x vs resp 0x%08x\n",
437 context->resp.flags);
446 static int mlx5_fpga_ipsec_enable_supported_caps(struct mlx5_core_dev *mdev)
448 u32 dev_caps = mlx5_fpga_ipsec_device_caps(mdev);
451 if (dev_caps & MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER)
452 flags |= MLX5_FPGA_IPSEC_CAP_NO_TRAILER;
454 return mlx5_fpga_ipsec_set_caps(mdev, flags);
458 mlx5_fpga_ipsec_build_hw_xfrm(struct mlx5_core_dev *mdev,
459 const struct mlx5_accel_esp_xfrm_attrs *xfrm_attrs,
460 struct mlx5_ifc_fpga_ipsec_sa *hw_sa)
462 const struct aes_gcm_keymat *aes_gcm = &xfrm_attrs->keymat.aes_gcm;
465 memcpy(&hw_sa->ipsec_sa_v1.key_enc, aes_gcm->aes_key,
466 aes_gcm->key_len / 8);
467 /* Duplicate 128 bit key twice according to HW layout */
468 if (aes_gcm->key_len == 128)
469 memcpy(&hw_sa->ipsec_sa_v1.key_enc[16],
470 aes_gcm->aes_key, aes_gcm->key_len / 8);
472 /* salt and seq_iv */
473 memcpy(&hw_sa->ipsec_sa_v1.gcm.salt_iv, &aes_gcm->seq_iv,
474 sizeof(aes_gcm->seq_iv));
475 memcpy(&hw_sa->ipsec_sa_v1.gcm.salt, &aes_gcm->salt,
476 sizeof(aes_gcm->salt));
479 if (xfrm_attrs->flags & MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED) {
480 hw_sa->ipsec_sa_v1.flags |= MLX5_FPGA_IPSEC_SA_ESN_EN;
481 hw_sa->ipsec_sa_v1.flags |=
483 MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP) ?
484 MLX5_FPGA_IPSEC_SA_ESN_OVERLAP : 0;
485 hw_sa->esn = htonl(xfrm_attrs->esn);
487 hw_sa->ipsec_sa_v1.flags &= ~MLX5_FPGA_IPSEC_SA_ESN_EN;
488 hw_sa->ipsec_sa_v1.flags &=
489 ~(xfrm_attrs->flags &
490 MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP) ?
491 MLX5_FPGA_IPSEC_SA_ESN_OVERLAP : 0;
496 hw_sa->ipsec_sa_v1.sw_sa_handle = htonl(xfrm_attrs->sa_handle);
499 switch (aes_gcm->key_len) {
501 hw_sa->ipsec_sa_v1.enc_mode =
502 MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_128_AUTH_128;
505 hw_sa->ipsec_sa_v1.enc_mode =
506 MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_256_AUTH_128;
511 hw_sa->ipsec_sa_v1.flags |= MLX5_FPGA_IPSEC_SA_SA_VALID |
512 MLX5_FPGA_IPSEC_SA_SPI_EN |
513 MLX5_FPGA_IPSEC_SA_IP_ESP;
515 if (xfrm_attrs->action & MLX5_ACCEL_ESP_ACTION_ENCRYPT)
516 hw_sa->ipsec_sa_v1.flags |= MLX5_FPGA_IPSEC_SA_DIR_SX;
518 hw_sa->ipsec_sa_v1.flags &= ~MLX5_FPGA_IPSEC_SA_DIR_SX;
522 mlx5_fpga_ipsec_build_hw_sa(struct mlx5_core_dev *mdev,
523 struct mlx5_accel_esp_xfrm_attrs *xfrm_attrs,
524 const __be32 saddr[4],
525 const __be32 daddr[4],
526 const __be32 spi, bool is_ipv6,
527 struct mlx5_ifc_fpga_ipsec_sa *hw_sa)
529 mlx5_fpga_ipsec_build_hw_xfrm(mdev, xfrm_attrs, hw_sa);
532 memcpy(hw_sa->ipsec_sa_v1.sip, saddr, sizeof(hw_sa->ipsec_sa_v1.sip));
533 memcpy(hw_sa->ipsec_sa_v1.dip, daddr, sizeof(hw_sa->ipsec_sa_v1.dip));
536 hw_sa->ipsec_sa_v1.spi = spi;
540 hw_sa->ipsec_sa_v1.flags |= MLX5_FPGA_IPSEC_SA_IPV6;
543 static bool is_full_mask(const void *p, size_t len)
547 return !memchr_inv(p, 0xff, len);
550 static bool validate_fpga_full_mask(struct mlx5_core_dev *dev,
554 const void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
557 const void *headers_c = MLX5_ADDR_OF(fte_match_param,
560 const void *headers_v = MLX5_ADDR_OF(fte_match_param,
564 if (mlx5_fs_is_outer_ipv4_flow(dev, headers_c, headers_v)) {
565 const void *s_ipv4_c = MLX5_ADDR_OF(fte_match_set_lyr_2_4,
567 src_ipv4_src_ipv6.ipv4_layout.ipv4);
568 const void *d_ipv4_c = MLX5_ADDR_OF(fte_match_set_lyr_2_4,
570 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
572 if (!is_full_mask(s_ipv4_c, MLX5_FLD_SZ_BYTES(ipv4_layout,
574 !is_full_mask(d_ipv4_c, MLX5_FLD_SZ_BYTES(ipv4_layout,
578 const void *s_ipv6_c = MLX5_ADDR_OF(fte_match_set_lyr_2_4,
580 src_ipv4_src_ipv6.ipv6_layout.ipv6);
581 const void *d_ipv6_c = MLX5_ADDR_OF(fte_match_set_lyr_2_4,
583 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
585 if (!is_full_mask(s_ipv6_c, MLX5_FLD_SZ_BYTES(ipv6_layout,
587 !is_full_mask(d_ipv6_c, MLX5_FLD_SZ_BYTES(ipv6_layout,
592 if (!is_full_mask(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
594 MLX5_FLD_SZ_BYTES(fte_match_set_misc, outer_esp_spi)))
600 static bool mlx5_is_fpga_ipsec_rule(struct mlx5_core_dev *dev,
601 u8 match_criteria_enable,
605 u32 ipsec_dev_caps = mlx5_accel_ipsec_device_caps(dev);
608 ipv6_flow = mlx5_fs_is_outer_ipv6_flow(dev, match_c, match_v);
610 if (!(match_criteria_enable & MLX5_MATCH_OUTER_HEADERS) ||
611 mlx5_fs_is_outer_udp_flow(match_c, match_v) ||
612 mlx5_fs_is_outer_tcp_flow(match_c, match_v) ||
613 mlx5_fs_is_vxlan_flow(match_c) ||
614 !(mlx5_fs_is_outer_ipv4_flow(dev, match_c, match_v) ||
618 if (!(ipsec_dev_caps & MLX5_ACCEL_IPSEC_CAP_DEVICE))
621 if (!(ipsec_dev_caps & MLX5_ACCEL_IPSEC_CAP_ESP) &&
622 mlx5_fs_is_outer_ipsec_flow(match_c))
625 if (!(ipsec_dev_caps & MLX5_ACCEL_IPSEC_CAP_IPV6) &&
629 if (!validate_fpga_full_mask(dev, match_c, match_v))
635 static bool mlx5_is_fpga_egress_ipsec_rule(struct mlx5_core_dev *dev,
636 u8 match_criteria_enable,
639 struct mlx5_flow_act *flow_act)
641 const void *outer_c = MLX5_ADDR_OF(fte_match_param, match_c,
643 bool is_dmac = MLX5_GET(fte_match_set_lyr_2_4, outer_c, dmac_47_16) ||
644 MLX5_GET(fte_match_set_lyr_2_4, outer_c, dmac_15_0);
645 bool is_smac = MLX5_GET(fte_match_set_lyr_2_4, outer_c, smac_47_16) ||
646 MLX5_GET(fte_match_set_lyr_2_4, outer_c, smac_15_0);
649 ret = mlx5_is_fpga_ipsec_rule(dev, match_criteria_enable, match_c,
654 if (is_dmac || is_smac ||
655 (match_criteria_enable &
656 ~(MLX5_MATCH_OUTER_HEADERS | MLX5_MATCH_MISC_PARAMETERS)) ||
657 (flow_act->action & ~(MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | MLX5_FLOW_CONTEXT_ACTION_ALLOW)) ||
658 flow_act->has_flow_tag)
664 void *mlx5_fpga_ipsec_create_sa_ctx(struct mlx5_core_dev *mdev,
665 struct mlx5_accel_esp_xfrm *accel_xfrm,
666 const __be32 saddr[4],
667 const __be32 daddr[4],
668 const __be32 spi, bool is_ipv6)
670 struct mlx5_fpga_ipsec_sa_ctx *sa_ctx;
671 struct mlx5_fpga_esp_xfrm *fpga_xfrm =
672 container_of(accel_xfrm, typeof(*fpga_xfrm),
674 struct mlx5_fpga_device *fdev = mdev->fpga;
675 struct mlx5_fpga_ipsec *fipsec = fdev->ipsec;
680 sa_ctx = kzalloc(sizeof(*sa_ctx), GFP_KERNEL);
682 return ERR_PTR(-ENOMEM);
686 /* build candidate SA */
687 mlx5_fpga_ipsec_build_hw_sa(mdev, &accel_xfrm->attrs,
688 saddr, daddr, spi, is_ipv6,
691 mutex_lock(&fpga_xfrm->lock);
693 if (fpga_xfrm->sa_ctx) { /* multiple rules for same accel_xfrm */
694 /* all rules must be with same IPs and SPI */
695 if (memcmp(&sa_ctx->hw_sa, &fpga_xfrm->sa_ctx->hw_sa,
696 sizeof(sa_ctx->hw_sa))) {
697 context = ERR_PTR(-EINVAL);
701 ++fpga_xfrm->num_rules;
702 context = fpga_xfrm->sa_ctx;
706 /* This is unbounded fpga_xfrm, try to add to hash */
707 mutex_lock(&fipsec->sa_hash_lock);
709 err = rhashtable_lookup_insert_fast(&fipsec->sa_hash, &sa_ctx->hash,
712 /* Can't bound different accel_xfrm to already existing sa_ctx.
713 * This is because we can't support multiple ketmats for
716 context = ERR_PTR(-EEXIST);
720 /* Bound accel_xfrm to sa_ctx */
721 opcode = is_v2_sadb_supported(fdev->ipsec) ?
722 MLX5_FPGA_IPSEC_CMD_OP_ADD_SA_V2 :
723 MLX5_FPGA_IPSEC_CMD_OP_ADD_SA;
724 err = mlx5_fpga_ipsec_update_hw_sa(fdev, &sa_ctx->hw_sa, opcode);
725 sa_ctx->hw_sa.ipsec_sa_v1.cmd = 0;
727 context = ERR_PTR(err);
731 mutex_unlock(&fipsec->sa_hash_lock);
733 ++fpga_xfrm->num_rules;
734 fpga_xfrm->sa_ctx = sa_ctx;
735 sa_ctx->fpga_xfrm = fpga_xfrm;
737 mutex_unlock(&fpga_xfrm->lock);
742 WARN_ON(rhashtable_remove_fast(&fipsec->sa_hash, &sa_ctx->hash,
745 mutex_unlock(&fipsec->sa_hash_lock);
748 mutex_unlock(&fpga_xfrm->lock);
754 mlx5_fpga_ipsec_fs_create_sa_ctx(struct mlx5_core_dev *mdev,
758 struct mlx5_accel_esp_xfrm *accel_xfrm;
759 __be32 saddr[4], daddr[4], spi;
760 struct mlx5_flow_group *fg;
761 bool is_ipv6 = false;
763 fs_get_obj(fg, fte->node.parent);
766 !mlx5_is_fpga_egress_ipsec_rule(mdev,
767 fg->mask.match_criteria_enable,
768 fg->mask.match_criteria,
771 return ERR_PTR(-EINVAL);
772 else if (!mlx5_is_fpga_ipsec_rule(mdev,
773 fg->mask.match_criteria_enable,
774 fg->mask.match_criteria,
776 return ERR_PTR(-EINVAL);
778 /* get xfrm context */
780 (struct mlx5_accel_esp_xfrm *)fte->action.esp_id;
783 if (mlx5_fs_is_outer_ipv4_flow(mdev, fg->mask.match_criteria,
786 MLX5_ADDR_OF(fte_match_set_lyr_2_4,
788 src_ipv4_src_ipv6.ipv4_layout.ipv4),
791 MLX5_ADDR_OF(fte_match_set_lyr_2_4,
793 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
797 MLX5_ADDR_OF(fte_match_param,
799 outer_headers.src_ipv4_src_ipv6.ipv6_layout.ipv6),
802 MLX5_ADDR_OF(fte_match_param,
804 outer_headers.dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
810 spi = MLX5_GET_BE(typeof(spi),
811 fte_match_param, fte->val,
812 misc_parameters.outer_esp_spi);
815 return mlx5_fpga_ipsec_create_sa_ctx(mdev, accel_xfrm,
821 mlx5_fpga_ipsec_release_sa_ctx(struct mlx5_fpga_ipsec_sa_ctx *sa_ctx)
823 struct mlx5_fpga_device *fdev = sa_ctx->dev->fpga;
824 struct mlx5_fpga_ipsec *fipsec = fdev->ipsec;
825 int opcode = is_v2_sadb_supported(fdev->ipsec) ?
826 MLX5_FPGA_IPSEC_CMD_OP_DEL_SA_V2 :
827 MLX5_FPGA_IPSEC_CMD_OP_DEL_SA;
830 err = mlx5_fpga_ipsec_update_hw_sa(fdev, &sa_ctx->hw_sa, opcode);
831 sa_ctx->hw_sa.ipsec_sa_v1.cmd = 0;
837 mutex_lock(&fipsec->sa_hash_lock);
838 WARN_ON(rhashtable_remove_fast(&fipsec->sa_hash, &sa_ctx->hash,
840 mutex_unlock(&fipsec->sa_hash_lock);
843 void mlx5_fpga_ipsec_delete_sa_ctx(void *context)
845 struct mlx5_fpga_esp_xfrm *fpga_xfrm =
846 ((struct mlx5_fpga_ipsec_sa_ctx *)context)->fpga_xfrm;
848 mutex_lock(&fpga_xfrm->lock);
849 if (!--fpga_xfrm->num_rules) {
850 mlx5_fpga_ipsec_release_sa_ctx(fpga_xfrm->sa_ctx);
851 kfree(fpga_xfrm->sa_ctx);
852 fpga_xfrm->sa_ctx = NULL;
854 mutex_unlock(&fpga_xfrm->lock);
857 static inline struct mlx5_fpga_ipsec_rule *
858 _rule_search(struct rb_root *root, struct fs_fte *fte)
860 struct rb_node *node = root->rb_node;
863 struct mlx5_fpga_ipsec_rule *rule =
864 container_of(node, struct mlx5_fpga_ipsec_rule,
868 node = node->rb_left;
869 else if (rule->fte > fte)
870 node = node->rb_right;
877 static struct mlx5_fpga_ipsec_rule *
878 rule_search(struct mlx5_fpga_ipsec *ipsec_dev, struct fs_fte *fte)
880 struct mlx5_fpga_ipsec_rule *rule;
882 mutex_lock(&ipsec_dev->rules_rb_lock);
883 rule = _rule_search(&ipsec_dev->rules_rb, fte);
884 mutex_unlock(&ipsec_dev->rules_rb_lock);
889 static inline int _rule_insert(struct rb_root *root,
890 struct mlx5_fpga_ipsec_rule *rule)
892 struct rb_node **new = &root->rb_node, *parent = NULL;
894 /* Figure out where to put new node */
896 struct mlx5_fpga_ipsec_rule *this =
897 container_of(*new, struct mlx5_fpga_ipsec_rule,
901 if (rule->fte < this->fte)
902 new = &((*new)->rb_left);
903 else if (rule->fte > this->fte)
904 new = &((*new)->rb_right);
909 /* Add new node and rebalance tree. */
910 rb_link_node(&rule->node, parent, new);
911 rb_insert_color(&rule->node, root);
916 static int rule_insert(struct mlx5_fpga_ipsec *ipsec_dev,
917 struct mlx5_fpga_ipsec_rule *rule)
921 mutex_lock(&ipsec_dev->rules_rb_lock);
922 ret = _rule_insert(&ipsec_dev->rules_rb, rule);
923 mutex_unlock(&ipsec_dev->rules_rb_lock);
928 static inline void _rule_delete(struct mlx5_fpga_ipsec *ipsec_dev,
929 struct mlx5_fpga_ipsec_rule *rule)
931 struct rb_root *root = &ipsec_dev->rules_rb;
933 mutex_lock(&ipsec_dev->rules_rb_lock);
934 rb_erase(&rule->node, root);
935 mutex_unlock(&ipsec_dev->rules_rb_lock);
938 static void rule_delete(struct mlx5_fpga_ipsec *ipsec_dev,
939 struct mlx5_fpga_ipsec_rule *rule)
941 _rule_delete(ipsec_dev, rule);
946 uintptr_t saved_esp_id;
948 u32 saved_outer_esp_spi_value;
951 static void restore_spec_mailbox(struct fs_fte *fte,
952 struct mailbox_mod *mbox_mod)
954 char *misc_params_v = MLX5_ADDR_OF(fte_match_param,
958 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
959 mbox_mod->saved_outer_esp_spi_value);
960 fte->action.action |= mbox_mod->saved_action;
961 fte->action.esp_id = (uintptr_t)mbox_mod->saved_esp_id;
964 static void modify_spec_mailbox(struct mlx5_core_dev *mdev,
966 struct mailbox_mod *mbox_mod)
968 char *misc_params_v = MLX5_ADDR_OF(fte_match_param,
972 mbox_mod->saved_esp_id = fte->action.esp_id;
973 mbox_mod->saved_action = fte->action.action &
974 (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
975 MLX5_FLOW_CONTEXT_ACTION_DECRYPT);
976 mbox_mod->saved_outer_esp_spi_value =
977 MLX5_GET(fte_match_set_misc, misc_params_v,
980 fte->action.esp_id = 0;
981 fte->action.action &= ~(MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
982 MLX5_FLOW_CONTEXT_ACTION_DECRYPT);
983 if (!MLX5_CAP_FLOWTABLE(mdev,
984 flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
985 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi, 0);
988 static enum fs_flow_table_type egress_to_fs_ft(bool egress)
990 return egress ? FS_FT_NIC_TX : FS_FT_NIC_RX;
993 static int fpga_ipsec_fs_create_flow_group(struct mlx5_core_dev *dev,
994 struct mlx5_flow_table *ft,
996 unsigned int *group_id,
999 int (*create_flow_group)(struct mlx5_core_dev *dev,
1000 struct mlx5_flow_table *ft, u32 *in,
1001 unsigned int *group_id) =
1002 mlx5_fs_cmd_get_default(egress_to_fs_ft(is_egress))->create_flow_group;
1003 char *misc_params_c = MLX5_ADDR_OF(create_flow_group_in, in,
1004 match_criteria.misc_parameters);
1005 u32 saved_outer_esp_spi_mask;
1006 u8 match_criteria_enable;
1009 if (MLX5_CAP_FLOWTABLE(dev,
1010 flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1011 return create_flow_group(dev, ft, in, group_id);
1013 match_criteria_enable =
1014 MLX5_GET(create_flow_group_in, in, match_criteria_enable);
1015 saved_outer_esp_spi_mask =
1016 MLX5_GET(fte_match_set_misc, misc_params_c, outer_esp_spi);
1017 if (!match_criteria_enable || !saved_outer_esp_spi_mask)
1018 return create_flow_group(dev, ft, in, group_id);
1020 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi, 0);
1022 if (!(*misc_params_c) &&
1023 !memcmp(misc_params_c, misc_params_c + 1, MLX5_ST_SZ_BYTES(fte_match_set_misc) - 1))
1024 MLX5_SET(create_flow_group_in, in, match_criteria_enable,
1025 match_criteria_enable & ~MLX5_MATCH_MISC_PARAMETERS);
1027 ret = create_flow_group(dev, ft, in, group_id);
1029 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi, saved_outer_esp_spi_mask);
1030 MLX5_SET(create_flow_group_in, in, match_criteria_enable, match_criteria_enable);
1035 static int fpga_ipsec_fs_create_fte(struct mlx5_core_dev *dev,
1036 struct mlx5_flow_table *ft,
1037 struct mlx5_flow_group *fg,
1041 int (*create_fte)(struct mlx5_core_dev *dev,
1042 struct mlx5_flow_table *ft,
1043 struct mlx5_flow_group *fg,
1044 struct fs_fte *fte) =
1045 mlx5_fs_cmd_get_default(egress_to_fs_ft(is_egress))->create_fte;
1046 struct mlx5_fpga_device *fdev = dev->fpga;
1047 struct mlx5_fpga_ipsec *fipsec = fdev->ipsec;
1048 struct mlx5_fpga_ipsec_rule *rule;
1049 bool is_esp = fte->action.esp_id;
1050 struct mailbox_mod mbox_mod;
1054 !(fte->action.action &
1055 (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
1056 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)))
1057 return create_fte(dev, ft, fg, fte);
1059 rule = kzalloc(sizeof(*rule), GFP_KERNEL);
1063 rule->ctx = mlx5_fpga_ipsec_fs_create_sa_ctx(dev, fte, is_egress);
1064 if (IS_ERR(rule->ctx)) {
1065 int err = PTR_ERR(rule->ctx);
1071 WARN_ON(rule_insert(fipsec, rule));
1073 modify_spec_mailbox(dev, fte, &mbox_mod);
1074 ret = create_fte(dev, ft, fg, fte);
1075 restore_spec_mailbox(fte, &mbox_mod);
1077 _rule_delete(fipsec, rule);
1078 mlx5_fpga_ipsec_delete_sa_ctx(rule->ctx);
1085 static int fpga_ipsec_fs_update_fte(struct mlx5_core_dev *dev,
1086 struct mlx5_flow_table *ft,
1087 unsigned int group_id,
1092 int (*update_fte)(struct mlx5_core_dev *dev,
1093 struct mlx5_flow_table *ft,
1094 unsigned int group_id,
1096 struct fs_fte *fte) =
1097 mlx5_fs_cmd_get_default(egress_to_fs_ft(is_egress))->update_fte;
1098 bool is_esp = fte->action.esp_id;
1099 struct mailbox_mod mbox_mod;
1103 !(fte->action.action &
1104 (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
1105 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)))
1106 return update_fte(dev, ft, group_id, modify_mask, fte);
1108 modify_spec_mailbox(dev, fte, &mbox_mod);
1109 ret = update_fte(dev, ft, group_id, modify_mask, fte);
1110 restore_spec_mailbox(fte, &mbox_mod);
1115 static int fpga_ipsec_fs_delete_fte(struct mlx5_core_dev *dev,
1116 struct mlx5_flow_table *ft,
1120 int (*delete_fte)(struct mlx5_core_dev *dev,
1121 struct mlx5_flow_table *ft,
1122 struct fs_fte *fte) =
1123 mlx5_fs_cmd_get_default(egress_to_fs_ft(is_egress))->delete_fte;
1124 struct mlx5_fpga_device *fdev = dev->fpga;
1125 struct mlx5_fpga_ipsec *fipsec = fdev->ipsec;
1126 struct mlx5_fpga_ipsec_rule *rule;
1127 bool is_esp = fte->action.esp_id;
1128 struct mailbox_mod mbox_mod;
1132 !(fte->action.action &
1133 (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
1134 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)))
1135 return delete_fte(dev, ft, fte);
1137 rule = rule_search(fipsec, fte);
1141 mlx5_fpga_ipsec_delete_sa_ctx(rule->ctx);
1142 rule_delete(fipsec, rule);
1144 modify_spec_mailbox(dev, fte, &mbox_mod);
1145 ret = delete_fte(dev, ft, fte);
1146 restore_spec_mailbox(fte, &mbox_mod);
1152 mlx5_fpga_ipsec_fs_create_flow_group_egress(struct mlx5_core_dev *dev,
1153 struct mlx5_flow_table *ft,
1155 unsigned int *group_id)
1157 return fpga_ipsec_fs_create_flow_group(dev, ft, in, group_id, true);
1161 mlx5_fpga_ipsec_fs_create_fte_egress(struct mlx5_core_dev *dev,
1162 struct mlx5_flow_table *ft,
1163 struct mlx5_flow_group *fg,
1166 return fpga_ipsec_fs_create_fte(dev, ft, fg, fte, true);
1170 mlx5_fpga_ipsec_fs_update_fte_egress(struct mlx5_core_dev *dev,
1171 struct mlx5_flow_table *ft,
1172 unsigned int group_id,
1176 return fpga_ipsec_fs_update_fte(dev, ft, group_id, modify_mask, fte,
1181 mlx5_fpga_ipsec_fs_delete_fte_egress(struct mlx5_core_dev *dev,
1182 struct mlx5_flow_table *ft,
1185 return fpga_ipsec_fs_delete_fte(dev, ft, fte, true);
1189 mlx5_fpga_ipsec_fs_create_flow_group_ingress(struct mlx5_core_dev *dev,
1190 struct mlx5_flow_table *ft,
1192 unsigned int *group_id)
1194 return fpga_ipsec_fs_create_flow_group(dev, ft, in, group_id, false);
1198 mlx5_fpga_ipsec_fs_create_fte_ingress(struct mlx5_core_dev *dev,
1199 struct mlx5_flow_table *ft,
1200 struct mlx5_flow_group *fg,
1203 return fpga_ipsec_fs_create_fte(dev, ft, fg, fte, false);
1207 mlx5_fpga_ipsec_fs_update_fte_ingress(struct mlx5_core_dev *dev,
1208 struct mlx5_flow_table *ft,
1209 unsigned int group_id,
1213 return fpga_ipsec_fs_update_fte(dev, ft, group_id, modify_mask, fte,
1218 mlx5_fpga_ipsec_fs_delete_fte_ingress(struct mlx5_core_dev *dev,
1219 struct mlx5_flow_table *ft,
1222 return fpga_ipsec_fs_delete_fte(dev, ft, fte, false);
1225 static struct mlx5_flow_cmds fpga_ipsec_ingress;
1226 static struct mlx5_flow_cmds fpga_ipsec_egress;
1228 const struct mlx5_flow_cmds *mlx5_fs_cmd_get_default_ipsec_fpga_cmds(enum fs_flow_table_type type)
1232 return &fpga_ipsec_ingress;
1234 return &fpga_ipsec_egress;
1241 int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev)
1243 struct mlx5_fpga_conn_attr init_attr = {0};
1244 struct mlx5_fpga_device *fdev = mdev->fpga;
1245 struct mlx5_fpga_conn *conn;
1248 if (!mlx5_fpga_is_ipsec_device(mdev))
1251 fdev->ipsec = kzalloc(sizeof(*fdev->ipsec), GFP_KERNEL);
1255 fdev->ipsec->fdev = fdev;
1257 err = mlx5_fpga_get_sbu_caps(fdev, sizeof(fdev->ipsec->caps),
1260 mlx5_fpga_err(fdev, "Failed to retrieve IPSec extended capabilities: %d\n",
1265 INIT_LIST_HEAD(&fdev->ipsec->pending_cmds);
1266 spin_lock_init(&fdev->ipsec->pending_cmds_lock);
1268 init_attr.rx_size = SBU_QP_QUEUE_SIZE;
1269 init_attr.tx_size = SBU_QP_QUEUE_SIZE;
1270 init_attr.recv_cb = mlx5_fpga_ipsec_recv;
1271 init_attr.cb_arg = fdev;
1272 conn = mlx5_fpga_sbu_conn_create(fdev, &init_attr);
1274 err = PTR_ERR(conn);
1275 mlx5_fpga_err(fdev, "Error creating IPSec command connection %d\n",
1279 fdev->ipsec->conn = conn;
1281 err = rhashtable_init(&fdev->ipsec->sa_hash, &rhash_sa);
1283 goto err_destroy_conn;
1284 mutex_init(&fdev->ipsec->sa_hash_lock);
1286 fdev->ipsec->rules_rb = RB_ROOT;
1287 mutex_init(&fdev->ipsec->rules_rb_lock);
1289 err = mlx5_fpga_ipsec_enable_supported_caps(mdev);
1291 mlx5_fpga_err(fdev, "Failed to enable IPSec extended capabilities: %d\n",
1293 goto err_destroy_hash;
1299 rhashtable_destroy(&fdev->ipsec->sa_hash);
1302 mlx5_fpga_sbu_conn_destroy(conn);
1310 static void destroy_rules_rb(struct rb_root *root)
1312 struct mlx5_fpga_ipsec_rule *r, *tmp;
1314 rbtree_postorder_for_each_entry_safe(r, tmp, root, node) {
1315 rb_erase(&r->node, root);
1316 mlx5_fpga_ipsec_delete_sa_ctx(r->ctx);
1321 void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev)
1323 struct mlx5_fpga_device *fdev = mdev->fpga;
1325 if (!mlx5_fpga_is_ipsec_device(mdev))
1328 destroy_rules_rb(&fdev->ipsec->rules_rb);
1329 rhashtable_destroy(&fdev->ipsec->sa_hash);
1331 mlx5_fpga_sbu_conn_destroy(fdev->ipsec->conn);
1336 void mlx5_fpga_ipsec_build_fs_cmds(void)
1339 fpga_ipsec_ingress.create_flow_table =
1340 mlx5_fs_cmd_get_default(egress_to_fs_ft(false))->create_flow_table;
1341 fpga_ipsec_ingress.destroy_flow_table =
1342 mlx5_fs_cmd_get_default(egress_to_fs_ft(false))->destroy_flow_table;
1343 fpga_ipsec_ingress.modify_flow_table =
1344 mlx5_fs_cmd_get_default(egress_to_fs_ft(false))->modify_flow_table;
1345 fpga_ipsec_ingress.create_flow_group =
1346 mlx5_fpga_ipsec_fs_create_flow_group_ingress;
1347 fpga_ipsec_ingress.destroy_flow_group =
1348 mlx5_fs_cmd_get_default(egress_to_fs_ft(false))->destroy_flow_group;
1349 fpga_ipsec_ingress.create_fte =
1350 mlx5_fpga_ipsec_fs_create_fte_ingress;
1351 fpga_ipsec_ingress.update_fte =
1352 mlx5_fpga_ipsec_fs_update_fte_ingress;
1353 fpga_ipsec_ingress.delete_fte =
1354 mlx5_fpga_ipsec_fs_delete_fte_ingress;
1355 fpga_ipsec_ingress.update_root_ft =
1356 mlx5_fs_cmd_get_default(egress_to_fs_ft(false))->update_root_ft;
1359 fpga_ipsec_egress.create_flow_table =
1360 mlx5_fs_cmd_get_default(egress_to_fs_ft(true))->create_flow_table;
1361 fpga_ipsec_egress.destroy_flow_table =
1362 mlx5_fs_cmd_get_default(egress_to_fs_ft(true))->destroy_flow_table;
1363 fpga_ipsec_egress.modify_flow_table =
1364 mlx5_fs_cmd_get_default(egress_to_fs_ft(true))->modify_flow_table;
1365 fpga_ipsec_egress.create_flow_group =
1366 mlx5_fpga_ipsec_fs_create_flow_group_egress;
1367 fpga_ipsec_egress.destroy_flow_group =
1368 mlx5_fs_cmd_get_default(egress_to_fs_ft(true))->destroy_flow_group;
1369 fpga_ipsec_egress.create_fte =
1370 mlx5_fpga_ipsec_fs_create_fte_egress;
1371 fpga_ipsec_egress.update_fte =
1372 mlx5_fpga_ipsec_fs_update_fte_egress;
1373 fpga_ipsec_egress.delete_fte =
1374 mlx5_fpga_ipsec_fs_delete_fte_egress;
1375 fpga_ipsec_egress.update_root_ft =
1376 mlx5_fs_cmd_get_default(egress_to_fs_ft(true))->update_root_ft;
1380 mlx5_fpga_esp_validate_xfrm_attrs(struct mlx5_core_dev *mdev,
1381 const struct mlx5_accel_esp_xfrm_attrs *attrs)
1383 if (attrs->tfc_pad) {
1384 mlx5_core_err(mdev, "Cannot offload xfrm states with tfc padding\n");
1388 if (attrs->replay_type != MLX5_ACCEL_ESP_REPLAY_NONE) {
1389 mlx5_core_err(mdev, "Cannot offload xfrm states with anti replay\n");
1393 if (attrs->keymat_type != MLX5_ACCEL_ESP_KEYMAT_AES_GCM) {
1394 mlx5_core_err(mdev, "Only aes gcm keymat is supported\n");
1398 if (attrs->keymat.aes_gcm.iv_algo !=
1399 MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ) {
1400 mlx5_core_err(mdev, "Only iv sequence algo is supported\n");
1404 if (attrs->keymat.aes_gcm.icv_len != 128) {
1405 mlx5_core_err(mdev, "Cannot offload xfrm states with AEAD ICV length other than 128bit\n");
1409 if (attrs->keymat.aes_gcm.key_len != 128 &&
1410 attrs->keymat.aes_gcm.key_len != 256) {
1411 mlx5_core_err(mdev, "Cannot offload xfrm states with AEAD key length other than 128/256 bit\n");
1415 if ((attrs->flags & MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED) &&
1416 (!MLX5_GET(ipsec_extended_cap, mdev->fpga->ipsec->caps,
1418 mlx5_core_err(mdev, "Cannot offload xfrm states with AEAD key length other than 128/256 bit\n");
1425 struct mlx5_accel_esp_xfrm *
1426 mlx5_fpga_esp_create_xfrm(struct mlx5_core_dev *mdev,
1427 const struct mlx5_accel_esp_xfrm_attrs *attrs,
1430 struct mlx5_fpga_esp_xfrm *fpga_xfrm;
1432 if (!(flags & MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA)) {
1433 mlx5_core_warn(mdev, "Tried to create an esp action without metadata\n");
1434 return ERR_PTR(-EINVAL);
1437 if (mlx5_fpga_esp_validate_xfrm_attrs(mdev, attrs)) {
1438 mlx5_core_warn(mdev, "Tried to create an esp with unsupported attrs\n");
1439 return ERR_PTR(-EOPNOTSUPP);
1442 fpga_xfrm = kzalloc(sizeof(*fpga_xfrm), GFP_KERNEL);
1444 return ERR_PTR(-ENOMEM);
1446 mutex_init(&fpga_xfrm->lock);
1447 memcpy(&fpga_xfrm->accel_xfrm.attrs, attrs,
1448 sizeof(fpga_xfrm->accel_xfrm.attrs));
1450 return &fpga_xfrm->accel_xfrm;
1453 void mlx5_fpga_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm)
1455 struct mlx5_fpga_esp_xfrm *fpga_xfrm =
1456 container_of(xfrm, struct mlx5_fpga_esp_xfrm,
1458 /* assuming no sa_ctx are connected to this xfrm_ctx */
1462 int mlx5_fpga_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
1463 const struct mlx5_accel_esp_xfrm_attrs *attrs)
1465 struct mlx5_core_dev *mdev = xfrm->mdev;
1466 struct mlx5_fpga_device *fdev = mdev->fpga;
1467 struct mlx5_fpga_ipsec *fipsec = fdev->ipsec;
1468 struct mlx5_fpga_esp_xfrm *fpga_xfrm;
1469 struct mlx5_ifc_fpga_ipsec_sa org_hw_sa;
1473 if (!memcmp(&xfrm->attrs, attrs, sizeof(xfrm->attrs)))
1476 if (mlx5_fpga_esp_validate_xfrm_attrs(mdev, attrs)) {
1477 mlx5_core_warn(mdev, "Tried to create an esp with unsupported attrs\n");
1481 if (is_v2_sadb_supported(fipsec)) {
1482 mlx5_core_warn(mdev, "Modify esp is not supported\n");
1486 fpga_xfrm = container_of(xfrm, struct mlx5_fpga_esp_xfrm, accel_xfrm);
1488 mutex_lock(&fpga_xfrm->lock);
1490 if (!fpga_xfrm->sa_ctx)
1491 /* Unbounded xfrm, chane only sw attrs */
1492 goto change_sw_xfrm_attrs;
1494 /* copy original hw sa */
1495 memcpy(&org_hw_sa, &fpga_xfrm->sa_ctx->hw_sa, sizeof(org_hw_sa));
1496 mutex_lock(&fipsec->sa_hash_lock);
1497 /* remove original hw sa from hash */
1498 WARN_ON(rhashtable_remove_fast(&fipsec->sa_hash,
1499 &fpga_xfrm->sa_ctx->hash, rhash_sa));
1500 /* update hw_sa with new xfrm attrs*/
1501 mlx5_fpga_ipsec_build_hw_xfrm(xfrm->mdev, attrs,
1502 &fpga_xfrm->sa_ctx->hw_sa);
1503 /* try to insert new hw_sa to hash */
1504 err = rhashtable_insert_fast(&fipsec->sa_hash,
1505 &fpga_xfrm->sa_ctx->hash, rhash_sa);
1509 /* modify device with new hw_sa */
1510 err = mlx5_fpga_ipsec_update_hw_sa(fdev, &fpga_xfrm->sa_ctx->hw_sa,
1511 MLX5_FPGA_IPSEC_CMD_OP_MOD_SA_V2);
1512 fpga_xfrm->sa_ctx->hw_sa.ipsec_sa_v1.cmd = 0;
1514 WARN_ON(rhashtable_remove_fast(&fipsec->sa_hash,
1515 &fpga_xfrm->sa_ctx->hash,
1519 /* return original hw_sa to hash */
1520 memcpy(&fpga_xfrm->sa_ctx->hw_sa, &org_hw_sa,
1522 WARN_ON(rhashtable_insert_fast(&fipsec->sa_hash,
1523 &fpga_xfrm->sa_ctx->hash,
1526 mutex_unlock(&fipsec->sa_hash_lock);
1528 change_sw_xfrm_attrs:
1530 memcpy(&xfrm->attrs, attrs, sizeof(xfrm->attrs));
1531 mutex_unlock(&fpga_xfrm->lock);