2 * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
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6 * General Public License (GPL) Version 2, available from the file
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11 * without modification, are permitted provided that the following
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15 * copyright notice, this list of conditions and the following
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23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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34 #include <linux/mlx5/driver.h>
36 #include "mlx5_core.h"
37 #include "fpga/ipsec.h"
39 #include "fpga/core.h"
41 #define SBU_QP_QUEUE_SIZE 8
43 enum mlx5_ipsec_response_syndrome {
44 MLX5_IPSEC_RESPONSE_SUCCESS = 0,
45 MLX5_IPSEC_RESPONSE_ILLEGAL_REQUEST = 1,
46 MLX5_IPSEC_RESPONSE_SADB_ISSUE = 2,
47 MLX5_IPSEC_RESPONSE_WRITE_RESPONSE_ISSUE = 3,
50 enum mlx5_fpga_ipsec_sacmd_status {
51 MLX5_FPGA_IPSEC_SACMD_PENDING,
52 MLX5_FPGA_IPSEC_SACMD_SEND_FAIL,
53 MLX5_FPGA_IPSEC_SACMD_COMPLETE,
56 struct mlx5_ipsec_command_context {
57 struct mlx5_fpga_dma_buf buf;
58 struct mlx5_accel_ipsec_sa sa;
59 enum mlx5_fpga_ipsec_sacmd_status status;
61 struct completion complete;
62 struct mlx5_fpga_device *dev;
63 struct list_head list; /* Item in pending_cmds */
66 struct mlx5_ipsec_sadb_resp {
72 struct mlx5_fpga_ipsec {
73 struct list_head pending_cmds;
74 spinlock_t pending_cmds_lock; /* Protects pending_cmds */
75 u32 caps[MLX5_ST_SZ_DW(ipsec_extended_cap)];
76 struct mlx5_fpga_conn *conn;
79 static bool mlx5_fpga_is_ipsec_device(struct mlx5_core_dev *mdev)
81 if (!mdev->fpga || !MLX5_CAP_GEN(mdev, fpga))
84 if (MLX5_CAP_FPGA(mdev, ieee_vendor_id) !=
85 MLX5_FPGA_CAP_SANDBOX_VENDOR_ID_MLNX)
88 if (MLX5_CAP_FPGA(mdev, sandbox_product_id) !=
89 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_IPSEC)
95 static void mlx5_fpga_ipsec_send_complete(struct mlx5_fpga_conn *conn,
96 struct mlx5_fpga_device *fdev,
97 struct mlx5_fpga_dma_buf *buf,
100 struct mlx5_ipsec_command_context *context;
103 context = container_of(buf, struct mlx5_ipsec_command_context,
105 mlx5_fpga_warn(fdev, "IPSec command send failed with status %u\n",
107 context->status = MLX5_FPGA_IPSEC_SACMD_SEND_FAIL;
108 complete(&context->complete);
112 static inline int syndrome_to_errno(enum mlx5_ipsec_response_syndrome syndrome)
115 case MLX5_IPSEC_RESPONSE_SUCCESS:
117 case MLX5_IPSEC_RESPONSE_SADB_ISSUE:
119 case MLX5_IPSEC_RESPONSE_ILLEGAL_REQUEST:
121 case MLX5_IPSEC_RESPONSE_WRITE_RESPONSE_ISSUE:
127 static void mlx5_fpga_ipsec_recv(void *cb_arg, struct mlx5_fpga_dma_buf *buf)
129 struct mlx5_ipsec_sadb_resp *resp = buf->sg[0].data;
130 struct mlx5_ipsec_command_context *context;
131 enum mlx5_ipsec_response_syndrome syndrome;
132 struct mlx5_fpga_device *fdev = cb_arg;
135 if (buf->sg[0].size < sizeof(*resp)) {
136 mlx5_fpga_warn(fdev, "Short receive from FPGA IPSec: %u < %zu bytes\n",
137 buf->sg[0].size, sizeof(*resp));
141 mlx5_fpga_dbg(fdev, "mlx5_ipsec recv_cb syndrome %08x sa_id %x\n",
142 ntohl(resp->syndrome), ntohl(resp->sw_sa_handle));
144 spin_lock_irqsave(&fdev->ipsec->pending_cmds_lock, flags);
145 context = list_first_entry_or_null(&fdev->ipsec->pending_cmds,
146 struct mlx5_ipsec_command_context,
149 list_del(&context->list);
150 spin_unlock_irqrestore(&fdev->ipsec->pending_cmds_lock, flags);
153 mlx5_fpga_warn(fdev, "Received IPSec offload response without pending command request\n");
156 mlx5_fpga_dbg(fdev, "Handling response for %p\n", context);
158 if (context->sa.sw_sa_handle != resp->sw_sa_handle) {
159 mlx5_fpga_err(fdev, "mismatch SA handle. cmd 0x%08x vs resp 0x%08x\n",
160 ntohl(context->sa.sw_sa_handle),
161 ntohl(resp->sw_sa_handle));
165 syndrome = ntohl(resp->syndrome);
166 context->status_code = syndrome_to_errno(syndrome);
167 context->status = MLX5_FPGA_IPSEC_SACMD_COMPLETE;
169 if (context->status_code)
170 mlx5_fpga_warn(fdev, "IPSec SADB command failed with syndrome %08x\n",
172 complete(&context->complete);
175 void *mlx5_fpga_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev,
176 struct mlx5_accel_ipsec_sa *cmd)
178 struct mlx5_ipsec_command_context *context;
179 struct mlx5_fpga_device *fdev = mdev->fpga;
183 BUILD_BUG_ON((sizeof(struct mlx5_accel_ipsec_sa) & 3) != 0);
184 if (!fdev || !fdev->ipsec)
185 return ERR_PTR(-EOPNOTSUPP);
187 context = kzalloc(sizeof(*context), GFP_ATOMIC);
189 return ERR_PTR(-ENOMEM);
191 memcpy(&context->sa, cmd, sizeof(*cmd));
192 context->buf.complete = mlx5_fpga_ipsec_send_complete;
193 context->buf.sg[0].size = sizeof(context->sa);
194 context->buf.sg[0].data = &context->sa;
195 init_completion(&context->complete);
197 spin_lock_irqsave(&fdev->ipsec->pending_cmds_lock, flags);
198 list_add_tail(&context->list, &fdev->ipsec->pending_cmds);
199 spin_unlock_irqrestore(&fdev->ipsec->pending_cmds_lock, flags);
201 context->status = MLX5_FPGA_IPSEC_SACMD_PENDING;
203 res = mlx5_fpga_sbu_conn_sendmsg(fdev->ipsec->conn, &context->buf);
205 mlx5_fpga_warn(fdev, "Failure sending IPSec command: %d\n",
207 spin_lock_irqsave(&fdev->ipsec->pending_cmds_lock, flags);
208 list_del(&context->list);
209 spin_unlock_irqrestore(&fdev->ipsec->pending_cmds_lock, flags);
213 /* Context will be freed by wait func after completion */
217 int mlx5_fpga_ipsec_sa_cmd_wait(void *ctx)
219 struct mlx5_ipsec_command_context *context = ctx;
222 res = wait_for_completion_killable(&context->complete);
224 mlx5_fpga_warn(context->dev, "Failure waiting for IPSec command response\n");
228 if (context->status == MLX5_FPGA_IPSEC_SACMD_COMPLETE)
229 res = context->status_code;
237 u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev)
239 struct mlx5_fpga_device *fdev = mdev->fpga;
242 if (mlx5_fpga_is_ipsec_device(mdev))
243 ret |= MLX5_ACCEL_IPSEC_DEVICE;
250 if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, esp))
251 ret |= MLX5_ACCEL_IPSEC_ESP;
253 if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, ipv6))
254 ret |= MLX5_ACCEL_IPSEC_IPV6;
256 if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, lso))
257 ret |= MLX5_ACCEL_IPSEC_LSO;
262 unsigned int mlx5_fpga_ipsec_counters_count(struct mlx5_core_dev *mdev)
264 struct mlx5_fpga_device *fdev = mdev->fpga;
266 if (!fdev || !fdev->ipsec)
269 return MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps,
270 number_of_ipsec_counters);
273 int mlx5_fpga_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
274 unsigned int counters_count)
276 struct mlx5_fpga_device *fdev = mdev->fpga;
283 if (!fdev || !fdev->ipsec)
286 addr = (u64)MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps,
287 ipsec_counters_addr_low) +
288 ((u64)MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps,
289 ipsec_counters_addr_high) << 32);
291 count = mlx5_fpga_ipsec_counters_count(mdev);
293 data = kzalloc(sizeof(*data) * count * 2, GFP_KERNEL);
299 ret = mlx5_fpga_mem_read(fdev, count * sizeof(u64), addr, data,
300 MLX5_FPGA_ACCESS_TYPE_DONTCARE);
302 mlx5_fpga_err(fdev, "Failed to read IPSec counters from HW: %d\n",
308 if (count > counters_count)
309 count = counters_count;
311 /* Each counter is low word, then high. But each word is big-endian */
312 for (i = 0; i < count; i++)
313 counters[i] = (u64)ntohl(data[i * 2]) |
314 ((u64)ntohl(data[i * 2 + 1]) << 32);
321 int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev)
323 struct mlx5_fpga_conn_attr init_attr = {0};
324 struct mlx5_fpga_device *fdev = mdev->fpga;
325 struct mlx5_fpga_conn *conn;
328 if (!mlx5_fpga_is_ipsec_device(mdev))
331 fdev->ipsec = kzalloc(sizeof(*fdev->ipsec), GFP_KERNEL);
335 err = mlx5_fpga_get_sbu_caps(fdev, sizeof(fdev->ipsec->caps),
338 mlx5_fpga_err(fdev, "Failed to retrieve IPSec extended capabilities: %d\n",
343 INIT_LIST_HEAD(&fdev->ipsec->pending_cmds);
344 spin_lock_init(&fdev->ipsec->pending_cmds_lock);
346 init_attr.rx_size = SBU_QP_QUEUE_SIZE;
347 init_attr.tx_size = SBU_QP_QUEUE_SIZE;
348 init_attr.recv_cb = mlx5_fpga_ipsec_recv;
349 init_attr.cb_arg = fdev;
350 conn = mlx5_fpga_sbu_conn_create(fdev, &init_attr);
353 mlx5_fpga_err(fdev, "Error creating IPSec command connection %d\n",
357 fdev->ipsec->conn = conn;
366 void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev)
368 struct mlx5_fpga_device *fdev = mdev->fpga;
370 if (!mlx5_fpga_is_ipsec_device(mdev))
373 mlx5_fpga_sbu_conn_destroy(fdev->ipsec->conn);