2 * Copyright (c) 2017, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/etherdevice.h>
34 #include <linux/mlx5/cmd.h>
35 #include <linux/mlx5/driver.h>
36 #include <linux/mlx5/device.h>
38 #include "mlx5_core.h"
41 #define MLX5_FPGA_ACCESS_REG_SZ (MLX5_ST_SZ_DW(fpga_access_reg) + \
42 MLX5_FPGA_ACCESS_REG_SIZE_MAX)
44 int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
45 void *buf, bool write)
47 u32 in[MLX5_FPGA_ACCESS_REG_SZ] = {0};
48 u32 out[MLX5_FPGA_ACCESS_REG_SZ];
55 if (size > MLX5_FPGA_ACCESS_REG_SIZE_MAX)
58 MLX5_SET(fpga_access_reg, in, size, size);
59 MLX5_SET64(fpga_access_reg, in, address, addr);
61 memcpy(MLX5_ADDR_OF(fpga_access_reg, in, data), buf, size);
63 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
64 MLX5_REG_FPGA_ACCESS_REG, 0, write);
69 memcpy(buf, MLX5_ADDR_OF(fpga_access_reg, out, data), size);
74 int mlx5_fpga_caps(struct mlx5_core_dev *dev)
76 u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0};
78 return mlx5_core_access_reg(dev, in, sizeof(in), dev->caps.fpga,
79 MLX5_ST_SZ_BYTES(fpga_cap),
80 MLX5_REG_FPGA_CAP, 0, 0);
83 int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op)
85 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
86 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
88 MLX5_SET(fpga_ctrl, in, operation, op);
90 return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
91 MLX5_REG_FPGA_CTRL, 0, true);
94 int mlx5_fpga_sbu_caps(struct mlx5_core_dev *dev, void *caps, int size)
96 unsigned int cap_size = MLX5_CAP_FPGA(dev, sandbox_extended_caps_len);
97 u64 addr = MLX5_CAP64_FPGA(dev, sandbox_extended_caps_addr);
101 if (cap_size > size) {
102 mlx5_core_warn(dev, "Not enough buffer %u for FPGA SBU caps %u",
107 while (cap_size > 0) {
108 read = min_t(unsigned int, cap_size,
109 MLX5_FPGA_ACCESS_REG_SIZE_MAX);
111 ret = mlx5_fpga_access_reg(dev, read, addr, caps, false);
113 mlx5_core_warn(dev, "Error reading FPGA SBU caps %u bytes at address 0x%llx: %d",
126 int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query)
128 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
129 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
132 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
133 MLX5_REG_FPGA_CTRL, 0, false);
137 query->status = MLX5_GET(fpga_ctrl, out, status);
138 query->admin_image = MLX5_GET(fpga_ctrl, out, flash_select_admin);
139 query->oper_image = MLX5_GET(fpga_ctrl, out, flash_select_oper);
143 int mlx5_fpga_create_qp(struct mlx5_core_dev *dev, void *fpga_qpc,
146 u32 in[MLX5_ST_SZ_DW(fpga_create_qp_in)] = {0};
147 u32 out[MLX5_ST_SZ_DW(fpga_create_qp_out)];
150 MLX5_SET(fpga_create_qp_in, in, opcode, MLX5_CMD_OP_FPGA_CREATE_QP);
151 memcpy(MLX5_ADDR_OF(fpga_create_qp_in, in, fpga_qpc), fpga_qpc,
152 MLX5_FLD_SZ_BYTES(fpga_create_qp_in, fpga_qpc));
154 ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
158 memcpy(fpga_qpc, MLX5_ADDR_OF(fpga_create_qp_out, out, fpga_qpc),
159 MLX5_FLD_SZ_BYTES(fpga_create_qp_out, fpga_qpc));
160 *fpga_qpn = MLX5_GET(fpga_create_qp_out, out, fpga_qpn);
164 int mlx5_fpga_modify_qp(struct mlx5_core_dev *dev, u32 fpga_qpn,
165 enum mlx5_fpga_qpc_field_select fields,
168 u32 in[MLX5_ST_SZ_DW(fpga_modify_qp_in)] = {0};
169 u32 out[MLX5_ST_SZ_DW(fpga_modify_qp_out)];
171 MLX5_SET(fpga_modify_qp_in, in, opcode, MLX5_CMD_OP_FPGA_MODIFY_QP);
172 MLX5_SET(fpga_modify_qp_in, in, field_select, fields);
173 MLX5_SET(fpga_modify_qp_in, in, fpga_qpn, fpga_qpn);
174 memcpy(MLX5_ADDR_OF(fpga_modify_qp_in, in, fpga_qpc), fpga_qpc,
175 MLX5_FLD_SZ_BYTES(fpga_modify_qp_in, fpga_qpc));
177 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
180 int mlx5_fpga_query_qp(struct mlx5_core_dev *dev,
181 u32 fpga_qpn, void *fpga_qpc)
183 u32 in[MLX5_ST_SZ_DW(fpga_query_qp_in)] = {0};
184 u32 out[MLX5_ST_SZ_DW(fpga_query_qp_out)];
187 MLX5_SET(fpga_query_qp_in, in, opcode, MLX5_CMD_OP_FPGA_QUERY_QP);
188 MLX5_SET(fpga_query_qp_in, in, fpga_qpn, fpga_qpn);
190 ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
194 memcpy(fpga_qpc, MLX5_ADDR_OF(fpga_query_qp_out, out, fpga_qpc),
195 MLX5_FLD_SZ_BYTES(fpga_query_qp_out, fpga_qpc));
199 int mlx5_fpga_destroy_qp(struct mlx5_core_dev *dev, u32 fpga_qpn)
201 u32 in[MLX5_ST_SZ_DW(fpga_destroy_qp_in)] = {0};
202 u32 out[MLX5_ST_SZ_DW(fpga_destroy_qp_out)];
204 MLX5_SET(fpga_destroy_qp_in, in, opcode, MLX5_CMD_OP_FPGA_DESTROY_QP);
205 MLX5_SET(fpga_destroy_qp_in, in, fpga_qpn, fpga_qpn);
207 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
210 int mlx5_fpga_query_qp_counters(struct mlx5_core_dev *dev, u32 fpga_qpn,
211 bool clear, struct mlx5_fpga_qp_counters *data)
213 u32 in[MLX5_ST_SZ_DW(fpga_query_qp_counters_in)] = {0};
214 u32 out[MLX5_ST_SZ_DW(fpga_query_qp_counters_out)];
217 MLX5_SET(fpga_query_qp_counters_in, in, opcode,
218 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS);
219 MLX5_SET(fpga_query_qp_counters_in, in, clear, clear);
220 MLX5_SET(fpga_query_qp_counters_in, in, fpga_qpn, fpga_qpn);
222 ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
226 data->rx_ack_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
228 data->rx_send_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
230 data->tx_ack_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
232 data->tx_send_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
234 data->rx_total_drop = MLX5_GET64(fpga_query_qp_counters_out, out,