drivers/net/ethernet/mellanox/mlx5/core/eq.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/interrupt.h>
  34 #include <linux/module.h>
  35 #include <linux/mlx5/driver.h>
  36 #include <linux/mlx5/cmd.h>
  37 #include "mlx5_core.h"
  38 #include "fpga/core.h"
  39 #include "eswitch.h"
  40
  41 enum {
  42         MLX5_EQE_SIZE           = sizeof(struct mlx5_eqe),
  43         MLX5_EQE_OWNER_INIT_VAL = 0x1,
  44 };
  45
  46 enum {
  47         MLX5_EQ_STATE_ARMED             = 0x9,
  48         MLX5_EQ_STATE_FIRED             = 0xa,
  49         MLX5_EQ_STATE_ALWAYS_ARMED      = 0xb,
  50 };
  51
  52 enum {
  53         MLX5_NUM_SPARE_EQE      = 0x80,
  54         MLX5_NUM_ASYNC_EQE      = 0x100,
  55         MLX5_NUM_CMD_EQE        = 32,
  56         MLX5_NUM_PF_DRAIN       = 64,
  57 };
  58
  59 enum {
  60         MLX5_EQ_DOORBEL_OFFSET  = 0x40,
  61 };
  62
  63 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG)           | \
  64                                (1ull << MLX5_EVENT_TYPE_COMM_EST)           | \
  65                                (1ull << MLX5_EVENT_TYPE_SQ_DRAINED)         | \
  66                                (1ull << MLX5_EVENT_TYPE_CQ_ERROR)           | \
  67                                (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR)     | \
  68                                (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED)    | \
  69                                (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
  70                                (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR)    | \
  71                                (1ull << MLX5_EVENT_TYPE_PORT_CHANGE)        | \
  72                                (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR)    | \
  73                                (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE)       | \
  74                                (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
  75
  76 struct map_eq_in {
  77         u64     mask;
  78         u32     reserved;
  79         u32     unmap_eqn;
  80 };
  81
  82 struct cre_des_eq {
  83         u8      reserved[15];
  84         u8      eqn;
  85 };
  86
  87 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
  88 {
  89         u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0};
  90         u32 in[MLX5_ST_SZ_DW(destroy_eq_in)]   = {0};
  91
  92         MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
  93         MLX5_SET(destroy_eq_in, in, eq_number, eqn);
  94         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
  95 }
  96
  97 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
  98 {
  99         return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
 100 }
 101
 102 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
 103 {
 104         struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
 105
 106         return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
 107 }
 108
 109 static const char *eqe_type_str(u8 type)
 110 {
 111         switch (type) {
 112         case MLX5_EVENT_TYPE_COMP:
 113                 return "MLX5_EVENT_TYPE_COMP";
 114         case MLX5_EVENT_TYPE_PATH_MIG:
 115                 return "MLX5_EVENT_TYPE_PATH_MIG";
 116         case MLX5_EVENT_TYPE_COMM_EST:
 117                 return "MLX5_EVENT_TYPE_COMM_EST";
 118         case MLX5_EVENT_TYPE_SQ_DRAINED:
 119                 return "MLX5_EVENT_TYPE_SQ_DRAINED";
 120         case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 121                 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
 122         case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
 123                 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
 124         case MLX5_EVENT_TYPE_CQ_ERROR:
 125                 return "MLX5_EVENT_TYPE_CQ_ERROR";
 126         case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 127                 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
 128         case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 129                 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
 130         case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 131                 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
 132         case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 133                 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
 134         case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
 135                 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
 136         case MLX5_EVENT_TYPE_INTERNAL_ERROR:
 137                 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
 138         case MLX5_EVENT_TYPE_PORT_CHANGE:
 139                 return "MLX5_EVENT_TYPE_PORT_CHANGE";
 140         case MLX5_EVENT_TYPE_GPIO_EVENT:
 141                 return "MLX5_EVENT_TYPE_GPIO_EVENT";
 142         case MLX5_EVENT_TYPE_PORT_MODULE_EVENT:
 143                 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT";
 144         case MLX5_EVENT_TYPE_REMOTE_CONFIG:
 145                 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
 146         case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
 147                 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
 148         case MLX5_EVENT_TYPE_STALL_EVENT:
 149                 return "MLX5_EVENT_TYPE_STALL_EVENT";
 150         case MLX5_EVENT_TYPE_CMD:
 151                 return "MLX5_EVENT_TYPE_CMD";
 152         case MLX5_EVENT_TYPE_PAGE_REQUEST:
 153                 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
 154         case MLX5_EVENT_TYPE_PAGE_FAULT:
 155                 return "MLX5_EVENT_TYPE_PAGE_FAULT";
 156         case MLX5_EVENT_TYPE_PPS_EVENT:
 157                 return "MLX5_EVENT_TYPE_PPS_EVENT";
 158         case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
 159                 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";
 160         case MLX5_EVENT_TYPE_FPGA_ERROR:
 161                 return "MLX5_EVENT_TYPE_FPGA_ERROR";
 162         case MLX5_EVENT_TYPE_GENERAL_EVENT:
 163                 return "MLX5_EVENT_TYPE_GENERAL_EVENT";
 164         default:
 165                 return "Unrecognized event";
 166         }
 167 }
 168
 169 static enum mlx5_dev_event port_subtype_event(u8 subtype)
 170 {
 171         switch (subtype) {
 172         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 173                 return MLX5_DEV_EVENT_PORT_DOWN;
 174         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 175                 return MLX5_DEV_EVENT_PORT_UP;
 176         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
 177                 return MLX5_DEV_EVENT_PORT_INITIALIZED;
 178         case MLX5_PORT_CHANGE_SUBTYPE_LID:
 179                 return MLX5_DEV_EVENT_LID_CHANGE;
 180         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
 181                 return MLX5_DEV_EVENT_PKEY_CHANGE;
 182         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
 183                 return MLX5_DEV_EVENT_GUID_CHANGE;
 184         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
 185                 return MLX5_DEV_EVENT_CLIENT_REREG;
 186         }
 187         return -1;
 188 }
 189
 190 static void eq_update_ci(struct mlx5_eq *eq, int arm)
 191 {
 192         __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
 193         u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
 194
 195         __raw_writel((__force u32)cpu_to_be32(val), addr);
 196         /* We still want ordering, just not swabbing, so add a barrier */
 197         mb();
 198 }
 199
 200 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 201 static void eqe_pf_action(struct work_struct *work)
 202 {
 203         struct mlx5_pagefault *pfault = container_of(work,
 204                                                      struct mlx5_pagefault,
 205                                                      work);
 206         struct mlx5_eq *eq = pfault->eq;
 207
 208         mlx5_core_page_fault(eq->dev, pfault);
 209         mempool_free(pfault, eq->pf_ctx.pool);
 210 }
 211
 212 static void eq_pf_process(struct mlx5_eq *eq)
 213 {
 214         struct mlx5_core_dev *dev = eq->dev;
 215         struct mlx5_eqe_page_fault *pf_eqe;
 216         struct mlx5_pagefault *pfault;
 217         struct mlx5_eqe *eqe;
 218         int set_ci = 0;
 219
 220         while ((eqe = next_eqe_sw(eq))) {
 221                 pfault = mempool_alloc(eq->pf_ctx.pool, GFP_ATOMIC);
 222                 if (!pfault) {
 223                         schedule_work(&eq->pf_ctx.work);
 224                         break;
 225                 }
 226
 227                 dma_rmb();
 228                 pf_eqe = &eqe->data.page_fault;
 229                 pfault->event_subtype = eqe->sub_type;
 230                 pfault->bytes_committed = be32_to_cpu(pf_eqe->bytes_committed);
 231
 232                 mlx5_core_dbg(dev,
 233                               "PAGE_FAULT: subtype: 0x%02x, bytes_committed: 0x%06x\n",
 234                               eqe->sub_type, pfault->bytes_committed);
 235
 236                 switch (eqe->sub_type) {
 237                 case MLX5_PFAULT_SUBTYPE_RDMA:
 238                         /* RDMA based event */
 239                         pfault->type =
 240                                 be32_to_cpu(pf_eqe->rdma.pftype_token) >> 24;
 241                         pfault->token =
 242                                 be32_to_cpu(pf_eqe->rdma.pftype_token) &
 243                                 MLX5_24BIT_MASK;
 244                         pfault->rdma.r_key =
 245                                 be32_to_cpu(pf_eqe->rdma.r_key);
 246                         pfault->rdma.packet_size =
 247                                 be16_to_cpu(pf_eqe->rdma.packet_length);
 248                         pfault->rdma.rdma_op_len =
 249                                 be32_to_cpu(pf_eqe->rdma.rdma_op_len);
 250                         pfault->rdma.rdma_va =
 251                                 be64_to_cpu(pf_eqe->rdma.rdma_va);
 252                         mlx5_core_dbg(dev,
 253                                       "PAGE_FAULT: type:0x%x, token: 0x%06x, r_key: 0x%08x\n",
 254                                       pfault->type, pfault->token,
 255                                       pfault->rdma.r_key);
 256                         mlx5_core_dbg(dev,
 257                                       "PAGE_FAULT: rdma_op_len: 0x%08x, rdma_va: 0x%016llx\n",
 258                                       pfault->rdma.rdma_op_len,
 259                                       pfault->rdma.rdma_va);
 260                         break;
 261
 262                 case MLX5_PFAULT_SUBTYPE_WQE:
 263                         /* WQE based event */
 264                         pfault->type =
 265                                 (be32_to_cpu(pf_eqe->wqe.pftype_wq) >> 24) & 0x7;
 266                         pfault->token =
 267                                 be32_to_cpu(pf_eqe->wqe.token);
 268                         pfault->wqe.wq_num =
 269                                 be32_to_cpu(pf_eqe->wqe.pftype_wq) &
 270                                 MLX5_24BIT_MASK;
 271                         pfault->wqe.wqe_index =
 272                                 be16_to_cpu(pf_eqe->wqe.wqe_index);
 273                         pfault->wqe.packet_size =
 274                                 be16_to_cpu(pf_eqe->wqe.packet_length);
 275                         mlx5_core_dbg(dev,
 276                                       "PAGE_FAULT: type:0x%x, token: 0x%06x, wq_num: 0x%06x, wqe_index: 0x%04x\n",
 277                                       pfault->type, pfault->token,
 278                                       pfault->wqe.wq_num,
 279                                       pfault->wqe.wqe_index);
 280                         break;
 281
 282                 default:
 283                         mlx5_core_warn(dev,
 284                                        "Unsupported page fault event sub-type: 0x%02hhx\n",
 285                                        eqe->sub_type);
 286                         /* Unsupported page faults should still be
 287                          * resolved by the page fault handler
 288                          */
 289                 }
 290
 291                 pfault->eq = eq;
 292                 INIT_WORK(&pfault->work, eqe_pf_action);
 293                 queue_work(eq->pf_ctx.wq, &pfault->work);
 294
 295                 ++eq->cons_index;
 296                 ++set_ci;
 297
 298                 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
 299                         eq_update_ci(eq, 0);
 300                         set_ci = 0;
 301                 }
 302         }
 303
 304         eq_update_ci(eq, 1);
 305 }
 306
 307 static irqreturn_t mlx5_eq_pf_int(int irq, void *eq_ptr)
 308 {
 309         struct mlx5_eq *eq = eq_ptr;
 310         unsigned long flags;
 311
 312         if (spin_trylock_irqsave(&eq->pf_ctx.lock, flags)) {
 313                 eq_pf_process(eq);
 314                 spin_unlock_irqrestore(&eq->pf_ctx.lock, flags);
 315         } else {
 316                 schedule_work(&eq->pf_ctx.work);
 317         }
 318
 319         return IRQ_HANDLED;
 320 }
 321
 322 /* mempool_refill() was proposed but unfortunately wasn't accepted
 323  * http://lkml.iu.edu/hypermail/linux/kernel/1512.1/05073.html
 324  * Chip workaround.
 325  */
 326 static void mempool_refill(mempool_t *pool)
 327 {
 328         while (pool->curr_nr < pool->min_nr)
 329                 mempool_free(mempool_alloc(pool, GFP_KERNEL), pool);
 330 }
 331
 332 static void eq_pf_action(struct work_struct *work)
 333 {
 334         struct mlx5_eq *eq = container_of(work, struct mlx5_eq, pf_ctx.work);
 335
 336         mempool_refill(eq->pf_ctx.pool);
 337
 338         spin_lock_irq(&eq->pf_ctx.lock);
 339         eq_pf_process(eq);
 340         spin_unlock_irq(&eq->pf_ctx.lock);
 341 }
 342
 343 static int init_pf_ctx(struct mlx5_eq_pagefault *pf_ctx, const char *name)
 344 {
 345         spin_lock_init(&pf_ctx->lock);
 346         INIT_WORK(&pf_ctx->work, eq_pf_action);
 347
 348         pf_ctx->wq = alloc_ordered_workqueue(name,
 349                                              WQ_MEM_RECLAIM);
 350         if (!pf_ctx->wq)
 351                 return -ENOMEM;
 352
 353         pf_ctx->pool = mempool_create_kmalloc_pool
 354                 (MLX5_NUM_PF_DRAIN, sizeof(struct mlx5_pagefault));
 355         if (!pf_ctx->pool)
 356                 goto err_wq;
 357
 358         return 0;
 359 err_wq:
 360         destroy_workqueue(pf_ctx->wq);
 361         return -ENOMEM;
 362 }
 363
 364 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
 365                                 u32 wq_num, u8 type, int error)
 366 {
 367         u32 out[MLX5_ST_SZ_DW(page_fault_resume_out)] = {0};
 368         u32 in[MLX5_ST_SZ_DW(page_fault_resume_in)]   = {0};
 369
 370         MLX5_SET(page_fault_resume_in, in, opcode,
 371                  MLX5_CMD_OP_PAGE_FAULT_RESUME);
 372         MLX5_SET(page_fault_resume_in, in, error, !!error);
 373         MLX5_SET(page_fault_resume_in, in, page_fault_type, type);
 374         MLX5_SET(page_fault_resume_in, in, wq_number, wq_num);
 375         MLX5_SET(page_fault_resume_in, in, token, token);
 376
 377         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 378 }
 379 EXPORT_SYMBOL_GPL(mlx5_core_page_fault_resume);
 380 #endif
 381
 382 static void general_event_handler(struct mlx5_core_dev *dev,
 383                                   struct mlx5_eqe *eqe)
 384 {
 385         switch (eqe->sub_type) {
 386         case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
 387                 if (dev->event)
 388                         dev->event(dev, MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT, 0);
 389                 break;
 390         default:
 391                 mlx5_core_dbg(dev, "General event with unrecognized subtype: sub_type %d\n",
 392                               eqe->sub_type);
 393         }
 394 }
 395
 396 static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr)
 397 {
 398         struct mlx5_eq *eq = eq_ptr;
 399         struct mlx5_core_dev *dev = eq->dev;
 400         struct mlx5_eqe *eqe;
 401         int set_ci = 0;
 402         u32 cqn = -1;
 403         u32 rsn;
 404         u8 port;
 405
 406         while ((eqe = next_eqe_sw(eq))) {
 407                 /*
 408                  * Make sure we read EQ entry contents after we've
 409                  * checked the ownership bit.
 410                  */
 411                 dma_rmb();
 412
 413                 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
 414                               eq->eqn, eqe_type_str(eqe->type));
 415                 switch (eqe->type) {
 416                 case MLX5_EVENT_TYPE_COMP:
 417                         cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
 418                         mlx5_cq_completion(dev, cqn);
 419                         break;
 420
 421                 case MLX5_EVENT_TYPE_PATH_MIG:
 422                 case MLX5_EVENT_TYPE_COMM_EST:
 423                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 424                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 425                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 426                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 427                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 428                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 429                         rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
 430                         rsn |= (eqe->data.qp_srq.type << MLX5_USER_INDEX_LEN);
 431                         mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
 432                                       eqe_type_str(eqe->type), eqe->type, rsn);
 433                         mlx5_rsc_event(dev, rsn, eqe->type);
 434                         break;
 435
 436                 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
 437                 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
 438                         rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
 439                         mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
 440                                       eqe_type_str(eqe->type), eqe->type, rsn);
 441                         mlx5_srq_event(dev, rsn, eqe->type);
 442                         break;
 443
 444                 case MLX5_EVENT_TYPE_CMD:
 445                         mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
 446                         break;
 447
 448                 case MLX5_EVENT_TYPE_PORT_CHANGE:
 449                         port = (eqe->data.port.port >> 4) & 0xf;
 450                         switch (eqe->sub_type) {
 451                         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 452                         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 453                         case MLX5_PORT_CHANGE_SUBTYPE_LID:
 454                         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
 455                         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
 456                         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
 457                         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
 458                                 if (dev->event)
 459                                         dev->event(dev, port_subtype_event(eqe->sub_type),
 460                                                    (unsigned long)port);
 461                                 break;
 462                         default:
 463                                 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
 464                                                port, eqe->sub_type);
 465                         }
 466                         break;
 467                 case MLX5_EVENT_TYPE_CQ_ERROR:
 468                         cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
 469                         mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
 470                                        cqn, eqe->data.cq_err.syndrome);
 471                         mlx5_cq_event(dev, cqn, eqe->type);
 472                         break;
 473
 474                 case MLX5_EVENT_TYPE_PAGE_REQUEST:
 475                         {
 476                                 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
 477                                 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
 478
 479                                 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
 480                                               func_id, npages);
 481                                 mlx5_core_req_pages_handler(dev, func_id, npages);
 482                         }
 483                         break;
 484
 485                 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
 486                         mlx5_eswitch_vport_event(dev->priv.eswitch, eqe);
 487                         break;
 488
 489                 case MLX5_EVENT_TYPE_PORT_MODULE_EVENT:
 490                         mlx5_port_module_event(dev, eqe);
 491                         break;
 492
 493                 case MLX5_EVENT_TYPE_PPS_EVENT:
 494                         if (dev->event)
 495                                 dev->event(dev, MLX5_DEV_EVENT_PPS, (unsigned long)eqe);
 496                         break;
 497
 498                 case MLX5_EVENT_TYPE_FPGA_ERROR:
 499                         mlx5_fpga_event(dev, eqe->type, &eqe->data.raw);
 500                         break;
 501
 502                 case MLX5_EVENT_TYPE_GENERAL_EVENT:
 503                         general_event_handler(dev, eqe);
 504                         break;
 505                 default:
 506                         mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
 507                                        eqe->type, eq->eqn);
 508                         break;
 509                 }
 510
 511                 ++eq->cons_index;
 512                 ++set_ci;
 513
 514                 /* The HCA will think the queue has overflowed if we
 515                  * don't tell it we've been processing events.  We
 516                  * create our EQs with MLX5_NUM_SPARE_EQE extra
 517                  * entries, so we must update our consumer index at
 518                  * least that often.
 519                  */
 520                 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
 521                         eq_update_ci(eq, 0);
 522                         set_ci = 0;
 523                 }
 524         }
 525
 526         eq_update_ci(eq, 1);
 527
 528         if (cqn != -1)
 529                 tasklet_schedule(&eq->tasklet_ctx.task);
 530
 531         return IRQ_HANDLED;
 532 }
 533
 534 static void init_eq_buf(struct mlx5_eq *eq)
 535 {
 536         struct mlx5_eqe *eqe;
 537         int i;
 538
 539         for (i = 0; i < eq->nent; i++) {
 540                 eqe = get_eqe(eq, i);
 541                 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
 542         }
 543 }
 544
 545 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
 546                        int nent, u64 mask, const char *name,
 547                        enum mlx5_eq_type type)
 548 {
 549         u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
 550         struct mlx5_priv *priv = &dev->priv;
 551         irq_handler_t handler;
 552         __be64 *pas;
 553         void *eqc;
 554         int inlen;
 555         u32 *in;
 556         int err;
 557
 558         eq->type = type;
 559         eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
 560         eq->cons_index = 0;
 561         err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, &eq->buf);
 562         if (err)
 563                 return err;
 564
 565 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 566         if (type == MLX5_EQ_TYPE_PF)
 567                 handler = mlx5_eq_pf_int;
 568         else
 569 #endif
 570                 handler = mlx5_eq_int;
 571
 572         init_eq_buf(eq);
 573
 574         inlen = MLX5_ST_SZ_BYTES(create_eq_in) +
 575                 MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages;
 576
 577         in = kvzalloc(inlen, GFP_KERNEL);
 578         if (!in) {
 579                 err = -ENOMEM;
 580                 goto err_buf;
 581         }
 582
 583         pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas);
 584         mlx5_fill_page_array(&eq->buf, pas);
 585
 586         MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ);
 587         MLX5_SET64(create_eq_in, in, event_bitmask, mask);
 588
 589         eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry);
 590         MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent));
 591         MLX5_SET(eqc, eqc, uar_page, priv->uar->index);
 592         MLX5_SET(eqc, eqc, intr, vecidx);
 593         MLX5_SET(eqc, eqc, log_page_size,
 594                  eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 595
 596         err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
 597         if (err)
 598                 goto err_in;
 599
 600         snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
 601                  name, pci_name(dev->pdev));
 602
 603         eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
 604         eq->irqn = pci_irq_vector(dev->pdev, vecidx);
 605         eq->dev = dev;
 606         eq->doorbell = priv->uar->map + MLX5_EQ_DOORBEL_OFFSET;
 607         err = request_irq(eq->irqn, handler, 0,
 608                           priv->irq_info[vecidx].name, eq);
 609         if (err)
 610                 goto err_eq;
 611
 612         err = mlx5_debug_eq_add(dev, eq);
 613         if (err)
 614                 goto err_irq;
 615
 616 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 617         if (type == MLX5_EQ_TYPE_PF) {
 618                 err = init_pf_ctx(&eq->pf_ctx, name);
 619                 if (err)
 620                         goto err_irq;
 621         } else
 622 #endif
 623         {
 624                 INIT_LIST_HEAD(&eq->tasklet_ctx.list);
 625                 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
 626                 spin_lock_init(&eq->tasklet_ctx.lock);
 627                 tasklet_init(&eq->tasklet_ctx.task, mlx5_cq_tasklet_cb,
 628                              (unsigned long)&eq->tasklet_ctx);
 629         }
 630
 631         /* EQs are created in ARMED state
 632          */
 633         eq_update_ci(eq, 1);
 634
 635         kvfree(in);
 636         return 0;
 637
 638 err_irq:
 639         free_irq(eq->irqn, eq);
 640
 641 err_eq:
 642         mlx5_cmd_destroy_eq(dev, eq->eqn);
 643
 644 err_in:
 645         kvfree(in);
 646
 647 err_buf:
 648         mlx5_buf_free(dev, &eq->buf);
 649         return err;
 650 }
 651 EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
 652
 653 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
 654 {
 655         int err;
 656
 657         mlx5_debug_eq_remove(dev, eq);
 658         free_irq(eq->irqn, eq);
 659         err = mlx5_cmd_destroy_eq(dev, eq->eqn);
 660         if (err)
 661                 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
 662                                eq->eqn);
 663         synchronize_irq(eq->irqn);
 664
 665         if (eq->type == MLX5_EQ_TYPE_COMP) {
 666                 tasklet_disable(&eq->tasklet_ctx.task);
 667 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 668         } else if (eq->type == MLX5_EQ_TYPE_PF) {
 669                 cancel_work_sync(&eq->pf_ctx.work);
 670                 destroy_workqueue(eq->pf_ctx.wq);
 671                 mempool_destroy(eq->pf_ctx.pool);
 672 #endif
 673         }
 674         mlx5_buf_free(dev, &eq->buf);
 675
 676         return err;
 677 }
 678 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
 679
 680 int mlx5_eq_init(struct mlx5_core_dev *dev)
 681 {
 682         int err;
 683
 684         spin_lock_init(&dev->priv.eq_table.lock);
 685
 686         err = mlx5_eq_debugfs_init(dev);
 687
 688         return err;
 689 }
 690
 691 void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
 692 {
 693         mlx5_eq_debugfs_cleanup(dev);
 694 }
 695
 696 int mlx5_start_eqs(struct mlx5_core_dev *dev)
 697 {
 698         struct mlx5_eq_table *table = &dev->priv.eq_table;
 699         u64 async_event_mask = MLX5_ASYNC_EVENT_MASK;
 700         int err;
 701
 702         if (MLX5_VPORT_MANAGER(dev))
 703                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
 704
 705         if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
 706             MLX5_CAP_GEN(dev, general_notification_event))
 707                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_GENERAL_EVENT);
 708
 709         if (MLX5_CAP_GEN(dev, port_module_event))
 710                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PORT_MODULE_EVENT);
 711         else
 712                 mlx5_core_dbg(dev, "port_module_event is not set\n");
 713
 714         if (MLX5_PPS_CAP(dev))
 715                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PPS_EVENT);
 716
 717         if (MLX5_CAP_GEN(dev, fpga))
 718                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR);
 719
 720         err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
 721                                  MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
 722                                  "mlx5_cmd_eq", MLX5_EQ_TYPE_ASYNC);
 723         if (err) {
 724                 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
 725                 return err;
 726         }
 727
 728         mlx5_cmd_use_events(dev);
 729
 730         err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
 731                                  MLX5_NUM_ASYNC_EQE, async_event_mask,
 732                                  "mlx5_async_eq", MLX5_EQ_TYPE_ASYNC);
 733         if (err) {
 734                 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
 735                 goto err1;
 736         }
 737
 738         err = mlx5_create_map_eq(dev, &table->pages_eq,
 739                                  MLX5_EQ_VEC_PAGES,
 740                                  /* TODO: sriov max_vf + */ 1,
 741                                  1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
 742                                  MLX5_EQ_TYPE_ASYNC);
 743         if (err) {
 744                 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
 745                 goto err2;
 746         }
 747
 748 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 749         if (MLX5_CAP_GEN(dev, pg)) {
 750                 err = mlx5_create_map_eq(dev, &table->pfault_eq,
 751                                          MLX5_EQ_VEC_PFAULT,
 752                                          MLX5_NUM_ASYNC_EQE,
 753                                          1 << MLX5_EVENT_TYPE_PAGE_FAULT,
 754                                          "mlx5_page_fault_eq",
 755                                          MLX5_EQ_TYPE_PF);
 756                 if (err) {
 757                         mlx5_core_warn(dev, "failed to create page fault EQ %d\n",
 758                                        err);
 759                         goto err3;
 760                 }
 761         }
 762
 763         return err;
 764 err3:
 765         mlx5_destroy_unmap_eq(dev, &table->pages_eq);
 766 #else
 767         return err;
 768 #endif
 769
 770 err2:
 771         mlx5_destroy_unmap_eq(dev, &table->async_eq);
 772
 773 err1:
 774         mlx5_cmd_use_polling(dev);
 775         mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
 776         return err;
 777 }
 778
 779 void mlx5_stop_eqs(struct mlx5_core_dev *dev)
 780 {
 781         struct mlx5_eq_table *table = &dev->priv.eq_table;
 782         int err;
 783
 784 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 785         if (MLX5_CAP_GEN(dev, pg)) {
 786                 err = mlx5_destroy_unmap_eq(dev, &table->pfault_eq);
 787                 if (err)
 788                         mlx5_core_err(dev, "failed to destroy page fault eq, err(%d)\n",
 789                                       err);
 790         }
 791 #endif
 792
 793         err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
 794         if (err)
 795                 mlx5_core_err(dev, "failed to destroy pages eq, err(%d)\n",
 796                               err);
 797
 798         err = mlx5_destroy_unmap_eq(dev, &table->async_eq);
 799         if (err)
 800                 mlx5_core_err(dev, "failed to destroy async eq, err(%d)\n",
 801                               err);
 802         mlx5_cmd_use_polling(dev);
 803
 804         err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
 805         if (err)
 806                 mlx5_core_err(dev, "failed to destroy command eq, err(%d)\n",
 807                               err);
 808 }
 809
 810 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
 811                        u32 *out, int outlen)
 812 {
 813         u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0};
 814
 815         MLX5_SET(query_eq_in, in, opcode, MLX5_CMD_OP_QUERY_EQ);
 816         MLX5_SET(query_eq_in, in, eq_number, eq->eqn);
 817         return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
 818 }
 819 EXPORT_SYMBOL_GPL(mlx5_core_eq_query);