2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
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33 #include <linux/irq.h>
36 static inline bool mlx5e_channel_no_affinity_change(struct mlx5e_channel *c)
38 int current_cpu = smp_processor_id();
39 const struct cpumask *aff;
40 struct irq_data *idata;
42 idata = irq_desc_get_irq_data(c->irq_desc);
43 aff = irq_data_get_affinity_mask(idata);
44 return cpumask_test_cpu(current_cpu, aff);
47 int mlx5e_napi_poll(struct napi_struct *napi, int budget)
49 struct mlx5e_channel *c = container_of(napi, struct mlx5e_channel,
55 for (i = 0; i < c->num_tc; i++)
56 busy |= mlx5e_poll_tx_cq(&c->sq[i].cq, budget);
59 busy |= mlx5e_poll_xdpsq_cq(&c->rq.xdpsq.cq);
61 if (likely(budget)) { /* budget=0 means: don't poll rx rings */
62 work_done = mlx5e_poll_rx_cq(&c->rq.cq, budget);
63 busy |= work_done == budget;
66 busy |= c->rq.post_wqes(&c->rq);
69 if (likely(mlx5e_channel_no_affinity_change(c)))
71 if (budget && work_done == budget)
75 if (unlikely(!napi_complete_done(napi, work_done)))
78 for (i = 0; i < c->num_tc; i++)
79 mlx5e_cq_arm(&c->sq[i].cq);
81 if (MLX5E_TEST_BIT(c->rq.state, MLX5E_RQ_STATE_AM))
84 mlx5e_cq_arm(&c->rq.cq);
85 mlx5e_cq_arm(&c->icosq.cq);
90 void mlx5e_completion_event(struct mlx5_core_cq *mcq)
92 struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq);
95 napi_schedule(cq->napi);
98 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event)
100 struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq);
101 struct mlx5e_channel *c = cq->channel;
102 struct net_device *netdev = c->netdev;
104 netdev_err(netdev, "%s: cqn=0x%.6x event=0x%.2x\n",
105 __func__, mcq->cqn, event);