2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/tcp.h>
34 #include <linux/if_vlan.h>
36 #include "ipoib/ipoib.h"
37 #include "en_accel/ipsec_rxtx.h"
39 #define MLX5E_SQ_NOPS_ROOM MLX5_SEND_WQE_MAX_WQEBBS
40 #define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\
43 static inline void mlx5e_tx_dma_unmap(struct device *pdev,
44 struct mlx5e_sq_dma *dma)
47 case MLX5E_DMA_MAP_SINGLE:
48 dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
50 case MLX5E_DMA_MAP_PAGE:
51 dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
54 WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n");
58 static inline void mlx5e_dma_push(struct mlx5e_txqsq *sq,
61 enum mlx5e_dma_map_type map_type)
63 u32 i = sq->dma_fifo_pc & sq->dma_fifo_mask;
65 sq->db.dma_fifo[i].addr = addr;
66 sq->db.dma_fifo[i].size = size;
67 sq->db.dma_fifo[i].type = map_type;
71 static inline struct mlx5e_sq_dma *mlx5e_dma_get(struct mlx5e_txqsq *sq, u32 i)
73 return &sq->db.dma_fifo[i & sq->dma_fifo_mask];
76 static void mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq *sq, u8 num_dma)
80 for (i = 0; i < num_dma; i++) {
81 struct mlx5e_sq_dma *last_pushed_dma =
82 mlx5e_dma_get(sq, --sq->dma_fifo_pc);
84 mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
88 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
89 void *accel_priv, select_queue_fallback_t fallback)
91 struct mlx5e_priv *priv = netdev_priv(dev);
92 int channel_ix = fallback(dev, skb);
96 if (!netdev_get_num_tc(dev))
99 if (skb_vlan_tag_present(skb))
100 up = skb->vlan_tci >> VLAN_PRIO_SHIFT;
102 /* channel_ix can be larger than num_channels since
103 * dev->num_real_tx_queues = num_channels * num_tc
105 num_channels = priv->channels.params.num_channels;
106 if (channel_ix >= num_channels)
107 channel_ix = reciprocal_scale(channel_ix, num_channels);
109 return priv->channel_tc2txq[channel_ix][up];
112 static inline int mlx5e_skb_l2_header_offset(struct sk_buff *skb)
114 #define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
116 return max(skb_network_offset(skb), MLX5E_MIN_INLINE);
119 static inline int mlx5e_skb_l3_header_offset(struct sk_buff *skb)
121 struct flow_keys keys;
123 if (skb_transport_header_was_set(skb))
124 return skb_transport_offset(skb);
125 else if (skb_flow_dissect_flow_keys(skb, &keys, 0))
126 return keys.control.thoff;
128 return mlx5e_skb_l2_header_offset(skb);
131 static inline u16 mlx5e_calc_min_inline(enum mlx5_inline_modes mode,
137 case MLX5_INLINE_MODE_NONE:
139 case MLX5_INLINE_MODE_TCP_UDP:
140 hlen = eth_get_headlen(skb->data, skb_headlen(skb));
141 if (hlen == ETH_HLEN && !skb_vlan_tag_present(skb))
144 case MLX5_INLINE_MODE_IP:
145 /* When transport header is set to zero, it means no transport
146 * header. When transport header is set to 0xff's, it means
147 * transport header wasn't set.
149 if (skb_transport_offset(skb)) {
150 hlen = mlx5e_skb_l3_header_offset(skb);
154 case MLX5_INLINE_MODE_L2:
156 hlen = mlx5e_skb_l2_header_offset(skb);
158 return min_t(u16, hlen, skb_headlen(skb));
161 static inline void mlx5e_tx_skb_pull_inline(unsigned char **skb_data,
162 unsigned int *skb_len,
169 static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs,
170 unsigned char **skb_data,
171 unsigned int *skb_len)
173 struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start;
174 int cpy1_sz = 2 * ETH_ALEN;
175 int cpy2_sz = ihs - cpy1_sz;
177 memcpy(vhdr, *skb_data, cpy1_sz);
178 mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy1_sz);
179 vhdr->h_vlan_proto = skb->vlan_proto;
180 vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
181 memcpy(&vhdr->h_vlan_encapsulated_proto, *skb_data, cpy2_sz);
182 mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy2_sz);
186 mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg)
188 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
189 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
190 if (skb->encapsulation) {
191 eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM |
192 MLX5_ETH_WQE_L4_INNER_CSUM;
193 sq->stats.csum_partial_inner++;
195 eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM;
196 sq->stats.csum_partial++;
199 sq->stats.csum_none++;
203 mlx5e_txwqe_build_eseg_gso(struct mlx5e_txqsq *sq, struct sk_buff *skb,
204 struct mlx5_wqe_eth_seg *eseg, unsigned int *num_bytes)
208 eseg->mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
210 if (skb->encapsulation) {
211 ihs = skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
212 sq->stats.tso_inner_packets++;
213 sq->stats.tso_inner_bytes += skb->len - ihs;
215 ihs = skb_transport_offset(skb) + tcp_hdrlen(skb);
216 sq->stats.tso_packets++;
217 sq->stats.tso_bytes += skb->len - ihs;
220 *num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs;
225 mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq *sq, struct sk_buff *skb,
226 unsigned char *skb_data, u16 headlen,
227 struct mlx5_wqe_data_seg *dseg)
229 dma_addr_t dma_addr = 0;
234 dma_addr = dma_map_single(sq->pdev, skb_data, headlen,
236 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
237 goto dma_unmap_wqe_err;
239 dseg->addr = cpu_to_be64(dma_addr);
240 dseg->lkey = sq->mkey_be;
241 dseg->byte_count = cpu_to_be32(headlen);
243 mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE);
248 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
249 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
250 int fsz = skb_frag_size(frag);
252 dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
254 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
255 goto dma_unmap_wqe_err;
257 dseg->addr = cpu_to_be64(dma_addr);
258 dseg->lkey = sq->mkey_be;
259 dseg->byte_count = cpu_to_be32(fsz);
261 mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
269 mlx5e_dma_unmap_wqe_err(sq, num_dma);
274 mlx5e_txwqe_complete(struct mlx5e_txqsq *sq, struct sk_buff *skb,
275 u8 opcode, u16 ds_cnt, u32 num_bytes, u8 num_dma,
276 struct mlx5e_tx_wqe_info *wi, struct mlx5_wqe_ctrl_seg *cseg)
278 struct mlx5_wq_cyc *wq = &sq->wq;
281 wi->num_bytes = num_bytes;
282 wi->num_dma = num_dma;
283 wi->num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
286 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
287 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
289 netdev_tx_sent_queue(sq->txq, num_bytes);
291 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
292 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
294 sq->pc += wi->num_wqebbs;
295 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, MLX5E_SQ_STOP_ROOM))) {
296 netif_tx_stop_queue(sq->txq);
300 if (!skb->xmit_more || netif_xmit_stopped(sq->txq))
301 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, cseg);
303 /* fill sq edge with nops to avoid wqe wrap around */
304 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
305 sq->db.wqe_info[pi].skb = NULL;
306 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
311 static netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
312 struct mlx5e_tx_wqe *wqe, u16 pi)
314 struct mlx5e_tx_wqe_info *wi = &sq->db.wqe_info[pi];
316 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
317 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
319 unsigned char *skb_data = skb->data;
320 unsigned int skb_len = skb->len;
321 u8 opcode = MLX5_OPCODE_SEND;
322 unsigned int num_bytes;
328 mlx5e_txwqe_build_eseg_csum(sq, skb, eseg);
330 if (skb_is_gso(skb)) {
331 opcode = MLX5_OPCODE_LSO;
332 ihs = mlx5e_txwqe_build_eseg_gso(sq, skb, eseg, &num_bytes);
333 sq->stats.packets += skb_shinfo(skb)->gso_segs;
335 ihs = mlx5e_calc_min_inline(sq->min_inline_mode, skb);
336 num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
339 sq->stats.bytes += num_bytes;
340 sq->stats.xmit_more += skb->xmit_more;
342 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
344 if (skb_vlan_tag_present(skb)) {
345 mlx5e_insert_vlan(eseg->inline_hdr.start, skb, ihs, &skb_data, &skb_len);
348 memcpy(eseg->inline_hdr.start, skb_data, ihs);
349 mlx5e_tx_skb_pull_inline(&skb_data, &skb_len, ihs);
351 eseg->inline_hdr.sz = cpu_to_be16(ihs);
352 ds_cnt += DIV_ROUND_UP(ihs - sizeof(eseg->inline_hdr.start), MLX5_SEND_WQE_DS);
353 } else if (skb_vlan_tag_present(skb)) {
354 eseg->insert.type = cpu_to_be16(MLX5_ETH_WQE_INSERT_VLAN);
355 eseg->insert.vlan_tci = cpu_to_be16(skb_vlan_tag_get(skb));
358 headlen = skb_len - skb->data_len;
359 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb_data, headlen,
360 (struct mlx5_wqe_data_seg *)cseg + ds_cnt);
361 if (unlikely(num_dma < 0))
364 mlx5e_txwqe_complete(sq, skb, opcode, ds_cnt + num_dma,
365 num_bytes, num_dma, wi, cseg);
371 dev_kfree_skb_any(skb);
376 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
378 struct mlx5e_priv *priv = netdev_priv(dev);
379 struct mlx5e_txqsq *sq = priv->txq2sq[skb_get_queue_mapping(skb)];
380 struct mlx5_wq_cyc *wq = &sq->wq;
381 u16 pi = sq->pc & wq->sz_m1;
382 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
384 memset(wqe, 0, sizeof(*wqe));
386 #ifdef CONFIG_MLX5_EN_IPSEC
387 if (sq->state & BIT(MLX5E_SQ_STATE_IPSEC)) {
388 skb = mlx5e_ipsec_handle_tx_skb(dev, wqe, skb);
394 return mlx5e_sq_xmit(sq, skb, wqe, pi);
397 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
399 struct mlx5e_txqsq *sq;
400 struct mlx5_cqe64 *cqe;
407 sq = container_of(cq, struct mlx5e_txqsq, cq);
409 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
412 cqe = mlx5_cqwq_get_cqe(&cq->wq);
419 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
420 * otherwise a cq overrun may occur
424 /* avoid dirtying sq cache line every cqe */
425 dma_fifo_cc = sq->dma_fifo_cc;
432 mlx5_cqwq_pop(&cq->wq);
434 wqe_counter = be16_to_cpu(cqe->wqe_counter);
437 struct mlx5e_tx_wqe_info *wi;
442 last_wqe = (sqcc == wqe_counter);
444 ci = sqcc & sq->wq.sz_m1;
445 wi = &sq->db.wqe_info[ci];
448 if (unlikely(!skb)) { /* nop */
453 if (unlikely(skb_shinfo(skb)->tx_flags &
455 struct skb_shared_hwtstamps hwts = {};
457 mlx5e_fill_hwstamp(sq->tstamp,
458 get_cqe_ts(cqe), &hwts);
459 skb_tstamp_tx(skb, &hwts);
462 for (j = 0; j < wi->num_dma; j++) {
463 struct mlx5e_sq_dma *dma =
464 mlx5e_dma_get(sq, dma_fifo_cc++);
466 mlx5e_tx_dma_unmap(sq->pdev, dma);
470 nbytes += wi->num_bytes;
471 sqcc += wi->num_wqebbs;
472 napi_consume_skb(skb, napi_budget);
475 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
477 mlx5_cqwq_update_db_record(&cq->wq);
479 /* ensure cq space is freed before enabling more cqes */
482 sq->dma_fifo_cc = dma_fifo_cc;
485 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
487 if (netif_tx_queue_stopped(sq->txq) &&
488 mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, MLX5E_SQ_STOP_ROOM)) {
489 netif_tx_wake_queue(sq->txq);
493 return (i == MLX5E_TX_CQ_POLL_BUDGET);
496 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq)
498 struct mlx5e_tx_wqe_info *wi;
504 while (sq->cc != sq->pc) {
505 ci = sq->cc & sq->wq.sz_m1;
506 wi = &sq->db.wqe_info[ci];
509 if (!skb) { /* nop */
514 for (i = 0; i < wi->num_dma; i++) {
515 struct mlx5e_sq_dma *dma =
516 mlx5e_dma_get(sq, sq->dma_fifo_cc++);
518 mlx5e_tx_dma_unmap(sq->pdev, dma);
521 dev_kfree_skb_any(skb);
523 nbytes += wi->num_bytes;
524 sq->cc += wi->num_wqebbs;
526 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
529 #ifdef CONFIG_MLX5_CORE_IPOIB
531 struct mlx5_wqe_eth_pad {
535 struct mlx5i_tx_wqe {
536 struct mlx5_wqe_ctrl_seg ctrl;
537 struct mlx5_wqe_datagram_seg datagram;
538 struct mlx5_wqe_eth_pad pad;
539 struct mlx5_wqe_eth_seg eth;
543 mlx5i_txwqe_build_datagram(struct mlx5_av *av, u32 dqpn, u32 dqkey,
544 struct mlx5_wqe_datagram_seg *dseg)
546 memcpy(&dseg->av, av, sizeof(struct mlx5_av));
547 dseg->av.dqp_dct = cpu_to_be32(dqpn | MLX5_EXTENDED_UD_AV);
548 dseg->av.key.qkey.qkey = cpu_to_be32(dqkey);
551 netdev_tx_t mlx5i_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
552 struct mlx5_av *av, u32 dqpn, u32 dqkey)
554 struct mlx5_wq_cyc *wq = &sq->wq;
555 u16 pi = sq->pc & wq->sz_m1;
556 struct mlx5i_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
557 struct mlx5e_tx_wqe_info *wi = &sq->db.wqe_info[pi];
559 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
560 struct mlx5_wqe_datagram_seg *datagram = &wqe->datagram;
561 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
563 unsigned char *skb_data = skb->data;
564 unsigned int skb_len = skb->len;
565 u8 opcode = MLX5_OPCODE_SEND;
566 unsigned int num_bytes;
572 memset(wqe, 0, sizeof(*wqe));
574 mlx5i_txwqe_build_datagram(av, dqpn, dqkey, datagram);
576 mlx5e_txwqe_build_eseg_csum(sq, skb, eseg);
578 if (skb_is_gso(skb)) {
579 opcode = MLX5_OPCODE_LSO;
580 ihs = mlx5e_txwqe_build_eseg_gso(sq, skb, eseg, &num_bytes);
581 sq->stats.packets += skb_shinfo(skb)->gso_segs;
583 ihs = mlx5e_calc_min_inline(sq->min_inline_mode, skb);
584 num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
588 sq->stats.bytes += num_bytes;
589 sq->stats.xmit_more += skb->xmit_more;
591 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
593 memcpy(eseg->inline_hdr.start, skb_data, ihs);
594 mlx5e_tx_skb_pull_inline(&skb_data, &skb_len, ihs);
595 eseg->inline_hdr.sz = cpu_to_be16(ihs);
596 ds_cnt += DIV_ROUND_UP(ihs - sizeof(eseg->inline_hdr.start), MLX5_SEND_WQE_DS);
599 headlen = skb_len - skb->data_len;
600 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb_data, headlen,
601 (struct mlx5_wqe_data_seg *)cseg + ds_cnt);
602 if (unlikely(num_dma < 0))
605 mlx5e_txwqe_complete(sq, skb, opcode, ds_cnt + num_dma,
606 num_bytes, num_dma, wi, cseg);
612 dev_kfree_skb_any(skb);