2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include "en_accel/ipsec.h"
35 #include "en_accel/tls.h"
37 static const struct counter_desc sw_stats_desc[] = {
38 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) },
39 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) },
40 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) },
41 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) },
42 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) },
43 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) },
44 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) },
45 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) },
46 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_added_vlan_packets) },
47 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_nop) },
49 #ifdef CONFIG_MLX5_EN_TLS
50 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_ooo) },
51 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_resync_bytes) },
54 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) },
55 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) },
56 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_ecn_mark) },
57 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_removed_vlan_packets) },
58 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) },
59 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) },
60 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) },
61 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete_tail) },
62 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete_tail_slow) },
63 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) },
64 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) },
65 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_redirect) },
66 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_xmit) },
67 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) },
68 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_err) },
69 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_cqe) },
70 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_none) },
71 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) },
72 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) },
73 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) },
74 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) },
75 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) },
76 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_recover) },
77 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqes) },
78 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) },
79 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqe_err) },
80 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_xmit) },
81 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_full) },
82 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_err) },
83 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_cqes) },
84 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) },
85 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_cqes) },
86 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_strides) },
87 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_oversize_pkts_sw_drop) },
88 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) },
89 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) },
90 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) },
91 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_page_reuse) },
92 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_reuse) },
93 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_full) },
94 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_empty) },
95 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_busy) },
96 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_waive) },
97 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_congst_umr) },
98 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_events) },
99 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_poll) },
100 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_arm) },
101 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_aff_change) },
102 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_eq_rearm) },
105 #define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc)
107 static int mlx5e_grp_sw_get_num_stats(struct mlx5e_priv *priv)
109 return NUM_SW_COUNTERS;
112 static int mlx5e_grp_sw_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx)
116 for (i = 0; i < NUM_SW_COUNTERS; i++)
117 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
121 static int mlx5e_grp_sw_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
125 for (i = 0; i < NUM_SW_COUNTERS; i++)
126 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw, sw_stats_desc, i);
130 void mlx5e_grp_sw_update_stats(struct mlx5e_priv *priv)
132 struct mlx5e_sw_stats temp, *s = &temp;
135 memset(s, 0, sizeof(*s));
137 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++) {
138 struct mlx5e_channel_stats *channel_stats =
139 &priv->channel_stats[i];
140 struct mlx5e_xdpsq_stats *xdpsq_red_stats = &channel_stats->xdpsq;
141 struct mlx5e_xdpsq_stats *xdpsq_stats = &channel_stats->rq_xdpsq;
142 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
143 struct mlx5e_ch_stats *ch_stats = &channel_stats->ch;
146 s->rx_packets += rq_stats->packets;
147 s->rx_bytes += rq_stats->bytes;
148 s->rx_lro_packets += rq_stats->lro_packets;
149 s->rx_lro_bytes += rq_stats->lro_bytes;
150 s->rx_ecn_mark += rq_stats->ecn_mark;
151 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets;
152 s->rx_csum_none += rq_stats->csum_none;
153 s->rx_csum_complete += rq_stats->csum_complete;
154 s->rx_csum_complete_tail += rq_stats->csum_complete_tail;
155 s->rx_csum_complete_tail_slow += rq_stats->csum_complete_tail_slow;
156 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
157 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
158 s->rx_xdp_drop += rq_stats->xdp_drop;
159 s->rx_xdp_redirect += rq_stats->xdp_redirect;
160 s->rx_xdp_tx_xmit += xdpsq_stats->xmit;
161 s->rx_xdp_tx_full += xdpsq_stats->full;
162 s->rx_xdp_tx_err += xdpsq_stats->err;
163 s->rx_xdp_tx_cqe += xdpsq_stats->cqes;
164 s->rx_wqe_err += rq_stats->wqe_err;
165 s->rx_mpwqe_filler_cqes += rq_stats->mpwqe_filler_cqes;
166 s->rx_mpwqe_filler_strides += rq_stats->mpwqe_filler_strides;
167 s->rx_oversize_pkts_sw_drop += rq_stats->oversize_pkts_sw_drop;
168 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
169 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
170 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
171 s->rx_page_reuse += rq_stats->page_reuse;
172 s->rx_cache_reuse += rq_stats->cache_reuse;
173 s->rx_cache_full += rq_stats->cache_full;
174 s->rx_cache_empty += rq_stats->cache_empty;
175 s->rx_cache_busy += rq_stats->cache_busy;
176 s->rx_cache_waive += rq_stats->cache_waive;
177 s->rx_congst_umr += rq_stats->congst_umr;
178 s->ch_events += ch_stats->events;
179 s->ch_poll += ch_stats->poll;
180 s->ch_arm += ch_stats->arm;
181 s->ch_aff_change += ch_stats->aff_change;
182 s->ch_eq_rearm += ch_stats->eq_rearm;
184 s->tx_xdp_xmit += xdpsq_red_stats->xmit;
185 s->tx_xdp_full += xdpsq_red_stats->full;
186 s->tx_xdp_err += xdpsq_red_stats->err;
187 s->tx_xdp_cqes += xdpsq_red_stats->cqes;
189 for (j = 0; j < priv->max_opened_tc; j++) {
190 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
192 s->tx_packets += sq_stats->packets;
193 s->tx_bytes += sq_stats->bytes;
194 s->tx_tso_packets += sq_stats->tso_packets;
195 s->tx_tso_bytes += sq_stats->tso_bytes;
196 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
197 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
198 s->tx_added_vlan_packets += sq_stats->added_vlan_packets;
199 s->tx_nop += sq_stats->nop;
200 s->tx_queue_stopped += sq_stats->stopped;
201 s->tx_queue_wake += sq_stats->wake;
202 s->tx_queue_dropped += sq_stats->dropped;
203 s->tx_cqe_err += sq_stats->cqe_err;
204 s->tx_recover += sq_stats->recover;
205 s->tx_xmit_more += sq_stats->xmit_more;
206 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
207 s->tx_csum_none += sq_stats->csum_none;
208 s->tx_csum_partial += sq_stats->csum_partial;
209 #ifdef CONFIG_MLX5_EN_TLS
210 s->tx_tls_ooo += sq_stats->tls_ooo;
211 s->tx_tls_resync_bytes += sq_stats->tls_resync_bytes;
213 s->tx_cqes += sq_stats->cqes;
215 /* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92657 */
220 memcpy(&priv->stats.sw, s, sizeof(*s));
223 static const struct counter_desc q_stats_desc[] = {
224 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) },
227 static const struct counter_desc drop_rq_stats_desc[] = {
228 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_if_down_packets) },
231 #define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc)
232 #define NUM_DROP_RQ_COUNTERS ARRAY_SIZE(drop_rq_stats_desc)
234 static int mlx5e_grp_q_get_num_stats(struct mlx5e_priv *priv)
239 num_stats += NUM_Q_COUNTERS;
241 if (priv->drop_rq_q_counter)
242 num_stats += NUM_DROP_RQ_COUNTERS;
247 static int mlx5e_grp_q_fill_strings(struct mlx5e_priv *priv, u8 *data, int idx)
251 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
252 strcpy(data + (idx++) * ETH_GSTRING_LEN,
253 q_stats_desc[i].format);
255 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
256 strcpy(data + (idx++) * ETH_GSTRING_LEN,
257 drop_rq_stats_desc[i].format);
262 static int mlx5e_grp_q_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
266 for (i = 0; i < NUM_Q_COUNTERS && priv->q_counter; i++)
267 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
269 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
270 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
271 drop_rq_stats_desc, i);
275 static void mlx5e_grp_q_update_stats(struct mlx5e_priv *priv)
277 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
278 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
280 if (priv->q_counter &&
281 !mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out,
283 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out,
285 if (priv->drop_rq_q_counter &&
286 !mlx5_core_query_q_counter(priv->mdev, priv->drop_rq_q_counter, 0,
288 qcnt->rx_if_down_packets = MLX5_GET(query_q_counter_out, out,
292 #define VNIC_ENV_OFF(c) MLX5_BYTE_OFF(query_vnic_env_out, c)
293 static const struct counter_desc vnic_env_stats_desc[] = {
294 { "rx_steer_missed_packets",
295 VNIC_ENV_OFF(vport_env.nic_receive_steering_discard) },
298 #define NUM_VNIC_ENV_COUNTERS ARRAY_SIZE(vnic_env_stats_desc)
300 static int mlx5e_grp_vnic_env_get_num_stats(struct mlx5e_priv *priv)
302 return MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard) ?
303 NUM_VNIC_ENV_COUNTERS : 0;
306 static int mlx5e_grp_vnic_env_fill_strings(struct mlx5e_priv *priv, u8 *data,
311 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
314 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++)
315 strcpy(data + (idx++) * ETH_GSTRING_LEN,
316 vnic_env_stats_desc[i].format);
320 static int mlx5e_grp_vnic_env_fill_stats(struct mlx5e_priv *priv, u64 *data,
325 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
328 for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++)
329 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out,
330 vnic_env_stats_desc, i);
334 static void mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
336 u32 *out = (u32 *)priv->stats.vnic.query_vnic_env_out;
337 int outlen = MLX5_ST_SZ_BYTES(query_vnic_env_out);
338 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {0};
339 struct mlx5_core_dev *mdev = priv->mdev;
341 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
344 MLX5_SET(query_vnic_env_in, in, opcode,
345 MLX5_CMD_OP_QUERY_VNIC_ENV);
346 MLX5_SET(query_vnic_env_in, in, op_mod, 0);
347 MLX5_SET(query_vnic_env_in, in, other_vport, 0);
348 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
351 #define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c)
352 static const struct counter_desc vport_stats_desc[] = {
353 { "rx_vport_unicast_packets",
354 VPORT_COUNTER_OFF(received_eth_unicast.packets) },
355 { "rx_vport_unicast_bytes",
356 VPORT_COUNTER_OFF(received_eth_unicast.octets) },
357 { "tx_vport_unicast_packets",
358 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) },
359 { "tx_vport_unicast_bytes",
360 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) },
361 { "rx_vport_multicast_packets",
362 VPORT_COUNTER_OFF(received_eth_multicast.packets) },
363 { "rx_vport_multicast_bytes",
364 VPORT_COUNTER_OFF(received_eth_multicast.octets) },
365 { "tx_vport_multicast_packets",
366 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) },
367 { "tx_vport_multicast_bytes",
368 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) },
369 { "rx_vport_broadcast_packets",
370 VPORT_COUNTER_OFF(received_eth_broadcast.packets) },
371 { "rx_vport_broadcast_bytes",
372 VPORT_COUNTER_OFF(received_eth_broadcast.octets) },
373 { "tx_vport_broadcast_packets",
374 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) },
375 { "tx_vport_broadcast_bytes",
376 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) },
377 { "rx_vport_rdma_unicast_packets",
378 VPORT_COUNTER_OFF(received_ib_unicast.packets) },
379 { "rx_vport_rdma_unicast_bytes",
380 VPORT_COUNTER_OFF(received_ib_unicast.octets) },
381 { "tx_vport_rdma_unicast_packets",
382 VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) },
383 { "tx_vport_rdma_unicast_bytes",
384 VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) },
385 { "rx_vport_rdma_multicast_packets",
386 VPORT_COUNTER_OFF(received_ib_multicast.packets) },
387 { "rx_vport_rdma_multicast_bytes",
388 VPORT_COUNTER_OFF(received_ib_multicast.octets) },
389 { "tx_vport_rdma_multicast_packets",
390 VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) },
391 { "tx_vport_rdma_multicast_bytes",
392 VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) },
395 #define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc)
397 static int mlx5e_grp_vport_get_num_stats(struct mlx5e_priv *priv)
399 return NUM_VPORT_COUNTERS;
402 static int mlx5e_grp_vport_fill_strings(struct mlx5e_priv *priv, u8 *data,
407 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
408 strcpy(data + (idx++) * ETH_GSTRING_LEN, vport_stats_desc[i].format);
412 static int mlx5e_grp_vport_fill_stats(struct mlx5e_priv *priv, u64 *data,
417 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
418 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
419 vport_stats_desc, i);
423 static void mlx5e_grp_vport_update_stats(struct mlx5e_priv *priv)
425 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
426 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
427 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
428 struct mlx5_core_dev *mdev = priv->mdev;
430 MLX5_SET(query_vport_counter_in, in, opcode, MLX5_CMD_OP_QUERY_VPORT_COUNTER);
431 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
432 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
433 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
436 #define PPORT_802_3_OFF(c) \
437 MLX5_BYTE_OFF(ppcnt_reg, \
438 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
439 static const struct counter_desc pport_802_3_stats_desc[] = {
440 { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) },
441 { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) },
442 { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) },
443 { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) },
444 { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) },
445 { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) },
446 { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) },
447 { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) },
448 { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) },
449 { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) },
450 { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) },
451 { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) },
452 { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) },
453 { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) },
454 { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) },
455 { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) },
456 { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) },
457 { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) },
460 #define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc)
462 static int mlx5e_grp_802_3_get_num_stats(struct mlx5e_priv *priv)
464 return NUM_PPORT_802_3_COUNTERS;
467 static int mlx5e_grp_802_3_fill_strings(struct mlx5e_priv *priv, u8 *data,
472 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
473 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_802_3_stats_desc[i].format);
477 static int mlx5e_grp_802_3_fill_stats(struct mlx5e_priv *priv, u64 *data,
482 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
483 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
484 pport_802_3_stats_desc, i);
488 static void mlx5e_grp_802_3_update_stats(struct mlx5e_priv *priv)
490 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
491 struct mlx5_core_dev *mdev = priv->mdev;
492 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
493 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
496 MLX5_SET(ppcnt_reg, in, local_port, 1);
497 out = pstats->IEEE_802_3_counters;
498 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
499 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
502 #define PPORT_2863_OFF(c) \
503 MLX5_BYTE_OFF(ppcnt_reg, \
504 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
505 static const struct counter_desc pport_2863_stats_desc[] = {
506 { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) },
507 { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) },
508 { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) },
511 #define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc)
513 static int mlx5e_grp_2863_get_num_stats(struct mlx5e_priv *priv)
515 return NUM_PPORT_2863_COUNTERS;
518 static int mlx5e_grp_2863_fill_strings(struct mlx5e_priv *priv, u8 *data,
523 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
524 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2863_stats_desc[i].format);
528 static int mlx5e_grp_2863_fill_stats(struct mlx5e_priv *priv, u64 *data,
533 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
534 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
535 pport_2863_stats_desc, i);
539 static void mlx5e_grp_2863_update_stats(struct mlx5e_priv *priv)
541 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
542 struct mlx5_core_dev *mdev = priv->mdev;
543 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
544 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
547 MLX5_SET(ppcnt_reg, in, local_port, 1);
548 out = pstats->RFC_2863_counters;
549 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
550 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
553 #define PPORT_2819_OFF(c) \
554 MLX5_BYTE_OFF(ppcnt_reg, \
555 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
556 static const struct counter_desc pport_2819_stats_desc[] = {
557 { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) },
558 { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) },
559 { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) },
560 { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) },
561 { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) },
562 { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) },
563 { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) },
564 { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) },
565 { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) },
566 { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) },
567 { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) },
568 { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) },
569 { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) },
572 #define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc)
574 static int mlx5e_grp_2819_get_num_stats(struct mlx5e_priv *priv)
576 return NUM_PPORT_2819_COUNTERS;
579 static int mlx5e_grp_2819_fill_strings(struct mlx5e_priv *priv, u8 *data,
584 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
585 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2819_stats_desc[i].format);
589 static int mlx5e_grp_2819_fill_stats(struct mlx5e_priv *priv, u64 *data,
594 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
595 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
596 pport_2819_stats_desc, i);
600 static void mlx5e_grp_2819_update_stats(struct mlx5e_priv *priv)
602 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
603 struct mlx5_core_dev *mdev = priv->mdev;
604 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
605 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
608 MLX5_SET(ppcnt_reg, in, local_port, 1);
609 out = pstats->RFC_2819_counters;
610 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
611 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
614 #define PPORT_PHY_STATISTICAL_OFF(c) \
615 MLX5_BYTE_OFF(ppcnt_reg, \
616 counter_set.phys_layer_statistical_cntrs.c##_high)
617 static const struct counter_desc pport_phy_statistical_stats_desc[] = {
618 { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) },
619 { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) },
622 #define NUM_PPORT_PHY_STATISTICAL_COUNTERS ARRAY_SIZE(pport_phy_statistical_stats_desc)
624 static int mlx5e_grp_phy_get_num_stats(struct mlx5e_priv *priv)
626 /* "1" for link_down_events special counter */
627 return MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group) ?
628 NUM_PPORT_PHY_STATISTICAL_COUNTERS + 1 : 1;
631 static int mlx5e_grp_phy_fill_strings(struct mlx5e_priv *priv, u8 *data,
636 strcpy(data + (idx++) * ETH_GSTRING_LEN, "link_down_events_phy");
638 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
641 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
642 strcpy(data + (idx++) * ETH_GSTRING_LEN,
643 pport_phy_statistical_stats_desc[i].format);
647 static int mlx5e_grp_phy_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
651 /* link_down_events_phy has special handling since it is not stored in __be64 format */
652 data[idx++] = MLX5_GET(ppcnt_reg, priv->stats.pport.phy_counters,
653 counter_set.phys_layer_cntrs.link_down_events);
655 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
658 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
660 MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
661 pport_phy_statistical_stats_desc, i);
665 static void mlx5e_grp_phy_update_stats(struct mlx5e_priv *priv)
667 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
668 struct mlx5_core_dev *mdev = priv->mdev;
669 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
670 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
673 MLX5_SET(ppcnt_reg, in, local_port, 1);
674 out = pstats->phy_counters;
675 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
676 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
678 if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
681 out = pstats->phy_statistical_counters;
682 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
683 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
686 #define PPORT_ETH_EXT_OFF(c) \
687 MLX5_BYTE_OFF(ppcnt_reg, \
688 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
689 static const struct counter_desc pport_eth_ext_stats_desc[] = {
690 { "rx_buffer_passed_thres_phy", PPORT_ETH_EXT_OFF(rx_buffer_almost_full) },
693 #define NUM_PPORT_ETH_EXT_COUNTERS ARRAY_SIZE(pport_eth_ext_stats_desc)
695 static int mlx5e_grp_eth_ext_get_num_stats(struct mlx5e_priv *priv)
697 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
698 return NUM_PPORT_ETH_EXT_COUNTERS;
703 static int mlx5e_grp_eth_ext_fill_strings(struct mlx5e_priv *priv, u8 *data,
708 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
709 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
710 strcpy(data + (idx++) * ETH_GSTRING_LEN,
711 pport_eth_ext_stats_desc[i].format);
715 static int mlx5e_grp_eth_ext_fill_stats(struct mlx5e_priv *priv, u64 *data,
720 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
721 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
723 MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters,
724 pport_eth_ext_stats_desc, i);
728 static void mlx5e_grp_eth_ext_update_stats(struct mlx5e_priv *priv)
730 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
731 struct mlx5_core_dev *mdev = priv->mdev;
732 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
733 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
736 if (!MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters))
739 MLX5_SET(ppcnt_reg, in, local_port, 1);
740 out = pstats->eth_ext_counters;
741 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
742 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
745 #define PCIE_PERF_OFF(c) \
746 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c)
747 static const struct counter_desc pcie_perf_stats_desc[] = {
748 { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) },
749 { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) },
752 #define PCIE_PERF_OFF64(c) \
753 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
754 static const struct counter_desc pcie_perf_stats_desc64[] = {
755 { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) },
758 static const struct counter_desc pcie_perf_stall_stats_desc[] = {
759 { "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) },
760 { "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) },
761 { "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) },
762 { "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) },
765 #define NUM_PCIE_PERF_COUNTERS ARRAY_SIZE(pcie_perf_stats_desc)
766 #define NUM_PCIE_PERF_COUNTERS64 ARRAY_SIZE(pcie_perf_stats_desc64)
767 #define NUM_PCIE_PERF_STALL_COUNTERS ARRAY_SIZE(pcie_perf_stall_stats_desc)
769 static int mlx5e_grp_pcie_get_num_stats(struct mlx5e_priv *priv)
773 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
774 num_stats += NUM_PCIE_PERF_COUNTERS;
776 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
777 num_stats += NUM_PCIE_PERF_COUNTERS64;
779 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
780 num_stats += NUM_PCIE_PERF_STALL_COUNTERS;
785 static int mlx5e_grp_pcie_fill_strings(struct mlx5e_priv *priv, u8 *data,
790 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
791 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
792 strcpy(data + (idx++) * ETH_GSTRING_LEN,
793 pcie_perf_stats_desc[i].format);
795 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
796 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
797 strcpy(data + (idx++) * ETH_GSTRING_LEN,
798 pcie_perf_stats_desc64[i].format);
800 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
801 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
802 strcpy(data + (idx++) * ETH_GSTRING_LEN,
803 pcie_perf_stall_stats_desc[i].format);
807 static int mlx5e_grp_pcie_fill_stats(struct mlx5e_priv *priv, u64 *data,
812 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
813 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
815 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
816 pcie_perf_stats_desc, i);
818 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
819 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
821 MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters,
822 pcie_perf_stats_desc64, i);
824 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
825 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
827 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
828 pcie_perf_stall_stats_desc, i);
832 static void mlx5e_grp_pcie_update_stats(struct mlx5e_priv *priv)
834 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
835 struct mlx5_core_dev *mdev = priv->mdev;
836 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
837 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
840 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
843 out = pcie_stats->pcie_perf_counters;
844 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
845 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
848 #define PPORT_PER_PRIO_OFF(c) \
849 MLX5_BYTE_OFF(ppcnt_reg, \
850 counter_set.eth_per_prio_grp_data_layout.c##_high)
851 static const struct counter_desc pport_per_prio_traffic_stats_desc[] = {
852 { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) },
853 { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) },
854 { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) },
855 { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) },
858 #define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS ARRAY_SIZE(pport_per_prio_traffic_stats_desc)
860 static int mlx5e_grp_per_prio_traffic_get_num_stats(void)
862 return NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * NUM_PPORT_PRIO;
865 static int mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv *priv,
871 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
872 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
873 sprintf(data + (idx++) * ETH_GSTRING_LEN,
874 pport_per_prio_traffic_stats_desc[i].format, prio);
880 static int mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv *priv,
886 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
887 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
889 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
890 pport_per_prio_traffic_stats_desc, i);
896 static const struct counter_desc pport_per_prio_pfc_stats_desc[] = {
897 /* %s is "global" or "prio{i}" */
898 { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) },
899 { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) },
900 { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) },
901 { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) },
902 { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },
905 static const struct counter_desc pport_pfc_stall_stats_desc[] = {
906 { "tx_pause_storm_warning_events ", PPORT_PER_PRIO_OFF(device_stall_minor_watermark_cnt) },
907 { "tx_pause_storm_error_events", PPORT_PER_PRIO_OFF(device_stall_critical_watermark_cnt) },
910 #define NUM_PPORT_PER_PRIO_PFC_COUNTERS ARRAY_SIZE(pport_per_prio_pfc_stats_desc)
911 #define NUM_PPORT_PFC_STALL_COUNTERS(priv) (ARRAY_SIZE(pport_pfc_stall_stats_desc) * \
912 MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) * \
913 MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
915 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
917 struct mlx5_core_dev *mdev = priv->mdev;
922 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
925 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
927 return err ? 0 : pfc_en_tx | pfc_en_rx;
930 static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
932 struct mlx5_core_dev *mdev = priv->mdev;
937 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
940 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
942 return err ? false : rx_pause | tx_pause;
945 static int mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv *priv)
947 return (mlx5e_query_global_pause_combined(priv) +
948 hweight8(mlx5e_query_pfc_combined(priv))) *
949 NUM_PPORT_PER_PRIO_PFC_COUNTERS +
950 NUM_PPORT_PFC_STALL_COUNTERS(priv);
953 static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv,
957 unsigned long pfc_combined;
960 pfc_combined = mlx5e_query_pfc_combined(priv);
961 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
962 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
963 char pfc_string[ETH_GSTRING_LEN];
965 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
966 sprintf(data + (idx++) * ETH_GSTRING_LEN,
967 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
971 if (mlx5e_query_global_pause_combined(priv)) {
972 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
973 sprintf(data + (idx++) * ETH_GSTRING_LEN,
974 pport_per_prio_pfc_stats_desc[i].format, "global");
978 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
979 strcpy(data + (idx++) * ETH_GSTRING_LEN,
980 pport_pfc_stall_stats_desc[i].format);
985 static int mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv,
989 unsigned long pfc_combined;
992 pfc_combined = mlx5e_query_pfc_combined(priv);
993 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
994 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
996 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
997 pport_per_prio_pfc_stats_desc, i);
1001 if (mlx5e_query_global_pause_combined(priv)) {
1002 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
1004 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
1005 pport_per_prio_pfc_stats_desc, i);
1009 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
1010 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
1011 pport_pfc_stall_stats_desc, i);
1016 static int mlx5e_grp_per_prio_get_num_stats(struct mlx5e_priv *priv)
1018 return mlx5e_grp_per_prio_traffic_get_num_stats() +
1019 mlx5e_grp_per_prio_pfc_get_num_stats(priv);
1022 static int mlx5e_grp_per_prio_fill_strings(struct mlx5e_priv *priv, u8 *data,
1025 idx = mlx5e_grp_per_prio_traffic_fill_strings(priv, data, idx);
1026 idx = mlx5e_grp_per_prio_pfc_fill_strings(priv, data, idx);
1030 static int mlx5e_grp_per_prio_fill_stats(struct mlx5e_priv *priv, u64 *data,
1033 idx = mlx5e_grp_per_prio_traffic_fill_stats(priv, data, idx);
1034 idx = mlx5e_grp_per_prio_pfc_fill_stats(priv, data, idx);
1038 static void mlx5e_grp_per_prio_update_stats(struct mlx5e_priv *priv)
1040 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1041 struct mlx5_core_dev *mdev = priv->mdev;
1042 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1043 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1047 MLX5_SET(ppcnt_reg, in, local_port, 1);
1048 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
1049 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1050 out = pstats->per_prio_counters[prio];
1051 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1052 mlx5_core_access_reg(mdev, in, sz, out, sz,
1053 MLX5_REG_PPCNT, 0, 0);
1057 static const struct counter_desc mlx5e_pme_status_desc[] = {
1058 { "module_unplug", 8 },
1061 static const struct counter_desc mlx5e_pme_error_desc[] = {
1062 { "module_bus_stuck", 16 }, /* bus stuck (I2C or data shorted) */
1063 { "module_high_temp", 48 }, /* high temperature */
1064 { "module_bad_shorted", 56 }, /* bad or shorted cable/module */
1067 #define NUM_PME_STATUS_STATS ARRAY_SIZE(mlx5e_pme_status_desc)
1068 #define NUM_PME_ERR_STATS ARRAY_SIZE(mlx5e_pme_error_desc)
1070 static int mlx5e_grp_pme_get_num_stats(struct mlx5e_priv *priv)
1072 return NUM_PME_STATUS_STATS + NUM_PME_ERR_STATS;
1075 static int mlx5e_grp_pme_fill_strings(struct mlx5e_priv *priv, u8 *data,
1080 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1081 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
1083 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1084 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
1089 static int mlx5e_grp_pme_fill_stats(struct mlx5e_priv *priv, u64 *data,
1092 struct mlx5_priv *mlx5_priv = &priv->mdev->priv;
1095 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1096 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
1097 mlx5e_pme_status_desc, i);
1099 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1100 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
1101 mlx5e_pme_error_desc, i);
1106 static int mlx5e_grp_ipsec_get_num_stats(struct mlx5e_priv *priv)
1108 return mlx5e_ipsec_get_count(priv);
1111 static int mlx5e_grp_ipsec_fill_strings(struct mlx5e_priv *priv, u8 *data,
1114 return idx + mlx5e_ipsec_get_strings(priv,
1115 data + idx * ETH_GSTRING_LEN);
1118 static int mlx5e_grp_ipsec_fill_stats(struct mlx5e_priv *priv, u64 *data,
1121 return idx + mlx5e_ipsec_get_stats(priv, data + idx);
1124 static void mlx5e_grp_ipsec_update_stats(struct mlx5e_priv *priv)
1126 mlx5e_ipsec_update_stats(priv);
1129 static int mlx5e_grp_tls_get_num_stats(struct mlx5e_priv *priv)
1131 return mlx5e_tls_get_count(priv);
1134 static int mlx5e_grp_tls_fill_strings(struct mlx5e_priv *priv, u8 *data,
1137 return idx + mlx5e_tls_get_strings(priv, data + idx * ETH_GSTRING_LEN);
1140 static int mlx5e_grp_tls_fill_stats(struct mlx5e_priv *priv, u64 *data, int idx)
1142 return idx + mlx5e_tls_get_stats(priv, data + idx);
1145 static const struct counter_desc rq_stats_desc[] = {
1146 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) },
1147 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) },
1148 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) },
1149 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete_tail) },
1150 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete_tail_slow) },
1151 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
1152 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
1153 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) },
1154 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) },
1155 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_redirect) },
1156 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) },
1157 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) },
1158 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, ecn_mark) },
1159 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, removed_vlan_packets) },
1160 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) },
1161 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_cqes) },
1162 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_strides) },
1163 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, oversize_pkts_sw_drop) },
1164 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
1165 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
1166 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
1167 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, page_reuse) },
1168 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_reuse) },
1169 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_full) },
1170 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_empty) },
1171 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_busy) },
1172 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_waive) },
1173 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, congst_umr) },
1176 static const struct counter_desc sq_stats_desc[] = {
1177 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) },
1178 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) },
1179 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) },
1180 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
1181 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
1182 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
1183 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial) },
1184 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
1185 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) },
1186 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) },
1187 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) },
1188 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) },
1189 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) },
1190 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
1191 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, recover) },
1192 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqes) },
1193 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) },
1194 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqe_err) },
1197 static const struct counter_desc rq_xdpsq_stats_desc[] = {
1198 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, xmit) },
1199 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, full) },
1200 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, err) },
1201 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, cqes) },
1204 static const struct counter_desc xdpsq_stats_desc[] = {
1205 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, xmit) },
1206 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, full) },
1207 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, err) },
1208 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, cqes) },
1211 static const struct counter_desc ch_stats_desc[] = {
1212 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, events) },
1213 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, poll) },
1214 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, arm) },
1215 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, aff_change) },
1216 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, eq_rearm) },
1219 #define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
1220 #define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
1221 #define NUM_XDPSQ_STATS ARRAY_SIZE(xdpsq_stats_desc)
1222 #define NUM_RQ_XDPSQ_STATS ARRAY_SIZE(rq_xdpsq_stats_desc)
1223 #define NUM_CH_STATS ARRAY_SIZE(ch_stats_desc)
1225 static int mlx5e_grp_channels_get_num_stats(struct mlx5e_priv *priv)
1227 int max_nch = priv->profile->max_nch(priv->mdev);
1229 return (NUM_RQ_STATS * max_nch) +
1230 (NUM_CH_STATS * max_nch) +
1231 (NUM_SQ_STATS * max_nch * priv->max_opened_tc) +
1232 (NUM_RQ_XDPSQ_STATS * max_nch) +
1233 (NUM_XDPSQ_STATS * max_nch);
1236 static int mlx5e_grp_channels_fill_strings(struct mlx5e_priv *priv, u8 *data,
1239 int max_nch = priv->profile->max_nch(priv->mdev);
1242 for (i = 0; i < max_nch; i++)
1243 for (j = 0; j < NUM_CH_STATS; j++)
1244 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1245 ch_stats_desc[j].format, i);
1247 for (i = 0; i < max_nch; i++) {
1248 for (j = 0; j < NUM_RQ_STATS; j++)
1249 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1250 rq_stats_desc[j].format, i);
1251 for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++)
1252 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1253 rq_xdpsq_stats_desc[j].format, i);
1256 for (tc = 0; tc < priv->max_opened_tc; tc++)
1257 for (i = 0; i < max_nch; i++)
1258 for (j = 0; j < NUM_SQ_STATS; j++)
1259 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1260 sq_stats_desc[j].format,
1261 priv->channel_tc2txq[i][tc]);
1263 for (i = 0; i < max_nch; i++)
1264 for (j = 0; j < NUM_XDPSQ_STATS; j++)
1265 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1266 xdpsq_stats_desc[j].format, i);
1271 static int mlx5e_grp_channels_fill_stats(struct mlx5e_priv *priv, u64 *data,
1274 int max_nch = priv->profile->max_nch(priv->mdev);
1277 for (i = 0; i < max_nch; i++)
1278 for (j = 0; j < NUM_CH_STATS; j++)
1280 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].ch,
1283 for (i = 0; i < max_nch; i++) {
1284 for (j = 0; j < NUM_RQ_STATS; j++)
1286 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].rq,
1288 for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++)
1290 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].rq_xdpsq,
1291 rq_xdpsq_stats_desc, j);
1294 for (tc = 0; tc < priv->max_opened_tc; tc++)
1295 for (i = 0; i < max_nch; i++)
1296 for (j = 0; j < NUM_SQ_STATS; j++)
1298 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].sq[tc],
1301 for (i = 0; i < max_nch; i++)
1302 for (j = 0; j < NUM_XDPSQ_STATS; j++)
1304 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i].xdpsq,
1305 xdpsq_stats_desc, j);
1310 /* The stats groups order is opposite to the update_stats() order calls */
1311 const struct mlx5e_stats_grp mlx5e_stats_grps[] = {
1313 .get_num_stats = mlx5e_grp_sw_get_num_stats,
1314 .fill_strings = mlx5e_grp_sw_fill_strings,
1315 .fill_stats = mlx5e_grp_sw_fill_stats,
1316 .update_stats = mlx5e_grp_sw_update_stats,
1319 .get_num_stats = mlx5e_grp_q_get_num_stats,
1320 .fill_strings = mlx5e_grp_q_fill_strings,
1321 .fill_stats = mlx5e_grp_q_fill_stats,
1322 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1323 .update_stats = mlx5e_grp_q_update_stats,
1326 .get_num_stats = mlx5e_grp_vnic_env_get_num_stats,
1327 .fill_strings = mlx5e_grp_vnic_env_fill_strings,
1328 .fill_stats = mlx5e_grp_vnic_env_fill_stats,
1329 .update_stats = mlx5e_grp_vnic_env_update_stats,
1332 .get_num_stats = mlx5e_grp_vport_get_num_stats,
1333 .fill_strings = mlx5e_grp_vport_fill_strings,
1334 .fill_stats = mlx5e_grp_vport_fill_stats,
1335 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1336 .update_stats = mlx5e_grp_vport_update_stats,
1339 .get_num_stats = mlx5e_grp_802_3_get_num_stats,
1340 .fill_strings = mlx5e_grp_802_3_fill_strings,
1341 .fill_stats = mlx5e_grp_802_3_fill_stats,
1342 .update_stats_mask = MLX5E_NDO_UPDATE_STATS,
1343 .update_stats = mlx5e_grp_802_3_update_stats,
1346 .get_num_stats = mlx5e_grp_2863_get_num_stats,
1347 .fill_strings = mlx5e_grp_2863_fill_strings,
1348 .fill_stats = mlx5e_grp_2863_fill_stats,
1349 .update_stats = mlx5e_grp_2863_update_stats,
1352 .get_num_stats = mlx5e_grp_2819_get_num_stats,
1353 .fill_strings = mlx5e_grp_2819_fill_strings,
1354 .fill_stats = mlx5e_grp_2819_fill_stats,
1355 .update_stats = mlx5e_grp_2819_update_stats,
1358 .get_num_stats = mlx5e_grp_phy_get_num_stats,
1359 .fill_strings = mlx5e_grp_phy_fill_strings,
1360 .fill_stats = mlx5e_grp_phy_fill_stats,
1361 .update_stats = mlx5e_grp_phy_update_stats,
1364 .get_num_stats = mlx5e_grp_eth_ext_get_num_stats,
1365 .fill_strings = mlx5e_grp_eth_ext_fill_strings,
1366 .fill_stats = mlx5e_grp_eth_ext_fill_stats,
1367 .update_stats = mlx5e_grp_eth_ext_update_stats,
1370 .get_num_stats = mlx5e_grp_pcie_get_num_stats,
1371 .fill_strings = mlx5e_grp_pcie_fill_strings,
1372 .fill_stats = mlx5e_grp_pcie_fill_stats,
1373 .update_stats = mlx5e_grp_pcie_update_stats,
1376 .get_num_stats = mlx5e_grp_per_prio_get_num_stats,
1377 .fill_strings = mlx5e_grp_per_prio_fill_strings,
1378 .fill_stats = mlx5e_grp_per_prio_fill_stats,
1379 .update_stats = mlx5e_grp_per_prio_update_stats,
1382 .get_num_stats = mlx5e_grp_pme_get_num_stats,
1383 .fill_strings = mlx5e_grp_pme_fill_strings,
1384 .fill_stats = mlx5e_grp_pme_fill_stats,
1387 .get_num_stats = mlx5e_grp_ipsec_get_num_stats,
1388 .fill_strings = mlx5e_grp_ipsec_fill_strings,
1389 .fill_stats = mlx5e_grp_ipsec_fill_stats,
1390 .update_stats = mlx5e_grp_ipsec_update_stats,
1393 .get_num_stats = mlx5e_grp_tls_get_num_stats,
1394 .fill_strings = mlx5e_grp_tls_fill_strings,
1395 .fill_stats = mlx5e_grp_tls_fill_stats,
1398 .get_num_stats = mlx5e_grp_channels_get_num_stats,
1399 .fill_strings = mlx5e_grp_channels_fill_strings,
1400 .fill_stats = mlx5e_grp_channels_fill_stats,
1404 const int mlx5e_num_stats_grps = ARRAY_SIZE(mlx5e_stats_grps);